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F D M S 7 October 2014 6 9 FDMS7692A 2 A ® N N-Channel PowerTrench MOSFET - C 30 V, 8 mΩ h a Features General Description n n e (cid:132) Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A This N-Channel MOSFET has been designed specifically to l improve the overall efficiency and to minimize switch node P (cid:132) Max rDS(on) = 14 mΩ at VGS = 4.5 V, ID = 10 A ringing of DC/DC converters using either synchronous or o w conventional switching PWM controllers. It has been optimized (cid:132) Advanced Package and Silicon combination for low rDS(on) e and high efficiency for low gate charge, low rDS(on), fast switching speed and body r diode reverse recovery performance. T r (cid:132) Next generation enhanced body diode technology, engineered e for soft recovery. Applications n c h (cid:132) MSL1 robust package design (cid:132) IMVP Vcore Switching for Notebook ® (cid:132) 100% UIL tested (cid:132) VRM Vcore Switching for Desktop and Server M O (cid:132) RoHS Compliant (cid:132) OringFET / Load Switch S F (cid:132) DC-DC Conversion E T Top Bottom Pin 1 S D 5 4 G S S G D 6 3 S D 7 2 S D D D 8 1 S D D Power 56 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol Parameter Ratings Units V Drain to Source Voltage 30 V DS V Gate to Source Voltage ±20 V GS Drain Current -Continuous (Package limited) T = 25 °C 28 C -Continuous (Silicon limited) T = 25 °C 45 I C A D -Continuous T = 25 °C (Note 1a) 13.5 A -Pulsed 50 E Single Pulse Avalanche Energy (Note 3) 21 mJ AS Power Dissipation T = 25 °C 27 P C W D Power Dissipation T = 25 °C (Note 1a) 2.5 A T , T Operating and Storage Junction Temperature Range -55 to +150 °C J STG Thermal Characteristics R Thermal Resistance, Junction to Case 4.6 θJC °C/W R Thermal Resistance, Junction to Ambient (Note 1a) 50 θJA Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity FDMS7692A FDMS7692A Power 56 13 ’’ 12 mm 3000 units ©2009 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDMS7692A Rev.C1

F D Electrical Characteristics T = 25 °C unless otherwise noted M J S Symbol Parameter Test Conditions Min Typ Max Units 7 6 9 Off Characteristics 2 A BV Drain to Source Breakdown Voltage I = 250 µA, V = 0 V 30 V DSS D GS N ∆BV Breakdown Voltage Temperature ∆TDSS Coefficient ID = 250 µA, referenced to 25 °C 13 mV/°C -C J h IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1 µA a n I Gate to Source Leakage Current, Forward V = 20 V, V = 0 V 100 nA GSS GS DS n e On Characteristics l P V Gate to Source Threshold Voltage V = V , I = 250 µA 1.0 2.0 3.0 V o GS(th) GS DS D w ∆VGS(th) Gate to Source Threshold Voltage I = 250 µA, referenced to 25 °C -6 mV/°C e ∆T Temperature Coefficient D r J T V = 10 V, I = 13 A 6.8 8 r GS D e r Static Drain to Source On Resistance V = 4.5 V, I = 10 A 10 14 mΩ n DS(on) GS D c VGS = 10 V, ID = 13 A, TJ = 125 °C 9.5 12 h ® g Forward Transconductance V = 5 V, I = 13 A 68 S FS DS D M Dynamic Characteristics O S Ciss Input Capacitance 1015 1350 pF F C Output Capacitance VDS = 15 V, VGS = 0 V, 325 435 pF E oss f = 1 MHz T C Reverse Transfer Capacitance 45 65 pF rss R Gate Resistance 1.5 3.0 Ω g Switching Characteristics t Turn-On Delay Time 8 16 ns d(on) tr Rise Time VDD = 15 V, ID = 13 A, 2.7 10 ns td(off) Turn-Off Delay Time VGS = 10 V, RGEN = 6 Ω 17 31 ns t Fall Time 2.3 10 ns f Q Total Gate Charge V = 0 V to 10 V 15 22 nC g GS Qg Total Gate Charge VGS = 0 V to 4.5 V VDD = 15 V, 7 10 nC Qgs Gate to Source Charge ID = 13 A 3.4 nC Q Gate to Drain “Miller” Charge 1.9 nC gd Drain-Source Diode Characteristics V = 0 V, I = 2.1 A (Note 2) 0.75 1.1 V Source to Drain Diode Forward Voltage GS S V SD V = 0 V, I = 13 A (Note 2) 0.84 1.2 GS S t Reverse Recovery Time 21 34 ns rr I = 13 A, di/dt = 100 A/µs Q Reverse Recovery Charge F 6 12 nC rr t Reverse Recovery Time 17 31 ns rr I = 13 A, di/dt = 300 A/µs Q Reverse Recovery Charge F 12 21 nC rr Notes: 1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. a. 50 °C/W when mounted on a b. 125 °C/W when mounted on a 1 in2 pad of 2 oz copper. minimum pad of 2 oz copper. 2. Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%. 3. Starting TJ = 25 °C, L = 0.3 mH, IAS = 12 A, VDD = 27 V, VGS = 10 V. ©2009 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FDMS7692A Rev.C1

F D Typical Characteristics M T = 25 °C unless otherwise noted J S 7 6 9 50 10 2 E C A 40 VGS = 10 V TAN 8 VGS = 3.0 V N A) VGS = 4.5 V SIS PULSE DURATION = 80 µs -C URRENT ( 30 VGS = 4.0 V VGS = 3.5 V MALIZEDCE ON-RE 6 VGSD =U 3T.Y5 VCYCLE = 0.5% MAX hann DRAIN C 20 PDUULTSYE C DYUCRLEA T=I O0.N5 %= 8M0A µXs NORO SOUR 4 VGS = 4.0 V el Po , ID 10 VGS = 3.0 V AIN T 2 we 0 DR 0 VGS = 4. 5 V VGS = 10 V rT r 0.0 0.5 1.0 1.5 2.0 0 10 20 30 40 50 e VDS, DRAIN TO SO URCE VOLTAGE (V) ID, DRAIN CURRENT (A) nc h ® Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage M O S F 1.6 30 E NORMALIZED O SOURCE ON-RESISTANCE 111111......012345 IVDG =S 1=3 1 A0 V rDRAIN TO ,DS(on)()CE ON-RESISTANCE mΩ 122505 ID = 13 A PDUUTLTJ SY=E 1C 2DY5UC oRLCEA T=I O0.N5 %= 8M0A µXs T T R10 AIN 0.9 SOU DR 0.8 5 TJ = 25 oC -75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10 TJ, JUNCTION TEM PERATURE (oC) VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On Resistance Figure 4. On-Resistance vs Gate to vs Junction Temperature Source Voltage 50 100 PULSE DURATION = 80 µs A) VGS = 0 V DUTY CYCLE = 0.5% MAX T ( 40 N T (A) VDS = 5 V URRE 10 URREN 30 TJ = 150 oC RAIN C 1 TJ = 150 oC N C 20 E D TJ = 25 oC RAI TJ = 25 oC ERS D V 0.1 I, D 10 TJ = -55 oC I, RES TJ = -55 oC 0 0.01 1 2 3 4 5 0.2 0.4 0.6 0.8 1.0 1.2 VGS, GATE TO SOU RCE VOLTAGE (V) VSD, BODY DIODE FOR WARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current ©2009 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FDMS7692A Rev.C1

F D Typical Characteristics T = 25 °C unless otherwise noted M J S 7 6 10 2000 9 OLTAGE (V) 8 ID = 13 A VDD = 15 V E (pF)1000 Ciss 2A N-C V C h CE 6 AN a UR VDD = 10 V VDD = 20 V CIT Coss nn O A 100 S 4 P e TO CA l P E V, GATGS 02 10 fV =G S1 =M 0H Vz Crss owerT 0 4 8 12 16 0.1 1 10 30 r e Qg, GATE CH ARGE (nC) VDS, DRAIN TO SOU RCE VOLTAGE (V) n c h Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain ® to Source Voltage M O S F 50 50 E T RENT (A) TJ = 25 oC ENT (A) 40 UR 10 RR 30 HE C TJ = 100 oC N CU VGS = 10 V C AI 20 N R ALA TJ = 125 oC , DD Limited by Package VGS = 4.5 V V I 10 A I, AS RθJC = 4.6 oC/W 1 0 0.001 0.01 0.1 1 10 100 25 50 75 100 125 150 tAV, TIME IN AVA LANCHE (ms) TC, CASE TEMPERATURE (oC) Figure 9. Unclamped Inductive Figure 10. Maximum Continuous Drain Switching Capability Current vs Case Temperature 100 300 ER (W) 100 VGS = 10 V SRIθNJAG =L E1 2P5U oLCS/WE T (A) 10 100 us POW TA = 25 oC AIN CURREN 1 TLIHMISIT AERDE BAY I SrD S(on) 11100 m 0m smss TRANSIENT 10 DR SINGLE PULSE 1 s AK I, D 0.1 TRTJAθ J ==A M2=5 A1 oX2C5 R oACT/WED 1D0C s , PPE()PK 1 0.01 0.5 0.01 0.1 1 10 100 200 10-4 10-3 10-2 10-1 1 10 100 1000 VDS, DRAIN to SOU RCE VOLTAGE (V) t, PULSE WIDT H (sec) Figure 11. Forward Bias Safe Figure 12. Single Pulse Maximum Operating Area Power Dissipation ©2009 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FDMS7692A Rev.C1

F D Typical Characteristics T = 25 °C unless otherwise noted M J S 7 6 9 2 2 A 1 DUTY CYCLE-DESCENDING ORDER N - D = 0.5 C AL 0.2 h M A 0.1 a ERZJθ 0.1 0.05 n ALIZED TH PEDANCE, 00..0021 PDM t1 nel Po RMIM 0.01 t2 w O NOTES: e N SINGLE PULSE DUTY FACTOR: D = t1/t2 rT R = 125 oC/W PEAK TJ = PDM x ZθJA x RθJA + TA r θJA e n 0.001 10-4 10-3 10-2 10-1 1 10 100 1000 ch t, RECTANGULAR PULSE DURATION (sec) ® M Figure 13. Junction-to-Ambient Transient Thermal Response Curve O Figure 15. S 14 F E 12 T 10 A) 8 NT ( 6 di/dt = 300 A/µs RE R 4 U C 2 0 -2 0 20 40 60 80 100 TIME (ns ) Figure 14. Body Diode Reverse Recovery Characteristics ©2009 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FDMS7692A Rev.C1

PQFN85X6,1.27P CASE483AE ISSUEA 5.10 A 5.10 3.91 PKG SEE CL B DETAILB 1.27 8 5 8 7 6 5 0.77 4.52 3.75 PKGCL 6.15 5.85 6.61 5.65 KEEPOUT AREA 1.27 1 4 1 2 3 4 TOPVIEW 1.27 0.61 3.81 LANDPATTERN OPTIONALDRAFT RECOMMENDATION ANGLEMAYAPPEAR SEE ONFOURSIDES 5.00 4.80 DETAILC OFTHEPACKAGE 0.35 0.15 (cid:19)(cid:131)(cid:16)(cid:20)(cid:21)(cid:131) 0.10 C 0.30 0.05 0.05 SIDEVIEW 0.00 (cid:19)(cid:131)(cid:16)(cid:20)(cid:21)(cid:131) 8X 0.08 C 0.35 C 5.20 0.15 4.80 1.10 SEATING 0.90 PLANE DETAILC DETAILB 3.81 SCALE:2:1 SCALE:2:1 1.27 0.51 (8X) 0.31 (0.34) NOTES:UNLESSOTHERWISESPECIFIED 0.10 C A B A.PACKAGESTANDARDREFERENCE:JEDECMO-240, 1 2 3 4 ISSUEA,VAR.AA,. B.DIMENSIONSDONOTINCLUDEBURRSORMOLDFLASH. 0.76 MOLDFLASHORBURRSDOESNOTEXCEED0.10MM. 0.51 (0.52) C.ALLDIMENSIONSAREINMILLIMETERS. 6.25 D.DIMENSIONINGANDTOLERANCINGPERASMEY14.5M-2009. 5.90 E.ITISRECOMMENDEDTOHAVENOTRACESOR VIASWITHINTHEKEEPOUTAREA. (0.50) 3.48+0.30 -0.10 (0.30) (2X) 8 7 6 5 +0.10 (cid:19)(cid:17)(cid:23)(cid:23)(cid:147)(cid:19)(cid:17)(cid:20)(cid:19) 0.20 (8X) 3.96 -0.15 3.61 BOTTOMVIEW

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