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F D M S December 2011 3 6 2 FDMS3622S 2 S ® P PowerTrench Power Stage o w 25V Asymmetric Dual N-Channel MOSFET e r T Features General Description re n Q1: N-Channel c This device includes two specialized N-Channel MOSFETs in a h (cid:132) Max rDS(on) = 5.0 mΩ at VGS = 10 V, ID = 17.5 A dual PQFN package. The switch node has been internally ® P (cid:132) Max rDS(on) = 5.7 mΩ at VGS = 4.5 V, ID = 16 A connected to enable easy placement and routing of synchronous o Q2: N-Channel buck converters. The control MOSFET (Q1) and synchronous w e SyncFET (Q2) have been designed to provide optimal power (cid:132) Max r = 1.4 mΩ at V = 10 V, I = 34 A r DS(on) GS D efficiency. S (cid:132) Max rDS(on) = 1.6 mΩ at VGS = 4.5 V, ID = 32 A ta (cid:132) Low inductance packaging shortens rise/fall times, resulting in Applications g e lower switching losses (cid:132) Computing (cid:132) MOSFET integration enables optimum layout for lower circuit (cid:132) Communications inductance and reduced switch node ringing (cid:132) General Purpose Point of Load (cid:132) RoHS Compliant (cid:132) Notebook VCORE Pin 1 G1D1 D1 D1 Pin 1 D1 PHASE (S1/D2) G2 S2 S2 S2 Top Power 56 Bottom MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol Parameter Q1 Q2 Units V Drain to Source Voltage 25 25 V DS V Gate to Source Voltage (Note 4) ±12 ±12 V GS Drain Current -Continuous (Package limited) T = 25 °C 30 70 C I -Continuous T = 25 °C 17.51a 341b A D A -Pulsed 70 140 E Single Pulse Avalanche Energy (Note 3) 29 145 mJ AS Power Dissipation for Single Operation T = 25 °C 2.21a 2.51b P A W D Power Dissipation for Single Operation T = 25 °C 1.01c 1.01d A T , T Operating and Storage Junction Temperature Range -55 to +150 °C J STG Thermal Characteristics R Thermal Resistance, Junction to Ambient 571a 501b θJA R Thermal Resistance, Junction to Ambient 1251c 1201d °C/W θJA R Thermal Resistance, Junction to Case 3.0 1.9 θJC Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity 08OD FDMS3622S Power 56 13 ” 12 mm 3000 units 09OD ©2011 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDMS3622S Rev.C2

F D Electrical Characteristics M T = 25 °C unless otherwise noted J S Symbol Parameter Test Conditions Type Min Typ Max Units 3 6 2 Off Characteristics 2 S BVDSS Drain to Source Breakdown Voltage IID == 215 m0A μ,A V, VG =S =0 V0 V QQ12 2255 V P D GS o ΔBV Breakdown Voltage Temperature I = 250 μA, referenced to 25 °C Q1 12 w DSS D mV/°C ΔT Coefficient I = 10 mA, referenced to 25 °C Q2 24 e J D r Q1 1 μA T I Zero Gate Voltage Drain Current V = 20 V, V = 0 V r DSS DS GS Q2 500 μA e n Q1 ±100 nA c I Gate to Source Leakage Current V = 12 V/-8 V, V = 0 V GSS GS DS Q2 ±100 nA h ® On Characteristics P o V = V , I = 250 μA Q1 0.8 1.2 2.0 w VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 1 mA Q2 1.1 1.4 2.2 V e GS DS D r ΔV Gate to Source Threshold Voltage I = 250 μA, referenced to 25 °C Q1 -4 S ΔTGJS(th) Temperature Coefficient IDD = 10 mA, referenced to 25 °C Q2 -4 mV/°C ta g V = 10 V, I = 17.5 A 3.8 5.0 GS D e V = 4.5 V, I = 16 A Q1 4.4 5.7 GS D V = 10 V, I = 17.5 A,T =125 °C 5.4 7.0 r Drain to Source On Resistance GS D J mΩ DS(on) V = 10 V, I = 34 A 1.1 1.4 GS D V = 4.5 V, I = 32 A Q2 1.3 1.6 GS D V = 10 V, I =34 A ,T =125 °C 1.5 2.0 GS D J V = 5 V, I = 17.5 A Q1 100 g Forward Transconductance DS D S FS V = 5 V, I = 34 A Q2 272 DS D Dynamic Characteristics C Input Capacitance Q1: Q1 1570 pF iss V = 13 V, V = 0 V, f = 1 MHZ Q2 5565 DS GS Q1 448 C Output Capacitance pF oss Q2: Q2 1405 VDS = 13 V, VGS = 0 V, f = 1 MHZ Q1 61 C Reverse Transfer Capacitance pF rss Q2 182 Q1 0.4 R Gate Resistance Ω g Q2 0.8 Switching Characteristics Q1 7 t Turn-On Delay Time ns d(on) Q2 14 Q1: Q1 2 tr Rise Time VDD = 13 V, ID = 17.5 A, RGEN = 6 Ω Q2 7 ns Q1 23 t Turn-Off Delay Time Q2: ns d(off) Q2 48 V = 13 V, I = 34 A, R = 6 Ω DD D GEN Q1 2 t Fall Time ns f Q2 6 Q1 26 Qg Total Gate Charge VGS = 0 V to 10 V Q1 Q2 86 nC V = 13 V, DD Q1 12 Qg Total Gate Charge VGS = 0 V to 4.5 V ID = 17.5 A Q2 40 nC Q1 3.3 Qgs Gate to Source Gate Charge Q2 Q2 12 nC V = 13 V, DD Qgd Gate to Drain “Miller” Charge ID = 34 A QQ12 21.07 nC ©2011 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FDMS3622S Rev.C2

F D M Electrical Characteristics TJ = 25 °C unless otherwise noted S 3 Symbol Parameter Test Conditions Type Min Typ Max Units 6 2 Drain-Source Diode Characteristics 2 S V Source to Drain Diode Forward Voltage VGS = 0 V, IS = 17.5 A (Note 2) Q1 0.8 1.2 V P SD V = 0 V, I = 34 A (Note 2) Q2 0.8 1.2 o GS S w t Reverse Recovery Time Q1 Q1 23 ns e rr I = 17.5 A, di/dt = 100 A/μs Q2 35 r F T Q2 Q1 9 r Qrr Reverse Recovery Charge IF = 34 A, di/dt = 300 A/μs Q2 43 nC en c Notes: h ® 1th.eR θuJsAe irs's d beotearrmd idneesdi gwni.th the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by P o w b. 50 °C/W when mounted on a . a5 71 °iCn2/W pa wdh oefn 2m oozu n ctoepdp oenr a 1 in2 pad of 2 oz copper er S t a g e GDFDSSFSS GDFDSSFSS c. 125 °C/W when mounted on a d. 120 °C/W when mounted on a minimum pad of 2 oz copper minimum pad of 2 oz copper GDDSS GDDSS FSFS FSFS 2 Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. Q1 :EAS of 29 mJ is based on starting TJ = 25 oC; N-ch: L = 1.2 mH, IAS = 7 A, VDD = 23 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 16 A. Q2: EAS of 145 mJ is based on starting TJ = 25 oC; N-ch: L = 0.9 mH, IAS = 18 A, VDD = 23 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 39 A. 4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied. ©2011 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FDMS3622S Rev.C2

F D Typical Characteristics (Q1 N-Channel) M T = 25°C unless otherwise noted J S 3 6 70 3.0 2 T (A) 5600 VGVSG S= =4 .150 V V ESISTANCE 2.5 PDUULTSYE C DYUCRLEA TV=I GO0S.N5 = %= 2 8.M50 A VμXs 2S Pow DRAIN CURREN 234000 VGS = V2.G5S V V=G 3S V= 3.5 V NORMALIZED O SOURCE ON-R 12..50 VGS = 3 V erTrench I, D 10 PDUULTSYE C DYUCRLEA T=I O0.N5 %= 8M0A μXs RAIN T 1.0 VGS = 3.5 V VGS = 4.5 V VGS = 10 V Po® 0 D 0.5 w 0.0 0.3 0.6 0.9 1.2 1.5 0 10 20 30 40 50 60 70 e VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURR ENT (A) r S t a Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance g vs Drain Current and Gate Voltage e 1.8 20 TANCE 1.6 VIDG =S 1=7 1.50 AV ()mΩ 16 ID = 17.5 A PDUULTSYE C DYUCRLEA T=I O0.N5 %= 8M0A μXs S E ALIZEDE ON-RESI 11..24 DRAIN TO ESISTANC 12 NORM AIN TO SOURC 01..80 r,DS(on)SOURCE ON-R 48 TTJJ == 12255 o oCC R D 0.6 0 -75 -50 -25 0 25 50 75 100 125 150 2 3 4 5 6 7 8 9 10 TJ, JUNCTION TEM PERATURE (oC) VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On Resistance Figure 4. On-Resistance vs Gate to vs Junction Temperature Source Voltage 70 70 CURRENT (A) 34560000 PDVUUDLTSS Y=E C5 D YVUCRLEA T=IT O0J.N 5= % =1 58M00A oμXCs DRAIN CURRENT (A) 101 VGS = 0 VTJ = 150 oC TJ = 25 oC AIN TJ = 25 oC SE 0.1 , DRD 20 TJ = -55 oC EVER0.01 TJ = -55 oC I 10 , RS I 0 0.001 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VGS, GATE TO SOU RCE VOLTAGE (V) VSD, BODY DIODE FOR WARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current ©2011 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FDMS3622S Rev.C2

F D Typical Characteristics (Q1 N-Channel) T = 25°C unless otherwise noted M J S 3 6 2 10 2000 2 V) ID = 17.5 A S GE ( 8 1000 Ciss P A o RCE VOLT 6 VDD = 10 V VDD = 1V3D DV = 15 V ANCE (pF) Coss werTr O SOU 4 PACIT 100 enc T A h ATE 2 C Crss ® G f = 1 MHz P , GS VGS = 0 V o V 0 10 w 0 4 8 12 16 20 24 28 0.1 1 10 30 e Qg, GATE CH ARGE (nC) VDS, DRAIN TO SOU RCE VOLTAGE (V) r S t a Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain g to Source Voltage e 50 80 70 HE CURRENT (A) 10 TJ = 25 oCTJ = 100 oC N CURRENT (A) 456000 VGS = 4.5 V VGS = 10 V NC RAI 30 ALA TJ = 125 oC , DD20 V I Limited by Package A , AS 10 RθJC = 3.0 oC/W I 1 0 0.001 0.01 0.1 1 10 50 25 50 75 100 125 150 tAV, TIME IN AVA LANCHE (ms) TC, CASE TEMPERATURE (oC) Figure 9. Unclamped Inductive Figure 10. Maximum Continuous Drain Switching Capability Current vs Case Temperature 100 1000 W) SINGLE PULSE 100 μs R ( RθJA = 125 oC/W T (A) 10 OWE 100 N P DRAIN CURRE 1 SINTLGHIMLISIET AE PRDUE BLAYS I ESrD S(on) 11100 m 0m msss K TRANSIENT 10 I, D0.00.11 TRTJAθ J ==A M2=5 A1 Xo2C5 R oACT/WED D11s0Cs P, PEA()PK 0.15 0.01 0.1 1 10 100200 10-4 10-3 10-2 10-1 1 10 100 1000 VDS, DRAIN to SOU RCE VOLTAGE (V) t, PULSE WIDT H (sec) Figure 11. Forward Bias Safe Figure 12. Single Pulse Maximum Operating Area Power Dissipation ©2011 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FDMS3622S Rev.C2

F D Typical Characteristics (Q1 N-Channel) T = 25°C unless otherwise noted M J S 3 6 2 2 DUTY CYCLE-DESCENDING ORDER 2 1 S D = 0.5 P L 0.2 o MA A 0.1 w ALIZED THER ZPEDANCE,Jθ 0.1 000...000521 PDM t1 erTrenc RMIM 0.01 SINGLE PULSE t2 h NO R(NθoJAte = 1 1b2)5 oC/W NDOUTTYE SF:ACTOR: D = t1/t2 P® PEAK TJ = PDM x ZθJA x RθJA + TA o w 0.001 e 10-4 10-3 10-2 10-1 1 10 100 1000 r S t, RECTANGULAR PULSE DURATION (sec) t a Figure 13. Junction-to-Ambient Transient Thermal Response Curve g e ©2011 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com FDMS3622S Rev.C2

F D Typical Characteristics (Q2 N-Channel) T = 25 °C unless otherwise noted M J S 3 6 2 140 4 2 VGS = 10 V CE PULSE DURATION = 80 μs S 120 VGS = 4.5 V AN VGS = 2.5 V DUTY CYCLE = 0.5% MAX P NT (A)100 VGVSG =S 3= V3.5 V DRESIST 3 owe N CURRE 6800 VGS = 2.5 V ORMALIZEURCE ON- 2 VGS = 3 V VGS = 3.5 V rTren I, DRAID 2400 PULSE DURATION = 80 μs NAIN TO SO 1 VGS = 4.5 V VGS = 10 V ch P® 0 DUTY CYCLE = 0.5% MAX DR 0 ow 0.0 0.3 0.6 0.9 1.2 1.5 0 20 40 60 80 100 120 140 e r V , DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURR ENT (A) S DS t a Figure 14. On-Region Characteristics Figure 15. Normalized on-Resistance vs Drain g Current and Gate Voltage e 1.6 5 E ID = 34 A PULSE DURATION = 80 μs TANC 1.4 VGS = 10 V ()mΩ 4 DUTY CYCLE = 0.5% MAX S E ALIZEDE ON-RESI 1.2 DRAIN TO ESISTANC 3 ID = 34 A NORM N TO SOURC 01..80 r,DS(on)OURCE ON-R 12 TJ = 125 oC AI S TJ = 25 oC R D 0.6 0 -75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10 TJ, JUNCTION TEM PERATURE (oC) VGS, GATE TO SOURCE VOLTAGE (V) Figure 16. Normalized On-Resistance Figure 17. On-Resistance vs Gate to vs Junction Temperature Source Voltage 140 200 120 PDUULTSYE C DYUCRLEA T=I O0.N5 %= 8M0A μXs T (A) 100 VGS = 0 V NT (A)100 VDS = 5 V URREN 10 TJ = 125 oC RE 80 N C 1 RAIN CUR 4600 TJ = 125 oC TJ = 25 oC RSE DRAI 0.1 TJ = -55T oJC = 25 oC D E I, D 20 TJ = -55 oC REV0.01 , S I 0 1.0 1.5 2.0 2.5 3.0 0.001 0.0 0.2 0.4 0.6 0.8 1.0 VGS, GATE TO SOU RCE VOLTAGE (V) VSD, BODY DIODE FO RWARD VOLTAGE (V) Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode Forward Voltage vs Source Current ©2011 Fairchild Semiconductor Corporation 7 www.fairchildsemi.com FDMS3622S Rev.C2

F D M Typical Characteristics (Q2 N-Channel) T = 25°C unless otherwise noted S J 3 6 2 10 10000 2 S GE (V) 8 ID = 34 A Ciss Po A E VOLT 6 VDD = 10 V CE (pF) Coss werT E TO SOURC 4 VDD = 1V5D VD = 13 V CAPACITAN1000 Crss rench® AT 2 f = 1 MHz P , GS VGS = 0 V o VG 0 100 w 0 15 30 45 60 75 90 0.1 1 10 30 e Qg, GATE CH ARGE (nC) VDS, DRAIN TO SOU RCE VOLTAGE (V) r S t a g Figure 20. Gate Charge Characteristics Figure 21. Capacitance vs Drain e to Source Voltage 100 180 RENT (A) TJ = 25 oC ENT (A) 112500 VGS = 10 V R R VALANCHE CU 10 TJ = 125 oC TJ = 100 oC , IDRAIN CURD 6900 Limited by PacVkGaSg =e 4.5 V I, AAS 30 RθJC = 1.9 oC/W 1 0 0.001 0.01 0.1 1 10 100 1000 25 50 75 100 125 150 tAV, TIME IN AVA LANCHE (ms) TC, CASE TEMPERATURE (oC) Figure 22. Unclamped Inductive Figure 23. Maximum Continuous Drain Switching Capability Current vs Case Temperature 200 3000 100 100 μs W) 1000 SINGLE PULSE R ( R = 120 oC/W A) E θJA T ( 10 OW RREN 1 ms NT P 100 AIN CU 1 TLHIMISIT AERDE BAY I SrD S(on) 1100 0m mss RANSIE R SINGLE PULSE T 10 I, DD 0.1 TRTJAθ J ==A M2=5 A1 Xo2C 0R oACT/WED D11sC0s , PEAK )PK 1 0.01 P( 0.5 0.01 0.1 1 10 100 10-4 10-3 10-2 10-1 1 10 100 1000 VDS, DRAIN to SOU RCE VOLTAGE (V) t, PULSE WIDT H (sec) Figure 24. Forward Bias Safe Figure 25. Single Pulse Maximum Power Operating Area Dissipation ©2011 Fairchild Semiconductor Corporation 8 www.fairchildsemi.com FDMS3622S Rev.C2

F D M Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted S 3 6 2 2 DUTY CYCLE-DESCENDING ORDER 2 1 S P L D = 0.5 o MA A 0.1 0.2 w ERZJθ 0.1 e ALIZED TH PEDANCE, 0.01 000...000521 PDM t1 rTrenc NORMIM 0.001 SRIθNJAG =L E1 2P0U oLCS/EW NDOUTTYE SF:ACTOR: D = t1/t2 t2 h P® (Note 1b) PEAK TJ = PDM x ZθJA x RθJA + TA o w 0.0001 e 10-4 10-3 10-2 10-1 1 10 100 1000 r S t, RECTANGULAR PULSE DURATION (sec) t a g Figure 26. Junction-to-Ambient Transient Thermal Response Curve e ©2011 Fairchild Semiconductor Corporation 9 www.fairchildsemi.com FDMS3622S Rev.C2

F D Typical Characteristics M (continued) S 3 6 2 SyncFET Schottky body diode 2 S Characteristics P o Fairchild’s SyncFET process embeds a Schottky diode in parallel Schottky barrier diodes exhibit significant leakage at high tem- w with PowerTrench MOSFET. This diode exhibits similar perature and high reverse voltage. This will increase the power e characteristics to a discrete external Schottky diode in parallel in the device. rT with a MOSFET. Figure 27 shows the reverse recovery re characteristic of the FDMS3622S. n c h ® P 40 10-2 o 3305 ENT (A) TJ = 125 oC wer RR 10-3 S A) 25 CU ta RRENT ( 1250 di/dt = 300 A/μs AKAGE 10-4 TJ = 100 oC ge CU 10 E LE 5 ERS 10-5 TJ = 25 oC V 0 E R -50 40 80 120 160 200 240 280 320 360 I, DSS10-60 5 10 15 20 25 TIME (ns) V , REVERSE VOLTAGE (V) DS Figure 27. FDMS3622S SyncFET body Figure 28. SyncFET body diode reverse diode reverse recovery characteristic leakage versus drain-source voltage ©2011 Fairchild Semiconductor Corporation 10 www.fairchildsemi.com FDMS3622S Rev.C2

4.00 0 0 5.10 2. CL 0.10 C 4.90 A 00 (2X) PKG B 0. 10..2675 TTYYPP CL 8 5 8 7 6 5 0.63 2.52 1.60 6.25 2.15 KEEP OUT AREA PKG CL 5.90 0.00CL 4.16 1.21 2.13 2.31 1 4 0.10 C 1 2 3 4 3.15 PIN # 1 0.63 INDICATOR (2X) 0.59 TOP VIEW 8 1 1. 3.18 5.10 SEE RECOMMENDED LAND PATTERN DETAIL A FOR SAWN / PUNCHED TYPE SIDE VIEW 0.10 C A B 0.10 C 0.05 C 0.65 3.16 0.70 0.38 2.80 0.36 8X 0.45 0.08 C 0.25 1 2 3 4 1.34 0.35 0.05 C (6X) 1.12 1.10 0.15 0.00 0.90 SEATING PLANE 0.66±.05 (SCALE: 2X) 2.25 4.08 2.05 3.70 1.02 0.65 8 7 6 5 0.82 0.38 0.44 0.61 (8X) 0.24 0.31 1.27 3.81 BOTTOM VIEW

5.10 0.10 C 4.90 (2X) SEE PKG DETAIL B 0.35 C 0.15 L 8 5 0.28 0.08 10° 6.25 5.90 PKG CL 5.90 5.70 (SCALE: 2X) 1 4 0.10 C (2X) 0.41 (8X) 0.21 TOP VIEW 5.00 4.80 SEE 0.10 C DETAIL C 0.35 0.15 8X 0.08 C C SIDE VIEW 1.10 SEATING 0.90 PLANE (SCALE: 2X) 0.65 3.16 0.70 0.10 C A B 0.38 2.80 0.36 0.05 C 0.45 0.25 1 2 3 4 1.34 (6X) 1.12 NOTES: UNLESS OTHERWISE SPECIFIED 0.66±.05 A) PACKAGE STANDARD REFERENCE: JEDEC REGISTRATION, MO-240, VARIATION AA. 4.08 2.25 B) ALL DIMENSIONS ARE IN MILLIMETERS. 3.70 2.05 C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER 1.02 ASME Y14.5M-1994. 0.65 8 7 6 5 0.82 E) IT IS RECOMMENDED TO HAVE NO TRACES 0.38 OR VIAS WITHIN THE KEEP OUT AREA. 0.44 0.61 F) DRAWING FILE NAME: PQFN08EREV6. (8X) 0.24 0.31 G) FAIRCHILD SEMICONDUCTOR 1.27 3.81 BOTTOM VIEW

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