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F D M S 3 September 2011 6 0 FDMS3604AS 4 A ® S PowerTrench Power Stage P o 30 V Asymmetric Dual N-Channel MOSFET w e Features General Description r T r Q1: N-Channel This device includes two specialized N-Channel MOSFETs in a e n (cid:132) Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A dual PQFN package. The switch node has been internally c h (cid:132) Max rDS(on) = 11 mΩ at VGS = 4.5 V, ID = 11 A connected to enable easy placement and routing of synchronous ® buck converters. The control MOSFET (Q1) and synchronous P Q2: N-Channel SyncFET (Q2) have been designed to provide optimal power o (cid:132) Max r = 2.6 mΩ at V = 10 V, I = 23 A w DS(on) GS D efficiency. e (cid:132) Max r = 3.5 mΩ at V = 4.5 V, I = 21 A r DS(on) GS D Applications S (cid:132) Low inductance packaging shortens rise/fall times, resulting in t a lower switching losses (cid:132) Computing g e (cid:132) MOSFET integration enables optimum layout for lower circuit (cid:132) Communications inductance and reduced switch node ringing (cid:132) General Purpose Point of Load (cid:132) RoHS Compliant (cid:132) Notebook VCORE (cid:132) Sever G1 D1 D1D1 D1 S2 5 Q2 4 D1 PHASE S2 6 PHASE 3 D1 (S1/D2) S2 7 2 D1 G2 S2 S2 G2 8 1 G1 S2 Q1 Top Power 56 Bottom MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol Parameter Q1 Q2 Units V Drain to Source Voltage 30 30 V DS V Gate to Source Voltage (Note 3) ±20 ±20 V GS Drain Current -Continuous (Package limited) T = 25 °C 30 40 C -Continuous (Silicon limited) T = 25 °C 60 130 I C A D -Continuous T = 25 °C 131a 231b A -Pulsed 40 100 E Single Pulse Avalanche Energy 404 1125 mJ AS Power Dissipation for Single Operation T = 25 °C 2.21a 2.51b P A W D Power Dissipation for Single Operation T = 25 °C 1.01c 1.01d A T , T Operating and Storage Junction Temperature Range -55 to +150 °C J STG Thermal Characteristics R Thermal Resistance, Junction to Ambient 571a 501b θJA R Thermal Resistance, Junction to Ambient 1251c 1201d °C/W θJA R Thermal Resistance, Junction to Case 3.5 2 θJC Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity 22CA FDMS3604AS Power 56 13 ” 12 mm 3000 units N7CC ©2011 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDMS3604AS Rev.C4

F D Electrical Characteristics M T = 25 °C unless otherwise noted J S Symbol Parameter Test Conditions Type Min Typ Max Units 3 6 0 Off Characteristics 4 A BV Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V Q1 30 V S DSS I = 1 mA, V = 0 V Q2 30 D GS P ΔBV Breakdown Voltage Temperature I = 250 μA, referenced to 25 °C Q1 15 o DSS D mV/°C w ΔT Coefficient I = 10 mA, referenced to 25 °C Q2 12 J D e Q1 1 μA r IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V Q2 500 μA Tr e I Gate to Source Leakage Current, V = 20 V, V = 0 V Q1 100 nA n GSS Forwad GS DS Q2 100 nA c h ® On Characteristics P V = V , I = 250 μA Q1 1.1 2 2.7 o VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 1 mA Q2 1.1 1.8 3 V w GS DS D e ΔV Gate to Source Threshold Voltage I = 250 μA, referenced to 25 °C Q1 -6 r ΔTGS(th) Temperature Coefficient ID = 10 mA, referenced to 25 °C Q2 -5 mV/°C S J D t V = 10 V, I = 13 A 5.8 8 a GS D g VGS = 4.5 V, ID = 11 A Q1 8.5 11 e V = 10 V, I = 13 A , T = 125 °C 7.8 10.8 r Drain to Source On Resistance GS D J mΩ DS(on) V = 10 V, I = 23 A 2 2.6 GS D V = 4.5 V, I = 21 A Q2 2.6 3.5 GS D V = 10 V, I = 23 A , T = 125 °C 2.6 4 GS D J V = 5 V, I = 13 A Q1 61 g Forward Transconductance DS D S FS V = 5 V, I = 23 A Q2 130 DS D Dynamic Characteristics C Input Capacitance Q1: Q1 1273 1695 pF iss V = 15 V, V = 0 V, f = 1 MHZ Q2 3078 4095 DS GS Q1 461 615 C Output Capacitance pF oss Q2: Q2 1169 1555 VDS = 15 V, VGS = 0 V, f = 1 MHZ Q1 50 75 C Reverse Transfer Capacitance pF rss Q2 98 150 Q1 0.2 0.6 2 R Gate Resistance Ω g Q2 0.2 0.8 3 Switching Characteristics Q1 8.2 16 t Turn-On Delay Time ns d(on) Q2 13 23 Q1: Q1 2.5 10 tr Rise Time VDD = 15 V, ID = 13 A, RGEN = 6 Ω Q2 4.8 10 ns Q1 20 32 t Turn-Off Delay Time Q2: ns d(off) Q2 31 50 V = 15 V, I = 23 A, R = 6 Ω DD D GEN Q1 2.2 10 t Fall Time ns f Q2 3.4 10 Q1 21 29 Qg Total Gate Charge VGS = 0 V to 10 V Q1 Q2 47 66 nC V = 15 V, DD Q1 10 14 Qg Total Gate Charge VGS = 0 V to 4.5 V ID = 13 A Q2 22 31 nC Q1 3.9 Qgs Gate to Source Gate Charge Q2 Q2 9 nC V = 15 V, DD Qgd Gate to Drain “Miller” Charge ID = 23 A QQ12 35..15 nC ©2011 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FDMS3604AS Rev.C4

F D Electrical Characteristics M T = 25 °C unless otherwise noted J S Symbol Parameter Test Conditions Type Min Typ Max Units 3 6 0 Drain-Source Diode Characteristics 4 A V Source to Drain Diode Forward Voltage VGS = 0 V, IS = 13 A (Note 2) Q1 0.8 1.2 V S SD VGS = 0 V, IS = 23A (Note 2) Q2 0.8 1.2 P Q1 Q1 25 40 o trr Reverse Recovery Time I = 13 A, di/dt = 100 A/μs Q2 32 51 ns w F e Q2 Q1 9 18 r Qrr Reverse Recovery Charge IF = 23 A, di/dt = 300 A/μs Q2 39 62 nC Tr e Notes: n 1: Rbyθ JtAh eis u dseetre'sr mboinaerdd wdeitshi gthne. device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined ch ® b. 50 °C/W when mounted on P a . a5 71 °iCn2/W p wadh eonf m2 oouzn tceodp opne r a 1 in2 pad of 2 oz copper o w e r S t a g e c. 125 °C/W when mounted on a d. 120 °C/W when mounted on a minimum pad of 2 oz copper minimum pad of 2 oz copper 2: Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied. 4: EAS of 40 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 9 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 14 A. 5: EAS of 112 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 15 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 22 A. ©2011 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FDMS3604AS Rev.C4

F D Typical Characteristics (Q1 N-Channel) M T = 25 °C unless otherwise noted J S 3 6 40 4 0 VGS = 10 V NCE VGS = 3.5 V PDUULTSYE C DYUCRLEA T=I O0.N5 %= 8M0A μXs 4A NT (A) 30 VGSV =G S4 .5= V6 V DRESISTA 3 VGS = 4 V S Po I, DRAIN CURRE D 1200 VGSV G=S 4= V 3.5 VPULSE DURATION = 80 μs NORMALIZEAIN TO SOURCE ON- 12 VVGGVSSG = S= 4= 1. 506 VVV werTrench® DUTY CYCLE = 0.5% MAX R D P 0 0 0.0 0.2 0.4 0.6 0.8 1.0 0 10 20 30 40 o w VDS, DRAIN TO SO URCE VOLTAGE (V) ID, DRAIN CURR ENT (A) e r Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance S vs Drain Current and Gate Voltage ta g e 1.6 20 NORMALIZED O SOURCE ON-RESISTANCE 111...024 VIDG =S 1=3 1 A0 V rDRAIN TO ,DS(on)()mCE ON-RESISTANCE Ω 11826 PDUULTTSYJIE D C= =D Y1 UC1235RL EAoAC T=I O0.N5 %= 8M0A μXs RAIN T 0.8 SOUR 4 TJ = 25 oC D 0.6 0 -75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10 TJ, JUNCTION TEM PERATURE (oC) VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On Resistance Figure 4. On-Resistance vs Gate to vs Junction Temperature Source Voltage 40 40 PULSE DURATION = 80 μs A) VGS = 0 V DUTY CYCLE = 0.5% MAX T ( 10 N E A) 30 R T ( VDS = 5 V UR 1 CURREN 20 TJ = 150 oC DRAIN C 0.1 TJ = 150 oC TJ = 25 oC AIN TJ = 25 oC RSE R E D 10 V , D RE 0.01 TJ = -55 oC I TJ = -55 oC I, S 0 0.001 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VGS, GATE TO SOU RCE VOLTAGE (V) VSD, BODY DIODE FOR WARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current ©2011 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FDMS3604AS Rev.C4

F D Typical Characteristics (Q1 N-Channel) M T = 25 °C unless otherwise noted J S 3 6 10 2000 0 E (V) ID = 13 A VDD = 10 V 1000 Ciss 4A G 8 S A LT VDD = 15 V F) P SOURCE VO 46 VDD = 20 V CITANCE (p 100 Coss owerT O PA re E T CA n AT 2 Crss c G f = 1 MHz h , GS VGS = 0 V ® V 0 10 P 0 5 10 15 20 25 0.1 1 10 30 o Qg, GATE CH ARGE (nC) VDS, DRAIN TO SOU RCE VOLTAGE (V) w e r Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain S to Source Voltage t a g e 20 100 RθJC = 3.5 oC/W NT (A) 10 T (A) 80 VGS = 10 V E N R E UR TJ = 25 oC RR 60 C U CHE TJ = 100 oC AIN C 40 VGS = 4.5 V AVALAN , IDRD 20 , S TJ = 125 oC Limited by Package A I 1 0 0.01 0.1 1 10 100 25 50 75 100 125 150 tAV, TIME IN AVA LANCHE (ms) TC, CASE TEMPERATURE (oC) Figure 9. Unclamped Inductive Figure 10. Maximum Continuous Drain Switching Capability Current vs Case Temperature 100 1000 W) T (A) 10 100us OWER ( 100 SRTAIθNJ =AG 2=L5 E1 o 2PC5U oLCS/WE REN 1 ms NT P AIN CUR 1 TLHIMISIT AERDE BAY I SrD S(on) 11000 m mss RANSIE 10 DR SINGLE PULSE 1s K T I, D00.0.11 RTTJAθ J ==A M2=5 A1 Xo2C 5R oACT/WED D10Cs , PPEA()PK 0.11 0.01 0.1 1 10 100 200 10-4 10-3 10-2 10-1 1 10 100 1000 VDS, DRAIN to SOU RCE VOLTAGE (V) t, PULSE WI DTH (sec) Figure 11. Forward Bias Safe Figure 12. Single Pulse Maximum Operating Area Power Dissipation ©2011 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FDMS3604AS Rev.C4

F D Typical Characteristics (Q1 N-Channel) M T = 25 °C unless otherwise noted J S 3 6 2 0 DUTY CYCLE-DESCENDING ORDER 4 1 A D = 0.5 S MAL A 00..21 Po ERZJθ 0.1 0.05 w RMALIZED TH IMPEDANCE, 0.01 00..0021 SINGLE PULSE PDM t1t2 erTrenc NO RθJA = 125 oC/W NDOUTTYE SF:ACTOR: D = t1/t2 h® (Note 1c) PEAK TJ = PDM x ZθJA x RθJA + TA P o 0.001 w 10-4 10-3 10-2 10-1 1 10 100 1000 e t, RECTANGULAR PULSE DURATION (sec) r S Figure 13. Junction-to-Ambient Transient Thermal Response Curve ta g e ©2011 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com FDMS3604AS Rev.C4

F D Typical Characteristics (Q2 N-Channel) T = 25 oC unlenss otherwise noted M J S 3 6 100 8 0 VGS = 10 V CE PULSE DURATION = 80 μs 4 NT (A) 80 VGVS G=S 4= V 4.5 V DRESISTAN 6 VGS = 3 V DUTY CYCLVEG S= =0 .35.%5 V MAX AS Po , DRAIN CURRED 246000 VGS = 3.5 PDVUULTSYE C DYUCRLEA T=I O0.N5 %= 8M0A μXs NORMALIZEN TO SOURCE ON- 24 VGS = 4 V VGS = 4.5 V werTrench I AI ® 0 VGS = 3 V DR 0 VGS = 10 V P 0.0 0.2 0.4 0.6 0.8 1.0 0 20 40 60 80 100 o w VDS, DRAIN TO SO URCE VOLTAGE (V) ID, DRAIN CURR ENT (A) e r Figure 14. On-Region Characteristics Figure 15. Normalized on-Resistance vs Drain S Current and Gate Voltage t a g e 1.6 12 CE ID = 23 A ) PULSE DURATION = 80 μs AN VGS = 10 V mΩ DUTY CYCLE = 0.5% MAX ST 1.4 (E 9 ALIZEDE ON-RESI 1.2 DRAIN TO ESISTANC 6 ID = 23 A NORM AIN TO SOURC 1.0 r,DS(on)SOURCE ON-R 3 TTJJ == 12255 o oCC R D 0.8 0 -75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10 TJ, JUNCTION TEM PERATURE (oC) VGS, GATE TO SOURCE VOLTAGE (V) Figure 16. Normalized On-Resistance Figure 17. On-Resistance vs Gate to vs Junction Temperature Source Voltage 100 100 PULSE DURATION = 80 μs A) VGS = 0 V DUTY CYCLE = 0.5% MAX T ( T (A) 80 VDS = 5 V URREN 10 TJ = 125 oC N C URRE 60 TJ = 125 oC RAIN 1 TJ = 25 oC C D N 40 E 0.1 RAI TJ = 25 oC ERS , DD 20 REV 0.01 TJ = -55 oC I TJ = -55 oC I, S 0 0.001 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VGS, GATE TO SOU RCE VOLTAGE (V) VSD, BODY DIODE FOR WARD VOLTAGE (V) Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode Forward Voltage vs Source Current ©2011 Fairchild Semiconductor Corporation 7 www.fairchildsemi.com FDMS3604AS Rev.C4

F D M Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted S 3 6 10 10000 0 OLTAGE (V) 8 ID = 23 A VDD = 10 V pF)1000 Ciss 4AS Po E V 6 CE ( Coss w C N e O SOUR 4 VDD = 15 V PACITA 100 rTre E T VDD = 20 V CA Crss nc AT 2 h , GGS fV =G S1 =M 0H Vz P® V 0 10 0 10 20 30 40 50 0.1 1 10 30 o w Qg, GATE CH ARGE (nC) VDS, DRAIN TO SOU RCE VOLTAGE (V) e r Figure 20. Gate Charge Characteristics Figure 21. Capacitance vs Drain S to Source Voltage ta g e 50 160 RθJC = 2 oC/W NT (A) T (A) 120 RE TJ = 25 oC EN VGS = 10 V UR 10 RR C U VALANCHE TJ = 125 oC TJ = 100 oC , IDRAIN CD 4800 VGS = 4.5 V A , AS Limited by Package I 1 0 0.01 0.1 1 10 100 1000 25 50 75 100 125 150 tAV, TIME IN AVA LANCHE (ms) TC, CASE TEMPERATURE (oC) Figure 22. Unclamped Inductive Figure 23. Maximun Continuous Drain Switching Capability Current vs Case Temperature 200 1000 100 W) T (A) 10 1 ms OWER ( 100 TSRAIθNJ =AG 2=L5 E1 o 2PC0U oLCS/WE N P E T RR 10 ms EN N CU 1 TLHIMISIT AERDE BAY I SrD S(on) 100 ms ANSI 10 AI R DR SINGLE PULSE 1s K T , D 0.1 TJ = MAX RATED 10s EA 1 I 0.01 TRAθJ =A 2=5 1 o2C0 oC/W DC , PP()PK 0.1 0.01 0.1 1 10 100200 10-3 10-2 10-1 1 10 100 1000 VDS, DRAIN to SOU RCE VOLTAGE (V) t, PULSE WI DTH (sec) Figure 24. Forward Bias Safe Figure 25. Single Pulse Maximum Operating Area Power Dissipation ©2011 Fairchild Semiconductor Corporation 8 www.fairchildsemi.com FDMS3604AS Rev.C4

F D Typical Characteristics (Q2 N-Channel) T = 25 oC unless otherwise noted M J S 3 6 0 4 2 A DUTY CYCLE-DESCENDING ORDER S 1 P D = 0.5 o AL 0.2 w D THERM NCE,ZJAθ 0.1 0000....1000521 PDM erTre LIZEEDA t1 nc NORMAIMP 0.01 SRIθNJAG =L E1 2P0U oLCS/WE NDOUTTYE SF:ACTOR: D = t1/t2 t2 h P® (Note 1d) PEAK TJ = PDM x ZθJA x RθJA + TA o w e 0.001 r 10-3 10-2 10-1 1 10 100 1000 S t, RECTANGULAR PULSE DURATION (sec) t a g Figure 26. Junction-to-Ambient Transient Thermal Response Curve e ©2011 Fairchild Semiconductor Corporation 9 www.fairchildsemi.com FDMS3604AS Rev.C4

F D Typical Characteristics (continued) M S 3 6 0 SyncFET Schottky body diode 4 A Characteristics S P Fairchild’s SyncFET process embeds a Schottky diode in parallel Schottky barrier diodes exhibit significant leakage at high tem- o with PowerTrench MOSFET. This diode exhibits similar perature and high reverse voltage. This will increase the power w characteristics to a discrete external Schottky diode in parallel in the device. er with a MOSFET. Figure 27 shows the reverse recovery T r characteristic of the FDMS3604AS. e n c h ® 25 10-2 A) TJ = 125 oC P 20 NT ( ow didt = 300 A/μs RE 10-3 e A) 15 CUR TJ = 100 oC r S CURRENT ( 105 E LEAKAGE 10-4 tage S R 10-5 0 VE TJ = 25 oC E R , S -5 DS10-6 0 50 100 150 200 I 0 5 10 15 20 25 30 TIME (ns) VDS, REVERSE VOLTAGE (V) Figure 27. FDMS3604AS SyncFET body Figure 28. SyncFET body diode reverse diode reverse recovery characteristic leakage versus drain-source voltage ©2011 Fairchild Semiconductor Corporation 10 www.fairchildsemi.com FDMS3604AS Rev.C4

F D Application Information M S 3 1. Switch Node Ringing Suppression 6 0 Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch 4 node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage A S solution rings significantly less than competitor solutions under the same set of test conditions. P o w e r T r e n c h ® P o w e r S t a g e Power Stage Device Competitors solution Figure 29. Power Stage phase node rising edge, High Side Turn on *Patent Pending ©2011 Fairchild Semiconductor Corporation 11 www.fairchildsemi.com FDMS3604AS Rev.C4

F D M S 3 6 0 4 A S P o w e r T r e n c h ® P o w e r S t a g e Figure 30. Shows the Power Stage in a buck converter topology 2. Recommended PCB Layout Guidelines As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout proce- dure is discussed below to maximize the electrical and thermal performance of the part. Figure 31. Recommended PCB Layout ©2011 Fairchild Semiconductor Corporation 12 www.fairchildsemi.com FDMS3604AS Rev.C4

F D Following is a guideline, not a requirement which the PCB designer should consider: M S 1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic 3 6 inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close 0 to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected 4 A depending upon the application. S P 2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output o inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to w present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction e r losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high T noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance re between the thermal and electrical performance of Power Stage. n c h 3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace ® resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be P directly in line (as shown in figure 31) with the inductor for space savings and compactness. o w 4. The PowerTrench® Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the er part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If S the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen ta the high-frequency ringing. g e 5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses. Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This provides a very compact path for the drive signals and improves efficiency of the part. 6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET. 7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction. Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected from the backside via a network of low inductance vias. ©2011 Fairchild Semiconductor Corporation 13 www.fairchildsemi.com FDMS3604AS Rev.C4

4.00 0 0 5.10 2. CL 0.10 C 4.90 A 00 (2X) PKG B 0. 10..2675 TTYYPP CL 8 5 8 7 6 5 0.63 2.52 1.60 6.25 2.15 KEEP OUT AREA PKG CL 5.90 0.00CL 4.16 1.21 2.13 2.31 1 4 0.10 C 1 2 3 4 3.15 PIN # 1 0.63 INDICATOR (2X) 0.59 TOP VIEW 8 1 1. 3.18 5.10 SEE RECOMMENDED LAND PATTERN DETAIL A FOR SAWN / PUNCHED TYPE SIDE VIEW 0.10 C A B 0.10 C 0.05 C 0.65 3.16 0.70 0.38 2.80 0.36 8X 0.45 0.08 C 0.25 1 2 3 4 1.34 0.35 0.05 C (6X) 1.12 1.10 0.15 0.00 0.90 SEATING PLANE 0.66±.05 (SCALE: 2X) 2.25 4.08 2.05 3.70 1.02 0.65 8 7 6 5 0.82 0.38 0.44 0.61 (8X) 0.24 0.31 1.27 3.81 BOTTOM VIEW

5.10 0.10 C 4.90 (2X) SEE PKG DETAIL B 0.35 C 0.15 L 8 5 0.28 0.08 10° 6.25 5.90 PKG CL 5.90 5.70 (SCALE: 2X) 1 4 0.10 C (2X) 0.41 (8X) 0.21 TOP VIEW 5.00 4.80 SEE 0.10 C DETAIL C 0.35 0.15 8X 0.08 C C SIDE VIEW 1.10 SEATING 0.90 PLANE (SCALE: 2X) 0.65 3.16 0.70 0.10 C A B 0.38 2.80 0.36 0.05 C 0.45 0.25 1 2 3 4 1.34 (6X) 1.12 NOTES: UNLESS OTHERWISE SPECIFIED 0.66±.05 A) PACKAGE STANDARD REFERENCE: JEDEC REGISTRATION, MO-240, VARIATION AA. 4.08 2.25 B) ALL DIMENSIONS ARE IN MILLIMETERS. 3.70 2.05 C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER 1.02 ASME Y14.5M-1994. 0.65 8 7 6 5 0.82 E) IT IS RECOMMENDED TO HAVE NO TRACES 0.38 OR VIAS WITHIN THE KEEP OUT AREA. 0.44 0.61 F) DRAWING FILE NAME: PQFN08EREV6. (8X) 0.24 0.31 G) FAIRCHILD SEMICONDUCTOR 1.27 3.81 BOTTOM VIEW

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