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F D M F 6 April 2013 8 2 0 C — FDMF6820C — Extra-Small, High-Performance, E x t High-Frequency DrMOS Module r a - S m Benefits Description a l l ,  Ultra-Compact 6x6 mm PQFN, 72% Space-Saving The XS™ DrMOS family is Fairchild’s next-generation, H Compared to Conventional Discrete Solutions fully optimized, ultra-compact, integrated MOSFET plus ig  Fully Optimized System Efficiency driver power stage solution for high-current, high- h- frequency, synchronous buck DC-DC applications. The P  Clean Switching Waveforms with Minimal Ringing FDMF6820C integrates a driver IC, two power er f  High-Current Handling MOSFETs, and a bootstrap Schottky diode into a o thermally enhanced, ultra-compact 6x6 mm package. rm Features a With an integrated approach, the complete switching n power stage is optimized with regard to driver and c  Over 93% Peak-Efficiency e MOSFET dynamic performance, system inductance, ,  High-Current Handling: 50 A and power MOSFET RDS(ON). XS™ DrMOS uses H  High-Performance PQFN Copper-Clip Package Fteacihrcnhoillod'gsy , hwighhi-cphe rdforarmmaanticcea llyP orewdeurcTeres nscwh®it chM OrinSgFinEgT, igh -  3-State 3.3 V PWM Input Driver eliminating the need for snubber circuit in most buck F r converter applications. e  Skip-Mode SMOD# (Low-Side Gate Turn Off) Input q A driver IC with reduced dead times and propagation u  Thermal Warning Flag for Over-Temperature e delays further enhances the performance. A thermal n Condition warning function warns of a potential over-temperature c y  Driver Output Disable Function (DISB# Pin) situation. The FDMF6820C also incorporates a Skip D Mode (SMOD#) for improved light-load efficiency. The  Internal Pull-Up and Pull-Down for SMOD# and FDMF6820C also provides a 3-state 3.3 V PWM input rM DISB# Inputs, Respectively for compatibility with a wide range of PWM controllers. O  Fairchild PowerTrench® Technology MOSFETs for S Applications M Clean Voltage Waveforms and Reduced Ringing o  Fairchild SyncFET™ (Integrated Schottky Diode)  High-Performance Gaming Motherboards d u Technology in Low-Side MOSFET  Compact Blade Servers, V-Core and Non-V-Core le  Integrated Bootstrap Schottky Diode DC-DC Converters  Adaptive Gate Drive Timing for Shoot-Through  Desktop Computers, V-Core and Non-V-Core Protection DC-DC Converters  Under-Voltage Lockout (UVLO)  Workstations  Optimized for Switching Frequencies up to 1MHz  High-Current DC-DC Point-of-Load Converters  Low-Profile SMD Package  Networking and Telecom Microprocessor Voltage  Fairchild Green Packaging and RoHS Compliance Regulators  Based on the Intel® 4.0 DrMOS Standard  Small Form-Factor Voltage Regulator Modules Ordering Information Part Number Current Rating Package Top Mark FDMF6820C 50 A 40-Lead, Clipbond PQFN DrMOS, 6.0 mm x 6.0 mm Package FDMF6820C © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3

Typical Application Circuit F D M V5V VIN F R 3V ~ 16V 6 VCIN 8 CVDRV CVCIN CVIN 2 0 C — VDRV VCIN VIN E DISB# DISB# RBOOT x t BOOT r PWM a - Input PWM FDMF6820C CBOOT S m OFF PHASE a ON SMOD# ll , Open- VSWH H ODuratpinu t THWN# CGND PGND LOUT COUT VOUT igh-P e r f o r m Figure 1. Typical Application Circuit a n c e , DrMOS Block Diagram H i g h VDRV BOOT VIN - F re VCIN UVLO Q1 q HS Power u DBoot MOSFET e n c y DISB# GH Level-Shift GH D r Logic M 10µA O 30kΩ S V PHASE M CIN o d RUP_PWM Dead-Time u In put Control VSWH le PWM 3-State Logic RDN_PWM VDRV GL GL Logic THWN# VCIN 30kΩ Q2 Temp. LS Power MOSFET Sense 10µA CGND SMOD# PGND Figure 2. DrMOS Block Diagram © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 2

F Pin Configuration D M F 6 8 2 0 C — E x t r a - S m a l l , H i g h - P e r f o r m a n c e , H i Figure 3. Bottom View Figure 4. Top View g h - F Pin Definitions r e q Pin # Name Description u e n When SMOD#=HIGH, the low-side driver is the inverse of the PWM input. When c 1 SMOD# SMOD#=LOW, the low-side driver is disabled. This pin has a 10 µA internal pull-up current y source. Do not add a noise filter capacitor. D r M 2 VCIN IC bias supply. Minimum 1 µF ceramic capacitor is recommended from this pin to CGND. O Power for the gate driver. Minimum 1 µF ceramic capacitor is recommended to be connected S 3 VDRV as close as possible from this pin to CGND. M Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a o 4 BOOT d bootstrap capacitor from this pin to PHASE. u l e 5, 37, 41 CGND IC ground. Ground return for driver IC. 6 GH For manufacturing test only. This pin must float; it must not be connected to any pin. 7 PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin. No connect. The pin is not electrically connected internally, but can be connected to VIN for 8 NC convenience. 9 - 14, 42 VIN Power input. Output stage supply voltage. 15, 29 - Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point VSWH 35, 43 for the adaptive shoot-through protection. 16 – 28 PGND Power ground. Output stage ground. Source pin of the low-side MOSFET. 36 GL For manufacturing test only. This pin must float; it must not be connected to any pin. Thermal warning flag, open collector output. When temperature exceeds the trip limit, the 38 THWN# output is pulled LOW. THWN# does not disable the module. Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are 39 DISB# held LOW). This pin has a 10 µA internal pull-down current source. Do not add a noise filter capacitor. 40 PWM PWM signal input. This pin accepts a three-state 3.3 V PWM signal from the controller. © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 3

Absolute Maximum Ratings F D Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be M operable above the recommended operating conditions and stressing the parts to these levels is not recommended. F 6 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. 8 The absolute maximum ratings are stress ratings only. 2 0 C Symbol Parameter Min. Max. Unit — VCIN Supply Voltage Referenced to CGND -0.3 6.0 V E V Drive Voltage Referenced to CGND -0.3 6.0 V x DRV t r VDISB# Output Disable Referenced to CGND -0.3 6.0 V a - V PWM Signal Input Referenced to CGND -0.3 6.0 V S PWM m VSMOD# Skip Mode Input Referenced to CGND -0.3 6.0 V a l VGL Low Gate Manufacturing Test Pin Referenced to CGND -0.3 6.0 V l, H VTHWN# Thermal Warning Flag Referenced to CGND -0.3 6.0 V ig V Power Input Referenced to PGND, CGND -0.3 25.0 V h IN - P Referenced to VSWH, PHASE -0.3 6.0 V e VBOOT Bootstrap Supply r Referenced to CGND -0.3 25.0 V f o Referenced to VSWH, PHASE -0.3 6.0 V rm V High Gate Manufacturing Test Pin GH Referenced to CGND -0.3 25.0 V a n V PHASE Referenced to CGND -0.3 25.0 V c PHS e Referenced to PGND, CGND (DC Only) -0.3 25.0 V , V Switch Node Input H SWH Referenced to PGND, <20 ns -8.0 28.0 V ig h Referenced to VDRV 22.0 V - V Bootstrap Supply F BOOT Referenced to VDRV, <20 ns 25.0 V r e q I THWN# Sink Current -0.1 7.0 mA THWN# u e f =300 kHz, V =12 V, V =1.0 V 50 I Output Current(1) SW IN O A n O(AV) c f =1 MHz, V =12 V, V =1.0 V 45 SW IN O y θ Junction-to-PCB Thermal Resistance 2.7 °C/W D JPCB r T Ambient Temperature Range -40 +125 °C M A O T Maximum Junction Temperature +150 °C J S T Storage Temperature Range -55 +150 °C M STG o Human Body Model, JESD22-A114 2000 d ESD Electrostatic Discharge Protection V u Charged Device Model, JESD22-C101 2500 l e Note: 1. I is rated using Fairchild’s DrMOS evaluation board, at T = 25°C, with natural convection cooling. This rating O(AV) A is limited by the peak DrMOS temperature, T = 150°C, and varies depending on operating conditions and PCB J layout. This rating can be changed with different application settings. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit V Control Circuit Supply Voltage 4.5 5.0 5.5 V CIN V Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V DRV V Output Stage Supply Voltage 3.0 12.0 16.0(2) V IN Note: 2. Operating at high V can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes IN during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional information. © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 4

Electrical Characteristics F D Typical values are V = 12 V, V = 5 V, V = 5 V, and T = T = +25°C unless otherwise noted. IN CIN DRV A J M Symbol Parameter Condition Min. Typ. Max. Unit F 6 8 Basic Operation 2 0 I Quiescent Current I =I +I , PWM=LOW or HIGH or Float 2 mA C Q Q VCIN VDRV — V UVLO Threshold V Rising 2.9 3.1 3.3 V UVLO CIN V UVLO Hysteresis 0.4 V E UVLO_Hys x PWM Input (VCIN = VDRV = 5 V ±10%) tra RUP_PWM Pull-Up Impedance VPWM=5 V 26 kΩ -S m R Pull-Down Impedance V =0 V 12 kΩ DN_PWM PWM a VIH_PWM PWM High Level Voltage 1.88 2.25 2.61 V ll, H V 3-State Upper Threshold 1.84 2.20 2.56 V TRI_HI i g V 3-State Lower Threshold 0.70 0.95 1.19 V h TRI_LO - P V PWM Low Level Voltage 0.62 0.85 1.13 V IL_PWM e r tD_HOLD-OFF 3-State Shut-Off Time 160 200 ns fo r VHiZ_PWM 3-State Open Voltage 1.40 1.60 1.90 V m t PWM Minimum Off Time 120 ns a PWM-OFF_MIN n c PWM Input (V = V = 5 V ±5%) CIN DRV e , RUP_PWM Pull-Up Impedance VPWM=5 V 26 kΩ H i R Pull-Down Impedance V =0 V 12 kΩ g DN_PWM PWM h VIH_PWM PWM High Level Voltage 2.00 2.25 2.50 V -F r V 3-State Upper Threshold 1.94 2.20 2.46 V e TRI_HI q V 3-State Lower Threshold 0.75 0.95 1.15 V u TRI_LO e V PWM Low Level Voltage 0.66 0.85 1.09 V n IL_PWM c t 3-State Shut-Off Time 160 200 ns y D_HOLD-OFF D VHiZ_PWM 3-State Open Voltage 1.45 1.60 1.80 V rM tPWM-OFF_MIN PWM Minimum Off Time 120 ns O S DISB# Input M VIH_DISB High-Level Input Voltage 2 V o d V Low-Level Input Voltage 0.8 V u IL_DISB l e IPLD Pull-Down Current 10 µA PWM=GND, Delay Between DISB# from t Propagation Delay 25 ns PD_DISBL HIGH to LOW to GL from HIGH to LOW PWM=GND, Delay Between DISB# from t Propagation Delay 25 ns PD_DISBH LOW to HIGH to GL from LOW to HIGH SMOD# Input V High-Level Input Voltage 2 V IH_SMOD V Low-Level Input Voltage 0.8 V IL_SMOD I Pull-Up Current 10 µA PLU PWM=GND, Delay Between SMOD# from t Propagation Delay 10 ns PD_SLGLL HIGH to LOW to GL from HIGH to LOW PWM=GND, Delay Between SMOD# from t Propagation Delay 10 ns PD_SHGLH LOW to HIGH to GL from LOW to HIGH Continued on the following page… © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 5

Electrical Characteristics F D Typical values are V = 12 V, V = 5 V, V = 5 V, and T = T = +25°C unless otherwise noted. IN CIN DRV A J M Symbol Parameter Condition Min. Typ. Max. Unit F 6 8 Thermal Warning Flag 2 0 T Activation Temperature 150 °C C ACT — T Reset Temperature 135 °C RST R Pull-Down Resistance I =5 mA 30 Ω E THWN PLD x 250ns Timeout Circuit tr a SW=0 V, Delay Between GH from HIGH to -S t Timeout Delay 250 ns D_TIMEOUT LOW and GL from LOW to HIGH m a High-Side Driver (fSW = 1000 kHz, IOUT = 30 A, TA = +25°C) ll, H RSOURCE_GH Output Impedance, Sourcing Source Current=100 mA 1 Ω ig R Output Impedance, Sinking Sink Current=100 mA 0.8 Ω h SINK_GH - P tR_GH Rise Time GH=10% to 90% 10 ns e r tF_GH Fall Time GH=90% to 10% 10 ns fo r GL Going LOW to GH Going HIGH, m t LS to HS Deadband Time 15 ns D_DEADON 1.0 V GL to 10% GH a n PWM LOW Propagation PWM Going LOW to GH Going LOW, c tPD_PLGHL Delay VIL_PWM to 90% GH 20 30 ns e, H tPD_PHGHH PDWelaMy H(SIGMHO DPr#o =p0a)g ation PVWM Gotoin 1g0 H%I GGHH t(oS GMHO DG#o i=ng0, HIIGH>, 0 ) 30 ns ig IH_PWM D_LS h - Exiting 3-State Propagation PWM (From 3-State) Going HIGH to GH F tPD_TSGHH Delay Going HIGH, VIH_PWM to 10% GH 30 ns re q Low-Side Driver (f = 1000 kHz, I = 30 A, T = +25°C) u SW OUT A e n RSOURCE_GL Output Impedance, Sourcing Source Current=100 mA 1 Ω c y R Output Impedance, Sinking Sink Current=100 mA 0.5 Ω SINK_GL D tR_GL Rise Time GL=10% to 90% 20 ns rM O t Fall Time GL=90% to 10% 10 ns F_GL S t HS to LS Deadband Time SW Going LOW to GL Going HIGH, 15 ns M D_DEADOFF 2.2 V SW to 10% GL o d t PWM-HIGH Propagation PWM Going HIGH to GL Going LOW, 10 25 ns u PD_PHGLL Delay VIH_PWM to 90% GL le Exiting 3-State Propagation PWM (From 3-State) Going LOW to GL t 20 ns PD_TSGLH Delay Going HIGH, V to 10% GL IL_PWM Boot Diode V Forward-Voltage Drop I =20 mA 0.3 V F F V Breakdown Voltage I =1 mA 22 V R R © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 6

F D M V IH_PWM F 6 8 2 V 0 IL_PWM C PWM — E x GL 90% tra 1.0V -S 10% m a l l , H 90% GH ig to h VSWH 10% 1.2V t -P D_TIMEOUT (2 50ns Timeout) e r f o r m a n c 2.2V e VSWH , H i g h tPD PHGLL tPD PLGHL -F r e q t tD_DEADOFF u D_DEADON e n c y Figure 5. PWM Timing Diagram D r M O S M o d u l e © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 7

Typical Performance Characteristics F D Test Conditions: V =12 V, V =1 V, V =5 V, V =5 V, L =250 nH, T =25°C, and natural convection cooling, IN OUT CIN DRV OUT A M unless otherwise specified. F 6 50 11 8 2 45 10 300kHz VIN= 12V, VDRV& VCIN= 5V, VOUT= 1V 0 500kHz C utput Current, I(A)OUT 2233405050 FSW= 3F00SWkH=z 1000kHz wer Loss, PL(W)MOD 456789 810000k0HkHzz — Extra-Sm O o Module 1105 Module P 23 all, H 5 VIN= 12V, VDRV& VCIN= 5V, VOUT= 1V 1 i g 0 0 h 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 45 -P PCB Temperature, TPCB(°C) Module Output Current, IOUT(A) e r f Figure 6. Safe Operating Area Figure 7. Power Loss vs. Output Current o r m 1.5 1.08 a VIN= 12V, VDRV& VCIN= 5V, VOUT= 1V, IOUT= 30A VDRV& VCIN= 5V, VOUT= 1V, FSW= 300kHz, IOUT= 30A n c 1.4 e malized Module Power Loss 111...123 malized Module Power Loss1111....00000246 , High-Frequen Nor 1.0 Nor cy D 0.9 0.98 r 100 200 300 400 500 600 700 800 900 1000 1100 4 6 8 10 12 14 16 18 M Module Switching Frequency, FSW (kHz) Module Input Voltage, VIN (V) O S Figure 8. Power Loss vs. Switching Frequency Figure 9. Power Loss vs. Input Voltage M 1.15 1.8 o VIN= 12V, VOUT= 1V, FSW= 300kHz, IOUT= 30A 1.7 du l 1.10 e ss ss 1.6 o o er L er L 1.5 w1.05 w Po Po 1.4 e e dul dul 1.3 o1.00 o M M d d 1.2 e e maliz0.95 maliz 1.1 Nor Nor 1.0 VIN= 12V, VDRV& VCIN= 5V, FSW= 300kHz, IOUT= 30A 0.90 0.9 4.0 4.5 5.0 5.5 6.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Driver Supply Voltage, VDRV & VCIN (V) Module Output Voltage, VOUT (V) Figure 10. Power Loss vs. Driver Supply Voltage Figure 11. Power Loss vs. Output Voltage © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 8

Typical Performance Characteristics F D Test Conditions: V =12 V, V =1 V, V =5 V, V =5 V, L =250 nH, T =25°C, and natural convection cooling, M IN OUT CIN DRV OUT A F unless otherwise specified. 6 8 1.01 45 2 VIN= 12V, VDRV& VCIN= 5V, FSW= 300kHz, VOUT= 1V, IOUT= 30A VIN= 12V, VDRV& VCIN= 5V, VOUT= 1V, IOUT= 0A 0C 40 1.00 A) — ss (m 35 o N E er L & ICI 30 x Module Pow00..9989 urrent, IDRV 2205 tra-Sm malized 0.97 Supply C 15 all, H Nor ver 10 ig Dri h 0.96 5 - 200 250 300 350 400 450 500 100 200 300 400 500 600 700 800 900 1000 1100 P Output Inductor, LOUT (nH) Module Switching Frequency, FSW (kHz) er f o Figure 12. Power Loss vs. Output Inductor Figure 13. Driver Supply Current vs. Switching r m Frequency a n 17 1.04 c VIN= 12V, VOUT= 1V, FSW= 300kHz, IOUT= 0A VIN= 12V, VDRV& VCIN= 5V, VOUT= 1V e, 16 1.03 H mA) nt ig & I(DRVCIN1145 pply Curre1.02 FSW= 300kHz h-Fre Current, I13 Driver Su11..0001 quen y 12 d c Driver Suppl1110 Normalize00..9989 FSW= 1000kHz y DrMO 4.0 4.5 5.0 5.5 6.0 0 5 10 15 20 25 30 35 40 45 S Driver Supply Voltage, VDRV & VCIN (V) Module Output Current, IOUT(A) M o Figure 14. Driver Supply Current vs. Driver Supply Figure 15. Driver Supply Current vs. Output Current d Voltage u l e 3.2 3.0 TA= 25°C UVLOUP V(V)CIN 33..01 V(V)PWM 2.5 VIH_PWM e, e, 2.0 VTRI_HI g g Volta 2.9 Volta VHIZ_PWM y d pl ol 1.5 up 2.8 sh S e Driver IC 2.7 UVLODN PWM Thr 1.0 VVTILR_IP_WLOM 2.6 0.5 -55 0 25 55 100 125 150 4.50 4.75 5.00 5.25 5.50 Driver IC Junction Temperature, TJ(oC) Driver IC Supply Voltage, VCIN (V) Figure 16. UVLO Threshold vs. Temperature Figure 17. PWM Threshold vs. Driver Supply Voltage © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 9

Typical Performance Characteristics F D Test Conditions: V =5 V, V =5 V, T =25°C, and natural convection cooling, unless otherwise specified. M CIN DRV A F 6 3.0 2.2 8 VCIN= 5V TA= 25°C 2 old Voltage, V(V)PWM122...505 VVVIHHTI_ZRP_IW_PHWMIM shold Voltage, V(V)SMOD 112...680 VIH_SMOD# 0C — Extra-S WM Thresh 1.0 VTRI_LO MOD# Thre 1.4 VIL_SMOD# mall, P VIL_PWM S H i 0.5 1.2 g h -55 0 25 55 100 125 150 4.50 4.75 5.00 5.25 5.50 - Driver IC Junction Temperature, TJ(oC) Driver IC Supply Voltage, VCIN (V) P e r Figure 18. PWM Threshold vs. Temperature Figure 19. SMOD# Threshold vs. Driver Supply f o Voltage r m 2.2 -9.0 a n VCIN= 5V VCIN= 5V c V) e hold Voltage, V(SMOD 11..682 VIH_SMOD# Up Current, I(uA)PLU--11-009...505 , High-Freq SMOD# Thres 1.4 VIL_SMOD# SMOD# Pull- --1111..50 uency D 1.2 -12.0 rM -55 0 25 55 100 125 150 -55 0 25 55 100 125 150 O Driver IC Junction Temperature, TJ(oC) Driver IC Junction Temperature, TJ(oC) S M Figure 20. SMOD# Threshold vs. Temperature Figure 21. SMOD# Pull-Up Current vs. Temperature o d 2.2 2.2 u TA= 25°C VCIN= 5V le (V) 2.0 VIH_DISB# (V) 2.0 VDISB VDISB VIH_DISB# e, e, g 1.8 g 1.8 Volta Volta d d hol 1.6 hol 1.6 hres VIL_DISB# hres B# T 1.4 B# T 1.4 VIL_DISB# S S DI DI 1.2 1.2 4.50 4.75 5.00 5.25 5.50 -55 0 25 55 100 125 150 Driver IC Supply Voltage, VCIN(V) Driver IC Junction Temperature, TJ(oC) Figure 22. DISB# Threshold vs. Driver Supply Figure 23. DISB# Threshold vs. Temperature Voltage © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 10

Typical Performance Characteristics F D Test Conditions: V =5 V, V =5 V, T =25°C, and natural convection cooling, unless otherwise specified. M CIN DRV A F 6 12.0 500 8 VCIN= 5V IF= 20mA 20 450 C A)11.5 V) nt, I(uPLD11.0 ge, V(mF 345000 — Ex wn Curre10.5 ard Volta 300 tra-S B# Pull-Do109..50 Diode Forw 220500 mall, DIS ot 150 H o i B g 9.0 100 h -55 0 25 55 100 125 150 -55 0 25 55 100 125 150 - P Driver IC Junction Temperature, TJ(oC) Driver IC Junction Temperature, TJ(oC) e r f o r Figure 24. DISB# Pull-Down Current vs. Figure 25. Boot Diode Forward Voltage vs. m Temperature Temperature a n c e , H i g h - F r e q u e n c y D r M O S M o d u l e © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 11

Functional Description F D The FDMF6820C is a driver-plus-FET module optimized Three-State PWM Input M for the synchronous buck converter topology. A single F The FDMF6820C incorporates a three-state 3.3 V PWM 6 PWM input signal is all that is required to properly drive 8 input gate drive design. The three-state gate drive has the high-side and the low-side MOSFETs. Each part is 2 both logic HIGH level and LOW level, along with a 0 capable of driving speeds up to 1 MHz. C three-state shutdown window. When the PWM input VCIN and Disable (DISB#) signal enters and remains within the three-state window — The VCIN pin is monitored by an Under-Voltage Lockout for a defined hold-off time (tD_HOLD-OFF), both GL and GH E are pulled LOW. This enables the gate drive to shut x (UVLO) circuit. When VCIN rises above ~3.1 V, the driver down both high-side and low-side MOSFETs to support tr is enabled. When V falls below ~2.7 V, the driver is a CIN features such as phase shedding, which is common on - disabled (GH, GL=0). The driver can also be disabled by S multi-phase voltage regulators. pulling the DISB# pin LOW (DISB# < V ), which m IL_DISB holds both GL and GH LOW regardless of the PWM Exiting Three-State Condition a l input state. The driver can be enabled by raising the l, When exiting a valid three-state condition, the H DISB# pin voltage HIGH (DISB# > V ). IH_DISB FDMF6820C follows the PWM input command. If the i g Table 1. UVLO and Disable Logic PWM input goes from three-state to LOW, the low-side h MOSFET is turned on. If the PWM input goes from -P UVLO DISB# Driver State three-state to HIGH, the high-side MOSFET is turned e r 0 X Disabled (GH, GL=0) on. This is illustrated in Figure 27. The FDMF6820C fo design allows for short propagation delays when exiting r 1 0 Disabled (GH, GL=0) m the three-state window (see Electrical Characteristics). a 1 1 Enabled (see Table 2) n Low-Side Driver c 1 Open Disabled (GH, GL=0) e The low-side driver (GL) is designed to drive a ground- , Note: referenced, low-R , N-channel MOSFET. The bias H 3. DISB# internal pull-down current source is 10 µA. for GL is internallyDS (cOoNn)nected between the VDRV and ig CGND pins. When the driver is enabled, the driver's h - output is 180° out of phase with the PWM input. When F Thermal Warning Flag (THWN#) r the driver is disabled (DISB#=0 V), GL is held LOW. e The FDMF6820C provides a thermal warning flag q u (THWN#) to warn of over-temperature conditions. The High-Side Driver e thermal warning flag uses an open-drain output that n The high-side driver (GH) is designed to drive a floating c pulls to CGND when the activation temperature (150°C) N-channel MOSFET. The bias voltage for the high-side y is reached. The THWN# output returns to a high- driver is developed by a bootstrap supply circuit D impedance state once the temperature falls to the reset r consisting of the internal Schottky diode and external M temperature (135°C). For use, the THWN# output bootstrap capacitor (CBOOT). During startup, VSWH is held O requires a pull-up resistor, which can be connected to at PGND, allowing C to charge to V through the S BOOT DRV VCIN. THWN# does NOT disable the DrMOS module. internal diode. When the PWM input goes HIGH, GH M begins to charge the gate of the high-side MOSFET (Q1). o 135°C Reset 150°C During this transition, the charge is removed from CBOOT du Temperature Activation and delivered to the gate of Q1. As Q1 turns on, VSWH le HIGH Temperature rises to VIN, forcing the BOOT pin to VIN + VBOOT, which provides sufficient V enhancement for Q1. To complete GS THWN# the switching cycle, Q1 is turned off by pulling GH to Logic State Normal Thermal VSWH. CBOOT is then recharged to VDRV when VSWH falls to Operation Warning PGND. GH output is in-phase with the PWM input. The high-side gate is held LOW when the driver is disabled or LOW the PWM signal is held within the three-state window for longer than the three-state hold-off time, t . D_HOLD-OFF T J_driver IC Figure 26. THWN Operation © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 12

HIGH, Q2 begins to turn off after a propagation delay F Adaptive Gate Drive Circuit (t ). Once the GL pin is discharged below 1.0 V, D PD_PHGLL Q1 begins to turn on after adaptive delay t . M The driver IC advanced design ensures minimum D_DEADON F MOSFET dead-time, while eliminating potential shoot- To preclude overlap during the HIGH-to-LOW transition 6 through (cross-conduction) currents. It senses the state (Q1 off to Q2 on), the adaptive circuitry monitors the 82 of the MOSFETs and adjusts the gate drive adaptively voltage at the GH-to-PHASE pin pair. When the PWM 0 C to ensure they do not conduct simultaneously. Figure 27 signal goes LOW, Q1 begins to turn off after a provides the relevant timing waveforms. To prevent propagation delay (t ). Once the voltage across — PD_PLGHL overlap during the LOW-to-HIGH switching transition GH-to-PHASE falls below 2.2 V, Q2 begins to turn on E (Q2 off to Q1 on), the adaptive circuitry monitors the after adaptive delay t . x voltage at the GL pin. When the PWM signal goes D_DEADOFF tr a - S m VIH_PWM tD_HOLD-OFF VIH_PWM VTRI_HI VIH_PWM VVITHR_IP_WHIM all, H VIL_PWM VTRI_LO i t t VIL_PWM g PWM R_GH F_GH h - P 90% e r GH f to 10% o VSWH r m a VIN n c CCM DCM DCM e , 2.2V VOUT Hi VSWH g h t t - R_GL F_GL F GL r 90% 90% e q 1.0V 10% 10% u e n tPD_PHGLL tPD_PLGHL tPD_TSGHH tD_HOLD-OFF tPD_TSGHH tD_HOLD-OFF tPD_TSGLH cy D t D_DEADON tD_DEADOFF r Enter Exit Enter Exit Enter Exit M 3-state 3-state 3-state 3-state 3-state 3-state O S Notes: M tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal. Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW) o tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH) d u PWM Exiting 3-state l e tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS tPD_TSGHH = PWM 3-state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS tPD_TSGLH = PWM 3-state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW) SMOD# Dead Times tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS tD_DEADON = LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS Figure 27. PWM and 3-StateTiming Diagram © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 13

F Skip Mode (SMOD#) When the SMOD# pin is pulled HIGH, the synchronous D buck converter works in Synchronous Mode. This mode M The Skip Mode function allows for higher converter allows for gating on the Low Side MOSFET. When the F efficiency when operated in light-load conditions. When SMOD# pin is pulled LOW, the low-side MOSFET is 68 SMOD# is pulled LOW, the low-side MOSFET gate gated off. If the SMOD# pin is connected to the PWM 2 signal is disabled (held LOW), preventing discharge of controller, the controller can actively enable or disable 0C the output capacitors as the filter inductor current SMOD# when the controller detects light-load condition — attempts reverse current flow – known as “Diode from output current sensing. Normally this pin is active Emulation” Mode. LOW. See Figure 28 for timing delays. E x t r a - Table 2. SMOD# Logic S m DISB# PWM SMOD# GH GL a l l , 0 X X 0 0 H i 1 3-State X 0 0 g h 1 0 0 0 0 -P e 1 1 0 1 0 r f o 1 0 1 0 1 r m 1 1 1 1 0 a n Note: c 4. The SMOD# feature is intended to have a short propagation delay between the SMOD# signal and the low-side FET V e GS , response time to control diode emulation on a cycle-by-cycle basis. H i g h - F SMOD# r e VIH_SMOD q VIL_SMOD u e VIH_PWM VIH_PWM nc y VIL_PWM D PWM r M 90% O GH to 10% 10% S VSWH M o d u DCM le CCM CCM VOUT 2.2V VSWH GL 90% 1.0V 10% 10% tPD_PHGLL tPD_PLGHL tPD_SLGLL tPD_PHGHH tPD_SHGLH tD_DEADON tD_DEADOFF Delay from SMOD# going Delay from SMOD# going LOW to LS VGSLOW HIGH to LS VGS HIGH HS turn-on with SMOD# LOW Figure 28. SMOD# Timing Diagram © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 14

F Application Information D VCIN Filter M Supply Capacitor Selection F The VDRV pin provides power to the gate drive of the 6 For the supply inputs (VCIN), a local ceramic bypass high-side and low-side power MOSFET. In most cases, 8 capacitor is recommended to reduce noise and to 2 it can be connected directly to VCIN, the pin that 0 supply the peak current. Use at least a 1 µF X7R or X5R C provides power to the logic section of the driver. For capacitor. Keep this capacitor close to the VCIN pin and additional noise immunity, an RC filter can be inserted — connect it to the GND plane with vias. between the VDRV and VCIN pins. Recommended E Bootstrap Circuit values would be 10 Ω and 1 µF. x t r The bootstrap circuit uses a charge storage capacitor Power Loss and Efficiency a - (C ), as shown in Figure 30. A bootstrap capacitance S BOOT Measurement and Calculation m of 100 nF X7R or X5R capacitor is usually adequate. A series bootstrap resistor may be needed for specific Refer to Figure 30 for power loss testing method. a l l applications to improve switching noise immunity. The Power loss calculations are: , H boot resistor may be required when operating above 15 V and is effective at controlling the high-side PIN=(VIN x IIN) + (V5V x I5V) (W) (1) ig IN h MOSFET turn-on slew rate and VSHW overshoot. RBOOT PSW=VSW x IOUT (W) (2) -P values from 0.5 to 3.0 Ω are typically effective in POUT=VOUT x IOUT (W) (3) e reducing VSWH overshoot. r PLOSS_MODULE=PIN - PSW (W) (4) fo r P =P - P (W) (5) m LOSS_BOARD IN OUT a EFFMODULE=100 x PSW/PIN (%) (6) n c EFFBOARD=100 x POUT/PIN (%) (7) e , H i g h - F r e q u e n c y D r M VOUT O S M o d u l e Figure 29. Block Diagram With VCIN Filter Figure 30. Power Loss Measurement © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 15

F PCB Layout Guidelines D M Figure 31 and Figure 32 provide an example of a proper noise issues due to ground bounce or high positive F layout for the FDMF6820C and critical components. All and negative V ringing. Inserting a boot 6 SWH 8 of the high-current paths, such as VIN, VSWH, VOUT, resistance lowers the DrMOS efficiency. Efficiency 2 and GND copper, should be short and wide for low versus noise trade-offs must be considered. R 0 BOOT C inductance and resistance. This aids in achieving a values from 0.5 Ω to 3.0 Ω are typically effective in — more stable and evenly distributed current flow, along reducing V overshoot. SWH with enhanced heat radiation and system performance. E 8. The VIN and PGND pins handle large current x Recommendations for PCB Designers transients with frequency components greater than t r 100 MHz. If possible, these pins should be a 1. Input ceramic bypass capacitors must be placed - connected directly to the VIN and board GND S close to the VIN and PGND pins. This helps reduce m planes. The use of thermal relief traces in series with the high-current power loop inductance and the input a current ripple induced by the power MOSFET these pins is discouraged since this adds inductance ll switching operation. to the power path. This added inductance in series , H with either the VIN or PGND pin degrades system i 2. The VSWH copper trace serves two purposes. In noise immunity by increasing positive and negative g h afrdodmit iothne tDo rMbeOinSg ptahcek ahgieg ht-ofr ethqeu eonuctyp uct uirnrdeunct topra, thit VSWH ringing. -P serves as a heat sink for the low-side MOSFET in 9. GND pad and PGND pins should be connected to er the DrMOS package. The trace should be short and the GND copper plane with multiple vias for stable fo wide enough to present a low-impedance path for grounding. Poor grounding can create a noise rm the high-frequency, high-current flow between the transient offset voltage level between CGND and a DrMOS and inductor. The short and wide trace PGND. This could lead to faulty operation of the gate n minimizes electrical losses as well as the DrMOS driver and MOSFETs. ce temperature rise. Note that the VSWH node is a high- 10. Ringing at the BOOT pin is most effectively , H voltage and high-frequency switching node with high controlled by close placement of the boot capacitor. ig noise potential. Care should be taken to minimize Do not add an additional BOOT to the PGND h coupling to adjacent traces. Since this copper trace - capacitor. This may lead to excess current flow F acts as a heat sink for the lower MOSFET, balance through the BOOT diode. re using the largest area possible to improve DrMOS q cooling while maintaining acceptable noise emission. 11. The SMOD# and DISB# pins have weak internal u e pull-up and pull-down current sources, respectively. 3. An output inductor should be located close to the n These pins should not have any noise filter c FDMF6820C to minimize the power loss due to the y capacitors. Do not to float these pins unless VSWH copper trace. Care should also be taken so the absolutely necessary. D inductor dissipation does not heat the DrMOS. r M 12. Use multiple vias on the VIN and VOUT copper 4. PowerTrench® MOSFETs are used in the output O areas to interconnect top, inner, and bottom layers S stage and are effective at minimizing ringing due to to distribute current flow and heat conduction. Do fast switching. In most cases, no VSWH snubber is M not put many vias on the VSWH copper to avoid required. If a snubber is used, it should be placed o extra parasitic inductance and noise on the d close to the VSWH and PGND pins. The selected u switching waveform. As long as efficiency and resistor and capacitor need to be the proper size for thermal performance are acceptable, place only le power dissipation. one VSWH copper on the top layer and use no vias 5. VCIN, VDRV, and BOOT capacitors should be on the VSWH copper to minimize switch node placed as close as possible to the VCIN-to-CGND, parasitic noise. Vias should be relatively large and VDRV-to-CGND, and BOOT-to-PHASE pin pairs to of reasonably low inductance. Critical high- ensure clean and stable power. Routing width and frequency components, such as RBOOT, CBOOT, RC length should be considered as well. snubber, and bypass capacitors; should be located as close to the respective DrMOS module pins as 6. Include a trace from the PHASE pin to the VSWH pin possible on the top layer of the PCB. If this is not to improve noise margin. Keep this trace as short as feasible, they can be connected from the backside possible. through a network of low-inductance vias. 7. The layout should include the option to insert a small-value series boot resistor between the boot capacitor and BOOT pin. The boot-loop size, including R and C , should be as small as BOOT BOOT possible. The boot resistor may be required when operating above 15 V and is effective at controlling IN the high-side MOSFET turn-on slew rate and V SHW overshoot. R can improve noise operating BOOT margin in synchronous buck designs that may have © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 16

F D M F 6 8 2 0 C — E x t r a - S m a l l , H i g h - P e r f o r m a n c e , H i g Figure 31. PCB Layout Example (Top View) h - F r e q u e n c y D r M O S M o d u l e Figure 32. PCB Layout Example (Bottom View) © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 17

Physical Dimensions F D M F 6 B PIN#1 8 2 0.10 C INDICATOR 0 6.00 2X A 5.80 C — 4.50 30 21 E x 31 t 20 r a 6.00 2.50 0.40 -S m 0.65 a 0.25 ll 1.60 , H 0.10 C 11 2X 40 ig 1 10 h TOP VIEW SEE 0.60 0.35 -P DETAIL 'A' 0.50 TYP 0.15 e r 2.10 f 2.10 o r LAND PATTERN m FRONT VIEW 0.10 C A B RECOMMENDATION a n 4.40±0.10 0.05 C c (2.20) 0.30 e 0.40 21 300.20(40X) , H 31 i g 0.50 20 PIN #1 INDICATOR h (0.70) 2.40±0.10 0.20 MAY APPEAR AS -F OPTIONAL re q 1.50±0.10 0.50 u 0.30 (40X) e 40 n 11 c 0.40 10 1 y 2.00±0.10 2.00±0.10 D (0.20) 0.50 r (0.20) NOTES: UNLESS OTHERWISE SPECIFIED M BOTTOM VIEW O A) DOES NOT FULLY CONFORM TO JEDEC S REGISTRATION MO-220, DATED M 1.10 MAY/2005. 0.90 o B) ALL DIMENSIONS ARE IN MILLIMETERS. d C) DIMENSIONS DO NOT INCLUDE BURRS u 0.10 C OR MOLD FLASH. MOLD FLASH OR le BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 0.08 C 0.30 0.05 E) DRAWING FILE NAME: PQFN40AREV3 0.20 0.00 C SEATING DETAIL 'A' PLANE SCALE: 2:1 Figure 33. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0 mm Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 18

F D M F 6 8 2 0 C — E x t r a - S m a l l , H i g h - P e r f o r m a n c e , H i g h - F r e q u e n c y D r M O S M o d u l e © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6820C • Rev. 1.0.3 19

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