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F D M F 6 April 2013 7 0 5 - E x t FDMF6705 - Extra-Small, High-Performance, High- r a - S Frequency DrMOS Module m a l Benefits Description l H i  Ultra-Compact 6x6 mm PQFN, 72% Space-Saving The XS™ DrMOS family is Fairchild’s next-generation, gh fully optimized, ultra-compact, integrated MOSFET plus Compared to Conventional Discrete Solutions - driver power stage solutions for high-current, high- P  Fully Optimized System Efficiency frequency, synchronous buck DC-DC applications. The er f  Clean Switching Waveforms with Minimal Ringing FanDdM Fa6 70b5o ointstetrgarpa teSsc ah odtrtikvye r IdCio, dtwe o pinotow era M OthSeFrmEaTlsly, orm  High-Current Handling enhanced, ultra-compact 6x6mm PQFN package. a n Features With an integrated approach, the complete switching c e power stage is optimized with regards to driver and ,  Over 93% Peak-Efficiency MOSFET dynamic performance, system inductance, H  High-Current Handling of 40 A, at 12 VIN aFnadir chPilodw'se rh igMh-OpSerFfoErTm aRncDeS( OPN)o. weXrST™re ncDhr®M OMSO SuFsEeTs igh  High-Current Handling of 38 A at 19 VIN technology, which dramatically reduces switch ringing, -F r  High-Performance PQFN Copper-Clip Package eliminating the need for a snubber circuit in most buck e q converter applications.  3-State 5 V PWM Input Driver u e  Skip-Mode SMOD# (Low-Side Gate Turn Off) Input Apr opnaegwa tiodnri vdeerl ayIsC furwthitehr ernehdauncceeds thdee apde rfotimrmeasn cea nodf nc  Thermal Warning Flag for Over-Temperature this part. A thermal warning function has been included y D Condition to warn of a potential over-temperature situation. The r  Driver Output Disable Function (DISB# Pin) FMDoMdeF 6(S70M5O Dal)s,o f oirn cimorpproorvaetde sl igfehat-tluoraeds ,e fsfiucciehn cays aSloknipg MO  Internal Pull-Up and Pull-Down for SMOD# and with a 3-state PWM input for compatibility with a wide S DISB# Inputs, Respectively range of PWM controllers. M o  Fairchild PowerTrench® Technology MOSFETs for Applications d Clean Voltage Waveforms and Reduced Ringing u l e  Fairchild SyncFET™ (Integrated Schottky Diode)  High-Performance Gaming Motherboards Technology in the Low-Side MOSFET  Notebook Computer V-Core and Non-V-Core  Integrated Bootstrap Schottky Diode  Compact Blade Server, V-Core and Non-V-Core  Adaptive Gate Drive Timing for Shoot-through DC-DC Converters Protection  Desktop Computer, V-Core and Non-V-Core  Under-Voltage Lockout (UVLO) DC-DC Converters  Optimized for Switching Frequencies up to 1 MHz  Workstations  Low-Profile SMD Package  High-Current DC-DC Point-of-Load (POL)  Fairchild Green Packaging and RoHS Compliant Converters  Based on the Intel® 4.0 DrMOS Standard  Small Form-Factor Voltage Regulator Modules Ordering Information Part Number Current Rating Package Top Mark FDMF6705 40 A 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0 mm Package FDMF6705 © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4

F D Typical Application Circuit M F 6 7 0 5 - E x t r a - S m a l l H i g h - P e r f o r m a n c e , Figure 1. Typical Application Circuit H i g DrMOS Block Diagram h - F r e q u e n c y D r M O S M o d u l e Figure 2. DrMOS Block Diagram © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 2

F Pin Configuration D M F 6 7 0 5 - E x t r a - S m a l l H i g h - P e r f o r m a n c e , H i g h - F r e Figure 3. Bottom View Figure 4. Top View q u e Pin Definitions n c y Pin # Name Description D r When SMOD#=HIGH, the low-side driver is the inverse of PWM input. When SMOD#=LOW, M 1 SMOD# the low-side driver is disabled. This pin has a 10 µA internal pull-up current source. Do not add O S a noise filter capacitor. M 2 VCIN IC bias supply. Minimum 1 µF ceramic capacitor is recommended from this pin to CGND. o d 3 VDRV Power for gate driver. Minimum 1 µF ceramic capacitor is recommended to be connected as u close as possible from this pin to CGND. le Bootstrap supply input. Provides voltage supply to high-side MOSFET driver. Connect 4 BOOT bootstrap capacitor from this pin to PHASE. 5, 37, 41 CGND IC ground. Ground return for driver IC. 6 GH For manufacturing test only. This pin must float. Must not be connected to any pin. 7 PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin. No connect. The pin is not electrically connected internally, but can be connected to VIN for 8 NC convenience. 9 - 14, 42 VIN Power input. Output stage supply voltage. 15, 29 - Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point VSWH 35, 43 for the adaptive shoot-through protection. 16 – 28 PGND Power ground. Output stage ground. Source pin of low-side MOSFET. 36 GL For manufacturing test only. This pin must float. Must not be connected to any pin. Thermal warning flag, open collector output. When temperature exceeds the trip limit, the 38 THWN# output is pulled LOW. THWN# does not disable the module. Output disable. When LOW, this pin disables Power MOSFET switching (GH and GL are held 39 DISB# LOW). This pin has a 10 µA internal pull-down current source. Do not add a noise filter capacitor. 40 PWM PWM signal input. This pin accepts a 3-state logic-level PWM signal from the controller. © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 3

F D Absolute Maximum Ratings M F Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be 6 7 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 0 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. 5 - The absolute maximum ratings are stress ratings only. E x Symbol Parameter Min. Max. Unit tr a VCIN, VDRV, DISB#, PWM, SMOD#, GL, THWN# to CGND Pins -0.3 6.0 -S m VIN to PGND, CGND Pins -0.3 30.0 a l BOOT, GH to VSWH, PHASE Pins -0.3 6.0 l H BOOT, PHASE, GH to CGND Pins -0.3 30.0 i g V h VSWH to CGND/PGND (DC Only) -0.3 30.0 - P VSWH to PGND (<20 ns) -8.0 33.0 e r BOOT to VDRV 22.0 fo r BOOT to VDRV (<20 ns) 25.0 m a ITHWN# THWN# Sink Current -0.1 7.0 mA n c f =300 kHz 38 e IO(AV)(1) VIN=19 V, VO=1.0 V fSW=1 MHz 35 A , H SW i g θ Junction-to-PCB Thermal Resistance 3.5 °C/W JPCB h - T Ambient Temperature Range -40 +125 °C F A r e T Maximum Junction Temperature +150 °C J q u T Storage Temperature Range -55 +150 °C STG e n Human Body Model, JESD22-A114 2000 c ESD Electrostatic Discharge Protection V y Charged Device Model, JESD22-C101 1000 D r Note: M 1. I is rated using Fairchild’s DrMOS evaluation board, T = 25°C, natural convection cooling. This rating is limited O O(AV) A by the peak DrMOS temperature, T = 150°C, and varies depending on operating conditions and PCB layout. This S J rating can be changed with different application settings. M o Recommended Operating Conditions d u l The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended e operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit V Control Circuit Supply Voltage 4.5 5.0 5.5 V CIN V Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V DRV V Output Stage Supply Voltage 3.0 12.0 24.0(2) V IN Note: 2. Operating at high V can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes IN during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional information. © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 4

F D Electrical Characteristics M F Typical values are V = 12 V, V = 5 V, V = 5 V, and T = +25°C unless otherwise noted. 6 IN CIN DRV A 7 0 Symbol Parameter Condition Min. Typ. Max. Unit 5 - Basic Operation E x IQ Quiescent Current IQ=IVCIN+IVDRV, PWM=LOW or HIGH or Float 2 mA tr a UVLO UVLO Threshold VCIN Rising 2.9 3.1 3.3 V -S m UVLO UVLO Hysteresis 0.4 V _Hyst a PWM Input (VCIN = VDRV = 5 V ±10%) ll H RUP_PWM Pull-Up Impedance 10 kΩ ig R Pull-Down Impedance 10 kΩ h DN_PWM - P VIH_PWM PWM High Level Voltage 3.04 3.55 4.05 V e r VTRI_HI 3-State Upper Threshold 2.95 3.45 3.94 V fo r V 3-State Lower Threshold 0.98 1.25 1.52 V m TRI_LO a VIL_PWM PWM Low Level Voltage 0.84 1.15 1.42 V n c tD_HOLD-OFF 3-State Shutoff Time 160 200 ns e , V 3-State Open Voltage 2.2 2.5 2.8 V H HiZ_PWM i g PWM Input (V = V = 5 V ±5%) CIN DRV h - R Pull-Up Impedance 10 kΩ F UP_PWM r R Pull-Down Impedance 10 kΩ e DN_PWM q u V PWM High Level Voltage 3.22 3.55 3.87 V IH_PWM e n V 3-State Upper Threshold 3.13 3.45 3.77 V TRI_HI c y VTRI_LO 3-State Lower Threshold 1.04 1.25 1.46 V D V PWM Low Level Voltage 0.90 1.15 1.36 V r IL_PWM M t 3-State Shutoff Time 160 200 ns O D_HOLD-OFF S VHiZ_PWM 3-State Open Voltage 2.3 2.5 2.7 V M DISB# Input o d V High-Level Input Voltage 2 V u IH_DISB l e VIL_DISB Low-Level Input Voltage 0.8 V I Pull-Down Current 10 µA PLD PWM=GND, Delay Between DISB# from t Propagation Delay 25 ns PD_DISBL HIGH to LOW to GL from HIGH to LOW PWM=GND, Delay Between DISB# from t Propagation Delay 25 ns PD_DISBH LOW to HIGH to GL from LOW to HIGH SMOD# Input V High-Level Input Voltage 2 V IH_SMOD V Low-Level Input Voltage 0.8 V IL_SMOD I Pull-Up Current 10 µA PLU PWM=GND, Delay Between SMOD# from t Propagation Delay 10 ns PD_SLGLL HIGH to LOW to GL from HIGH to LOW PWM=GND, Delay Between SMOD# from t Propagation Delay 10 ns PD_SHGLH LOW to HIGH to GL from LOW to HIGH Continued on the following page… © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 5

F D Electrical Characteristics M F Typical values are V = 12 V, V = 5 V, V = 5 V, and T = +25°C unless otherwise noted. 6 IN CIN DRV A 7 0 Symbol Parameter Condition Min. Typ. Max. Unit 5 - Thermal Warning Flag E x TACT Activation Temperature 150 °C tr a TRST Reset Temperature 135 °C -S m R Pull-Down Resistance I =5 mA 30 Ω THWN PLD a 250 ns Timeout Circuit ll H SW=0 V, Delay Between GH from HIGH to i t Timeout Delay 250 ns g D_TIMEOUT LOW and GL from LOW to HIGH h - High-Side Driver P e R Output Impedance, Sourcing Source Current=100 mA 1 Ω r SOURCE_GH f o R Output Impedance, Sinking Sink Current=100 mA 0.8 Ω r SINK_GH m t Rise Time GH=10% to 90%, C =1.1 nF 6 ns a R_GH LOAD n t Fall Time GH=90% to 10%, C =1.1 nF 5 ns c F_GH LOAD e GL going LOW to GH going HIGH, , t LS to HS Deadband Time 10 ns H D_DEADON 1 V GL to 10% GH i g PWM LOW Propagation PWM going LOW to GH going LOW, h tPD_PLGHL Delay V to 90% GH 16 30 ns -F IL_PWM r PWM HIGH Propagation PWM going HIGH to GH going HIGH, e t 30 ns q PD_PHGHH Delay (SMOD Held LOW) VIH_PWM to 10% GH (SMOD=LOW) u e Exiting 3-State Propagation PWM (from 3-State) going HIGH to GH n tPD_TSGHH Delay going HIGH, V to 10% GH 30 ns c IH_PWM y Low-Side Driver D r R Output Impedance, Sourcing Source Current=100 mA 1 Ω M SOURCE_GL O RSINK_GL Output Impedance, Sinking Sink Current=100 mA 0.5 Ω S t Rise Time GL=10% to 90%, C =2.7 nF 10 ns M R_GL LOAD o tF_GL Fall Time GL=90% to 10%, CLOAD=2.7 nF 8 ns d u SW going LOW to GL going HIGH, l t HS to LS Deadband Time 12 ns e D_DEADOFF 2.2 V SW to 10% GL PWM-HIGH Propagation PWM going HIGH to GL going LOW, t 9 25 ns PD_PHGLL Delay V to 90% GL IH_PWM Exiting 3-State Propagation PWM (from 3-State) going LOW to GL t 20 ns PD_TSGLH Delay going HIGH, V to 10% GL IL_PWM Boot Diode V Forward-Voltage Drop I =10 mA 0.35 V F F V Breakdown Voltage I =1 mA 22 V R R © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 6

F D M V F IH_PWM 6 7 0 5 VIL_PWM - PWM E x t r a - S GL 90% m a 1.0V l 10% l H i g h 90% - P GH e r to f 10% 1.2V o VSWH t (2 50nD_sT IMTEiOmUeT out) rm a n c e , H 2.2V ig VSWH h - F r e t t q PD PHGLL PD PLGHL u e n c t D_DEADON tD_DEADOFF y D r M Figure 5. PWM Timing Diagram O S M o d u l e © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 7

F Typical Performance Characteristics D M F Test Conditions: V =12 V, V =1.0 V, V =5 V, V =5 V, L =320 nH, T =25°C, and natural convection cooling, IN OUT CIN DRV OUT A 6 unless otherwise specified. 7 0 5 45 11 - 10 300kHz VIN= 12V, VOUT= 1V E 40 (A) 35 W) 9 500kHZ xtr nt, IOUT 30 fSW= 300kHz Loss ( 78 810M0HkzHz a-Sm put curre 2205 fSW= 1MHz e Power 456 all H Out 15 dul 3 ig e 10 Mo h Modul 5 VΘIJNP=CB 1=2 V3,. 5V°OCU/TW= 1.0V 12 -Per 0 0 fo 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 r m PCB Temperature (°C) Output Current, I (A) OUT a n c Figure 6. Safe Operating Area Figure 7. Module Power Loss vs. Output Current e , H 12 9 i 11 300kHz VIN= 19V, VOUT= 1V Vin = 19V, Iout = 30A gh 8 wer Loss (W)106789 58100M00HkkzHHzz wer Loss (W)567 VVViiinnn === 111292VVV,,, IIIooouuuttt === 322000AAA -Frequen o o c ule P 45 ule P4 y D Mod 3 Mod3 rM 2 2 O 1 S 0 1 M 0 5 10 15 20 25 30 35 40 200 300 400 500 600 700 800 900 100 o Output Current, IOUT(A) Module Switching Frequency, fSW(kHz) du l e Figure 8. Module Power Loss vs. Output Current Figure 9. Module Power Loss vs. Switching Frequency 1.20 1.15 s IOUT= 30A, fSW= 300kHz s VIN= 12V, IOUT= 30A, fSW= 300kHz s s o o L1.15 L1.10 er er w w o o e P1.10 e P1.05 ul ul d d o o malized M11..0005 malized M01..9050 Nor Nor 0.90 0.95 4.50 4.75 5.00 5.25 5.50 4 6 8 10 12 14 16 18 2 Driver Supply Voltage, V and V (V) Module Input Voltage, V (V) DRV CIN IN Figure 10. Normalized Power Loss vs. Input Figure 11. Normalized Power Loss vs. Driver Voltage Supply Voltage © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 8

F Typical Performance Characteristics (Continued) D M F Test Conditions: V =12 V, V =1.0 V, V =5 V, V =5 V, L =320 nH, T =25°C, and natural convection cooling, IN OUT CIN DRV OUT A 6 unless otherwise specified. 7 0 5 1.9 1.05 - oss VIN= 12V, IOUT= 30A, fSW= 300kHz oss1.04 VIN= 12V, IOUT= 30A, fSW= 300kHz Ex L1.7 L t ower ower 1.03 ra-S e P1.5 e P1.02 m dul dul a d Mo1.3 d Mo1.01 ll H e e maliz1.1 maliz1.00 igh or or0.99 -P N N e 0.9 0.98 r f 0.5 1.0 1.5 2.0 2.5 3.0 3.5 225 275 325 375 425 o r Output Voltage, VOUT(V) Output Inductance, LOUT(nH) m a n Figure 12. Normalized Power Loss vs. Output Figure 13. Module Power Loss vs. Output c Voltage Inductance e , H + I(mA)VCIN 233604 VIN= 12V, IOUT= 0A, fSW= 300kHz + I(mA) VCIN12 VIN= 12V, IOUT= 0A, fSW= 300kHz igh-Fre Current, IVDRV 1282 Current, IVDRV11 quency ply 14 ply 10 D up up r S S M Driver 106 Driver 9 OS 200 400 600 800 1000 4.5 4.75 5 5.25 5.5 M Module Switching Frequency, fSW(kHz) Driver Supply Voltage, VDRV& VCIN(V) od u l Figure 14. Driver Supply Current vs. Frequency Figure 15. Driver Supply Current vs. Driver e Supply Voltage 1.10 4.0 Current 1.08 310M0HkzHz e (V) 3.5 TA= 25°C VIH_PWM VTRI_HI pply 1.06 oltag 3.0 VHIZ_PWM u V 2.5 ver S 1.04 hold 2.0 zed Dri 1.02 M Thres 1.5 VTRI_LO mali 1.00 PW 1.0 VIL_PWM or N 0.98 0.5 0 5 10 15 20 25 30 35 40 4.50 4.75 5.00 5.25 5.50 Module Output Current, IOUT(A) Driver Supply Voltage, VDRV& VCIN(V) Figure 16. Normalized Driver Supply Current vs. Figure 17. PWM Thresholds vs. Driver Supply Output Current Voltage © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 9

F Typical Performance Characteristics (Continued) D M F Test Conditions: V =12 V, V =1.0 V, V =5 V, V =5 V, L =320 nH, T =25°C, and natural convection cooling, IN OUT CIN DRV OUT A 6 unless otherwise specified. 7 0 5 - 4.0 2.2 E VCIN= 5V VIH_PWM TA= 25°C x WM Threshold Voltage ( V)12233.....50505 VTRI_HI VTRI_LO D# Threshold Voltage (V)1112....4680 VIH_SMOD VIL_SMOD tra-Small High-P P01..50 VIL_PWM SMO1.2 erfo -50 -25 0 25 50 75 100 125 150 4.50 4.75 5.00 5.25 5.50 rm Driver Supply Voltage, V (V) Driver IC Junction Temperature, TJ(°C) CIN a n Figure 18. PWM Thresholds vs. Temperature Figure 19. SMOD# Thresholds vs. Driver Supply c e Voltage , H i g 2.0 -9.0 h eshold Voltage (V)1111....6789 VCIN= 5V VIH_SMOD up Current, I(uA)PLU--11-009...505 VCIN= 5V -Frequency D D# Thr1.5 VIL_SMOD # Pull- -11.0 rMO MO1.4 OD -11.5 S S M S M 1.3 -12.0 o -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 d u Driver IC Junction Temperature, TJ(°C) Driver IC Junction Temperature, TJ(oC) le Figure 20. SMOD# Thresholds vs. Temperature Figure 21. SMOD# Pull-Up Current vs. Temperature 2.1 2.00 TA= 25oC VCIN = 5V # Threshold Voltage (V) 111112......567890 VVIHIL__DDIISSBB B Threshold Voltage (V)1111....67890000 VVIIHL__DDIISSBB B S DIS 1.4 DI1.50 1.3 1.40 4.50 4.75 5.00 5.25 5.50 -50 -25 0 25 50 75 100 125 150 Driver Supply Voltage, V (V) Driver IC Junction Temperature, T (°C) CIN J Figure 22. DISB# Thresholds vs. Driver Supply Figure 23. DISB# Thresholds vs. Temperature Voltage © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 10

F Typical Performance Characteristics (Continued) D M F Test Conditions: V =12 V, V =1.0 V, V =5 V, V =5 V, L =320 nH, T =25°C, and natural convection cooling, IN OUT CIN DRV OUT A 6 unless otherwise specified. 7 0 5 11.5 - A) VCIN= 5V E (u x D t L 11.0 r nt, IP a-S e I Curr 10.5 PLD ma n l w l o H D ull- 10.0 ig P h # - B P S DI 9.5 er -50 -25 0 25 50 75 100 125 150 fo Driver IC Junction Temperature, T (°C) r J m a Figure 24. DISB# Pull-Down Current vs. Temperature n c e , H i g h - F r e q u e n c y D r M O S M o d u l e © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 11

F Functional Description D M F The FDMF6705 is a driver-plus-FET module optimized 3-State PWM Input 6 for the synchronous buck converter topology. A single 7 The FDMF6705 incorporates a 3-state PWM input gate 0 PWM input signal is all that is required to properly drive drive design. The 3-state gate drive has both logic HIGH 5 the high-side and the low-side MOSFETs. Each part is level and LOW level, along with a 3-state shutdown - capable of driving speeds up to 1 MHz. E window. When the PWM input signal enters and x VCIN and Disable remains within the 3-state window for a defined hold-off tr time (t ), both GL and GH are pulled LOW. This a The VCIN pin is monitored by an under-voltage lockout featureD _eHnOaLDb-OleFsF the gate drive to shut down both high- -S (UVLO) circuit. When V rises above ~3.1 V, the driver m CIN and low-side MOSFETs to support features such as is enabled for operation. When V falls below ~2.7 V, a CIN phase shedding, which is a common feature on l the driver is disabled (GH, GL=0). The driver can also l multiphase voltage regulators. H be disabled by pulling the DISB# pin LOW (DISB# < i VIL_DISB), which holds both GL and GH LOW regardless Operation when Exiting 3-State Condition gh of the PWM input state. The driver can be enabled by - When exiting a valid 3-state condition, the FDMF6705 P raising the DISB# pin voltage HIGH (DISB# > V ). IH_DISB design follows the PWM input command. If the PWM e r input goes from 3-state to LOW, the low side MOSFET f o Table 1. UVLO and Disable Logic is turned on. If the PWM input goes from 3-state to r m HIGH, the high-side MOSFET is turned on. This is a UVLO DISB# Driver State illustrated in Figure 26. The FDMF6705 design allows n for short propagation delays when exiting the 3-state c 0 X Disabled (GH, GL=0) e window (see Electrical Characteristics). , 1 0 Disabled (GH, GL=0) H Low-Side Driver i g 1 1 Enabled (See Table 2) h The low-side driver (GL) is designed to drive a ground- - 1 Open Disabled (GH, GL=0) F referenced low R N-channel MOSFET. The bias DS(ON) r Note: for GL is internally connected between VDRV and e q 3. DISB# has an internal pull-down current source of CGND. When the driver is enabled, the driver's output is u 10 µA. 180° out of phase with the PWM input. When the driver e n is disabled (DISB#=0 V), GL is held LOW. c Thermal Warning Flag y High-Side Driver D The FDMF6705 provides a thermal warning flag r (THWN) to warn of over-temperature conditions. The The high-side driver is designed to drive a floating N- M thermal warning flag uses an open-drain output that channel MOSFET. The bias voltage for the high-side O pulls to CGND when the activation temperature (150°C) driver is developed by a bootstrap supply circuit, S is reached. The THWN output returns to a high- consisting of the internal Schottky diode and external M impedance state once the temperature falls to the reset bootstrap capacitor (CBOOT). During startup, VSWH is o d temperature (135°C). For use, the THWN output held at PGND, allowing CBOOT to charge to VDRV u requires a pull-up resistor, which can be connected to through the internal diode. When the PWM input goes l e VCIN. THWN does NOT disable the DrMOS module. HIGH, GH begins to charge the gate of the high-side MOSFET (Q1). During this transition, the charge is 135°C 150°C removed from CBOOT and delivered to the gate of Q1. As Reset Activation Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to HIGH Temperature VIN + VBOOT, which provides sufficient VGS enhancement THWN for Q1. To complete the switching cycle, Q1 is turned off by pulling GH to VSWH. C is then recharged to Logic BOOT State Normal Thermal VDRV when VSWH falls to PGND. GH output is in- Operation Warning phase with the PWM input. The high-side gate is held LOW when the driver is disabled or the PWM signal is LOW held within the 3-state window for longer than the 3- state hold-off time, t . D_HOLD-OFF TJ_driverIC Figure 25. THWN Operation © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 12

F Adaptive Gate Drive Circuit D M The driver IC advanced design ensures minimum transition (Q1 off to Q2 on), the adaptive circuitry F MOSFET dead-time while eliminating potential shoot monitors the voltage at the VSWH pin. When the PWM 6 7 through (cross-conduction) currents. It senses the state signal goes LOW, Q1 begins to turn off after some 0 of the MOSFETs and adjusts the gate drive adaptively propagation delay (t ). Once the VSWH pin falls 5 PD_PLGHL - to ensure they do not conduct simultaneously. Figure 26 below ~2.2 V, Q2 begins to turn on after adaptive delay E provides the relevant timing waveforms. To prevent tD_DEADOFF. Additionally, VGS(Q1) is monitored. When x overlap during the LOW-to-HIGH switching transition VGS(Q1) is discharged below ~1.2 V, a secondary tr a (Q2 off to Q1 on), the adaptive circuitry monitors the adaptive delay is initiated, which results in Q2 being - S voltage at the GL pin. When the PWM signal goes driven on after t , regardless of SW state. This D_TIMEOUT m HIGH, Q2 begins to turn off after some propagation function is implemented to ensure C is recharged BOOT a delay (tPD_PHGLL). Once the GL pin is discharged below each switching cycle in the event that the SW voltage ll ~1 V, Q1 begins to turn on after adaptive delay does not fall below the 2.2 V adaptive threshold. H tD_DEADON. To preclude overlap during the HIGH-to-LOW Secondary delay tD_TIMEOUT is longer than tD_DEADOFF. ig h - P e r f VIH_PWM VIH_PWM VTRI_HI VIH_PWM VIHPWM or VTRI_HI m VIL_PWM VTRI_LO an t t VIL_PWM c R_GH F_GH PWM e , H less th a n tD_HOLD-OFF 90 % i GH tD_HOLD-OFF g to 10% h VSWH - F r e VIN q u CCM DCM DCM e n VSWH 2.2V VOUT cy D r M GL 90% 90% O S 1.0V 10% 10% M t PD_PHGLL t PD_PLGHL tR_GL t F_GL tPD_TSGHH tD_HOLD-OFF tPD_TSGHH less th a n t D_HOLD-OFF tPD_TSGLH od tD_HOLD-OFF u l t D_DEADON t D_DEADOFF En ter Exit Enter Exit E nter Exit e 3-State 3-State 3-State 3 State 3-State 3-State Notes: tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal. Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW) tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH) PWM Exiting 3-state tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS tPD_TSGHH = PWM 3-state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS tPD_TSGLH = PWM 3-state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW) SMOD# Dead Times tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS tD_DEADON = LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS Figure 26. PWM and 3-StateTiming Diagram © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 13

F D M Skip Mode (SMOD) F 6 The SMOD function allows for higher converter Table 2. SMOD Logic 7 0 efficiency under light-load conditions. During SMOD, the 5 low-side FET gate signal is disabled (held LOW), DISB# PWM SMOD# GH GL - preventing discharging of the output capacitors as the E 0 X X 0 0 filter inductor current attempts reverse current flow – x t also known as “Diode Emulation” Mode. When the 1 3-State X 0 0 ra SMOD pin is pulled HIGH, the synchronous buck 1 0 0 0 0 -S converter works in Synchronous Mode, gating on the m 1 1 0 1 0 low-side FET. When the SMOD pin is pulled LOW, the a l low-side FET is gated off. The SMOD pin is connected 1 0 1 0 1 l H to the PWM controller, which enables or disables the SMOD automatically when the controller detects light- 1 1 1 1 0 ig h load condition from output current sensing. Normally this Note: - P pin is active LOW. See Figure 27 for timing delays. 4. The SMOD feature is intended to have low e propagation delay between the SMOD signal and r f the low-side FET V response time to control o GS r diode emulation on a cycle-by-cycle basis. m a n c e , SMOD# H i VIH_SMOD g VIL_SMOD h - F VIH_PWM VIH_PWM re q VIL_PWM u PWM e n 90% c y GH to 10% 10% D VSWH r M O S DCM M CCM CCM VOUT o 2.2V VSWH d u l e GL 90% 1.0V 10% 10% tPD_PHGLL tPD_PLGHL tPD_SLGLL tPD_PHGHH tPD_SHGLH tD_DEADON tD_DEADOFF Delay from SMOD# going Delay from SMOD# going LOW to LS VGSLOW HIGH to LS VGS HIGH HS turn-on with SMOD# LOW Figure 27. SMOD Timing Diagram © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 14

F Application Information D M F Supply Capacitor Selection VCIN Filter 6 7 For the supply inputs (VDRV & VCIN), a local ceramic The VDRV pin provides power to the gate drive of the 0 bypass capacitor is required to reduce noise and to high-side and low-side power MOSFETs. In most cases, 5 supply peak transient currents during gate drive VDRV can be connected directly to VCIN, which - E switching action. It is recommended to use a minimum supplies power to the logic circuitry of the gate driver. x capacitor value of 1 µF X7R or X5R. Keep this capacitor For additional noise immunity, an RC filter can be tr close to the VCIN and VDRV pins and connect it to the inserted between VDRV and VCIN. Recommended a - GND plane with vias. values of 10 Ω (R ) placed between VDRV and VCIN S VCIN m and 1 µF (C ) from VCIN to CGND (see Figure 29). Bootstrap Circuit VCIN a l The bootstrap circuit uses a charge storage capacitor Power Loss and Efficiency l H (CBOOT), as shown in Figure 28. A bootstrap capacitance Measurement and Calculation ig of 100 nF X7R or X5R capacitor is typically adequate. A Refer to Figure 28 for power loss testing method. h - series bootstrap resistor would be needed for specific P applications to improve switching noise immunity. The Power loss calculations are: e r boot resistor (R ) may be required when operating f BOOT P =(V x I ) + (V x I ) (W) (1) o IN IN IN 5V 5V near the maximum rated V and is effective at controlling r the high-side MOSFET tINurn-on slew rate and VSHW PSW=VSW x IOUT (W) (2) ma overshoot. Typical RBOOT values from 0.5 Ω to 3.0 Ω are POUT=VOUT x IOUT (W) (3) n effective in reducing V overshoot for the FDMF6705. c SWH P =P - P (W) (4) e LOSS_MODULE IN SW , P =P - P (W) (5) H LOSS_BOARD IN OUT i g EFF =100 x P /P (%) (6) MODULE SW IN h - EFFBOARD=100 x POUT/PIN (%) (7) F r e q u e n c y D r M O S M o d u l e Figure 28. Power Loss Measurement Block Diagram Figure 29. Block Diagram with V Filter CIN © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 15

F PCB Layout Guidelines D M F Figure 30 provides an example of a proper layout for the the boot capacitor (C ) and DrMOS BOOT pin. BOOT 6 FDMF6705 and critical components. All of the high- The BOOT-to-VSWH loop size, including R 7 BOOT 0 current paths, such as V , V , V , and GND and C , should be as small as possible. The IN SWH OUT BOOT 5 copper, should be short and wide for low inductance boot resistor may be required when operating near - and resistance. This technique aids in achieving a more the maximum rated V . The boot resistor is E IN stable and evenly distributed current flow, along with effective at controlling the high-side MOSFET turn- x t enhanced heat radiation and system performance. on slew rate and VSHW overshoot. RBOOT can ra improve noise operating margin in synchronous -S The following guidelines are recommendations for the buck designs that may have noise issues due to m PCB designer: ground bounce or high positive and negative a 1. Input ceramic bypass capacitors must be placed VSWH ringing. However, inserting a boot ll H close to the VIN and PGND pins. This helps resistance lowers the DrMOS efficiency. Efficiency i reduce the high-current power loop inductance versus noise trade-offs must be considered. RBOOT gh and the input current ripple induced by the power values from 0.5 Ω to 3.0 Ω are typically effective in - P MOSFET switching operation. reducing VSWH overshoot for the FDMF6705. e r 2. The VSWH copper trace serves two purposes. In The VIN and PGND pins handle large current fo addition to being the high-frequency current path transients with frequency components greater than r m from the DrMOS package to the output inductor, it 100MHz. If possible, these pins should be a also serves as a heat sink for the low-side connected directly to the VIN and board GND n MOSFET in the DrMOS package. The trace planes. The use of thermal relief traces in series c e should be short and wide enough to present a low- with these pins is discouraged since this adds , impedance path for the high-frequency, high- inductance to the power path. This added H i current flow between the DrMOS and inductor to inductance in series with either the VIN or PGND g h minimize losses and temperature rise. Note that pin degrades system noise immunity by increasing - the VSWH node is a high voltage and high- positive and negative VSWH ringing. F r frequency switching node with high noise e 8. CGND pad and PGND pins should be connected to q potential. Care should be taken to minimize u the GND plane copper with multiple vias for stable coupling to adjacent traces. Since this copper e grounding. Poor grounding can create a noise n trace also acts as a heat sink for the lower FET, transient offset voltage level between CGND and c balance using the largest area possible to improve y PGND. This could lead to faulty operation of the DrMOS cooling while maintaining acceptable D gate driver and MOSFETs. r noise emission. M 9. Ringing at the BOOT pin is most effectively O 3. An output inductor should be located close to the controlled by close placement of the boot S FDMF6705 to minimize the power loss due to the capacitor. Do not add an additional BOOT to the M VSWH copper trace. Care should also be taken so PGND capacitor. This may lead to excess current o the inductor dissipation does not heat the DrMOS. flow through the BOOT diode. d u 4. PowerTrench® MOSFETs are used in the output l 10. The SMOD# and DISB# pins have weak internal e stage. The Power MOSFETs are effective at pull-up and pull-down current sources, minimizing ringing due to fast switching. In most respectively. These pins should not have any cases, no VSWH snubber is required. If a snubber noise filter capacitors. Do not to float these pins is used, it should be placed close to the VSWH and unless absolutely necessary. PGND pins. The resistor and capacitor need to be of proper size for the power dissipation. 11. Use multiple vias on each copper area to interconnect top, inner, and bottom layers to help 5. VCIN, VDRV, and BOOT capacitors should be distribute current flow and heat conduction. Vias placed as close as possible to the VCIN to CGND, should be relatively large and of reasonably low VDRV to CGND, and BOOT to PHASE pins to inductance. Critical high-frequency components, ensure clean and stable power. Routing width and such as R , C , the RC snubber, and length should be considered as well. BOOT BOOT bypass capacitors should be located as close to 6. Include a trace from PHASE to VSWH to improve the respective DrMOS module pins as possible noise margin. Keep the trace as short as possible. on the top layer of the PCB. If this is not feasible, they should be connected from the backside 7. The layout should include a placeholder to insert a through a network of low-inductance vias. small-value series boot resistor (R ) between BOOT © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 16

F D M F 6 7 0 5 - E x t r a - S m a l l H i g h - P Top View Bottom View e r Figure 30. PCB Layout Example fo r m a n c e , H i g h - F r e q u e n c y D r M O S M o d u l e © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 17

F Physical Dimensions D M F 6 7 0 B PIN#1 5 0.10 C INDICATOR - 6.00 E 2X A 5.80 x t r 4.50 a 30 21 -S 31 m 20 a 6.00 2.50 0.40 ll H 0.65 ig 0.25 h 1.60 - P 0.10 C 11 e 2X 40 r TOP VIEW SEE 0.60 1 100.35 for DETAIL 'A' 0.50 TYP 0.15 m a 2.10 n 2.10 c LAND PATTERN e , FRONT VIEW 0.10 C A B RECOMMENDATION H 4.40±0.10 0.05 C ig (2.20) 0.30 h 0.40 21 300.20(40X) -F 31 r e 0.50 20 PIN #1 INDICATOR q (0.70) 2.40±0.10 0.20 MAY APPEAR AS ue OPTIONAL n c y 1.50±0.10 0.50 (40X) D 0.30 40 r 11 M 0.40 10 1 O 2.00±0.10 2.00±0.10 S (0.20) 0.50 (0.20) NOTES: UNLESS OTHERWISE SPECIFIED M o BOTTOM VIEW A) DOES NOT FULLY CONFORM TO JEDEC d u REGISTRATION MO-220, DATED l 1.10 MAY/2005. e 0.90 B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS 0.10 C OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 0.08 C 0.30 0.05 E) DRAWING FILE NAME: PQFN40AREV3 0.20 0.00 C SEATING DETAIL 'A' PLANE SCALE: 2:1 Figure 31. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0 mm Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 18

F D M F 6 7 0 5 - E x t r a - S m a l l H i g h - P e r f o r m a n c e , H i g h - F r e q u e n c y D r M O S M o d u l e © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FDMF6705 • Rev. 1.0.4 19

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