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F D M C 6 October 2013 1 2 FDMC612PZ P Z ® P-Channel PowerTrench MOSFET P - C -20 V, -14 A, 8.4 mΩ h a Features General Description n n e (cid:132) Max rDS(on) = 8.4 mΩ at VGS = -4.5 V, ID = -14 A This P-Channel MOSFET is produced using Fairchild l Semiconductor’s advanced PowerTrench® process that has P (cid:132) Max r = 13 mΩ at V = -2.5 V, I = -11 A DS(on) GS D been optimized for r , switching performance and o DS(ON) w (cid:132) High performance trench technology for extremely low rDS(on) ruggedness. e r (cid:132) High power and current handling capability in a widely used T surface mount package r Applications e n (cid:132) Termination is Lead-free and RoHS Compliant c (cid:132) Battery Management h (cid:132) HBM ESD capability level > 3.6 KV typical (Note 4) ® (cid:132) Load Switch M O S F E T D D D D 8 7 6 5 S D S D Pin 1 S D 1 2 3 4 G S S S Pin 1 G D Top Bottom MLP 3.3x3.3 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol Parameter Ratings Units V Drain to Source Voltage -20 V DS V Gate to Source Voltage ±12 V GS Drain Current -Continuous T = 25 °C -40 C I -Continuous T = 25 °C (Note 1a) -14 A D A -Pulsed -50 E Single Pulse Avalanche Energy (Note 3) 38 mJ AS Power Dissipation T = 25 °C 26 P C W D Power Dissipation T = 25 °C (Note 1a) 2.3 A T , T Operating and Storage Junction Temperature Range -55 to +150 °C J STG Thermal Characteristics R Thermal Resistance, Junction to Case 4.9 θJC °C/W R Thermal Resistance, Junction to Ambient (Note 1a) 53 θJA Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity FDMC612PZ FDMC612PZ MLP 3.3X3.3 13 ’’ 12 mm 3000 units ©2013 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDMC612PZ Rev.C3

F D Electrical Characteristics T = 25 °C unless otherwise noted M J C Symbol Parameter Test Conditions Min Typ Max Units 6 1 Off Characteristics 2 P BV Drain to Source Breakdown Voltage I = -250 μA, V = 0 V -20 V Z DSS D GS ΔBV Breakdown Voltage Temperature P DSS I = -250 μA, referenced to 25 °C -19 mV/°C - ΔT Coefficient D C J h IDSS Zero Gate Voltage Drain Current VDS = -16 V, VGS = 0 V -1 μA a I Gate to Source Leakage Current V = ±12 V, V = 0 V ±10 μA n GSS GS DS n e On Characteristics l P V Gate to Source Threshold Voltage V = V , I = -250 μA -0.6 -0.9 -1.5 V o GS(th) GS DS D w ΔV Gate to Source Threshold Voltage GS(th) I = -250 μA, referenced to 25 °C 9 mV/°C e ΔTJ Temperature Coefficient D rT VGS = -4.5 V, ID = -14 A 5.9 8.4 re r Static Drain to Source On Resistance V = -2.5 V, I = -11 A 8.2 13 mΩ n DS(on) GS D c VGS = -4.5 V, ID = -14 A, TJ = 125 °C 8.3 13 h g Forward Transconductance V = -5 V, I = -14 A 85 S ® FS DS D M Dynamic Characteristics O S C Input Capacitance 5710 7995 pF iss F V = -10 V, V = 0 V, C Output Capacitance DS GS 1215 1700 pF E oss f = 1 MHz T C Reverse Transfer Capacitance 1170 1640 pF rss Switching Characteristics t Turn-On Delay Time 26 42 ns d(on) tr Rise Time VDD = -10 V, ID = -14 A, 52 83 ns td(off) Turn-Off Delay Time VGS = -4.5 V, RGEN = 6 Ω 96 154 ns t Fall Time 81 130 ns f Q Total Gate Charge 53 74 nC g V = -10 V, I = -14 A, Q Gate to Source Charge DD D 9.4 nC gs V = -4.5 V GS Q Gate to Drain “Miller” Charge 18 nC gd Drain-Source Diode Characteristics V = 0 V, I = -14 A (Note 2) -0.8 -1.3 V Source to Drain Diode Forward Voltage GS S V SD V = 0 V, I = -2 A (Note 2) -0.7 -1.2 GS S t Reverse Recovery Time 39 62 ns rr I = -14 A, di/dt = 100 A/μs Q Reverse Recovery Charge F 17 31 nC rr Notes: 1: RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθJA is determined by the user’s board design. a. 53 °C/W when mounted on a b. 125 °C/W when mounted on a 1 in2 pad of 2 oz copper. minimum pad of 2 oz copper. GDDSS FSFS GDDSS FSFS 2: Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %. 3: EAS of 38 mJ is based on starting TJ = 25 °C, L = 0.3 mH, IAS = -16 A, VDD = -18 V, VGS = -10 V. 4: The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. ©2013 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FDMC612PZ Rev.C3

F D Typical Characteristics M T = 25 °C unless otherwise noted J C 6 50 2.0 1 2 V = -4.5 V CE PULSE DURATION = 80 μs P URRENT (A)3400 VGS = -2V.G5S V V= G-3S. 0= GV-3S.5 V ALIZEDE ON-RESISTAN1.5 VGS = -2.5 VVGS = -3.0 DVUTY CYCLE = 0.5% MAX Z P-Chan RAIN C20 NORM SOURC1.0 nel -I, DD10 PULSE DURATION = 80 μs AIN TO VGS = -3.5 V VGS = -4.5 V Pow DUTY CYCLE = 0.5% MAX R e 00.0 0.2 0.4 0.6 D0.50 10 20 30 40 50 rT -V , DRAIN TO SOURCE VOLTAGE (V) r DS -ID, DRAIN CURR ENT (A) en c Figure 1. On-Region Characteristics Figure 2. Normalized On-Resistance h ® vs Drain Current and Gate Voltage M O 1.5 25 S E PULSE DURATION = 80 μs F NC1.4 ID = -14 A )Ω DUTY CYCLE = 0.5% MAX E STA1.3 VGS = -4.5 V (mE 20 ID = -14 A T NORMALIZED TO SOURCE ON-RESI0111....9012 rDRAIN TO ,DS(on)URCE ON-RESISTANC11505 TJ = 125 oC AIN 0.8 SO TJ = 25 oC R D0.7 0 -75 -50 -25 0 25 50 75 100 125 150 1.5 2.0 2.5 3.0 3.5 4.0 4.5 TJ, JUNCTION TEM PERATURE (oC) -VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On- Resistance Figure 4. On-Resistance vs Gate to vs Junction Temperature Source Voltage 50 50 PDUULTSYE C DYUCRLEA T=I O0.N5 %= 8M0A μXs T (A) 10 VGS = 0 V N 40 E DRAIN CURRENT (A) 2300 VDS = -5 V TJ = 150 oC TJ = 25 oC VERSE DRAIN CURR 0.11 TJ = 150 oC TJ = 25 oC -I, D 10 TJ = -55 oC -I, RES0.01 TJ = -55 oC 0 0.001 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -VGS, GATE TO SO URCE VOLTAGE (V) -VSD, BODY DIODE FO RWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current ©2013 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FDMC612PZ Rev.C3

F D Typical Characteristics M T = 25 °C unless otherwise noted J C 6 1 4.5 10000 2 E (V) ID = -14 A VDD = -8 V Ciss PZ AG P E VOLT3.0 VDD = -10 V E (pF) -Ch URC VDD = -12 V ANC Coss an O T n S CI e TE TO 1.5 CAPA1000 Crss l Po A G f = 1 MHz w -V, GS0.0 500 VGS = 0 V erT 0 20 40 60 0.1 1 10 20 r Qg, GATE CH ARGE (nC) -VDS, DRAIN TO SOU RCE VOLTAGE (V) en c Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain h to Source Voltage ® M 50 50 O RθJC = 4.9 oC/W SF NT (A) TJ = 25 oC T (A) 40 ET URRE 10 TJ = 100 oC RREN 30 VGS = -4.5 V C U AVALANCHE TJ = 125 oC , -IDRAIN CD1200 Limited by Package VGS = -2.5 V , S A -I 1 0 0.001 0.01 0.1 1 10 100 25 50 75 100 125 150 tAV, TIME IN AVA LANCHE (ms) TC, CASE TEMPERATURE (oC) Figure 9. Unclamped Inductive Figure 10. Maximum Continuous Drain Switching Capability Current vs Case Temperature 10-1 100 10-2 VDS = 0 V A) 100 μs RENT ( 1100--43 NT (A) 10 1 ms R E CU 10-5 TJ = 125 oC RR 10 ms GATE LEAKAGE 11110000----9876 TJ = 25 oC -I, DRAIN CUD 0.11 TLSTRHIJIθMN JI=SAIG T M =ALE AERD1X 2E PB5 ARU Yo ALIC SrST/D WEESD(on) CURVE BENT TO 11D10 0Cs0 s ms , g TA = 25 oC MEASURED DATA -I 10-10 0.01 0 6 12 18 0.01 0.1 1 10 100 -VGS, GATE TO S OURCE VOLTAGE (V) -VDS, DRAIN to SOU RCE VOLTAGE (V) Figure 11. Gate Leakage Current vs Gate to Figure 12. Forward Bias Safe Source Voltage Operating Area ©2013 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FDMC612PZ Rev.C3

F D Typical Characteristics M T = 25 °C unless otherwise noted J C 1000 6 1 2 OWER (W) 100 TSRAIθNJ =AG 2=L5 E1 o 2PC5U oLCS/EW PZ P-C P T h N a NSIE 10 nn RA e K T l P A 1 E o , PPK) we P( r 0.1 T 10-4 10-3 10-2 10-1 1 10 100 1000 re n t, PULSE WIDTH (s ec) c Figure 13. Single Pulse Maximum Power Dissipation h ® 2 M DUTY CYCLE-DESCENDING ORDER 1 O S AL D = 00..25 FE ALIZED THERM PEDANCE,ZJAθ 0.1 0000....1000521 PDM t1 T RMIM0.01 t2 NO SINGLE PULSE NOTES: R = 125 oC/W DUTY FACTOR: D = t1/t2 θJA PEAK TJ = PDM x ZθJA x RθJA + TA 0.001 10-4 10-3 10-2 10-1 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 14. Junction-to-Ambient Transient Thermal Response Curve ©2013 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FDMC612PZ Rev.C3

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