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F D D 8 March 2015 8 8 2 FDD8882 / FDU8882 / F D ® N-Channel PowerTrench MOSFET U 8 30V, 55A, 11.5mΩ 8 8 2 Features General Description N - C ! r = 11.5mΩ, V = 10V, I = 35A This N-Channel MOSFET has been designed specifically to DS(ON) GS D h improve the overall efficiency of DC/DC converters using ! r = 15mΩ, V = 4.5V, I = 35A a DS(ON) GS D either synchronous or conventional switching PWM n ! High performance trench technology for extremely low controllers. It has been optimized for low gate charge, low n rDS(ON) rDS(ON) and fast switching speed. el ! Low gate charge P o ! High power and current handling capability w (cid:132) RoHS Complicant e r Application T r e ! DC/DC converters n c h ® M O S F E T D D G I-PAK G S D-PAK (TO-251AA) TO-252 (TO-252) G D S S ©2008 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDD8882/FDU8882 Rev. 1.2

F Absolute Maximum Ratings TC = 25°C unless otherwise noted D D Symbol Parameter Ratings Units 8 V Drain to Source Voltage 30 V 8 DSS 8 VGS Gate to Source Voltage ±20 V 2 Drain Current / Continuous (T = 25oC, V = 10V) (Note 1) 55 A F C GS D I Continuous (T = 25oC, V = 4.5V) (Note 1) 50 A D C GS U Continuous (Tamb = 25oC, VGS = 10V, with RθJA = 52oC/W) 12.6 A 8 Pulsed Figure 4 A 8 8 EAS Single Pulse Avalanche Energy (Note 2) 41 mJ 2 Power dissipation 55 W N P D Derate above 25oC 0.37 W/oC - C TJ, TSTG Operating and Storage Temperature -55 to 175 oC h a Thermal Characteristics n n RθJC Thermal Resistance Junction to Case TO-252, TO-251 2.73 oC/W el RθJA Thermal Resistance Junction to Ambient TO-252, TO-251 100 oC/W P o RθJA Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 52 oC/W w e Package Marking and Ordering Information r T r Device Marking Device Package Reel Size Tape Width Quantity e FDD8882 FDD8882 TO-252AA 13” 16mm 2500 units n c FDU8882 FDU8882 TO-251AA N/A (Tube) N/A 75 units h F ® F M O Electrical Characteristics T = 25°C unless otherwise noted S C F Symbol Parameter Test Conditions Min Typ Max Units E T Off Characteristics B Drain to Source Breakdown Voltage I = 250µA, V = 0V 30 - - V VDSS D GS V = 24V - - 1 I Zero Gate Voltage Drain Current DS µA DSS V = 0V T = 150oC - - 250 GS C I Gate to Source Leakage Current V = ±20V - - ±100 nA GSS GS On Characteristics V Gate to Source Threshold Voltage V = V , I = 250µA 1.2 - 2.5 V GS(TH) GS DS D I = 35A, V = 10V - 0.0094 0.0115 D GS I = 35A, V = 4.5V - 0.0130 0.0150 r Drain to Source On Resistance D GS Ω DS(ON) I = 35A, V = 10V, D GS - 0.0150 0.0190 T = 175oC J www.fairchildsemi.com FDD8882/FDU8882 Rev. 1.2 2

F Dynamic Characteristics D D C Input Capacitance - 1260 - pF ISS V = 15V, V = 0V, 8 COSS Output Capacitance f =D S1MHz GS - 240 - pF 8 8 C Reverse Transfer Capacitance - 140 - pF RSS 2 RG Gate Resistance VGS = 0.5V, f = 1MHz - 2.4 - Ω / Q Total Gate Charge at 10V V = 0V to 10V - 22 33 nC F g(TOT) GS D Q Total Gate Charge at 5V V = 0V to 5V - 11.7 17.6 nC g(5) GS V = 15V U Q Threshold Gate Charge V = 0V to 1V DD - 1.2 1.8 nC g(TH) GS I = 35A 8 Qgs Gate to Source Gate Charge ID= 1.0mA - 3.7 - nC 8 g 8 Q Gate Charge Threshold to Plateau - 2.5 - nC gs2 2 Q Gate to Drain “Miller” Charge - 4.6 - nC gd N - Switching Characteristics (V = 10V) C GS h t Turn-On Time - - 135 ns ON a t Turn-On Delay Time - 8 - ns n d(ON) n tr Rise Time VDD = 15V, ID = 35A - 82 - ns e td(OFF) Turn-Off Delay Time VGS = 10V, RGS = 13Ω - 40 - ns l P t Fall Time - 25 - ns f o tOFF Turn-Off Time - - 98 ns w e Drain-Source Diode Characteristics r T I = 35A - - 1.25 V r V Source to Drain Diode Voltage SD e SD ISD = 15A - - 1.0 V n t Reverse Recovery Time I = 35A, dI /dt = 100A/µs - - 32 ns c rr SD SD h QRR Reverse Recovered Charge ISD = 35A, dISD/dt = 100A/µs - - 21 nC ® Notes: M 1: Package current limitation is 35A. O 2: Starting TJ = 25°C, L = 0.1mH, IAS = 28A, VDD = 27V, VGS = 10V. 3 S F E T www.fairchildsemi.com FDD8882/FDU8882 Rev. 1.2 3

F D Typical Characteristics T = 25°C unless otherwise noted D C 8 8 8 1.2 60 2 / R 1.0 CURRENT LIMITED F E BY PACKAGE MULTIPLI 0.8 RENT (A)40 DU8 SSIPATION 00..46 DRAIN CUR20 882 N R DI I, D - E C OW 0.2 VGS = 10V h P a 0 0 n 0 25 50 75 100 125 150 175 25 50 75 100 125 150 175 n TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC) el P Figure 1. Normalized Power Dissipation vs Case Figure 2. Maximum Continuous Drain Current vs o Temperature Case Temperature w e r 2 T DUTY CYCLE - DESCENDING ORDER r 1 0.5 e 0.2 n 0.1 c E ZEDANC 00..0052 h® NORMALIAL IMPED0.1 0.01 PDM MO Z, θJCHERM t1 SF T t2 E SINGLE PULSE NOTES: T DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 600 TRANSCONDUCTANCE TC = 25oC MAY LIMIT CURRENT IN THIS REGION FOR TEMPERATURES ABOVE 25oC DERATE PEAK A) CURRENT AS FOLLOWS: T ( REN I = I25 175 - TC R 150 U C AK 100 VGS = 4.5V E P , M D I 30 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) Figure 4. Peak Current Capability www.fairchildsemi.com FDD8882/FDU8882 Rev. 1.2 4

F Typical Characteristics T = 25°C unless otherwise noted D C D 8 1000 500 8 8 I, DRAIN CURRENT (A)D111000 TOSLJIPIN M=EG IRAMTLAREAETEDX PIA O BRU NMYAL TSAIrNEDYE SD TB(HOENIS) 11110m00m0µssµss I, AVALANCHE CURRENT (A)AS11000 tIItffAA VVRR ===≠ S((00LLT/)AR(IAR)lSnT)[I/N((I1AG.S3 *T*RRJ )A=/(T 11E.53D0*R oBCAVTDESDS -B VVSDDTDSA)SR -T VINDGD) T+J1 =] 25oC 2 / FDU8882 N-C TC = 25oC DC h 0.1 1 a 1 10 60 0.001 0.01 0.1 1 10 100 n VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms) n e Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 l Figure 6. Unclamped Inductive Switching P o Capability w e r 80 80 T PULSE DURATION = 80µs PULSE DURATION = 80µs r DVDUDT =Y 1C5YVCLE = 0.5% MAX VGS = 10V DUTY CYCLE = 0.5% MAX en A)60 A) 60 VGS = 4.5V c T ( T ( h EN EN VGS = 3.5V ® R R AIN CUR40 TJ = 25oC AIN CUR 40 MO DR DR S I, D20 I, D20 VGS = 3V F E TJ = 175oC TJ = -55oC TC = 25oC T 0 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5 2.0 2.5 VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics 1.8 20 PULSE DURATION = 80µs PULSE DURATION = 80µs E DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX C 1.6 E ID = 35A UR , DRAIN TO SOURCN)ΩN RESISTANCE (m)1126 ALIZED DRAIN TO SOON RESISTANCE111...024 rDS(OO ID = 1A NORM 0.8 VGS = 10V, ID = 35A 0.6 8 -80 -40 0 40 80 120 160 200 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC) Figure 9. Drain to Source On Resistance vs Gate Figure 10. Normalized Drain to Source On Voltage and Drain Current Resistance vs Junction Temperature www.fairchildsemi.com FDD8882/FDU8882 Rev. 1.2 5

F Typical Characteristics T = 25°C unless otherwise noted D C D 8 1.2 1.10 8 8 VGS = VDS, ID = 250µA E ID = 250µA 2 C R / NORMALIZED GATEHRESHOLD VOLTAGE01..80 ALIZED DRAIN TO SOUREAKDOWN VOLTAGE 11..0005 FDU8882 T0.6 MB 0.95 N R O - N C h 0.4 0.90 a -80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200 n TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) n e Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source l P Junction Temperature Breakdown Voltage vs Junction Temperature o w 3000 10 e r T CISS = CGS + CGD GE (V) 8 VDD = 15V re CE (pF) 1000 E VOLTA 6 nch ACITAN COSS ≅ CDS + CGD SOURC ® M C, CAP CRSS = CGD V, GATE TO GS 24 WDEASVCIEDEF =NO D3R5IMNASG IONRDER: OSFE VGS = 0V, f = 1MHz ID = 5A T 100 0 0.1 1 10 30 0 5 10 15 20 25 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant Voltage Gate Current www.fairchildsemi.com FDD8882/FDU8882 Rev. 1.2 6

F D D 8 Test Circuits and Waveforms 8 8 2 / VDS F BVDSS D U L tP VDS 8 8 VRAERQYU ItRP ETDO POEBATKA IINAS RG +VDD IAS VDD 82 VGS - N - DUT C h tP a 0V IAS n 0.01Ω 0 n e tAV l P o Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms w e r T VDS re VDD Qg(TOT) n c L VDS VGS h VGS = 10V ® VGS + Qg(5) M VDD Qgs2 VGS = 5V O - S DUT F Ig(REF) VGS = 1V E 0 T Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr tf VDS 90% 90% + VGS VDD 10% 10% - 0 DUT 90% RGS VGS 50% 50% PULSE WIDTH VGS 10% 0 Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms www.fairchildsemi.com FDD8882/FDU8882 Rev. 1.2 7

F Thermal Resistance vs. Mounting Pad Area D D The maximum rated junction temperature, T , and the JM 125 8 thermal resistance of the heat dissipating path determines 8 the maximum allowable device power dissipation, P , in an RθJA = 33.32+ 23.84/(0.268+Area) EQ.2 8 DM atepmplpicearatiotunr.e , T A (TohCe)r, eafonrde thetrhme al raepspislitcaantcioen ’Rs θJAa (moCbi/eWn)t 100 RθJA = 33.32+ 154/(1.73+Area) EQ.3 2 / must be reviewed to ensure that TJM is never exceeded. W) FD Equation 1 mathematically represents the relationship and C/ serves as the basis for establishing the rating of the part. o(A 75 U RθJ 8 (T –T ) 8 PDM = ------J--R--M---θ---J---A-----A----- (EQ. 1) 50 82 N In using surface mount devices such as the TO-252 - 25 C package, the environment in which it is applied will have a 0.01 0.1 1 10 h significant influence on the part’s current and maximum (0.0645) (0.645) (6.45) (64.5) a power dissipation ratings. Precise determination of PDM is n complex and influenced by many factors: AREA, TOP COPPER AREA in2 (cm2) n Figure 21. Thermal Resistance vs Mounting e 1. Mounting pad area onto which the device is attached and Pad Area l whether there is copper on one side or both sides of the P board. o w 2. The number of copper layers and the thickness of the e board. r T 3. The use of external heat sinks. re n 4. The use of thermal vias. c h 5. Air flow and board orientation. ® 6. For non steady state applications, the pulse width, the M duty cycle and the transient thermal response of the part, O the board and the environment they are in. S Fairchild provides thermal information to assist the F designer’s preliminary application evaluation. Figure 21 E defines the RθJA for the device as a function of the top T copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. 23.84 RθJA = 33.32+(---0---.-2---6---8-----+-----A----r---e---a---)- (EQ. 2) Area in Inches Squared 154 RθJA = 33.32+(---1---.-7---3-----+-----A----r---e---a----) (EQ. 3) Area in Centimeters Squared www.fairchildsemi.com FDD8882/FDU8882 Rev. 1.2 8

F PSPICE Electrical Model D D .SUBCKT FDD8882 2 1 3 ; rev October 2004 8 Ca 12 8 9e-10 8 Cb 15 14 9e-10 LDRAIN 8 Cin 6 8 1.55e-9 DPLCAP 5 DRAIN 2 10 2 / DDbbroedayk 7 5 5 1 D1 bDobdryeMakOMDOD RSLC1 RLDRAIN F 51 DBREAK D Dplcap 10 5 DplcapMOD RSLC2 + U 5 Ebreak 11 7 17 18 34.1 51 ESLC 11 8 Eds 14 8 5 8 1 -50 + 8 - 8 EEEvgsgtsh r16e3 1s 80 6 66 2 881 1119 8 1 ESG+68 EVTHRES RDR1A6IN EBREAK -1178 DBODY 2 N Evtemp 20 6 18 22 1 LGATE EVTEMP + 189 - 21 MWEAK -C GATE RGATE + 18 - 6 It 8 17 1 1 RLGATE 9 20 22 MSTROMMED ha Lgate 1 9 8.6e-9 LSOURCE n LLdsorauirnc e2 35 71 .20.e6-79e-9 CIN 8 7 SOU3RCE ne RSOURCE l RLSOURCE P RLgate 1 9 86 S1A S2A RRLLsdorauirnc e2 35 71 026.7 12 183 1143 15 17 RBREAK 18 ow S1B S2B RVTEMP e MMmstreod 1166 66 88 8 8 M MsmtroeMdMOODD CA 13++ CB+ 14 IT -19 rTr Mweak 16 21 8 8 MweakMOD EGS 68 EDS 58 + VBAT en Rbreak 17 18 RbreakMOD 1 -- - 8 c Rdrain 50 16 RdrainMOD 2.5e-3 22 h Rgate 9 20 2.43 RVTHRES ® RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 M Rsource 8 7 RsourceMOD 6.5e-3 O Rvthres 22 8 RvthresMOD 1 S Rvtemp 18 19 RvtempMOD 1 F S1a 6 12 13 8 S1AMOD E S1b 13 12 13 8 S1BMOD T S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*600),10))} .MODEL DbodyMOD D (IS=2E-12 IKF=10 N=1.01 RS=5.7e-3 TRS1=8e-4 TRS2=2e-7 + CJO=4.6e-10 M=0.58 TT=1e-11 XTI=2.7) .MODEL DbreakMOD D (RS=1 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=5.0e-10 IS=1e-30 N=10 M=0.45) .MODEL MmedMOD NMOS (VTO=2.11 KP=14 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.43) .MODEL MstroMOD NMOS (VTO=2.65 KP=240 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=1.82 KP=0.09 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=24.3 RS=0.1) .MODEL RbreakMOD RES (TC1=8.0e-4 TC2=-8e-7) .MODEL RdrainMOD RES (TC1=-6e-3 TC2=6e-6) .MODEL RSLCMOD RES (TC1=8e-5 TC2=2e-6) .MODEL RsourceMOD RES (TC1=7.5e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-1.2e-3 TC2=-8.3e-6) .MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=3.3e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-1.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-2) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. www.fairchildsemi.com FDD8882/FDU8882 Rev. 1.2 9

F SABER Electrical Model D D rev October 2004 8 template FDD8882 n2,n1,n3 8 electrical n2,n1,n3 8 { 2 var i iscl / dp..model dbodymod = (isl=2.0e-12,ikf=10,nl=1.01,rs=5.7e-3,trs1=8e-4,trs2=2e-7,cjo=4.6e-10,m=0.58,tt=1e-11,xti=2.7) F dp..model dbreakmod = (rs=1,trs1=1e-3,trs2=-8.9e-6) D dp..model dplcapmod = (cjo=5.0e-10,isl=10e-30,nl=10,m=0.45) U m..model mmedmod = (type=_n,vto=2.11,kp=14,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.65,kp=240,is=1e-30, tox=1) 8 m..model mweakmod = (type=_n,vto=1.82,kp=0.09,is=1e-30, tox=1,rs=0.1) 8 8 sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5) LDRAIN 2 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4) DPLCAP 5 DRAIN sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-1.5) 2 N sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-2) 10 - c.ca n12 n8 = 9e-10 RSLC1 RLDRAIN C c.cb n15 n14 = 9e-10 51 h c.cin n6 n8 = 1.1e-9 RSLC2 a ISCL n dp.dbody n7 n5 = model=dbodymod 50 DBREAK n dp.dbreak n5 n11 = model=dbreakmod - e dp.dplcap n10 n5 = model=dplcapmod ESG+68 EVTHRES RDR1A6IN 11 DBODY l P ssppee..eebdrse na1k4 n n181 nn57 nn81 7= n118 = 34.1 LGATE EVTEMP + 189 - 21 MWEAK ow ssppee..eesggs nn163 n n180 nn66 nn88 == 11 GA1TE 9RGATE20+ 1282 - 6 MMED EBREA+K er spe.evthres n6 n21 n19 n8 = 1 RLGATE MSTRO 1178 LSOURCE Tr spe.evtemp n20 n6 n18 n22 = 1 CIN 8 - 7 SOU3RCE en i.it n8 n17 = 1 RSOURCE c RLSOURCE h lll...llldgsoraauteirn c nen1 2n n3n9 5n =7= 8=1. .620e.e6--979e-9 12S1A183 1143S2A 15 17 RBREAK 18 ® M S1B S2B RVTEMP O rreess..rrllgdaratein n n12 n n95 = = 8 160 CA 13++ CB+ 14 IT -19 S res.rlsource n3 n7 = 26.7 EGS 68 EDS 58 + VBAT FE -- - 8 T 22 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u RVTHRES m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=8.0e-4,tc2=-8e-7 res.rdrain n50 n16 = 2.5e-3, tc1=-6e-3,tc2=6e-6 res.rgate n9 n20 = 2.43 res.rslc1 n5 n51 = 1e-6, tc1=8e-5,tc2=2e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 6.5e-3, tc1=7.5e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-1.2e-3,tc2=-8.3e-6 res.rvtemp n18 n19 = 1, tc1=-2.5e-3,tc2=3.3e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/600))** 10)) } } www.fairchildsemi.com FDD8882/FDU8882 Rev. 1.2 10

F PSPICE Thermal Model D th JUNCTION D REV 23 October 2004 8 8 FDD8882T 8 2 CTHERM1 TH 6 5.6e-4 / CTHERM2 6 5 6.8e-4 F CTHERM3 5 4 2.0e-3 RTHERM1 CTHERM1 D CTHERM4 4 3 2.8e-3 U CTHERM5 3 2 5.7e-3 CTHERM6 2 TL 5.8e-3 8 6 8 8 RTHERM1 TH 6 5.3e-2 2 RTHERM2 6 5 2.2e-1 RTHERM3 5 4 2.9e-1 N RTHERM2 CTHERM2 RTHERM4 4 3 3.9e-1 - RTHERM5 3 2 6.0e-1 C RTHERM6 2 TL 6.6e-1 h 5 a SABER Thermal Model n n SABER thermal model FDD8882T e template thermal_model th tl RTHERM3 CTHERM3 l P thermal_c th, tl { o ctherm.ctherm1 th 6 =5.6e-4 w ctherm.ctherm2 6 5 =6.8e-4 4 e ctherm.ctherm3 5 4 =2.0e-3 r T ctherm.ctherm4 4 3 =2.8e-3 r ctherm.ctherm5 3 2 =5.7e-3 RTHERM4 CTHERM4 e ctherm.ctherm6 2 tl =5.8e-3 n c rtherm.rtherm1 th 6 =5.3e-2 h rtherm.rtherm2 6 5 =2.2e-1 3 ® rtherm.rtherm3 5 4 =2.9e-1 rtherm.rtherm4 4 3 =3.9e-1 M rtherm.rtherm5 3 2 =6.0e-1 O RTHERM5 CTHERM5 rtherm.rtherm6 2 tl =6.6e-1 S } F E 2 T RTHERM6 CTHERM6 tl CASE www.fairchildsemi.com FDD8882/FDU8882 Rev. 1.2 11

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