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FDC5614P产品简介:
ICGOO电子元器件商城为您提供FDC5614P由Fairchild Semiconductor设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 FDC5614P价格参考。Fairchild SemiconductorFDC5614P封装/规格:晶体管 - FET,MOSFET - 单, P-Channel 60V 3A (Ta) 1.6W (Ta) Surface Mount SuperSOT™-6。您可以下载FDC5614P参考资料、Datasheet数据手册功能说明书,资料中有FDC5614P 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | |
ChannelMode | Enhancement |
描述 | MOSFET P-CH 60V 3A SSOT-6MOSFET SSOT-6 P-CH |
产品分类 | FET - 单分离式半导体 |
FET功能 | 逻辑电平门 |
FET类型 | MOSFET P 通道,金属氧化物 |
Id-ContinuousDrainCurrent | 3 A |
Id-连续漏极电流 | 3 A |
品牌 | Fairchild Semiconductor |
产品手册 | |
产品图片 | |
rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | 晶体管,MOSFET,Fairchild Semiconductor FDC5614PPowerTrench® |
数据手册 | |
产品型号 | FDC5614P |
PCN封装 | |
PCN设计/规格 | |
Pd-PowerDissipation | 1.6 W |
Pd-功率耗散 | 1.6 W |
RdsOn-Drain-SourceResistance | 105 mOhms |
RdsOn-漏源导通电阻 | 105 mOhms |
Vds-Drain-SourceBreakdownVoltage | - 60 V |
Vds-漏源极击穿电压 | - 60 V |
Vgs-Gate-SourceBreakdownVoltage | +/- 20 V |
Vgs-栅源极击穿电压 | 20 V |
上升时间 | 10 ns |
下降时间 | 10 ns |
不同Id时的Vgs(th)(最大值) | 3V @ 250µA |
不同Vds时的输入电容(Ciss) | 759pF @ 30V |
不同Vgs时的栅极电荷(Qg) | 24nC @ 10V |
不同 Id、Vgs时的 RdsOn(最大值) | 105 毫欧 @ 3A,10V |
产品培训模块 | http://www.digikey.cn/PTM/IndividualPTM.page?site=cn&lang=zhs&ptm=356 |
产品目录页面 | |
产品种类 | MOSFET |
供应商器件封装 | 6-SSOT |
其它名称 | FDC5614PTR |
典型关闭延迟时间 | 19 ns |
功率-最大值 | 800mW |
包装 | 带卷 (TR) |
单位重量 | 36 mg |
商标 | Fairchild Semiconductor |
安装类型 | 表面贴装 |
安装风格 | SMD/SMT |
封装 | Reel |
封装/外壳 | SOT-23-6 细型,TSOT-23-6 |
封装/箱体 | SSOT-6 |
工厂包装数量 | 3000 |
晶体管极性 | P-Channel |
最大工作温度 | + 150 C |
最小工作温度 | - 55 C |
标准包装 | 3,000 |
正向跨导-最小值 | 8 S |
漏源极电压(Vdss) | 60V |
电流-连续漏极(Id)(25°C时) | 3A (Ta) |
系列 | FDC5614P |
通道模式 | Enhancement |
配置 | Single Quad Drain |
零件号别名 | FDC5614P_NL |
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F D C 5 April 2015 6 1 4 P FDC5614P 60V P-Channel Logic Level PowerTrench MOSFET General Description Features This 60V P-Channel MOSFET uses Fairchild’s high • –3 A, –60 V. R = 0.105 Ω @ V = –10 V voltage PowerTrench process. It has been optimized for DS(ON) GS R = 0.135 Ω @ V = –4.5 V power management applications. DS(ON) GS Applications • Fast switching speed • High performance trench technology for extremely • DC-DC converters low R • Load switch DS(ON) • Power management S D 1 6 D 2 5 G D 3 4 SuperSOT T M-6 D Absolute Maximum Ratings TA=25oC unless otherwise noted Symbol Parameter Ratings Units V Drain-Source Voltage –60 V DSS VGSS Gate-Source Voltage ±20 V ID Drain Current – Continuous (Note 1a) –3 A – Pulsed –20 PD Maximum Power Dissipation (Note 1a) 1.6 W (Note 1b) 0.8 TJ, TSTG Operating and Storage Junction Temperature Range –55 to +150 °C Thermal Characteristics RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 30 °C/W Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity .564 FDC5614P 7’’ 8mm 3000 units 2002 Fairchild Semiconductor Corporation FDC5614P Rev. 1.4
F D Electrical Characteristics T = 25°C unless otherwise noted C A 5 Symbol Parameter Test Conditions Min Typ Max Units 6 1 Off Characteristics 4 P BVDSS Drain–Source Breakdown Voltage VGS = 0 V, ID = –250 µA –60 V ∆BVDSS Breakdown Voltage Temperature ID = –250 µA, Referenced to –49 mV/°C ∆T Coefficient 25°C J IDSS Zero Gate Voltage Drain Current VDS = –48 V, VGS = 0 V –1 µA I Gate–Body Leakage, Forward V = 20V, V = 0 V 100 nA GSSF GS DS I Gate–Body Leakage, Reverse V = –20 V V = 0 V –100 nA GSSR GS DS On Characteristics (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = –250 µA –1 –1.6 –3 V ∆VGS(th) Gate Threshold Voltage ID = –250 µA,Referenced to 25°C 4 mV/°C ∆T Temperature Coefficient J RDS(on) Static Drain–Source VGS = –10 V, ID = –3 A 82 105 mΩ On–Resistance VGS = –4.5 V, ID = –2.7 A 105 135 V = –10 V, I = –3 A T=125°C 130 190 GS D J I On–State Drain Current V = –10 V, V = –5 V –20 A D(on) GS DS g Forward Transconductance V = –5 V, I = –3 A 8 S FS DS D Dynamic Characteristics Ciss Input Capacitance VDS = –30 V, V GS = 0 V, 759 pF C Output Capacitance f = 1.0 MHz 90 pF oss C Reverse Transfer Capacitance 39 pF rss Switching Characteristics (Note 2) td(on) Turn–On Delay Time VDD = –30 V, ID = –1 A, 7 14 ns tr Turn–On Rise Time VGS = –10 V, RGEN = 6 Ω 10 20 ns t Turn–Off Delay Time 19 34 ns d(off) t Turn–Off Fall Time 12 22 ns f Qg Total Gate Charge VDS = –30V, ID = –3.0 A, 15 24 nC Qgs Gate–Source Charge VGS = –10 V 2.5 nC Q Gate–Drain Charge 3.0 nC gd Drain–Source Diode Characteristics and Maximum Ratings I Maximum Continuous Drain–Source Diode Forward Current –1.3 A S VSD Drain–Source Diode Forward VGS = 0 V, IS = –1.3 A (Note 2) –0.8 –1.2 V Voltage Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a. 78°C/W when mounted on a 1in2 pad of 2oz copper on FR-4 board. b. 156°C/W when mounted on a minimum pad. 2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0% FDC5614P Rev. 1.4
F D Typical Characteristics C 5 6 1 4 P 15 1.8 129 VGS --=65 ..-001VV0V -4-.45.V0V -3.5V RMALIZEDON-RESISTANCE 11..46 VGS = -3.5V -4.0V -4.5V 36 -3.0V R, NODS(ON)AIN-SOURCE 1.12 -5.0V -6.0V -7.0V -8.0V -10V R D -2.5V 0.8 0 0 2 4 6 8 10 0 1 2 3 4 5 -VDS, DRAIN-SOURCE VOLTAGE (V) -ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.8 0.4 1.6 VIDG S= = - 3-.100AV ID = -1.5A 0.3 1.4 1.2 TA = 125oC 0.2 1 0.8 0.1 0.6 TA = 25oC 0.4 0 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10 TJ, JUNCTION TEMPERATURE (oC) -VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation with Figure 4. On-Resistance Variation with Temperature. Gate-to-Source Voltage. 15 100 VDS = -5V TA = -55oC 25oC VGS = 0V 12 10 125oC TA = 125oC 9 1 25oC -55oC 6 0.1 3 0.01 0 0.001 1 2 3 4 5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -VGS, GATE TO SOURCE VOLTAGE (V) -VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDC5614P Rev. 1.4
F D Typical Characteristics C 5 6 1 4 P 10 1200 AGE (V) 8 ID = -3.0A VDS = -10V -20V 1000 fV =G S1 = M 0H Vz OLT -30V 800 E V 6 CISS C R 600 U SO 4 E- 400 T A -V, GGS 2 200 CRSS COSS 0 0 0 4 8 12 16 0 10 20 30 40 50 60 Qg, GATE CHARGE (nC) -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. 100 40 SINGLE PULSE T (A) 10 RDS(ON) LIMIT 100µs 30 RθJTA A= = 1 2556°°CC/W N 10ms E RR 100ms N CU 1 1s 20 DRAI VGS = -10V 10s -I, D 0.1 SRIθNJAG =L E1 5P6UoCLS/WE DC 10 TA = 25oC 0.01 0 0.1 1 10 100 0.1 1 10 100 1000 -VDS, DRAIN-SOURCE VOLTAGE (V) t1, TIME (sec) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. 1 D = 0.5 0.2 RθJA(t) = r(t) + RθJA 0.1 0.1 RθJA = 156°C/W 0.05 P(pk) 0.02 0.01 t1 0.01 t2 SINGLE PULSE TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 t1, TIME (sec) Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient themal response will change depending on the circuit board design. FDC5614P Rev. 1.4
SYMM C L C 0.95 0.95 3.00 A 2.80 6 4 1.00 MIN B 3.00 2.60 2.60 1.70 C 1.50 1 3 0.50 0.95 0.30 0.70 MIN 0.20 M A B 1.90 LAND PATTERN RECOMMENDATION (0.30) SEE DETAIL A 1.10 MAX H 1.00 0.70 C 0.20 0.10 0.08 0.00 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MO-193. VAR. AA, ISSUE E. B) ALL DIMENSIONS ARE IN MILLIMETERS. GAGE PLANE C PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.25mm PER END. PACKAGE WIDTH 0.25 DOES NOT INCLUDE INTERLEAD FLASH OR 8° PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25mm PER 0° SIDE. PACKAGE LENGTH AND WIDTH DIMENSIONS ARE DETERMINED AT DATUM H. 0.55 D) DRAWING FILE NAME: MKT-MA06AREVF 0.35 SEATING PLANE 0.60 REF DETAIL A SCALE: 50X
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