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F D B 3 March 2013 6 8 2 FDB3682 / FDP3682 / F N-Channel PowerTrench® MOSFET D P 100 V, 32 A, 36 mΩ 3 6 8 2 Features Applications N • R = 32 mΩ ( Typ.) @ V = 10 V, I = 32 A (cid:127) Consumer Appliances -C DS(on) GS D h • QG(tot) = 18.5 nC( Typ.) @ VGS = 10 V (cid:127) Synchronous Rectification a n (cid:127) Low Miller Charge n (cid:127) Battery Protection Circuit e (cid:127) Low Qrr Body Diode l (cid:127) Motor drives and Uninterruptible Power Supplies P (cid:127) UIS Capability (Single Pulse and Repetitive Pulse) o w (cid:127) Micro Solar Inverter e r T Formerly developmental type 82755 r e n c h ® M D D O S F E G T G G D2-PAK DS TO-220 S S (TO-263) MOSFET Maximum Ratings TC = 25°C unless otherwise noted Symbol Parameter FDB3682 / FDP3682 Unit V Drain to Source Voltage 100 V DSS V Gate to Source Voltage ±20 V GS Drain Current Continuous (T = 25oC, V = 10V) 32 A C GS I Continuous (T = 100oC, V = 10V) 23 A D C GS Continuous (Tamb = 25oC, VGS = 10V, RθJA = 43oC/W) 6 A Pulsed Figure 4 A E Single Pulse Avalanche Energy (Note 1) 55 mJ AS Power dissipation 95 W P D Derate above 25oC 0.63 W/oC T , T Operating and Storage Temperature -55 to 175 oC J STG Thermal Characteristics RθJC Thermal Resistance Junction to Case TO-220, TO-263, Max. 1.58 oC/W RθJA Thermal Resistance Junction to Ambient TO-220, TO-263 (Note 2), Max. 62 oC/W RθJA MThaexr.mal Resistance Junction to Ambient TO-263, 1in2 copper pad area, 43 oC/W ©2002 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDB3682 / FDP3682 Rev. C1

F Package Marking and Ordering Information D B Device Marking Device Package Reel Size Tape Width Quantity 3 6 FDB3682 FDB3682 TO-263 330mm 24mm 800 units 8 2 FDP3682 FDP3682 TO-220 Tube N/A 50 units / F Electrical Characteristics D T = 25°C unless otherwise noted C P 3 Symbol Parameter Test Conditions Min Typ Max Unit 6 8 Off Characteristics 2 N BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 100 - - V - C I Zero Gate Voltage Drain Current VDS = 80V - - 1 µA h DSS V = 0V T = 150oC - - 250 a GS C n IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA n e l On Characteristics P o VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 2 - 4 V w I =32A, V =10V - 0.032 0.036 e D GS r r Drain to Source On Resistance I = 16A, V = 6V, - 0.040 0.060 Ω T DS(ON) D GS r I =32A, V =10V, T =175oC - 0.080 0.090 e D GS C n c Dynamic Characteristics h ® CISS Input Capacitance V = 25V, V = 0V, - 1250 - pF M COSS Output Capacitance f =D S1MHz GS - 190 - pF O C Reverse Transfer Capacitance - 45 - pF S RSS F Q Total Gate Charge at 10V V = 0V to 10V - 18.5 28 nC g(TOT) GS E Qg(TH) Threshold Gate Charge VGS = 0V to 2V VDD = 50V - 2.4 3.6 nC T Q Gate to Source Gate Charge I = 32A - 6.5 - nC gs D Qgs2 Gate Charge Threshold to Plateau Ig = 1.0mA - 4.1 - nC Q Gate to Drain “Miller” Charge - 4.6 - nC gd Resistive Switching Characteristics (V = 10V) GS t Turn-On Time - - 83 ns ON t Turn-On Delay Time - 9 - ns d(ON) tr Rise Time VDD = 50V, ID = 32A - 46 - ns td(OFF) Turn-Off Delay Time VGS = 10V, RGS = 16Ω - 26 - ns t Fall Time - 32 - ns f t Turn-Off Time - - 87 ns OFF Drain-Source Diode Characteristics I = 32A - - 1.25 V V Source to Drain Diode Voltage SD SD I = 16A - - 1.0 V SD t Reverse Recovery Time I = 32A, dI /dt = 100A/µs - - 55 ns rr SD SD Q Reverse Recovery Charge I = 32A, dI /dt = 100A/µs - - 90 nC RR SD SD Notes: 1: Starting TJ = 25°C, L = 0.27mH, IAS = 20A. 2: Pulse Width = 100s ©2002 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FDB3682 / FDP3682 Rev. C1

F Typical Characteristics D TC = 25°C unless otherwise noted B 3 6 1.2 35 8 2 R 1.0 30 VGS = 10V / F E ULTIPLI 0.8 NT (A) 25 DP3 N M RRE 20 68 TIO 0.6 CU 2 WER DISSIPA 00..24 I, DRAIN D 1105 N-Cha O 5 n P n 0 e 0 25 50 75 100 125 150 175 0 l 25 50 75 100 125 150 175 P TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC) ow Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs e r Ambient Temperature Case Temperature T r e n 2 c DUTY CYCLE - DESCENDING ORDER h 1 00..52 ® 0.1 M E 0.05 O NORMALIZEDAL IMPEDANC0.1 00..0012 PDM SFET Z, θJCHERM t1 T t2 NOTES: SINGLE PULSE DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 400 TRANSCONDUCTANCE TC = 25oC MAY LIMIT CURRENT FOR TEMPERATURES IN THIS REGION ABOVE 25oC DERATE PEAK A) CURRENT AS FOLLOWS: T ( RREN VGS = 10V I = I25 17155 -0 TC U K C 100 A E P , M D I 30 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) Figure 4. Peak Current Capability ©2002 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FDB3682 / FDP3682 Rev. C1

F Typical Characteristics TC = 25°C unless otherwise noted D B 3 200 100 6 10µs If R = 0 8 100 100µs T (A) tItfAA VVR ==≠ ( (0LL)/(RIA)lSn)[/((I1A.S3**RR)A/(T1E.3D* RBAVTDESDS -B VVDDDS)S - VDD) +1] 2 / F URRENT (A)10 OPERATION IN THIS 10m1sms HE CURREN 10 STARTING TJ = 25oC DP368 C C 2 AIN LIMITAERDE AB YM rADYS (BOEN) LAN N R A I, DD 1 TSJIN =G MLAEX P RUALTSEED DC I, AVAS STARTING TJ = 150oC -Cha TC = 25oC n n 0.1 1 e 1 10 100 200 0.001 0.01 0.1 1 10 l VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms) Po w Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 e Figure 6. Unclamped Inductive Switching r Capability T r e n c 80 80 h PULSE DURATION = 80µs VGS = 20V ® A) 60 DVDUDT =Y 1C5YVCLE = 0.5% MAX A) 60 PDUULTSYE C DYUCRLEA T=I O0.N5 %= 8M0AµsX VGS = 10V MO NT ( NT ( TC = 25oC S E E F R R CUR 40 CUR 40 VGS = 6V ET AIN TJ = 175oC AIN R R D D I, D20 TJ = 25oC I, D 20 TJ = -55oC VGS = 5V 0 0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 0 1 2 3 4 VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics 60 3.0 ΩANCE (m) 50 PDUULTSYE C DYUCRLEA T=I O0.N5 %= 8M0AmXs VGS = 6V OURCE 2.5 DPUULTSYE C DYUCRLEA T=I O0N.5 %= 8M0AµsX SIST TO SNCE N TO SOURCE ON RE 3400 VGS = 10V NORMALIZED DRAIN ON RESISTA112...050 RAI VGS = 10V, ID =32A D 20 0.5 0 5 10 15 20 25 30 35 -80 -40 0 40 80 120 160 200 Id, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE (oC) Figure 9. Drain to Source On Resistance vs Drain Figure 10. Normalized Drain to Source On Current Resistance vs Junction Temperature ©2002 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FDB3682 / FDP3682 Rev. C1

F Typical Characteristics D T = 25°C unless otherwise noted C B 3 6 1.2 1.2 8 2 VGS = VDS, ID = 250µA RCE ID = 250µA / F NORMALIZED GATETHRESHOLD VOLTAGE001...680 RMALIZED DRAIN TO SOUBREAKDOWN VOLTAGE11..01 DP3682 N-Ch O a N n n 0.4 0.9 e l -80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200 P TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) o w Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source e r Junction Temperature Breakdown Voltage vs Junction Temperature T r e n 2000 10 c h 1000 CISS = CGS + CGD GE (V) 8 VDD = 50V M® E (pF) COSS ≅ CDS + CGD VOLTA OS APACITANC CRSS = CGD O SOURCE 46 FET C 100 T C, TE A G WAVEFORMS IN S, 2 DESCENDING ORDER: VGS = 0V, f = 1MHz VG IIDD == 3126AA 20 0 0.1 1 10 100 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 13. Capacitance vs Drain to Source Figure14. Gate Charge Waveforms for Constant Voltage Gate Currents ©2002 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FDB3682 / FDP3682 Rev. C1

F Test Circuits and Waveforms D B 3 6 8 VDS BVDSS 2 / tP F L VDS D P IAS 3 VARY tP TO OBTAIN + VDD 68 REQUIRED PEAK IAS RG VDD 2 VGS - N DUT -C h tP a 0V IAS 0 n 0.01Ω n tAV el P o w Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms e r T r e n VDS VDD Qg(TOT) ch VDS ® L M VGS = 10V O VGS + S F -VDD VGS E T DUT VGS = 2V Ig(REF) Qg(0TH) Qgs2 Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr tf VDS 90% 90% + VGS VDD 10% 10% - 0 DUT 90% RGS VGS 50% 50% PULSE WIDTH VGS 0 10% Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms ©2002 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com FDB3682 / FDP3682 Rev. C1

F Thermal Resistance vs. Mounting Pad Area D B The maximum rated junction temperature, TJM, and the 80 36 thermal resistance of the heat dissipating path determines RθJA = 26.51+ 19.84/(0.262+Area) EQ.2 8 the maximum allowable device power dissipation, P , in an 2 DM application. Therefore the application’s ambient RθJA = 26.51+ 128/(1.69+Area) EQ.3 / tmemuspt ebraet urerev,i eTwAe (do Cto), eannsdu rteh etrhmaat l Tres isista nnecvee Rr θeJxAc (eoeCd/eWd). 60 FD JM W) P Equation 1 mathematically represents the relationship and C/ 3 serPves a=s (-t--hT---eJ----M --b----–a----s-T---iA-s----) for establishing the rating of th(eE Qpa. r1t). oR(θJA 40 682 N DM RθJA -C h In using surface mount devices such as the TO-263 a n package, the environment in which it is applied will have a 20 n significant influence on the part’s current and maximum 0.1 1 10 e l power dissipation ratings. Precise determination of PDM is (0.645) (6.45) (64.5) P complex and influenced by many factors: AREA, TOP COPPER AREA in2 (cm2) o Figure 21. Thermal Resistance vs Mounting w 1. Mounting pad area onto which the device is attached and Pad Area e whether there is copper on one side or both sides of the rT board. r e n 2. The number of copper layers and the thickness of the c board. h ® 3. The use of external heat sinks. M 4. The use of thermal vias. O S 5. Air flow and board orientation. F E 6. For non steady state applications, the pulse width, the T duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeter square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. 19.84 RθJA = 26.51+(---0---.-2---6---2-----+-----A----r---e---a---)- (EQ. 2) Area in Inches Squared 128 RθJA = 26.51+(---1---.-6---9-----+-----A----r---e---a---)- (EQ. 3) Area in Centimeters Squared ©2002 Fairchild Semiconductor Corporation 7 www.fairchildsemi.com FDB3682 / FDP3682 Rev. C1

F PSPICE Electrical Model D B .SUBCKT FDB3682 2 1 3 ; rev May 2002 3 CA 12 8 4e-10 6 8 Cb 15 14 5.5e-10 LDRAIN 2 Cin 6 8 1.22e-9 DPLCAP 5 DRAIN / 2 F Dbody 7 5 DbodyMOD 10 D RLDRAIN Dbreak 5 11 DbreakMOD RSLC1 P Dplcap 10 5 DplcapMOD 51 DBREAK 3 RSLC2 + 6 Ebreak 11 7 17 18 108 551 ESLC 11 82 EEdgss 1143 88 56 88 11 - -50 + N Esg 6 10 6 8 1 ESG 68 RDRAIN EBREAK 1178 DBODY -C Evthres 6 21 19 8 1 + EVTHRES 16 - h Evtemp 20 6 18 22 1 LGATE EVTEMP + 189 - 21 MWEAK an ILt g8a 1te7 11 9 5.96e-9 GA1TE RLGATE 9RGATE20+ 1282 - 6 MSTROMMED nel P LSOURCE LLdsorauirnc e2 35 71 .30.e1-99e-9 CIN 8 7 SOU3RCE ow RSOURCE e RLgate 1 9 59.6 RLSOURCE rT RRLLdsorauirnc e2 35 71 031.9 12S1A13 14S2A 15 17 RBREAK 18 re 8 13 n c Mmed 16 6 8 8 MmedMOD S1B S2B RVTEMP h MMRbswrtereoaa kk1 611 676 21818 8 8R M b8sr MetraowkMeMOaOkDMD O1D CA EGS13++68 EDSCB+5814 IT +-19VBAT MO® Rdrain 50 16 RdrainMOD 10.5e-3 -- - 8 S 22 F Rgate 9 20 1.86 RVTHRES E RSLC1 5 51 RSLCMOD 1.0e-6 T RSLC2 5 50 1.0e3 Rsource 8 7 RsourceMOD 11.9e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*70),2.5))} .MODEL DbodyMOD D (IS=2.4E-12 RS=4.4e-3 TRS1=2.0e-3 TRS2=4.5e-7 + CJO=9e-10 M=0.57 TT=2.9e-8 XTI=4.0) .MODEL DbreakMOD D (RS=0.6 TRS1=1.4e-3 TRS2=-5.0e-5) .MODEL DplcapMOD D (CJO=2.7e-10 IS=1.0e-30 N=10 M=0.56) .MODEL MstroMOD NMOS (VTO=4.16 KP=32 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=3.48 KP=2.7 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.86) .MODEL MweakMOD NMOS (VTO=2.97 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=18.6 RS=0.1) .MODEL RbreakMOD RES (TC1=1.05e-3 TC2=-1.1e-8) .MODEL RdrainMOD RES (TC1=1.6e-2 TC2=4e-5) .MODEL RSLCMOD RES (TC1=3.0e-3 TC2=2.9e-6) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-4.1e-3 TC2=-1.4e-5) .MODEL RvtempMOD RES (TC1=-3.5e-3 TC2=1.3e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-2.0) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-5.0) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.4 VOFF=0.3) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.4) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2002 Fairchild Semiconductor Corporation 8 www.fairchildsemi.com FDB3682 / FDP3682 Rev. C1

F SABER Electrical Model D B REV May 2002 3 template FDB3682 n2,n1,n3 6 8 electrical n2,n1,n3 2 { / var i iscl F dp..model dbodymod = (isl=2.4e-12,rs=4.4e-3,trs1=2.0e-3,trs2=4.5e-7,cjo=9e-10,m=0.57,tt=2.9e-8,xti=4.0) D dp..model dbreakmod = (rs=0.6,trs1=1.4e-3,trs2=-5e-5) P dp..model dplcapmod = (cjo=2.7e-10,isl=10e-30,nl=10,m=0.56) 3 m..model mstrongmod = (type=_n,vto=4.16,kp=32,is=1e-30, tox=1) 6 8 m..model mmedmod = (type=_n,vto=3.48,kp=2.7,is=1e-30, tox=1) 2 m..model mweakmod = (type=_n,vto=2.97,kp=0.04,is=1e-30, tox=1,rs=0.1) N sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5,voff=-2) LDRAIN - sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-5) DPLCAP 5 DRAIN C sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.4,voff=0.3) h sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.4) 10 a c.ca n12 n8 = 4e-10 RSLC1 RLDRAIN n c.cb n15 n14 = 5.5e-10 51 n RSLC2 e c.cin n6 n8 = 1.22e-9 l ISCL P dp.dbody n7 n5 = model=dbodymod 50 DBREAK o dp.dbreak n5 n11 = model=dbreakmod - w dp.dplcap n10 n5 = model=dplcapmod ESG +68 EVTHRES RDR1A6IN 11 DBODY erT ssppee..eebdrse na1k4 n n181 nn57 nn81 7= n118 = 108 LGATE EVTEMP + 189 - 21 MWEAK re ssspppeee...eeevgstgsh rnne16s3 nn n1680 n nn2661 nnn881 9== n118 = 1 GA1TE RLGATE 9RGATE20+ 1282 - 6 MSTROMMED EBREA+K1178 LSOURCE nch® spe.evtemp n20 n6 n18 n22 = 1 CIN 8 - 7 SOU3RCE M O i.it n8 n17 = 1 RSOURCE RLSOURCE S ll..llgdaratein n n12 n n95 = = 5 1.9.06ee--99 12S1A183 1143S2A 15 17 RBREAK 18 FET l.lsource n3 n7 = 3.19e-9 S1B S2B RVTEMP rreess..rrllgdaratein n n12 n n95 = = 5 190.6 CA 13++ CB+ 14 IT -19 res.rlsource n3 n7 = 31.9 EGS 68 EDS 58 + VBAT m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u -- - 8 22 m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u RVTHRES m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=-1.1e-8 res.rdrain n50 n16 = 10.5e-3, tc1=1.6e-2,tc2=4e-5 res.rgate n9 n20 = 1.86 res.rslc1 n5 n51 = 1.0e-6, tc1=3.0e-3,tc2=2.9e-6 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 11.9e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-4.1e-3,tc2=-1.4e-5 res.rvtemp n18 n19 = 1, tc1=-3.5e-3,tc2=1.3e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/70))** 2.5)) } } ©2002 Fairchild Semiconductor Corporation 9 www.fairchildsemi.com FDB3682 / FDP3682 Rev. C1

F SPICE Thermal Model D th JUNCTION B REV 20 May 2002 3 6 8 FDB3682_JC TH TL 2 / CTHERM1 TH 6 1.6e-3 F CTHERM2 6 5 4.5e-3 D CTHERM3 5 4 5.0e-3 RTHERM1 CTHERM1 P CTHERM4 4 3 8.0e-3 3 CTHERM5 3 2 8.2e-3 6 8 CTHERM6 2 TL 4.7e-2 2 6 N RTHERM1 TH 6 3.3e-2 - RTHERM2 6 5 7.9e-2 C RTHERM3 5 4 9.5e-2 h RTHERM2 CTHERM2 RTHERM4 4 3 1.4e-1 a RTHERM5 3 2 2.9e-1 n n RTHERM6 2 TL 6.7e-1 e 5 l SABER Thermal Model P o SABER thermal model FDB3682 w template thermal_model th tl RTHERM3 CTHERM3 e thermal_c th, tl rT { r e ctherm.ctherm1 th 6 =1.6e-3 ctherm.ctherm2 6 5 =4.5e-3 4 nc ctherm.ctherm3 5 4 =5.0e-3 h ctherm.ctherm4 4 3 =8.0e-3 ® ctherm.ctherm5 3 2 =8.2e-3 RTHERM4 CTHERM4 M ctherm.ctherm6 2 tl =4.7e-2 O S rtherm.rtherm1 th 6 =3.3e-2 F rtherm.rtherm2 6 5 =7.9e-2 3 E rtherm.rtherm3 5 4 =9.5e-2 T rtherm.rtherm4 4 3 =1.4e-1 rtherm.rtherm5 3 2 =2.9e-1 RTHERM5 CTHERM5 rtherm.rtherm6 2 tl =6.7e-1 } 2 RTHERM6 CTHERM6 tl CASE ©2002 Fairchild Semiconductor Corporation 10 www.fairchildsemi.com FDB3682 / FDP3682 Rev. C1

F D Mechanical Dimensions B 3 6 8 D2-PAK 2 / F D P 3 6 8 2 N 190.6.657 -A- 12.70 -C 1.68 4 1.00 h a n n e 9.45 l 9.65 P 8.38 o w 10.00 e r T 1.78 MAX (6.40) r e 2 n 3.80 c 1 3 h ® (2.12) 1.78 1.05 M 1.14 0.99 5.08 O 0.51 LAND PATTERN RECOMMENDATION S 5.08 0.25 M B AM UNLESS NOTED, ALL DIMS TYPICAL F E -B- T 4.83 4.06 6.22 MIN 1.65 1.14 4 6.86 MIN 15.88 14.61 SEE DETAIL A 2 3 1 NOTES: UNLESS OTHERWISE SPECIFIED A) ALL DIMENSIONS ARE IN MILLIMETERS. B) REFERENCE JEDEC, TO-263, VARIATION AB. C) DIMENSIONING AND TOLERANCING PER ANSI Y14.5M - 1994. D) LOCATION OF THE PIN HOLE MAY VARY GAGE PLANE (LOWER LEFT CORNER, LOWER CENTER AND CENTER OF THE PACKAGE). 0.25 00..7343 8(cid:31) E) LANDPATTERN RECOMMENDATION PER IPC 0(cid:31) TO254P1524X482-3N F) FILENAME: TO263A02REV6 0.10 B 2.79 8(cid:31) 0.25 MAX 1.78 0(cid:31) (5.38) SEATING PLANE DETAIL A, ROTATED 90(cid:31) SCALE: 2X Dimensions in Millimeters ©2002 Fairchild Semiconductor Corporation 11 www.fairchildsemi.com FDB3682 / FDP3682 Rev. C1

F D Mechanical Dimensions B 3 6 8 2 TO-220 / F D P 3 6 8 2 N - C h a n n e l P o w e r T r e n c h ® M O S F E T Dimensions in Millimeters ©2002 Fairchild Semiconductor Corporation 12 www.fairchildsemi.com FDB3682 / FDP3682 Rev. C1

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A critical component in any component of a life support, device, or intended for surgical implant into the body or (b) support or sustain life, system whose failure to perform can be reasonably expected to cause and (c) whose failure to perform when properly used in accordance with the failure of the life support device or system, or to affect its safety or instructions for use provided in the labeling, can be reasonably effectiveness. expected to result in a significant injury of the user. ANTI-COUNTERFEITING POLICY Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support. Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Datasheet contains the design specifications for product development. Specifications Advance Information Formative / In Design may change in any manner without notice. Datasheet contains preliminary data; supplementary data will be published at a later Preliminary First Production date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Datasheet contains final specifications. Fairchild Semiconductor reserves the right to No Identification Needed Full Production make changes at any time without notice to improve the design. Datasheet contains specifications on a product that is discontinued by Fairchild Obsolete Not In Production Semiconductor. The datasheet is for reference information only. Rev. I64 ©2002 Fairchild Semiconductor Corporation 13 www.fairchildsemi.com FDB3682 / FDP3682 Rev. C1

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