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F D P 2 October 2013 5 3 2 FDP2532 / FDB2532 / F ® D N-Channel PowerTrench MOSFET B 2 150 V, 79 A, 16 mΩ 5 3 2 Features Applications — • RDS(on) = 14 mΩ ( Typ.) @ VGS = 10 V, ID = 33 A • Consumer Appliances N - • QG(tot) = 82 nC ( Typ.) @ VGS = 10 V • Synchronous Rectification C h • Low Miller Charge • Battery Protection Circuit a n • Low Qrr Body Diode • Motor drives and Uninterruptible Power Supplies ne • UIS Capability (Single Pulse and Repetitive Pulse) • Micro Solar Inverter l P o w Formerly developmental type 82884 e r T r D e n c h D ® M O G G G S DS TO-220 S D2-PAK FE T S MOSFET Maximum Ratings TC = 25°C unless otherwise noted Symbol Parameterr FDP2532 / FDB2532 Unit V Drain to Source Voltage 150 V DSS V Gate to Source Voltage ±20 V GS Drain Current Continuous (T = 25oC, V = 10V) 79 A C GS I Continuous (T = 100oC, V = 10V) 56 A D C GS Continuous (Tamb = 25oC, VGS = 10V, RθJA = 43oC/W) 8 A Pulsed Figure 4 A E Single Pulse Avalanche Energy (Note 1) 400 mJ AS Power dissipation 310 W P D Derate above 25oC 2.07 W/oC T , T Operating and Storage Temperature -55 to 175 oC J STG Thermal Characteristics RθJC Thermal Resistance Junction to Case, Max. TO-220, D2-PAK 0.61 oC/W RθJA Thermal Resistance Junction to Ambient, Max. TO-220, D2-PAK (Note 2) 62 oC/W RθJA Thermal Resistance Junction to Ambient D2-PAK, Max. 1in2 copper pad area 43 oC/W ©2002 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDP2532 / FDB2532 Rev. C2

F D Package Marking and Ordering Information P 2 Device Marking Device Package Reel Size Tape Width Quantity 5 FDB2532 FDB2532 D2-PAK 330 mm 24 mm 800 units 3 2 FDP2532 FDP2532 TO-220 Tube N/A 50 units / F D Electrical Characteristics TC = 25°C unless otherwise noted B 2 Symbol Parameter Test Conditions Min Typ Max Unit 5 3 2 Off Characteristics — B Drain to Source Breakdown Voltage I = 250µA, V = 0V 150 - - V VDSS D GS N V = 120V - - 1 IDSS Zero Gate Voltage Drain Current VDS = 0V T = 150oC - - 250 µA -C GS C h IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA a n n On Characteristics e VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 2 - 4 V Pl I = 33A, V = 10V - 0.014 0.016 o D GS w r Drain to Source On Resistance ID = 16A, VGS = 6V, - 0.016 0.024 Ω e DS(ON) r ID = 33A, VGS = 10V, - 0.040 0.048 T T = 175oC r C e n Dynamic Characteristics c h ® CISS Input Capacitance - 5870 - pF V = 25V, V = 0V, M C Output Capacitance DS GS - 615 - pF OSS f = 1MHz O CRSS Reverse Transfer Capacitance - 135 - pF S Q Total Gate Charge at 10V V = 0V to 10V - 82 107 nC F g(TOT) GS E Qg(TH) Threshold Gate Charge VGS = 0V to 2V VDD = 75V - 11 14 nC T Q Gate to Source Gate Charge I = 33A - 23 - nC gs D Qgs2 Gate Charge Threshold to Plateau Ig = 1.0mA - 13 - nC Q Gate to Drain “Miller” Charge - 19 - nC gd Resistive Switching Characteristics (V = 10V) GS t Turn-On Time - - 69 ns ON t Turn-On Delay Time - 16 - ns d(ON) tr Rise Time VDD = 75V, ID = 33A - 30 - ns td(OFF) Turn-Off Delay Time VGS = 10V, RGS = 3.6Ω - 39 - ns t Fall Time - 17 - ns f t Turn-Off Time - - 84 ns OFF Drain-Source Diode Characteristics I = 33A - - 1.25 V V Source to Drain Diode Voltage SD SD I = 16A - - 1.0 V SD t Reverse Recovery Time I = 33A, dI /dt= 100A/µs - - 105 ns rr SD SD Q Reverse Recovery Charge I = 33A, dI /dt= 100A/µs - - 327 nC RR SD SD Notes: 1: Starting TJ = 25°C, L = 0.5 mH, IAS = 40A. 2: Pulse Width = 100s ©2002 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FDP2532 / FDB2532 Rev. C2

F D Typical Characteristics TC = 25°C unless otherwise noted P 2 5 1.2 125 3 2 VGS = 10V R 1.0 / MULTIPLIE 0.8 ENT (A) 17050 FDB2 SSIPATION 00..46 RAIN CURR 50 532 — R DI , DD N OWE 0.2 I 25 -C P h 0 a 0 n 0 25 50 75 100 125 150 175 25 50 75 100 125 150 175 n TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC) el P Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs o Ambient Temperature Case Temperature w e r T 2.0 r e DUTY CYCLE - DESCENDING ORDER n 1.0 0.5 c 0.2 h 0.1 ® E 0.05 M DC 0.02 ZEAN 0.01 O ORMALIL IMPED0.1 PDM SFE Z, NθJCTHERMA t1t2 T NOTES: SINGLE PULSE DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 2000 TC = 25oC FOR TEMPERATURES 1000 TMRAAYN LSIMCIOTN CDUURCRTEANNTCE ABOVE 25oC DERATE PEAK IN THIS REGION CURRENT AS FOLLOWS: A) NT ( I = I25 175 - TC E 150 R UR VGS = 10V C K A E P , M100 D I 50 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) Figure 4. Peak Current Capability ©2002 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FDP2532 / FDB2532 Rev. C2

F D Typical Characteristics TC = 25°C unless otherwise noted P 2 5 1000 200 10µs STARTING TJ = 25oC 32 100 / 100µs A) F A) 100 T ( D T ( EN B EN RR 2 AIN CURR 10 OLPIMEIRATARETDEIAO B NNMY AIrNDY S B(OHENIS) 101mmss NCHE CU 10 STARTING TJ = 150oC 532 — R A I, DD 1 SINGLE PULSE DC , AVALAS ItfA VR == (0L)(IAS)/(1.3*RATED BVDSS - VDD) N-C TJ = MAX RATED I If R ≠ 0 h TC = 25oC tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] a 0.1 1 n 1 10 100 300 0.001 0.01 0.1 1 n VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms) el P Figure5. Forward Bias Safe Operating Area NOTE:RefertoFairchildApplicationNotesAN7515andAN7517 o Figure6. Unclamped Inductive Switching w Capability e r T r 180 180 e n PULSE DURATION = 80µs VGS = 10V VGS = 7V c 150 DUTY CYCLE = 0.5% MAX 150 h VDD = 15V VGS = 6V ® A) A) M T (120 T (120 O N N RRE TJ = 175oC RRE 90 SF U 90 U RAIN C 60 RAIN C 60 VGS = 5V TC = 25oC ET I, DD TJ = 25oC TJ = -55oC I, DD 30 PULSE DURATION = 80µs 30 DUTY CYCLE = 0.5% MAX 0 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics 18 3.0 PULSE DURATION = 80µs PULSE DURATION = 80µs Ωm ) DUTY CYCLE = 0.5% MAX E DUTY CYCLE = 0.5% MAX ON RESISTANCE (1167 VGS = 6V DRAIN TO SOURCESISTANCE22..05 E 15 D R1.5 C EN UR VGS = 10V LIZO O A O S14 RM 1.0 T O AIN N VGS = 10V, ID =33A DR13 0.5 0 20 40 60 80 -80 -40 0 40 80 120 160 200 ID, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE (oC) Figure 9. Drain to Source On Resistance vs Drain Figure 10. Normalized Drain to Source On Current Resistance vs Junction Temperature ©2002 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FDP2532 / FDB2532 Rev. C2

F D Typical Characteristics TC = 25°C unless otherwise noted P 2 5 1.4 1.2 3 VGS = VDS, ID = 250µA ID = 250µA 2 1.2 CE / F R NORMALIZED GATEHRESHOLD VOLTAGE 01..80 ALIZED DRAIN TO SOUREAKDOWN VOLTAGE11..01 DB2532 — N T 0.6 RMB - O C N h a 0.4 0.9 n -80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200 n TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) el P Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source o Junction Temperature Breakdown Voltage vs Junction Temperature w e r T 10000 10 r VDD = 75V en V) c CISS = CGS + CGD E ( 8 h E (pF)1000 COSS ≅ CDS + CGD E VOLTAG 6 MO® NC RC S CITA CRSS = CGD SOU 4 FE C, CAPA GATE TO 2 WDEASVCEEFNODRIMNSG IONRDER: T 100 VGS = 0V, f = 1MHz V, GS IIDD == 3136AA 50 0 0.1 1 10 150 0 20 40 60 80 100 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant Voltage Gate Currents ©2002 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FDP2532 / FDB2532 Rev. C2

F D Test Circuits and Waveforms P 2 5 3 2 VDS / BVDSS F D L tP B VDS 2 VRAERQYU ItRP ETDO POEBATKA IINAS RG +VDD IAS VDD 532 VGS - — DUT N - tP C 0V IAS h 0.01Ω 0 an n tAV e l P o Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms w e r T r VDS e n VDD Qg(TOT) c h L VDS VGS VGS = 10V M® VGS + O VDD Qgs2 S - F E DUT T Ig(REF) VGS = 2V 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr tf VDS 90% 90% + VGS VDD 10% 10% - 0 DUT 90% RGS VGS 50% 50% PULSE WIDTH VGS 10% 0 Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms ©2002 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com FDP2532 / FDB2532 Rev. C2

F Thermal Resistance vs. Mounting Pad Area D P 2 The maximum rated junction temperature, TJM, and the 80 5 tthhee rmmaaxl imreusimst aanllocew aobf leth dee hviecaet pdoiswseipr adtiisnsgip paatitohn ,d Peterm, inin aens RθJA = 26.51+ 19.84/(0.262+Area) EQ.2 32 DM application. Therefore the application’s ambient RθJA = 26.51+ 128/(1.69+Area) EQ.3 / temperature, TA (oC), and thermal resistance RθJA (oC/W) FD must be reviewed to ensure that TJM is never exceeded. W) 60 B Equation 1 mathematically represents the relationship and C/ 2 serves as the basis for establishing the rating of the part. o(A 53 P = -(--T----J---M------–-----T---A-----) (EQ. 1) RθJ 40 2 — DM RθJA N - C In using surface mount devices such as the TO-263 h package, the environment in which it is applied will have a 20 a significant influence on the part’s current and maximum 0.1 1 10 n n power dissipation ratings. Precise determination of PDM is (0.645) (6.45) (64.5) e complex and influenced by many factors: AREA, TOP COPPER AREA in2 (cm2) l Figure 21. Thermal Resistance vs Mounting P 1. Mounting pad area onto which the device is attached and Pad Area o w whether there is copper on one side or both sides of the e board. r T 2. The number of copper layers and the thickness of the r e board. n c 3.The use of external heat sinks. h ® 4.The use of thermal vias. M O 5.Air flow and board orientation. S F 6. For non steady state applications, the pulse width, the E duty cycle and the transient thermal response of the part, T the board and the environment they are in. Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. 19.84 RθJA = 26.51+(---0---.-2---6---2-----+-----A----r---e---a---)- (EQ. 2) Area in Inches Squared 128 RθJA = 26.51+(---1---.-6---9-----+-----A----r---e---a----) (EQ. 3) Area in Centimeters Squared ©2002 Fairchild Semiconductor Corporation 7 www.fairchildsemi.com FDP2532 / FDB2532 Rev. C2

F PSPICE Electrical Model D P .SUBCKT FDB2532 2 1 3 ; rev April 2002 2 5 CA 12 8 1.4e-9 3 CB 15 14 1.6e-9 2 CIN 6 8 5.61e-9 DPLCAP 5 LDRAIN DRAIN / 2 F Dbody 7 5 DbodyMOD 10 D RLDRAIN Dbreak 5 11 DbreakMOD RSLC1 B Dplcap 10 5 DplcapMOD 51 DBREAK 2 RSLC2 + 5 Ebreak 11 7 17 18 159 551 ESLC 11 32 EEdgss 1143 88 56 88 11 - -50 + — Esg 6 10 6 8 1 ESG 68 RDRAIN EBREAK 1178 DBODY N Evthres 6 21 19 8 1 + EVTHRES 16 - - Evtemp 20 6 18 22 1 LGATE EVTEMP + 189 - 21 MWEAK Ch It 8 17 1 GA1TE 9RGATE20+ 1282 - 6 MMED an Lgate 1 9 9.56e-9 RLGATE MSTRO ne LSOURCE LLdsorauirnc e2 35 71 .70.e7-19e-9 CIN 8 7 SOU3RCE Pl RSOURCE o RLgate 1 9 95.6 RLSOURCE w RRLLdsorauirnc e2 35 71 077.1 12S1A13 14S2A 15 17 RBREAK 18 erT 8 13 r Mmed 16 6 8 8 MmedMOD S1B S2B RVTEMP en MMswteroa k1 61 66 281 8 8 M 8s MtrowMeOakDM OD CA 13++ CB+ 14 IT -19 ch Rbreak 17 18 RbreakMOD 1 EGS 68 EDS 58 + VBAT M® Rdrain 50 16 RdrainMOD 9.6e-3 -- - 8 O 22 Rgate 9 20 1.01 RVTHRES S RSLC1 5 51 RSLCMOD 1.0e-6 F RSLC2 5 50 1.0e3 E Rsource 8 7 RsourceMOD 3.0e-3 T Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*190),3))} .MODEL DbodyMOD D (IS=6.0E-11 N=1.09 RS=2.3e-3 TRS1=3.0e-3 TRS2=1.0e-6 + CJO=3.9e-9 M=0.65 TT=4.8e-8 XTI=4.2) .MODEL DbreakMOD D (RS=0.17 TRS1=3.0e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=1.0e-9 IS=1.0e-30 N=10 M=0.6) .MODEL MmedMOD NMOS (VTO=3.55 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.01) .MODEL MstroMOD NMOS (VTO=4.2 KP=145 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=2.9 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=10.1 RS=0.1) .MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-9.0e-7) .MODEL RdrainMOD RES (TC1=9.0e-3 TC2=3.5e-5) .MODEL RSLCMOD RES (TC1=3.4e-3 TC2=1.5e-6) .MODEL RsourceMOD RES (TC1=4.0e-3 TC2=1.0e-6) .MODEL RvthresMOD RES (TC1=-4.1e-3 TC2=-1.4e-5) .MODEL RvtempMOD RES (TC1=-4.0e-3 TC2=3.5e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.0 VOFF=-4.0) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=-6.0) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.4 VOFF=1.0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.0 VOFF=-1.4) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2002 Fairchild Semiconductor Corporation 8 www.fairchildsemi.com FDP2532 / FDB2532 Rev. C2

F SABER Electrical Model D P 2 REV April 2002 5 ttemplate FDB2532 n2,n1,n3 3 electrical n2,n1,n3 2 { / var i iscl F dp..model dbodymod = (isl=6.0e-11,nl=1.09,rs=2.3e-3,trs1=3.0e-3,trs2=1.0e-6,cjo=3.9e-9,m=0.65,tt=4.8e-8,xti=4.2) D dp..model dbreakmod = (rs=0.17,trs1=3.0e-3,trs2=-8.9e-6) B dp..model dplcapmod = (cjo=1.0e-9,isl=10.0e-30,nl=10,m=0.6) 2 m..model mmedmod = (type=_n,vto=3.55,kp=10,is=1e-30, tox=1) 5 3 m..model mstrongmod = (type=_n,vto=4.2,kp=145,is=1e-30, tox=1) 2 m..model mweakmod = (type=_n,vto=2.9,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-6.0,voff=-4.0) LDRAIN — sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-4.0,voff=-6.0) DPLCAP 5 DR2AIN N sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.4,voff=1.0) 10 - sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=1.0,voff=-1.4) RSLC1 RLDRAIN C c.ca n12 n8 = 1.4e-9 51 h c.cb n15 n14 = 1.6e-9 RSLC2 a n c.cin n6 n8 = 5.61e-9 ISCL n 50 DBREAK e dp.dbody n7 n5 = model=dbodymod - l ddpp..ddbprlceaapk nn150 n n151 == mmooddeell==ddpblrceaapkmmoodd ESG +68 EVTHRES RDR1A6IN 11 DBODY Pow spe.ebreak n11 n7 n17 n18 = 159 LGATE EVTEMP + 189 - 21 MWEAK e ssssspppppeeeee.....eeeeevdgsvtgtsshe rmnnne116ps43 nnn nn1268800 n nnn2n56616 nnnnn88811 98=== nn11182 2= = 1 1 GA1TE RLGATE 9RGATE20+ 1282 - 6 CIN MSTR8OMMED EBREA+K-1178 7 LSOURCE SOU3RCE rTrench ® RSOURCE i.it n8 n17 = 1 RLSOURCE M S1A S2A O l.lgate n1 n9 = 9.56e-9 12 13 14 15 17 RBREAK 18 S 8 13 l.ldrain n2 n5 = 1.0e-9 F l.lsource n3 n7 = 7.71e-9 S1B S2B RVTEMP E CA 13 CB 19 T res.rlgate n1 n9 = 95.6 ++ + 14 IT - res.rldrain n2 n5 = 10 6 5 VBAT res.rlsource n3 n7 = 77.1 EGS 8 EDS 8 + -- - 8 22 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u RVTHRES m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-9.0e-7 res.rdrain n50 n16 = 9.6e-3, tc1=9.0e-3,tc2=3.5e-5 res.rgate n9 n20 = 1.01 res.rslc1 n5 n51 = 1.0e-6, tc1=3.4e-3,tc2=1.5e-6 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 3.0e-3, tc1=4.0e-3,tc2=1.0e-6 res.rvthres n22 n8 = 1, tc1=-4.1e-3,tc2=-1.4e-5 res.rvtemp n18 n19 = 1, tc1=-4.0e-3,tc2=3.5e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/190))** 3)) } } ©2002 Fairchild Semiconductor Corporation 9 www.fairchildsemi.com FDP2532 / FDB2532 Rev. C2

F SPICE Thermal Model D P 2 th JUNCTION 5 REV 26 February 2002 3 2 FDB2532 / F CTHERM1 TH 6 7.5e-3 D CTHERM2 6 5 8.0e-3 B CTHERM3 5 4 9.0e-3 RTHERM1 CTHERM1 2 CTHERM4 4 3 2.4e-2 5 3 CTHERM5 3 2 3.4e-2 2 CTHERM6 2 TL 6.5e-2 — 6 RTHERM1 TH 6 3.1e-4 N RTHERM2 6 5 2.5e-3 - RTHERM3 5 4 2.0e-2 C RTHERM4 4 3 8.0e-2 RTHERM2 CTHERM2 h RTHERM5 3 2 1.2e-1 a n RTHERM6 2 TL 1.3e-1 n 5 e SABER Thermal Model l P o SABER thermal model FDB2532 w template thermal_model th tl RTHERM3 CTHERM3 e thermal_c th, tl r { T cctthheerrmm..cctthheerrmm12 t6h 56 ==87..05ee--33 4 ren ctherm.ctherm3 5 4 =9.0e-3 c ctherm.ctherm4 4 3 =2.4e-2 h ® ctherm.ctherm5 3 2 =3.4e-2 RTHERM4 CTHERM4 ctherm.ctherm6 2 tl =6.5e-2 M O rrtherm.rtherm1 th 6 =3.1e-4 S rtherm.rtherm2 6 5 =2.5e-3 3 F rtherm.rtherm3 5 4 =2.0e-2 E rtherm.rtherm4 4 3 =8.0e-2 T rtherm.rtherm5 3 2 =1.2e-1 RTHERM5 CTHERM5 rtherm.rtherm6 2 tl =1.3e-1 } 2 RTHERM6 CTHERM6 tl CASE ©2002 Fairchild Semiconductor Corporation 10 www.fairchildsemi.com FDP2532 / FDB2532 Rev. C2

F D Mechanical Dimensions P 2 5 3 TO-220 3L 2 / F D B 2 5 3 2 — N - C h a n n e l P o w e r T r e n c h ® M O S F E T Figure 22. TO-220, Molded, 3Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif- ically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TT220-003 Dimension in Millimeters ©2002 Fairchild Semiconductor Corporation 11 www.fairchildsemi.com FDP2532 / FDB2532 Rev. C2

F D Mechanical Dimensions P 2 5 2 3 TO-263 2L (D PAK) 2 / F D B 2 5 3 2 — N - C h a n n e l P o w e r T r e n c h ® M O S F E T Figure 23. 2LD, TO263, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif- ically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TT263-002 Dimension in Millimeters ©2002 Fairchild Semiconductor Corporation 12 www.fairchildsemi.com FDP2532 / FDB2532 Rev. C2

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A critical component in any component of a life support, device, or intended for surgical implant into the body or (b) support or sustain life, system whose failure to perform can be reasonably expected to cause and (c) whose failure to perform when properly used in accordance with the failure of the life support device or system, or to affect its safety or instructions for use provided in the labeling, can be reasonably effectiveness. expected to result in a significant injury of the user. ANTI-COUNTERFEITING POLICY Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support. Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Datasheet contains the design specifications for product development. Specifications Advance Information Formative / In Design may change in any manner without notice. Datasheet contains preliminary data; supplementary data will be published at a later Preliminary First Production date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Datasheet contains final specifications. Fairchild Semiconductor reserves the right to No Identification Needed Full Production make changes at any time without notice to improve the design. Datasheet contains specifications on a product that is discontinued by Fairchild Obsolete Not In Production Semiconductor. The datasheet is for reference information only. Rev. I66 ©2002 Fairchild Semiconductor Corporation 13 www.fairchildsemi.com FDP2532 / FDB2532 Rev. C2

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