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F D B 1 January 2014 3 A N FDB13AN06A0 0 6 A ® N-Channel PowerTrench MOSFET 0 — 60 V, 62 A, 13.5 mΩ N Features Applications - C • rDS(on) = 11.5 mΩ ( Typ.) @ VGS = 10 V, ID = 62 A • Motor Load Control ha n • Qg(tot) = 22 nC ( Typ.) @ VGS = 10 V • DC-DC converters and Off-line UPS n e • Low Miller Charge • Distributed Power Architectures and VRMs l P • Low Qrr Body Diode o w • UIS Capability (Single Pulse and Repetitive Pulse) e r T Formerly developmental type 82555 re n c h D ® M O D S F E G T G S D2-PAK S MOSFET Maximum Ratings TC = 25°C unless otherwise noted Symbol Parameter Ratings Units V Drain to Source Voltage 60 V DSS V Gate to Source Voltage ±20 V GS Drain Current Continuous (T = 25oC, V = 10V) 62 A C GS I Continuous (T = 100oC, V = 10V) 44 A D C GS Continuous (TA = 25oC, VGS = 10V, RθJA = 43oC/W) 10.9 A Pulsed Figure 4 A E Single Pulse Avalanche Energy (Note 1) 56 mJ AS Power dissipation 115 W P D Derate above 25oC 0.77 W/oC T , T Operating and Storage Temperature -55 to 175 oC J STG Thermal Characteristics RθJC Thermal Resistance Junction to Case 1.3 oC/W RθJA Thermal Resistance Junction to Ambient (Note 2) 62 oC/W RθJA Thermal Resistance Junction to Ambient, 1in2 copper pad area 43 oC/W ©2012 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDB13AN06A0 Rev. C2

F D Package Marking and Ordering Information B 1 Device Marking Device Package Reel Size Tape Width Quantity 3 FDB13AN06A0 FDB13AN06A0 D2-PAK 330 mm 24 mm 800 units A N 0 6 Electrical Characteristics T = 25°C unless otherwise noted A C 0 Symbol Parameter Test Conditions Min Typ Max Units — Off Characteristics N - B Drain to Source Breakdown Voltage I = 250µA, V = 0V 60 - - V C VDSS D GS h I Zero Gate Voltage Drain Current VDS = 50V - - 1 µA a DSS V = 0V T = 150oC - - 250 n GS C n IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA e l P On Characteristics o w V Gate to Source Threshold Voltage V = V , I = 250µA 2 - 4 V GS(TH) GS DS D e I = 62A, V = 10V - 0.0115 0.0135 r D GS T I = 31A, V = 6V - 0.022 0.034 r r Drain to Source On Resistance D GS Ω e DS(ON) I = 62A, V = 10V, n TDJ = 175oCGS - 0.026 0.030 ch ® Dynamic Characteristics M O C Input Capacitance - 1350 - pF ISS V = 25V, V = 0V, S C Output Capacitance DS GS - 260 - pF F OSS f = 1MHz E C Reverse Transfer Capacitance - 90 - pF RSS T Q Total Gate Charge at 10V V = 0V to 10V 22 29 nC g(TOT) GS Qg(TH) Threshold Gate Charge VGS = 0V to 2V VDD = 30V - 2.6 3.4 nC Q Gate to Source Gate Charge I = 62A - 8.5 - nC gs D Qgs2 Gate Charge Threshold to Plateau Ig = 1.0mA - 5.9 - nC Q Gate to Drain “Miller” Charge - 6.4 - nC gd Switching Characteristics (V = 10V) GS t Turn-On Time - - 158 ns ON t Turn-On Delay Time - 9 - ns d(ON) tr Rise Time VDD = 30V, ID = 62A - 96 - ns td(OFF) Turn-Off Delay Time VGS = 10V, RGS = 12Ω - 24 - ns t Fall Time - 26 - ns f t Turn-Off Time - - 74 ns OFF Drain-Source Diode Characteristics I = 62A - - 1.25 V V Source to Drain Diode Voltage SD SD I = 31A - - 1.0 V SD t Reverse Recovery Time I = 62A, dI /dt = 100A/µs - - 25 ns rr SD SD Q Reverse Recovered Charge I = 62A, dI /dt = 100A/µs - - 17 nC RR SD SD Notes: 1: Starting TJ = 25°C, L = 45µH, IAS = 50A. 2: Pulse width = 100s. ©2012 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FDB13AN06A0 Rev. C2

F D Typical Characteristics TC = 25°C unless otherwise noted B 1 3 1.2 80 A N R 1.0 0 E 6 MULTIPLI 0.8 RENT (A)60 A0 — N R ATIO 0.6 N CU40 N R DISSIP 0.4 I, DRAID20 -Cha WE 0.2 n O n P e 0 0 Pl 0 25 50 75 100 125 150 175 25 50 75 100 125 150 175 o TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC) w e r Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs T Ambient Temperature Case Temperature r e n c 2 h DUTY CYCLE - DESCENDING ORDER ® 1 0.5 M 0.2 O 0.1 0.05 S DCE 0.02 F ZEAN 0.01 E ORMALIL IMPED 0.1 PDM T NA Z, θJCHERM t1t2 T NOTES: DUTY FACTOR: D = t1/t2 SINGLE PULSE PEAK TJ = PDM x ZθJC x RθJC + TC 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 800 TC = 25oC FOR TEMPERATURES TRANSCONDUCTANCE ABOVE 25oC DERATE PEAK A) MAY LIMIT CURRENT CURRENT AS FOLLOWS: ENT ( IN THIS REGION I = I25 175 - TC RR VGS = 10V 150 U C K EA 100 P , M D I 30 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) Figure 4. Peak Current Capability ©2012 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FDB13AN06A0 Rev. C2

F D Typical Characteristics TC = 25°C unless otherwise noted B 1 3 1000 100 If R = 0 A 10µs ItfA VR =≠ (0L)(IAS)/(1.3*RATED BVDSS - VDD) N0 A) tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 6 RENT (A) 100 100µs URRENT ( STARTING TJ = 25oC A0 — R C CU 10 OPERATION IN THIS 1ms HE 10 N DRAIN LIMIATREEDA B MY ArDYS B(OEN) ALANC STARTING TJ = 150oC -Ch I, D 1 TTSJCIN ==G M2L5AEoX CP RUALTSEED DC 10ms I, AVAS annel 0.1 1 P 1 10 100 0.01 0.1 1 10 100 o VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms) w e Figure 5. Forward Bias Safe Operating Area NOTE:RefertoFairchildApplicationNotesAN7514andAN7515 rT Figure 6. Unclamped Inductive Switching r e Capability n c h ® 100 100 PULSE DURATION = 80µs TC = 25oC VGS = 20V M DUTY CYCLE = 0.5% MAX O 80 VDD = 15V 80 S A) A) VGS = 10V F RENT ( 60 RENT ( 60 ET R R CU CU VGS = 6V AIN 40 TJ = 175oC AIN 40 R R I, DD TJ = 25oC TJ = -55oC I, DD PDUULTSYE C DYUCRLEA T=I O0N.5 %= 8M0AµsX 20 20 VGS = 5V 0 0 33 4 5 7 0 0.5 1.0 1.5 2.0 VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics 30 2.5 Ω) PULSE DURATION = 80µs PULSE DURATION = 80µs m DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX STANCE( 25 SOURCEE2.0 ON RESI 20 VGS = 6V RAIN TO SISTANC1.5 E DE RC ED N R U ZO O LI O S 15 MA 1.0 T R AIN VGS = 10V NO R D 10 VGS = 10V, ID =62A 0.5 0 10 20 30 40 50 60 70 -80 -40 0 40 80 120 160 200 ID, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE (oC) Figure 9. Drain to Source On Resistance vs Drain Figure 10. Normalized Drain to Source On Current Resistance vs Junction Temperature ©2012 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FDB13AN06A0 Rev. C2

F D Typical Characteristics TC = 25°C unless otherwise noted B 1 3 1.4 1.2 A VGS = VDS, ID = 250µA ID = 250µA N E 0 1.2 RC 6 NORMALIZED GATEHRESHOLD VOLTAGE01..80 ALIZED DRAIN TO SOUREAKDOWN VOLTAGE 11..01 A0 — N-Cha T0.6 RMB n O n N e l 0.4 P -80 -40 0 40 80 120 160 200 0.9-80 -40 0 40 80 120 160 200 o TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) w e r Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source T Junction Temperature Breakdown Voltage vs Junction Temperature re n c h 3000 10 ® VDD = 30V M V) E (pF)1000 COSS ≅ CDS + CGD CISS = CGS + CGD VOLTAGE (8 OSFE C E 6 T N C A R CIT OU C, CAPA CRSS = CGD ATE TO S4 WAVEFORMS IN 100 , GGS2 DESCIDE =N 6D2INAG ORDER: VGS = 0V, f = 1MHz V ID = 31A 40 0 0.1 1 10 60 0 5 10 15 20 25 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant Voltage Gate Current ©2012 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FDB13AN06A0 Rev. C2

F D Test Circuits and Waveforms B 1 3 A VDS N BVDSS 06 A L tP 0 VDS — VRAERQYU ItRP ETDO POEBATKA IINAS RG +VDD IAS VDD N- VGS - C h DUT a n tP n 0V IAS e 0.01Ω 0 Pl o tAV w e r T Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms r e n c h VDS ® VDD Qg(TOT) M O L VDS VGS VGS = 10V SF VGS + E T VDD Qgs2 - DUT Ig(REF) VGS = 2V 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr tf VDS 90% 90% + VGS VDD 10% 10% - 0 DUT 90% RGS VGS 50% 50% PULSE WIDTH VGS 10% 0 Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms ©2012 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com FDB13AN06A0 Rev. C2

F D Thermal Resistance vs. Mounting Pad Area B 1 The maximum rated junction temperature, TJM, and the 80 3 tthhee rmmaaxl imreusimst aanllocew aobf leth dee hviecaet pdoiswseipr adtiisnsgip paatitohn ,d Peterm, inin aens RθJA = 26.51+ 19.84/(0.262+Area) EQ.2 AN DM application. Therefore the application’s ambient RθJA = 26.51+ 128/(1.69+Area) EQ.3 0 6 temperature, TA (oC), and thermal resistance RθJA (oC/W) A must be reviewed to ensure that T is never exceeded. 60 0 JM W) Equation 1 mathematically represents the relationship and C/ — serPves a=s -(t--hT---e-J---M --b----–a----s-T---iA-s----) for establishing the rating of th(eE Qpa. r1t). oR(θJA 40 N-C DM RθJA ha n n In using surface mount devices such as the TO-263 e package, the environment in which it is applied will have a 20 l P significant influence on the part’s current and maximum 0.1 1 10 o power dissipation ratings. Precise determination of PDM is (0.645) (6.45) (64.5) w complex and influenced by many factors: AREA, TOP COPPER AREA in2 (cm2) e Figure 21. Thermal Resistance vs Mounting r T 1. Mounting pad area onto which the device is attached and Pad Area r whether there is copper on one side or both sides of the e n board. c h 2. The number of copper layers and the thickness of the ® board. M O 3.The use of external heat sinks. S F 4.The use of thermal vias. E T 5.Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. 19.84 RθJA = 26.51+(---0---.-2---6---2-----+-----A----r---e---a---)- (EQ. 2) Area in Inches Squared 128 RθJA = 26.51+(---1---.-6---9-----+-----A----r---e---a----) (EQ. 3) Area in Centimeters Squared ©2012 Fairchild Semiconductor Corporation 7 www.fairchildsemi.com FDB13AN06A0 Rev. C2

F PSPICE Electrical Model D B .SUBCKT FDB13AN06A0 2 1 3 ; rev August 2002 1 Ca 12 8 5.1e-10 3 A Cb 15 14 5.1e-10 LDRAIN Cin 6 8 1.3e-9 DPLCAP 5 DRAIN N 2 0 10 6 Dbody 7 5 DbodyMOD RLDRAIN A Dbreak 5 11 DbreakMOD 5R1SLC1 DBREAK 0 Dplcap 10 5 DplcapMOD RSLC2 + — 5 Ebreak 11 7 17 18 65.40 51- ESLC 11 N EEEdgsgss 11643 1 880 566 888 111 ESG -68 R50DRAIN EBREAK +1178 DBODY -Ch Evthres 6 21 19 8 1 + EVTHRES 16 - a Evtemp 20 6 18 22 1 LGATE EVTEMP + 189 - 21 MWEAK nn GATE RGATE + 18 - 6 e ILLtd g8ra a1tein7 121 95 61..90ee--99 1 RLGATE 9 20 22 CIN MSTR8OMMED 7 LSOURCE SOU3RCE Powel Lsource 3 7 2.91e-9 RSOURCE r RLSOURCE T RLgate 1 9 69 S1A S2A re RRLLdsorauirnc e2 35 71 029.1 12 183 1143 15 17 RBREAK 18 nc h MMMmswtereoad k 11 616 6 66 2 881 8 88 M M8s mMtreowdMeMOaOkDMD OD CA S1B 13++6S2B CB+514 IT -R19VVTBEAMTP MO® EGS 8 EDS 8 + S Rbreak 17 18 RbreakMOD 1 -- - 8 F Rdrain 50 16 RdrainMOD 3.0e-3 22 E Rgate 9 20 3.77 RVTHRES T RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 5.5e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*160),6))} .MODEL DbodyMOD D (IS=1.5E-11 N=1.08 RS=3.3e-3 TRS1=2.2e-3 TRS2=2.5e-9 + CJO=0.9e-9 M=5.1e-1 TT=1e-9 XTI=3.9) .MODEL DbreakMOD D (RS=1.5e-1 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=4.1e-10 IS=1e-30 N=10 M=0.45) .MODEL MmedMOD NMOS (VTO=3.5 KP=6 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.77) .MODEL MstroMOD NMOS (VTO=4.3 KP=50 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=2.88 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.77e+1 RS=0.1) .MODEL RbreakMOD RES (TC1=9e-4 TC2=-5e-7) .MODEL RdrainMOD RES (TC1=1.5e-2 TC2=4e-5) .MODEL RSLCMOD RES (TC1=1.8e-3 TC2=1.7e-5) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-5.3e-3 TC2=-1.0e-5) .MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=1e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-2) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-5) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1.5) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank * Wheatley. ©2012 Fairchild Semiconductor Corporation 8 www.fairchildsemi.com FDB13AN06A0 Rev. C2

F SABER Electrical Model D B rev August 2002 1 3 template FDB13AN06A0 n2,n1,n3 A electrical n2,n1,n3 N { 0 var i iscl 6 dp..model dbodymod = (isl=1.5e-11,nl=1.08,rs=3.3e-3,trs1=2.2e-3,trs2=2.5e-9,cjo=0.9e-9,m=5.1e-1,tt=1e-9,xti=3.9) A dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6) 0 dp..model dplcapmod = (cjo=4.1e-10,isl=10e-30,nl=10,m=0.45) — m..model mmedmod = (type=_n,vto=3.5,kp=6,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.3,kp=50,is=1e-30, tox=1) N m..model mweakmod = (type=_n,vto=2.88,kp=0.05,is=1e-30, tox=1,rs=0.1) - sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5,voff=-2) LDRAIN C DPLCAP 5 DRAIN h sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-5) 2 a sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=0.5) 10 n sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1.5) RSLC1 RLDRAIN n c.ca n12 n8 = 5.1e-10 51 e c.cb n15 n14 = 5.1e-10 RSLC2 l c.cin n6 n8 = 1.3e-9 ISCL P o 50 DBREAK w dp.dbody n7 n5 = model=dbodymod - ddspppe..dd.ebpbrlceraeapak k nn 1n501 n 1n1 5n1 7 == n mm1o7o ddnee1ll=8=d d=pb l6rce5aa.p4km0moodd LGATE EVETSEGM+P68 E+VT18H9RE-S 2R1DR1A6IN MWEAK11 DBODY erTren ssppee..eedgss nn1143 nn88 nn56 nn88 == 11 GA1TE 9RGATE20+ 1282 - 6 MMED EBREA+K ch ssspppeee...eeevsvtgthe rmne6ps nnn12600 n n2n616 nnn811 98= nn182 2= = 1 1 RLGATE CIN MSTR8O -1178 7 LSOURCESOU3RCE MO® RSOURCE S i.it n8 n17 = 1 RLSOURCE F S1A S2A E l.lgate n1 n9 = 6.9e-9 12 13 14 15 17 RBREAK 18 T 8 13 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2.91e-9 S1B S2B RVTEMP CA 13 CB 19 res.rlgate n1 n9 = 69 ++ + 14 IT - res.rldrain n2 n5 = 10 6 5 VBAT res.rlsource n3 n7 = 29.1 EGS 8 EDS 8 + -- - 8 22 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u RVTHRES m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=9e-4,tc2=-5e-7 res.rdrain n50 n16 = 3.0e-3, tc1=1.5e-2,tc2=4e-5 res.rgate n9 n20 = 3.77 res.rslc1 n5 n51 = 1e-6, tc1=1.8e-3,tc2=1.7e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 5.5e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1.0e-5 res.rvtemp n18 n19 = 1, tc1=-2.5e-3,tc2=1e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/160))** 6)) } ©2012 Fairchild Semiconductor Corporation 9 www.fairchildsemi.com FDB13AN06A0 Rev. C2

F SPICE Thermal Model D B th JUNCTION 1 REV 23 March 2002 3 A FDB13AN06A0T N CTHERM1 TH 6 9.7e-4 0 6 CTHERM2 6 5 6.2e-3 A CTHERM3 5 4 4.6e-3 0 CTHERM4 4 3 4.9e-3 RTHERM1 CTHERM1 — CTHERM5 3 2 8e-3 CTHERM6 2 TL 4.2e-2 N - RTHERM1 TH 6 5.24e-2 6 C RTHERM2 6 5 10.08e-2 h RTHERM3 5 4 4.28e-1 a n RTHERM4 4 3 1.8e-1 RTHERM2 CTHERM2 n RTHERM5 3 2 1.9e-1 e RTHERM6 2 TL 2.1e-1 l P SABER Thermal Model 5 o w SABER thermal model FDB14AN06A0T e r template thermal_model th tl T thermal_c th, tl RTHERM3 CTHERM3 r e { n ctherm.ctherm1 th 6 =9.7e-4 c ctherm.ctherm2 6 5 =6.2e-3 h ctherm.ctherm3 5 4 =4.6e-3 4 ® ctherm.ctherm4 4 3 =4.9e-3 M ctherm.ctherm5 3 2 =8e-3 O ctherm.ctherm6 2 tl =4.2e-2 RTHERM4 CTHERM4 S F rtherm.rtherm1 th 6 =5.24e-2 E rtherm.rtherm2 6 5 =10.08e-2 T rtherm.rtherm3 5 4 =4.28e-1 3 rtherm.rtherm4 4 3 =1.8e-1 rtherm.rtherm5 3 2 =1.9e-1 rtherm.rtherm6 2 tl =2.1e-1 RTHERM5 CTHERM5 } 2 RTHERM6 CTHERM6 tl CASE ©2012 Fairchild Semiconductor Corporation 10 www.fairchildsemi.com FDB13AN06A0 Rev. C2

F D Mechanical Dimensions B 1 3 A N 0 6 A 0 — N - C h a n n e l P o w e r T r e n c h ® M O S F E T Figure 22. TO263 (D2PAK), Molded, 2-Lead, Surface Mount Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif- ically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TT263-002 ©2012 Fairchild Semiconductor Corporation 11 www.fairchildsemi.com FDB13AN06A0 Rev. C2

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Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Datasheet contains the design specifications for product development. Specifications Advance Information Formative / In Design may change in any manner without notice. Datasheet contains preliminary data; supplementary data will be published at a later Preliminary First Production date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Datasheet contains final specifications. Fairchild Semiconductor reserves the right to No Identification Needed Full Production make changes at any time without notice to improve the design. Datasheet contains specifications on a product that is discontinued by Fairchild Obsolete Not In Production Semiconductor. The datasheet is for reference information only. Rev. I66 ©2012 Fairchild Semiconductor Corporation 12 www.fairchildsemi.com FDB13AN06A0 Rev. C2

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