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F A N 7 3 October 2012 8 3 3 — FAN73833 H a Half-Bridge Gate-Drive IC lf - B r i d Features Description g e  Floating Channel for Bootstrap Operation to +600V The FAN73833 is a half-bridge gate-drive IC for driving G  Typically 350 mA / 650 mA Sourcing/Sinking Current MOSFETs and IGBTs, operating up to +600 V. at e Driving Capability for Both Channels Fairchild’s high-voltage process and common-mode - D  Extended Allowable Negative VS Swing to -9.8 V for noise canceling technique provide stable operation of ri Signal Propagation at VDD=VBS=15 V high-side driver under high dv/dt noise circumstances. ve  3.3 V and 5 V Input Logic Compatible An advanced level-shift circuit allows high-side gate IC  Outputs in Phase with Input Signals driver operation up to V =-9.8 V (typical) for V =15 V. S BS  Built-in UVLO Functions for Both Channels The UVLO circuits for both channels prevent malfunction  Built-on Shoot-Through Prevention Circuit when V and V are lower than the specified thresh- DD BS  Built-in Common-Mode dv/dt Noise Canceling Circuit old voltage.  Internal Dead-Time Typically 400 ns Output drivers typically source/sink 350 mA / 650 mA, respectively, which is suitable for all kinds of half- and full-bridge inverters. Applications  SMPS  Motor Drive Inverter 8-SOP  Fluorescent Lamp Ballast  HID Ballast Ordering Information Part Number Package Operating Temperature Range Packing Method FAN73833M Tube 8-SOP -40°C to +125°C FAN73833MX Tape & Reel © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73833 • Rev. 1.0.2

F A Typical Application Circuit N 7 3 8 3 3 Up to 600V — R D BOOT BOOT V H DD a l f - B r LIN 1 LIN VB 8 id g e HIN 2 HIN HO 7 G a CBOOT te 3 VDD VS 6 Load -D r i v 4 COM LO 5 e I C Figure 1. Application Circuit for Half-Bridge Internal Block Diagram 8 VB UVLO D R GE IV 7 HO NERAPULS CANNCOEISLELER RS R Q ER TE O R 6 VS SCHMITT HS(ON/OFF) TRIGGER INPUT HIN 2 UVLO 3 VDD 100K SHOOT-THROUGH PREVENTION D R LIN 1 LS(ON/OFF) DELAY IV 5 LO DEAD-TIME E 100K { 400ns } R 4 COM Figure 2. Functional Block Diagram © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73833 • Rev.1.0.2 2

F A Pin Configuration N 7 3 8 3 3 LIN 1 F 8 VB — A H HIN 2 N 7 HO a l 7 f - V 3 3 6 V B DD 8 S ri d 3 g COM 4 3 5 LO e G a t e - D Figure 3. Pin Configuration (Top View) r i v e I Pin Definitions C Pin # Name Description 1 LIN Logic Input for Low-Side Driver 2 HIN Logic Input for High-Side Driver 3 V Low-Side Supply Voltage DD 4 COM Logic Ground and Low-Side Driver Return 5 LO Low-Side Driver Output 6 V High-Side Floating Supply Return S 7 HO High-Side Driver Output 8 V High-Side Floating Supply B © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73833 • Rev.1.0.2 3

F A Absolute Maximum Ratings N 7 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera- 8 ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi- 3 3 tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. T =25°C, unless otherwise specified. — A H Symbol Parameter Min. Max. Unit a l VS High-side offset voltage VB-25 VB+0.3 V f-B V High-side floating supply voltage -0.3 625 V r B i d V High-side floating output voltage HO V -0.3 V +0.3 V g HO S B e VDD Low-side and logic-fixed supply voltage -0.3 25 V G a VLO Low-side output voltage LO -0.3 VDD+0.3 V te VIN Logic input voltage (HIN/LIN) -0.3 VDD+0.3 V -D r COM Logic ground and low-side driver return V -25 V +0.3 V i DD DD v e dVS/dt Allowable offset voltage slew rate 50 V/ns I C P (1)(2)(3) Power dissipation 0.625 W D  Thermal resistance, junction-to-ambient 200 C/W JA T Junction temperature 150 C J T Storage temperature -55 150 C STG Notes: 1. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR-4 glass epoxy material). 2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages 3. Do not exceed P under any circumstances. D Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit V High-side floating supply voltage V +11 V +20 V B S S V High-side floating supply offset voltage 6-V 600 V S DD V Low-side supply voltage 11 20 V DD V High-side (HO) output voltage V V V HO S B V Low-side (LO) output voltage COM V V LO DD V Logic input voltage (HIN/LIN) COM V V IN DD T Ambient temperature -40 125 C A © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73833 • Rev.1.0.2 4

F A Electrical Characteristics N 7 3 V (V , V ) = 15.0 V, andT =25C, unless otherwise specified. The V and I parameters are referenced to BIAS DD BS A IN IN 8 COM. The V and I parameters are referenced to V and COM and are applicable to respective outputs HO and LO. 3 O O S 3 Symbol Parameter Condition Min. Typ. Max. Unit — SUPPLY CURRENT SECTION H a IQBS Quiescent VBS supply current VIN=0 V or 5 V 35 100 µA lf - I Quiescent V supply current V =0 V or 5 V 80 200 µA B QDD DD IN r i I Operating V supply current f =20 kHz, rms value 420 750 µA d PBS BS IN g I Operating V supply current f =20 kHz, rms value 420 750 µA e PDD DD IN G ILK Offset supply leakage current VB=VS=600 V 10 µA a t POWER SUPPLY SECTION e - D VDDUV+ VDD and VBS supply under-voltage  8.2 9.2 10.1 V ri V positive going threshold v BSUV+ e VDDUV- VDD and VBS supply under-voltage  7.2 8.3 9.2 V IC V negative going threshold BSUV- V V supply under-voltage lockout  DDUVH DD 0.9 V V hysteresis BSUVH GATE DRIVER OUTPUT SECTION V High-level output voltage, V -V I =20 mA 1.0 V OH BIAS O O V Low-level output voltage, V 0.6 V OL O I (4) Output high short-circuit pulse current V =0 V, V =5 V with PW<10 µs 250 350 mA O+ O IN I (4) Output low short-circuit pulsed current V =15 V, V =0 V with PW<10 µs 500 650 mA O- O IN Allowable negative V pin voltage for V S -9.8 -7.0 V S IN signal propagation to HO LOGIC INPUT SECTION (INPUT and SHUTDOWN) V Logic "1" input voltage 2.5 V IH V Logic "0" input voltage 1.2 V IL I Logic "1" input bias current V =5 V 50 100 µA IN+ IN I Logic "0" input bias current V =0 V 2.0 µA IN- IN R Input pull-down resistance 100 K PD Note: 4. This parameter is guaranteed by design. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73833 • Rev.1.0.2 5

F A Dynamic Electrical Characteristics N 7 V (V , V )=15.0 V, V =COM, C =1000 pF, and T = 25C, unless otherwise specified. 3 BIAS DD BS S L A 8 3 Symbol Parameter Conditions Min. Typ. Max. Unit 3 — t Turn-on propagation delay time V =0 V 150 270 ns ON S H t Turn-off propagation delay time V =0 V 140 250 ns OFF S a t Turn-on rising time 50 100 ns lf R - B tF Turn-off falling time 30 80 ns r i d DT Dead-time 330 450 580 ns g e G a t e - D r i v e I C © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73833 • Rev.1.0.2 6

F A Typical Characteristics N 7 3 8 3 3 300 300 — 250 250 H a l t [ns] ON 125000 t [ns] OFF 125000 f-Bridg 100 100 e G 50 50 a t e 0 0 -D -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 r Temperature [°C] Temperature [°C] iv e I C Figure 4. Turn-on Propagation Delay vs. Temp. Figure 5. Turn-off Propagation Delay vs. Temp. 120 80 100 60 s] 80 s] n n t [R 60 t [F 40 40 20 20 0 0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 6. Turn-on Rise Time vs. Temp. Figure 7. Turn-off Fall Time vs. Temp. 700 100 600 80 ] T [ns] 500 [AN+ 60 D II 400 40 300 20 200 0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 8. Dead Time vs. Temp. Figure 9. Logic Input High Bias Current vs. Temp. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73833 • Rev.1.0.2 7

F A Typical Characteristics (Continued) N 7 3 8 3 3 200 100 — H 160 80 a l f - ]A 120 ]A 60 Br   i [ [ d I QDD 80 I QBS 40 ge G 40 20 a t e - 0 0 D -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 r i v Temperature [°C] Temperature [°C] e I C Figure 10. Quiescent V Supply Current Figure 11. Quiescent V Supply Current DD BS vs. Temp. vs. Temp. 750 750 600 600 ]A 450 ]A 450 [I PDD300 [I PBS300 150 150 0 0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 12. Operating V Supply Current vs. Temp. Figure 13. Operating V Supply Current vs. Temp. DD BS 10.0 9.2 8.8 9.6 V] V] 8.4 V [DDUV+9.2 V [DDUV- 8.0 8.8 7.6 8.4 7.2 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 14. V UVLO+ vs. Temp. Figure 15. V UVLO- vs. Temp. DD DD © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73833 • Rev. 1.0.2 8

F A Typical Characteristics (Continued) N 7 3 8 3 3 10.0 9.2 — H 9.6 8.8 a l f - V] V] 8.4 B V [BSUV+ 9.2 V [BSUV- 8.0 ridge 8.8 G 7.6 a t 8.4 e - 7.2 D -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 r i v Temperature [°C] Temperature [°C] e I C Figure 16. V UVLO+ vs. Temp. Figure 17. V UVLO- vs. Temp. BS BS 1.0 0.6 0.5 0.8 0.4 V] 0.6 V] V [OH 0.4 V [OL 0.3 0.2 0.2 0.1 0.0 0.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 18. High-Level Output Voltage vs. Temp. Figure 19. Low-Level Output Voltage vs. Temp. 3.0 3.0 2.5 2.5 2.0 2.0 V [V] IH 1.5 V [V] IL 1.5 1.0 1.0 0.5 0.5 0.0 0.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 20. Logic High Input Voltage vs. Temp. Figure 21. Logic Low Input Voltage vs. Temp. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73833 • Rev. 1.0.2 9

F A Typical Characteristics (Continued) N 7 3 8 3 3 0 — -2 H a l -4 f - B V] -6 ri V [S -8 dg e -10 G a -12 t e - -14 D -40 -20 0 20 40 60 80 100 120 r i v Temperature [°C] e I C Figure 22. Allowable Negative V Voltage vs. Temp. S © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73833 • Rev. 1.0.2 10

F A Application Information N 7 3 8 3 3 1. Protection Function 2. Switching Time Definitions — 1.1 Under-Voltage Lockout (UVLO) H a The high- and low-side drivers include under-voltage LIN 50% 50% 50% lf- lockout (UVLO) protection circuitry for each channel that B r monitors the supply voltage (VDD) and bootstrap capaci- More than More than id tor voltage (V ) independently. It can be designed pre- dead-time dead-time g BS HIN 50% 50% e vent malfunction when V and V are lower than the DD BS G specified threshold voltage. The UVLO hysteresis pre- tOFF tOFF a t vent chattering during power supply transitions. 90% 90% e - LO tON D 1.2 Shoot-Through Prevention Function 10% r i The FAN73833 has shoot-through prevention circuitry tOFF ve 90% monitoring the high- and low-side control inputs. It can tON IC HO be designed to prevent outputs of high and low side from 10% turning on at same time, as shown Figure 23 and 28. Figure 25. Switching Time Definition HIN LIN Shoot-Through Prevent HO After DT LO After DT Figure 23. Waveforms for Shoot-Through Prevention HIN LIN Shoot-Through Prevent HO After DT LO Figure 24. Waveforms for Shoot-Through Prevention © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73833 • Rev.1.0.2 11

F A Mechanical Dimensions N 7 3 8 3 3 (cid:7)(cid:4)(cid:9)(cid:8) — (cid:2) (cid:12) (cid:6)(cid:4)(cid:7)(cid:9)(cid:2) (cid:20) (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:2) H (cid:10)(cid:4)(cid:8)(cid:9) a l (cid:19) f- B (cid:21) (cid:6) r i d (cid:2)(cid:7)(cid:4)(cid:8)(cid:6)(cid:2) g e (cid:5)(cid:4)(cid:11)(cid:3) (cid:10)(cid:4)(cid:7)(cid:6) (cid:2)(cid:6)(cid:4)(cid:5)(cid:3)(cid:2) G (cid:2) (cid:2) (cid:2) (cid:2) (cid:6)(cid:4)(cid:8)(cid:3) (cid:11)(cid:4)(cid:8)(cid:6) a t e - D r i (cid:7) (cid:10) v e (cid:13)(cid:14)(cid:15)(cid:2)(cid:16)(cid:7)(cid:2)(cid:14)(cid:17) (cid:7)(cid:4)(cid:9)(cid:8) IC (cid:2)(cid:3)(cid:4)(cid:11)(cid:6)(cid:2) (cid:3)(cid:4)(cid:9)(cid:6) (cid:18) (cid:12) (cid:19) (cid:20) (cid:30)(cid:20)(cid:15)(cid:17)(cid:2)(cid:13)(cid:20) (cid:29)"(cid:15)(cid:2)"(cid:29)(cid:12)#(cid:18)(cid:18)(cid:29)(cid:15)(cid:17)(cid:20) (cid:14)#(cid:15) #(cid:13)(cid:2)!(cid:14)(cid:29)& (cid:19) (cid:7)(cid:4)(cid:21)(cid:3) (cid:7)(cid:4)(cid:8)(cid:6) (cid:2) (cid:12) (cid:2) (cid:2) (cid:2) (cid:7)(cid:4)(cid:11)(cid:6) (cid:7)(cid:4)(cid:9)(cid:6) (cid:12) (cid:3)(cid:4)(cid:9)(cid:6) (cid:3)(cid:4)(cid:6)(cid:7) (cid:2) (cid:2) (cid:2) (cid:2)(cid:22)(cid:21)(cid:23)(cid:24)(cid:2) (cid:3)(cid:4)(cid:7)(cid:3) (cid:3)(cid:4)(cid:11)(cid:7) #(cid:13) (cid:14)#(cid:15)(cid:2)(cid:20)(cid:2)(cid:26)(cid:2)(cid:19)(cid:29)!(cid:29)(cid:30)(cid:2)(cid:29)(cid:17)(cid:27)(cid:29) (cid:3)(cid:4)(cid:7)(cid:3) (cid:12) ’"#(cid:15) (cid:2)!(cid:14)(cid:29)& (cid:3)(cid:4)(cid:9)(cid:6) (cid:2) (cid:12) (cid:2) (cid:3)(cid:4)(cid:7)(cid:6) #(cid:13) (cid:14)#(cid:15)(cid:2)(cid:19)(cid:2)(cid:26)(cid:2)(cid:15)#(cid:15)(cid:2)(cid:19)(cid:29)!(cid:29)(cid:30)(cid:2)(cid:29)(cid:17)(cid:27)(cid:29) (cid:15)# (cid:29)(cid:31)$(cid:2)(cid:28)(cid:15)(cid:30)(cid:29)(cid:31)(cid:31)(cid:2)# %(cid:29)"&(cid:14)(cid:31)(cid:29)(cid:2)(cid:31)(cid:13)(cid:29)(cid:12)(cid:14)’(cid:14)(cid:29)(cid:17) (cid:19)(cid:29)!(cid:29)(cid:30) (cid:2)(cid:2)(cid:20)(cid:4)(cid:2) %(cid:14)(cid:31)(cid:2)(cid:13)(cid:20)(cid:12)((cid:20)(cid:27)(cid:29)(cid:2)(cid:12)#(cid:15)’#"(cid:18)(cid:31)(cid:2) #(cid:2))(cid:29)(cid:17)(cid:29)(cid:12)(cid:2)(cid:18)(cid:31)(cid:26)(cid:3)(cid:7)(cid:9) (cid:27)(cid:20)(cid:28)(cid:27)(cid:29)(cid:2) (cid:2)(cid:2)(cid:2)(cid:2)(cid:2)(cid:2)(cid:2)!(cid:20)"(cid:14)(cid:20) (cid:14)#(cid:15)(cid:2)(cid:20)(cid:2)(cid:29)(cid:23)(cid:12)(cid:29)(cid:13) (cid:2)&%(cid:29)"(cid:29)(cid:2)(cid:15)# (cid:29)(cid:17)(cid:4) (cid:13)(cid:30)(cid:20)(cid:15)(cid:29) "(cid:3)(cid:4)(cid:7)(cid:3) (cid:2)(cid:2)(cid:19)(cid:4)(cid:2)(cid:20)(cid:30)(cid:30)(cid:2)(cid:17)(cid:14)(cid:18)(cid:29)(cid:15)(cid:31)(cid:14)#(cid:15)(cid:31)(cid:2)(cid:20)"(cid:29)(cid:2)(cid:14)(cid:15)(cid:2)(cid:18)(cid:14)(cid:30)(cid:30)(cid:14)(cid:18)(cid:29) (cid:29)"(cid:31)(cid:4) (cid:31)(cid:29)(cid:20) (cid:14)(cid:15)(cid:27) (cid:3)(cid:4)(cid:9)(cid:6) (cid:2)(cid:2)(cid:12) #(cid:28) (cid:2)#’(cid:2))(cid:29)(cid:17)(cid:29)(cid:12)(cid:2)(cid:31) (cid:20)(cid:15)(cid:17)(cid:20)"(cid:17)(cid:2)!(cid:20)(cid:30)(cid:28)(cid:29)(cid:4) (cid:2)(cid:13)(cid:30)(cid:20)(cid:15)(cid:29) (cid:2)(cid:2)(cid:17)(cid:4)(cid:2)(cid:17)(cid:14)(cid:18)(cid:29)(cid:15)(cid:31)(cid:14)#(cid:15)(cid:31)(cid:2)(cid:20)"(cid:29)(cid:2)(cid:29)(cid:23)(cid:12)(cid:30)(cid:28)(cid:31)(cid:14)!(cid:29)(cid:2)#’(cid:2)(cid:19)(cid:28)""(cid:31)* (cid:2)(cid:18)#(cid:30)(cid:17)(cid:2)’(cid:30)(cid:20)(cid:31)%(cid:2)(cid:20)(cid:15)(cid:17)(cid:2) (cid:14)(cid:29)(cid:2)(cid:19)(cid:20)"(cid:2)(cid:29)(cid:23) "(cid:28)(cid:31)(cid:14)#(cid:15)(cid:31)(cid:4) (cid:2)(cid:10)(cid:25)(cid:26)(cid:2)(cid:21) (cid:2) (cid:2)(cid:2)(cid:29)(cid:4)(cid:2)(cid:30)(cid:20)(cid:15)(cid:17)(cid:2)(cid:13)(cid:20) (cid:29)"(cid:15)(cid:2)(cid:20)(cid:31)(cid:2)(cid:13)(cid:29)"(cid:2)(cid:14)(cid:13)(cid:12)(cid:2)(cid:31)#(cid:14)(cid:12)(cid:7)(cid:9)(cid:8)(cid:13)(cid:5)(cid:3)(cid:3)(cid:23)(cid:7)(cid:8)(cid:6)(cid:26)(cid:21)(cid:18) (cid:3)(cid:4)(cid:21)(cid:3) (cid:2)(cid:2)’(cid:4)(cid:2)’(cid:14)(cid:30)(cid:29)(cid:2)(cid:15)(cid:20)(cid:18)(cid:29)$(cid:2)(cid:18)( (cid:26)(cid:18)(cid:3)(cid:21)(cid:19)(cid:2)"(cid:29)!(cid:7) (cid:2) (cid:2) (cid:3)(cid:4)(cid:11)(cid:3) (cid:2)(cid:7)(cid:4)(cid:3)(cid:10)(cid:2) (cid:17)(cid:29) (cid:20)(cid:14)(cid:30)(cid:2)+(cid:19),(cid:2) (cid:31)(cid:12)(cid:20)(cid:30)(cid:29)(cid:2)(cid:9)$(cid:7) Figure 26. 8-Lead, Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,  specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73833 • Rev. 1.0.2 12

F A N 7 3 8 3 3 — H a l f - B r i d g e G a t e - D r i v e I C © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN73833 • Rev. 1.0.2 13

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