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F A N 7 3 September 2015 8 0 — H a l FAN7380 f- B r Half-Bridge Gate Driver id g e G Features Description a t  Floating Channel Designed for Bootstrapping The FAN7380 is a monolithic half-bridge gate-drive IC for e Operation to +600V MOSFETs and IGBTs that operate up to +600V. D r  Typically 90mA/180mA Sourcing/Sinking Current Fairchild’s high-voltage process and common-mode iv Driving Capability for Both Channels noise cancelling technique provide stable operation of e r high-side driver under high-dv/dt noise circumstances.  Common-Mode dv/dt Noise Cancelling Circuit An advanced level-shift circuit allows high-side gate  Extended Allowable Negative VS Swing to -9.8V for driver operation up to V =-9.8V (typical) for V =15V. Signal Propagation at V =V =15V S BS CC BS The input logic level is compatible with standard TTL-  VCC & VBS Supply Range from 10V to 20V series logic gates. The internal shoot-through protection  UVLO Functions for Both Channels circuit provides 100ns dead-time to prevent output  TTL-Compatible Input Logic Threshold Levels switching devices from both conducting during transition  Matched Propagation Delay Below 50 ns periods. UVLO circuits for both channels prevent malfunction when V and V are lower than the  Built-in 100 ns Dead-Time Control Function CC BS specified threshold voltage. Output drivers typically  Output In-Phase with Input Signal source / sink at 90mA/180mA, respectively, which is suitable for fluorescent / compact fluorescent lamp Typical Applications ballast applications and systems requiring low di/dt noise.  Fluorescent Lamp Ballast  Compact Fluorescent Lamp Ballast 8-SOP Related Resources  AN-6076 - Design and Application Guide of Bootstrap Circuit for High-Voltage Gate-Drive IC  AN-9052 - Design Guide for Selection of Bootstrap Components  AN-8102 - Recommendations to Avoid Short Pulse Width Issues in HVIC Gate Driver Applications Ordering Information Device Package Pb-Free Operating Temperature Packing Description FAN7380MX(1) 8-SOP Yes -40°C ~ +125°C Tape & Reel Lighting Application Note: 1. This device has passed wave soldering test by JESD22A-111. © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7380 • Rev. 2.7

F A Typical Application Circuit N 7 3 15V 600V 8 0 — RBOOT DBOOT H a l f - B LIN 1 LIN VB 8 ri Q1 d R1 g HIN 2 HIN HO 7 e G CBOOT R2 a 3 VCC VS 6 te C1 Q2 D R3 4 COM LO 5 Load riv e R4 r FAN7380 Rev.03 Figure 1. Application Circuit for Fluorescent Lamp Ballast Internal Block Diagram 8 V B UVLO D R GE IV 7 HO NEPU NOISE R R ER RALS CANCELLER S Q TE O R 6 V S SCHMITT TRIGGER HS(ON/OFF) HIN 2 INPUT UVLO 3 VCC SHOOT THROUGH LIN 1 PREVENTION D R LS(ON/OFF) DELAY IV 5 LO {DEAD-TIME=100ns} E R 4 COM FAN7380 Rev.02 Figure 2. Functional Block Diagram © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7380 • Rev. 2.7 2

F A Pin Configuration N 7 3 8 0 — LIN 1 8 V H B a l f - HIN 2 7 HO B r FAN7380 i d V g CC 3 6 V S e G a COM 4 5 LO t e D r i v FAN7380 Rev.02 e r Figure 3. Pin Configuration (Top View) Pin Definitions Pin # Name I/O Description 1 LIN I Logic Input for Low-Side Gate Driver Output 2 HIN I Logic Input for High-Side Gate Driver Output 3 V I Low-Side Supply Voltage CC 4 COM Logic Ground and Low-Side Driver Return 5 LO O Low-Side Driver Output 6 V I High-Voltage Floating Supply Return S 7 HO O High-Side Driver Output 8 V I High-Side Floating Supply B © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7380 • Rev. 2.7 3

F A Absolute Maximum Ratings N 7 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be 3 8 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In 0 addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. — The absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified. H a Symbol Parameter Min. Max. Unit l f - V High-side offset voltage V -25 V +0.3 B S B B r i V High-side floating supply voltage -0.3 625.0 d B g V High-side floating output voltage HO V -0.3 V +0.3 e HO S B G VCC Low-side and logic-fixed supply voltage -0.3 25.0 V a t V Low-side output voltage LO -0.3 V +0.3 e LO CC D VIN Logic input voltage (HIN, LIN) -0.3 VCC+0.3 r i v COM Logic ground VCC-25 VCC+0.3 e r dV /dt Allowable offset voltage slew rate 50 V/ns S P (2)(3)(4) Power dissipation 0.625 W D  Thermal resistance, junction-to-ambient 200 °C/W JA T Junction temperature 150 °C J T Storage temperature -50 150 °C S Notes: 2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). 3. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages 4. Do not exceed P under any circumstances. D Recommended Operating Ratings The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit V High-side floating supply voltage V +10 V +20 B S S V High-side floating supply offset voltage 6-V 600 S CC V High-side (HO) output voltage V V HO S B V V Low-side (LO) output voltage COM V LO CC V Logic input voltage (HIN, LIN) COM V IN CC V Low-side supply voltage 10 20 CC T Ambient temperature -40 125 °C A © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7380 • Rev. 2.7 4

F A Static Electrical Characteristics N 7 V (V , V ) = 15.0V, T = 25C, unless otherwise specified. The V and I parameters are referenced to COM. 3 BIAS CC BS A IN IN 8 The VO and IO parameters are referenced to VS and COM and are applicable to the respective outputs HO and LO. 0 — Symbol Parameter Conditions Min. Typ. Max. Unit H VCCUV+ VCC & VBS supply under-voltage 8.2 9.2 10.0 al V + positive going threshold f BSUV - B VCCUV- VCC & VBS supply under-voltage 7.6 8.7 9.6 V ri V - negative going threshold d BSUV g V V supply under-voltage lockout e VCCUVH hyCsCteresis 0.5 G BSUVH a ILK Offset supply leakage current VB=VS=600V 50 te I Quiescent V supply current V =0V or 5V 44 100 µA D QBS BS IN r i I Quiescent V supply current V =0V or 5V 70 180 v QCC CC IN e I Operating V supply current f =20kHz, rms value 600 r PBS BS IN µA I Operating V supply current f =20kHz, rms value 610 PCC CC IN V Logic "1" input voltage 2.5 IH V V Logic "0" input voltage 0.8 IL V High-level output voltage, V -V 2.8 OH BIAS O I =20mA V O V Low-level output voltage, V 1.2 OL O I Logic "1" input bias current V =5V 5 40 IN+ IN µA I Logic "0" input bias current V =0V 1.0 2.0 IN- IN I Output HIGH short-circuit pulse current V =0V,V =5V with PW10µs 60 90 O+ O IN V =15V,V =0V with mA I Output LOW short-circuit pulsed current O IN 130 180 O- PW10µs Allowable negative V pin voltage for V S -9.8 -7.0 V S HIN signal propagation to HO Dynamic Electrical Characteristics V (V , V ) = 15.0 V, V = COM, C = 1000 pF and T = 25C, unless otherwise specified. BIAS CC BS S L A Symbol Parameter Conditions Min. Typ. Max. Unit t Turn-on propagation delay V =0V 70 135 200 on S t Turn-off propagation delay V =0V or 600V(5) 60 130 190 off S t Turn-on rise time 160 230 290 r ns t Turn-off fall time 20 90 160 f DT Dead time 80 120 190 MT Delay matching, HS & LS turn-on/off 50 Note: 5. This parameter guaranteed by design. © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7380 • Rev. 2.7 5

F A Typical Performance Characteristics N 7 3 8 220000 220000 0 Turn-on Propagation Delay [ns]Turn-On Propagation Delay [nsec]Turn-On Propagation Delay [nsec] 11111111111111111111898901234567890123456789000000000000000000000000 LLooww--SSiiddeeHHiiggVCCThhVCCTVCCTACOL--aaCC==OLOLCSSM=====21CCMMii22dd11V5n===55==nnee°VVBF0°°00CFFSCCBBVVVSS Turn-on Propagation Delay [ns]Turn-On Propagation Delay [nsec]Turn-On Propagation Delay [nsec] 11111111111111111111898901234567890123456789000000000000000000000000--4400VCCVCCVCCCCLLOOCOL===CCC--MM22M=111==00==nnVnVV=00FFBF0BBVVSVSS=00==111555VVV2200HHiigghh44--00SSLLiiddooeeww6600--SSiiddee8800 110000 112200 — Half-Bridge Gate Driv 1100 1122 1144 1166 1188 2200 e SSSuuupppppplllyyy VVVooollttltaaagggeee [[ VV[V]]] TeTTmeepmmeppraeetrruaarttuuerr [ee° C[[°°]CC]] r Figure 4. Turn-On Propagation Delay vs. Supply Figure 5. Turn-On Propagation Delay vs. Temp. Voltage Propagation Delay [ns]Propagation Delay [nsec]Propagation Delay [nsec] 111121111224680246800000000000 HHiiggLLhhoo--SSwwii--ddSSeeiiddeeVCCTVCCTVCCTACOLaa=CC=OOLLCM===2==1CCMM2211V5n===55==nn°BFVV0°°00CFFSCCBBVVVSS ropagation Delay [ns]Propagation Delay [nsec]Propagation Delay [nsec] 111111112111111112234567890234567890000000000000000000 VCCVCCVCCCCOOLLCOL=C==CCMMM=111====nnVn=VV00FFBF0BBVVSVSS=LL==1oo115ww55VVV--SSiiddee HHiigghh--SSiiddee urn-off urn-Off urn-Off 110000 rn-off Purn-Off urn-Off 1111990101000000 TTT uTT 8800 T 8800 1100 1122 1144 1166 1188 2200 --4400 --2200 00 2200 4400 6600 8800 110000 112200 SSSuuupppppplyllyy V VVoooltllattaagggeee [ V[[VV]]] TTTeeemmmpppeeerrraaattuuturrreee [[ °°[CC°C]]] Figure 6. Turn-Off Propagation Delay vs. Supply Figure 7. Turn-Off Propagation Delay vs. Temp. Voltage 335500 330000 Rising Time [nsec]Rising Time [nsec]Rising Time [ns] 223223050050000000 LLooHHwwii--ggSShhii--ddSSeeiiddee VCCTVCCTVCCTACOL==aaCCCOLOLM===21==CCMM22V511n===55==nn°BF0VV°°00CFFSCCVBBVVSS Rising Time [ns]Rising Time [nsec]Rising Time [nsec] 122222122222802468802468000000000000 VCCVCCVCCCOLCCOLOL=C==CCMMM=111==Vn===nnVV00BF0FFBBVVSVLL=SSoo1==ww51155V--SSVViiddee HHiigghh--SSiiddee Turn-On Turn-On Turn-on 115500 Turn-on Turn-On Turn-On 111111246246000000 110000 110000 1100 1122 1144 1166 1188 2200 --4400 --2200 00 2200 4400 6600 8800 110000 112200 SSSuuupppppplyllyy V VVoooltllattaagggeee [ [[VVV]]] TTTeeemmmpppeeerrraaatttuuurrreee [[[°°°CCC]]] Figure 8. Turn-On Rising Time vs. Supply Voltage Figure 9. Turn-On Rising Time vs. Temp. © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7380 • Rev. 2.7 6

F A Typical Performance Characteristics (Continued) N 7 3 112200 115500 8 VVVCCCC===VVVBBSS 114400 VVVCCCC===VVVBB=SS1==511V55VV 0 Falling Time [ns]Falling Time [nsec]Falling Time [nsec] 11118989010100000000 LLooHHwwiigg--SShhii__ddsseeiiddee CCTCCTCCTACOLaaOOLL==C====MMM2122115n=55==nn°°°BF000FFCCCSVVV Falling Time [ns]Falling Time [nsec]Falling Time [nsec]1111111167896789012301230000000000000000 CCCCCCCOLLLOO=C==MMM111n===nn00BF0FFSVVV HHiigghhLL--SSoowwiidd--eeSSiiddee — Half-Bridg n-off n-Off n-Off 7700 n-off n-Off n-Off 45450000 e G TurTurTur 6600 TurTurTur 23230000 ate 1100 D 5500 00 r 1100 1122 1144 1166 1188 2200 --4400 --2200 00 2200 4400 6600 8800 110000 112200 iv SSSuuupppppplyllyy V VVoooltllttaaagggeee [[[VVV]]] TTTeeemmmpppeeerrraaatttuuurrreee [[ °°[°CCC]]] e r Figure 10. Turn-Off Falling Time vs. Supply Voltage Figure 11. Turn-Off Falling Time vs. Temp. 220000 220000 118800 HHHIIINNN 111189890000 HHHIIINNN VVVCCCCCC===VVVBBBS=SS1==511V55VV LLLIIINNN 117700 LLLIIINNN CCCOOOMMM===000VVV Dead-Time [ns]Dead-Time [nsec]Dead-Time [nsec] 1111111188024602460000000000 DDTTDD11TT22 HHHLLLOOOOOO DDD999TTT000111%%% 111000%%% VCVCVCCO999CCOOC000%%%M=CCMMV===111==DDD000TTTVV%%%B022200SBBVVVSS Dead-Time [ns]Dead-Time [nsec]Dead-Time [nsec] 11111111111111567895678901234560123456000000000000000000000000 HHHLLLOOOOOO DDD999TTT000111%%% 111000%%% 999000%%% 111DDD000TTT%%%222 CCCLLL===111nDDDDnnFFFTTTT1212 6600 CCCLL===111nnnFFF 4400 TTLaa==2255°°CC 3300 T =25°C 2200 4400 A 1100 00 1100 1122 1144 1166 1188 2200 --4400 --2200 00 2200 4400 6600 8800 110000 112200 SuSSpuuppplppyll yyV VVoooltllattaagggeee [ V[[VV]]] TTTeeemmmpppeeerrraaatttuuurrreee [[ [°°°CCC]]] Figure 12. Dead-Time vs. Supply Voltage Figure 13. Dead-Time vs. Temp. 220000 113300 rcing Current [mA]urcing Current [mA]urcing Current [mA] 11111189890120120000000000 VCLTVCLTVCLTOOaaCCOOAOCO===CCC==HHMM=22M=2HH==ii55H==ggV5OOVV=°°00O°hhCCBBB0VV==CS--V=00SSSSVV0iiddVee LLooww--SSiiddee cing Current [mA]urcing Current [mA]urcing Current [mA] 1111111111880246802468000000000000 VCLVCLVCLOOOCCOOCOCCC==MM=M=HH==H==V=OOVV00OB0BB==VVSV=00SS=0VV==1V11555VVV LLooww--SSiiddee Output SouOutput SoOutput So 567567000000 utput SourOutput SoOutput So 246246000000 HHiigghh--SSiiddee O 4400 00 1100 1122 1144 1166 1188 2200 --4400 --2200 00 2200 4400 6600 8800 110000 112200 SSSuuupppppplyllyy V VVoooltllattaagggeee [[[VVV]]] TTTeeemmmpppeeerrraaatttuuurrreee [[ °°[CC°C]]] Figure 14. Output Sourcing Current vs. Supply Figure 15. Output Sourcing Current vs. Temp. Voltage © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7380 • Rev. 2.7 7

F A Typical Performance Characteristics (Continued) N 7 3 224400 330000 8 king Current [mA]nking Current [mA]nking Current [mA] 111221112246802468020000000000 VCLTVCLTVCLTOOaaCCOOAOCO==CC===CMM22=MVV=HH2==55==VCCVVV5ii°°=00ggCCCBBCC°BVV0ChhCSSS,,V, -- HHSSHOOiiOdd==ee=VVVBBB LLooww--SSiiddee king Current [mA]nking Current [mA]nking Current [mA] 112222211222226802468680246800000000000000 VCLVCLVCLOCOOOCCOOC=MCC===MMVVVV=====CCCLLVVB000CooBBCCSVVV,=ww SS,,H 1HH==--O5SS11OOV55ii===ddVVVVVeeBBB 0 — Half-Bridg Output SinOutput SiOutput Si 111102020000 Output SinOutput SiOutput Si 1111118802402400000000 HHiigghh--SSiiddee e Gate D 8800 6600 r 1100 1122 1144 1166 1188 2200 --4400 --2200 00 2200 4400 6600 8800 110000 112200 iv SSSuuuppppppllyyly VV Vooollttlaatagggeee [[ VV[V]]] TTTeeemmmpppeeerrraaattuuturrreee [[ °°[CC°C]]] e r Figure 16. Output Sinking Current vs. Supply Voltage Figure 17. Output Sinking Current vs. Temp. Allowable Negative V VoltageSAllowable Negative VS VoltageAllowable Negative VS Voltagefor Signal Propagation to High-Side [V]for Signal Propagatioto High-Side [V]for Signal Propagatioto High-Side [V]----------1111111111------86486486420864201100 1122 SSSupuupppppl11yll44yy V VVoooltllttaaaggge11ee66 [[[VVV]]]VCTVCTVCTaaCCOOACO===CCCMM22M11=2==8855==V5VV=°°00CC°BBB0VVCSSSV 2200 Allowable Negative V VoltageSAllowable Negative VS VoltageAllowable Negative VS Voltagefor Signal Propagation to High-Side [V]for Signal Propagation to High-Side [V]for Signal Propagation to High-Side [V]------111111--------99889988100100..............50505050050050--4400VCVCVCCCOOCOCCMMC--22M=====00VVV00=BBVVB0SSSV===00T111e555mTTVVVeep22mm00eppraeetrruaa4400ttruuerr [ee° 66C[[°°00]CC]] 8800 110000 112200 Figure 18. Allowable Negative V Voltage for Signal Figure 19. Allowable Negative V Voltage for Signal S S Propagation to High-Side vs. Supply Voltage Propagation to High-Side vs. Temperature 110000 110055 VVVBBCCSS===V1155BVVS 110000 VVVCCCCCC===VVVBBBSSS===111555VVV CCCOOOMMM===000VVV 9955 CCCOOOMMM===000VVV 8800 HHIINN==LLIINN==00VV HHIINN==LLIINN==00VV TTHAAIN==22=55L°°ICCN=0V 9900 HIN=LIN=0V T =25°C 8855 uA]uA]A] 6600 A A]uA]uA] 8800 QCC [QCC [ [QCC 4400 [QCC [QCC [CC 77770505 III IIIQ 6655 6600 2200 5555 5500 00 4455 00 55 1100 1155 2200 --4400 --2200 00 2200 4400 6600 8800 110000 112200 SuSSpuuppplppyll yyV VVoooltllattaagggeee [ V[[VV]]] TeTTmeemmpppereearrtaauttuurerr ee[ °[[C°°CC]]] Figure 20. I vs. Supply Voltage Figure 21. I vs. Temperature QCC QCC © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7380 • Rev. 2.7 8

F A Typical Performance Characteristics (Continued) N 7 3 8800 5566 8 7700 VCVCVCCOCCOOCCCMMM===1===11500055VVVVVV 5544 VCVCCCOOCCMM====110055VVVV 0 — HHHIIINNN===LLLIIINNN===000VVV 5522 HHIINN==LLIINN==00VV 6600 TTTAaa===222555°°°CCC 5500 Ha A]A]A] 5500 A]A]4488 lf- I [IQBS [uIQBS [uQBS 34340000 I [A]IQBS [uIQBS [uQBS444444246246 Bridge 2200 4400 G 3388 a 1100 te 3366 D 00 3344 r 00 55 1100 1155 2200 --4400 --2200 00 2200 4400 6600 8800 110000 112200 iv SSSuuupppppplllyyy VVVooollltttaaagggeee [[[VVV]]] TTTeeemmmpppeeerarraatuttuurerree [ °[[C°°CC]]] e r Figure 22. I vs. Supply Voltage Figure 23. I vs. Temperature QBS QBS V =V =15V 22..33 VVVCC=CCV==VVBBSS 22..22 VVCCCCCC==VVBBBSSS==1155VV CC BS COM=0V 22..22 COCHCHOIOIMNNMM===LL==0II00VNNVV==55VV CHCHHIIOOINNNMM===LL==LII00NNIVVN==55=VV5V 22..11 HIIILLN===22L00ImmNAA=5V 22..00 IIILLL===222000mmmAAA 22..00 IL=TT2aa==022m55°°ACC HHiigghh--SSiiddee V [V]VOH [V]VOH [V]OH 1111....8989 LLooww--SSiiddee TA=25°C V [V]VOH [V]VOH [V]OH 1111....6868 LLooww--SSiiddee HHiigghh--SSiiddee 11..77 11..44 11..66 11..55 11..22 11..44 1100 1122 1144 1166 1188 2200 --4400 --2200 00 2200 4400 6600 8800 110000 112200 SSSuuupppppplllyyy VV Vooollttlaatagggeee [[ VV[V]]] TTTeeemmmpppeeerrraaatttuuurrreee [[[°°°CCC]]] Figure 24. High-Level Output Voltage vs. Supply Figure 25. High-Level Output Voltage vs. Temp. Voltage 00..7755 V VV=CCVCC==VVBBSS 00..8800 VVVCCCCCC===VVVBBBSSS===111555VVV CCCCOOMMB==S00VV 00..7755 CCCOOOMMM===000VVV 00..7700 COHHMIINN===0LLVIINN==00VV HHHIIINNN===LLLIINNIN===00VV0V HINIILL===22L00INmm=AA0V 00..7700 IIILL===222000mmmAAA L I =TT2aa0==m2255A°°CC 00..6655 00..6655 L V [V]VOL [V]VOL [V]OL 00..6600 TA=25°C V [V]OLVOL [V]VOL [V]0000....56565050 LLooww--SSiiddee HHiigghh--SSiiddee 00..5500 00..5555 HHiigghh--SSiiddee 00..4455 00..4400 00..5500 LLooww--SSiiddee 00..3355 1100 1122 1144 1166 1188 2200 --4400 --2200 00 2200 4400 6600 8800 110000 112200 SSSuuupppppplllyyy VV Vooollttlaatagggeee [[ VV[V]]] TTTeeemmmpppeeerarraatuttuurerree [ °[[°°CCC]]] Figure 26. Low-Level Output Voltage vs. Supply Figure 27. Low-Level Output Voltage vs. Temp. Voltage © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7380 • Rev. 2.7 9

F A Typical Performance Characteristics (Continued) N 7 77..00 3 8 55 IINN++ 66..55 HHIINN==LLIINN==55VV 0 — 66..00 44 H 55..55 N+/IN- [A]N+/IN-[uA]N+/IN-[uA] 2323 VCITNVCITVCITANNCOaaCC=OO=C====MV=CC2MMVV22V5C===CC55==C°VVB0°°00CCC CCSBBVoVV ooSSr rrI NIINN===000VVV IN+ [A]IN+ [uA]IN+ [uA] 445445......050050 LLIINN HHIINN alf-Bridg III 33..55 e 11 G 33..00 a IINN-- t 22..55 e 00 D 22..00 r 00 55 1100 1155 2200 --4400 --2200 00 2200 4400 6600 8800 110000 112200 iv SSSuuupppppplllyyy VVVooollltttaaagggeee [[[VVV]]] TTTeeemmmpppeeerrraaatttuuurrreee [[[°°°CCC]]] e r Figure 28. Input Bias Current vs. Supply Voltage Figure 29. Input Bias Current vs. Temperature 1111 1111..00 1100..55 V]V] 1100 V]V] 1100..00 V/V [V]VCCUV+/VCCUV-[VCCUV+/VCCUV-[CCUV+CCUV- 8989 VVVCCCCCCVVUUUCCVVVV-CCC--CUUUVVV+++ V/V [V]VBSUV+/VBSUV-[VBSUV+/VBSUV-[SBUV+SBUV- 88998899........05050505 VVVVVBBBVBBSSSBUSSUUSV__U+VVVUU++-VV-- 77..55 77 77..00 --4400 --2200 00 2200 4400 6600 8800 110000 112200 --4400 --2200 00 2200 4400 6600 8800 110000 112200 TTTeeemmmpppeeerrraaatttuuurrreee [[[°°°CCC]]] TTTeeemmmpppeeerrraaatttuuurrreee [[[°°°CCC]]] Figure 30. V UVLO Threshold Voltage vs. Temp. Figure 31. V UVLO Threshold Voltage vs. Temp. CC BS 22..00 22..66 VVVBB---tttooo---CCCOOOMMM===66655005VV0V 22..55 VVVCCCCCC===VVVBBBSSS===111555VVV B V]V] 22..44 CCCOOOMMM===000VVV 11..55 old [old [ 22..33 VVVIIIHHH (((HHHIIINNN))) hh ss 22..22 A]uA]uA] hrehre 22..11 VVVIIHHIH(( (LLLIIINNN))) I [ILK [ILK [LK 11..00 ogic Togic T 1212....9090 VVVIILLIL(( (LLLIIINNN))) LL 00..55 put put 11..88 VVV(IILLH((IHHNII)NN)) nn 11..77 IL II 11..66 00..00 11..55 --4400 --2200 00 2200 4400 6600 8800 110000 112200 --4400 --2200 00 2200 4400 6600 8800 110000 112200 TTTeeemmmpppeeerrraaatttuuurrreee [[[°°°CCC]]] TTTeeemmmpppeeerrraaatttuuurrreee [[[°°°CCC]]] Figure 32. VB to COM Leakage Current vs. Temp. Figure 33. Input Logic Threshold vs. Temp. © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7380 • Rev. 2.7 10

F A Switching Time Definitions N 7 3 8 0 — 5V HIN H HIN a 50% 50% l LIN LIN 50% 50% f-B r i d tr tf g ton toff LO 10% 90% e G a HO t HO 90% 90% DT DT e 90% D LO 10 r 10% 10% % iv FAN7380 Rev.01 FAN7380 Rev.01 e r Figure 34. Switching Time Waveforms Figure 35. Internal Dead-Time Timing © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7380 • Rev. 2.7 11

5.12 C A 4.72 0.35 8 5 B 1.75 0.65 6.30 4.15 5.70 3.75 5.60 1.27 1 4 1.27 PIN #1 ID 0.25 M C B A LAND PATTERN RECOMMENDATION TOP VIEW 1.85 1.75 B 0.25 1.35 C 1.25 C 0.15 C 0.51 0.25 (8X) 0.31 OPTION A OPTION B 0.10 BEVEL EDGE NON-BEVEL EDGE 0.10 C SIDE VIEW FRONT VIEW NOTES: UNLESS OTHERWISED SPECIFIED GAGE PLANE BEVEL R0.10 A. THIS PACKAGE CONFORMS TO JEDEC MS-012 VARIATION A EXCEPT WHERE NOTED. 0.25 B. ALL DIMENSIONS ARE IN MILLIMETERS C OUT OF JEDEC STANDARD VALUE 8° 4° D. DIMENSIONS ARE EXCLUSIVE OF BURRS, 0.80 MOLD FLASH AND TIE BAR EXTRUSIONS. SEATING 0.30 E. LAND PATTERN AS PER IPC PLANE 1.04 SOIC127P600X175-8M F. DRAWING FILENAME: MKT-M08Brev2 DETAIL "B" SCALE 2:1

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