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F A N 6 7 November 2013 5 7 — m W FAN6757— mWSaver® PWM Controller S a v e r ® P Features Description W M  Single-Ended Topologies, such as Flyback and The FAN6757 is a next-generation Green Mode PWM C Forward Converters controller with innovative mWSaver® technology, which o dramatically reduces standby and no-load power n  mWSaver® Technology consumption, enabling conformance to worldwide tr o - Achieves Low No-Load Power Consumption: Standby Mode efficiency guidelines. ll e <50 mW at 230 VAC (EMI Filter Loss Included) An innovative AX-CAP® method minimizes losses in the r - Eliminates X Capacitor Discharge Resistor Loss EMI filter stage by eliminating X-cap discharge resistors with AX-CAP® Technology while meeting IEC61010-1 safety requirements. - Linearly Decreases Switching Frequency Protections ensure safe operation of the power system to 23 kHz in various abnormal conditions. A proprietary frequency- - Burst Mode Operation at Light-Load Condition hopping function decreases EMI emission. Built-in synchronized slope compensation allows more stable - 500 V High-Voltage JFET Startup Circuit to Peak-Current-Mode control over a wide range of input Eliminate Startup Resistor Loss voltage and load conditions. The proprietary internal line  Highly Integrated with Rich Features compensation ensures constant output power limit over the entire universal line voltage range. - Proprietary Frequency Hopping to Reduce EMI Requiring a minimum number of external components, - High-Voltage Sampling to Detect Input Voltage FAN6757 provides a basic platform that is well suited for - Peak-Current-Mode Control with Slope cost-effective flyback converter designs that require Compensation extremely low standby power consumption. - Cycle-by-Cycle Current Limiting with Line Compensation Applications - Leading-Edge Blanking (LEB) Flyback power supplies that demand extremely low - Built-In 7 ms Soft-Start standby power consumption, such as:  Advanced Protections  Adapters for Notebooks, Printers, Game Consoles - Brown-In/Brownout Recovery  Open-Frame SMPS for LCD TV, LCD Monitors, - Internal Overload / Open-Loop Protection (OLP) Printers - V Under-Voltage Lockout (UVLO) DD - V Over-Voltage Protection (V OVP) DD DD - Over-Temperature Protection (OTP) - Current-Sense Short-Circuit Protection (SSCP) Ordering Information Protections(1) Operating Packing Part Number Package Temperature Range Method OLP OVP OTP SSCP 8-Pin, Small-Outline Tape & FAN6757MRMX A/R L L A/R -40 to +105°C Package (SOP) Reel Note: 1. A/R = Auto Recovery Mode protection, L = Latch Mode protection. © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1

F A N Application Diagram 6 7 5 7 — VAC + m VO W S a - v e r® P W M FAN6757 C o 1 GND GATE 8 n 2 FB VDD 7 tr o 3 NC SENSE 6 l l 4 HV RT 5 e r Figure 1. Typical Application Internal Block Diagram HV NC 4 3 VDDOVP Line OTP ProLtaetccthion Re-Start SSCP Sensing Protection OLP Brownout Function Soft High/Low Line Driver Compensation VLimit VPWM 8 GATE S Q Internal OSC SSCP VDD 7 BIAS R Comparator UVLO VRESET SSCP tD-SSCP VSSCP-H/L … Soft-Start VDD-ON / Pattern Comparator VRESTART Generator Soft-Start Current Limit VRESET Comparator Blanking 6 SENSE Circuit tD-VDDOVP VODVDP GMroedeen PWM VLimit Comparator VDD-OVP MDuatxy. VPWM C o m Spleonpseation VFB-OPEN IRT ZFB RT 5 tD-OTP1 OTP OLP tD-OLP 3R 2 FB VRTTH1 OLP R tD-OTP2 Comparator VRTTH2 VFB-OLP 1 GND Figure 2. Functional Block Diagram © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1 2

F A N Marking Information 6 7 5 7 — Z - Plant Code X - 1-Digit Year Code m ZXYTT Y - 1-Digit Week Code W 6757 TT - 2-Digit Die Run Code S a TM T - Package Type (M=SOP) v e M - Manufacture Flow Code r ® P Figure 3. Top Mark W M Pin Configuration C o n SOP-8 tr o l l GND 1 8 GATE e r FB 2 7 VDD NC 3 6 SENSE HV 4 5 RT Figure 4. Pin Configuration (Top View) Pin Definitions Pin # Name Description Ground. This pin is used for the ground potential of all the pins. A 0.1 µF decoupling capacitor 1 GND placed between VDD and GND is recommended. Feedback. The output voltage feedback information from the external compensation circuit is fed into this pin. The PWM duty cycle is determined from this pin and the current-sense signal from 2 FB Pin 6. The FAN6757 performs open-loop protection: if the FB voltage is higher than a threshold voltage (around 4.6 V) for more than 57.5 ms, the controller latches off the PWM. 3 NC No connection High-Voltage Startup. This pin is connected to the line input or bulk capacitor, via 200 kΩ resistors, to achieve brownout and high/low line compensation. If the voltage of the HV pin is 4 HV lower than the brownout voltage (AC line peak voltage less than 100 V) and lasts for 65 ms, PWM output turns off. High/low line compensation dominates the OCP level and cycle-by-cycle current limit, to solve the unequal OCP level and power-limit problems under universal input. Over-Temperature Protection. An external NTC thermistor is connected from this pin to the GND pin. The impedance of the NTC thermistor decreases at high temperatures. Once the voltage of the RT pin drops below the threshold voltage, the controller latches off the PWM. If the 5 RT RT pin is not connected to an NTC resistor for over-temperature protection, it is recommended to place one 100 kΩ resistor to ground to prevent from noise interference. This pin is limited by an internal clamping circuit. Current Sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle 6 SENSE current limiting. Power Supply. The internal protection circuit disables PWM output as long as V exceeds the 7 VDD DD OVP trigger point. Gate Drive Output. The totem-pole output driver for the power MOSFET. It is internally clamped 8 GATE below 14.5 V. © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1 3

F A N Absolute Maximum Ratings 6 7 5 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be 7 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. — In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. m The absolute maximum ratings are stress ratings only. W S Symbol Parameter Min. Max. Units a v VVDD DC Supply Voltage(1,2) 30 V e r V FB Pin Input Voltage -0.3 7.0 V ® FB P VSENSE SENSE Pin Input Voltage -0.3 7.0 V W V RT Pin Input Voltage -0.3 7.0 V M RT V HV Pin Input Voltage 500 V C HV o PD Power Dissipation (TA＜50°C) 400 mW nt r ϴJA Thermal Resistance (Junction-to-Air) 150 C/W ol l e TJ Operating Junction Temperature -40 +125 C r TSTG Storage Temperature Range -55 +150 C TL Lead Temperature (Wave Soldering or IR, 10 Seconds) +260 C Human Body Model, JEDEC:JESD22-A114 All Pins except HV Pin(3) 6.5 ESD kV Charged Device Model, JEDEC:JESD22-C101 All Pins except HV Pin(3) 2.0 Notes: 1. All voltage values, except differential voltages, are given with respect to the network ground terminal. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 3. ESD level on the HV pin is CDM=1 kV and HBM=1 kV. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. We does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit R Resistance on HV Pin 150 200 250 kΩ HV © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1 4

F A N Electrical Characteristics 6 7 5 VDD=15 V and TJ=TA=25C unless otherwise noted. 7 — Symbol Parameter Conditions Min. Typ. Max. Unit m V Section W DD S VDD-ON Threshold Voltage to Startup VDD Rising 16 17 18 V a v Threshold Voltage to Stop Switching in e VUVLO Normal Mode VDD Falling 5.5 6.5 7.5 V r® Threshold Voltage to enable HV Startup P VRESTART to Charge V in Normal Mode VDD Falling 4.7 V W DD M VDD-OFF TPhroreteschtoioldn VMooldtaeg e to Stop Operating in VDD Falling 10 11 12 V C o n Threshold Voltage to Enable HV Startup V V Falling 6 7 8 V t DD-OLP to Charge VDD in Protection Mode DD ro l Threshold Voltage to Release Latch le V V Falling 3.5 4.0 4.5 V DD-LH Mode DD r Minimum Voltage of VDD Pin for V V V V UVLO UVLO UVLO V DD-AC Enabling Brown-in to Avoid Startup Fail +2.5 +3.0 +3.5 I Startup Current V =V – 0.16 V 30 µA DD-ST DD DD-ON V =15 V, V =3 V, I Supply Current in PWM Operation DD FB 1.8 mA DD-OP1 Gate Open V =15 V, V <1.4 V, I Supply Current when PWM Stops DD FB 800 µA DD-OP2 Gate Off Internal Sink Current when V IDD-OLP <V <V in ProtectionD DM-ode VDD = VDD-OLP + 0.1 V 90 140 190 µA OLP DD DD-OFF Internal Sink Current when V <V I DD DD-OLP V = 5 V 30 µA LH in Latch-Protection Mode DD Threshold Voltage for V Over-Voltage V DD 23.5 24.5 25.5 V DD-OVP Protection V Over-Voltage Protection Debounce t DD 110 205 300 µs D-VDDOVP Time HV Section V =90 V (V =120 V), I Inherent Current Limit of HV Pin AC DC 1.50 3.25 5.00 mA HV V =0 V DD DC Source Series, V Threshold Voltage for Brownout 90 100 110 V AC-OFF R=200 kΩ to HV Pin DC Source Series, V Threshold Voltage for Brown-In 100 110 120 V AC-ON R=200 kΩ to HV Pin DC Source Series, △VAC VAC-ON – VAC-OFF R=200 kΩ to HV Pin 8 12 16 V t Debounce Time for Brownout 40 65 90 ms D-AC-OFF Work Period of HV-Sampling Circuit in t V <V 95 140 185 ms S-WORK Standby Mode FB FB-ZDC Rest Period of HV-Sampling Circuit in t V <V 180 260 320 ms S-REST Standby Mode FB FB-ZDC V V V V HV Discharge Threshold R =200 kΩ to HV Pin DC DC DC V HV-DIS HV ×0.45 ×0.51 ×0.56 t Debounce Time for HV Discharge 75 115 155 ms D-HV-DIS t HV Discharge Time 360 510 660 ms HV-DIS Continued on the following page… © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1 5

F A Electrical Characteristics N 6 V =15 V and T=T =25C unless otherwise noted. 7 DD J A 5 7 Symbol Parameter Conditions Min. Typ. Max. Unit — Oscillator Section m W Center Frequency 62 65 68 S f Frequency in Normal Mode kHz OSC a Hopping Range (VFB>VFB-N) ±3.55 ±4.25 ±4.95 v e tHOP Hopping Period VFB>VFB-G 5.12 6.40 7.68 ms r® Center Frequency 20 23 26 P W f Green-Mode Frequency Hopping Range (Increase kHz OSC-G V from V Until Hopping ±1.25 ±1.50 ±1.75 M FB FB-G Starts) C o fDV Frequency Variation vs. VDD Deviation VDD=11 V to 22 V 5 % n t fDT FDreevqiauteionnc y Variation vs. Temperature TA=-40 to 105C 5 % rol l e Feedback Input Section r Input Voltage to Current-Sense A 1/4.50 1/3.75 1/3.00 V/V V Attenuation Z Pull High Impedance at Normal Mode 17 19 21 kΩ FB V Output High Voltage FB Pin Open 5.2 5.4 5.6 V FB-OPEN V FB Open-Loop Trigger Level 4.3 4.6 4.9 V FB-OLP t Delay of FB Pin Open-Loop Protection 45.0 57.5 70.0 ms D-OLP V Green-Mode Entry FB Voltage 2.6 2.8 3.0 V FB-N V Green-Mode Ending FB Voltage 2.1 2.3 2.5 V FB-G FB Threshold Voltage for Zero-Duty V 1.9 2.1 2.3 V FB-ZDCR Recovery at Normal Mode FB Threshold Voltage for Zero-Duty at V 1.8 2.0 2.2 V FB-ZDC Normal Mode Current-Sense Section t Delay to Output 100 250 ns PD t Leading-Edge Blanking Time 200 265 330 ns LEB Current Limit at Low Line V =122 V, V DC 0.43 0.46 0.49 V LIMIT-L (V =86 V) Series R=200 kΩ to HV AC-RMS Current Limit at High Line V =366 V, V DC 0.36 0.39 0.42 V LIMIT-H (V =259 V) Series R=200 kΩ to HV AC-RMS Threshold Voltage for SENSE Short- V =122 V, V DC 30 50 70 mV SSCP-L Circuit Protection Series R=200 kΩ to HV Threshold Voltage for SENSE Short- V =366 V, V DC 80 100 120 mV SSCP-H Circuit Protection Series R=200 kΩ to HV t On Time for V Checking V <V 4.00 4.55 5.10 µs ON-SSCP SSCP-(L/H) SENSE SSCP-(L/H) Debounce Time for SENSE Short- t V <V 110 170 230 µs D-SSCP Circuit Protection SENSE SSCP-(L/H) t Soft-Startup Time Startup Time 5 7 9 ms SS Continued on the following page… © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1 6

F A Electrical Characteristics N 6 V =15 V and T=T =25C unless otherwise noted. 7 DD J A 5 7 Symbol Parameter Conditions Min. Typ. Max. Unit — GATE Section m W DCY Maximum Duty Cycle 75.0 82.5 90.0 % MAX S a VGATE-L Gate Low Voltage VDD=15 V, IO=50 mA 1.5 V v e VGATE-H Gate High Voltage VDD=12 V, IO=50 mA 8 V r® t Gate Rising Time (10~90%) V =15 V, C =1 nF 85 110 135 ns r DD L P W t Gate Falling Time (10~90%) V =15 V, C =1 nF 30 40 50 ns f DD L M V Gate Output Clamping Voltage V =22 V 11.0 14.5 18.0 V GATE-CLAMP DD C RT Section o n IRT Output Current of RT Pin 100 µA tr o Threshold Voltage, Latch Protection l VRTTH1 (TGriegngeerrainllgy) Used for External OTP VARftTeTrH 12＜4.5 V mRTs ＜ LaVtRcThT HO1f,f 1.000 1.035 1.070 V ler Second Latch Protection Threshold V ＜ 0.7 V, V RTTH2 0.65 0.70 0.75 V RTTH2 Voltage After 185 µs Latch Off R Value of V /I 9.66 10.50 11.34 kΩ OTP RTTH1 RT Debounce Time, First Latch Protection t V ＜ V ＜ V 11.0 14.5 18.0 ms D-OTP1 Triggering RTTH2 RT RTTH1 Debounce Time, Second Latch t V < V 110 185 260 µs D-OTP2 Protection Triggering RT RTTH2 Over-Temperature Protection Section (OTP) T Protection Junction Temperature +135 °C OTP T - T Restart Junction Temperature OTP °C RESTART 25 © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1 7

F A N 6 7 Typical Characteristics 5 7 — m 6.0 11.4 W 11.2 S 5.5 a 11.0 v (V) 5.0 (V)1100..68 er® ART 4.5 FF10.4 P EST 4.0 D-O10.2 W VR VD10.0 M 3.5 C 9.8 o 3.0 9.6 n t -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 25 50 75 85 100 125 r o Temperature (ºC) Temperature (ºC) l le r Figure 5. V vs. Temperature Figure 6. V vs. Temperature RESTART DD-OFF 9.0 8 8.5 7 8.0 6 V) 7.5 V) 5 ( ( P7.0 H 4 L L D-O6.5 DD- 3 D V V 6.0 2 5.5 1 5.0 0 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 7. V vs. Temperature Figure 8. V vs. Temperature DD-OLP DD-LH 70 100 65 90 80 60 s) 55 A)70 m µ60 (P 50 (H50 OL 45 IL40 _ tD 40 30 20 35 10 30 0 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 9. T vs. Temperature Figure 10. I vs. Temperature D-OLP LH © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1 8

F A N Typical Characteristics 6 7 5 7 — 120 115 m 118 110 W 116 114 105 S V) V) a ( 112 ( 100 v ON110 FF er VAC-110068 VAC-O 9905 ® P W 104 102 85 M 100 80 C o -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 25 50 75 85 100 125 n Temperature (ºC) Temperature (ºC) t r o l l e Figure 11. VAC-ON vs. Temperature Figure 12. VAC-OFF vs. Temperature r 80 6.0 5.5 75 5.0 z) 70 V) 4.5 (kH 65 (V/ 4.0 SC AV 3.5 fO 60 1/ 3.0 55 2.5 50 2.0 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 13. fOSC vs. Temperature Figure 14. 1/AV vs. Temperature 21.0 6.0 20.5 5.9 20.0 5.8 19.5 5.7 Ω)19.0 V) 5.6 ( (k18.5 N 5.5 E FB18.0 OP 5.4 Z17.5 FB- 5.3 17.0 V 5.2 16.5 5.1 16.0 5.0 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 15. Z vs. Temperature Figure 16. V vs. Temperature FB FB-OPEN © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1 9

F A N Typical Characteristics 6 7 5 7 — 100 0.60 m 90 0.55 W 80 S %) V) 0.50 a (MAX 6700 (MIT-L0.45 ver® CY 50 VLI0.40 P D W 0.35 40 M 0.30 30 C -40 -30 -15 0 25 50 75 85 100 125 o -40 -30 -15 0 25 50 75 85 100 125 n Temperature (ºC) Temperature (ºC) t r o l l e Figure 17. DCYMAX vs. Temperature Figure 18. VLIMIT-L vs. Temperature r 0.60 380 0.55 360 0.50 340 V) 0.45 s) 320 (H0.40 (n 300 MIT-0.35 LEB 280 LI t 260 V 0.30 240 0.25 220 0.20 200 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 19. V vs. Temperature Figure 20. t vs. Temperature LIMIT-H LEB © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1 10

F A N Functional Description 6 7 5 Current Mode Control switching, reducing switching loss for lower power 7 consumption, as shown in Figure 23. — FAN6757 employs peak current-mode control, as shown in Figure 21. An opto-coupler (such as the H11A817A) V m O and a shunt regulator (such as the KA431) are typically W used to implement the feedback network. Comparing S the feedback voltage with the voltage across the R a sense v resistor makes it possible to control the switching duty VFB e cycle. The built-in slope compensation stabilizes the r® current loop and prevents sub-harmonic oscillation. VVFFBB..ZZDDCCR P W 5.4 V I M VO Drain ZFB C FB 2 o n PWM 3R Switching Switching tro GATE8 dGriavteer Comparator R KA431 Figure 23. BurDsista Sblweditching iDnis Gabrleeden Mode ller Operating Current SENSE 6 ++ Primary side Secsoidnedary In normal conditions, operating current is less than 1.8 mA (I ). When V <1.4 V, operating current is DD-OP1 FB Slope further reduced below 800 µA (I ) by disabling compensatin DD-OP2 several blocks of the FAN6757. The low operating current improves light-load efficiency and reduces the Figure 21. Current Mode Control Circuit Diagram requirement of V hold-up capacitance. DD Green-Mode Operation High-Voltage Startup and Line Sensing The FAN6757 modulates the PWM frequency as a The HV pin is typically connected to the AC line input function of the FB voltage to improve the medium- and through two external diodes and one resistor (R ), as HV light-load efficiency, as shown in Figure 22. Since the shown in Figure 24. When the AC line voltage is output power is proportional to the FB voltage in current- applied, the V hold-up capacitor is charged by the line DD mode control, the switching frequency decreases as voltage through the diodes and resistor. After V DD load decreases. In heavy-load conditions, the switching reaches the turn-on threshold voltage (V ), the DD-ON frequency is fixed at 65 kHz. Once V decreases below FB startup circuit charging V capacitor is switched off and DD V (2.8 V), the PWM frequency starts linearly FB-N V is supplied by the auxiliary winding of the DD decreasing from 65 kHz to 23 kHz to reduce switching transformer. Once the FAN6757 starts up, it continues losses. As V drops to V (2.3 V), where switching FB FB-G operation until V drops below 6.5 V (V ). The IC DD UVLO frequency is decreased to 23 kHz, the switching startup time with a given AC line input voltage is: frequency is fixed to avoid acoustic noise. 2 2 fS VACIN  fOSC tSTARTUP RHV CDDln 2 2 (1) V  V ACIN  DDON RHV HV fOSC-G 4 7 VDD + VDD Good - VFB-ZDC VFB-ZDCRVFB-G VFB-N VFB CDD VDD-ON/ Figure 22. VFB vs. PWM Frequency VRESTART When V falls below V (2.0 V) as load decreases CX RLS FB FB-ZDC Sampling Brown-in/out further, the FAN6757 enters Burst Mode operation, Circuit Function AC Line where PWM switching is disabled. Then the output High/ Low Line VLIMIT voltage starts to drop, causing the feedback voltage to Compensation VOCP rise. Once V rises above V (2.1 V), switching FB FB-ZDCR resumes. Burst Mode alternately enables and disables Figure 24. Startup Circuit © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1 11

F A The HV pin detects the AC line voltage using a switched increases. The current-limit level is also proportional to N voltage divider consisting of an external resistor (R ) the R resistor value and the power-limit level can be 6 HV HV 7 and an internal resistor (RLS), as shown in Figure 24. tuned using the RHV resistor. 5 The internal line-sensing circuit detects line voltage 7 — using a sampling circuit and a peak-detection circuit. 5.4 V Since the voltage divider causes power consumption PWM ZFB m Comparator 3R when it is switched on, the switching is driven by a 2 W signal with a very narrow pulse width to minimize power OSC FB S loss. The sampling frequency is also adaptively GATE ScoSmparator R a 8 DRV Q S v changed according to the load condition to minimize e power consumption in light-load condition. Q R VSS r® Based on the detected line voltage, brown-in and + P brownout thresholds are determined as: Current limit VLIMIT + comSpelonpsea tion W comparator M VBROWN-IN(RMS)2R0H0VkVAC2ON (2) 4HV SeLninsein g PCoowmerp Leinmsiat tLioinne SENSE6 Co n VBROWN-OUT (RMS)2R0H0VkVAC2OFF (3) Figure 25. Pulse-by-pulse Current Limit Circuit troll e Since the internal resistor (R =1.62 kΩ) of the voltage VLIMIT (V) r LS 0.5 divider is much smaller than R , the thresholds are HV given as a function of R . HV Note that VDD must be larger than VDD-AC to start up, 0.45 even though sensed line voltage satisfies Equation 2. RHV=240 kΩ AX-CAP® Discharge 0.4 RHV=200 kΩ The EMI filter in the front end of the Switched-Mode Power Supply (SMPS) typically includes a capacitor RHV=160 kΩ across the AC line connector. Most of the safety 0.35 regulations, such as UL 1950 and IEC61010-1, require the capacitor be discharged to a safe level within a given time when AC plug is removed from its receptacle. Typically, discharge resistors across the capacitor are 0.3 used to ensure the capacitor is discharged naturally, 70 110 150 190 230 270 which introduces power loss as long as it is connected Line Voltage (VAC) Figure 26. Current Limit vs. Line Voltage to the receptacle. The innovative AX-CAP® technology intelligently Under-Voltage Lockout (UVLO) discharges the filter capacitor only when the power As shown in Figure 27, as long as protection is not supply is unplugged from the power outlet. Since the triggered, the turn-off threshold of V is fixed internally AX-CAP® discharge circuit is disabled in normal DD at V (6.5 V). When Protection Mode is triggered, the UVLO operation, the power loss in the EMI filter can be V level to terminate PWM gate switching is changed DD virtually removed. to V (11 V), as shown in Figure 28. When V DD-OFF DD The discharge of the capacitor is achieved through the drops below V , switching is terminated and the DD-OFF HV pin. Once AC outlet detaching is detected, the operating current from VDD is reduced to I to slow DD-OLP FAN6757 discharges the capacitor across the AC line down the discharge of VDD until V reaches V . DD DD-OLP connector by the external resistor on the HV pin. This delays re-startup after shutdown by protection to minimize the input power and voltage/current stress of High/Low Line Compensation for Constant switching devices during fault condition. Power Limit V DD FAN6757 has pulse-by-pulse current limit, as shown in VDD-ON 17 V Figure 25, to limit the maximum input power with a given input voltage. If the output consumes beyond this maximum power, the output voltage drops triggering the overload protection. VUVLO 6.5 V VRESTART 4.7 V As shown in Figure 25, the high/low line compensation block adjusts the current-limit level, V , based on the LIMIT line voltage. Figure 26 shows how the pulse-by-pulse current-limit level changes with the line voltage for GATE different R resistors. To maintain the constant output HV power limit regardless of line voltage, the cycle-by-cycle t current-limit level, V , decreases as line voltage LIMIT Figure 27. V UVLO at Normal Mode DD © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1 12

F A V function. For OTP applications, an NTC thermistor, N DD VDD-ON 17 V RNTC, usually in series with a resistor RA, is connected 67 between the RT pin and ground. The internal current 5 source, I , (100 µA) introduces voltage on RT as: 7 RT — VDD-OFF 11 V VRTIRT(RNTCRA) (4) m W VDD-OLP 7 V At high ambient temperature, RNTC decreases reducing S VRT. When VRT is lower than VRTTH1 (1.035 V) for longer a than t (14.5 ms), the protection is triggered and the v D-OTP1 e FAN6757 enters latch mode protection. r GATE ® The OTP can be also trigged by pulling down the RT pin P t voltage using an opto-coupler or transistor. Once V is W RT less than V (0.7 V) for longer than t (185 µs), M Figure 28. V UVLO at Protection Mode RTTH2 D-OTP2 DD the protection is triggered and latch mode protection C Leading-Edge Blanking (LEB) begins. o n Each time the power MOSFET is switched on, a turn-on When OTP is not used, it is recommended to place a t r spike occurs on the sense resistor. To avoid premature 10 kΩ resistor between this pin and ground to prevent o l termination of the switching pulse, a leading-edge noise interference. le blanking time, tLEB, is introduced. During this blanking Sense-Pin Short-Circuit Protection r period, the current-limit comparator is disabled and cannot switch off the gate driver. FAN6757 provides safety protection for Limited Power Source (LPS) test. When the current-sense resistor is Gate Output / Soft Driving short circuited by a soldering defect during production, The BiCMOS output stage has a fast totem-pole gate the current-sensing information is not properly obtained, driver. The output driver is clamped by an internal which results in unstable operation of the power supply. 14.5 V Zener diode to protect power MOSFET gate from To protect the power supply against a short circuit over voltage. A soft driving is implemented to minimize across the current-sense resistor, the FAN6757 shuts electromagnetic interference (EMI) by reducing the down when the current-sense voltage is very low, even switching noise. with a relatively large duty cycle. As shown in Figure 29, VDD Over-Voltage Protection (OVP) the current-sense voltage is sampled tON-SSCP (4.55 µs) after the gate turn-on. If the sampled voltage (V ) is V over-voltage protection prevents IC damage from S-CS DD lower than V for 11 consecutive switching cycles over-voltage exceeding the IC voltage rating. When the SSCP (170 µs), the FAN6757 shuts down immediately. V V voltage exceeds 24.5 V, the protection is triggered. SSCP DD varies linearly with the line voltage. At 122 V DC input, it This protection is typically caused by open circuit of the is typically 50 mV (V ); while at 366 V DC, it is secondary-side feedback network. SSCP-L typically100 mV (V ). SSCP-H Soft-Start tD-SSCP An internal soft-start circuit progressively increases the pulse-by-pulse current-limit level of the MOSFET for VSENSE VS-CS 7 ms during startup to establish the correct working conditions for the transformers and capacitors. GATE Over-Temperature Protection (OTP) tON-SSCP The RT pin provides adjustable Over-Temperature Figure 29. Timing Diagram of SSCP Protection (OTP) and an external latch triggering © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1 13

F A N Typical Application Circuit 6 7 5 Application PWM Controller Input Voltage Range Output 7 — 65 W Notebook Adapter FAN6757MRMX 85 VAC ~ 265 VAC 19 V, 3.42 A m W S X-cap BD1 CDO RDO a 0.33F/275V 2A/600V 1nF/100V 23.5 v TF1 LO er 510H 1.5H ® VAC + P ZDSN DO W P6KE150A 20A/150V 1C00O01F/ 4C70O2F/ VO M 12C0INF/ FDRS1N07 25V 25V Co 1N4007 400V - n 1N4007 t r o Q1 lle FQPF7N65C r RG 20 RHV RSENSE 200k 0.176 FAN6757 RLPF 100 1 GND GATE 8 RD 2 FB VDD 7 1.2k R1 200k 34 NHCV SENRSET 65 4C7L0PpFF PC817A RF CF 4.7k 2.2nF C1nFFB RA DDD1N4935 5.6k 1R0N0kTC 4C7DDF/ 50V KA431 R2 30k Figure 30. Schematic of Typical Application Circuit Transformer Schematic Diagram  Core: Ferrite Core RM-10  Bobbin: RM-10 RM-10 3-Layer Tape 4 S N4 N1 3-Layer Tape 5 N2 Shielding N3 1-Layer Tape N 4 3-Layer Tape 6 F N2 3-Layer Tape Shielding 7 1-Layer Tape N1 N 3 9 Bobbin Figure 31. Transformer Specification © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1 14

F A Winding Specification N 6 7 Pin (Start → Finish) Wire Turns Winding Method Remark 5 7 N1 4 → 5 0.5φ×1 19 Solenoid Winding Enameled Copper Wire — Insulation: Polyester Tape, t = 0.025 mm, 1 Layer m W Shielding: Adhesive Tape of Copper Foil, t = 0.025×7 mm, 1.2 Layers, Open Loop, Connected to Pin 4 S Insulation: Polyester Tape t = 0.025 mm, 3 Layers a v N2 S → F 0.9φ×1 8 Solenoid Winding Triple Insulated Wire e r ® Insulation: Polyester Tape, t = 0.025mm, 3 Layers P N3 9 → 7 0.4φ×1 7 Solenoid Winding Enameled Copper Wire W Insulation: Polyester Tape, t = 0.025 mm, 1 Layer M C Shielding: Adhesive Tape of Copper Foil, t = 0.025×7 mm, 1.2 Layers, Open Loop, Connected to Pin 4 o n Insulation: Polyester Tape t = 0.025 mm, 3 Layers t r N4 5 → 6 0.5φ×1 19 Solenoid Winding Enameled Copper Wire o l l Insulation: Polyester Tape t = 0.025 mm, 3 Layers e r Electrical Characteristics Pin Specification Remark Primary-Side Inductance 4－6 510 H ±5% 1 kHz, 1 V Primary-Side Effective Leakage Inductance 4－6 20 H Maximum Short All Other Pins Typical Performance Table 1. Power Consumption Input Voltage Output Power Actual Output Power Input Power Specification No Load 0 W 0.045 W Input Power < 0.05 W 230 V 0.25 W 0.255 W 0.360 W Input Power < 0.5 W AC 0.5 W 0.521 W 0.711 W Input Power < 1 W Table 2. Efficiency Output Power 16.25 W 32.5 W 48.75 W 65 W Average 115 V 60 Hz 87.84% 87.42% 86.92% 86.23% 87.10% 230 V 50 Hz 87.88% 87.95% 87.82% 87.69% 87.83% © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6757 • Rev. 1.0.1 15

F A N Physical Dimensions 6 7 5 7 — m 5.00 W A 4.80 0.65 S a 3.81 v e r 8 5 ® B P W 1.75 M 6.20 5.80 4.00 5.60 C 3.80 o n t r o l l e r PIN ONE 1 4 INDICATOR 1.27 1.27 (0.33) 0.25 C B A LAND PATTERN RECOMMENDATION 0.25 SEE DETAIL A 0.10 0.25 1.75 MAX C 0.19 0.51 0.10 0.33 OPTION A - BEVEL EDGE 0.50 x 45° 0.25 R0.10 GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 8° NOTES: UNLESS OTHERWISE SPECIFIED 0° A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA. 0.90 SEATING PLANE B) ALL DIMENSIONS ARE IN MILLIMETERS. 0.40 C) DIMENSIONS DO NOT INCLUDE MOLD (1.04) FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. DETAIL A E) DRAWING FILENAME: M08Arev14 SCALE: 2:1 F) FAIRCHILD SEMICONDUCTOR. Figure 32. 8-Pin, SOP-8 Package Package drawings are provided as a service to customers considering our components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact our representative to verify or obtain the most recent revision. Package specifications do not expand the terms of our worldwide terms and conditions, specifically the warranty therein, which covers our products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/M0/M08A.pdf. © 2013 Fairchild Semiconductor Corporation FAN6757 • Rev. 1.0.1 16

F A N 6 7 5 7 — m W S a v e r ® P W M C o n t r o l l e r © 2013 Fairchild Semiconductor Corporation FAN6757 • Rev. 1.0.1 17

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