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F A N 6 2 September 2015 2 4 — S y n c FAN6224 h r o n Synchronous Rectification Controller for Flyback and o u Forward Freewheeling Rectification s R e c t i f Features Description ic a t  mWSaver™ Technology: FAN6224 is a secondary-side Synchronous Rectification io - Internal Green Mode to Stop SR Switching for (SR) controller to drive SR MOSFET for improved n Lower No-Load Power Consumption efficiency. The IC is suitable for flyback converters and C o forward freewheeling rectification. - 300 A Ultra-Low Green Mode Operating n t Current FAN6224 can be applied in Continuous or r o  Synchronous Rectification Controller Discontinuous Conduction Mode (CCM and DCM) and lle Quasi-Resonant (QR) flyback converters based on a r  Suited for High-Side and Low-Side of Flyback proprietary linear-predict timing-control technique. The f o Converters in QR, DCM, and CCM Operation benefits of this technique include a simple control r method without current-sense circuitry to accomplish F  Suited for Forward Freewheeling Rectification l noise immunity. y  PWM Frequency Tracking with Secondary-Side b With PWM frequency tracking and secondary-side a Winding Voltage Detection c winding voltage detection, FAN6224 can operate in both k  140 kHz Maximum Operation Frequency fixed- and variable-frequency systems up to 140kHz. a n  VDD Pin Over-Voltage Protection (OVP) FAN6224 detects output load condition and determines d  LPC Pin Open/Short Protection adjustable loading levels for Green Mode. In Green Fo Mode, the SR controller stops all SR switching operation r  RES Pin Open/Short Protection to reduce the operating current. Power consumption is w a  RP Pin Open/Short Protection maintained at a minimum level in light-load condition. rd  Internal Over-Temperature Protection (OTP) F r e  SOP-8 Package Available e w h Applications e e l  AC-DC NB Adapters in g  Open-Frame SMPS R e c t i f i c Ordering Information a t i o n Operating Packing Part Number Package Temperature Range Method FAN6224M -40°C to +105°C 8-Lead, Small Outline Package (SOP-8) Tape & Reel © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4

F A Typical Application Diagrams N 6 2 2 4 VIN N1 N2 ISR VOUT — N3 S Q2 VIN N1 ISR Q2 VDET VOUT ynch Q1 VDET ro VLRP1C LPC8 F3GAANT6E2524VDD7RES VRR3ES Q1 N2 VRRE3S RES7 F5AVND6D2243GA8TLPEC RV1LPC nous R RP 1 4 6 R RP 1 4GND6AGND R R4 GND AGND R2 ec 2 CRP RRP 4 CRP RRP tif ic a t i Figure 1. Flyback Low-Side SR Figure 2. Flyback High-Side SR o n C o n VIN VDET VOUT tro Q1 Q3 lle r f o ISR r F GATE VDD ly R1 LPC 3 5 RES R3 ba Q2 VLPC 8 FAN6224 7 VRES ck RP 1 4 6 a R2 GND AGND R4 nd CRP RRP F o r w Figure 3. Forward Freewheeling Rectification a r d F r e e w h e e l i n g R e c t i f i c a t i o n © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 2

F Internal Block Diagram A N 6 VDD GATE 2 2 5 3 4 Internal Bias — RP 1 0.35V +- CaTlcimuliantgio n SFreettqinuge nHciyg hM/Loodwe + Protection VCT Syn - c GAredejuns tMaboldee tGREEN-ON/OFF 10.5V/10.1VtGREEN-ON/OFF Green Mode Gate Expand Limit hr + o S&H CVaLlcPuC-l EaNte VLPC-EN 27.5V/26V - OVP RESET no LPC 8 2.5V +- btlLaPnCk-EiNng GATE S Q PWM Block Drive 26 AAGGNNDD us R Causal R Q e Function 1.45V - c + VCT ti Maximum Enable RESET fi Period S&H iCHR iDISCHR ca Internal OTP 1µA/V CT 0.256µA/V tio RESET n Fault Timing C Protection Protection o n t S&H r o l l 7 4 e r RES GND f o Figure 4. Block Diagram r F l y b a c k a n d F o r w a r d F r e e w h e e l i n g R e c t i f i c a t i o n © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 3

F Marking Information A N 6 : Fairchild Logo 2 2 Z: Plant Code 4 — ZXYTT X: Year Code 6224 Y: Week Code S y TT: Die Run Code n TM c T: Package Type (M = SOP) h r M: Manufacturing Flow Code o n o u s Figure 5. Top Mark R e c t i f i c Pin Configuration a t i o n LPC RES AGND VDD C o n t r o 8 7 6 5 l l e r f o FAN6224 r F l y b a 1 2 3 4 c k a n d F RP AGND GATE GND o rw a Figure 6. Pin Configuration r d F Pin Definitions r e e w Pin # Name Description h e Programmable. A resistor paralleled with a capacitor is connected to RP pin and reference e 1 RP ground externally. The timing to enter / exit Green Mode is programmable by the resistor, while li n the range of operating frequency is programmable by the capacitor. g 2, 6 AGND Signal Ground. R e 3 GATE Driver Output. The totem-pole output driver for driving the power MOSFET. c t i 4 GND Ground. MOSFET source connection. fi c Power Supply. The threshold voltages for startup and turn-off are 10.5 V and 10.1 V, a 5 VDD t respectively. io n Reset Control of Linear Predict. RES pin is used to detect output voltage level through a 7 RES voltage divider. An internal current source, I , is modulated by this voltage level on the DISCHR RES pin. Winding Detection. This pin is used to detect the voltage on the winding during the on-time 8 LPC period of the primary GATE. © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 4

F A Absolute Maximum Ratings N 6 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be 2 2 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 4 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. — The absolute maximum ratings are stress ratings only. S y Symbol Parameter Min. Max. Unit n c V DC Supply Voltage 30 V h DD r o VLPC Voltage on LPC Pin (TA=25°C) -0.3 7.0 V n o VRES Voltage on RES Pin (Continuously in -0.5 V) (TA=25°C) -1.5 7.0 V u s VRP Voltage on RP Pin (TA=25°C) -0.3 7.0 V R P Power Dissipation (T =25°C) 0.8 W e D A c t ΘJA Thermal Resistance (Junction-to-Air) 151 °C/W if i c ΘJC Thermal Resistance (Junction-to-Case) 58 °C/W a t TSTG Storage Temperature Range -55 150 °C io n TL Lead Temperature (Soldering) 10s 260 °C C Electrostatic Discharge Human Body Model, JESD22-A114 5500 o ESD V n Capability Charged Device Model, JESD22-C101 2000 tr o Notes: l l e 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. r 2. All voltage values, except differential voltages, are given with respect to GND pin. f o r F l y b a Recommended Operating Conditions c k The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended a n operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not d recommend exceeding them or designing to Absolute Maximum Ratings. F o Symbol Parameter Condition Min. Max. Unit r w a VLPC Voltage on LPC Pin 4.8 V r d V Voltage on RES Pin Continuous Operation 4.8 V RES F r V Voltage on RP Pin 0.5 2.5 V e RP e w h e e l i n g R e c t i f i c a t i o n © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 5

Electrical Characteristics F A V =15 V and T =25°C, unless otherwise noted. N DD A 6 Symbol Parameter Condition Min. Typ. Max. Unit 2 2 4 VOP Continuously Operating Voltage VDD-OFF VDD-OVP V — VDD-ON Turn-On Threshold Voltage 9.5 10.5 11.5 V S V Turn-Off Threshold Voltage 9.1 10.1 11.1 V y DD-OFF n Hysteresis Voltage for Turn-On / c VDD-HYST Turn-Off Threshold 0.1 0.7 V hr o IDD-OP Operating Current VCD=D=61050 0V p, FL PC=65 kHz, 7 8 mA no L u I Operating Current in Green Mode V =15 V 300 400 µA s DD-GREEN DD R VDD-OVP VDD Over-Voltage Protection 26.0 27.5 29.0 V e c VDD-OVP-HYST Hysteresis Voltage for VDD OVP 1.1 1.5 1.9 V ti f t V OVP Debounce Time(3) 100 µs ic VDD-OVP DD a Output Driver for internal SR Mosfet Section t i o Output Voltage Maximum n VZ (Clamp) 10 12 14 V C o VOL Output Voltage LOW VDD=12 V, IO=50 mA 0.5 V n t VOH Output Voltage HIGH VDD=12 V, IO=50 mA 9 V ro l t Rising Time VDD=12 V, CL=6 nF, 30 70 120 ns le R GATE=2 V~9 V r f V =12 V, C =6 nF, o t Falling Time DD L 20 50 100 ns r F GATE=9 V~2 V F l tPD_HIGH_LPC Propagation Delay to GATE t :0%~10%, V =12 V 150 250 ns yb R DD HIGH (LPC Trigger) a c tPD_LOW_LPC Propagation Delay to GATE LOW k (LPC Trigger(3) tF:100%~90%,VDD=12 V 150 ns a n d Limitation between LPC Rising fs=65 kHz 24.0 29.5 35.0 F t µs MAX-PERIOD Edge to Gate Falling Edge o fs=140 kHz 12.5 15.5 18.5 r w LPC Section a r tBNK Blanking Time for Charging CT(3) 150 ns d F fs=65 kHz, re R =75 k~200 k, 0.9 1.1 1.3 µs e RP w LPC Sampling Timing of Previous CRP=100 nF h t LPC-SMP Cycle f =140 kHz, e s e RRP=75 k~200 k, 0.5 0.6 0.7 µs lin C =1 nF g RP R VLPC-SOURCE Lower Clamp Voltage Source ILPC=10 µA 0 0.1 0.2 V e c Threshold Voltage for LPC to V >V , SR VLPC-HIGH-EN Enable SR ELnPaCb-HleIG H LPC-HIGH-EN 1.38 1.45 1.54 V tifi c SR Enable Threshold Clamp V =2.5 V at V a V LPC-EN LPC-HIGH 2.5 V t EN-CLAMP Voltage(3) >3 V io n Threshold Voltage on LPC Rising VLPC-TH-HIGH Edge(3) 1.22 V VLPC-CLAMP-H VLPC High Clamping Voltage VLPC>VLPC-CLAMP-H 5.7 6.2 6.7 V Threshold Voltage of V to VLPC-DIS Disable SR Gate SwitchLPinCg VLPC>VLPC-DIS 4.8 5.5 V tLPC-EN-RES No LPC Signal, Reset VLPC-EN(3) 95 s Continued on the following page… © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 6

F A Electrical Characteristics (Continued) N 6 2 VDD=15 V and TA=25°C, unless otherwise noted. 2 4 Symbol Parameter Condition Min. Typ. Max. Unit — S RES Section y n t V Sampling Time(3) t =5 µs 2.5 µs c RES-SMP RES SR_gate h r o Threshold Voltage of V to V RES V >V 1.3 1.6 2.0 V n RES-EN Enable SR Gate Switching RES RES-EN o u V V High Clamping Voltage V >V 5.7 6.2 6.7 V s RES-CLAMP-H RES RES RES-CLAMP-H R K V Drop Protection Ratio(3) V [n+1]<V [n] x K 85 % RES-DROP RES RES RES RES-DROP e c VRES-SOURCE VRES Low Clamping Voltage IRES=10 µA, VDD=15 V 0 0.2 0.4 V ti f Linear Prediction Section ic a RatioLPC Transfer Ratio of VLPC to ILPC(3) 1 µA/V tio Ratio Transfer Ratio of V to I (3) 0.256 µA/V n RES RES RES C Ratio Ratio /Ratio V =3 V,V =3 V C =100 nF 3.65 3.90 4.15 LPC-RES LPC RES RES LPC RP o n f =65 kHz, R =75 k~200 k, s RP 0.9 1.1 1.3 tr t Debounce Time for VLPC>VLPC- CRP=100 nF µs ol LPC-EN EN=0.875 x VLPC-HIGH fs=140 kHz, RRP=75 k~200 k, 0.5 0.6 0.7 ler CRP=1 nF fo Maximum Ratio of SR Gate On r RatioSR-LMT Time(3) RatioSR-LMT < tON-SR[n+1]/ tON-SR[n] 120 % Fl y t LPC Pulse Width Expansion Limit t < t [n+1]- t [n] 0.5 0.7 0.9 µs b LPC-EXP-LMT LPC-EXP-LMT LPC LPC a t LPC Pulse Width Shrink Limit t < t [n]- t [n+1] 0.6 0.8 1.0 µs c LPC-SRK-LMT LPC-SRK-LMT LPC LPC k Green Mode Section a n d t SR Gate On Time to Exit Green RRP=200 k, CRP=100 nF 5.5 5.9 6.3 µs F GREEN-OFF Mode R =75 k,C =1 nF 3.0 3.3 3.6 o RP RP r w t SR Gate On time to Enter Green RRP=200 k, CRP=100 nF 4.0 4.4 4.8 µs a GREEN-ON Mode RRP=75 k,CRP=1 nF 1.6 1.9 2.2 rd t Hysteresis Voltage for t F GREEN- GREEN- R =200 k, C =100 nF 1.5 µs r /t Threshold(3) RP RP e HYST(65kHz) On GREEN-Off e w t Hysteresis Voltage for t GREEN- GREEN- R =75 k,C =1 nF 1.4 µs h HYST(140kHz) On/tGREEN-Off Threshold(3) RP RP e e Number of Switching Cycles to l nGREEN-OFF Exit Green Mode(3) SR Gate On Time > tGREEN-OFF 15 times ing Number of Switching Cycles to R nGREEN-ON Enter Green Mode(3) SR Gate On Time < tGREEN-ON 3 times ec t Threshold Voltage for RP Pin Pull if VRP-OPEN High Protection 3.0 3.5 4.0 V ic a t V Threshold Voltage for RP Pin Pull 0.30 0.35 0.40 V io RP-SHORT Low Protection n No Gate Signal to Enter Green t 75 s GREEN-ENTER Mode(3) Continued on the following page… © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 7

F A Electrical Characteristics N 6 V =15 V and T =25℃, unless otherwise noted. 2 DD A 2 4 Symbol Parameter Condition Min. Typ. Max. Unit — Operation Frequency Setting Section S y Threshold Voltage for High / Low Set V > V for Higher n VCRP-TH Frequency Determination(3) OperaRtPing FCrRePq-thuency 0.35 V ch r Debounce Time for High / Low o t 170 µs n CRP-TH Frequency Determination(3) o u IRP-SOURCE RP Pin Source Current 8.5 9.5 10.5 µA s Casual Function Section R e f =65 kHz, c S t i (R =75 k~200 k, 480 680 880 ns f RP i c SR Turn-Off Dead Time by Causal CRP=100 nF) a tDEAD-CAUSAL Function fS=140 kHz, tio n (R =75 k~200 k, 350 500 650 ns RP C C =1 nF) RP o n If t (n+1) > t x t (n), S-PWM CAUSAL S-PWM t r t SR Stops Switching & Enters f =65 kHz to 140 kHz 130 150 170 % o CAUSAL-FAULT S l Green Mode le r (Assume SR Triggers Fault f o Causal Protection) If LPC Rises r Twice during t and F tCAUSAL_LEAVE Previous On-TCimAUeS AoL_f LVEAVE is 5.3 µs ly LPC-HIGH b Longer than t , then SR a LPC-EN c Leaves Fault Causal Protection(3) k a n Once CFR is Triggered, SR d Terminates & Forces SR to Enter Causal Function Regulator F tDEAD-CFR Green Mode (The Last Time from (CFR) 70 ns or SR Gate Falling to LPC Rising)(3) w a r d Internal Over-Temperature Protection for OTP F r Internal Threshold Temperature e TOTP for OTP(3) 140 °C ew h Hysteresis Temperature for T 20 °C e OTP-HYST Internal OTP(3) e l i Note: n g 3. Guaranteed by Design R e c t i f i c a t i o n © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 8

F A Typical Performance Characteristics N 6 2 2 4 — S y n c h r o n o u s R e c t i fi c a t i o n Figure 7. V vs. Temperature Figure 8. V vs. Temperature DD-ON DD-OFF C o n t r o l l e r f o r F l y b a c k a n d F o r w a r d Figure 9. tGREEN-OFF vs. Temperature Figure 10. tGREEN-OFF vs. Temperature F r e e w h e e l i n g R e c t i f i c a t i o n Figure 11. I vs. Temperature Figure 12. I vs. Temperature RP-SOURCE DD-GREEN © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 9

F A Typical Performance Characteristics (Continued) N 6 2 2 4 — S y n c h r o n o u s R e c t i f i c a t i o Figure 13. t vs. Temperature Figure 14. t vs. Temperature n DEAD-CAUSAL DEAD-CAUSAL C o n t r o l l e r f o r F l y b a c k a n d F o r w a r d Figure 15. VRES-EN vs. Temperature Figure 16. RatioLPC-RES vs. Temperature F r e e w h e e l i n g R e c t i f i c a t i o n Figure 17. t vs. Temperature Figure 18. t vs. Temperature LPC-EN LPC-EN © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 10

F A Typical Performance Characteristics (Continued) N 6 2 2 4 — S y n c h r o n o u s R e c t i fi c a t i o n Figure 19. t vs. Temperature Figure 20. t vs. Temperature MAX-PERIOD MAX-PERIOD C o n t r o l l e r f o r F l y b a c k a n d F o r w a r d Figure 21. VLPC-SOURCE vs. Temperature Figure 22. VRES-SOURCE vs. Temperature F r e e w h e e l i n g R e c t i f i c a t i o n Figure 23. t vs. R Figure 24. t vs. R GREEN-ON RP GREEN-OFF RP © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 11

F A Functional Description N 6 2 Body diode of Body diode of Body diode of Body diode of 2 SR MOSFET SR MOSFET SR MOSFET SR MOSFET 4 V V — GS GS Primary SynchronousRectifier Primary SynchronousRectifier Primary MOSFET MOSFET MOSFET MOSFET MOSFET S y n c V V h DET DET r o n VIN/n VIN/n o VIN/n+VOUT VIN/n+VOUT u s VOUT VOUT R e c t i f i V Blanking Time V c LPC VLPC-HIGH (tLPC-EN) LPC VLPC-HIGH at 0.875VLPC-HIGH 0.875VLPC-HIGH io n VLPC-TH-HIGH VLPC-TH-HIGH C o n VRES VRES tr o l l e r VRES-EN VRES-EN f o IM,max IM,max r F IM IM IM,av ly IDS ISR/n IDS b I a M,min I I /n c DS SR k I a M,min n d VCT VCT F o r w a r t t t t d PM.ON CT.DIS PM.ON CT.DIS F tL.DIS tL.DIS r e e Figure 25. Waveforms of Linear-Predict Timing Control in CCM and DCM / QR Flyback w h for Low-Side Application e e l i n g R e c t i f i c a t i o n © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 12

F A N 6 Body diode of Body diode of Body diode of Body diode of 2 SR MOSFET SR MOSFET SR MOSFET SR MOSFET 2 V V 4 GS GS Primary SynchronousRectifier Primary SynchronousRectifier Primary — MOSFET MOSFET MOSFET MOSFET MOSFET S y n V V DET DET c h r V /n V /n o IN V /n+V IN V /n+V n IN OUT IN OUT o V V u OUT OUT s R e c t VLPC VLPC-HIVGHLPC-EN= Blan(tkLPinCg-E NT)ime VLPC VLPC-HVIGLHPC-EN= ific 0.875VLPC-HIGH 0.875VLPC-HIGH a VLPC-TH-HIGH VLPC-TH-HIGH tio n C V V RES RES o n t tRES-SMP tRES-SMP ro VRES- EN VRES-E N lle IM,max IM,max r f o I I I M,av r M M IDS ISR/n IDS F IM,min ly IDS ISR/n b a I c M,min k V V a CT CT n d F o r tPM.ON tCT.DIS tPM.ON tCT.DIS w a tL.DIS tL.DIS rd Figure 26. Waveforms of Linear-Predict Timing Control in CCM and DCM / QR Flyback for F r High-Side Application e e Linear Predict Timing Control FAN6224 uses the LPC and RES pins with two sets of w h voltage dividers to sense DET voltage (V ) and output The SR MOSFET turn-off timing is determined by DET e voltage (V ), respectively; so V /n, t , and V e linear-predict timing control and the operation principle OUT IN PM.ON OUT l is based on the volt-second balance theorem, which can be obtained. As a result, tL,DIS, which is the on-time in of SR MOSFET, can be predicted by Equation 1. As g states: the inductor average voltage is zero during a shown in Figure 25, the SR MOSFET is turned on when R switching period in steady state, so the charge voltage the SR MOSFET body diode starts conducting and DET e and charge time product is equal to the discharge c voltage drops to zero. The SR MOSFET is turned off by t voltage and discharge time product. In flyback i linear-predict timing control. fi converters, the charge voltage on the magnetizing c a inductor is input voltage (VIN), while the discharge Circuit Realization t vtyopltiacagle wias verefoflremcste ds hoowut piunt Fvioglutareg e2 5(n. VTOhUeT ),f oallos wtinhge The linear-predict timing-control circuit generates a ion replica (V ) of the magnetizing current of the flyback equation can be drawn: CT transformer using an internal timing capacitor (C ), as T shown in Figure 27. Using the internal capacitor voltage, VIN tPM.ON nVOUT tL.DIS (1) the inductor discharge time (tL.DIS) can be detected indirectly, as shown in Figure 25. When C is discharged T where t is inductor charge time; t is inductor PM,ON L,DIS to zero, the SR controller turns off the SR MOSFET. discharge time; and n is turn ratio of primary windings (N ) to secondary windings (N ). 1 2 © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 13

F A VLPC Turn on SR Gate at N6 VDET VLPC-TH + the fallingS edgQe SR Gate VOUT Iann da dRdEitiSo nv,o cltoangsei dsehroinugld t hbee ulinnedaerr o4p.8e rVa,t ianngd r athnegree,f oLrPe:C 22 - VCTSTRur Gn aotfef R Q 4 — R1 R3 R V LPC8 iCHR VCT iDISCHR 7RES R12R2 ( INn.MAX VOUT)4.8 (8) Sy n R2 1µA/V CT 0.256µA/V R4 R4 V 4.8 (9) ch R3R4 OUT ro Figure 27. Simplified Linear-Predict Block n For high-side applications, as shown in Figure 2, an o The voltage-second balance equation for the primary- extra auxiliary winding (N3) is used to supply voltage for us side inductance of the flyback converter is given in controller. To detect output voltage, the RES pin is R Equation (1). Inductor current discharge time is given as: connected to the auxiliary winding through a set of e voltage dividers. As Figure 26 shows, V is c RES tL.DIS VInNVtPM.ON (2) pdrioodpeo rticoonnadl utcot s.V OTUTh ewrehfeonre ,S Rin foMrOmSatFioEnT oofr iVtsO UbTo diys tific OUT sampled at t after the primary-side MOSFET a RES-SMP t The voltage scale-down ratio between RES and LPC is turns off. As a result, Equation (4) can be rewritten as: io defined as K below: n 3.9 V ( ( IN V )V )t V t (10) C R /R R  Kn' n OUT OUT PM.ON OUT CT.DIS o K  R42/R31R24 (3) where n’ is the turn ratio of auxiliary windings (N3) to ntr secondary windings (N ). o 2 During tPM.ON, the charge current of CT is iCHR-iDICHR, The discharge time of C can be obtained as: lle while during tL.DIS, the discharge current is iDICHR. As a T r result, the current-second balance equation for internal 3.9 V f ( ( IN V )V )t o timing capacitor (CT) can be derived from: t  Kn' n OUT OUT PM.ON (11) r F 3.9 V CT.DIS VOUT ly ( ( IN V )V )t V t (4) b K n OUT OUT PM.ON OUT CT.DIS Therefore, when the voltage scale-down ratio (K) and a turn ratio (n’) product is 3.9; the discharge time, t , c Therefore, the discharge time of CT is given as: is the same as inductor current discharge time, tL.DCIST.. DTISo k a 3.9 V guarantee tCT.DIS is shorter than tL.DIS, the K and n’ n t  ( K ( nIN VOUT)VOUT)tPM.ON (5) pprroodduucctt sahroouulndd b e4 .0la~rg4e.5r. thWanh e3n. 9d. eIts iisg ntyinpgic athl eto vsoeltt atghee d F CT.DIS V o OUT divider of LPC, the consideration is the same as that of r When the voltage scale-down ratio between LPC and low-side application, which means that the linear w a RsHaEomwSee ( vKea)r s,i s c o3inn.9ds,ui dcthetoerir n dgic sutchhrerae rntgote le trdiamisncech eoa fro gCfe Tv o(ttlitCmaTg.eDeI S )d( tiiLsv. DidtIhSe)er. osdapivteiidsraefietri ndog.f RHrEaoSnw,g enev,o eterE, tqhuwaaht tetiuonrn ns drae(tt6ieo)r mn’a inmnidnu gs t( 8bt)he e tm akuveosntlt aingbteoe rd Fr resistors and internal circuit, the scale-down ratio (K) consideration and so that Equation (7) and (9) are e e should be larger than 3.9 to guarantee that t is modified as: w CT.DIS shorter than t . It is typical to set K around 4.0~4.5. h Referring to LF.DiIgSure 25, when LPC voltage is higher RR4R n'VOUT 2 (12) eel than V over a period of blanking time (t ) 3 4 in LPC-EN LPC-EN g and lower than V (1.22 V), then SR LPC-TH-HIGH R MOSFET can be triggered. Therefore, VLPC-EN must be R4 n'V 4.8 e lager than VLPC-TH-HIGH or the SR MOSFET cannot be R R OUT (13) c turned on. As a result, when designing the voltage 3 4 ti f divider of the LPC, considering the tolerance, R1 and ic R should satisfy the equation: a 2 t i o R R2R (VINn.MIN VOUT)1.54 (6) n 1 2 On the other hand, there is also a threshold voltage, V , for RES pin to enable SR switching, hence R RES-EN 3 and R must satisfy: 4 R 3 V 2 (7) R R OUT 3 4 © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 14

F A CCM Operation R resistance corresponds to longer t and N RP GREEN-ON t , and vice versa. Therefore, by setting 6 The typical waveforms of CCM operation in steady state GREEN-OFF 2 are shown as right side of Figure 25 and Figure 26. deixfifteinregn Gt rreeesins tManocdee oisf aRdRjuP,s ttahbel elo. ading of entering and 24 When the primary-side MOSFET is turned on, the — energy is stored in L . During the on-time of the m SR Gate S primary-side MOSFET (t ), the magnetizing current PM.ON y (IM) increases linearly from IM,min to IM,max. Meanwhile, Normal Mode Green Mode n internal timing capacitor (CT) is charged by current 3 Times ch sinocurrecaes e(siC lHinRe-iaDrIClyH.R ) proportional to VIN, so VCT also 1.9µs~4.4µs 1.9µs~4.4µs 1.9µs~4.4µs t ron When the primary-side MOSFET is turned off, the IM ou energy stored in Lm is released to the output. During the s inductor discharge time (tL.DIS), the magnetizing current R (I ) decreases linearly from I toI . At the same e M M,max M,min c time, the internal timing capacitor (CT) is discharged by t i current source (i ) proportional to V , so V also f DISCHR OUT CT i c decreases linearly. To guarantee the proper operation a of SR, it is important to turn off the SR MOSFET just t i o before SR current reaches IM,min so that the body diode t n of the SR MOSFET is naturally turned off. C Figure 28. Entering Green Mode DCM / QR Operation o n In DCM / QR operation, when primary-side MOSFET is SR Gate tr Green Mode Normal Mode o turned off, the energy stored in L is fully released to m l the output at the turn-off timing of primary-side 15 Times 3.3µs~5.9µs le r MOSFET. Therefore, the DET voltage continues f resonating until the primary-side MOSFET is turned on, 3.3µs~5.9µs 3.3µs~5.9µs o t r as depicted in Figure 25. While DET voltage is IM F resonating, DET voltage and LPC voltage drop to zero l y by resonance, which can trigger the turn-on of the SR b a MOSFET. To prevent fault triggering of the SR c MOSFET in DCM operation, a blanking time is k …… introduced to LPC voltage. The SR MOSFET is not a n turned on even when LPC voltage drops below V LPC-TH- d unless LPC voltage stays above 0.875 V HloIGnHger than the blanking time (tLPC-EN). The LtuPCrn-H-IoGnH t Fo timing of the SR MOFET is inhibited by gate inhibit time Figure 29. Resuming Normal Operation rw (tINHIBIT), once the SR MOSFET turns off, to prevent a fault triggering. 6.5 rd 6 F mWSaver™ Technology 5.5 r 5 tGREEN-OFF ee Green-Mode Operation s) 4.5 w  Tcoon dmitiionnim, izthee tShRe cpiorcwueitr isc odnissuamblpetdio nw haetn ltihgeh t-llooaadd (T.DIS 3.534 t hee decreases. As illustrated in Figure 28, the discharge tC 2.5 GREEN-ON lin times of the inductor and internal timing capacitor 2 g decrease as load decreases. If the discharge time of 1.5 R the internal timing capacitor (tCT.DIS) is shorter than 50 70 90 110 130 150 170 190 210 230 e tGREEN-ON for more than three cycles, then the SR circuit RRP (kΩ) ct enters Green Mode. Once FAN6224 enters Green if Figure 30. Adjustable t and t i Mode, the SR MOSFET stops switching and the major GREEN-ON GREEN-OFF c a internal block is shut down to further reduce the t i operating current of the SR controller. In Green Mode, o n the operating current reduces to 300 µA. This allows power supplies to meet stringent power conservation requirements. When the discharge time of the internal capacitor is longer than t for more than fifteen GREEN-OFF cycles, the SR circuit is enabled and resumes the normal operation, as shown in Figure 29. To enhance flexibility of design, t and t GREEN-ON GREEN-OFF are adjustable by the external resistor of the RP pin within a certain range. As shown in Figure 30, larger © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 15

F A Selection of Operating Frequency time of the internal timing capacitor (t ) is longer N DIS.CT than 120% of the previous on-time of the SR MOSFET 6 For different operating frequency range, internal 2 parameters of the SR controller should be different to (sthono-SwRn[n i-n1 ]F);i gtounr-eSR 3[n3]. iWs lhimenit eodu ttpou 1t 2lo0a%d ochf atonng-SeRs[n r-a1p],i dalys 24 optimize signal processing. The capacitor of the RP pin from light load to heavy load, voltage-second balance — (C ) is used to determine the operating frequency RP theorem may not be applied. In this transient state, gate S range of the SR controller. For low switching frequency expand limit protection is activated to prevent overlap y systems (<100 kHz), CRP is recommended as 10 nF; for between the SR Gate and the PWM gate. n high switching frequency systems (100k~140 kHz), C c RP h is recommended as 1nF. SR Gate is limited to 120% of t [n-1] r on-SR o t [n]= t [n-1]*120% n Causal Function ton-SR [n-1] on-SR on-SR o u Causal function is utilized to limit the time interval (t SR Gate s ) from the rising edge of V to the falling edge SoRf- t R MtphAreeX vSioRu sG astwei.t cAhsin sgh opwenri oind F(tigS-uPLrWPeMC 3) 1m, tinSRu-sM AaX ids eliamdi tetidm teo, VCT tDIS.CT [n-1] tDIS.CT [n] t ectif say tDEAD-CAUSAL. When the system operates at fixed ic frequency, whether voltage-second balance theorem VLPC a t can be applied or not, causal function can guarantee io reliable operation. n t C tSR-MAX= tS-PWM – tDEAD-CAUSAL o VLPC tS-PWM n Figure 33. Gate Expand Limit Protection t r o t ll VCT RES Dropping Protection er t RES dropping protection prevents V dropping too fo SR Gate SR On-Time StcuaRrun Gseaadlt eofu fifns bc tyi on mreufecrhe ncweit hvionl taag e,c VycRlEeS.’ , oTnh eV LPVCR rEiSs inigs R eEsdSagme.p Olendc ea VsR EaS r Fly t drops below 85% of VRES’, the SR Gate is turned off b immediately, as shown in Figure 34. When output a c voltage drops rapidly within a switching cycle, voltage- k Figure 31. Causal Function Operation second balance may not be applied; RES dropping a n protection is activated to prevent overlap. d F Fault Causal Timing Protection o VRES r Fault causal timing protection is utilized to disable the w SR Gate under some abnormal conditions. Once the VRES’ a switching period (t [n]) is longer than 150% of 0.85*VRES’ rd S-PWM t previous switching period (t [n-1]), the SR Gate is F disabled and enters Green SM-PoWdMe, as shown in Figure VLPC re 32. Since the rising edge of V among switching e LPC w periods (t ) is tracked for causal function, the S-PWM t h accuracy of switching period is important. Therefore, if e the detected switching period has a serious variation, SR Gate SR Gate is turned e off immediately li the SR Gate is terminated to prevent fault trigger. n t g tS-PWM [n-1] tS-PWM [n] > 1.5xtS-PWM [n-1] Figure 34. VRES Dropping Protection R VLPC ec LPC Width Expansion / Shrink Protection t i f i c t LPC width expansion and shrink protection is utilized to a disable the SR MOSFET switching under some t Disable io SR Gate SR Gate & abnormal conditions. As Figure 35 shows, once the n eMnotdeer Green LPC pulse width (tLPC[n]) is longer than that of previous t cycle (t [n-1]) for t , the LPC width LPC LPC-EXP-LMT expansion protection is triggered and SR MOSFET Figure 32. Fault Causal Timing Protection switching is terminated immediately. Figure 36 shows the timing diagram of LPC width shrink protection. Once t [n] is shorter than t [n-1], the SR MOSFET LPC LPC Gate Expansion Limit Protection switching also shuts down immediately. Gate expansion limit protection controls the on-time expansion of the SR MOSFET. Once the discharge © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 16

F A tLPC[n-1] tLPC[n] LPC-Short Protection: If VLPC is pulled to ground and N6 VLPC the charging current of timing capacitor (CT) is near 2 zero, SR Gate is not output. 2 4 — t SR Gate off S SR Gate RES Pin Open / Short Protection y n t c RES-Open Protection: If VRES is pulled to HIGH level, h Figure 35. VLPC Width Expand Protection the gate signal is extremely small and FAN6224 enters ro Green Mode. In addition, V is clamped at 6.2 V to n tLPC[n-1] tLPC[n] avoid RES pin damage. RES o u VLPC s RES-Short Protection: If VRES is lower than VRES-EN R (1.6 V), FAN6224 stops switching immediately and e t enters Green Mode. c t i f SR Gate SR Gate off Under-Voltage Lockout (UVLO) ic a t The power ON and OFF VDD threshold voltages are tio fixed at 10.5 V and 10.1 V, respectively. The FAN6224 n Figure 36. VLPC Width Shrink Protection can be used in various output voltage applications. C V Pin Over-Voltage Protection (OVP) o DD n t Over-Time Protection Over-voltage conditions are usually caused by an open r o Generally, the minimum operating frequency of PWM fdeaemdbaagcek t ol otohpe . SVRD DM OoSveFrE-vTo.l tWaghee np rtohtee cvtoioltna gper eovne tnhtes lle controller in normal status is above 65 kHz VDD pin exceeds 27.5 V; the SR controller stops r f (65~140 kHz). In FAN6224, there are two over-time o switching the SR MOSFET. r protections that force the SR controller to go into green F mode. As shown in upper part of Figure 37, the first one Over-Temperature Protection (OTP) l y is when the time between LPC pulses (from LPC falling b To prevent the SR Gate from fault triggering in high edge to rising edge) is longer than 95 us. This is a temperatures, internal over-temperature protection is c typically triggered when the primary side controller k operates in burst mode operation. To minimize the integrated in FAN6224. If the temperature is over a power consumption, FAN6224 enters into green mode 140°C, the SR Gate is disabled until the temperature n drops below 120°C. d in this condition. This green mode is also triggered F when the LCP voltage divider is malfunctioning. o r w Another condition is when the time duration from SR a turn-off to SR turn-on is longer than 75us as shown in r d lower part of Figure 37. This happens when the F PWM controller in the primary side goes into burst r mode operation at light load condition. ee w VLPC tLPC < 95uS tLPC > 95uS he VSR-GATE e li n g VLPC tSR-Gate < 75uS tSR-Gate > 75uS Disable tSR Gate & R VVSCRT-GATE enter Green Mode ect t if ic Figure 37. Over-Time Protection a t io n LPC Pin Open / Short Protection LPC-Open Protection: If V is higher than V LPC LPC-DIS for longer than debounce time t , FAN6224 stops LPC-HIGH switching immediately and enters Green Mode. VLPC is clamped at 6.2 V to avoid LPC pin damage. © 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6224 • Rev. 1.4 17

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