F A N 5 3 6 1 — 6 M H z FAN5361 , 6 0 6 MHz, 600 mA / 750 mA Synchronous Buck Regulator 0 m A / 7 Features Description 5 0 6 MHz Fixed-Frequency Operation The FAN5361 is a 600 mA or 750 mA, step-down, switching m voltage regulator that delivers a fixed output from a 2.3 V to A 35 µA Typical Quiescent Current 5.5 V input voltage supply. Using a proprietary architecture S Best-in-Class Load Transient Response with synchronous rectification, the FAN5361 is capable of y Best-in-Class Efficiency delivering a peak efficiency of 92%, while maintaining n c 600 mA or 750 mA Output Current Capability efficiency over 80% at load currents as low as 1 mA. h r 2.3 V to 5.5 V Input Voltage Range o The regulator operates at a nominal fixed frequency of n 1.0 to 1.90 V Fixed Output Voltage 6 MHz, which reduces the value of the external components o u Low Ripple Light-Load PFM Mode to 470 nH for the output inductor and 4.7 µF for the output s Forced PWM and External Clock Synchronization capacitor. The PWM modulator can be synchronized to an B Internal Soft-Start external frequency source. u c Input Under-Voltage Lockout (UVLO) At moderate and light loads, pulse frequency modulation is k Thermal Shutdown and Overload Protection used to operate the device in power-save mode with a R typical quiescent current of 35 µA. Even with such a low e 6-bump WLCSP, 0.4 mm Pitch g quiescent current, the part exhibits excellent transient u 6-pin 2 x 2 mm UMLP response during large load swings. At higher loads, the la Applications system automatically switches to fixed-frequency control, to operating at 6 MHz. In shutdown mode, the supply current r Cell Phones, Smart Phones drops below 1 µA, reducing power consumption. For Tablets, Netbooks®, Ultra-Mobile PCs applications that require minimum ripple or fixed frequency, 3G, LTE, WiMAX™, WiBro®, and WiFi® Data Cards PFM mode can be disabled using the MODE pin. Gaming Devices, Digital CamerasDC/DC Micro Modules The FAN5361 is available in 6-bump, 0.4 mm pitch, Wafer- Level Chip-Scale Package (WLCSP) and a 6-lead 2 x 2 mm ultra-thin MLP package (UMLP). Typical Applications FB GND MODE VIN 1 6 A1 A2 C OUT L1 SW B1 B2 EN CIN 4.7F L1 SW 2 (AGND) 5 EN CIN 470nH 2.2F 470nH 2.2F FB GND C1 C2 MODE VIN 3 4 4.7F COUT Figure 1. Typical Applications All trademarks are the property of their respective owners. © 2008 Semiconductor Components Industries, LLC. Publication Order Number: October-2017, Rev. 2 FAN5361/D

F A Ordering Information N 5 3 Output 6 Part Number Package Temperature Range Packing 1 Voltage(1) — FAN5361UC123X* 1.233 V 6 FAN5361UC182X 1.820 V WLCSP-6, 0.4 mm Pitch M H FAN5361UC19X 1.900 V z –40 to +85°C Tape and Reel , FAN5361UMP123X 1.233 V 6 0 FAN5361UMP15X 1.500 V 6-Lead, 2 x 2 mm UMLP 0 m FAN5361UMP182X 1.820 V A Note: / 1. Other voltage options available on request. Contact a ON Semiconductor representative. 7 5 0 * This device is End of Life. Please contact sales for additional information and assistance with replacement devices. m Pin Configurations A S y n c MODE A1 A2 VIN VIN A2 A1 MODE h r o n o SW B1 B2 EN EN B2 B1 SW u s B u FB C1 C2 GND GND C2 C1 FB ck R e g u Figure 2. WLCSP, Bumps Facing Down Figure 3. WLCSP, Bumps Facing Up l a t o r FB 1 6 GND P1 SW 2 5 EN (GND) MODE 3 4 VIN Figure 4. UMLP, Leads Facing Down Pin Definitions Pin # Name Description WLCSP UMLP MODE. Logic 1 on this pin forces the IC to stay in PWM mode. A logic 0 allows the IC to automatically switch to PFM during light loads. The regulator also synchronizes its switching A1 3 MODE frequency to four times the frequency provided on this pin. Do not leave this pin floating. When tying HIGH, use at least 1kΩ series resistor if VIN is expected to exceed 4.5 V. B1 2 SW Switching Node. Connect to output inductor. C1 1 FB Feedback / VOUT. Connect to output voltage. C2 6 GND Ground. Power and IC ground. All signals are referenced to this pin. Enable. The device is in shutdown mode when voltage to this pin is <0.4 V and enabled when B2 5 EN >1.2 V. Do not leave this pin floating. When tying HIGH, use at least 1 kΩ series resistor if VIN is expected to exceed 4.5 V. A2 4 VIN Input Voltage. Connect to input power source. www.onsemi.com 2

F A Absolute Maximum Ratings N 5 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above 6 the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended 1 exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings — are stress ratings only. 6 M Symbol Parameter Min. Max. Unit H VIN Input Voltage –0.3 7.0 V z, 6 VSW Voltage on SW Pin –0.3 VIN + 0.3(2) V 0 0 VCTRL EN and MODE Pin Voltage –0.3 VIN + 0.3(2) V m Other Pins –0.3 VIN + 0.3(2) V A / Electrostatic Discharge Human Body Model per JESD22-A114 4.0 7 ESD kV 5 Protection Level Charged Device Model per JESD22-C101 1.5 0 m TJ Junction Temperature –40 +150 °C A TSTG Storage Temperature –65 +150 °C S TL Lead Soldering Temperature, 10 Seconds +260 °C yn c Note: h 2. Lesser of 7 V or VIN+0.3 V. ro n o u s B Recommended Operating Conditions u c k The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating R conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend e exceeding them or designing to Absolute Maximum Ratings. g u l Symbol Parameter Min. Typ. Max. Unit a t o VCC Supply Voltage Range 2.3 5.5 V r IOUT Output Current 0 600 mA L Inductor 0.47 µH CIN Input Capacitor 2.2 µF COUT Output Capacitor 1.6 4.7 12.0 µF TA Operating Ambient Temperature –40 +85 °C TJ Operating Junction Temperature –40 +125 °C Thermal Properties Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer 1s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature TJ(max) at a given ambient temperate TA. Symbol Parameter Typical Unit WLCSP 150 °C/W JA Junction-to-Ambient Thermal Resistance UMLP 49 °C/W www.onsemi.com 3

F A Electrical Characteristics N 5 3 Minimum and maximum values are at VIN = VEN = 2.3V to 5.5V, VMODE = 0V (AUTO Mode), TA = -40°C to +85°C; circuit of 6 Figure 1, unless otherwise noted. Typical values are at TA = 25°C, VIN = VEN = 3.6 V. 1 — Symbol Parameter Conditions Min. Typ. Max. Unit 6 Power Supplies M H No Load, Not Switching 35 55 µA z IQ Quiescent Current PWM Mode 6 mA , 6 0 0 I(SD) Shutdown Supply Current VIN = 3.6 V, EN = GND 0.05 1.00 µA m VUVLO Under-Voltage Lockout Threshold Rising VIN 2.15 2.25 V A VUVHYST Under-Voltage Lockout Hysteresis 150 mV / 7 5 Logic Inputs: EN and MODE Pins 0 VIH Enable HIGH-Level Input Voltage 1.2 V m A VIL Enable LOW-Level Input Voltage 0.4 V S VLHYST Logic Input Hysteresis Voltage 100 mV y n IIN Enable Input Leakage Current Pin to VIN or GND 0.01 1.00 µA ch r Switching and Synchronization o n fSW Switching Frequency(3) VIN = 3.6 V, TA = 25°C 5.4 6.0 6.6 MHz o u fSYNC MODE Synchronization Range(3) Square Wave at MODE Input 1.3 1.5 1.7 MHz s B Regulation u c ILOAD = 0 to 750 mA(4) 1.832 1.900 1.957 k 1.900 V PWM Mode(4) 1.832 1.900 1.938 R e g ILOAD = 0 to 600 mA 1.784 1.820 1.875 u 1.820 V l PWM Mode 1.784 1.820 1.856 a VO OAcuctpuurta cVyo ltage ILOAD = 0 to 600 mA 1.470 1.500 1.545 V tor 1.500 V PWM Mode 1.470 1.500 1.530 ILOAD = 0 to 600 mA 1.207 1.233 1.272 1.233 V PWM Mode 1.207 1.233 1.259 tSS Soft-Start From EN Rising Edge 180 300 µs Output Driver PMOS On Resistance VIN = VGS = 3.6 V 350 RDS(on) m NMOS On Resistance VIN = VGS = 3.6 V 225 PMOS Open-Loop Peak Current VOUT = 1.233 V, 1.5 V, 1.82 V 900 1100 1250 ILIM(OL) Limit(5) VOUT = 1.9 V 1180 1375 1550 mA TTSD Thermal Shutdown CCM Only 150 °C THYS Thermal Shutdown Hysteresis 15 °C Notes: 3. Limited by the effect of tOFF minimum (see Figure 14 and Figure 15 in Typical Performance Characteristics). 4. Output voltage accuracy minimum: 1.862 V for VIN 2.7 to 5.5 V on 1.9 V option. 5. Refer to Operation Description and Typical Characteristics for closed-loop data. www.onsemi.com 4

F A N Typical Performance Characteristics 5 3 6 Unless otherwise noted, VIN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), VOUT = 1.82 V, TA = 25°C. 1 — 6 100% 100% M 95% 95% H z 90% 90% , 6 85% 85% 0 0 Efficiency 778050%%% AAuuttoo22..37VVIINN Efficiency 778050%%% 25C mA / 7 65% Auto3.6VIN 65% 85C 5 0 60% Auto4.2VIN 60% m 55% 55% -30C A 50% 50% S 1 10 100 1000 1 10 100 1000 y n ILOAD OutputCurrent(mA) I LOAD Output Current (mA) c h r Figure 5. Efficiency vs. Load Current and Input Supply Figure 6. Efficiency vs. Load Current and Temperature o n o u 100% s 100% 95% B 95% u 90% 90% c k 85% 85% R e Efficiency 778050%%% VIN=2.3V Efficiency 778050%%% gulato VIN=2.7V r 65% 65% VIN=3.6V Auto PFM/PWM 60% VIN=4.2V 60% 55% 55% Forced PWM 50% 50% 1 10 100 1000 1 10 100 1000 ILOAD OutputCurrent(mA) I LOAD Output Current (mA) Figure 7. 1.233 VOUT Efficiency vs. Load Current Figure 8. Efficiency, Auto PWM/PFM vs. Forced PWM and Supply 1.84 1.248 VIN=2.3V 1.243 VIN=2.7V 1.83 VIN=3.6V 1.238 V) VIN=4.2V (V)UT1.82 (VOUT VO VIN=2.3V 1.233 VIN=2.7V 1.81 1.228 VIN=3.6V VIN=4.2V 1.223 1.80 0 100 200 300 400 500 600 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Load Current(mA) ILOAD OutputCurrent(A) Figure 9. Load Regulation Figure 10. 1.233 VOUT Load Regulation vs. Input Supply www.onsemi.com 5

F A N Typical Performance Characteristics (Continued) 53 6 Unless otherwise noted, VIN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), VOUT = 1.82 V, TA = 25°C. 1 — 1.830 6 45 M 40 H 1.825 3.6VIN z 35 5.5VIN , 6 30 2.5VIN 0 (V) 1.820 Vpp) 25 0 m VOUT 1.815 Vout (m 20 A / 15 7 5 1.810 10 0 m AutoPWM/PFM 5 ForcedPWM A 1.805 0 S 1 10 100 1,000 0 100 200 300 400 500 600 y ILOAD OutputCurrent(mA) Load Current (mA) nc h Figure 11. Load Regulation, Auto PFM / PWM and Figure 12. 1.82 VOUT Peak-to-Peak Output Voltage r Forced PWM Ripple o n o 7 u 30 FPWM Mode s B 25 3.6VIN z)6 u 5.5VIN MH c 20 2.5VIN cy (5 k R n ut (mVpp) 15 Freque4 egul Vo ng at 10 hi3 VIN>2.9V o c r wit VIN=2.7V 5 S2 VIN=2.5V VIN=2.3V 0 1 0 100 200 300 400 500 600 0 0.1 0.2 0.3 0.4 0.5 0.6 Load Current (mA) Load Current (A) Figure 13. 1.233 VOUT Peak-to-Peak Output Voltage Figure 14. Effect of tOFF(MIN) on Reducing Switching Ripple Frequency 7 350 FPWM Mode z) H6 300 M AlwaysPWM y ( c5 250 uen mA) ng Freq34 Current(125000 Taht eth sewsietcbhoinrgdemrsode changes hi ad c o wit2 VIN>2.4V L100 S AlwaysPFM 50 1 VIN=2.3V PFMborder PWMborder 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Load Current (A) InputVoltage(V) Figure 15. 1.233 VOUT Effect of tOFF(MIN) on Reducing Figure 16. PFM / PWM Boundaries Switching Frequency www.onsemi.com 6

F A N Typical Performance Characteristics (Continued) 53 6 Unless otherwise noted, VIN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), VOUT = 1.82 V, TA = 25°C. 1 — 6 250 42 M H AlwaysPWM z 200 40 , 6 A) The switchingmode changes A) 0 nt(m 150 at theseborders ent ( 38 0 m LoadCurre 10500 AlwaysPFM PFMborder Quiescent Curr 3346 A / 750 m PWMborder 32 VEN=VIN A 0 VEN=1.8V S 2.5 3.0 3.5 4.0 4.5 5.0 5.5 30 y 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 n InputVoltage(V) VIN Input Voltage (V) ch r o Figure 17. 1.233 VOUT PFM / PWM Boundaries Figure 18. Quiescent Current vs. Input Voltage n o u 0.20 s B 0.18 u 0.16 VVIENN==50.V5V ck A)0.14 R µ nt (0.12 eg urre0.10 ul C a pply 0.08 tor u0.06 S 0.04 0.02 0.00 -40 -20 0 20 40 60 80 Ambient Temperature (°C) Figure 19. Shutdown Current vs. Temperature www.onsemi.com 7

F A N Typical Performance Characteristics (Continued) 5 3 Unless otherwise noted, VIN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), VOUT = 1.82 V, TA = 25°C, 5µs/div. horizontal sweep. 61 — 6 M H z , 6 0 0 m A / 7 5 0 m A S Figure 20. Line Transient 3.3 VIN to 3.9 VIN, Figure 21. Line Transient 3.3 VIN to 3.9 VIN, yn 50 mA Load, 10 µs/div. 250 mA Load, 10 µs/div. c h r o n o u s B u c k R e g u l a t o r Figure 22. Combined Line/Load Transient 3.9 to Figure 23. Combined Line/Load Transient 3.3 to 3.9 VIN 3.3 VIN Combined with 40 mA to 400 mA Load Transient Combined with 400 mA to 40 mA Load Transient Figure 24. Load Transient 0 to 150 mA, 2.5 VIN Figure 25. Load Transient 50 to 250 mA, 2.5 VIN www.onsemi.com 8

F A Typical Performance Characteristics (Continued) N 5 3 Unless otherwise noted, VIN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), VOUT = 1.82 V, TA = 25°C, 5 µs/div. horizontal sweep. 6 1 — 6 M H z , 6 0 0 m A / 7 5 0 m Figure 26. Load Transient 150 to 400 mA, 2.5 VIN Figure 27. Load Transient 0 to 150 mA, 3.6 VIN A S y n c h r o n o u s B u c k R e g u l a Figure 28. Load Transient 50 to 250 mA, 3.6 VIN Figure 29. Load Transient 150 to 400 mA, 3.6 VIN t o r Figure 30. Load Transient 0 to 150 mA, 4.5 VIN Figure 31. Load Transient 50 to 250 mA, 4.5 VIN Figure 32. Load Transient 150 to 400 mA, 4.5 VIN www.onsemi.com 9

F A N Typical Performance Characteristics (Continued) 53 6 Unless otherwise noted, VIN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), VOUT = 1.82 V, TA = 25°C, 5 µs/div. horizontal sweep. 1 — 6 M H z , 6 0 0 m A / 7 5 0 m A S y n Figure 33. Metallic Short Applied at VOUT, 50 μs/div. Figure 34. Metallic Short Applied at VOUT ch r o n o u s B u c k R e g u l a t o r Figure 35. Over-Current Fault Response, Figure 36. Over-Current Fault Response, RLOAD = 1 Ω RLOAD = 1 Ω, 50 μs/div. Figure 37. Overload Recovery to Light Load, 50 μs/div. Figure 38. Soft-Start, RLOAD = 50 Ω, 20 μs/div. www.onsemi.com 10

F A N Typical Performance Characteristics (Continued) 53 6 Unless otherwise noted, VIN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), VOUT = 1.82 V, TA = 25°C. 1 — 6 M H z , 6 0 0 m A / 7 5 0 m A SW S y n c h r o n o u s B u c k R Figure 39. SW-Node Jitter (Infinite Persistence), ILOAD = 200 mA, 50 ns/div. e g u l a t o r Figure 40. Power Supply Rejection Ratio at 300 mA Load www.onsemi.com 11

F A Operation Description N 5 3 The FAN5361 is a 600 mA or 750 mA, step-down, switching To prevent shut-down during soft-start, the following condition 6 voltage regulator that delivers a fixed output from an input must be met: 1 voltage supply of 2.3 V to 5.5 V. Using a proprietary — architecture with synchronous rectification, the FAN5361 is IDISP  ILOAD  IMAX(DC) (2) 6 capable of delivering a peak efficiency of 92%, while where IMAX(DC) is the maximum load current the IC is M maintaining efficiency over 80% at load currents as low as guaranteed to support (600 mA or 750 mA). H 1 mA. The regulator operates at a nominal frequency of z 6 MHz at full load, which reduces the value of the external Table 1 shows combinations of COUT that allow the IC to start , 6 components to 470 nH for the inductor and 4.7 µF for the successfully with the minimum RLOAD that can be supported. 0 0 output capacitor. Table 1. Minimum RLOAD Values for Soft-Start with m Control Scheme Various COUT Values A The FAN5361 uses a proprietary, non-linear, fixed-frequency COUT Minimum RLOAD / 7 PWM modulator to deliver a fast load transient response, 5 while maintaining a constant switching frequency over a wide 4.7 F, 0402 VOUT / 0.60 0 m range of operating conditions. The regulator performance is 2 X 4.7 F, 0402 VOUT / 0.60 A independent of the output capacitor ESR, allowing for the use of ceramic output capacitors. Although this type of operation 10 F, 0603 VOUT / 0.60 S y normally results in a switching frequency that varies with input 10 F, 0805 VOUT / 0.50 n voltage and load current, an internal frequency loop holds the c h svwoltiatcgheinsg a nfdre loqaude nccuyr recnotnss. t ant over a large range of input Startup into Large COUT ro n Multiple soft-start cycles are required for no-load startup if o For very light loads, the FAN5361 operates in Discontinuous u Current Mode (DCM) single-pulse PFM mode, which COUT is greater than 15 F. Large COUT requires light initial s load to ensure the FAN5361 starts appropriately. The IC produces low output ripple compared with other PFM B architectures. Transition between PWM and PFM is shuts down for 85 s when IDISP exceeds ILIMIT for more than u seamless, with a glitch of less than 18 mV at VOUT during the 21 s of current limit. The IC then begins a new soft-start ck transition between DCM and CCM modes. cycle. Since COUT retains its charge when the IC is off, the IC R reaches regulation after multiple soft-start attempts. e Combined with exceptional transient response g characteristics, the very low quiescent current of the MODE Pin u l controller (35 µA) maintains high efficiency; even at very light a Logic 1 on this pin forces the IC to stay in PWM mode. A t loads, while preserving fast transient response for o logic 0 allows the IC to automatically switch to PFM during r applications requiring tight output regulation. light loads. If the MODE pin is toggled, the converter synchronizes its switching frequency to four times the Enable and Soft-Start frequency on the mode pin (fMODE). When EN is LOW, all circuits in FAN5361 are off and the IC draws ~50 nA of current. When EN is HIGH and VIN is above The MODE pin is internally buffered with a Schmitt trigger, its UVLO threshold, the regulator begins a soft-start cycle. The which allows the MODE pin to be driven with slow rise and fall times. An asymmetric duty cycle for frequency output ramp during soft-start is a fixed slew rate of 50 mV/s synchronization is also permitted as long as the minimum from 0 to 1 VOUT, then 12.5 mV/s until the output reaches its setpoint. Regardless of the state of the MODE pin, PFM mode time below VIL(MAX) or above VIH(MAX) is 100 ns. is enabled to prevent current from being discharged from COUT Current Limit, Fault Shutdown, and Restart if soft-start begins when COUT is charged. A heavy load or short circuit on the output causes the current The IC may fail to start if heavy load is applied during startup in the inductor to increase until a maximum current threshold and/or if excessive COUT is used. This is due to the current- is reached in the high-side switch. Upon reaching this point, limit fault response, which protects the IC in the event of an the high-side switch turns off, preventing high currents from over-current condition present during soft-start. causing damage. The regulator continues to limit the current cycle-by-cycle. After 21 µs of current limit, the regulator The current required to charge COUT during soft-start is triggers an over-current fault, causing the regulator to shut commonly referred to as “displacement current” is given as: down for about 85s before attempting a restart. dV I C  (1) If the fault was caused by short circuit, the soft-start circuit DISP OUT dt attempts to restart and produces an over-current fault after about 32 s, which results in a duty cycle of less than 30%, dV limiting power dissipation. where the term refers to the soft-start slew rate above. dt The closed-loop peak-current limit, ILIM(PK), is not the same as the open-loop tested current limit, ILIM(OL), in the Electrical Characteristics table. This is primarily due to the effect of propagation delays of the IC current limit comparator. www.onsemi.com 12

F A Under-Voltage Lockout (UVLO) When VIN is LOW, fixed switching is maintained as long as N V 5 When EN is HIGH, the under-voltage lockout keeps the part OUT 1t f 0.7. 3 from operating until the input supply voltage rises high VIN OFF(MIN) SW 61 enough to properly operate. This ensures no misbehavior of — The switching frequency drops when the regulator cannot the regulator during startup or shutdown. provide sufficient duty cycle at 6MHz to maintain regulation. 6 Thermal Shutdown (TSD) This occurs when VOUT is greater than or equal to 1.82 V and M When the die temperature increases, due to a high load VIN is below 2.9 V at high load currents (see Figure 15). H z condition and/or a high ambient temperature, the output The calculation for switching frequency is given by: , 6 switching is disabled until the temperature on the die has 0 fallen sufficiently. The junction temperature at which the  1  0 thermal shutdown activates is nominally 150°C with a 15°C fSW min t , 6MHz (3) m hysteresis.  SW(MAX)  A / Minimum Off-Time Effect on Switching where: 7 5 Frequency 0 tOFF(MIN) is 50 ns. This imposes constraints on the maximum tSW(MAX) 50ns1VINVOUITOUTIOURTONROVFOFUT  (4) mA V OUT that the FAN5361 can provide, or the maximum where: S VIN y n output voltage it can provide at low VIN while maintaining a R =R DCR c fixed switching frequency in PWM mode. OFF DSON_N L h r RON =RDSON_P DCRL on o u s B u c k R e g u l a t o r www.onsemi.com 13

F A N Applications Information 5 3 6 Selecting the Inductor I  I 2  I2 (8) 1 — RMS OUT(DC) 12 The output inductor must meet both the required inductance 6 and the energy handling capability of the application. The The increased RMS current produces higher losses through M inductor value affects average current limit, the PWM-to- the RDS(ON) of the IC MOSFETs, as well as the inductor DCR. H PFM transition point, output voltage ripple, and efficiency. z Increasing the inductor value produces lower RMS currents, , The ripple current (∆I) of the regulator is: 6 but degrades transient response. For a given physical 0 inductor size, increased inductance usually results in an 0 IVOUT VIN VOUT  (5) inductor with lower saturation current and higher DCR. m VIN  LfSW  A Table 2 shows the effects of inductance higher or lower than / The maximum average load current, IMAX(LOAD), is related to the recommended 470 nH on regulator performance. 7 5 the peak current limit, ILIM(PK) by the ripple current, given by: Output Capacitor 0 m I I I (6) Table 3 suggests 0402 capacitors. 0603 capacitors may A MAX(LOAD) LIM(PK) 2 further improve performance in that the effective capacitance S is higher. This improves transient response and output ripple. y The transition between PFM and PWM operation is n determined by the point at which the inductor valley current Increasing COUT has no effect on loop stability and can c h crosses zero. The regulator DC current when the inductor therefore be increased to reduce output voltage ripple or to r current crosses zero, IDCM, is: improve transient response. Output voltage ripple, ∆VOUT, is: on o I  1  u IDCM  2 (7) VOUT I8COUT fSW ESR (9) s B u The FAN5361 is optimized for operation with L = 470 nH, but c Input Capacitor is stable with inductances up to 1.2 H (nominal). Up to k 2.2 H(nominal) may be used; however, in that case, VIN must The 2.2 F ceramic input capacitor should be placed as Re be greater than or equal to 2.7 V. The inductor should be rated close as possible between the VIN pin and GND to minimize g to maintain at least 80% of its value at ILIM(PK). the parasitic inductance. If a long wire is used to bring power ul to the IC, additional “bulk” capacitance (electrolytic or a Efficiency is affected by the inductor DCR and inductance tantalum) should be placed between CIN and the power to value. Decreasing the inductor value for a given physical size r source lead to reduce ringing that can occur between the typically decreases the DCR; but since ∆I increases, the RMS inductance of the power source leads and CIN. current increases, as do the core and skin effect losses. The effective capacitance value decreases as VIN increases due to DC bias effects. Table 2. Effects of Changes in Inductor Value (from 470 nH Recommended Value) on Regulator Performance Inductor Value I ∆V Transient Response MAX(LOAD) OUT Increase Increase Decrease Degraded Decrease Decrease Increase Improved Table 3. Recommended Passive Components and their Variation Due to DC Bias Component Description Vendor Min. Typ. Max.(6) Comment Murata LQM21PNR47MC0 470 nH, 2012, Minimum value occurs L1 Murata LQM21PNR54MG0 300 nH 470 nH 520 nH 90 m,1.1 A at maximum current Hitachi Metals HSLI-201210AG-R47 Murata or Equivalent Decrease primarily due 2.2 F, 6.3 V, CIN X5R, 0402 GRM155R60J225ME15 1.0 F 2.2 F 2.4 F to DC bias (VIN) and GRM188R60J225KE19D elevated temperature 4.7 F, X5R, Murata or Equivalent GRM155R60G475M Decrease primarily due COUT 0402 GRM155R60E475ME760 1.6 F 4.7 F 5.2 F to DC bias (VOUT) Note: 6. Higher inductance values are also acceptable. See “Selecting the Inductor” instructions in Applications Information. www.onsemi.com 14

F A N PCB Layout Guidelines 5 3 There are only three external components: the inductor and erratically due to excessive noise. This reduces switching 6 1 the input and output capacitors. For any buck switcher IC, cycle jitter and ensures good overall performance. It is — including the FAN5361, it is important to place a low-ESR important to place the common GND of CIN and COUT as close input capacitor very close to the IC, as shown in Figure 41. as possible to the FAN5361 C2 terminal. There is some 6 The input capacitor ensures good input decoupling, which flexibility in moving the inductor further away from the IC; in M helps reduce noise appearing at the output terminals and that case, VOUT should be considered at the COUT terminal. H z ensures that the control sections of the IC do not behave , 6 0 V 0 IN m A A1 A2 / 7 B1 B2 C 5 IN 0 m C1 C2 470nH GND A S y n c h C ro OUT n o u s V B OUT u c Figure 41. PCB Layout Guidance k R e g u l a t o The table below pertains to the Marketing Outline Drawing on the following page. r Product-Specific Dimensions Product D E X Y FAN5361UCX 1.370 ±0.040 0.970 ±0.040 0.285 0.285 www.onsemi.com 15

F A Physical Dimensions N 5 3 6 F 1 0.03 C — 2X E A 6 B 0.40 BALL A1 A1 M (Ø0.20) INDEX AREA Bottom of Cu Pad H z D F 0.40 , 6 (Ø0.30) 0 Solder Mask 0 0.03 C Opening 2X m TOP VIEW RECOMMENDED LAND PATTERN A (NSMD PAD TYPE) / 7 0.06 C 5 0.378±0.018 0 0.05 C 0.586±0.039 0.208±0.021 m A E S C SEATING PLANE y n D c SIDE VIEWS NOTES: h A. NO JEDEC REGISTRATION APPLIES. r o B. DIMENSIONS ARE IN MILLIMETERS. n Ø0.260±0.010 o 6X C. DIMENSIONS AND TOLERANCES PER u 0.40 ASMEY14.5M, 2009. s 0.005 C A B D. DATUM C, THE SEATING PLANE IS DEFINED B C BY THE SPHERICAL CROWNS OF THE BALLS. u c B (Y) +/-0.018 E. PACKAGE TYPICAL HEIGHT IS 586 MICRONS k 0.40 A ±39 MICRONS (547-625 MICRONS). R 1 2 F F. FOR DIMENSIONS D, E, X, AND Y SEE eg PRODUCT DATASHEET. u (X) +/-0.018 l G. DRAWING FILENAME: UC006ACrev5. a BOTTOM VIEW t o r Figure 42. 6-Bump WLCSP, 0.4mm Pitch www.onsemi.com 16

F A Physical Dimensions N 5 3 6 1 — 0.10 C 6 2X 2.0 A M H B z , 6 0 0 1.60 m 2.0 1.50 A 6 4 / 0.50 7 5 0.10 C 0 2X m 1.10 1.40 2.40 PIN1 A IDENT TOP VIEW S y n 1 3 c 0.30 h 0.55 MAX 0.65 r o 0.10 C n (0.15) o u RECOMMENDED LAND PATTERN s 0.08 C 0.05 0.00 C B u c k SEATING PLANE R e SIDE VIEW g u l a NOTES: t o r 1.50 A. OUTLINE BASED ON JEDEC REGISTRATION PIN1 MAX MO-229, VARIATION VCCC. IDENT 1 3 B. DIMENSIONS ARE IN MILLIMETERS. 1.10 C. DIMENSIONS AND TOLERANCES PER 0.35 MAX 6x ASME Y14.5M, 1994. 0.25 D. DRAWING FILENAME: MKT-UMLP06Crev1 6 4 0.35 0.65 6x 0.25 1.30 0.10 C A B 0.05 C BOTTOM VIEW Figure 43. 6-Lead, 2 x 2 mm, Ultra-Thin Molded Leadless Package (UMLP) www.onsemi.com 17

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