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F A N 3 2 October 2016 2 3 / F A N 3 FAN3223 / FAN3224 / FAN3225 2 2 4 Dual 4-A High-Speed, Low-Side Gate Drivers / F A N 3 Features Description 2 2  Industry-Standard Pinouts The FAN3223-25 family of dual 4 A gate drivers is 5 — designed to drive N-channel enhancement-mode  4.5-V to 18-V Operating Range MOSFETs in low-side switching applications by D  5-A Peak Sink/Source at V = 12 V providing high peak current pulses during the short u DD a  4.3-A Sink / 2.8-A Source at VOUT = 6 V sTwTiLtc hoinrg CinMteOrvSa ls.in Tpuhte dthrirveesrh oisld sa.v aIilnatbelren awl ithc ireciuthiteryr l 4  Choice of TTL or CMOS Input Thresholds provides an under-voltage lockout function by holding -A  Three Versions of Dual Independent Drivers: the output LOW until the supply voltage is within the H operating range. In addition, the drivers feature matched i - Dual Inverting + Enable (FAN3223) g internal propagation delays between A and B channels h - Dual Non-Inverting + Enable (FAN3224) for applications requiring dual gate drives with critical -S - Dual-Inputs (FAN3225) timing, such as synchronous rectifiers. This also pe  Internal Resistors Turn Driver Off If No Inputs ednoaubbllees t hceo cnunrercetnint gc atpwaob idlirtiyv edrrsiv iinng p aa rsainllegll et oM eOfSfeFcEtivTe. ly ed ,  MillerDrive™ Technology L The FAN322X drivers incorporate MillerDrive™ o  12-ns / 9-ns Typical Rise/Fall Times (2.2-nF Load) architecture for the final output stage. This bipolar- w  Under 20-ns Typical Propagation Delay Matched MOSFET combination provides high current during the -S within 1 ns to the Other Channel Miller plateau stage of the MOSFET turn-on / turn-off id process to minimize switching loss, while providing rail- e  Double Current Capability by Paralleling Channels to-rail voltage swing and reverse current capability. G  8-Lead 3x3 mm MLP or 8-Lead SOIC Package The FAN3223 offers two inverting drivers and the at e  Rated from –40°C to +125°C Ambient FAN3224 offers two non-inverting drivers. Each device D has dual independent enable pins that default to ON if  Automotive Qualified to AEC-Q100 (F085 Version) not connected. In the FAN3225, each channel has dual riv inputs of opposite polarity, which allows configuration as e Applications r non-inverting or inverting with an optional enable s function using the second input. If one or both inputs are  Switch-Mode Power Supplies left unconnected, internal resistors bias the inputs such  High-Efficiency MOSFET Switching that the output is pulled LOW to hold the power  Synchronous Rectifier Circuits MOSFET OFF.  DC-to-DC Converters Related Resources  Motor Control AN-6069 — Application Review and Comparative  Automotive-Qualified Systems (F085 version) Evaluation of Low-Side Gate Drivers ENA 1 8 ENB ENA 1 8 ENB INA- 1 8 INA+ + INA 2 A 7 OUTA INA 2 A 7 OUTA INB+ 2 A 7 OUTA - GND 3 6 VDD GND 3 6 VDD GND 3 6 VDD + INB 4 B 5 OUTB INB 4 B 5 OUTB INB- 4 -B 5 OUTB FAN3223 FAN3224 FAN3225 Figure 1. Pin Configurations © 2016 Semiconductor Components Industries, LLC www.onsemii.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15

F Ordering Information A N 3 2 Part Number Logic Input Package Packing Quantity 2 Threshold Method per Reel 3 / F FAN3223CMPX 3x3 mm MLP-8 Tape & Reel 3,000 A N FAN3223CMX CMOS SOIC-8 Tape & Reel 2,500 3 FAN3223CMX_F085(1) Dual Inverting SOIC-8 Tape & Reel 2,500 22 Channels + Dual 4 FAN3223TMPX Enable 3x3 mm MLP-8 Tape & Reel 3,000 / F FAN3223TMX TTL SOIC-8 Tape & Reel 2,500 A FAN3223TMX_F085(1) SOIC-8 Tape & Reel 2,500 N 3 FAN3224CMPX 3x3 mm MLP-8 Tape & Reel 3,000 2 2 5 FAN3224CMX CMOS SOIC-8 Tape & Reel 2,500 — FAN3224CMX_F085(1) SOIC-8 Tape & Reel 2,500 Dual Non-Inverting D FAN3224TMPX Channels + Dual 3x3 mm MLP-8 Tape & Reel 3,000 u Enable a FAN3224TMX SOIC-8 Tape & Reel 2,500 l TTL 4 FAN3224TMX_F085(1) SOIC-8 Tape & Reel 2,500 -A FAN3224TUMX_F085(2) SOIC-8 Tape & Reel 2,500 H i g FAN3225CMPX 3x3 mm MLP-8 Tape & Reel 3,000 h - FAN3225CMX CMOS SOIC-8 Tape & Reel 2,500 S FAN3225CMX_F085(1) Dual Channels of Two- SOIC-8 Tape & Reel 2,500 pe Input / One-Output e FAN3225TMPX Drivers 3x3 mm MLP-8 Tape & Reel 3,000 d , FAN3225TMX TTL SOIC-8 Tape & Reel 2,500 L o FAN3225TMX_F085(1) SOIC-8 Tape & Reel 2,500 w - Notes: S i 1. Qualified to AEC-Q100. d e 2. Modified UVLO thresholds. G a t e D r i v e r s © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 2

F A N Package Outlines 3 2 2 3 1 8 / F A 2 7 N 3 1 8 2 2 7 3 6 24 3 6 / F 4 5 4 5 A N Figure 2. 3x3 mm MLP-8 (Top View) Figure 3. SOIC-8 (Top View) 3 2 2 5 — Thermal Characteristics(3) D u Package  (4)  (5)  (6)  (7)  (8) Unit a JL JT JA JB JT l 4 8-Lead 3x3 mm Molded Leadless Package (MLP) 1.2 64 42 2.8 0.7 °C/W - A 8-Pin Small Outline Integrated Circuit (SOIC) 38 29 87 41 2.3 °C/W H i Notes: g 3. Estimates derived from thermal simulation; actual values depend on the application. h - 4. Theta_JL ( ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any S JL p thermal pad) that are typically soldered to a PCB. e 5. Theta_JT ( ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is e JT d held at a uniform temperature by a top-side heatsink. , 6. Theta_JA (Θ ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. L JA o The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2, w JESD51-5, and JESD51-7, as appropriate. - S 7. Psi_JB ( ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an JB i application circuit board reference point for the thermal environment defined in Note 6. For the MLP-8 package, the board d e reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the G SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. a 8. Psi_JT (JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and te the center of the top of the package for the thermal environment defined in Note 6. D r i v e r s © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 3

F A N 3 2 2 3 ENA 1 8 ENB ENA 1 8 ENB INA- 1 8 INA+ / F + INA 2 A 7 OUTA INA 2 A 7 OUTA INB+ 2 A 7 OUTA A - N GND 3 6 VDD GND 3 6 VDD GND 3 6 VDD 3 2 INB 4 B 5 OUTB INB 4 B 5 OUTB INB- 4 +-B 5 OUTB 24 / F A FAN3223 FAN3224 FAN3225 N Figure 4. Pin Assignments (Repeated) 32 2 5 Pin Definitions — Name Pin Description D u a Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and ENA l CMOS INx threshold. 4 - A Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and ENB H CMOS INx threshold. i g GND Ground. Common ground reference for input and output circuits. h - S INA Input to Channel A. p e INA+ Non-Inverting Input to Channel A. Connect to VDD to enable output. e d , INA- Inverting Input to Channel A. Connect to GND to enable output. L o INB Input to Channel B. w - S INB+ Non-Inverting Input to Channel B. Connect to VDD to enable output. i d INB- Inverting Input to Channel B. Connect to GND to enable output. e G OUTA Gate Drive Output A: Held LOW unless required input(s) are present and V is above UVLO threshold. a DD t e OUTB Gate Drive Output B: Held LOW unless required input(s) are present and V is above UVLO threshold. DD D r Gate Drive Output A (inverted from the input): Held LOW unless required input is present and V is i DD v OUTA above UVLO threshold. e r s Gate Drive Output B (inverted from the input): Held LOW unless required input is present and VDD is OUTB above UVLO threshold. Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected P1 to GND; NOT suitable for carrying current. VDD Supply Voltage. Provides power to the IC. Output Logic FAN3223 (x=A or B) FAN3224 (x=A or B) FAN3225 (x=A or B) ENx INx OUTx ENx INx OUTx INx+ INx− OUTx 0 0 0 0 0(9) 0 0(9) 0 0 0 1(9) 0 0 1 0 0(9) 1(9) 0 1(9) 0 1 1(9) 0(9) 0 1 0 1 1(9) 1(9) 0 1(9) 1 1 1 1(9) 0 Note: 9. Default input signal if no external connection is made. © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 4

F A N Block Diagrams 3 2 2 3 / VDD VDD F A N 100k 100k 3 ENA 1 8 ENB 2 2 4 V DD / F A 100k N 3 INA 2 OUTA 2 7 2 5 100k — GND 3 D UVLO 6 VDD u a l 4 VDD_OK -A V DD H i g 100k h OUTB 5 - INB 4 S p 100k e e d , L o w Figure 5. FAN3223 Block Diagram - S id e V V G DD DD a t e 100k 100k D ENA 1 8 ENB r i v e r s INA 2 7 OUTA 100k 100k UVLO 6 VDD GND 3 V DD_OK INB 4 5 OUTB 100k 100k Figure 6. FAN3224 Block Diagram © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 5

F A N Block Diagrams 3 2 2 3 / V F DD A N INA+ 8 3 2 2 4 / 100k F A INA- 1 7 OUTA N 3 100k 2 100k 2 5 — GND 3 VDD_OK D UVLO 6 VDD u VDD a l 4 INB+ 2 -A H i g h 100k - INB- 4 5 OUTB Sp e e 100k d 100k , L o w - S Figure 7. FAN3225 Block Diagram i d e G a t e D r i v e r s © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 6

F A N Absolute Maximum Ratings 3 2 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be 3 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. / In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. F A The absolute maximum ratings are stress ratings only. N 3 Symbol Parameter Min. Max. Unit 2 2 4 VDD VDD to PGND -0.3 20.0 V / F VEN ENA and ENB to GND GND - 0.3 VDD + 0.3 V A N VIN INA, INA+, INA–, INB, INB+ and INB– to GND GND - 0.3 VDD + 0.3 V 3 2 V OUTA and OUTB to GND DC GND - 0.3 V + 0.3 V 2 OUT DD 5 T Lead Soldering Temperature (10 Seconds) +260 ºC — L D T Junction Temperature -55 +150 ºC J u a TSTG Storage Temperature -65 +150 ºC l 4 - A H i g Recommended Operating Conditions h - S The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended p e operating conditions are specified to ensure optimal performance to the datasheet specifications. ON does not e recommend exceeding them or designing to Absolute Maximum Ratings. d , L Symbol Parameter Min. Max. Unit o w VDD Supply Voltage Range 4.5 18.0 V -S i V Supply Voltage Range (FAN3224TU only) 9.5 18.0 V d DD e V Enable Voltage ENA and ENB 0 V V G EN DD a VIN Input Voltage INA, INA+, INA–, INB, INB+ and INB– 0 VDD V te D VOUT OUTA and OUTB to GND Repetitive Pulse < 200 ns -2.0 VDD + 0.3 V r i v TA Operating Ambient Temperature -40 +125 ºC e r s © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 7

F A Electrical Characteristics N 3 2 Unless otherwise noted, VDD=12 V, TJ=-40°C to +125°C. Currents are defined as positive into the device and 2 negative out of the device. 3 / F Symbol Parameter Conditions Min. Typ. Max. Unit A N Supply 3 2 2 VDD Operating Range 4.5 18.0 V 4 / Supply Current, Inputs / EN Not All except FAN3225C 0.70 0.95 mA F IDD Connected FAN3225C(10) 0.21 0.35 mA AN 3 V Turn-On Voltage INA=ENA=V , INB=ENB=0 V 3.5 3.9 4.3 V 2 ON DD 2 5 V Turn-Off Voltage INA=ENA=V , INB=ENB=0 V 3.3 3.7 4.1 V OFF DD — FAN322xTMX_F085, FAN322xCMX_F085 (Automotive-Qualified Versions) D V Operating Range 4.5 18.0 V u DD a l Supply Current, Inputs / EN Not All Except FAN3225C 0.70 1.20 mA 4 IDD Connected(15) FAN3225C(10) 0.21 0.35 mA -A H VON Turn-On Voltage(15) INA=ENA=VDD, INB=ENB=0 V 3.4 3.9 4.5 V ig h VOFF Turn-Off Voltage(15) INA=ENA=VDD, INB=ENB=0 V 3.2 3.7 4.3 V -S p FAN3224TUMX_F085 (Modified UVLO Version) e e VDD Operating Range 9.5 18.0 V d , Supply Current, Inputs / EN Not L IDD Connected(15) 0.70 1.20 mA o w VON Turn-On Voltage(15) INA=ENA=VDD, INB=ENB=0 V 8.0 9.1 10.2 V -S i VOFF Turn-Off Voltage(15) INA=ENA=VDD, INB=ENB=0 V 7.0 8.2 9.3 V de Inputs (FAN322xT)(11) G a t V INx Logic LOW Threshold 0.8 1.2 V e INL_T D V INx Logic HIGH Threshold 1.6 2.0 V r INH_T i v V TTL Logic Hysteresis Voltage 0.2 0.4 0.8 V e HYS_T r s I Non-Inverting Input Current IN from 0 to V -1 175 µA IN+ DD I Inverting Input Current IN from 0 to V -175 1 µA IN- DD FAN322xTMX_F085, FAN3224TUMX_F085 (Automotive-Qualified Versions) V INx Logic LOW Threshold 0.8 1.2 V INL_T V INx Logic HIGH Threshold 1.6 2.0 V INH_T V TTL Logic Hysteresis Voltage 0.1 0.4 0.9 V HYS_T I Non-inverting Input Current(15) IN=0 V -1.5 1.5 µA INx_T I Non-inverting Input Current(15) IN=V 80 120 175 µA INx_T DD I Inverting Input Current(15) IN=0 V -175 -120 -90 µA INx_T I Inverting Input Current(15) IN=V -1.5 1.5 µA INx_T DD Inputs (FAN322xC)(11) V INx Logic Low Threshold 30 38 %V INL_C DD V INx Logic High Threshold 55 70 %V INH_C DD V CMOS Logic Hysteresis Voltage 17 %V HYS_C DD I Non-Inverting Input Current IN from 0 to V -1 175 µA IN+ DD © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 8

F Electrical Characteristics A N 3 Unless otherwise noted, V =12 V, T=-40°C to +125°C. Currents are defined as positive into the device and DD J 2 negative out of the device. 2 3 / Symbol Parameter Conditions Min. Typ. Max. Unit F A IIN- Inverting Input Current IN from 0 to VDD -175 1 µA N 3 FAN322xCMX_F085 (Automotive-Qualified Versions) 2 2 VINL_C INx Logic Low Threshold 30 38 %VDD 4 / V INx Logic High Threshold 55 70 %V INH_C DD F A V CMOS Logic Hysteresis Voltage 17 %V HYS_C DD N I Non-Inverting Input Current(15) IN=0 V -1.5 1.5 µA 3 INx_T 2 I Non-Inverting Input Current(15) IN=V 90 120 175 µA 2 INx_T DD 5 I Inverting Input Current(15) IN=0 V -175 -120 -90 µA — INx_T I Inverting Input Current(15) IN=V -1.5 1.5 µA D INx_T DD u ENABLE (FAN3223C, FAN3223T, FAN3224C, FAN3224T) a l V Enable Logic Low Threshold EN from 5 V to 0 V 0.8 1.2 V 4 ENL - A V Enable Logic High Threshold EN from 0 V to 5 V 1.6 2.0 V ENH H V TTL Logic Hysteresis Voltage(12) 0.4 V i HYS_T g R Enable Pull-Up Resistance(12) 100 kΩ h PU - S 0 V to 5 V EN, 1 V/ns Slew p tD3 Rate 9 17 26 ns e EN to Output Propagation Delay(13) e d 5 V to 0 V EN, 1 V/ns Slew tD4 Rate 11 18 28 ns , L o FAN3223C_TMX_F085, FAN3224C_TMX_F085, FAN3224TUMX_F085 (Automotive-Qualified Versions) w - V Enable Logic Low Threshold EN from 5 V to 0 V 0.8 1.2 V S ENL i d VENH Enable Logic High Threshold EN from 0 V to 5 V 1.6 2.0 V e V TTL Logic Hysteresis Voltage(12) 0.4 V G HYS_T a RPU Enable Pull-Up Resistance(12) 100 kΩ te 0 V to 5V EN, 1 V/ns Slew D tD3 Rate 6 17 34 ns ri EN to Output Propagation Delay(13,15) ve 5 V to 0V EN, 1 V/ns Slew r tD4 Rate 6 19 31 ns s Outputs I OUT Current, Mid-Voltage, Sinking(12) OUT at VDD/2, CLOAD=0.22 µF, 4.3 A SINK f=1 kHz OUT Current, Mid-Voltage, OUT at V /2, C =0.22 µF, ISOURCE Sourcing(12) f=1 kHz DD LOAD -2.8 A I OUT Current, Peak, Sinking(12) C =0.22 µF, f=1 kHz 5 A PK_SINK LOAD I OUT Current, Peak, Sourcing(12) C =0.22 µF, f=1 kHz -5 A PK_SOURCE LOAD t Output Rise Time(14) C =2200 pF 12 20 ns RISE LOAD t Output Fall Time(14) C =2200 pF 9 17 ns FALL LOAD Propagation Matching Between INA=INB, OUTA and OUTB at t 2 4 ns DEL.MATCH Channels 50% Point I Output Reverse Current Withstand(12) 500 mA RVS Output Propagation Delay, CMOS tD1, tD2 Inputs(14) 0 – 12 VIN, 1 V/ns Slew Rate 10 18 29 ns Output Propagation Delay, TTL tD1, tD2 Inputs(14) 0 – 5 VIN, 1 V/ns Slew Rate 9 17 29 ns © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 9

F Electrical Characteristics A N 3 Unless otherwise noted, V =12 V, T=-40°C to +125°C. Currents are defined as positive into the device and DD J 2 negative out of the device. 2 3 / Symbol Parameter Conditions Min. Typ. Max. Unit F A All Except for FAN3225C_TMX_F085 (Automotive-Qualified Versions) N tRISE Output Rise Time(14) CLOAD=2200 pF 12 20 ns 32 2 tFALL Output Fall Time(14) CLOAD=2200 pF 9 17 ns 4 / Propagation Matching Between INA=INB, OUTA and OUTB at t 2 4 ns F DEL.MATCH Channels 50% Point A N IRVS Output Reverse Current Withstand(12) 500 mA 3 2 Output Propagation Delay, CMOS 2 tD1, tD2 Inputs(14,15) 0 – 12 VIN, 1 V/ns Slew Rate 9 18 34 ns 5 — Output Propagation Delay, TTL tD1, tD2 Inputs(14,15) 0 – 5 VIN, 1 V/ns Slew Rate 6 16 30 ns D u VOH High Level Output Voltage(15) VOH =VDD–VOUT, IOUT=–1 mA 15 35 mV al 4 VOL Low Level Output Voltage(15) IOUT = 1 mA 10 25 mV -A FAN3225C_TMX_F085 (Automotive-Qualificed Versions) H i t Output Rise Time(14) C =2200 pF 12 28 ns g RISE LOAD h tFALL Output Fall Time(14) CLOAD=2200 pF 9 26 ns -S p VOH High Level Output Voltage(15) VOH =VDD–VOUT, IOUT=–1 mA 15 37 mV ee d VOL Low Level Output Voltage(15) IOUT = 1 mA 10 25 mV , L Notes: o 10. Lower supply current due to inactive TTL circuitry. w - 11. EN inputs have TTL thresholds; refer to the ENABLE section. S 12. Not tested in production. id 13. See Timing Diagrams of Figure 10 and Figure 11. e 14. See Timing Diagrams of Figure 8 and Figure 9. G 15. Applies only to _F085 versions. a t e D r i v e r s © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 10

F A Timing Diagrams N 3 2 2 3 / V V F Input INH Input INH AN V INL V 3 INL 2 2 4 t t D1 D2 t t / D1 D2 F A tRISE tFALL tFALL tRISE N3 2 90% 90% 2 5 Output Output — 10% 10% D u a l 4 - A Figure 8. Non-Inverting (EN HIGH or Floating) Figure 9. Inverting (EN HIGH or Floating) H i g h - S p HIGH HIGH e e Input Input d , LOW LOW L o w V -S ENH V Enable i ENH V d Enable ENL e V ENL G t t a tD3 tD4 D3 D4 te D t t RISE FALL r t t iv RISE FALL 90% e r 90% Output s Output 10% 10% Figure 10. Non-Inverting (IN HIGH) Figure 11. Inverting (IN LOW) © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 11

F A N Typical Performance Characteristics 3 2 2 Typical characteristics are provided at 25°C and V =12 V unless otherwise noted. DD 3 / F A N 3 2 2 4 / F A N 3 2 2 5 — D u a l 4 - A Figure 12. I (Static) vs. Supply Voltage(16) Figure 13. I (Static) vs. Supply Voltage(16) H DD DD i g h - S p e e d , L o w - S i d e G a t e D r i v e r Figure 14. I (Static) vs. Supply Voltage(16) s DD Figure 15. I (No-Load) vs. Frequency Figure 16. I (No-Load) vs. Frequency DD DD © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 12

F Typical Performance Characteristics A N 3 Typical characteristics are provided at 25°C and V =12 V unless otherwise noted. DD 2 2 3 / F A N 3 2 2 4 / F A N 3 2 2 5 — D u a l 4 Figure 17. IDD (2.2 nF Load) vs. Frequency Figure 18. IDD (2.2 nF Load) vs. Frequency -A H i g h - S p e e d , L o w - S i d e G a t e D r i v e Figure 19. IDD (Static) vs. Temperature(16) Figure 20. IDD (Static) vs. Temperature(16) rs Figure 21. I (Static) vs. Temperature(16) DD © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 13

F Typical Performance Characteristics A N 3 Typical characteristics are provided at 25°C and V =12 V unless otherwise noted. DD 2 2 3 / F A N 3 2 2 4 / F A N 3 2 2 5 — D u a l 4 Figure 22. Input Thresholds vs. Supply Voltage Figure 23. Input Thresholds vs. Supply Voltage -A H i g h - S p e e d , L o w - S i d e G a t e D r i v Figure 24. Input Threshold % vs. Supply Voltage e r s Figure 25. Input Thresholds vs. Temperature Figure 26. Input Thresholds vs. Temperature © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 14

F Typical Performance Characteristics A N 3 Typical characteristics are provided at 25°C and V =12 V unless otherwise noted. DD 2 2 3 / F A N 3 2 2 4 / F A N 3 2 2 5 — D u a l 4 Figure 27. UVLO Thresholds vs. Temperature Figure 28. UVLO Threshold vs. Temperature -A H i g h - S p e e d , L o w - S i d e G a t e D r iv Figure 29. UVLO Thresholds vs. Temperature e r s Figure 30. Propagation Delay vs. Supply Figure 31. Propagation Delay vs. Supply Voltage Voltage © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 15

F Typical Performance Characteristics A N 3 Typical characteristics are provided at 25°C and V =12 V unless otherwise noted. DD 2 2 3 / F A N 3 2 2 4 / F A N 3 2 2 5 — D u a l 4 Figure 32. Propagation Delay vs. Supply Figure 33. Propagation Delay vs. Supply - A Voltage Voltage H i g h - S p e e d , L o w - S i d e G a t e D r i v e Figure 34. Propagation Delays vs. Temperature Figure 35. Propagation Delays vs. Temperature rs Figure 36. Propagation Delays vs. Temperature Figure 37. Propagation Delays vs. Temperature © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 16

F Typical Performance Characteristics A N 3 Typical characteristics are provided at 25°C and V =12 V unless otherwise noted. DD 2 2 3 / F A N 3 2 2 4 / F A N 3 2 2 5 — D u a l 4 Figure 38. Fall Time vs. Supply Voltage Figure 39. Rise Time vs. Supply Voltage -A H i g h - S p e e d , L o w - S i d e G a t e D r i v e Figure 40. Rise and Fall Times vs. Temperature r s Figure 41. Rise/Fall Waveforms with 2.2 nF Figure 42. Rise/Fall Waveforms with 10 nF Load Load © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 17

F A N Typical Performance Characteristics 3 2 2 Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted. 3 / F A N 3 2 2 4 / F A N 3 2 2 5 — D u a l 4 - A Figure 43. Quasi-Static Source Current Figure 44. Quasi-Static Sink Current with H with VDD=12 V(17) VDD=12 V(17) ig h - S p e e d , L o w - S i d e G a t e D r i v e r s Figure 45. Quasi-Static Source Current Figure 46. Quasi-Static Sink Current with with V =8 V(17) V =8 V(17) DD DD Notes: 16. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high, static I increases by DD the current flowing through the corresponding pull-up/down resistor shown in the block diagram. 17. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the current-measurement loop. © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 18

F A N Test Circuit 3 2 2 3 / V F DD A N 3 4.7 µF 470 µF 2 2 ceramic Al. El. 4 / F Current Probe A N LECROY AP015 3 2 2 5 IOUT — IN 1 µF V CLOAD D 1 kHz ceramic OUT 0.22 µF u a l 4 - A Figure 47. Quasi-Static IOUT / VOUT Test Circuit H i g h - S p e e d , L o w - S i d e G a t e D r i v e r s © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 19

F A N Applications Information 3 2 2 Input Thresholds MillerDrive™ Gate Drive Technology 3 / Each member of the FAN322x driver family consists of FAN322x gate drivers incorporate the MillerDrive™ F A two identical channels that may be used independently architecture shown in Figure 48. For the output stage, a N at rated current or connected in parallel to double the combination of bipolar and MOS devices provide large 3 individual current capacity. In the FAN3223 and currents over a wide range of supply voltage and 2 2 FAN3224, channels A and B can be enabled or disabled temperature variations. The bipolar devices carry the 4 independently using ENA or ENB, respectively. The EN bulk of the current as OUT swings between 1/3 to 2/3 / pin has TTL thresholds for parts with either CMOS or V and the MOS devices pull the output to the HIGH or F DD A TTL input thresholds. If ENA and ENB are not LOW rail. N connected, an internal pull-up resistor enables the driver 3 The purpose of the MillerDrive™ architecture is to channels by default. ENA and ENB have TTL thresholds 2 speed up switching by providing high current during the 2 in parts with either TTL or CMOS INx threshold. If the 5 Miller plateau region when the gate-drain capacitance of channel A and channel B inputs and outputs are — the MOSFET is being charged or discharged as part of connected in parallel to increase the driver current the turn-on / turn-off process. D capacity, ENA and ENB should be connected and u driven together. For applications that have zero voltage switching during a l the MOSFET turn-on or turn-off interval, the driver The FAN322x family offers versions in either TTL or 4 supplies high peak current for fast switching even - CMOS input thresholds. In the FAN322xT, the input A thresholds meet industry-standard TTL-logic thresholds though the Miller plateau is not present. This situation H often occurs in synchronous rectifier applications independent of the VDD voltage, and there is a because the body diode is generally conducting before ig hysteresis voltage of approximately 0.4 V. These levels h the MOSFET is switched ON. - permit the inputs to be driven from a range of input logic S signal levels for which a voltage over 2 V is considered The output pin slew rate is determined by V voltage p DD e logic HIGH. The driving signal for the TTL inputs should and the load on the output. It is not user adjustable, but e have fast rising and falling edges with a slew rate of a series resistor can be added if a slower rise or fall time d , 6 V/µs or faster, so a rise time from 0 to 3.3 V should be at the MOSFET gate is needed. L 550 ns or less. With reduced slew rate, circuit noise o w could cause the driver input voltage to exceed the V DD - hysteresis voltage and retrigger the driver input, causing S i erratic operation. d e In the FAN322xC, the logic input thresholds are G dependent on the V level and, with V of 12V, the a DD DD t logic rising edge threshold is approximately 55% of VDD Input e and the input falling edge threshold is approximately D stage V 38% of VDD. The CMOS input configuration offers a OUT riv hysteresis voltage of approximately 17% of VDD. The e CMOS inputs can be used with relatively slow edges r s (approaching DC) if good decoupling and bypass techniques are incorporated in the system design to prevent noise from violating the input voltage hysteresis window. This allows setting precise timing intervals by fitting an R-C circuit between the controlling signal and Figure 48. MillerDrive™ Output Architecture the IN pin of the driver. The slow rising edge at the IN pin of the driver introduces a delay between the Under-Voltage Lockout controlling signal and the OUT pin of the driver. The FAN322x startup logic is optimized to drive ground- Static Supply Current referenced N-channel MOSFETs with an under-voltage lockout (UVLO) function to ensure that the IC starts up In the IDD (static) typical performance characteristics in an orderly fashion. When VDD is rising, yet below the (Figure 12 - Figure 14 and Figure 19 - Figure 21), the UVLO level, this circuit holds the output LOW, curve is produced with all inputs/enables floating (OUT regardless of the status of the input pins. After the part is low) and indicates the lowest static IDD current for the is active, the supply voltage must drop 0.2 V before the tested configuration. For other states, additional current part shuts down. This hysteresis helps prevent chatter flows through the 100 k resistors on the inputs and when low V supply voltages have noise from the DD outputs shown in the block diagram of each part (see power switching. This configuration is not suitable for Figure 5 - Figure 7). In these cases, the actual static IDD driving high-side P-channel MOSFETs because the low current is the value obtained from the curves plus this output voltage of the driver would turn the P-channel additional current. MOSFET ON with V below the UVLO level. DD © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 20

F A V Bypass Capacitor Guidelines For best results, make connections to all pins as N DD 3 short and direct as possible. To enable this IC to turn a device ON quickly, a local 2 high-frequency bypass capacitor, CBYP, with low ESR  The FAN322x is compatible with many other 23 and ESL should be connected between the VDD and industry-standard drivers. In single input parts with / GND pins with minimal trace length. This capacitor is enable pins, there is an internal 100 k resistor tied F A in addition to the bulk electrolytic capacitance of 10 µF to VDD to enable the driver by default; this should N to 47 µF commonly found on the driver and controller be considered in the PCB layout. 3 bias circuits. 2  The turn-on and turn-off current paths should be 2 4 A typical criterion for choosing the value of CBYP is to minimized, as discussed in the following section. / keep the ripple voltage on the VDD supply to ≤5%. This Figure 49 shows the pulsed gate drive current path F is often achieved with a value ≥20 times the equivalent A when the gate driver is supplying gate charge to turn the N load capacitance C , defined here as Q /V . EQV GATE DD MOSFET ON. The current is supplied from the local 3 Ceramic capacitors of 0.1 µF to 1 µF or larger are bypass capacitor, C , and flows through the driver to 2 common choices, as are dielectrics, such as X5R and BYP 2 the MOSFET gate and to ground. To reach the high 5 X7R with good temperature characteristics and high peak currents possible, the resistance and inductance in — pulse current capability. the path should be minimized. The localized CBYP acts D to contain the high peak current pulses within this driver- If circuit noise affects normal operation, the value of u C may be increased to 50-100 times the C , or MOSFET circuit, preventing them from disturbing the a CBBYYPP may be split into two capacitors. One shoulEdQ Vbe a sensitive analog circuitry in the PWM controller. l 4 larger value, based on equivalent load capacitance, and -A V V the other a smaller value, such as 1-10 nF mounted DD DS H closest to the VDD and GND pins to carry the higher i g frequency components of the current pulses. The h bypass capacitor must provide the pulsed current from CBYP -S both of the driver channels and, if the drivers are p switching simultaneously, the combined peak current e e sao suinrcgeled cfrhoamn ntehle i sC sBwYPit cwhoinugld. be twice as large as when FAN322x d, L o Layout and Connection Guidelines w PWM - The FAN3223-25 family of gate drivers incorporates S fast-reacting input circuits, short propagation delays, id and powerful output stages capable of delivering current e peaks over 4 A to facilitate voltage transition times from G Figure 49. Current Path for MOSFET Turn-On a under 10 ns to over 150 ns. The following layout and t e connection guidelines are strongly recommended: Figure 50 shows the current path when the gate driver D  Keep high-current output and power ground paths turns the MOSFET OFF. Ideally, the driver shunts the ri current directly to the source of the MOSFET in a small v separate logic and enable input signals and signal e circuit loop. For fast turn-off times, the resistance and ground paths. This is especially critical when inductance in this path should be minimized. rs dealing with TTL-level logic thresholds at driver inputs and enable pins. V V  Keep the driver as close to the load as possible to DD DS minimize the length of high-current traces. This reduces the series inductance to improve high- C speed switching, while reducing the loop area that BYP can radiate EMI to the driver inputs and FAN322x surrounding circuitry.  If the inputs to a channel are not externally connected, the internal 100 k resistors indicated on block diagrams command a low output. In noisy PWM environments, it may be necessary to tie inputs of an unused channel to VDD or GND using short traces to prevent noise from causing spurious output switching. Figure 50. Current Path for MOSFET Turn-Off  Many high-speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output re- triggering. These effects can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input, enable, or output leads. © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 21

F Truth Table of Logic Operation Operational Waveforms A N The FAN3225 truth table indicates the operational states At power-up, the driver output remains LOW until the 3 2 using the dual-input configuration. In a non-inverting V voltage reaches the turn-on threshold. The DD 2 driver configuration, the IN- pin should be a logic LOW magnitude of the OUT pulses rises with V until 3 DD signal. If the IN- pin is connected to logic HIGH, a disable steady-state V is reached. The non-inverting / DD F function is realized, and the driver output remains LOW operation illustrated in Figure 53 shows that the output A regardless of the state of the IN+ pin. remains LOW until the UVLO threshold is reached, then N the output is in-phase with the input. 3 IN+ IN- OUT 2 2 4 0 0 0 / 0 1 0 VDD F Turn-on threshold A 1 0 1 N 3 1 1 0 2 2 5 In the non-inverting driver configuration in Figure 51, the IN- — IN- pin is tied to ground and the input signal (PWM) is D applied to IN+ pin. The IN- pin can be connected to logic u HIGH to disable the driver and the output remains LOW, a regardless of the state of the IN+ pin. IN+ l 4 - VDD A H i g IN+ h PWM - OUT S FAN3225 OUT p IN- e e d GND , L Figure 53. Non-Inverting Startup Waveforms o w For the inverting configuration of Figure 52, startup -S waveforms are shown in Figure 54. With IN+ tied to id VDD and the input signal applied to IN–, the OUT e Figure 51. Dual-Input Driver Enabled, pulses are inverted with respect to the input. At power- G Non-Inverting Configuration up, the inverted output remains LOW until the VDD at voltage reaches the turn-on threshold, then it follows the e In the inverting driver application in Figure 52, the IN+ input with inverted phase. D pin is tied HIGH. Pulling the IN+ pin to GND forces the r i output LOW, regardless of the state of the IN- pin. v e r VDD s VDD Turn-on threshold IN+ OUT IN- FAN3225 IN- PWM GND IN+ (VDD) Figure 52. Dual-Input Driver Enabled, Inverting Configuration OUT Figure 54. Inverting Startup Waveforms © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 22

F Thermal Guidelines A N Gate drivers used to switch MOSFETs and IGBTs at To give a numerical example, assume for a 12 V VDD 3 high frequencies can dissipate significant amounts of (V ) system, the synchronous rectifier switches of 2 BIAS 2 power. It is important to determine the driver power Figure 55 have a total gate charge of 60 nC at 3 dissipation and the resulting junction temperature in the VGS = 7 V. Therefore, two devices in parallel would have / F application to ensure that the part is operating within 120 nC gate charge. At a switching frequency of A acceptable temperature limits. 300 kHz, the total power dissipation is: N 3 The total power dissipation in a gate driver is the sum of 2 two components, P and P : PGATE = 120 nC • 7 V • 300 kHz • 2 = 0.504 W (5) 2 GATE DYNAMIC 4 P = P + P (1) PDYNAMIC = 3.0 mA • 12 V • 1 = 0.036 W (6) / F TOTAL GATE DYNAMIC A PGATE (Gate Driving Loss): The most significant power PTOTAL = 0.540 W (7) N loss results from supplying gate current (charge per 3 The SOIC-8 has a junction-to-board thermal 2 unit time) to switch the load MOSFET on and off at characterization parameter of  = 42°C/W. In a 2 the switching frequency. The power dissipation that JB 5 system application, the localized temperature around results from driving a MOSFET at a specified gate- — the device is a function of the layout and construction of source voltage, VGS, with gate charge, QG, at the PCB along with airflow across the surfaces. To D switching frequency, fSW, is determined by: ensure reliable operation, the maximum junction u a temperature of the device must be prevented from l PGATE = QG • VGS • fSW • n (2) exceeding the maximum rating of 150°C; with 80% 4- A where n is the number of driver channels in use (1 or 2). derating, TJ would be limited to 120°C. Rearranging Equation 4 determines the board temperature required H P (Dynamic Pre-Drive / Shoot-through i DYNAMIC to maintain the junction temperature below 120°C: g Current): A power loss resulting from internal current h consumption under dynamic operating conditions, T = T - P •  (8) -S including pin pull-up / pull-down resistors. The internal B,MAX J TOTAL JB p e current consumption (IDYNAMIC) can be estimated using T = 120°C – 0.54 W • 42°C/W = 97°C (9) e the graphs in Figure 15 and Figure 16 of the Typical B,MAX d Performance Characteristics to determine the current , L I drawn from V under actual operating o DYNAMIC DD w conditions: - S i P = I • V • n (3) d DYNAMIC DYNAMIC DD e where n is the number of driver ICs in use. Note that n is G usually be one IC even if the IC has two channels, a unless two or more.driver ICs are in parallel to drive a te large load. D r Once the power dissipated in the driver is determined, iv the driver junction rise with respect to circuit board can e r be evaluated using the following thermal equation, s assuming  was determined for a similar thermal JB design (heat sinking and air flow): T = P •  + T (4) J TOTAL JB B where: T = driver junction temperature; J  = (psi) thermal characterization parameter JB relating temperature rise to total power dissipation; and T = board temperature in location as defined in B the Thermal Characteristics table. © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.1.5 23

F A Typical Application Diagrams N 3 2 2 3 / F A V IN N VOUT 3 2 2 4 / F A PWM N 3 1 8 FAN3224 2 2 2 7 1 ENA ENB8 5 Timing/ 3 6 Vbias — 2 A 7 Isolation 4 5 3 GND VDD 6 D FAN3224 4 B 5 ua l Figure 55. High Current Forward Converter Figure 56. Center-Tapped Bridge Output with 4 - with Synchronous Rectification Synchronous Rectifiers A H i g h - S p e Vin QC QA e d , L o w - S i QD QB d e G FAN3224 a t e D r i v e PWM-A r FAN3225 SR-1 s Secondary PWM-B Phase Shift SR-2 Controller PWM-C FAN3225 PWM-D Figure 57. Secondary Controlled Full Bridge with Current Doubler Output, Synchronous Rectifiers (Simplified) © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 24

F A N 3 Table 1. Related Products 2 2 Gate 3 Part Input Type Drive(18) Logic Package / Number Threshold F (Sink/Src) A N Single 1 A FAN3111C +1.1 A / -0.9 A CMOS Single Channel of Dual-Input/Single-Output SOT23-5, MLP6 3 2 Single 1 A FAN3111E +1.1 A / -0.9 A External(19) Single Non-Inverting Channel with External Reference SOT23-5, MLP6 2 4 Single 2 A FAN3100C +2.5 A / -1.8 A CMOS Single Channel of Two-Input/One-Output SOT23-5, MLP6 / F A Single 2 A FAN3100T +2.5 A / -1.8 A TTL Single Channel of Two-Input/One-Output SOT23-5, MLP6 N Single 2 A FAN3180 +2.4 A / -1.6 A TTL Single Non-Inverting Channel + 3.3-V LDO SOT23-5 3 2 2 Dual 2 A FAN3216T +2.4 A / -1.6 A TTL Dual Inverting Channels SOIC8 5 — Dual 2 A FAN3217T +2.4 A / -1.6 A TTL Dual Non-Inverting Channels SOIC8 D Dual 2 A FAN3226C +2.4 A / -1.6 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 u a Dual 2 A FAN3226T +2.4 A / -1.6 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 l 4 Dual 2 A FAN3227C +2.4 A / -1.6 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 - A Dual 2 A FAN3227T +2.4 A / -1.6 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 H i Dual 2 A FAN3228C +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8 g h - Dual 2 A FAN3228T +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8 S p Dual 2 A FAN3229C +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8 e e Dual 2 A FAN3229T +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8 d , L 20 V Non-Inverting Channel (NMOS) and Inverting Dual 2 A FAN3268T +2.4 A / -1.6 A TTL SOIC8 o Channel (PMOS) + Dual Enables w - 30 V Non-Inverting Channel (NMOS) and Inverting S Dual 2 A FAN3278T +2.4 A / -1.6 A TTL Channel (PMOS) + Dual Enables SOIC8 id e Dual 4 A FAN3213T +4.3 A / -2.8 A TTL Dual Inverting Channels SOIC8 G a Dual 4 A FAN3214T +4.3 A / -2.8 A TTL Dual Non-Inverting Channels SOIC8 t e Dual 4 A FAN3223C +4.3 A / -2.8 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 D r Dual 4 A FAN3223T +4.3 A / -2.8 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 iv e Dual 4 A FAN3224C +4.3 A / -2.8 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 r s Dual 4 A FAN3224T +4.3 A / -2.8 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 Dual 4 A FAN3225C +4.3 A / -2.8 A CMOS Dual Channels of Two-Input/One-Output SOIC8, MLP8 Dual 4 A FAN3225T +4.3 A / -2.8 A TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8 Single 9 A FAN3121C +9.7 A / -7.1 A CMOS Single Inverting Channel + Enable SOIC8, MLP8 Single 9 A FAN3121T +9.7 A / -7.1 A TTL Single Inverting Channel + Enable SOIC8, MLP8 Single 9 A FAN3122T +9.7 A / -7.1 A CMOS Single Non-Inverting Channel + Enable SOIC8, MLP8 Single 9 A FAN3122C +9.7 A / -7.1 A TTL Single Non-Inverting Channel + Enable SOIC8, MLP8 Dual 12 A FAN3240 +12.0 A TTL Dual-Coil Relay Driver, Timing Config. 0 SOIC8 Dual 12 A FAN3241 +12.0 A TTL Dual-Coil Relay Driver, Timing Config. 1 SOIC8 Notes: 18. Typical currents with OUTx at 6 V and V =12 V. DD 19. Thresholds proportional to an externally supplied reference voltage. © 2016 Semiconductor Components Industries, LLC www.onsemi.com FAN3223 / FAN3224 / FAN3225 • Rev. 1.15 25

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0.10 C 3.00 A 2.37 B 8 5 2X 1.99 3.00 1.42 3.30 PIN1IDENT (0.65) 0.10 C TOPVIEW 1 4 2X 0.65TYP 0.42TYP RECOMMENDEDLANDPATTERN 0.80MAX 0.10 C (0.20) 0.08 C 0.05 0.00 FRONTVIEW C NOTES: SEATING A.CONFORMSTOJEDECREGISTRATIONMO-229, PLANE VARIATIONVEEC,DATED112001. 0.45 2.25MAX B.DIMENSIONSAREINMILLIMETERS. 1 4 0.20 C.DIMENSIONSANDTOLERANCESPER PIN1IDENT ASMEY14.5M,2009. D.LANDPATTERNRECOMMENDATIONIS EXISTINGINDUSTRYLANDPATTERN. 1.30MAX E.DRAWINGFILENAME:MKT-MLP08Drev3 8 5 0.25 0.35 0.65 1.95 0.10 C A B 0.05 C BOTTOMVIEW

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