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F A N 3 2 September 2015 1 3 / F A N 3 FAN3213 / FAN3214 2 1 4 Dual-4 A, High-Speed, Low-Side Gate Drivers — D u Features a Description l- 4  Industry-Standard Pin Out A The FAN3213 and FAN3214 dual 4 A gate drivers are ,  4.5 to 18 V Operating Range designed to drive N-channel enhancement-mode H i  5 A Peak Sink/Source at V = 12 V MOSFETs in low-side switching applications by g DD h  4.3 A Sink / 2.8 A Source at VOUT = 6 V pswroitvcidhiinngg ihnitgehr vaplesa. kT hceuyr reanret pbuoltshe sa vdauilrainbgle twheit h sThoTrLt -S  TTL Input Thresholds input thresholds. Internal circuitry provides an under- pe  Two Versions of Dual Independent Drivers: voltage lockout function by holding the output LOW until ed - Dual Inverting (FAN3213) tahded itsiounp,p ly thveo ltagderi viesr sw ithfeina tuthree opmearatcthinegd raningtee.r nIanl , L - Dual Non-Inverting (FAN3214) propagation delays between A and B channels for ow  Internal Resistors Turn Driver Off If No Inputs applications requiring dual gate drives with critical -S timing, such as synchronous rectifiers. This also i  MillerDrive™ Technology enables connecting two drivers in parallel to effectively d e  12 ns / 9 ns Typical Rise/Fall Times with 2.2 nF double the current capability driving a single MOSFET. G Load The FAN3213/14 drivers incorporate MillerDrive™ at  Typical Propagation Delay Under 20 ns Matched architecture for the final output stage. This bipolar- e D within 1 ns to the Other Channel MOSFET combination provides high current during the r  Double Current Capability by Paralleling Channels Miller plateau stage of the MOSFET turn-on / turn-off iv process to minimize switching loss, while providing rail- e  Standard SOIC-8 Package to-rail voltage swing and reverse current capability. rs  Rated from –40°C to +125°C Ambient The FAN3213 offers two inverting drivers and the  Automotive Qualified to AEC-Q100 (F085 Version) FAN3214 offers two non-inverting drivers. Both are offered in a standard 8-pin SOIC package. Applications Related Resources  Switch-Mode Power Supplies AN-6069 — Application Review and Comparative  High-Efficiency MOSFET Switching Evaluation of Low-Side Gate Drivers  Synchronous Rectifier Circuits  DC-to-DC Converters  Motor Control  Automotive-Qualified Systems (F085 version) NC 1 8 NC NC 1 8 NC INA 2 A 7 OUTA INA 2 A 7 OUTA GND 3 6 VDD GND 3 6 VDD INB 4 B 5 OUTB INB 4 B 5 OUTB FAN3213 FAN3214 Figure 1. Pin Configurations © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9

F A N Ordering Information 3 2 1 3 Input Packing Quantity / Part Number Logic Package F Threshold Method per Reel A N FAN3213TMX Dual Inverting Channels 3 2 FAN3214TMX Dual Non-Inverting Channels 1 4 TTL SOIC-8 Tape & Reel 2,500 FAN3213TMX_F085(1) Dual Inverting Channels — D FAN3214TMX_F085(1) Dual Non-Inverting Channels u a Note: l- 4 1. Qualified to AEC-Q100 A , H i g h - Package Outlines S p e e 1 8 d , L o 2 7 w - S 3 6 id e G 4 5 a t e Figure 2. SOIC-8 (Top View) D r i v e r Thermal Characteristics(2) s Package  (3)  (4)  (5)  (6)  (7) Unit JL JT JA JB JT 8-Pin Small Outline Integrated Circuit (SOIC) 38 29 87 41 2.3 °C/W Notes: 2. Estimates derived from thermal simulation; actual values depend on the application. 3. Theta_JL ( ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads JL (including any thermal pad) that are typically soldered to a PCB. 4. Theta_JT ( ): Thermal resistance between the semiconductor junction and the top surface of the package, JT assuming it is held at a uniform temperature by a top-side heatsink. 5. Theta_JA (Θ ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, JA and airflow. The value given is for natural convection with no heatsink, using a 2S2P board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. 6. Psi_JB ( ): Thermal characterization parameter providing correlation between semiconductor junction JB temperature and an application circuit board reference point for the thermal environment defined in Note 5. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. 7. Psi_JT ( ): Thermal characterization parameter providing correlation between the semiconductor junction JT temperature and the center of the top of the package for the thermal environment defined in Note 5. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 2

F A N Pin Configurations 3 2 1 3 / F A NC 1 8 NC NC 1 8 NC N INA 2 A 7 OUTA INA 2 A 7 OUTA 3 2 1 GND 3 6 VDD GND 3 6 VDD 4 — INB 4 B 5 OUTB INB 4 B 5 OUTB D u FAN3213 FAN3214 a l - Figure 3. Pin Configurations (Repeated) 4 A , Pin Definitions H i g Pin Name Pin Description h - S 1 NC No Connect. This pin can be grounded or left floating. p e e 2 INA Input to Channel A. d , 3 GND Ground. Common ground reference for input and output circuits. L o 4 INB Input to Channel B. w - S 5 Gate Drive Output B (inverted from the input): Held LOW unless required input is i (FAN3213) OUTB present and VDD is above UVLO threshold. de G 5 Gate Drive Output B: Held LOW unless required input(s) are present and V is above OUTB DD a (FAN3214) UVLO threshold. t e 6 VDD Supply Voltage. Provides power to the IC. D r i 7 Gate Drive Output A (inverted from the input): Held LOW unless required input is v (FAN3213) OUTA present and VDD is above UVLO threshold. ers 7 Gate Drive Output A: Held LOW unless required input(s) are present and V is above OUTA DD (FAN3214) UVLO threshold. 8 NC No Connect. This pin can be grounded or left floating. Output Logic FAN3213 (x=A or B) FAN3214 (x=A or B) INx OUTx INx OUTx 0 1 0(9) 0 1(9) 0 1 1 Note: 9. Default input signal if no external connection is made. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 3

F A N Block Diagrams 3 2 1 3 / F NC 1 8 NC A N 3 2 1 4 — INA 2 D 7 u OUTA a 100k 100k l- 4 A , UVLO 6 VDD H GND 3 i g h VDD_OK -S p e e d INB 4 5 , L OUTB o 100k 100k w - S i d e G a Figure 4. FAN3213 Block Diagram t e D r i v e r s NC 1 8 NC INA 2 7 OUTA 100k 100k UVLO 6 VDD GND 3 VDD_OK INB 4 5 OUTB 100k 100k Figure 5. FAN3214 Block Diagram © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 4

F A N Absolute Maximum Ratings 3 2 1 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be 3 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. / F In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. A The absolute maximum ratings are stress ratings only. N 3 2 Symbol Parameter Min. Max. Unit 1 4 VDD VDD to PGND -0.3 20.0 V — V INA and INB to GND GND - 0.3 V + 0.3 V D IN DD u V OUTA and OUTB to GND GND - 0.3 V + 0.3 V a OUT DD l - 4 TL Lead Soldering Temperature (10 Seconds) +260 ºC A , TJ Junction Temperature -55 +150 ºC H i g T Storage Temperature -65 +150 ºC STG h - S p e e d Recommended Operating Conditions , L o The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended w operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not - S recommend exceeding them or designing to Absolute Maximum Ratings. i d e Symbol Parameter Min. Max. Unit G a V Supply Voltage Range 4.5 18.0 V t DD e V Input Voltage INA and INB 0 V V D IN DD r i T Operating Ambient Temperature -40 +125 ºC v A e r s © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 5

F A N Electrical Characteristics 3 2 Unless otherwise noted, V =12 V, T =-40°C to +125°C. Currents are defined as positive into the device and 1 DD J 3 negative out of the device. / F Symbol Parameter Conditions Min. Typ. Max. Unit A N Supply 3 2 1 FAN321xT 4 — V Operating Range 4.5 18.0 V DD D IDD Supply Current, Inputs Not Connected 0.70 0.95 mA u a V Turn-On Voltage INA=V , INB=0 V 3.5 3.9 4.3 V l ON DD - 4 V Turn-Off Voltage INA=V , INB=0 V 3.3 3.7 4.1 V A OFF DD , H FAN321xTMX_F085 (Automotive-Qualified Versions) i g I Supply Current, Inputs Not Connected(12) 0.70 1.20 mA h DD - S VON Turn-On Voltage(12) INA=VDD, INB=0 V 3.3 3.9 4.5 V p e V Turn-Off Voltage(12) INA=V , INB=0 V 3.1 3.7 4.3 V e OFF DD d , Inputs L o V INx Logic Low Threshold 0.8 1.2 V w IL_T - S V INx Logic High Threshold 1.6 2.0 V IH_T i d FAN321xT e G I Non-Inverting Input IN from 0 to V -1.5 175.0 µA a IN+ DD t e IIN- Inverting Input IN from 0 to VDD -175.0 1.5 µA D r V TTL Logic Hysteresis Voltage 0.2 0.4 0.8 V i HYS_T v e FAN321xTMX_F085 (Automotive-Qualified Versions) r s I Non-inverting Input Current(12) IN=0 V -1.5 1.5 µA INx_T I Non-inverting Input Current(12) IN=V 90 120 175 µA INx_T DD I Inverting Input Current(12) IN=0 V -175 -120 -90 µA INx_T I Inverting Input Current(12) IN=V -1.5 1.5 µA INx_T DD V TTL Logic Hysteresis Voltage(12) 0.1 0.4 0.8 V HYS_T Output OUTx at V /2, I OUT Current, Mid-Voltage, Sinking(10) DD 4.3 A SINK C =0.22 µF, f=1 kHz LOAD OUTx at V /2, I OUT Current, Mid-Voltage, Sourcing(10) DD -2.8 A SOURCE C =0.22 µF, f=1 kHz LOAD I OUT Current, Peak, Sinking(10) C =0.22 µF, f=1 kHz 5 A PK_SINK LOAD I OUT Current, Peak, Sourcing(10) C =0.22 µF, f=1 kHz -5 A PK_SOURCE LOAD I Output Reverse Current Withstand(10) 500 mA RVS INA=INB, OUTA and OUTB TDEL.MATCH Propagation Matching Between Channels at 50% Point 2 4 ns Continued on the following page… © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 6

F A N Electrical Characteristics (Continued) 3 2 Unless otherwise noted, V =12 V, T =-40°C to +125°C. Currents are defined as positive into the device and 1 DD J 3 negative out of the device. / F Symbol Parameter Conditions Min. Typ. Max. Unit A N FAN321xT 3 2 tRISE Output Rise Time(11) CLOAD=2200 pF 12 20 ns 14 t Output Fall Time(11) C =2200 pF 9 17 ns — FALL LOAD D tD1, tD2 Output Propagation Delay, TTL Inputs(11) 0 - 5 VIN, 1 V/ns Slew Rate 9 17 29 ns u a FAN321xTMX_F085 (Automotive-Qualified Versions) l - 4 t Output Rise Time(11)(12) C =2200 pF 12 22 ns A RISE LOAD , t Output Fall Time(11)(12) C =2200 pF 9 18 ns H FALL LOAD i g t , t Output Propagation Delay, TTL Inputs(11)(12) 0 – 5 V , 1 V/ns Slew Rate 9 17 32 ns h D1 D2 IN - S VOH High Level Output Voltage(12) VOH=VDD–VOUT, IOUT=–1 mA 15 35 mV pe e VOL Low Level Output Voltage(12) IOUT=1 mA 10 25 mV d , Notes: L o 10. Not tested in production. w 11. See Timing Diagrams of Figure 6 and Figure 7. - S 12. Apply only to Automotive Version(FAN321xTMX_F085) i d e G a t e 90% D 90% r i Output Output v e r 10% 10% s V INH V Input INH V Input INL V INL tD1 tD2 tD1 tD2 t t t t RISE FALL FALL RISE Figure 6. Non-Inverting Timing Diagram Figure 7. Inverting Timing Diagram © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 7

F A Typical Performance Characteristics N 3 Typical characteristics are provided at T =25°C and V =12 V unless otherwise noted. 2 A DD 1 3 / F A N 3 2 1 4 — D u a l - 4 A , H i g h -S p Figure 8. IDD (Static) vs. Supply Voltage(12) Figure 9. IDD (Static) vs. Temperature(12) ee d , L o w - S i d e G a t e D r i v e r s Figure 10. I (No Load) vs. Frequency Figure 11. I (2.2 nF Load) vs. Frequency DD DD Figure 12. Input Thresholds vs. Supply Voltage Figure 13. Input Thresholds vs. Temperature © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 8

F A Typical Performance Characteristics N 3 Typical characteristics are provided at T =25°C and V =12 V unless otherwise noted. 2 A DD 1 3 / F A N 3 2 1 4 — D u a l - 4 A , H i g h -S p UVLO Threshold vs. Temperature e e d , L o w - S i d e G a t e D r i v e r s Figure 14. Propagation Delay vs. Supply Voltage Figure 15. Propagation Delay vs. Supply Voltage Figure 16. Propagation Delays vs. Temperature Figure 17. Propagation Delays vs. Temperature © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 9

F A Typical Performance Characteristics N 3 Typical characteristics are provided at T =25°C and V =12 V unless otherwise noted. 2 A DD 1 3 / F A N 3 2 1 4 — D u a l - 4 A , H i g h -S p e Figure 18. Fall Time vs. Supply Voltage Figure 19. Rise Time vs. Supply Voltage e d , L o w - S i d e G a t e D r i v e r s Figure 20. Rise and Fall Times vs. Temperature Figure 21. Rise/Fall Waveforms with 2.2 nF Load Figure 22. Rise/Fall Waveforms with 10 nF Load © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 10

F A Typical Performance Characteristics N 3 Typical characteristics are provided at T =25°C and V =12 V unless otherwise noted. 2 A DD 1 3 / F A N 3 2 1 4 — D u a l - 4 A , H i g h - S Figure 23. Quasi-Static Source Current Figure 24. Quasi-Static Sink Current with V =12 V(13) p with VDD=12 V(13) DD e e d , L o w - S i d e G a t e D r i v e r s Figure 25. Quasi-Static Source Current Figure 26. Quasi-Static Sink Current with V =8 V(14) with V =8 V(14) DD DD Notes: 13. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high; static IDD increases by the current flowing through the corresponding pull-up/down resistor shown in Figure 4 and Figure 5. 14. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the current-measurement loop. Test Circuit V DD 4.7µF 470µF ceramic Al. El. Current Probe LECROY AP015 I OUT 1kINHz ce1raµmFic VOUT 0C.2L2OAµDF Figure 27. Quasi-Static I / V Test Circuit OUT OUT © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 11

F A Applications Information N 3 2 Input Thresholds VDD 1 3 The FAN3213 and the FAN3214 drivers consist of two / identical channels that may be used independently at F rated current or connected in parallel to double the A N individual current capacity. 3 2 The input thresholds meet industry-standard TTL-logic Input 1 thresholds independent of the VDD voltage, and there is stage VOUT 4 a hysteresis voltage of approximately 0.4 V. These — levels permit the inputs to be driven from a range of D input logic signal levels for which a voltage over 2 V is u considered logic HIGH. The driving signal for the TTL a l - inputs should have fast rising and falling edges with a 4 slew rate of 6 V/µs or faster, so a rise time from 0 to A , 3.3 V should be 550 ns or less. With reduced slew rate, Figure 28. MillerDrive™ Output Architecture H circuit noise could cause the driver input voltage to i g exceed the hysteresis voltage and retrigger the driver Under-Voltage Lockout h input, causing erratic operation. -S The FAN321x startup logic is optimized to drive ground- p Static Supply Current referenced N-channel MOSFETs with an under-voltage e lockout (UVLO) function to ensure that the IC starts up e In the I (static) typical performance characteristics d shown inD DFigure 8 and Figure 9, each curve is produced i3n. 9a Vn oordpeerrlayt ifoansahli olne.v Wel,h ethni sV DcDi ricsu riti sihnogl,d yse tt hbee loowu ttphuet , L with both inputs floating and both outputs LOW to o LOW, regardless of the status of the input pins. After the w indicate the lowest static I current. For other states, DD part is active, the supply voltage must drop 0.2 V before - additional current flows through the 100 k resistors on S the part shuts down. This hysteresis helps prevent i the inputs and outputs shown in the block diagram of d each part (see Figure 4 and Figure 5). In these cases, chatter when low VDD supply voltages have noise from e the power switching. This configuration is not suitable G the actual static I current is the value obtained from DD for driving high-side P-channel MOSFETs because the a the curves plus this additional current. low output voltage of the driver would turn the P-channel te MillerDrive™ Gate Drive Technology MOSFET on with VDD below 3.9 V. D r FAN3213 and FAN3214 gate drivers incorporate the V Bypass Capacitor Guidelines iv DD e MillerDrive™ architecture shown in Figure 28. For the To enable this IC to turn a device ON quickly, a local r output stage, a combination of bipolar and MOS devices s high-frequency bypass capacitor, C , with low ESR and provide large currents over a wide range of supply BYP ESL should be connected between the VDD and GND voltage and temperature variations. The bipolar devices pins with minimal trace length. This capacitor is in carry the bulk of the current as OUT swings between 1/3 addition to bulk electrolytic capacitance of 10 µF to 47 µF to 2/3 V and the MOS devices pull the output to the DD commonly found on driver and controller bias circuits. HIGH or LOW rail. A typical criterion for choosing the value of C is to The purpose of the MillerDrive™ architecture is to BYP keep the ripple voltage on the V supply to ≤ 5%. This speed up switching by providing high current during the DD is often achieved with a value ≥ 20 times the equivalent Miller plateau region when the gate-drain capacitance of load capacitance C , defined here as Q /V . the MOSFET is being charged or discharged as part of EQV GATE DD Ceramic capacitors of 0.1 µF to 1 µF or larger are the turn-on / turn-off process. common choices, as are dielectrics, such as X5R and For applications with zero voltage switching during the X7R, with good temperature characteristics and high MOSFET turn-on or turn-off interval, the driver supplies pulse current capability. high peak current for fast switching even though the If circuit noise affects normal operation, the value of Miller plateau is not present. This situation often occurs C may be increased, to 50-100 times the C , or in synchronous rectifier applications because the body BYP EQV C may be split into two capacitors. One should be a diode is generally conducting before the MOSFET is BYP larger value, based on equivalent load capacitance, and switched ON. the other a smaller value, such as 1-10 nF mounted The output pin slew rate is determined by V voltage closest to the VDD and GND pins to carry the higher- DD and the load on the output. It is not user adjustable, but frequency components of the current pulses. The a series resistor can be added if a slower rise or fall time bypass capacitor must provide the pulsed current from at the MOSFET gate is needed. both of the driver channels and, if the drivers are switching simultaneously, the combined peak current sourced from the C would be twice as large as when BYP a single channel is switching. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 12

F A Layout and Connection Guidelines N 3 The FAN3213 and FAN3214 gate drivers incorporate Figure 30 shows the current path when the gate driver 2 fast-reacting input circuits, short propagation delays, turns the MOSFET OFF. Ideally, the driver shunts the 1 3 and powerful output stages capable of delivering current current directly to the source of the MOSFET in a small / peaks over 4 A to facilitate voltage transition times from circuit loop. For fast turn-off times, the resistance and F under 10 ns to over 150 ns. The following layout and inductance in this path should be minimized. A connection guidelines are strongly recommended: N V V 3  Keep high-current output and power ground paths DD DS 21 separate from logic input signals and signal ground 4 — paths. This is especially critical for TTL-level logic C thresholds at driver input pins. BYP D  Keep the driver as close to the load as possible to FAN321x ua minimize the length of high-current traces. This l- 4 reduces the series inductance to improve high- A speed switching, while reducing the loop area that , can radiate EMI to the driver inputs and PWM H i surrounding circuitry. g h  If the inputs to a channel are not externally -S connected, the internal 100 k resistors indicated p Figure 30. Current Path for MOSFET Turn-Off e on block diagrams command a low output. In noisy e environments, it may be necessary to tie inputs of d , an unused channel to VDD or GND using short L traces to prevent noise from causing spurious o w output switching. - S  Many high-speed power circuits can be susceptible i d to noise injected from their own output or other e external sources, possibly causing output re- G triggering. These effects can be obvious if the a t circuit is tested in breadboard or non-optimal circuit e layouts with long input or output leads. For best D results, make connections to all pins as short and r i v direct as possible. e r  FAN3213 and FAN3214 are pin-compatible with s many other industry-standard drivers.  The turn-on and turn-off current paths should be minimized, as discussed in the following section. Figure 29 shows the pulsed gate drive current path when the gate driver is supplying gate charge to turn the MOSFET on. The current is supplied from the local bypass capacitor, C , and flows through the driver to BYP the MOSFET gate and to ground. To reach the high peak currents possible, the resistance and inductance in the path should be minimized. The localized C acts BYP to contain the high peak current pulses within this driver- MOSFET circuit, preventing them from disturbing the sensitive analog circuitry in the PWM controller. V V DD DS C BYP FAN321x PWM Figure 29. Current Path for MOSFET Turn-On © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 13

F A N Operational Waveforms 3 2 At power-up, the driver output remains LOW until the The inverting configuration of startup waveforms are 1 V voltage reaches the turn-on threshold. The shown in Figure 32. With IN+ tied to VDD and the input 3 DD magnitude of the OUT pulses rises with VDD until signal applied to IN–, the OUT pulses are inverted with / F steady-state VDD is reached. The non-inverting respect to the input. At power-up, the inverted output A operation illustrated in Figure 31 shows that the output remains LOW until the V voltage reaches the turn-on N DD remains LOW until the UVLO threshold is reached, then threshold, then it follows the input with inverted phase. 3 2 the output is in-phase with the input. 1 4 — VDD Turn-on threshold D VDD u Turn-on threshold a l - 4 A , IN- H IN- i g h - S p IN+ IN+ e (VDD) e d , L o w - S OUT OUT id e G a t e Figure 31. Non-Inverting Startup Waveforms Figure 32. Inverting Startup Waveforms D r i v e r s © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 14

F A N Thermal Guidelines 3 2 Gate drivers used to switch MOSFETs and IGBTs at To give a numerical example, assume for a 12 V VDD 1 high frequencies can dissipate significant amounts of (Vibas) system, the synchronous rectifier switches of 3 power. It is important to determine the driver power Figure 33 have a total gate charge of 60 nC at / F dissipation and the resulting junction temperature in the VGS = 7 V. Therefore, two devices in parallel would have A application to ensure that the part is operating within 120 nC gate charge. At a switching frequency of N acceptable temperature limits. 300 kHz, the total power dissipation is: 3 2 1 The total power dissipation in a gate driver is the sum of P = 120 nC • 7 V • 300 kHz • 2 = 0.504 W (5) 4 two components, PGATE and PDYNAMIC: GATE — P = 3.0 mA • 12 V • 1 = 0.036 W (6) DYNAMIC D P = P + P (1) TOTAL GATE DYNAMIC u PGATE (Gate Driving Loss): The most significant power PTOTAL = 0.540 W (7) al loss results from supplying gate current (charge per The SOIC-8 has a junction-to-board thermal -4 unit time) to switch the load MOSFET on and off at A the switching frequency. The power dissipation that cshysatreamct earipzpaltiicoant iopna, rathmee tleorc aolizf ed JBte m=p e4r2a°tuCr/eW .a roInu nda , H results from driving a MOSFET at a specified gate- i the device is a function of the layout and construction of g source voltage, VGS, with gate charge, QG, at the PCB along with airflow across the surfaces. To h switching frequency, fSW, is determined by: ensure reliable operation, the maximum junction -S p temperature of the device must be prevented from e PGATE = QG • VGS • fSW • n (2) exceeding the maximum rating of 150°C; with 80% e d where n is the number of driver channels in use (1 or 2). derating, TJ would be limited to 120°C. Rearranging , Equation 4 determines the board temperature required L P (Dynamic Pre-Drive / Shoot-through o DYNAMIC to maintain the junction temperature below 120°C: w Current): A power loss resulting from internal current - consumption under dynamic operating conditions, S including pin pull-up / pull-down resistors. The internal TB,MAX = TJ - PTOTAL • JB (8) id current consumption (I ) can be estimated using e DYNAMIC T = 120°C – 0.54 W • 42°C/W = 97°C (9) the graphs in Figure 10 of the Typical Performance B,MAX G Characteristics to determine the current IDYNAMIC at e drawn from V under actual operating conditions: DD D r PDYNAMIC = IDYNAMIC • VDD • n (3) iv e where n is the number of driver ICs in use. Note that n is r s usually be one IC even if the IC has two channels, unless two or more.driver ICs are in parallel to drive a large load. Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming  was determined for a similar thermal JB design (heat sinking and air flow): T = P •  + T (4) J TOTAL JB B where: T = driver junction temperature; J  = (psi) thermal characterization parameter JB relating temperature rise to total power dissipation; and T = board temperature in location as defined in B the Thermal Characteristics table. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 15

F A N Typical Application Diagrams 3 2 1 3 / F VIN A VOUT N 3 2 1 4 — PWM D u 1 8 a FAN3214 l 2 7 -4 Timing/ 3 6 Vbias 1 8 A , Isolation 4 5 2 A 7 H FAN3214 3 GND VDD 6 ig 4 B 5 h - S p Figure 33. High-Current Forward Converter Figure 34. Center-Tapped Bridge Output with e e with Synchronous Rectification Synchronous Rectifiers d , L o w - S i d VIN QC QA e G a t e D r i v QD QB e r s FAN3214 PWM-A FAN3225C SR-1 Secondary PWM-B Phase Shift SR-2 Controller PWM-C FAN3225C PWM-D Figure 35. Secondary Controlled Full Bridge with Current Doubler Output, Synchronous Rectifiers (Simplified) © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 16

F A Table 1. Related Products N 3 2 Part Gate Drive(15) Input 1 Type Logic Package 3 Number (Sink/Src) Threshold / F Single 1 A FAN3111C +1.1 A / -0.9 A CMOS Single Channel of Dual-Input/Single-Output SOT23-5, MLP6 A N Single 1 A FAN3111E +1.1 A / -0.9 A External(16) Single Non-Inverting Channel with External Reference SOT23-5, MLP6 3 2 1 Single 2 A FAN3100C +2.5 A / -1.8 A CMOS Single Channel of Two-Input/One-Output SOT23-5, MLP6 4 — Single 2 A FAN3100T +2.5 A / -1.8 A TTL Single Channel of Two-Input/One-Output SOT23-5, MLP6 D Single 2 A FAN3180 +2.4 A / -1.6 A TTL Single Non-Inverting Channel + 3.3 V LDO SOT23-5 u a l Dual 2 A FAN3216T +2.5 A / -1.8 A TTL Dual Inverting Channels SOIC8 -4 A Dual 2 A FAN3217T +2.5 A / -1.8 A TTL Dual Non-Inverting Channels SOIC8 , H i Dual 2 A FAN3226C +2.4 A / -1.6 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 g h - Dual 2 A FAN3226T +2.4 A / -1.6 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 S p Dual 2 A FAN3227C +2.4 A / -1.6 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 e e d Dual 2 A FAN3227T +2.4 A / -1.6 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 , L Dual 2 A FAN3228C +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8 o w - Dual 2 A FAN3228T +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8 S i d Dual 2 A FAN3229C +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8 e G Dual 2 A FAN3229T +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8 a t e 20 V Non-Inverting Channel (NMOS) and Inverting Dual 2 A FAN3268T +2.4 A / -1.6 A TTL SOIC8 D Channel (PMOS) + Dual Enables r i v 30 V Non-Inverting Channel (NMOS) and Inverting e Dual 2 A FAN3278T +2.4 A / -1.6 A TTL SOIC8 Channel (PMOS) + Dual Enables r s Dual 4 A FAN3213T +2.5 A / -1.8 A TTL Dual Inverting Channels SOIC8 Dual 4 A FAN3214T +2.5 A / -1.8 A TTL Dual Non-Inverting Channels SOIC8 Dual 4 A FAN3223C +4.3 A / -2.8 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 Dual 4 A FAN3223T +4.3 A / -2.8 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 Dual 4 A FAN3224C +4.3 A / -2.8 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 Dual 4 A FAN3224T +4.3 A / -2.8 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 Dual 4 A FAN3225C +4.3 A / -2.8 A CMOS Dual Channels of Two-Input/One-Output SOIC8, MLP8 Dual 4 A FAN3225T +4.3 A / -2.8 A TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8 Single 9 A FAN3121C +9.7 A / -7.1 A CMOS Single Inverting Channel + Enable SOIC8, MLP8 Single 9 A FAN3121T +9.7 A / -7.1 A TTL Single Inverting Channel + Enable SOIC8, MLP8 Single 9 A FAN3122C +9.7 A / -7.1 A CMOS Single Non-Inverting Channel + Enable SOIC8, MLP8 Single 9 A FAN3122T +9.7 A / -7.1 A TTL Single Non-Inverting Channel + Enable SOIC8, MLP8 Dual 12 A FAN3240 +12.0 A TTL Dual-Coil Relay Driver, Timing Config. 0 SOIC8 Dual 12 A FAN3241 +12.0 A TTL Dual-Coil Relay Driver, Timing Config. 1 SOIC8 Notes: 15. Typical currents with OUTx at 6 V and V =12 V. DD 16. Thresholds proportional to an externally supplied reference voltage. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3213 / FAN3214 • Rev. 1.9 17

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