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F A N 3 1 January 2015 2 1 / F A N 3 1 2 2 — FAN3121 / FAN3122 S i n Single 9-A High-Speed, Low-Side Gate Driver g l e 9 - A H Features Description i g h  Industry-Standard Pin-out with Enable Input The FAN3121 and FAN3122 MOSFET drivers are -S  4.5-V to 18-V Operating Range designed to drive N-channel enhancement MOSFETs in p low-side switching applications by providing high peak e  11.4 A Peak Sink at VDD = 12 V current pulses. The drivers are available with either TTL ed  9.7-A Sink / 7.1-A Source at VOUT = 6 V iinnppuutt tthhrreesshhoollddss ((FFAANN331122xxTC)) .o Irn tVeDrDn-apl rocpirocrutiiotrny apl rCovMidOeSs , L o  Inverting Configuration (FAN3121) and an under-voltage lockout function by holding the output w Non-Inverting Configuration (FAN3122) low until the supply voltage is within the operating range. - S  Internal Resistors Turn Driver Off If No Inputs FAN312x drivers incorporate the MillerDrive™ id e  23-ns / 19-ns Typical Rise/Fall Times (10 nF Load) architecture for the final output stage. This bipolar / G MOSFET combination provides the highest peak current  18 ns to 23 ns Typical Propagation Delay Time a during the Miller plateau stage of the MOSFET turn-on / t e  Choice of TTL or CMOS Input Thresholds turn-off process. D  MillerDrive™ Technology The FAN3121 and FAN3122 drivers implement an ri v  Available in Thermally Enhanced 3x3 mm 8-Lead enable function on pin 3 (EN), previously unused in the e MLP or 8-Lead SOIC Package (Pb-Free Finish) industry-standard pin-out. The pin is internally pulled up r to V for active HIGH logic and can be left open for  Rated from –40°C to +125°C standDaDrd operation.  Automotive Qualified to AEC-Q100 (F085 Versions) The commercial FAN3121/22 is available in a 3x3 mm 8-lead thermally-enhanced MLP package or an 8-lead Applications SOIC package. The AEC-Q100 automotive-qualified versions are available in the 8-lead SOIC package.  Synchronous Rectifier Circuits  High-Efficiency MOSFET Switching  Switch-Mode Power Supplies  DC-to-DC Converters  Motor Control  Automotive-Qualified Systems (F085 Versions) VDD 1 8 VDD VDD 1 8 VDD IN 2 7 OUT IN 2 7 OUT EN 3 6 OUT EN 3 6 OUT GND 4 5 GND GND 4 5 GND Figure 1. FAN3121 Pin Configuration Figure 2. FAN3122 Pin Configuration © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11

F A Ordering Information N 3 1 2 Input Packing Quantity 1 Part Number Logic Package Threshold Method per Reel / F A FAN3121CMPX 3x3 mm MLP-8 Tape & Reel 3,000 N FAN3121CMX CMOS SOIC-8 Tape & Reel 2,500 3 1 FAN3121CMX_F085(1) Inverting SOIC-8 Tape & Reel 2,500 2 Channels + 2 FAN3121TMPX Enable 3x3 mm MLP-8 Tape & Reel 3,000 — FAN3121TMX TTL SOIC-8 Tape & Reel 2,500 S FAN3121TMX_F085 (1) SOIC-8 Tape & Reel 2,500 in g FAN3122CMPX 3x3 mm MLP-8 Tape & Reel 3,000 l e FAN3122CMX CMOS SOIC-8 Tape & Reel 2,500 9 - FAN3122CMX_F085(1) Non-Inverting SOIC-8 Tape & Reel 2,500 A Channels + H FAN3122TMPX Enable 3x3 mm MLP-8 Tape & Reel 3,000 ig FAN3122TMX TTL SOIC-8 Tape & Reel 2,500 h - FAN3122TMX_F085(1) SOIC-8 Tape & Reel 2,500 S p e For additional information on Fairchild’s Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html e d , L Note: o 1. Qualified to AEC-Q100. w - S Package Outlines i d e G a t e D r i v e r Figure 3. 3x3 mm MLP-8 (Top View) Figure 4. SOIC-8 (Top View) Thermal Characteristics(2) Package Θ (3) Θ (4) Θ (5) Ψ (6) Ψ (7) Units JL JT JA JB JT 8-Lead 3x3 mm Molded Leadless Package (MLP) 1.2 64 42 2.8 0.7 °C/W 8-Pin Small Outline Integrated Circuit (SOIC) 38 29 87 41 2.3 °C/W Notes: 2. Estimates derived from thermal simulation; actual values depend on the application. 3. Theta_JL (Θ ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads JL (including any thermal pad) that are typically soldered to a PCB. 4. Theta_JT (Θ ): Thermal resistance between the semiconductor junction and the top surface of the package, JT assuming it is held at a uniform temperature by a top-side heatsink. 5. Theta_JA (Θ ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, JA and airflow. The value given is for natural convection with no heatsink, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. 6. Psi_JB (Ψ ): Thermal characterization parameter providing correlation between semiconductor junction JB temperature and an application circuit board reference point for the thermal environment defined in Note 5. For the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. 7. Psi_JT (Ψ ): Thermal characterization parameter providing correlation between the semiconductor junction JT temperature and the center of the top of the package for the thermal environment defined in Note 5. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 2

F A N Pin Definitions 3 1 2 1 FAN3121 FAN3122 Name Description / F 3 3 EN Enable Input. Pull pin LOW to inhibit driver. EN has logic thresholds for both A TTL and CMOS IN thresholds. N 3 4, 5 4, 5 GND Ground. Common ground reference for input and output circuits. 1 2 2 2 IN Input. 2 — Gate Drive Output. Held LOW unless required input is present and V is 6, 7 OUT DD above the UVLO threshold. S i n 6, 7 OUT Gate Drive Output (inverted from the input). Held LOW unless required g input is present and V is above the UVLO threshold. l DD e 1, 8 1, 8 V Supply Voltage. Provides power to the IC. 9 DD - A P1 Thermal Pad (MLP only). Exposed metal on the bottom of the package; H may be left floating or connected to GND; NOT suitable for carrying current. i g h - S VDD 1 8 VDD VDD 1 8 VDD p e e IN 2 7 OUT IN 2 7 OUT d , EN 3 6 OUT EN 3 6 OUT L o w GND 4 5 GND GND 4 5 GND -S i Figure 5. FAN3121 Pin Assignments (Repeated) Figure 6. FAN3122 Pin Assignments (Repeated) d e G a t e D r Output Logic iv e r FAN3121 FAN3122 EN IN OUT EN IN OUT 0 0 0 0 0(8) 0 0 1(8) 0 0 1 0 1(8) 0 1 1(8) 0(8) 0 1(8) 1(8) 0 1(8) 1 1 Note: 8. Default input signal if no external connection is made. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 3

F Block Diagram A N 3 1 2 1 V 1 8 V / DD DD F A Inverting N 100k 3 (FAN3121) UVLO 1 2 2 — V DD_OK S OUT (FAN3121) IN 2 in 7 OUT (FAN3122) g l e 9 100k - A 6 OUT (FAN3121) Non-Inverting H 100k (FAN3122) OUT (FAN3122) ig h - V S DD p e 100k e d EN 3 , L 5 GND o w GND 4 - S i d e G Figure 7. Block Diagram a t e D r i v e r © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 4

F A N Absolute Maximum Ratings 3 1 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be 2 1 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. / In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. F A The absolute maximum ratings are stress ratings only. N 3 Symbol Parameter Min. Max. Unit 1 2 2 VDD VDD to GND -0.3 20.0 V — VEN EN to GND GND - 0.3 VDD + 0.3 V S i V IN to GND GND - 0.3 V + 0.3 V n IN DD g l V OUT to GND GND - 0.3 V + 0.3 V e OUT DD 9 T Lead Soldering Temperature (10 Seconds) +260 °C - L A T Junction Temperature -55 +150 °C H J i g TSTG Storage Temperature -65 +150 °C h - S p e e d , Recommended Operating Conditions L o w The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended - S operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not i d recommend exceeding them or designing to Absolute Maximum Ratings. e G Symbol Parameter Min. Max. Unit a t e VDD Supply Voltage Range 4.5 18.0 V D VEN Enable Voltage EN 0 VDD V riv e VIN Input Voltage IN 0 VDD V r T Operating Ambient Temperature -40 +125 ºC A © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 5

F A N Electrical Characteristics 3 1 Unless otherwise noted, V =12 V and T =-40°C to +125°C. Currents are defined as positive into the device and 2 DD J 1 negative out of the device. / F Symbol Parameter Conditions Min. Typ. Max. Unit A N Supply 3 1 2 VDD Operating Range 4.5 18.0 V 2 TTL 0.65 0.90 — IDD Supply Current, Inputs / EN Not Connected CMOS(9) 0.58 0.85 mA S i n VON Device Turn-On Voltage (UVLO) 3.5 4.0 4.3 V g l V Device Turn-Off Voltage (UVLO) 3.30 3.75 4.10 V e OFF 9 FAN3121_F085, FAN3122_F085 (Automotive-Qualified Versions) - A VDD Operating Range 4.5 18.0 V H i TTL 0.65 1.00 g I Supply Current, Inputs / EN Not Connected mA h DD CMOS(9) 0.58 0.85 -S p VON Device Turn-On Voltage (UVLO) 3.5 4.0 4.3 V e e VOFF Device Turn-Off Voltage (UVLO)(13) 3.25 3.75 4.15 V d , Inputs (TTL, FAN312xT)(10) L o V INx Logic Low Threshold 0.8 1.0 V w IL_T - V INx Logic High Threshold 1.7 2.0 V S IH_T i d VHYS_T TTL Logic Hysteresis Voltage 0.40 0.70 0.85 V e FAN3121TMX, FAN3122TMX G a IIN+ Non-Inverting Input Current IN from 0 to VDD -1 175 µA te I Inverting Input Current IN from 0 to V -175 1 µA D IN- DD r i FAN3121TMX_F085, FAN3122TMX_F085 (Automotive-Qualified Versions) v e I Non-inverting Input Current(13) IN=0 V -1.5 1.5 µA r INx_T I Non-inverting Input Current(13) IN=V 90 120 175 µA INx_T DD I Inverting Input Current(13) IN=0 V -175 -120 -90 µA INx_T I Inverting Input Current(13) IN=V -1.5 1.5 µA INx_T DD Inputs (CMOS, FAN312xC)(10) V INx Logic Low Threshold 30 38 %V IL_C DD V INx Logic High Threshold 55 70 %V IH_C DD V CMOS Logic Hysteresis Voltage 12 17 24 %V HYS_C DD FAN3121CMX, FAN3122CMX I Non-Inverting Input Current IN from 0 to V -1 175 µA IN+ DD I Inverting Input Current IN from 0 to V -175 1 µA IN- DD FAN3121CMX_F085, FAN3122CMX_F085 (Automotive-Qualified Versions) I Non-Inverting Input Current(13) IN=0 V -1.5 1.5 µA INx_C I Non-Inverting Input Current(13) IN=V 90 120 175 µA INx_C DD I Inverting Input Current(13) IN=0 V -175 -120 -90 µA INx_C I Inverting Input Current(13) IN=V -1.5 1.5 µA INx_C DD Continued on the following page… © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 6

F A Electrical Characteristics (Continued) N Unless otherwise noted, V =12 V and T =-40°C to +125°C. Currents are defined as positive into the device and 3 DD J 1 negative out of the device. 2 1 Symbol Parameter Conditions Min. Typ. Max. Unit / F A ENABLE (FAN3121, FAN3122) N 3 V Enable Logic Low Threshold EN from 5 V to 0 V 1.2 1.6 2.0 V ENL 1 2 VENH Enable Logic High Threshold EN from 0 V to 5 V 1.8 2.2 2.6 V 2 V TTL Logic Hysteresis Voltage 0.2 0.6 0.8 V — HYS_T R Enable Pull-up Resistance 68 100 134 kΩ S PU i n tD1, tD2 Propagation Delay, CMOS EN(11) 8 17 27 ns g l t , t Propagation Delay, TTL EN(11) 14 21 33 ns e D1 D2 9 ENABLE (FAN3121_F085, FAN3122_F085) (Automotive-Qualified Versions) - A V Enable Logic Low Threshold EN from 5 V to 0 V 1.2 1.6 2.0 V H ENL i V Enable Logic High Threshold EN from 0 V to 5 V 1.8 2.2 2.6 V g ENH h VHYS_T TTL Logic Hysteresis Voltage 0.20 0.60 0.85 V -S p RPU Enable Pull-up Resistance 68 100 134 kΩ e e t , t Propagation Delay, CMOS EN (11) 6 17 35 ns d D1 D2 , t , t Propagation Delay, TTL EN(11) 8 22 34 ns L D1 D2 o Outputs w - OUT at V /2, S I OUT Current, Mid-Voltage, Sinking(12) DD 9.7 A i SINK C =1.0 µF, f=1 kHz d LOAD e I OUT Current, Mid-Voltage, Sourcing(12) OUT at VDD/2, 7.1 A G SOURCE C =1.0 µF, f=1 kHz a LOAD t IPK_SINK OUT Current, Peak, Sinking(12) CLOAD=1.0 µF, f=1 kHz 11.4 A e D I OUT Current, Peak, Sourcing(12) C =1.0 µF, f=1 kHz 10.6 A r PK_SOURCE LOAD i v t Output Rise Time(11) C =10 nF 18 23 29 ns e RISE LOAD r t Output Fall Time(11) C =10 nF 11 19 27 ns FALL LOAD t t Output Propagation Delay, CMOS Inputs(11) 0 – 12 V , 1 V/ns Slew Rate 9 18 28 ns D1, D2 IN t t Output Propagation Delay, TTL Inputs(11) 0 – 5 V , 1 V/ns Slew Rate 9 23 35 ns D1, D2 IN I Output Reverse Current Withstand(12) 1500 mA RVS FAN3121_F085, FAN3122_F085 (Automotive-Qualified Versions) t Output Rise Time(11) CMOS Inputs C =10 nF 12 23 31 ns RISE LOAD t Output Fall Time(11) CMOS Inputs C =10 nF 12 19 27 ns FALL LOAD t Output Rise Time(11) TTL Inputs C =10 nF 18 23 36 ns RISE LOAD t Output Fall Time(11) TTL Inputs C =10 nF 10 19 28 ns FALL LOAD t t Output Propagation Delay, CMOS Inputs(13) 0 – 12 V , 1 V/ns Slew Rate 6 18 35 ns D1, D2 IN t t Output Propagation Delay, TTL Inputs(11) 0 – 5 V , 1 V/ns Slew Rate 9 23 36 ns D1, D2 IN VOH High Level Output Voltage(13) VOH=VDD–VOUT, IOUT=–1 mA 15 35 mV VOL Low Level Output Voltage(13) IOUT=1 mA 10 25 mV Notes: 9. Lower supply current due to inactive TTL circuitry. 10. EN inputs have modified TTL thresholds; refer to the ENABLE section. 11. See Timing Diagrams of Figure 8 and Figure 9. 12. Not tested in production. 13. Automotive-qualified F085 version specifications. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 7

F A N Timing Diagrams 3 1 2 1 / F A N 3 1 2 2 — S i n g l e 9 - A H i g h - S p e e d , L o w Figure 8. Non-Inverting Figure 9. Inverting - S i d e G a t e D r i v e r © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 8

F A Typical Performance Characteristics N 3 1 Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted. 2 1 / F A N 3 1 2 2 — S i n g l e 9 - A H i g h - S p Figure 10. I (Static) vs. Supply Voltage(14) Figure 11. I (Static) vs. Supply Voltage(14) e DD DD e d , L o w - S i d e G a t e D r i v e r Figure 12. I (No-Load) vs. Frequency Figure 13. I (No-Load) vs. Frequency DD DD Figure 14. I (10 nF Load) vs. Frequency Figure 15. I (10 nF Load) vs. Frequency DD DD © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 9

F A Typical Performance Characteristics N 3 Typical characteristics are provided at 25°C and V =12 V unless otherwise noted. 1 DD 2 1 / F A N 3 1 2 2 — S i n g l e 9 - A H i g h - S p Figure 16. I (Static) vs. Temperature(14) Figure 17. I (Static) vs. Temperature(14) e DD DD e d , L o w - S i d e G a t e D r i v e r Figure 18. Input Thresholds vs. Supply Voltage Figure 19. Input Thresholds vs. Supply Voltage Figure 20. Input Thresholds % vs. Supply Voltage Figure 21. Enable Thresholds vs. Supply Voltage © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 10

F A Typical Performance Characteristics N 3 Typical characteristics are provided at 25°C and V =12 V unless otherwise noted. 1 DD 2 1 / F A N 3 1 2 2 — S i n g l e 9 - A H i g h - S p Figure 22. CMOS Input Thresholds vs. Temperature Figure 23. TTL Input Thresholds vs. Temperature e e d , L o w - S i d e G a t e D r i v e r Figure 24. Enable Thresholds vs. Temperature Figure 25. UVLO Thresholds vs. Temperature Figure 26. UVLO Hysteresis vs. Temperature Figure 27. Propagation Delay vs. Supply Voltage © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 11

F A Typical Performance Characteristics N 3 Typical characteristics are provided at 25°C and V =12 V unless otherwise noted. 1 DD 2 1 / F A N 3 1 2 2 — S i n g l e 9 - A H i g h - S p Figure 28. Propagation Delay vs. Supply Voltage Figure 29. Propagation Delay vs. Supply Voltage e e d , L o w - S i d e G a t e D r i v e r Figure 30. Propagation Delay vs. Supply Voltage Figure 31. Propagation Delay vs. Supply Voltage Figure 32. Propagation Delays vs. Temperature Figure 33. Propagation Delays vs. Temperature © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 12

F A Typical Performance Characteristics N 3 Typical characteristics are provided at 25°C and V =12 V unless otherwise noted. 1 DD 2 1 / F A N 3 1 2 2 — S i n g l e 9 - A H i g h - S p Figure 34. Propagation Delays vs. Temperature Figure 35. Propagation Delays vs. Temperature e e d , L o w - S i d e G a t e D r i v e r Figure 36. Propagation Delays vs. Temperature Figure 37. Fall Time vs. Supply Voltage Figure 38. Rise Time vs. Supply Voltage Figure 39. Rise and Fall Time vs. Temperature © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 13

F A Typical Performance Characteristics N 3 Typical characteristics are provided at 25°C and V =12 V unless otherwise noted. 1 DD 2 1 / F A N 3 1 2 2 — S i n g l e 9 - A H i g h Figure 40. Rise / Fall Waveforms with 10 nF Load Figure 41. Quasi-Static Source Current with V =12V(15) - DD S p e e d , L o w - S i d e G a t e D r i v e r Figure 43. Quasi-Static Source Current with Figure 42. Quasi-Static Sink Current with V =12 V(15) DD V =8 V(15) DD V DD (2)x4.7µF 470µF ceramic Al.El. CurrentProbe FAN3121/22 LECROYAP015 I OUT IN 1µF V C 1kHz ceramic OUT 1LµOFAD Figure 44. Quasi-Static Sink Current with V =8 V(15) Figure 45. Quasi-Static I / V Test Circuit DD OUT OUT Notes: 14. For any inverting inputs pulled LOW, non-inverting inputs pulled HIGH, or outputs driven HIGH; static I DD increases by the current flowing through the corresponding pull-up/down resistor, shown in Figure 7. 15. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the current-measurement loop. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 14

F A Applications Information N 3 1 The FAN3121 and FAN3122 family offers versions in For applications with zero voltage switching during the 2 either TTL or CMOS input configuration. In the MOSFET turn-on or turn-off interval, the driver supplies 1 FAN3121T and FAN3122T, the input thresholds meet high peak current for fast switching, even though the / F industry-standard TTL-logic thresholds independent of Miller plateau is not present. This situation often occurs A the VDD voltage, and there is a hysteresis voltage of in synchronous rectifier applications because the body N approximately 0.7 V. These levels permit the inputs to diode is generally conducting before the MOSFET is 3 1 be driven from a range of input logic signal levels for switched on. 2 which a voltage over 2 V is considered logic HIGH. The 2 driving signal for the TTL inputs should have fast rising The output pin slew rate is determined by VDD voltage — and the load on the output. It is not user adjustable, but and falling edges with a slew rate of 6 V/µs or faster, so a series resistor can be added if a slower rise or fall time S the rise time from 0 to 3.3 V should be 550 ns or less. i at the MOSFET gate is needed. n g The FAN3121 and FAN3122 output can be enabled or l e disabled using the EN pin with a very rapid response 9 time. If EN is not externally connected, an internal pull- - A up resistor enables the driver by default. The EN pin has logic thresholds for parts with either TTL or CMOS IN H i thresholds. g h - In the FAN3121C and FAN3122C, the logic input S thresholds are dependent on the V level and, with V p DD DD e of 12 V, the logic rising edge threshold is approximately e 55% of V and the input falling edge threshold is d DD , approximately 38% of VDD. The CMOS input L configuration offers a hysteresis voltage of o w approximately 17% of V . The CMOS inputs can be DD - used with relatively slow edges (approaching DC) if S i good decoupling and bypass techniques are d incorporated in the system design to prevent noise from Figure 46. Miller Drive™ Output Architecture e G violating the input voltage hysteresis window. This a allows setting precise timing intervals by fitting an R-C Under-Voltage Lockout (UVLO) t e circuit between the controlling signal and the IN pin of The FAN312x startup logic is optimized to drive ground- D the driver. The slow rising edge at the IN pin of the driver introduces a delay between the controlling signal referenced N-channel MOSFETs with an under-voltage riv and the OUT pin of the driver. lockout (UVLO) function to ensure that the IC starts in e an orderly fashion. When V is rising, yet below the r DD 4.0 V operational level, this circuit holds the output low, Static Supply Current regardless of the status of the input pins. After the part In the I (static) Typical Performance Characteristics, is active, the supply voltage must drop 0.25 V before the DD the curves are produced with all inputs / enables floating part shuts down. This hysteresis helps prevent chatter (OUT is LOW) and indicates the lowest static IDD current when low VDD supply voltages have noise from the for the tested configuration. For other states, additional power switching. This configuration is not suitable for current flows through the 100 kΩ resistors on the inputs driving high-side P-channel MOSFETs because the low and outputs, as shown in the block diagram (see Figure output voltage of the driver would turn the P-channel 7). In these cases, the actual static IDD current is the MOSFET on with VDD below 4.0 V. value obtained from the curves, plus this additional current. V Bypassing and Layout Considerations DD The FAN3121 and FAN3122 are available in either MillerDrive™ Gate-Drive Technology 8-lead SOIC or MLP packages. In either package, the FAN312x gate drivers incorporate the MillerDrive™ VDD pins 1 and 8 and the GND pins 4 and 5 should be architecture shown in Figure 46. For the output stage, a connected together on the PCB. combination of bipolar and MOS devices provide large In typical FAN312x gate-driver applications, high-current currents over a wide range of supply voltage and pulses are needed to charge and discharge the gate of temperature variations. The bipolar devices carry the a power MOSFET in time intervals of 50 ns or less. A bulk of the current as OUT swings between 1/3 to 2/3 bypass capacitor with low ESR and ESL should be V and the MOS devices pull the output to the HIGH or DD connected directly between the V and GND pins to LOW rail. DD provide these large current pulses without causing The purpose of the Miller Drive™ architecture is to unacceptable ripple on the VDD supply. To meet these speed up switching by providing high current during the requirements in a small size, a ceramic capacitor of 1 µF Miller plateau region when the gate-drain capacitance of or larger is typically used, with a dielectric material such the MOSFET is being charged or discharged as part of as X7R, to limit the change in capacitance over the the turn-on / turn-off process. temperature and / or voltage application ranges. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 15

F Figure 47 shows the pulsed gate drive current path A N when the gate driver is supplying gate charge to turn the MOSFET on. The current is supplied from the local VDD Turn-on threshold 31 bypass capacitor C and flows through the driver to 2 BYP 1 the MOSFET gate and to ground. To reach the high / peak currents possible with the FAN312x family, the F resistance and inductance in the path should be A IN- N minimized. The localized C acts to contain the high BYP 3 peak current pulses within this driver-MOSFET circuit, 1 preventing them from disturbing the sensitive analog 2 2 circuitry in the PWM controller. — IN+ V V (V ) S DD DS DD i n g C l BYP e 9 - A FAN3121/2 OUT H i g PWM h - S Figure 50. Inverting Startup Waveforms p e At power up, the FAN3122 non-inverting driver, shown e Figure 47. Current Path for MOSFET Turn-On d in Figure 51, holds the output LOW until the V voltage DD , Figure 48 shows the path the current takes when the gate reaches the UVLO turn-on threshold, as indicated in L driver turns the MOSFET off. Ideally, the driver shunts the Figure 52. The OUT pulses magnitude follow V o DD w current directly to the source of the MOSFET in a small magnitude until steady-state V is reached. DD - circuit loop. For fast turn-off times, the resistance and S i inductance in this path should be minimized. d V DD e V V G DD DS a t IN OUT e C D BYP r FAN3121/2 iv e r Figure 51. Non-Inverting Driver PWM V DD Turn-on threshold Figure 48. Current Path for MOSFET Turn-Off Operational Waveforms At power up, the FAN3121 inverting driver shown in IN- Figure 49 holds the output LOW until the V voltage DD reaches the UVLO turn-on threshold, as indicated in Figure 50. This facilitates proper startup control of low- side N-channel MOSFETs. IN+ V DD IN OUT OUT Figure 49. Inverting Configuration The OUT pulses’ magnitude follows V magnitude with DD Figure 52. Non-Inverting Startup Waveforms the output polarity inverted from the input until steady- state V is reached. DD © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 16

F A Thermal Guidelines N 3 Gate drivers used to switch MOSFETs and IGBTs at TB = board temperature in location as defined in 1 high frequencies can dissipate significant amounts of the Thermal Characteristics table. 2 1 power. It is important to determine the driver power In a full-bridge synchronous rectifier application, shown / dissipation and the resulting junction temperature in the F application to ensure that the part is operating within in Figure 53, each FAN3122 drives a parallel A combination of two high-current MOSFETs, (such as N acceptable temperature limits. FDMS8660S). The typical gate charge for each SR 3 1 The total power dissipation in a gate driver is the sum of MOSFET is 70 nC with VGS = VDD = 9 V. At a switching 2 two components, P and P : frequency of 300 kHz, the total power dissipation is: 2 GATE DYNAMIC — PTOTAL = PGATE + PDYNAMIC (1) PGATE = 2 • 70 nC • 9V • 300 kHz = 0.378 W (5) S Gate Driving Loss: The most significant power loss PDYNAMIC = 2 mA • 9 V = 18 mW (6) in results from supplying gate current (charge per unit g time) to switch the load MOSFET on and off at the PTOTAL = 0.396 W (7) le switching frequency. The power dissipation that The SOIC-8 has a junction-to-board thermal 9 - results from driving a MOSFET at a specified gate- characterization parameter of ψ = 42°C/W. In a system A JB source voltage, V , with gate charge, Q , at H GS G application, the localized temperature around the device switching frequency, fSW, is determined by: is a function of the layout and construction of the PCB ig h P = Q • V • f (2) along with airflow across the surfaces. To ensure - GATE G GS SW S reliable operation, the maximum junction temperature of p Dynamic Pre-drive / Shoot-through Current: A the device must be prevented from exceeding the e power loss resulting from internal current maximum rating of 150°C; with 80% derating, T would e J d consumption under dynamic operating conditions, be limited to 120°C. Rearranging Equation 4 determines L including pin pull-up / pull-down resistors, can be the board temperature required to maintain the junction o obtained using the “IDD (No-Load) vs. Frequency” temperature below 120°C: w graphs in Typical Performance Characteristics to - S determine the current IDYNAMIC drawn from VDD TB,MAX = TJ - PTOTAL • ψJB (8) id under actual operating conditions: e TB,MAX = 120°C – 0.396 W • 42°C/W = 104°C (9) G P = I • V (3) DYNAMIC DYNAMIC DD For comparison, replace the SOIC-8 used in the a t Once the power dissipated in the driver is determined, previous example with the 3x3 mm MLP package with e the driver junction rise with respect to circuit board can ψ = 2.8°C/W. The 3x3 mm MLP package can operate D JB r be evaluated using the following thermal equation, at a PCB temperature of 118°C, while maintaining the i v assuming ψ was determined for a similar thermal junction temperature below 120°C. This illustrates that e JB r design (heat sinking and air flow): the physically smaller MLP package with thermal pad offers a more conductive path to remove the heat from TJ = PTOTAL • ψJB + TB (4) the driver. Consider tradeoffs between reducing overall circuit size with junction temperature reduction for where: increased reliability. T = driver junction temperature; J ψ = (psi) thermal characterization parameter relating JB temperature rise to total power dissipation; and © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 17

F A N Typical Application Diagrams 3 1 2 1 / F V A VIN B2 A2 OUT N 3 1 2 2 — B1 A1 S i n BIAS g l e FAN3122 FAN3122 9 FromA2 SREN -A VDD 1 8 VDD VDD 1 8 VDD H IN 2 7 OUT IN 2 7 OUT ig h FromA1 EN 3 6 OUT SRENEN 3 6 OUT -S 4 5 4 5 p AGND PGND AGND PGND ee d , L o Figure 53. Full-Bridge Synchronous Rectification w -S i d e G a VIN VOUT te D r i v e r PWM V FAN3121 BIAS 1 8 V V DD DD 2 P1 7 SR Enable IN (AGND) OUT 3 6 Active HIGH EN OUT 4 5 AGND PGND Figure 54. Hybrid Synchronous Rectification in a Forward Converter © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 18

F A N Table 1. Related Products 3 1 2 Part Gate Drive(16) Input 1 Type Logic Package(18) / Number (Sink/Src) Threshold F A SOT23-5, N FAN3111C Single 1 A +1.1 A / -0.9 A CMOS Single Channel of Dual-Input/Single-Output MLP6 3 1 Single Non-Inverting Channel with External SOT23-5, 2 FAN3111E Single 1 A +1.1 A / -0.9 A External(17) 2 Reference MLP6 — SOT23-5, FAN3100C Single 2 A +2.5 A / -1.8 A CMOS Single Channel of Two-Input/One-Output S MLP6 i n SOT23-5, g FAN3100T Single 2 A +2.5 A / -1.8 A TTL Single Channel of Two-Input/One-Output l MLP6 e 9 FAN3180 Single 2 A +2.4 A / -1.6 A TTL Single Non-Inverting Channel + 3.3 V LDO SOT23-5 - A FAN3216T Dual 2 A +2.4 A / -1.6 A TTL Dual Inverting Channels SOIC8 H i g FAN3217T Dual 2 A +2.4 A / -1.6 A TTL Dual Non-Inverting Channels SOIC8 h - FAN3226C Dual 2 A +2.4 A / -1.6 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 S p FAN3226T Dual 2 A +2.4 A / -1.6 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 e e FAN3227C Dual 2 A +2.4 A / -1.6 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 d , FAN3227T Dual 2 A +2.4 A / -1.6 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 L o FAN3228C Dual 2 A +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output SOIC8, MLP8 w - S FAN3228T Dual 2A +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8 i d FAN3229C Dual 2 A +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output SOIC8, MLP8 e G FAN3229T Dual 2 A +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8 a t 20 V Non-Inverting Channel (NMOS) and e FAN3268T Dual 2 A +2.4 A / -1.6 A TTL SOIC8 Inverting Channel (PMOS) + Dual Enables D r 30 V Non-Inverting Channel (NMOS) and iv FAN3278T Dual 2 A +2.4 A / -1.6 A TTL SOIC8 Inverting Channel (PMOS) + Dual Enables e r FAN3223C Dual 4 A +4.3 A / -2.8 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3213T Dual 4 A +4.3 A / -2.8 A TTL Dual Inverting Channels SOIC8 FAN3214T Dual 4 A +4.3 A / -2.8 A TTL Dual Non-Inverting Channels SOIC8 FAN3223T Dual 4 A +4.3 A / -2.8 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3224C Dual 4 A +4.3 A / -2.8 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 FAN3224T Dual 4 A +4.3 A / -2.8 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 FAN3225C Dual 4 A +4.3 A / -2.8 A CMOS Dual Channels of Two-Input/One-Output SOIC8, MLP8 FAN3225T Dual 4 A +4.3 A / -2.8 A TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8 FAN3121C Single 9 A +9.7 A / -7.1 A CMOS Single Inverting Channel + Enable SOIC8, MLP8 FAN3121T Single 9 A +9.7 A / -7.1 A TTL Single Inverting Channel + Enable SOIC8, MLP8 FAN3122C Single 9 A +9.7 A / -7.1 A CMOS Single Non-Inverting Channel + Enable SOIC8, MLP8 FAN3122T Single 9 A +9.7 A / -7.1 A TTL Single Non-Inverting Channel + Enable SOIC8, MLP8 FAN3240 Dual 12 A > +12.0 A TTL Dual-Coil Relay Driver, Timing Config. 0 SOIC8 FAN3241 Dual 12 A > +12.0 A TTL Dual-Coil Relay Driver, Timing Config. 1 SOIC8 Notes: 16. Typical currents with OUT at 6 V and V = 12 V. DD 17. Thresholds proportional to an externally supplied reference voltage. 18. Automotive-qualified F085 versions are only offered in SOIC8 packages. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.11 19

None

0.10 C 3.00 A 2.37 B 8 5 2X 1.99 3.00 1.42 3.30 PIN1IDENT (0.65) 0.10 C TOPVIEW 1 4 2X 0.65TYP 0.42TYP RECOMMENDEDLANDPATTERN 0.80MAX 0.10 C (0.20) 0.08 C 0.05 0.00 FRONTVIEW C NOTES: SEATING A.CONFORMSTOJEDECREGISTRATIONMO-229, PLANE VARIATIONVEEC,DATED112001. 0.45 2.25MAX B.DIMENSIONSAREINMILLIMETERS. 1 4 0.20 C.DIMENSIONSANDTOLERANCESPER PIN1IDENT ASMEY14.5M,2009. D.LANDPATTERNRECOMMENDATIONIS EXISTINGINDUSTRYLANDPATTERN. 1.30MAX E.DRAWINGFILENAME:MKT-MLP08Drev3 8 5 0.25 0.35 0.65 1.95 0.10 C A B 0.05 C BOTTOMVIEW

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