Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

F A N 3 1 January 2015 1 1 — S i n g FAN3111 — Single 1A High-Speed, Low-Side l e 1 Gate Driver A H i g Features Description h - S  1.4 A Peak Sink / Source at V = 12 V The FAN3111 1A gate driver is designed to drive an N- p DD e channel enhancement-mode MOSFET in low-side e  1.1 A Sink / 0.9 A Source at VOUT = 6 V switching applications. d ,  4.5 to 18 V Operating Range Two input options are offered: FAN3111C has dual L o  FAN3111C Compatible with FAN3100C Footprint CMOS inputs with thresholds referenced to VDD for use w with PWM controllers and other input-signal sources -  Two Input Configurations: that operate from the same supply voltage as the driver. Si d  Dual CMOS Inputs Allow Configuration as For use with low-voltage controllers and other input- e Non-Inverting or Inverting with Enable Function signal sources that operate from a lower supply voltage G than the driver, that supply voltage may also be used as a  Single Non-Inverting, Low-Voltage Input for the reference for the input thresholds of the FAN3111E. te Compatibility with Low-Voltage Controllers This driver has a single, non-inverting, low-voltage input D  Small Footprint Facilitates Distributed Drivers for plus a DC input VXREF for an external reference voltage ri in the range 2 to 5 V. v Parallel Power Devices e r  15 ns Typical Delay Times The FAN3111 is available in a lead-free finish industry- standard 5-pin SOT23.  9 ns Typical Rise / 8 ns Typical Fall times with 470 pF Load  5-Pin SOT23 Package  Rated from –40°C to 125°C Ambient Applications  Switch-Mode Power Supplies  Synchronous Rectifier Circuits  Pulse Transformer Driver  Logic to Power Buffer  Motor Control VDD 1 5 OUT VDD 1 5 OUT GND 2 GND 2 IN+ 3 4 IN− IN+ 3 4 XREF Figure 1. FAN3111C (Top View) Figure 2. FAN3111E (Top View) © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6

F A Ordering Information N 3 1 Input Quantity per 1 Part Number Package Packing Method 1 Threshold Reel — FAN3111CSX CMOS 5-Pin SOT23 Tape & Reel 3,000 S i n FAN3111ESX External 5-Pin SOT23 Tape & Reel 3,000 g l e 1 A Thermal Characteristics(1) H i g Package  (2)  (3)  (4)  (5)  (6) Units h JL JT JA JB JT - S 5-Pin SOT23 58 102 161 53 6 °C/W p e e d Notes: , 1. Estimates derived from thermal simulation; actual values depend on the application. L o 2. Theta_JL ( ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads JL w (including any thermal pad) that are typically soldered to a PCB. - S 3. Theta_JT ( ): Thermal resistance between the semiconductor junction and the top surface of the package, JT i assuming it is held at a uniform temperature by a top-side heatsink. d e 4. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, G and airflow. The value given is for natural convection with no heatsink using a 2S2P board,, as specified in a JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. t e 5. Psi_JB ( ): Thermal characterization parameter providing correlation between semiconductor junction JB D temperature and an application circuit board reference point for the thermal environment defined in Note 4. For r i the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and v e protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB r copper adjacent to pin 6. 6. Psi_JT ( ): Thermal characterization parameter providing correlation between the semiconductor junction JT temperature and the center of the top of the package for the thermal environment defined in Note 4. Pin Definitions Pin # Name Description 1 VDD Supply Voltage. Provides power to the IC. 2 GND Ground. Common ground reference for input and output circuits. 3 IN+ Non-Inverting Input. Connect to VDD to enable output. IN– FAN3111C Inverting Input. Connect to GND to enable output. 4 XREF FAN3111E External Reference Voltage. Reference for input thresholds, 2 V to 5 V. 5 OUT Gate Drive Output. Held low unless required inputs are present. Output Logic with Dual-Input Configuration IN+ IN− OUT 0(7) 0 0 0(7) 1(7) 0 1 0 1 1 1(7) 0 Note: 7. Default input signal if no external connection is made. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 2

F A Block Diagrams N 3 1 1 1 1 — VDD IN+ 3 S i n g l e 100kΩ 1 A H i g h 5 OUT - S p e 100kΩ e V d DD , L o w 100kΩ -S i d e IN- 4 2 GND G a t e D r i v e r Figure 3. FAN3111C Simplified Block Diagram 1 VDD XREF 4 IN+ 3 5 OUT 100k 100k 2 GND Figure 4. FAN3111E Simplified Block Diagram © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 3

F A Absolute Maximum Ratings N 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be 1 1 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 1 In addition, extended exposure to stresses above the recommended operating conditions may affect device — reliability. The absolute maximum ratings are stress ratings only. S i Symbol Parameter Min. Max. Unit n g l V VDD to GND -0.3 20.0 V e DD 1 FAN3111C -0.3 V + 0.3 V A DD VIN Voltage on IN to GND H FAN3111E -0.3 VXREF+0.3 V ig h V Voltage on XREF to GND FAN3111E -0.3 5.5 V XREF - S V Voltage on OUT to GND -0.3 V +0.3 V p OUT DD e e T Lead Soldering Temperature (10 Seconds) +260 ºC L d , TJ Junction Temperature +150 ºC L o T Storage Temperature -65 +150 ºC w STG - S i d e G a Recommended Operating Conditions te D The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended r i operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not v e recommend exceeding them or designing to Absolute Maximum Ratings. r Symbol Parameter Min. Max. Unit V Supply Voltage Range 4.5 18.0 V DD FAN3111C 0 V V DD V Input Voltage IN IN FAN3111E 0 V V XREF V External Reference Voltage XREF FAN3111E 2.0 5.0 V XREF T Operating Ambient Temperature -40 +125 ºC A © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 4

F A Electrical Characteristics N 3 Unless otherwise noted, V = 12 V, V = 3.3 V, T = -40°C to +125°C. Currents are defined as positive into the 1 DD XREF J 1 device and negative out of the device. 1 — Symbol Parameter Conditions Min. Typ. Max. Unit S Supply in g VDD Operating Range 4.5 18.0 V le 1 IDD Static Supply Current Inputs Not Connected 5 10 µA A H Inputs (FAN3111C) i g V IN Logic, Low-Voltage Threshold 30 38 %V h IL_C DD - S VIH_C IN Logic, High-Voltage Threshold 55 70 %VDD p e I IN Current, Low IN from 0 to V -1 175 µA e INL DD d , I IN Current, High IN from 0 to V -175 1 µA INH DD L o VHYS_C Input Hysteresis Voltage 17 %VDD w - Inputs (FAN3111E) S i d V IN Logic, Low-Voltage Threshold 25 30 %V e IL_E XREF G VIH_E IN Logic, High-Voltage Threshold 50 60 %VXREF a t e IINL IN Current, Low IN from 0 to VXREF -1 50 µA D IINH IN Current, High IN from 0 to VXREF -50 1 µA riv e VHYS_E Input Hysteresis Voltage 20 %VXREF r Output I OUT Current, Mid-Voltage, Sinking(8) OUT at VDD/2, 1.1 A SINK C = 47nF, f = 1KHz LOAD I OUT Current, Mid-Voltage, Sourcing(8) OUT at VDD/2, -0.9 A SOURCE C = 47nF, f = 1KHz LOAD I OUT Current, Peak, Sinking(8) C = 47nF, f = 1KHz 1.4 A PK_SINK LOAD I OUT Current, Peak, Sourcing(8) C = 47nF, f = 1KHz -1.4 A PK_SOURCE LOAD t Output Rise Time(9) C = 470pF 9 18 ns RISE LOAD t Output Fall Time(9) C = 470pF 8 17 ns FALL LOAD FAN3111C: 0 - 12V , IN 1V/ns Slew Rate t , t Output Prop. Delay(9) 15 30 ns D1 D2 FAN3111E: 0 - 3.3V , IN 1V/ns Slew Rate I Output Reverse Current Withstand(8) 250 mA RVS Notes: 8. Not tested in production. 9. See Timing diagrams. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 5

F A N 3 1 1 Timing Diagrams 1 — S i 90% n g Output 90% le Output 1 10% A 10% H i V g INH h IN+ V VINH -S INL IN - V p INL e t t e D1 D2 t t d D1 D2 , L tRISE tFALL tFALL tRISE ow - S Figure 5. Non-Inverting Waveforms Figure 6. Inverting Waveforms i d e G a t e D r i v e r © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 6

F A Typical Performance Characteristics N 3 Typical characteristics are provided at 25°C, V = 12 V, and V = 3.3 V unless otherwise noted. 1 DD XREF 1 1 2.5 — 2.5 FAN3111E S 2.0 FAN3111C 2.0 in g l I(μA)DD11..05 I(μA)DD 11..05 e 1A H InputsFloating,OutputLow i InputsFloating,OutputLow g 0.5 0.5 h - S 0.0 0.0 p e 4 6 8 10 12 14 16 18 4 6 8 10 12 14 16 18 e d SupplyVoltage(V) SupplyVoltage(V) , L o Figure 7. I (Static) vs. Supply Voltage Figure 8. I (Static) vs. Supply Voltage DD DD w - S i d e 22..00 1.8 G 1111....6868 FFAANN33111111CC VDD=15V 11..46 FAN3111E VDD=15V ate 11..44 VDD=12V 1.2 VDD=12V Dr I(mA)I(mA)DDDD011011......802802 VDD=VV4D.D5V=8V I(mA)DD001...680 VDD=V4D.D5=V8V iver 00..66 0.4 00..44 0.2 00..22 00..00 0.0 00 220000 440000 660000 880000 11000000 0 200 400 600 800 1000 SSwwiittcchhiinnggFFrreeqquueennccyy((kkHHzz)) SwitchingFrequency(kHz) Figure 9. I (No-Load) vs. Frequency Figure 10. I (No-Load) vs. Frequency DD DD 9 9 8 FAN3111C VDD=15V 8 FAN3111E VDD=15V 7 V =12V 7 DD V =12V 6 6 DD mA) 5 VDD=8V mA) 5 VDD=8V (D 4 VDD=4.5V (D 4 V =4.5V D D DD I 3 I 3 2 2 1 1 0 0 0 200 400 600 800 1000 0 200 400 600 800 1000 SwitchingFrequency(kHz) SwitchingFrequency(kHz) Figure 11. I (470pF Load) vs. Frequency Figure 12. I (470pF Load) vs. Frequency DD DD © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 7

F A Typical Performance Characteristics N 3 Typical characteristics are provided at 25°C, V = 12 V, and V = 3.3 V unless otherwise noted. 1 DD XREF 1 1 3 3 — FAN3111C FAN3111E S i n g 2 2 l e A) A) 1 (μ (μ A IDD InputsFloating,OutputLow IDD InputsFloating,OutputLow H 1 1 i g h - S p 0 0 e e -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 d Temperature(°C) Temperature(°C) , L o Figure 13. I (Static) vs. Temperature Figure 14. I (Static) vs. Temperature DD DD w - S i d e 10 2.5 G 9 FAN3111C FAN3111E a t e olds(V) 678 VIH olds(V) 2.0 VIH Driv h h e hres 45 hres 1.5 r T T nput 23 VIL nput 1.0 VIL I I 1 0 0.5 4 6 8 10 12 14 16 18 2.5 3.0 3.5 4.0 4.5 5.0 SupplyVoltage(V) XREF(V) Figure 15. Input Thresholds vs. Supply Voltage Figure 16. Input Threshold vs. XREF Voltage 100% 7.0 )DD 90% FAN3111C FAN3111C s(%ofV 678000%%% VIH olds(V) 66..05 VIH d h shol 4500%% hres 5.5 Thre 30% V utT 5.0 V put 1200%% IL Inp 4.5 IL n I 0% 4.0 4 6 8 10 12 14 16 18 -50 -25 0 25 50 75 100 125 SupplyVoltage(V) Temperature(°C) Figure 17. Input Thresholds % vs. Supply Voltage Figure 18. Input Threshold vs. Temperature © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 8

F A Typical Performance Characteristics N 3 Typical characteristics are provided at 25°C, V = 12 V, and V = 3.3 V unless otherwise noted. 1 DD XREF 1 1 2.0 70 — FAN3111E 1.8 s)60 FAN3111C Inverting Input S ds(V) 1.6 ays(n50 ingl eshol 1.4 VIH nDel40 INrise toOUTfall e 1A r o30 InputTh 11..02 VIL Propagati1200 INfall toOUT High-S p 0.8 0 e -50 -25 0 25 50 75 100 125 4 6 8 10 12 14 16 18 e d Temperature(°C) SupplyVoltage(V) , L Figure 19. Input Threshold vs. Temperature Figure 20. Propagation Delay vs. Supply Voltage o w - S i d 80 90 e 80 FAN3111E G (ns)6700 FAN3111CNon-Inverting Input s(ns)70 ate s y60 y a D Dela50 Del50 riv n40 on40 INFall toOUTFall e atio30 INFall toOUTFall gati30 r g a pa20 op20 Pro10 Pr10 INRise toOUTRise INRise toOUTRise 0 0 4 6 8 10 12 14 16 18 4 6 8 10 12 14 16 18 SupplyVoltage(V) SupplyVoltage(V) Figure 21. Propagation Delay vs. Supply Voltage Figure 22. Propagation Delay vs. Supply Voltage 24 20 FAN3111E FAN3111CNon-Inverting Input s) 22 s) 18 n n ( ( s 20 s y y 16 a INFall toOUTFall a INFall toOUTFall Del 18 Del n n 14 o 16 o agati 14 agati 12 p p Pro 12 INRise toOUTRise Pro 10 INRise toOUTRise 10 8 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature(°C) Temperature(°C) Figure 23. Propagation Delay vs. Temperature Figure 24. Propagation Delays vs. Temperature © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 9

F A Typical Performance Characteristics N 3 Typical characteristics are provided at 25°C, V = 12 V, and V = 3.3 V unless otherwise noted. 1 DD XREF 1 1 22 120 — FAN3111C Inverting Input (ns)20 100 CL=4.7nF Sin elays18 INRise toOUTFall (ns) 80 gle pagationD1146 INFall toOUTRise FallTime 4600 CCLL==12.0.2nnFF 1A Hig Pro12 20 CL=470pF h- S 10 0 p -50 -25 0 25 50 75 100 125 e 0 5 10 15 20 e d Temperature(°C) SupplyVoltage(V) , L o Figure 25. Propagation Delays vs. Temperature Figure 26. Fall Time vs. Supply Voltage w - S i d e 140 12 G 120 CL=4.7nF (ns) 11 CL=470pF ate D s)100 es RiseTime r e(n 80 Tim 10 ive Tim 60 CL=2.2nF Fall 9 r Rise 40 CL=1.0nF eand 8 FallTime s 20 CL=470pF Ri 0 7 0 5 10 15 20 -50 -25 0 25 50 75 100 125 SupplyVoltage(V) Temperature(°C) Figure 27. Rise Time vs. Supply Voltage Figure 28. Rise and Fall Time vs. Temperature V = 12V DD C = 470 pF L t = 9 ns RISE V (5V/div) IOUT (0.5A /div) OUT t = 8 ns FALL VOUT (5V / div) V (5V/div) IN (CMOS Input) t = 20ns/div VIN (2V/div) CLOAD = 47 nF (3.3V Input) t = 100ns / div Figure 29. Rise and Fall Waveforms (470pF) Figure 30. Quasi-Static Source Current (V =12V) DD © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 10

F A Typical Performance Characteristics N 3 Typical characteristics are provided at 25°C, V = 12 V, and V = 3.3 V unless otherwise noted. 1 DD XREF 1 1 — S IOUT (0.5A /div) in IOUT (0.5A /div) g l e 1 A H VOUT (5V / div) ig VOUT (5V / div) h - S p (V3I.N3 (V2 VIn/dpiuvt)) Ct L=O A1D0 =0 n4s7 /n dFiv (V3I.N3 (V2 VIn/dpiuvt)) Ct L=O A1D0 =0 n4s7 /n dFiv eed , L Figure 31. Quasi-Static Sink Current (V =12V) Figure 32. Quasi-Static Source Current (V =8V) o DD DD w - S i d e V G DD a t IOUT (0.5A /div) e 4.7µF 470µF D Ceramic Al.El. r i v Current Probe e FAN3111 LECROY AP015 r VOUT (5V / div) IOUT IN 1µF V C VIN (2V/div) CLOAD = 47 nF 1kHz Ceramic OUT 47LOnAFD (3.3V Input) t = 100ns / div Figure 33. Quasi-Static Sink Current (V =8V) Figure 34. Quasi-Static I / V Test Circuit DD OUT OUT © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 11

F A Applications Information N 3 The FAN3111 offers CMOS- or logic-level-compatible Figure 36 illustrates startup operation as VDD increases 1 input thresholds. In the FAN3111C, the logic input from 0 to 12 V with the output commanded to the high 1 1 thresholds are dependent on the VDD level and, with VDD level (IN+ tied to VDD, IN- tied to GND). This — of 12 V, the logic rising-edge threshold is approximately configuration might not be suitable for driving high-side 55% of V and the input falling-edge threshold is P-channel MOSFETs because the low output voltage of S DD i approximately 38% of V . The CMOS input the driver would attempt to turn the P-channel MOSFET n DD configuration offers a hysteresis voltage of on with low V levels. g DD l approximately 17% of V . The CMOS inputs can be e DD used with relatively slow edges (approaching DC) if VDD 1 A good decoupling and bypass techniques are H incorporated in the system design to prevent noise from violating the input-voltage hysteresis window. This OUT OUT @ 5 V/Div ig h allows setting precise timing intervals by fitting an R-C FAN3111C - S circuit between the controlling signal and the IN pin of p the driver. The slow rising edge at the IN pin of the e driver introduces a delay between the controlling signal e d and the OUT pin of the driver. VDD @ 5 V/Div , L In the FAN3111E, the input thresholds are dependent o w on the V voltage that typically is chosen between 2V t = 200 us/Div XREF - and 5 V. This range of V allows compatibility with S TTL and other logic levelsX RuEpF to 5 V by connecting the id XREF pin to the same source as the logic circuit that Figure 36. Startup Operation as VDD Increases e drives the FAN3111E input stage. The logic rising edge Figure 37 illustrates FAN3111E startup operation with the G a threshold is approximately 50% of VXREF and the input output commanded to the low level (IN+ tied to ground) t falling-edge threshold is approximately 30% of VXREF. and the voltage on XREF ramped from 0 to 3.3 V. e D The TTL-like input configuration offers a hysteresis r voltage of approximately 20% of V . i XREF v VDD VDD @ 5 V/Div e r Startup Operation XREF OUT The FAN3111 internal logic is optimized to drive ground FAN3111E referenced N-channel MOSFETs as V supply voltage DD OUT @ 2 V/Div rises during startup operation. As V rises from 0V to DD approximately 2 V, the OUT pin is held LOW by an internal resistor, regardless of the state of the input pins. When the internal circuitry becomes active at VXREF @ 2 V/Div approximately 2 V, the output assumes the state commanded by the inputs. t = 50 us/Div Figure 35 illustrates FAN3111C startup operation with V increasing from 0 to 12 V, with the output Figure 37. FAN3111E Startup Operation DD commanded to the low level (IN+ and IN- tied to ground). Note that OUT is held LOW to maintain an N- MillerDrive™ Gate Drive Technology channel MOSFET in the OFF state. FAN3111 drivers incorporate the MillerDrive architecture shown in Figure 38 for the output stage, a VDD combination of bipolar and MOS devices capable of providing large currents over a wide range of supply- OUT voltage and temperature variations. The bipolar devices FAN3111C carry the bulk of the current as OUT swings between OUT @ 5 V/Div 1/3 to 2/3 VDD and the MOS devices pull the output to the high or low rail. The purpose of the MillerDrive architecture is to speed VDD @ 5 V/Div up switching by providing the highest current during the Miller plateau region when the gate-drain capacitance of t = 200 us/Div the MOSFET is being charged or discharged as part of the turn-on / turn-off process. For applications with zero voltage switching during the MOSFET turn-on or turn-off Figure 35. FAN3111C Startup Operation interval, the driver supplies high peak current for fast switching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is switched on. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 12

F A The output-pin slew rate is determined by VDD voltage  Keep the driver as close to the load as possible to N and the load on the output. It is not user adjustable, but minimize the length of high-current traces. This 31 if a slower rise or fall time at the MOSFET gate is reduces the series inductance to improve high- 1 needed, a series resistor can be added. speed switching, while reducing the loop area that 1 — can radiate EMI to the driver inputs and other VDD surrounding circuitry. S i  Many high-speed power circuits can be susceptible n g to noise injected from their own output or other l e external sources, possibly causing output re- 1 triggering. These effects can be especially obvious A if the circuit is tested in breadboard or non-optimal H Input circuit layouts with long input, enable, or output i g stage VOUT leads. For best results, make connections to all h pins as short and direct as possible. -S p  The turn-on and turn-off current paths should be e minimized as discussed in the following sections. e d , L Figure 39 shows the pulsed gate-drive current path o when the gate driver is supplying gate charge to turn w Figure 38. MillerDrive™ Output Architecture the MOSFET on. The current is supplied from the local -S bypass capacitor, CBYP, and flows through the driver to id V Bypass Capacitor Guidelines the MOSFET gate and to ground. To reach the high e DD peak currents possible, the resistance and inductance G To enable this IC to turn a power device on quickly, a ianc ttsh eto pcaotnht asinh otuhled hbigeh mpeinaimk-iczuerdr.e nTt hpeu llsoecsa lwiziethdi nC tBhYisP ate local, high-frequency, bypass capacitor CBYP with low driver-MOSFET circuit, preventing them from disturbing D ESR and ESL should be connected between the VDD the sensitive analog circuitry in the PWM controller. r and GND pins with minimal trace length. This capacitor iv is in addition to bulk electrolytic capacitance of 10 µF to V V er 47 µF often found on driver and controller bias circuits. DD DS A typical criterion for choosing the value of C is to C BYP BYP keep the ripple voltage on the V supply ≤5%. Often DD this is achieved with a value ≥ 20 times the equivalent load capacitance CEQV, defined here as Qgate/VDD. FAN3111 Ceramic capacitors of 0.1 µF to 1 µF or larger are common choices, as are dielectrics, such as X5R and PWM X7R, which have good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, the value of Figure 39. Current Path for MOSFET Turn-On C may be increased to 50-100 times the C or BYP EQV C may be split into two capacitors. One should be a BYP larger value, based on equivalent load capacitance, and Figure 40 shows the current path when the gate driver the other a smaller value, such as 1-10 nF, mounted turns the MOSFET off. Ideally, the driver shunts the closest to the VDD and GND pins to carry the higher- current directly to the source of the MOSFET in a small frequency components of the current pulses. circuit loop. For fast turn-off times, the resistance and inductance in this path should be minimized. V V DD DS Layout and Connection Guidelines C The FAN3111 incorporates fast reacting input circuits, BYP short propagation delays, and output stages capable of FAN3111 delivering current peaks over 1 A to facilitate voltage transition times from under 10 ns to over 100 ns. The following layout and connection guidelines are strongly recommended: PWM  Keep high-current output and power ground paths separate from logic input signals and signal ground paths. This is especially critical when dealing with Figure 40. Current Path for MOSFET Turn-Off TTL-level logic thresholds. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 13

F A Truth Table of Logic Operation Thermal Guidelines N 3 The FAN3111 truth table indicates the operational Gate drivers used to switch MOSFETs and IGBTs at 1 1 states using the dual-input configuration. In a non- high frequencies can dissipate significant amounts of 1 inverting driver configuration, the IN- pin should be a power. It is important to determine the driver power — logic low signal. If the IN- pin is connected to logic high, dissipation and the resulting junction temperature in the S a disable function is realized, and the driver output application to ensure that the part is operating within i remains low regardless of the state of the IN+ pin. acceptable temperature limits. n g l The total power dissipation in a gate driver is the sum of e Table 1. FAN3111 Truth Table three components; P , P , and P : 1 GATE QUIESCENT DYNAMIC A IN+ IN- OUT Ptotal  Pgate  PDynamic (1) Hi g 0 0 0 h Gate Driving Loss: The most significant power loss - 0 1 0 S results from supplying gate current (charge per unit p 1 0 1 time) to switch the load MOSFET on and off at the e e 1 1 0 switching frequency. The power dissipation that results d from driving a MOSFET at a specified gate-source , L In the non-inverting driver configuration in Figure 41, voltage, VGS, with gate charge, QG, at switching o the IN- pin is tied to ground and the input signal (PWM) frequency, fSW, is determined by: w is applied to the IN+ pin. The IN- pin can be connected - S to logic high to disable the driver and the output PGATE  QG VGS  fsw (2) id remains low, regardless of the state of the IN+ pin. e Dynamic Pre-drive / Shoot-through Current: A power loss G VDD resulting from internal current consumption under a dynamic operating conditions, including pin pull-up / te pull-down resistors, can be obtained using the graphs in D IN+ Figure 11 and Figure 12 in Typical Performance ri PWM Characteristics to determine the current IDYNAMIC drawn ve OUT from VDD under actual operating conditions: r FAN3111 IN- PDYNAMIC  IDYNAMIC  VDD (3) GND Once the power dissipated in the driver is determined, the driver junction temperature rise with respect to the device lead can be evaluated using thermal equation: T  P   T (4) Figure 41. Dual-Input Driver Enabled, Non- J TOTAL JL C Inverting Configuration where: T = driver junction temperature; J θ = thermal resistance from junction to lead; and JL T = lead temperature of device in application. In the inverting driver application shown in Figure 42, the L IN+ pin is tied high. Pulling the IN+ pin to GND forces the The power dissipated in a gate-drive circuit is output low, regardless of the state of the IN- pin. independent of the drive-circuit resistance and is split proportionately among the resistances present in the VDD driver, any discrete series resistor present, and the gate resistance internal to the power switching MOSFET. Power dissipated in the driver may be estimated using the following equation:  R  IN+ FAN3111 OUT PPKGPTOTALROUT,DRIVEROURT,EDXriTverRGATE,FET (5) PWM where: IN- PPKG = power dissipated in the driver package; GND ROUT,DRIVER = estimated driver impedance derived from I vs. V waveforms; OUT OUT R = external series resistance connected between EXT the driver output and the gate of the MOSFET; and Figure 42. Dual-Input Driver Enabled, Inverting RGATE,FET = resistance internal to the load MOSFET gate Configuration and source connections. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 14

F A Typical Application Diagrams N 3 1 1 Rectified 1 AC Input — S i n g l e V DD Downstream 1 Converters A 33W Q1A H FAN3111 ig h - S p Logic e PWM V e DD d , 33W Q1B L o FAN3111 w - S i d e Figure 43. PFC Boost Circuit Utilizing Distributed Drivers for Parallel Power Switches Q1A and Q1B G a t V e IN D r i v e V r DD PWM FAN3111 Figure 44. Driver for Forward Converter Low-Side Switch Q1 V IN T2 T1 D1 VSEC D2 V DD Q2 CC PWM FAN3111 0.1µF Figure 45. Driver for Two-Transistor, Forward-Converter Gate Transformer © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 15

F A Table 2. Related Products N 3 1 Gate 1 Part Input 1 Type Drive(10) Logic Package Number Threshold — (Sink/Src) S i n FAN3111C Single 1A +1.1 A /-0.9 A CMOS Single Channel of Dual-Input/Single-Output SOT23-5 g l e FAN3111E Single 1A +1.1 A /-0.9 A External(11) SRienfgerlee nNcoen -Inverting Channel with External SOT23-5 1 A FAN3100C Single 2A +2.5A / -1.8A CMOS Single Channel of Two-Input/One-Output SOT23-5, MLP6 H i g FAN3100T Single 2A +2.5A / -1.8A TTL Single Channel of Two-Input/One-Output SOT23-5, MLP6 h - S FAN3226C Dual 2A +2.4A / -1.6A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 p e e FAN3226T Dual 2A +2.4A / -1.6A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 d , FAN3227C Dual 2A +2.4A / -1.6A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 L o w FAN3227T Dual 2A +2.4A / -1.6A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 - S FAN3228C Dual 2A +2.4A / -1.6A CMOS Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8 id e FAN3228T Dual 2A +2.4A / -1.6A TTL Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8 G a FAN3229C Dual 2A +2.4A / -1.6A CMOS Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8 t e FAN3229T Dual 2A +2.4A / -1.6A TTL Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8 D r i v FAN3268T Dual 2A +2.4A / -1.6A TTL 18V Half-Bridge Driver: Non-Inverting Channel (NMOS) SOIC8 e and Inverting Channel (PMOS) + Dual Enables r FAN3223C Dual 4A +4.3A / -2.8A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3223T Dual 4A +4.3A / -2.8A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3224C Dual 4A +4.3A / -2.8A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 FAN3224T Dual 4A +4.3A / -2.8A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 FAN3225C Dual 4A +4.3A / -2.8A CMOS Dual Channels of Two-Input/One-Output SOIC8, MLP8 FAN3225T Dual 4A +4.3A / -2.8A TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8 FAN3121C Single 9A +9.7A / -7.1A CMOS Single Inverting Channel + Enable SOIC8, MLP8 FAN3121T Single 9A +9.7A / -7.1A TTL Single Inverting Channel + Enable SOIC8, MLP8 FAN3122T Single 9A +9.7A / -7.1A CMOS Single Non-Inverting Channel + Enable SOIC8, MLP8 FAN3122C Single 9A +9.7A / -7.1A TTL Single Non-Inverting Channel + Enable SOIC8, MLP8 Notes: 10. Typical currents with OUT at 6V and VDD = 12V. 11. Thresholds proportional to an externally supplied reference voltage. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN31 11 • Rev. 1.6 16

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