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F A N 2 1 September 2015 1 0 — 3 - 2 4 FAN2110 — 3-24 V Input, 10 A, High-Efficiency, V I n Integrated Synchronous Buck Regulator p u t , 1 Features Description 0 A ,  Wide Input Voltage Range: 3 V-24 V The FAN2110 is a highly efficient, small footprint, H  Wide Output Voltage Range: 0.8 V to 80% V constant frequency, 10 A integrated synchronous Buck ig IN regulator. h  10 A Output Current The FAN2110 contains both synchronous MOSFETs -E  1% Reference Accuracy Over Temperature and a controller/driver with optimized interconnects in ff i c  Over 93% Peak Efficiency one package, which enables designers to solve high- ie current requirements in a small area with minimal  Programmable Frequency Operation: 200 KHz to external components. Integration helps to minimize nc 600 KHz critical inductances making component layout simpler y ,  Fully Synchronous Operation with Integrated and more efficient compared to discrete solutions. In Schottky Diode on Low-Side MOSFET Boosts The FAN2110 provides for external loop compensation, te Efficiency g programmable switching frequency, and current limit. r  Internal Bootstrap Diode These features allow design flexibility and optimization. at High frequency operation allows for all ceramic solutions. e  Power-Good Signal d  Starts up on Pre-Bias Outputs The summing current mode modulator uses lossless Sy current sensing for current feedback and over-current n  Accepts Ceramic Capacitors on Output protection. Voltage feedforward helps operation over a c h  External Compensation for Flexible Design wide input voltage range. r o  Programmable Current Limit Fairchild’s advanced BiCMOS power process, n o combined with low-R internal MOSFETs and a  Under-Voltage, Over-Voltage, and Thermal DS(ON) u thermally efficient MLP package, provide the ability to s Shutdown Protections dissipate high power in a small package. B  Internal Soft-Start u Output over-voltage, under-voltage, and thermal c  5x6 mm, 25-Pin, 3-Pad MLP Package shutdown protections help protect the device from k damage during fault conditions. FAN2110 also prevents R Applications pre-biased output discharge during startup in point-of- eg load applications. u  Servers & Telecom la t  Graphics Cards & Displays Related Application Notes or  Computing Systems TinyCalc™ Calculator Design Tool  Point-of-Load Regulation AN-8022 — TinyCalc™ Calculator User Guide  Set-Top Boxes & Game Consoles Ordering Information Operating Packing Part Number Temperature Range Package Method FAN2110MPX -40°C to 85°C Molded Leadless Package (MLP) 5 x 6 mm Tape and Reel FAN2110EMPX © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12

F A N Typical Application 2 1 1 0 V — IN P2 3 +5V Boot -2 C C Diode 4 HF IN VCC BOOT 15 1 V C4 Q1 I n R p RAMP C u Power RAMP 25 BOOT VOUT t, Good PGOOD 13 P1 SW 10 Q2 L A Enable EN 14 , RILIM PWM H ILIM 17 + COUT ig R DRIVER h T R(T) 18 P3 PGND -E POWER f f COMP 20 MOSFETS 24 NC ic i C2 FB R1 en C1 AGND 19 c 16 y , C3 R2 RBIAS In t e R3 g r a t e d Figure 1. Typical Application Diagram S y n c h r o Block Diagram n o u s B 5V u BOOT c VCC k Boot R IILIM Current Limit Diode e Comparator g ILIM VIN u Int ref la t COMP Error CBOOT or FB Amplifier PCWomMp arator R Q DGraivtee VOUT S SW Circuit L SS VREF CLK COUT Summing OSC RAMP  Amplifier Current AGND EN GEN Sense PGND RAMP Figure 2. Block Diagram © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12 2

F A N Pin Configuration 2 1 T N N N N W W W 1 O VI VI VI VI S S S 0 O B — 1 2 3 4 5 6 7 8 3 - 2 RAMP 25 P2 9 SW 4 V VIN NC 4 0 SW 2 1 I n p P1 u SW t, PGND 23 11 SW 1 P3 0 PGND 22 GND 12 SW A , PGND 1 H 2 i g 0 9 8 7 6 5 4 3 h 2 1 1 1 1 1 1 1 - E D P D O ff COM FB R(T) ILIM AGN VCC EN PGO icie n Figure 3. MLP 5 x 6 mm Pin Configuration (Bottom View) c y Pin Definitions , I n t e Pin # Name Description g r P1, 6-12 SW Switching Node. Junction of high-side and low-side MOSFETs. a t e P2, 2-5 VIN Power Conversion Input Voltage. Connect to the main input power source. d S P3, 21-23 PGND Power Ground. Power return and Q2 source. y n High-Side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC c 1 BOOT includes an internal synchronous bootstrap diode to recharge the capacitor on this pin to h r VCC when SW is LOW. o n Power-Good Flag. An open-drain output that pulls LOW when FB is outside the limits o 13 PGOOD specified in electrical specs. PGOOD does not assert HIGH until the fault latch is enabled. u s ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the B 14 EN regulator after a latched fault condition. This input has an internal pull-up when the IC is u c functioning normally. When a latched fault occurs, EN is discharged by a current sink. k R Input Bias Supply for IC. The IC’s logic and analog circuitry are powered from this pin. 15 VCC e This pin should be decoupled to AGND through a > 2.2 µF X5R / X7R capacitor. g u Analog Ground. The signal ground for the IC. All internal control voltages are referred to l 16 AGND a this pin. Tie this pin to the ground island/plane through the lowest impedance connection. t o r 17 ILIM Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the current- limit trip threshold lower than the internal default setting. Oscillator Frequency. A resistor (R ) from this pin to AGND sets the PWM switching 18 R(T) T frequency. 19 FB Output Voltage Feedback. Connect through a resistor divider to the output voltage. Compensation. Error amplifier output. Connect the external compensation network 20 COMP between this pin and FB. 24 NC No Connect. This pin is not used. Ramp Amplitude. A resistor (R ) connected from this pin to V sets the ramp amplitude 25 RAMP RAMP IN and provides voltage feedforward functionality. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12 3

F A N Absolute Maximum Ratings 2 1 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be 1 0 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. — In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. 3 - 2 Parameter Conditions Min. Max. Unit 4 V VIN to PGND 28 V I n VCC to AGND AGND=PGND 6 V p u BOOT to PGND 35 V t , BOOT to SW -0.5 6.0 V 1 0 Continuous -0.5 24.0 V A SW to PGND , Transient (t < 20 ns, f < 600 KHz) -5 30 V H i All other pins -0.3 V +0.3 V g CC h Human Body Model, JEDEC JESD22-A114 2.0 -E ESD KV f Charged Device Model, JEDEC JESD22-C101 2.5 fi c i e n c y Recommended Operating Conditions , I n t The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended e g operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not r recommend exceeding them or designing to absolute maximum ratings. a t e d Symbol Parameter Conditions Min. Typ. Max. Unit S V Bias Voltage VCC to AGND 4.5 5.0 5.5 V y CC n c V Supply Voltage VIN to PGND 3 24 V IN h r TA Ambient Temperature -40 +85 °C o n TJ Junction Temperature +125 °C o u fSW Switching Frequency 200 600 kHz s B u c k Thermal Information R e g u Symbol Parameter Min. Typ. Max. Unit l a TSTG Storage Temperature -65 +150 °C to r T Lead Soldering Temperature, 10 Seconds +300 °C L P1 (Q2) 4 °C/W  Thermal Resistance: Junction-to-Case P2 (Q1) 7 °C/W JC P3 4 °C/W  Thermal Resistance: Junction-to-Mounting Surface(1) 35 °C/W J-PCB P Power Dissipation, T =25°C(1) 2.8 W D A Note: 1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 35. Actual results are dependent on mounting method and surface related to the design. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12 4

F A N Electrical Specifications 2 1 Electrical specifications are the result of using the circuit shown in Figure 1 with VIN=12 V, unless otherwise noted. 1 0 Symbol Parameter Conditions Min. Typ. Max. Unit — Power Supplies 3 ICC VCC Current SfSWW==6O0p0e KnH, Vz FB=0.7 V, VCC=5 V, 8 12 mA -24 V Shutdown: EN=0, VCC=5 V 7 10 µA I n Rising VCC 4.1 4.3 4.5 V p VUVLO VCC UVLO Threshold u Hysteresis 300 mV t , Oscillator 1 0 R =50 K to GND 255 300 345 KHz A T fSW Frequency , R =24 K to GND 540 600 660 KHz H T i t Minimum On-Time(2) 50 65 ns g ONmin h - 16 V , 1.8 V , R =30 K, E VRAMP Ramp Amplitude, Peak-to-Peak RRAMIPN=200 KOU T T 0.53 V ffi c tOFFmin Minimum Off-Time(2) 100 150 ns ie n Reference c y Reference Voltage (see Figure 4 for , VFB Temperature Coefficient) 795 800 805 mV In t e Error Amplifier g G DC Gain(2) 80 85 dB ra t GBW Gain Bandwidth Product(2) VCC=5 V 12 15 MHz ed V Output Voltage(2) 0.4 3.2 V S COMP y n I Output Current, Sourcing V =5 V, V =2.2 V 1.5 2.2 mA SINK CC COMP c h ISOURCE Output Current, Sinking VCC=5 V, VCOMP=1.2 V 0.8 1.2 mA ro I FB Bias Current V =0.8 V, 25°C -850 -650 -450 nA n BIAS FB o Protection and Shutdown u s R =182 K, 25°C, f =500 KHz, B ILIM CDuersrcernipt tLioimn)i(t2 )( see Circuit VOILUIMT=1.5 V, RRAMP=24S3W K 12 14 16 A uc 16 Consecutive Clock Cycles(3) k R IILIM ILIM Current VCC=5 V, 25°C -11 -10 -9 µA e T Over-Temperature Shutdown(2) +155 °C g TSD u Internal IC Temperature l T Over-Temperature Hysteresis(2) +30 °C a HYS t o V Over-Voltage Threshold 2 Consecutive Clock Cycles(3) 110 115 121 %V r OVP OUT V Under-Voltage Shutdown 16 Consecutive Clock Cycles(3) 68 73 78 %V UVSD OUT V Fault Discharge Threshold Measured at FB Pin 250 mV FLT VFLT_HYS Fault Discharge Hysteresis Measured at FB Pin (VFB ~500 mV) 250 mV Soft-Start t V to Regulation (T0.8) 5.3 ms SS OUT f =500 KHz t Fault Enable/SSOK (T1.0)(2) SW 6.7 ms EN Continued on the following page… © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12 5

F A N Electrical Specifications (Continued) 2 1 1 Electrical specifications are the result of using the circuit shown in Figure 1 with V =12 V, unless otherwise noted. 0 IN — Symbol Parameter Conditions Min. Typ. Max. Unit 3 Control Functions -2 4 VEN EN Threshold, Rising VCC=5 V 1.35 2.00 V V VEN_HYS EN Hysteresis VCC=5 V 250 mV In p REN EN Pull-Up Resistance VCC=5 V 800 K u t I EN Discharge Current Auto-Restart Mode, V =5 V 1 µA , EN_DISC CC 1 RFBok FB OK Drive Resistance 800  0 A VPGTH_LO FCByc <le Vs(R3E) F, 2 Consecutive Clock -14 -11 -8 , H PGOOD LOW Threshold %VREF ig VPGTH_UP FCByc >le Vs(R3E) F , 2 Consecutive Clock +7.0 +10.0 +13.5 h- E VPG_LO PGOOD Output Low IOUT < 2 mA 0.4 V ffi c IPG_LK PGOOD Leakage Current VPGOOD=5 V 0.2 1.0 µA ie n Notes: c 2. Specifications guaranteed by design and characterization; not production tested. y , 3. Delay times are not tested in production. Guaranteed by design. I n t e g r a t e d S y n c h r o n o u s B u c k R e g u l a t o r © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12 6

F A N Typical Characteristics 2 1 1 0 — 1.010 1.20 3 - 1.005 1.10 2 4 V V FB 1.000 I FB 1.00 In p u 0.995 0.90 t , 1 0 0.990 0.80 A -50 0 50 100 150 -50 0 50 100 150 , H Temperature (oC) Temperature (oC) ig h Figure 4. Reference Voltage (V ) Figure 5. Reference Bias Current (I ) - FB FB E vs. Temperature, Normalized vs. Temperature, Normalized f f i c i e n 1500 1.02 c y , 1200 In z) 1.01 t H e quency (K 690000 Frequency 1.00 300KH60z 0KHz grated e Fr 0.99 S 300 y n c h 0 0.98 r o 0 20 40 60 80 100 120 140 -50 0 50 100 150 n o RT (K) Temperature (oC) u s Figure 6. Frequency vs. RT Figure 7. Frequency vs. Temperature, Normalized B u c k 1.4 1.04 R e g u 1.2 1.02 l a t o M RDS 1 Q1 ~0.32%/°C I ILI 1.00 r Q2 ~0.35%/°C 0.98 0.8 0.96 0.6 -50 0 50 100 150 -50 0 50 100 150 Temperature (°C) Temperature (oC) Figure 8. R vs. Temperature, Normalized Figure 9. I Current (I ) vs. Temperature, DS LIM ILIM (V =V =5 V), Figure 1 Normalized CC GS © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12 7

F A N Application Circuits 2 1 FAN2110 1 0 +5 V VCC 15 P 2 VIN 10 - 20 V I N — 2X .2 5 R u 10K PGOOD 13 243K 3 .3 n 3 x 1 0 u 3-24 VO UT X 5 R V RAMP NC 24 25 In 2 .4 9K COMP 20 pu 34 2.49K t 5 .6 n 5 .6 n 120p FB 19 1 BOOT * H C Co8 o -p 1e Rr2 I -n Rd ustries , 10 A ILIM 17 0 .1 u , H VO U ig EN S T 182K 14 P1 W 1 .2 u * h- E R(T) 18 1 .5  ff i c 2. 80K 30. 1 K 4 x 4 7 u ie AGND 16 P 3 PGND 390p X 5 R nc 3.3n y , I n t e g Figure 10. Application Circuit: 1.5 V , 10 A, 500 KHz (10 V-20 V ) OUT IN r a t e d S y n c FAN2110 h 100 r o +5 V VCC 15 P 2 VIN 3 .3 - 5. 5 V I N no 2 .2 u 10K 1 u us VOT U X5R PGONOCD 1234 3 .3 n 1X0 5u R 470u Buck 100 2 .4 9K 4 .9 9K COMP 20 25 RAMP 140K Reg 3 .3 n 330p u 2 .2 n FB 19 1 BOOT * H CI nCod8 ou- p sRet r7ri 5e- s R lato ILIM 17 0 .1 u r VO UT EN S 182K 14 P1 W 750n * R(T) 18 1 .5  2. 80K 30. 1 K 4 x 4 7 u AGND 16 P 3 PGND 390p X 5 R 3.3n Figure 11. Application Circuit: 1.5 V , 10 A, 500 KHz (3.3 V-5.5 V ) OUT IN © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12 8

F A N Typical Performance Characteristics 2 Typical operating characteristics using the circuit in Figure 10. V =12 V, V =5 V, T =25°C, unless otherwise specified. 1 IN CC A 1 0 — FAN2110_1.5V_500Khz FAN2110_3.3V_500Khz 100 3 100 - 2 95 4 95 V 90 I Efficiency (%) 8805 VIN = 10V Efficiency (%) 889050 VIN = 10V nput, 10 75 VVIINN == 1126VV 75 VVIINN == 1126VV A, VIN = 20V VIN = 20V H 70 70 i g 0 2 4 6 8 10 0 2 4 6 8 10 h Load Current (Amps) Load Current (Amps) -E Figure 12. 1.5 VOUT Efficiency, 500 KHz Figure 13. 3.3 VOUT Efficiency, 500 KHz(4) ff i c i e n FAN2110_1.5V_300Khz FAN2110_3.3V_300Khz c y 100 , 100 I n 95 t 95 e g Efficiency (%) 889050 Efficiency (%) 889050 rated Sy VIN = 10V VIN = 10V n 75 VIN = 12V 75 VIN = 12V ch VIN = 16V VIN = 16V r VIN = 20V VIN = 20V o 70 70 n 0 2 4 6 8 10 0 2 4 6 8 10 o Load Current (Amps) Load Current (Amps) u s Figure 14. 1.5 VOUT Efficiency, 300 KHz Figure 15. 3.3 VOUT Efficiency, 300 KHz(4) B u c FAN2110_2.5V_600Khz FAN2110_1.5V_500K(3.3-5.5V) k 95 R 100 e g 95 90 u l a Efficiency (%) 889050 Efficiency (%) 8805 tor VIN = 10V VIN = 12V 75 VIN=3.5V 75 VIN = 16V VIN=4.5V VIN = 20V VIN=5.5V 70 70 0 2 4 6 8 10 0 2 4 6 8 10 Load Current (Amps) Load Current (Amps) Figure 16. 2.5 V Efficiency ,600 KHz(4) Figure 17. 1.5 V Efficiency, 500 KHz OUT OUT (V =3.3 V to 5 V), Figure 11 IN Note: 4. Circuit values for this configuration change in Figure 10. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12 9

F A N Typical Performance Characteristics (Continued) 2 1 Typical operating characteristics using the circuit in Figure 10. V =12 V, V =5 V, T =25°C unless otherwise specified. 1 IN CC A 0 — Peak HS & LS Mosfet Tempr for 1.5V Output Package Power Dissipation at various Vout(s) (Measured on Demo Board) Fsw = 500Khz 3 80 3 - 2 70 4 Temperatures(Deg C)123456000000 VVVIIINNN===112000VVV___HLHSSS Power Dissipation (Watts) 012...55512 VVoouutt == 11..58VV V Input, 10 A, VIN=20V_LS Vout = 3.3V H 0 0 i 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 g h Load Current (A) Load Current (Amps) -E f Figure 18. Peak MOSFET Temperatures, Figure 10 Figure 19. Device Dissipation Over V vs. Load f OUT i c i e Line Regulation Data Load Regulation n c y 0.02 0.05 , ge at 0.01 ge at 0 Int olta olta 0 2 4 6 8 10 eg V V Compared to 12V) -0.010 5 10 15 20 25 Compared to No load) -0-.00.51 rated S on ( -0.02 on ( -0.15 y ulati ulati nc eg -0.03 eg -0.2 h % R N1Ao LLooaadd % R VVIINN==1200VV ro -0.04 -0.25 n Input Voltage (Volts) Load Current (Amps) o u s Figure 20. 1.5 VOUT Line Regulation Figure 21. 1.5 VOUT Load Regulation B u c Peak HS & LS Mosfet Tempr for 3.3V Output Safe Operating Area curves for 70 Deg Temperature rise k (Measured on Demo Board) VIN = 20V, Natural Convection 100 R 12 e g 80 10 u Temperatures(Deg C) 246000 VVIINN==1100VV__HLSS Load Current (Amps) 2468 350000KK lator VIN=20V_HS 600K VIN=20V_LS 0 0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 Load Current (Amps) Output Voltage (Volts) Figure 23. Typical 20 V Safe Operation Area IN Figure 22. Peak MOSFET Temperatures, 3.3 V Output(5) (SOA), 70C Ambient Temperature, Natural Convection Note: 5. Circuit values for this configuration change in Figure 10. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12 10

F A N Typical Performance Characteristics (Continued) 2 1 Typical operating characteristics using the circuit in Figure 10. V =12 V, V =5 V, T =25°C unless otherwise specified. 1 IN CC A 0 — 3 - V 2 VOUT OUT 4 V I n VSW p u EN t, 1 0 A PGOOD PGOOD , H i g h -E f f Figure 24. Startup, 10 A Load Figure 25. Startup with 1.0 V Pre-Bias on VOUT ic i e n c y , VOUT, 50mV/div In t e g r a V OUT t e d V 10V/Div S EN SW, y n c h r o PGOOD n o u s B Figure 26. Shutdown, 10 A Resistive Load Figure 27. VOUT Ripple and SW Voltage, 10 A Load u c k R e g u V , 200mV/div OUT l a t o r I 5A/Div OUT, I 5A/Div OUT, EN, 2V/Div Figure 28. Transient Response, 0-8 A Load, Figure 29. Restart on Short Circuit (Fault) 5 A / µs Slew Rate © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12 11

F A N Circuit Description 2 1 1 PWM Generation 0 1.35V EN — Refer to Figure 2 for the PWM control mechanism. FAN2110 uses the summing-mode method of control to 3 generate the PWM pulses. An amplified current-sense 2400CLKs 0.8V -2 signal is summed with an internally generated ramp and 4 the combined signal is compared with the output of the FB V error amplifier to generate the pulse width to drive the I n high-side MOSFET. Sensed current from the previous Fault p cycle is used to modulate the output of the summing 1.0V Latch u 0.8V Enable t block. The output of the summing block is also , 1 compared against a voltage threshold set by the RLIM SS 0 resistor to limit the inductor current on a cycle-by-cycle A bthaes isin. tRerRnAaMlP rreasmispt ora nhde lppsr osveitd ethse icnhpaurtg ivnogl tcaugrer enfet efodr- 3200CLKs , H i forward function. The controller facilitates external T0.8 g h compensation for enhanced flexibility. - 4000CLKs E Initialization ff T1.0 ic Once VCC exceeds the UVLO threshold and EN is Figure 31. Soft-Start Timing Diagram ie HIGH, the IC checks for a shorted FB pin before n releasing the internal soft-start ramp (SS). VCC UVLO or toggling the EN pin discharges the c internal SS and resets the IC. In applications where y , If the parallel combination of R1 and RBIAS is  1 K, external EN signal is used, VIN and VCC should be In the internal SS ramp is not released and the regulator established before the EN signal comes up to prevent t e does not start. skipping the soft-start function. g r a Enable Startup on Pre-Bias te d FAN2110 has an internal pull-up to the enable (EN) pin The regulator does not allow the low-side MOSFET to S so that the IC is enabled once VCC exceeds the UVLO operate in full synchronous mode until SS reaches 95% y threshold. Connecting a small capacitor across EN and of V (~0.76 V). This enables the regulator to startup n REF c AGND delays the rate of voltage rise on the EN pin. The on a pre-biased output and ensures that pre-biased h EN pin also serves for the restart whenever a fault outputs are not discharged during the soft-start cycle. r o occurs (refer to the Auto-Restart section). If the n regulator is enabled externally, the external EN signal Protections o u should go HIGH only after VCC is established. For s applications where such sequencing is required, The converter output is monitored and protected B FAN2110 can be enabled (after the VCC comes up) with against extreme overload, short-circuit, over-voltage, u external control, as shown in Figure 30. under-voltage, and over-temperature conditions. c k R Under-Voltage Shutdown e g If voltage on the FB pin remains below the under- u voltage threshold for 16 consecutive clock cycles, the la fault latch is set and the converter shuts down. This to protection is not active until the internal SS ramp r reaches 1.0 V during soft-start. Figure 30. Enabling with External Control Soft-Start Once internal SS ramp has charged to 0.8 V (T0.8), the output voltage is in regulation. Until SS ramp reaches 1.0 V (T1.0), the fault latch is inhibited. To avoid skipping the soft-start cycle, it is necessary to apply V before V reaches its UVLO threshold. Normal IN CC sequence for powering up would be VINVCCEN. Soft-start time is a function of oscillator frequency. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12 12

F A If auto-restart is not desired, tie the EN pin to the VCC N Over-Voltage Protection 2 pin or pull it HIGH after VCC comes up with a logic gate 1 If voltage on the FB pin exceeds 115% of V for two to keep the 1 µA current sink from discharging EN to 1 REF 0 consecutive clock cycles, the fault latch is set and 1.1V. Figure 32 shows one method to pull up EN to VCC — shutdown occurs. for a latch configuration. A shorted high-side MOSFET condition is detected 3 - when SW voltage exceeds ~0.7 V while the low-side 2 4 MOSFET is fully enhanced. The fault latch is set V immediately upon detection. I n The OV/UV fault protection circuits above are active all p the time, including during soft-start. u t , Over-Temperature Protection (OTP) 1 0 The chip incorporates an over-temperature protection A circuit that sets the fault latch when a die temperature of , H about 150°C is reached. The IC restarts when the die i g temperature falls below 125°C. h - E Auto-Restart f Figure 32. Enable Control with Latch Option fi After a fault, EN pin is discharged by a 1 µA current sink c i e to a 1.1 V threshold before the internal 800 K pull-up Power-Good (PGOOD) Signal n is restored. A new soft-start cycle begins when EN c charges above 1.35 V. PGOOD is an open-drain output that asserts LOW y , Depending on the external circuit, the FAN2110 can be when VOUT is out of regulation, as measured at the FB In pin. Thresholds are specified in the Electrical t configured to remain latched-off or to automatically e Specifications section. PGOOD does not assert HIGH g restart after a fault. until the fault latch is enabled (T1.0) (see Figure 31). r a Table 1. Fault / Restart Configurations te d EN Pin Controller / Restart State S y Pull to GND OFF (Disabled) n c Pull-up to VCC with 100K N(Aof teRre Vstar tC –o mLaetcs hUepd) OFF hro CC n Open Immediate Restart After Fault o u New Soft-Start Cycle After: Cap. to GND s tDELAY (ms)=3.9 • C(nf) B u When EN is left open, restart is immediate. c k R e g u l a t o r © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12 13

F A N Application Information 2 1 operate at a lower switching frequency. The inductor 1 Bias Supply 0 value is calculated by the following formula: — The FAN2110 requires a 5 V supply rail to bias the IC aXn5dR porro Xvi7dRe dgeacteo-udprliivneg ecnaepragcyit.o rC boentnweecet na V C C2 .a2n µdf L VOUT  (1 - VVO iUnT) (4) 3-2 AGND. ILf 4 where f is the oscillator frequency. V Since VCC is used to drive the internal MOSFET I gates, supply current is frequency and voltage n Setting the Ramp Resistor Value p dependent. Approximate VCC current (ICC) is u calculated by: RRAMP resistor plays a critical role in the design by t, providing charging current to the internal ramp 1 V 5 capacitor and also serving as a means to provide 0 ICC(mA) 4.58[( C2C27 0.013)(f 128)] (1) input voltage feedforward. A, where frequency (f) is expressed in KHz. R is calculated by the following formula: H RAMP i g h STheet toinutgpu tth veo ltOaguet pouf tth Ve oreltgauglaeto r can be set from RRAMP(K)(312.0(V5INIOU1T.8))VVINOUTf106 2 (5) -Eff i 0.8V to 80% of VIN by an external resistor divider (R1 where frequency (f) is expressed in KHz. ci and R in Figure 1). For output voltages >3.3V, e BIAS For wide input operation, first calculate R for the n output current rating may need to be de-rated RAMP c depending on the ambient temperature, power minimum and maximum input voltage conditions and y dissipated in the package and the PCB layout. (Refer use larger of the two values calculated. , I n to Thermal Information table on page 4, Figure 22, In all applications, current through the R pin must t RAMP e and Figure 23.) be greater than 10 µA from the equation below for g The external resistor divider is calculated using: proper operation: ra t e 0.8V VOUT 0.8V 650nA (2) VIN 1.8 10A (6) d RBIAS R1 RRAMP 2 Sy Connect R between FB and AGND. n BIAS If the calculated RRAMP values in Equation (5) result in c If R1 is open (see Figure 1), the output voltage is not a current less than 10 µA, use the RRAMP value that hr regulated and a latched fault occurs after the SS is satisfies Equation (6). In applications with large Input o complete (T1.0). ripple voltage, the RRAMP resistor should be no adequately decoupled from the input voltage to u If the parallel combination of R1 and RBIAS is  1K, minimize ripple on the ramp pin. For example, see s the internal SS ramp is not released and the regulator Figure 11. B does not start. u Setting the Current Limit c k Setting the Clock Frequency The current limit system involves two comparators. R Oscillator frequency is determined by an external The MAX I comparator is used with a V fixed- e LIMIT ILIM g resistor, RT, connected between the RT pin and AGND. voltage reference and represents the maximum u Resistance is calculated by: current limit allowable. This reference voltage is la temperature compensated to reflect the RDSON to (106/f)135 variation of the low-side MOSFET. The ADJUST I r R  (3) LIMIT T(K) 65 comparator is used where the current limit needs to be set lower than the V fixed reference. The 10 µA ILIM where RT is in K and frequency (f) is in KHz. current source does not track the RDSON changes over temperature, so change is added into the equations The regulator cannot start if RT is left open. for calculating the ADJUST ILIMIT comparator reference voltage, as is shown below. Figure 33 Calculating the Inductor Value shows a simplified schematic of the over-current Typically the inductor value is chosen based on ripple system. current (I ), which is chosen between 10 to 35% of L the maximum DC load. Regulator designs that require fast transient response use a higher ripple-current setting, while regulator designs that require higher efficiency keep ripple current on the low side and © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12 14

F A PW fairly high. This could lead to operation at high load N RP AM + CMOMP currents, causing overheating of the regulator. For a 21 VERR _ given R and R setting, the current limit point 1 PW ILIM RAMP 0 M varies slightly in an inverse relationship with respect — to input voltage (V ). IN VCC VMI LI +_ ILMIMAXIT LThoeo lpoo Cp oism cpomenpesnastaitoend using a feedback network 3-24 10µA + ADILJUIMSITT ILIMTRIP acoromupnlde tet htey pee-r3ro rc omampepnlifsiearti.o nF ingeutrweo r3k.4 Foshr otwypse -a2 V I _ compensation, eliminate R3 and C3. n ILIM p u RILIM t, 1 0 A Figure 33. Current-Limit System Schematic , H Since the ILIM voltage is set by a 10 µA current source ig into the RILIM resistor, the basic equation for setting h the reference voltage is: - E f VRILIM = 10µA*RILIM (7) fic To calculate R : ie ILIM Figure 34. Compensation Network n c RILIM = VRILIM/ 10µA (8) Since the FAN2110 employs summing current-mode y , The voltage VRILIM is made up of two components, architecture, type-2 compensation can be used for In VsiBdOeT M(wOhSicFhE rTe)l aatensd toV RtMhPeE AcKu r(rwehnitc hth rroeulagthe st heto lothwe- mlooapn y baapnpdliwcaidtitohn sa. nFdo/or ra pupsliec atvioenrys tlhoawt -EreSqRui reo uwtpiduet teg peak current through the inductor). Combining those capacitors, type-3 compensation may be required. r a two voltage terms results in: t R also provides feedforward compensation for e RAMP d RILIM = (VBOT + VRMPEAK)/ 10µA (9) cmhoadnuglaetso r ing aiVnI Ni.n cWreiaths esa afsix eVd RisR Ar eMdP ucveadlu, ew, htihceh S IN y RILIM = {0.96 + (ILOAD * RDSON *KT*8)} + could make it difficult to compensate the loop. For n {D*(VIN – 1.8)/(fSW*0.03*10^- (10) low-input-voltage-range designs (3 V to 8 V), RRAMP ch 3*RRAMP)}/10 µA and the compensation component values are r o where: different compared to designs with VIN between 8 V n and 24 V. o V = 0.96 + (I * R *K *8); u BOT LOAD DSON T Recommended PCB Layout s VRMPEAK = D*(VIN – 1.8)/(fSW*0.03*10^-3*RRAMP); Good PCB layout and careful attention to temperature B u ILOAD = the desired maximum load current; rise is essential for reliable operation of the regulator. c Four-layer PCB with two-ounce copper on the top and k RDSON = the nominal RDSON of the low-side bottom side and thermal vias connecting the layers is R MOSFET; recommended. Keep power traces wide and short to e g K = the normalized temperature coefficient for the minimize losses and ringing. Do not connect AGND to u T PGND below the IC. Connect the AGND pin to PGND l low-side MOSFET (on datasheet graph); a at the output OR to the PGND plane. t o D = V /V duty cycle; r OUT IN f = Clock frequency in kHz; and SW R = chosen ramp resistor value in k. RAMP V IN After 16 consecutive, pulse-by-pulse, current-limit SW cycles, the fault latch is set and the regulator shuts GND down. Cycling V or EN restores operation after a CC GND normal soft-start cycle (refer to the Auto-Restart section). The over-current protection fault latch is active during V the soft-start cycle. Use 1% resistor for RILIM. OUT Figure 35. Recommended PCB Layout Always use an external resistor R to set the ILIM current limit at the desired level. When R is not ILIM connected, the IC’s internal default current limit is © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2110 • Rev. 1.12 15

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