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F A N 2 1 August 2014 0 8 — T in y B FAN2108 — TinyBuck™ 3-24 V Input, 8 A, High- u c k Efficiency, Integrated Synchronous Buck Regulator ™ , 3 - 2 Features Description 4 V  Wide Input Voltage Range: 3 V-24 V The FAN2108 TinyBuck™ is a highly efficient, small I footprint, 8 A, synchronous buck regulator. n  Wide Output Voltage Range: 0.8 V to 80% V p IN u  8 A Output Current Tanhde aF AcNon2t1r0o8lle rc/dornivtaeirn sw ibtho tho pstiymniczherdo ninotuesrc oMnOneScFtsE Tins t, 8  Programmable Frequency Operation: 200 KHz to one package, which enables designers to solve high- A 600 KHz current requirements in a small area with minimal ,  Over 95% Peak Efficiency external components. H i g  Integrated Schottky Diode on Low-side MOSFET External compensation, programmable switching h Boosts Efficiency frequency, and current limit features allow design -E optimization and flexibility. f  Internal Bootstrap diode fi c  Power-Good Signal The summing current mode modulator uses lossless ie current sensing for current feedback and over-current n  Pre-Bias Startup protection. Voltage feedforward helps operation over a c y  Accepts Ceramic Capacitors on Output wide input voltage range. , I n  External Compensation for Flexible Design Fairchild’s advanced BiCMOS power process, combined t e  Input Under-Voltage Lockout with low-RDS(ON) internal MOSFETs and a thermally g efficient MLP package, provide the ability to dissipate r a  Programmable Current Limit high power in a small package. t e  Under-Voltage, Over-Voltage, and Thermal Output over-voltage, under-voltage, and thermal d S Shutdown Protections shutdown protections help protect the device from y  Internal Soft-Start damage during fault conditions. FAN2108 prevents n c  5 x 6 mm, 25-Pin, 3-Pad MLP Package ploraed-b aiapspelidc aotiuotnpsu.t discharge during startup in point-of- hr o n Applications o Related Application Notes u  Servers AN-8022 — TinyCalc™ Calculator s B  Point-of-Load Regulation u c  High-End Computing Systems k R  Graphics Cards e g  Battery-Powered Equipment u l  Set-Top Boxes a t o r Ordering Information Operating Temperature Packing Part Number Range Package Method FAN2108MPX -10°C to 85°C Molded Leadless Package (MLP) 5 x 6 mm Tape and Reel FAN2108EMPX -40°C to 85°C © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2108 • Rev. 1.0.3

F A N Typical Application 2 1 0 8 — IN P2 T i +5V Boot n y C C Diode B HF IN VCC BOOT 15 1 u C4 Q1 c k R ™ RAMP C Power RAMP 25 BOOT , OUT 3 Good PGOOD 13 P1 SW -24 Enable EN Q2 L V 14 RILIM PWM In ILIM 17 + COUT p R DRIVER u T R(T) PGND t 18 P3 , POWER 8 COMP 20 MOSFETS 24 NC A, C2 R1 H FB i C1 AGND 19 g 16 h C3 -E R R2 BIAS f f i R3 c i e n c y , Figure 1. Typical Application Diagram I n t e g r a t e Block Diagram d S y n c h r o n o u s B u c k R e g u l a t o r Figure 2. Block Diagram © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2108 • Rev. 1.0.3 2

F A N Pin Configuration 2 1 0 8 — T i n y B u c k ™ , 3 - 2 4 V I n p u t , 8 A , H i Figure 3. MLP 5 x 6 mm Pin Configuration (Bottom View) g h - E Pin Definitions f f i c Pin # Name Description ie n P1, 6-12 SW Switching Node. c y P2, 2-5 VIN Power Input Voltage. Connect to the main input power source. , I n P3, 21-23 PGND Power Ground. Power return and Q2 source. t e g High-Side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC includes r a 1 BOOT an internal synchronous bootstrap diode to recharge the capacitor on this pin to V when CC t e SW is LOW. d Power-Good Flag. An open-drain output that pulls LOW when FB is outside a ±10% range S 13 PGOOD y of the reference. PGOOD does not assert HIGH until the fault latch is enabled. n c ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the h 14 EN regulator after a latched fault condition. This input has an internal pull-up when the IC is r o functioning normally. When a latched fault occurs, EN is discharged by a current sink. n o 15 VCC Input Bias Supply for IC. The IC’s logic and analog circuitry are powered from this pin. u s 16 AGND Analog Ground. The signal ground for the IC. All internal control voltages are referred to B this pin. Tie this pin to the ground island/plane through the lowest impedance connection. u c Current Limit. A resistor (R ) from this pin to AGND can be used to program the current- k 17 ILIM ILIM limit trip threshold lower than the default setting. R e Oscillator Frequency. A resistor (R ) from this pin to AGND sets the PWM switching g 18 R(T) T u frequency. l a 19 FB Output Voltage Feedback. Connect through a resistor divider to the output voltage. to r Compensation. Error amplifier output. Connect the external compensation network between 20 COMP this pin and FB. 24 NC No Connect. This pin is not used. Ramp Amplitude. A resistor (R ) connected from this pin to V sets the ramp amplitude 25 RAMP RAMP IN and provides voltage feedforward functionality. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2108 • Rev. 1.0.3 3

F A N Absolute Maximum Ratings 2 1 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be 0 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 8 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. — The absolute maximum ratings are stress ratings only. T i n Parameter Conditions Min. Max. Unit y B VIN to PGND 28 V u c VCC to AGND AGND=PGND 6 V k ™ BOOT to PGND 35 V , 3 BOOT to SW -0.3 6.0 V - 2 4 Continuous -0.5 24.0 V SW to PGND V Transient (t < 20 ns, f < 600 KHz) -5 30 V I n All other pins -0.3 V +0.3 V p CC u Human Body Model, JEDEC JESD22-A114 2 kV t , ESD 8 Charged Device Model, JEDEC JESD22-C101 2.5 A , H i Recommended Operating Conditions g h - The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended E operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not ff i recommend exceeding them or designing to absolute maximum ratings. c i e n Symbol Parameter Conditions Min. Typ. Max. Unit c y VCC Bias Voltage VCC to AGND 4.5 5.0 5.5 V , I n VIN Supply Voltage VIN to PGND 3 24 V te FAN2108MPX -10 +85 °C g TA Ambient Temperature ra FAN2108EMPX -40 +85 °C t e T Junction Temperature +125 °C d J S f Switching Frequency 600 kHz y n c h r o Thermal Information n o u Symbol Parameter Min. Typ. Max. Unit s B T Storage Temperature -65 +150 °C STG u T Lead Soldering Temperature, 10 Seconds +300 °C c L k T Vapor Phase, 60 Seconds +215 °C R VP e T Infrared, 15 Seconds +220 °C g I u P1 (Q2) 4 °C/W la t θ Thermal Resistance: Junction-to-Case P2 (Q1) 7 °C/W o JC r P3 4 °C/W θ Thermal Resistance: Junction-to-Mounting Surface(1) 35 °C/W J-PCB P Power Dissipation, T =25°C(1) 2.8 W D A Note: 1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 25. Actual results are dependent on mounting method and surface related to the design. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2108 • Rev. 1.0.3 4

F A N Electrical Specifications 2 1 0 Electrical specifications are the result of using the circuit shown in Figure 1 unless otherwise noted. 8 — Symbol Parameter Conditions Min. Typ. Max. Unit T i Power Supplies n y SW=Open, FB=0.7 V, V =5 V, B CC 8 12 mA u ICC VCC Current fSW=600 KHz c k Shutdown: EN=0, VCC=5 V 7 10 µA ™ Rising V 4.1 4.3 4.5 V , CC V V UVLO Threshold 3 UVLO CC Hysteresis 300 mV - 2 4 Oscillator V f Frequency RT=50 KΩ 255 300 345 KHz In R =24 KΩ 540 600 660 KHz p T u tON Minimum On-Time(2) 50 65 ns t, 8 16 V , 1.8 V , R =30 KΩ, V Ramp Amplitude, peak-to–peak IN OUT T 0.53 V A RAMP RRAMP=200 KΩ , H tOFF Minimum Off-Time(2) 100 150 ns ig Reference h - E Reference Voltage (see Figure 4 for FAN2108MPX, 25°C 794 800 806 mV f V f FB Temperature Coefficient) FAN2108EMPX, 25°C 795 800 805 mV ic i e Error Amplifier n G DC Gain(2) 80 85 dB cy , BW Gain Bandwidth Product(2) VCC=5 V 12 15 MHz In VCOMP Output Voltage 0.4 3.2 V te g ISINK Output Current, Sourcing VCC=5 V, VCOMP=2.2 V 1.5 2.2 mA ra ISOURCE Output Current, Sinking VCC=5 V, VCOMP=1.2 V 0.8 1.2 mA te d IBIAS FB Bias Current VFB=0.8 V, 25°C -850 -650 -450 nA S Protection and Shutdown y n R Open at 25°C (see Circuit c I Current Limit ILIM 12 15 18 A h LIM Description) r o I I Current -11 -10 -9 µA n ILIM LIM o T Over-Temperature Shutdown +155 °C u TSD Internal IC Temperature s THYS Over-Temperature Hysteresis +30 °C B u V Over-Voltage Threshold Two Consecutive Clock Cycles 110 115 121 %V OVP OUT c k V Under-Voltage Shutdown 16 Consecutive Clock Cycles 68 73 78 %V UVLO OUT R VFLT Fault Discharge Threshold Measured at FB Pin 250 mV e g V Fault Discharge Hysteresis Measured at FB Pin (V ~500 mV) 250 mV u FLT_HYS FB l a Soft-Start t o t V to Regulation (T0.8) 5.3 ms r SS OUT Frequency=600 KHz t Fault Enable/SSOK (T1.0) 6.7 ms EN Note: 2. Specifications guaranteed by design and characterization; not production tested. © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2108 • Rev. 1.0.3 5

F A N Electrical Specifications (Continued) 2 1 0 Recommended operating conditions are the result of using the circuit shown in Figure 1 unless otherwise noted. 8 — Symbol Parameter Conditions Min. Typ. Max. Unit T i Control Functions n y V EN Threshold, Rising 1.35 2.00 V B EN_R u V EN Hysteresis 250 mV c EN_HYS k R EN Pull-Up Resistance 800 KΩ ™ EN , I EN Discharge Current Auto-Restart Mode 1 µA 3 EN - RFB FB OK Drive Resistance 800 Ω 24 FB < V -14 -11 -8 V VPG PGOOD Threshold FB > VREF +7 +10 +13.5 %VREF In REF p V PGOOD Output Low I < 2 mA 0.4 V u PG_L OUT t , 8 A , H i g h - E f f i c i e n c y , I n t e g r a t e d S y n c h r o n o u s B u c k R e g u l a t o r © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2108 • Rev. 1.0.3 6

F A N Typical Characteristics 2 1 0 8 1.010 1.20 — T i n 1.005 1.10 y B u V FB 1.000 I FB 1.00 ck ™ 0.995 0.90 , 3 - 2 4 0.990 0.80 V -50 0 50 100 150 -50 0 50 100 150 I n Temperature (oC) Temperature (oC) p u Figure 4. Reference Voltage (V ) Figure 5. Reference Bias Current (I ) t FB FB , vs. Temperature, Normalized vs. Temperature, Normalized 8 A , H 1500 1.02 ig h - 1200 E z) 1.01 ff H i K y c equency ( 690000 Frequenc 1.00 300KH6z00KHz iency, Fr 0.99 In 300 t e g 0 0.98 ra t 0 20 40 60 80 100 120 140 -50 0 50 100 150 e d RT (KΩ) Temperature (oC) S y Figure 6. Frequency vs. R Figure 7. Frequency vs. Temperature, Normalized n T c h r o 1.4 1.04 n o u s 1.2 1.02 B u M c RDS 1 Q1 ~0.32%/°C I ILI 1.00 k R Q2 ~0.35%/°C e 0.98 g 0.8 u l a t 0.96 o 0.6 r -50 0 50 100 150 -50 0 50 100 150 Temperature (°C) Temperature (oC) Figure 9. I Current (I ) vs. Temperature, Figure 8. R vs. Temperature, Normalized LIM ILIM DS Normalized (V =V =5V) CC GS © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2108 • Rev. 1.0.3 7

F A N Application Circuit 2 1 +5V VCC 15 P2 VIN 8-20 VIN 08 1.0u 10K — X5R PGOOD 13 200K 3.3n 3 x 4.7u T VOUT X7R in RAMP NC 24 25 y B 2.49K COMP u 20 62 2.49K c 4.7n 56p k * Inter-Technical ™ FB 19 1 BOOT SC7232-2R2M , 4.7n 3 ILIM 17 0.1u - 2 VOUT 4 EN 14 P1 SW V 200K 2.2u * R(T) 18 1.5 Inp u 2.00K 30.1K 4 x 22u t , AGND 16 P3 PGND 390p X5R 8 3.3n A , H Figure 10. Application Circuit: 1.8 VOUT, 500 KHz ig h - Typical Performance Characteristics E f f i Typical operating characteristics using the circuit shown in Figure 10. V =12 V, V =5 V, unless otherwise specified. c IN CC i e n c Efficiency @ Vo=1.8V, fsw=500KHz, Ta=250C Efficiency @ Vo=3.3V, fsw=300KHz, Ta=250C y, 95 100 In t 95 e 90 g %) %) 90 r Efficiency ( 8805 VVViiinnn===811V26VV Efficiency ( 8805 VVViiinnn===511V02VV ated S 75 Vin=20V Vin=14V y Vin=24V 75 Vin=20V n 70 c 70 h 0 2 4 6 8 0 2 4 6 8 r Load Current (A) Load Current (A) on o Figure 11. 1.8 VOUT Efficiency Over VIN vs. Load Figure 12. 3.3 VOUT Efficiency Over VIN vs. Load u s B Efficiency@ Vin=12V, Vo=1.8V u Load Regulation @ Vo=0.8V, 500kHz, 25°C c 95 0.8012 Vin=8V k 0.801 Vin=12V R Efficiency (%) 78895050 356000000KKKHHHzzz Output Voltage (V)00000.....7888890000090000.824688 VVViiinnn===122604VVV egulator 0.7996 70 0.7994 0 1 2 3 4 5 6 7 8 0.7992 0 1 2 3 4 5 6 7 8 Load Current (A) Load Current (A) Figure 13. 1.8 V Efficiency Over Frequency Figure 14. 0.8 V Load Regulation Over V OUT OUT IN vs. Load vs. Load © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2108 • Rev. 1.0.3 8

F A N Typical Performance Characteristics (Continued) 2 1 0 Typical operating characteristics using the circuit shown in Figure 10. V =12 V, V =5 V, unless otherwise specified. 8 IN CC — T i n VOUT VOUT y B u c k SW ™ PGOOD , 3 - 2 EN 4 EN V I n p u t , 8 A , Figure 15. Startup, 3 A Load Figure 16. Startup with 1 V Pre-Bias on VOUT H i g h - E f f i c i V SW e OUT n c y PGOOD , I n EN te EN g r a t e d S y n c h r Figure 17. Shutdown, 1 A Load Figure 18. Restart on Fault o n o u HS and LS MOSFET Temperature s B 90 u V OUT LSFET@ 20Vin c 80 LSFET@ 12Vin k °C)70 HHSSFFEETT@@ 2102VViinn Re I mperature (5600 gula OUT Te40 to r 30 20 0 2 4 6 8 Load Current (A) Figure 20. MOSFET Temperature – Still Air at Room Figure 19. Transient Response, 2-8 A Load Temperature © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2108 • Rev. 1.0.3 9

F A N Circuit Description 2 1 Initialization Soft-Start 0 8 Once V exceeds the UVLO threshold and EN is HIGH, Once internal SS ramp has charged to 0.8 V (T0.8), the — CC the IC checks for an open or shorted FB pin before output voltage is in regulation. Until SS ramp reaches T releasing the internal soft-start ramp (SS). 1.0 V (T1.0), the fault latch is inhibited. i n y If R1 is open (Figure 1), the error amplifier output To avoid skipping the soft-start cycle, it is necessary to B (COMP) is forced LOW and no pulses are generated. apply VIN before VCC reaches its UVLO threshold. u After the SS ramp times out (T1.0), an under-voltage c Soft-start time is a function of oscillator frequency. k latched fault occurs. ™ If the parallel combination of R1 and RBIAS is ≤ 1 KΩ, the , 3 internal SS ramp is not released and the regulator does EN 1.35V -2 not start. 4 V Bias Supply 2400CLKs 0.8V I n The FAN2108 requires a 5 V supply rail to bias the IC p and provide gate-drive energy. Connect a ≥ 1.0 µf X5R FB ut , or X7R decoupling capacitor between VCC and PGND. Fault 8 1.0V Latch A Since VCC is used to drive the internal MOSFET gates, 0.8V Enable , supply current is frequency and voltage dependent. H Approximate VCC current (ICC) is calculated by: SS ig h I =4.58+[(VCC −5+0.013)•(f −128)] (1) 3200CLKs -E CC(mA) 227 ff T0.8 ic where frequency (f) is expressed in KHz. i e 4000CLKs n Enable c T1.0 y FAN2108 has an internal pull-up to enable pin so that Figure 21. Soft-Start Timing Diagram , I n the IC is enabled once VCC is applied. Connecting a The regulator does not allow the low-side MOSFET to te small capacitor across EN and AGND delays the rate of operate in full synchronous rectification mode until g voltage rise on the EN pin. EN pin also serves for the internal SS ramp reaches 95% of V (~0.76 V). This ra restart whenever a fault occurs (refer to the Auto-Restart REF t helps the regulator to start on a pre-biased output and e section). For applications where sequencing is required, d ensures that inductor current does not "ratchet" up FAN2108 can be enabled (after the VCC comes up) with during the soft-start cycle. S external control, as shown in Figure 20. y n VCC UVLO or toggling the EN pin discharges the SS and c resets the IC. h r o n Setting the Output Voltage o u The output voltage of the regulator can be set from s 0.8 V to 80% of VIN by an external resistor divider (R1 B and R in Figure 1). u BIAS c The internal reference is 0.8 V with 650 nA, sourced k Figure 20. Enabling with External Control from the FB pin to ensure that, if the pin is open, the R e regulator does not start. g Setting the Frequency u The external resistor divider is calculated using: l a Oscillator frequency is determined by an external resistor, t RRTe,s isctaonncnee ciste cda lcbuelatwteede bny : the R(T) pin and AGND. R0.8V =VOUTR−10.8V +650nA (3) or BIAS Connect R between FB and AGND. (106/f)−135 BIAS R = (2) T(KΩ) 65 where R is in KΩ and frequency (f) is in KHz. T The regulator cannot start if R is left open. T © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2108 • Rev. 1.0.3 10

F A N Calculating the Inductor Value R = V / 10µA (7) ILIM RILIM 2 Typically the inductor is set for a ripple current (ΔIL) of The voltage VRILIM is made up of two components, VBOT 10 10% to 35% of the maximum DC load. Regulators (which relates to the current through the low-side 8 requiring fast transient response use a value on the high MOSFET) and VRMPEAK (which relates to the peak — side of this range; while regulators that require very low current through the inductor). Combining those two T output ripple and/or use high-ESR capacitors restrict voltage terms results in: i n allowable ripple current. y RILIM = (VBOT + VRMPEAK)/ 10µA (8) B V u V • (1 - OUT) c L= OUT VIN (4) RILIM = {0.96 + (ILOAD * RDSON *KT*8)} + (9) k™ ΔIL•f {D*(VIN – 1.8)/(fSW*0.03*10^-3 RRAMP)}/10µA , where f is the oscillator frequency. where: 3- 2 Setting the Ramp Resistor Value VBOT = 0.96 + (ILOAD * RDSON *KT*8); 4 V The internal ramp voltage excursion (∆VRAMP) during tON VRMPEAK = D*(VIN – 1.8)/(fSW*0.03*10^-3*RRAMP); In should be set to 0.6 V at nominal operating point. RRAMP I = the desired maximum load current; p is approximately: LOAD u (V −1.8)•V RDSON = the nominal RDSON of the low-side MOSFET; t, 8 RRAMP(KΩ) =18IxN10−6•V O•UfT −2 (5) KT = the normalized temperature coefficient for the A IN low-side MOSFET (on datasheet graph); , H where frequency (f) is expressed in KHz. D = VOUT/VIN duty cycle; ig h Setting the Current Limit f = Clock frequency in kHz; and - SW E The current limit system involves two comparators. The RRAMP = chosen ramp resistor value in kΩ. ffic MAX ILIMIT comparator is used with a VILIM fixed-voltage After 16 consecutive, pulse-by-pulse, current-limit ie reference and represents the maximum current limit n cycles, the fault latch is set and the regulator shuts allowable. This reference voltage is temperature c down. Cycling V or EN restores operation after a y compensated to reflect the RDSON variation of the low- normal soft-startC Ccycle (refer to the Auto-Restart , side MOSFET. The ADJUST ILIMIT comparator is used section). In where the current limit needs to be set lower than the te V fixed reference. The 10 µA current source does not The over-current protection fault latch is active during g ILIM r track the RDSON changes over temperature, so change is the soft-start cycle. Use 1% resistor for RILIM. at added into the equations for calculating the ADJUST e Loop Compensation d I comparator reference voltage, as is shown below. LIMIT S Figure 22 shows a simplified schematic of the over- The loop is compensated using a feedback network y current system. around the error amplifier. Figure 23 shows a complete n c type-3 compensation network. For type-2 compensation, PWM h RAMP + COMP eliminate R3 and C3. r o VERR _ n PWM o u s MAX B + ILIMIT u VCC VILIM _ c k 10µA ADJUST ILIMTRIP R + ILIMIT e g _ ILIM u l a RILIM t o r Figure 23. Compensation Network Figure 22. Current-Limit System Schematic Since the FAN2108 employs summing current-mode Since the I voltage is set by a 10 µA current source LIM architecture, type-2 compensation can be used for many into the R resistor, the basic equation for setting the ILIM applications. For applications that require wide loop reference voltage is: bandwidth and/or use very low-ESR output capacitors, type-3 compensation may be required. V = 10µA*R (6) RILIM ILIM To calculate R : ILIM © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2108 • Rev. 1.0.3 11

F A Protection If auto-restart is not desired, tie the EN pin to the VCC N 2 The converter output is monitored and protected against pin or pull it HIGH after VCC comes up with a logic gate 1 to keep the 1 µA current sink from discharging EN to 0 extreme overload, short-circuit, over-voltage, under- 8 voltage, and over-temperature conditions. 1.1 V. Figure 24 shows one method to pull up EN to VCC — for a latch configuration. An internal fault latch is set for any fault intended to shut T i down the IC. When the fault latch is set, the IC n discharges VOUT by enhancing the low-side MOSFET 15 VCC yB until FB<0.25 V. The MOSFET is not turned on again u unless FB>0.5 V. This behavior discharges the output 100K FAN2108 ck without causing undershoot (negative output voltage). ™ , Under-Voltage Shutdown 3 14 EN -2 If voltage on the FB pin remains below the under-voltage 4 threshold for 16 consecutive clock cycles, the fault latch V is set and the converter shuts down. This protection is I n not active until the internal SS ramp reaches 1.0 V 3.3n p during soft-start. u t, Over-Voltage Protection / Shutdown Figure 24. Enable Control with Latch Option 8 A If voltage on the FB pin exceeds the over-voltage , Over-Temperature Protection (OTP) H threshold for two consecutive clock cycles, the fault latch i is set and shutdown occurs. The chip incorporates an over-temperature protection g h circuit that sets the fault latch when a die temperature of A shorted high-side MOSFET condition is detected -E about 150°C is reached. The IC restarts when the die when SW voltage exceeds ~0.7 V while the low-side f MOSFET is fully enhanced. The fault latch is set temperature falls below 125°C. fic immediately upon detection. ie Power-Good (PGOOD) Signal n The two fault protection circuits above are active all the c time, including during soft-start. PGOOD is an open-drain output that asserts LOW when y , VOUT is out of regulation, as measured at the FB pin. In Auto-Restart Thresholds are specified in the Electrical Specifications t e After a fault, EN pin is discharged by a 1 µA current sink section. PGOOD does not assert HIGH until the fault g to a 1.1 V threshold before the internal 800 KΩ pull-up is latch is enabled (T1.0). ra t restored. A new soft-start cycle begins when EN e charges above 1.35 V. PCB Layout d S Depending on the external circuit, the FAN2108 can be y n configured to remain latched-off or to automatically c restart after a fault. h r o Table 1. Fault / Restart Configurations n o EN Pin Controller / Restart State u s Pull to GND OFF (Disabled) B Pull-up to V with No Restart – Latched OFF(After u CC c 100K VCC Comes Up) k Open Immediate Restart After Fault R e New Soft-Start Cycle After: g Cap. to GND t (ms)=3.9 • C(nf) u DELAY l a With EN is left open, restart is immediate. Figure 25. Recommended PCB Layout to r © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2108 • Rev. 1.0.3 12

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