Circuit Note CN-0187 Devices Connected/Referenced ADL5502 450 MHz to 6 GHz Crest Factor Detector Differential/Single-Ended Input, Dual, Circuits from the Lab™ reference circuits are engineered and AD7266 Simultaneous Sampling, 2 MSPS, 12-Bit, tested for quick and easy system integration to help solve today’s 3-Channel SAR Analog-to-Digital Converter analog, mixed-signal, and RF design challenges. For more information and/or support, visit www.analog.com/CN0187. ADA4891-4 Low Cost, Quad, CMOS, High Speed, Rail-to- Rail Amplifier 150 mA, Low Quiescent Current, CMOS Linear ADP121 Regulator in 5-Lead TSOT or 4-Ball WLCSP Crest Factor, Peak, and RMS RF Power Measurement Circuit Optimized for High Speed, Low Power, and Single 3.3 V Supply EVALUATION AND DESIGN SUPPORT CIRCUIT FUNCTION AND BENEFITS Circuit Evaluation Boards The circuit shown in Figure 1 measures peak and rms power CN-0187 Circuit Evaluation Board (EVAL-CN0187-SDPZ) at any RF frequency from 450 MHz to 6 GHz over a range of System Demonstration Platform (EVAL-SDP-CB1Z) approximately 45 dB. The measurement results are converted Design and Integration Files to differential signals in order to eliminate noise and are Schematics, Layout Files, Bill of Materials provided as digital codes at the output of a 12-bit SAR ADC with serial interface and integrated reference. A simple two- point calibration is performed in the digital domain. +3.3V +3.3V +3.3V *SEE TEXT 220Ω 442Ω +3.3V AVDD DVDD 8 U2-B 27Ω 1000pF 0.1µF CFLTR* ENBL * * U2-A VA1 1 FLTR U1 VRMS 7 U6 0.01µF ADL5502 220Ω AD7266 SDP 2 VPOS PEAK 6 * * U3-B VDRIVE BOARD 220Ω AND 0.01µF 0.01µF 27Ω SUPPORT RFIN 3 RFIN CNTL 5 CONTROL +1.25V U2-D VA2 CIRCUITS COMM (HIGH RESET; +2.5V 75Ω 4 LOW PEAK HOLD) 10kΩ DCAPA U2-C CS NOTE: U2 AND U3 ARE ADA4891-4 0.47µF 10kΩ DOUTA 0.47µF SCLK 220Ω 442Ω +3.3V +5.5V +3.3V UU33--AA 27Ω VB1 VIN VOUT 1µF U5 1µF ADP121 EN 220Ω GND 220Ω 27Ω +1.25V UU33--DD VB2 +2.5V 10kΩ DCAPB U3-C AGND DGND 0.47µF 10kΩ 0.47µF 09569-001 Figure 1. High Speed, Low Power, Crest Factor, Peak, and RMS Power Measurement System (Simplified Schematic: All connections and Decoupling Not Shown) Rev.0 Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause Tel: 781.329.4700 www.analog.com whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.

CN-0187 Circuit Note The ADL5502 is a mean-responding (true rms) power detector The internal filter capacitor of the ADL5502 provides averaging in combination with an envelope detector to accurately in the square domain but leaves some residual ac on the output. determine the crest factor (CF) of a modulated signal. It can be Signals with high peak-to-average ratios, such as W-CDMA or used in high frequency receiver and transmitter signal chains CDMA2000, can produce ac residual levels on the ADL5502 from 450 MHz to 6 GHz with envelope bandwidths over 10 MHz. VRMS dc output. To reduce the effects of these low frequency The peak-hold function allows the capture of short peaks in the components in the waveforms, some additional filtering is envelope with lower sampling rate ADCs. Total current required. The internal square-domain filter capacitance of the consumption is only 3 mA @ 3 V. ADL5502 can be augmented by connecting a C capacitor FLTR between Pin 1 (FLTR) and Pin 2 (VPOS). The ac residual can be The ADA4891-4 is a high speed, quad, CMOS amplifier that reduced further by adding capacitance to the VRMS output. offers high performance at a low cost. Current consumption is The combination of the internal 100 Ω output resistance and only 4.4 mA/amplifier at 3 V. The amplifier features true single- supply capability, with an input voltage range that extends 300 mV the added output capacitance produces a low-pass filter to reduce output ripple of the VRMS output (see the Selecting the below the negative rail. The rail-to-rail output stage enables Square-Domain Filter and Output Low-Pass Filter section of the the output to swing to within 50 mV of each rail, ensuring ADL5502 data sheet for more details). maximum dynamic range. Low distortion and fast settling time makes it ideal for this application. To measure the peak of a waveform, the control line (CNTL) must be temporally set to a logic high (reset mode for >1 µs) The AD7266 is a dual, 12-bit, high speed, low power, successive and then set back to a logic low (peak-hold mode). This allows approximation ADC that operates from a single 2.7 V to 5.25 V the ADL5502 to be initialized to a known state. When setting power supply and features sampling rates up to 2 MSPS. The the device to measure peak, peak-hold mode should be toggled device contains two ADCs, each preceded by a 3-channel for a period in which the input rms power and crest factor (CF) multiplexer, and a low noise, wide bandwidth track-and-hold is not likely to change. amplifier that can handle input frequencies in excess of 30 MHz. Current consumption is only 3 mA at 3 V. It also contains an If the ADL5502 is in peak-hold mode and the CF changes from internal 2.5 V reference. high to low or the input power changes from high to low, a faulty peak measurement is reported. The ADL5502 simply The circuit operates on a single +3.3 V supply from the keeps reporting the highest peak that occurred when the peak- ADP121, a low quiescent current, low dropout, linear regulator hold mode was activated and the input power or the CF was that operates from 2.3 V to 5.5 V and provides up to 150 mA high. Unless CNTL is reset, the PEAK output does not reflect of output current. The low 135 mV dropout voltage at 150 mA the new peak in the signal. load improves efficiency and allows operation over a wide input voltage range. The low 30 μA of quiescent current at full load The ADL5502 is capable of sourcing a VRMS output current of makes the ADP121 ideal for battery-operated portable equipment. approximately 3 mA. The output current is sourced through the on-chip, 100 Ω series resistor; therefore, any load resistor forms The ADP121 is available in output voltages ranging from 1.2 V a voltage divider with this on-chip resistance. It is to 3.3 V. The parts are optimized for stable operation with small recommended that the ADL5502 VRMS output drive high 1 μF ceramic output capacitors. The ADP121 delivers good resistive loads to preserve output swing. If an application transient performance with minimal board area. requires driving a low resistance load (as well as in cases where Short-circuit protection and thermal overload protection increasing the nominal conversion gain is desired), a buffering circuits prevent damage in adverse conditions. The ADP121 is circuit is necessary. available in tiny 5-lead TSOT and 4-ball, 0.4 mm pitch halide- The PEAK output is designed to drive 2 pF loads. It is free WLCSP packages and utilizes the smallest footprint recommended that the ADL5502 PEAK output drive low solution to meet a variety of portable applications. capacitive loads to achieve a full output response time. The CIRCUIT DESCRIPTION effects of larger capacitive loads are particularly visible when The RF signal being measured is applied to the ADL5502. tracking envelopes during the falling transitions. When the A single 75 Ω termination resistor at the RF input in parallel envelope is in a fall transition, the load capacitor discharges with the input impedance of the ADL5502 provides a through the on-chip load resistance of 1.9 kΩ. If the larger broadband match of 50 Ω. More precise resistive or reactive capacitive load is unavoidable, the additional capacitance can be matches can be applied for narrow frequency band use (see counteracted by putting a shunt resistor to ground on the PEAK the RF Input Interfacing section of the ADL5502 data sheet). output to allow for fast discharge. Such a shunt resistor also makes the ADL5502 run higher current, and it should not be lower than 500 Ω. Rev. 0| Page 2 of 7

Circuit Note CN-0187 Typical measured performance characteristics of the circuit are presented in Figure 2 through Figure 5. 2.0 1.8 10 1.6 1.4 V) 1.2 V) 1 TPUT ( 1.0 T ( OU 0.8 U P UT 450MHz 0.6 450MHz O 900MHz 900MHz 0.1 1900MHz 0.4 1900MHz 2350MHz 2350MHz 2600MHz 0.2 2600MHz 0.0–125 –20 –15 –10INPU–T5 (dBm)0 5 10 15 09569-002 Fig0u0re 59. 0M0e MasHu0zr.,2e 1d9 P0E0A MKH Oz0uI,.N 4t2Pp3Uu5Tt0 v( MVs. rHImnz0ps,. )62u6t 0L0ev MelH (Lz0i, n.S8euaprp Slyc a+le3)1.3,. 04 V5 09569-0050 MHz, Figure 2. Measured VRMS Output vs. Input Level (Log Scale), 450 MHz, 900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V The turn-on time and pulse response is strongly influenced by the size of the square-domain filter (C ) and output shunt 2.0 FLTR capacitor connected to the VRMS output. Figure 6 (taken from 1.8 the ADL5502 data sheet) shows a plot of the output response to 1.6 an RF pulse on the RFIN pin, with a 0.1 μF output filter 1.4 capacitor and no square-domain filter capacitor (C ). The FLTR V) 1.2 falling edge is particularly dependent on the output shunt PUT ( 1.0 capacitance. UT 450MHz O 0.8 900MHz 1900MHz 0.6 2350MHz PULSED RFIN 2600MHz 0.4 400mV rms RF INPUT 0.2 V) 00 0.2 0I.N4PUT (V rm0s.)6 0.8 1.0 09569-003 250mV/DI 126500mmVV rrmmss Figure 3. Measured VRMS Output vs. Input Level (Linear Scale), 450 MHz, S ( 900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V M R V 70mV rms 10 1ms/DIV VRMS 09569-053 Figure 6. Output Response to Various RF Input Pulse Levels, Supply3 V, 900 MHz Frequency, Square-Domain Filter Open, Output Filter 0.1 μF 1 T (V) U To improve the falling edge of the enable and pulse responses, P T U 450MHz a resistor can be placed in parallel with the output shunt O 900MHz 0.1 1900MHz capacitor. The added resistance helps to discharge the output 2350MHz 2600MHz filter capacitor. Although this method reduces the power-off time, the added load resistor also attenuates the output (see the Output Drive Capability and Buffering section of the ADL5502 0.01–25 –20 –15 –10INPU–T5 (dBm)0 5 10 15 09569-004 dshaotaw ssh teheet )i.m Fpigruorvee m7 (etnatk oebnt farionmed t bhye aAdDdLin5g5 0a 2p daraatall eslh 1e ektΩ) resistor. Figure 4. Measured PEAK Output vs. Input Level (Log Scale), 450 MHz, 900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V Rev. 0| Page 3 of 7

CN-0187 Circuit Note PULSED RFIN Figure 8 and Figure 9 show plots of the VRMS and PEAK error at 25°C, the temperature at which the ADL5502 is calibrated. 400mV rms RF INPUT Note that the error is not zero; this is because the ADL5502 V) does not perfectly follow the ideal linear equation, even within DI mV/ 250mV rms its operating region. The error at the calibration points is, 50 however, equal to zero by definition. 2 S ( 160mV rms M R V 70mV rms 3 2 1ms/DIV VRMS 09569-054 1 Figure 7. Output Response to Various RF Input Pulse Levels, Supply 3 V, B) 900 MHz Frequency, Squawreit-hD oPmaraailnle Fl 1ilt keΩr O pen, Output Filter 0.1 μF OR (d 0 R R E 450MHz –1 900MHz The RMS and PEAK outputs of the ADL5502 pass through 1900MHz 2350MHz unity gain buffers that drive cross-coupled stages for converting –2 2600MHz the single-ended outputs to differential signals. The internal +pa2s.5se Vs trherfoeuregnhc ea noof tthheer AuDni7ty2 6g6a i(nv ibau tfhfeer D anCAdP Aa vaonldta DgeC AdPiBv ipdienrs. ) –3–25 –20 –15 –10INPU–T5 (dBm)0 5 10 15 09569-008 This sets the common-mode voltage of the network to +1.25 V. Figure 8. Measured VRMS Linearity Error vs. Input Level, 450 MHz, 900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V The AD7266 achieves simultaneous samples of the RMS and PEAK outputs and transfers the data within a 1 µs response 3 time. The data is provided on a single serial data line. Because slope and intercept vary from device to device, board-level 2 calibration must be performed to achieve high accuracy. In general, calibration is performed by applying two input power 1 levels to the ADL5502 and measuring the corresponding output B) vwoitlthaigne tsh. Te hlien ecaarli obrpaetriaotnin pgo rianntsg aer oef g tehnee draelvlyic ceh. Tosheen b teos tb-efi t line ROR (d 0 R is characterized by calculating the conversion gain (or slope) E 450MHz –1 900MHz and intercept using the following equations: 1900MHz 2350MHz Gain = (VVRMS2 − VVRMS1)/(VIN2 − VIN1) (1) –2 2600MHz Intercept = V − (Gain × V ) (2) VRMS1 IN1 wVIhNe irse t: h e rms input voltage to RFIN. Figure –93–. 2M5easu–2re0d PE–A1K5 Line–a1r0itINy PEUr–rTo5 (rd vBsm. I)n0put Lev5el, 4501 M0Hz, 91050 M09569-009 Hz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V V is the voltage output at VRMS. VRMS Once gain and intercept are calculated, an equation can be When the characteristics (slope and intercept) of the VRMS and written that allows calculation of an (unknown) input power PEAK outputs are known, the calibration for the CF calculation based on the measured output voltage. is complete. A three-stage process must be taken to measure VIN = (VVRMS − Intercept)/Gain (3) and calculate the crest factor of any waveform. First, the unknown signal must be applied to the RF input, and the For an ideal (known) input power, the law conformance error of corresponding VRMS level is measured. This level is indicated the measured data can be calculated as in Figure 10 as VVRMS-UNKNOWN. The RF input, VIN, is calculated ERROR(dB) =20 × log VVRMS, MEASURED – Intercept (4) using VVRMS-UNKNOWN and Equation 3.    Gain × VIN, IDEAL  Rev. 0| Page 4 of 7

Circuit Note CN-0187 3.0 V) PEAK OF 2.5 T ( UNKNOWN WAVEFORM U P VRMS OF 2.0 UT UNKNOWN WAVEFORM B) VPEAK-UNKNOWON 3 (ORFE SWUALVTE IFNODREMPE)NDENT OR (d 1.5 T 450MHz VVRMS-UNKNOWN PEAK OF AC 1.0 900MHz VPEAK-CW 2 CW, CF = 0dB RESTF 0.5 122936050000MMMHHHzzz C 0 VIN1 INPUT (V rms) 09569-057 0 –0.5 Figure 10. Procedure for Crest Factor Calculation –1.0–25 –15 INPU–T5 (dBm) 5 15 09569-012 Next, the CW reference level of PEAK, VPEAK-CW, is calculated Figure 12. Measured Crest Factor of CW Signals vs. Input Level, 450 MHz, using VIN (that is, the output voltage that would be seen if the 900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V incoming waveform was a CW signal). VPEAK-CW = (VIN GainPEAK) + InterceptPEAK (5) The performance of this or any high speed circuit is highly Finally, the actual level of PEAK, V , is measured and PEAK-UNKNOWN dependent on proper PCB layout. This includes, but is not the CF can be calculated as limited to, power supply bypassing, controlled impedance lines CF = 20 log10 (VPEAK-UNKNOWN /VPEAK-CW) (6) (where required), component placement, signal routing, and power and ground planes. (See MT-031 Tutorial, MT-101 Tutorial, where V is used as a reference point to compare PEAK-CW and article, A Practical Guide to High-Speed Printed-Circuit- VPEAK-UNKNOWN. If both VPEAK values are equal, then the CF is 0 dB, Board Layout, for more detailed information regarding PCB as shown in Figure 11 with the CW signal (taken from the layout.) ADL5502 data sheet). Across the dynamic range, the calculated CF hovers about the 0 dB line. Likewise, for complex waveforms A complete design support package for this circuit note can be of 3 dB, 6 dB, and 9 dB CFs, the calculations accurately hover found at http://www.analog.com/CN0187-DesignSupport. about the corresponding CF levels. COMMON VARIATIONS 10 For applications that require less RF detection range, the 8-TONE WAVEFORM, 9dB CF 9 AD8363 rms detector can be used. The AD8363 has a detection range of 50 dB and operates at frequencies up to 6 GHz. For 8 non-rms detection applications, the AD8317/AD8318/AD8319 7 B) 4-TONE WAVEFORM, 6dB CF or ADL5513 can be used. These devices offer varying detection OR (d 6 ranges and have varying input frequency ranges up to 10 GHz T 5 C (see CN-0150 for more details). A T F 4 2-TONE WAVEFORM, 3dB CF S E 3 CIRCUIT EVALUATION AND TEST R C 2 This circuit uses the EVAL-CN0187-SDPZ circuit board and the 1 EVAL-SDP-CB1Z System Demonstration Platform (SDP) CW, 0dB CF 0 evaluation board. The two boards have 120-pin mating –1–25 –20 –15 –10INPUT– 5(dBm)0 5 10 15 09569-058 ccoirncnueitc’st opresr,f aolrlmowainncge .f oTrh teh Ee VqAuiLc-kC sNet0u1p8 a7n-SdD ePvZal ubaotaiordn coof nthtaei ns the circuit to be evaluated, as described in this note, and the Figure 11. Reported Crest Factor of Various Waveforms SDP evaluation board is used with the CN0187 evaluation software to capture the data from the EVAL-CN0187-SDPZ circuit board. Rev. 0| Page 5 of 7

CN-0187 Circuit Note The data in this circuit note were generated using a Rohde & Equipment Needed Schwarz SMT-03 RF signal source and an Agilent E3631A • PC with a USB port and Windows® XP or Windows Vista® power supply. The signal source was set to the frequencies (32-bit), or Windows® 7 (32-bit) indicated in the graphs, and the input power was stepped and data recorded in 1 dB increments. • EVAL-CN0187-SDPZ circuit evaluation board Information and details regarding how to use the evaluation • EVAL-SDP-CB1Z SDP evaluation board software for data capture can be found in the CN0187 • CN0187 evaluation software Evaluation Software Readme file. • Power supply: +6 V, or +6 V “wall wart” Information regarding the SDP board can be found in the SDP User Guide. • RF signal source • Coaxial RF cable with SMA connectors LEARN MORE Getting Started CN0187 Design Support Package: Load the evaluation software by placing the CN0187 Evaluation http://www.analog.com/CN0187-DesignSupport Software disc in the CD drive of the PC. Using "My Computer," SDP User Guide locate the drive that contains the evaluation software disc and open the Readme file. Follow the instructions contained in the Ardizzoni, John. A Practical Guide to High-Speed Printed-Circuit- Readme file for installing and using the evaluation software. Board Layout, Analog Dialogue 39-09, September 2005. Functional Block Diagram CN-0150 Circuit Note, Software-Calibrated, 1 MHz to 8 GHz, 70 dB RF Power Measurement System Using the AD8318 See Figure 1 of this circuit note for the circuit block diagram, Logarithmic Detector, Analog Devices. and the “EVAL-CN0187-SDPZ-SCH” pdf file for the circuit schematics. This file is contained in the CN0187 Design MT-031 Tutorial, Grounding Data Converters and Solving the Support Package. Mystery of “AGND” and “DGND”, Analog Devices. Setup MT-073 Tutorial, High Speed Variable Gain Amplifiers (VGAs), Analog Devices. Connect the 120-pin connector on the EVAL-CN0187-SDPZ circuit board to the connector marked “CON A” on the MT-077 Tutorial, Log Amp Basics, Analog Devices. EVAL-SDP-CB1Z evaluation (SDP) board. Nylon hardware MT-078 Tutorial, High Speed Log Amps, Analog Devices. should be used to firmly secure the two boards, using the holes MT-081 Tutorial, RMS-to-DC Converters, Analog Devices. provided at the ends of the 120-pin connectors. Using an appropriate RF cable, connect the RF signal source to the MT-101 Tutorial, Decoupling Techniques, Analog Devices. EVAL-CN0187-SDPZ board via the SMA RF input connector. Whitlow, Dana. Design and Operation of Automatic Gain With power to the supply off, connect a +6 V power supply to Control Loops for Receivers in Modern Communications the pins marked “+6 V” and “GND” on the board. If available, a Systems. Chapter 8. Analog Devices Wireless Seminar. 2006. +6 V "wall wart" can be connected to the barrel jack connector Data Sheets and Evaluation Boards on the board and used in place of the +6 V power supply. Connect the USB cable supplied with the SDP board to the USB CN-0187 Circuit Evaluation Board (EVAL-CN0187-SDPZ) port on the PC. Note: Do not connect the USB cable to the mini System Demonstration Platform (EVAL-SDP-CB1Z) USB connector on the SDP board at this time. ADL5502 Data Sheet Test ADL5502 Evaluation Board Apply power to the +6 V supply (or “wall wart”) connected to EVAL-CN0187-SDPZ circuit board. Launch the evaluation AD7266 Data Sheet software and connect the USB cable from the PC to the USB AD7266 Evaluation Board mini-connector on the SDP board. The software will be able to ADA4891 Data Sheet communicate to the SDP board if the Analog Devices System Development Platform driver is listed in the Device Manager. Once USB communications are established, the SDP board can now be used to send, receive, and capture serial data from the EVAL-CN0187-SDPZ board. Rev. 0| Page 6 of 7

Circuit Note CN-0187 REVISION HISTORY 4/11—Revision 0: Initial Version (Continued from first page) Circuits from the Lab circuits are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you may use the Circuits from the Lab circuits in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of the Circuits from the Lab circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, "Circuits from the Lab" are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. Analog Devices reserves the right to change any Circuits from the Lab circuits at any time without notice but is under no obligation to do so. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. CN09569-0-4/11(0) Rev. 0| Page 7 of 7