Dual Ultrafast Voltage Comparator Data Sheet ADCMP567 FEATURES FUNCTIONAL BLOCK DIAGRAM 250 ps propagation delay input to output 50 ps propagation delay dispersion NONINVERTING INPUT Q OUTPUT Differential PECL compatible outputs ADCMP567 Differential latch control INVERTING Q OUTPUT INPUT Robust input protection Input common-mode range −2.0 V to +3.0 V LATCH ENABLE LATCH ENABLE Input differential range ±5 V INPUT INPUT ESD protection >3 kV HBM, >200 V MM 03632-0-001 Figure 1. Power supply sensitivity >65 dB 200 ps minimum pulse width 5 GHz equivalent input rise time bandwidth Typical output rise/fall of 165 ps APPLICATIONS High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers and signal restoration Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero-crossing detectors Clock drivers Automatic test equipment GENERAL DESCRIPTION The ADCMP567 is an ultrafast voltage comparator fabricated A fast, high precision differential input stage permits consistent on Analog Devices, Inc., proprietary XFCB process. The device propagation delay with a wide variety of signals in the common- features 250 ps propagation delay with less than 35 ps overdrive mode range from −2.0 V to +3.0 V. Outputs are complementary dispersion. Overdrive dispersion, a particularly important digital signals fully compatible with PECL 10 K and 10 KH logic characteristic of high speed comparators, is a measure of the families. The outputs provide sufficient drive current to directly difference in propagation delay under differing overdrive drive transmission lines terminated in 50 Ω to V − 2 V. A latch DD conditions. input is included, which permits tracking, track-and-hold, or sample-and-hold modes of operation. The ADCMP567 is available in a 32-lead LFCSP package. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2003–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADCMP567 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Timing Information ..........................................................................8 Applications ....................................................................................... 1 Applications Information .................................................................9 Functional Block Diagram .............................................................. 1 Clock Timing Recovery ................................................................9 General Description ......................................................................... 1 Optimizing High Speed Performance ........................................9 Revision History ............................................................................... 2 Comparator Propagation Delay Dispersion ..................................9 Specifications ..................................................................................... 3 Comparator Hysteresis .............................................................. 10 Electrical Characteristics ............................................................. 3 Minimum Input Slew Rate Requirement ................................ 10 Absolute Maximum Ratings ............................................................ 5 Typical Application Circuits ......................................................... 11 Thermal Considerations .............................................................. 5 Typical Performance Characteristics ........................................... 12 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 14 Pin Configuration and Function Descriptions ............................. 6 Ordering Guide .......................................................................... 14 REVISION HISTORY 1/15—Rev. 0 to Rev. A Changes to Figure 2 and Table 3 ..................................................... 6 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 10/03—Revision 0: Initial Version Rev. A | Page 2 of 14

Data Sheet ADCMP567 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = +5.0 V, V = −5.2 V, V = +3.3 V, T = 25°C, unless otherwise noted. CC EE DD A Table 1. Parameter Symbol Condition Min Typ Max Unit DC INPUT CHARACTERISTICS1 Input Common-Mode Range V −2.0 +3.0 V CM Input Differential Voltage −5 +5 V Input Offset Voltage V −5.0 ±1.0 +5.0 mV OS Input Offset Voltage Channel Matching ±1.0 mV Offset Voltage Tempco DV /d 10.0 μV/°C OS T Input Bias Current I −10 +24 +42 μA BC Input Bias Current Tempco 10.0 nA/°C Input Offset Current −8.0 ±0.5 +8.0 μA Input Capacitance C 0.75 pF IN Input Resistance, Differential Mode 100 kΩ Input Resistance, Common-Mode 600 kΩ Open Loop Gain 60 dB Common-Mode Rejection Ratio CMRR V = −2.0 V to +3.0 V 69 dB CM Hysteresis ±1.0 mV LATCH ENABLE CHARACTERISTICS Latch Enable Common-Mode Range V V − 2.0 V V LCM DD DD Latch Enable Differential Input Voltage V 0.4 2.0 V LD Input High Current at 0.0 V −12 +6 +12 μA Input Low Current at −2.0 V −12 +6 +12 μA Latch Setup Time t 250 mV overdrive 50 ps S Latch to Output Delay t t 250 mV overdrive 300 ps PLOH, PLOL Latch Pulse Width t 250 mV overdrive 150 ps PL Latch Hold Time t 250 mV overdrive 90 ps H OUTPUT CHARACTERISTICS Output Voltage—High Level V PECL 50 Ω to −2.0 V V − 1.1 V − 0.81 V OH DD DD Output Voltage—Low Level V PECL 50 Ω to −2.0 V V − 1.95 V − 1.54 V OL DD DD Rise Time t 20% to 80% 175 ps R Fall Time t 20% to 80% 140 ps F AC PERFORMANCE Propagation Delay t 1 V overdrive 250 ps PD Propagation Delay t 20 mV overdrive 300 ps PD Propagation Delay Tempco 0.5 ps/°C Prop Delay Skew—Rising Transition to Falling ±10 ps Transition Within Device Propagation Delay Skew— ±10 ps Channel to Channel Propagation Delay Dispersion vs. ±10 ps Duty Cycle Propagation Delay Dispersion vs. Overdrive 50 mV to 1.5 V 35 ps Propagation Delay Dispersion vs. Overdrive 20 mV to 1.5 V 50 ps Propagation Delay Dispersion vs. Slew Rate 0 V to 1 V swing, 50 ps 20% to 80%, 50 ps and 600 ps Propagation Delay Dispersion vs. 1 V swing, −1.5 V to 5 ps Common-Mode Voltage 2.5 V CM Rev. A | Page 3 of 14

ADCMP567 Data Sheet Parameter Symbol Condition Min Typ Max Unit AC PERFORMANCE (continued) Equivalent Input Rise Time Bandwidth BW 0 V to 1 V swing, 3500 5000 MHz 20% to 80%, 50 ps t, t R F Toggle Rate >50% output swing 5 Gbps Minimum Pulse Width PW t from 10 ns to 200 ps PD 200 ps < ±25 ps Unit to Unit Propagation Delay Skew ±10 ps POWER SUPPLY Positive Supply Current I at +5.0 V 7 13 20 mA VCC Negative Supply Current I at −5.2 V 60 78 95 mA VEE Logic Supply Current I at 3.3 V, without load 8 13 18 mA VDD Logic Supply Current I at 3.3 V, with load 50 65 80 mA VDD Positive Supply Voltage V Dual 4.75 5.0 5.25 V CC Negative Supply Voltage V Dual −4.96 −5.2 −5.45 V EE Logic Supply Voltage V Dual 2.5 3.3 5.0 V DD Power Dissipation Dual, without load 415 515 615 mW Power Dissipation Dual, with load 575 675 mW Power Supply Sensitivity—V PSS 69 dB CC VCC Power Supply Sensitivity—V PSS 85 dB EE VEE Power Supply Sensitivity—V PSS 70 dB DD VDD 1 Under no circumstances should the input voltages exceed the supply voltages. Rev. A | Page 4 of 14

Data Sheet ADCMP567 ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS Table 2. Parameter Rating The ADCMP567 LFCSP 32-lead package option has a θJA Supply Voltages (junction-to-ambient thermal resistance) of 27.2°C/W in still air. Positive Supply Voltage (V to GND) −0.5 V to +6.0 V CC Negative Supply Voltage (V to GND) −6.0 V to +0.5 V EE ESD CAUTION Logic Supply Voltage (V to GND) −0.5 V to +6.0 V DD Ground Voltage Differential −0.5 V to +0.5 V Input Voltages Input Common-Mode Voltage −3.0 V to +4.0 V Differential Input Voltage −7.0 V to +7.0 V Input Voltage, Latch Controls −0.5 V to +5.5 V Output Current 30 mA Temperature Operating Temperature, Ambient −40°C to +85°C Operating Temperature, Junction 125°C Storage Temperature Range −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 5 of 14

ADCMP567 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GNDLEALEANCVDDQAQAVDD 21098765 33322222 GND1 PIN 1 24VEE –INA2 23NC INDICATOR +INA3 22VEE VCC4 ADCMP567 21VCC VCC5 TOP VIEW 20VCC +INB6 (Not to Scale) 19VEE –INB7 18NC GND8 17VEE 90123456 1111111 DBBCDBB D GNLELENVDQQVD NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. N1 . O TETHXEEPS ORSEECDO MPAMDE NISD GEDR OCUONNDN.ECTION FOR THE 03632-002 Figure 2. ADCMP567 Pin Configuration Table 3. ADCMP567 Pin Function Descriptions Pin No. Mnemonic Function 1 GND Analog Ground. 2 −INA Inverting analog input of the differential input stage for Channel A. The inverting A input must be driven in conjunction with the noninverting A input. 3 +INA Noninverting analog input of the differential input stage for Channel A. The noninverting A input must be driven in conjunction with the inverting A input. 4 V Positive Supply Terminal. CC 5 V Positive Supply Terminal. CC 6 +INB Noninverting analog input of the differential input stage for Channel B. The noninverting B input must be driven in conjunction with the inverting B input. 7 −INB Inverting analog input of the differential input stage for Channel B. The inverting B input must be driven in conjunction with the noninverting B input. 8 GND Analog Ground. 9 GND Analog Ground. 10 LEB One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic low), the output will track changes at the input of the comparator. In the latch mode (logic high), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven in conjunction with LEB. 11 LEB One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic high), the output will track changes at the input of the comparator. In the latch mode (logic low), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven in conjunction with LEB. 12 NC No Connect. Do not connect to this pin. 13 V Logic Supply Terminal. DD 14 QB One of two complementary outputs for Channel B. QB will be at logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEB description (Pin 11) for more information. 15 QB One of two complementary outputs for Channel B. QB will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEB description (Pin 11) for more information. 16 V Logic Supply Terminal. DD 17 V Negative Supply Terminal. EE 18 NC No Connect. Do not connect to this pin. 19 V Negative Supply Terminal. EE 20 V Positive Supply Terminal. CC 21 V Positive Supply Terminal. CC 22 V Negative Supply Terminal. EE 23 NC No Connect. Do not connect to this pin. Rev. A | Page 6 of 14

Data Sheet ADCMP567 Pin No. Mnemonic Function 24 V Negative Supply Terminal. EE 25 V Logic Supply Terminal. DD 26 QA One of two complementary outputs for Channel A. QA will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEA description (Pin 30) for more information. 27 QA One of two complementary outputs for Channel A. QA will be at logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEA description (Pin 30) for more information. 28 V Logic Supply Terminal. DD 29 NC No Connect. Do not connect to this pin. 30 LEA One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic high), the output will track changes at the input of the comparator. In the latch mode (logic low), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. 31 LEA One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic low), the output will track changes at the input of the comparator. In the latch mode (logic high), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. 32 GND Analog Ground. EPAD Exposed Pad. The recommended connection for the exposed pad is ground. Rev. A | Page 7 of 14

ADCMP567 Data Sheet TIMING INFORMATION LATCH ENABLE 50% LATCH ENABLE tS tPL tH DIFFERENTIAL VIN INPUT VOLTAGE VOD VREF± VOS tPDL tPLOH Q OUTPUT 50% tF tPDH 50% Q OUTPUT tPLOL tR 03633-0-003 Figure 3. System Timing Diagram The timing diagram in Figure 3 shows the ADCMP567 compare and latch features. Table 4 describes the terms in the diagram. Table 4. Timing Descriptions Symbol Timing Description t Input to output high Propagation delay measured from the time the input signal crosses the reference (± the input offset PDH delay voltage) to the 50% point of an output low-to-high transition t Input to output low Propagation delay measured from the time the input signal crosses the reference (± the input offset PDL delay voltage) to the 50% point of an output high-to-low transition t Latch enable to output Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to PLOH high delay the 50% point of an output low-to-high transition t Latch enable to output Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to PLOL low delay the 50% point of an output high-to-low transition t Minimum hold time Minimum time after the negative transition of the Latch Enable signal that the input signal must H remain unchanged to be acquired and held at the outputs t Minimum latch enable Minimum time that the Latch Enable signal must be high to acquire an input signal change PL pulse width t Minimum setup time Minimum time before the negative transition of the Latch Enable signal that an input signal change S must be present to be acquired and held at the outputs t Output rise time Amount of time required to transition from a low to a high output as measured at the 20% and 80% R points t Output fall time Amount of time required to transition from a high to a low output as measured at the 20% and 80% F points V Voltage overdrive Difference between the differential input and reference input voltages OD Rev. A | Page 8 of 14

Data Sheet ADCMP567 APPLICATIONS INFORMATION The ADCMP567 comparators are very high speed devices. CLOCK TIMING RECOVERY Consequently, high speed design techniques must be employed Comparators are often used in digital systems to recover clock to achieve the best performance. The most critical aspect of any timing signals. High speed square waves transmitted over a ADCMP567 design is the use of a low impedance ground plane. distance, even tens of centimeters, can become distorted due to A ground plane, as part of a multilayer board, is recommended stray capacitance and inductance. Poor layout or improper for proper high speed performance. Using a continuous con- termination can also cause reflections on the transmission line, ductive plane over the surface of the circuit board can create further distorting the signal waveform. A high speed comparator this, allowing breaks in the plane only for necessary signal can be used to recover the distorted waveform while maintaining a paths. The ground plane provides a low inductance ground, minimum of delay. eliminating any potential differences at different ground points OPTIMIZING HIGH SPEED PERFORMANCE throughout the circuit board caused by ground bounce. A proper ground plane also minimizes the effects of stray capacitance on As with any high speed comparator amplifier, proper design and the circuit board. layout techniques should be used to ensure optimal performance from the ADCMP567. The performance limits of high speed It is also important to provide bypass capacitors for the power circuitry can easily be a result of stray capacitance, improper supply in a high speed application. A 1 μF electrolytic bypass ground impedance, or other layout issues. capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors will reduce any potential voltage Minimizing resistance from source to the input is an important ripples from the power supply. In addition, a 10 nF ceramic consideration in maximizing the high speed operation of the capacitor should be placed as close as possible from the power ADCMP567. Source resistance in combination with equivalent supply pins on the ADCMP567 to ground. These capacitors act input capacitance could cause a lagged response at the input, as a charge reservoir for the device during high frequency thus delaying the output. The input capacitance of the ADCMP567 switching. in combination with stray capacitance from an input pin to ground could result in several picofarads of equivalent capacitance. The LATCH ENABLE input is active low (latched). If the A combination of 3 kΩ source resistance and 5 pF of input latching function is not used, the LATCH ENABLE input capacitance yields a time constant of 15 ns, which is significantly should be attached to V (V is a PECL logic high), and the DD DD slower than the sub 500 ps capability of the ADCMP567. Source complementary input, LATCH ENABLE, should be tied to impedances should be significantly less than 100 Ω for best V − 2.0 V. This will disable the latching function. DD performance. Occasionally, one of the two comparator stages within the Sockets should be avoided due to stray capacitance and induc- ADCMP567 will not be used. The inputs of the unused comparator tance. If proper high speed techniques are used, the ADCMP567 should not be allowed to float. The high internal gain may cause should be free from oscillation when the comparator input signal the output to oscillate (possibly affecting the comparator that is passes through the switching threshold. being used) unless the output is forced into a fixed state. This is easily accomplished by ensuring that the two inputs are at least COMPARATOR PROPAGATION DELAY one diode drop apart, while also appropriately connecting the DISPERSION LATCH ENABLE and LATCH ENABLE inputs as described The ADCMP567 has been specifically designed to reduce above. propagation delay dispersion over an input overdrive range of The best performance is achieved with the use of proper PECL 100 mV to 1 V. Propagation delay overdrive dispersion is the terminations. The open emitter outputs of the ADCMP567 are change in propagation delay that results from a change in the designed to be terminated through 50 Ω resistors to V −2.0 V, degree of overdrive (how far the switching point is exceeded by DD or any other equivalent PECL termination. If high speed PECL the input). The overall result is a higher degree of timing accuracy signals must be routed more than a centimeter, microstrip or since the ADCMP567 is far less sensitive to input variations than stripline techniques may be required to ensure proper transition most comparator designs. times and prevent output ringing. Propagation delay dispersion is a specification that is important in critical timing applications such as ATE, bench instruments, and nuclear instrumentation. Overdrive dispersion is defined Rev. A | Page 9 of 14

ADCMP567 Data Sheet as the variation in propagation delay as the input overdrive –VH +VH 2 2 conditions are changed (see Figure 4). For the ADCMP567, 0V overdrive dispersion is typically 35 ps as the overdrive is INPUT changed from 100 mV to 1 V. This specification applies for both 1 positive and negative overdrive since the ADCMP567 has equal delays for positive and negative going inputs. The 35 ps propagation delay overdrive dispersion of the ADCMP567 offers considerable improvement of the 100 ps dispersion of other similar series comparators. 1.5V OVERDRIVE 0 INPUT VOLTAGE OUTPUT 20mV OVERDRIVE VREF± VOS 03633-0-005 Figure 5. Comparator Hysteresis Transfer Function 60 DISPERSION Q OUTPUT 50 03633-0-004 Figure 4. Propagation Delay Dispersion V) 40 m COMPARATOR HYSTERESIS S ( SI 30 E R The addition of hysteresis to a comparator is often useful in a E T S noisy environment or where it is not desirable for the com- Y 20 H parator to toggle between states when the input signal is at the switching threshold. The transfer function for a comparator 10 with hysteresis is shown in Figure 5. If the input voltage acpomprpoaarcahteosr twhiel lt hswreistchho lfdro fmro ma 0 t htoe na e1g wathiveen d tihree citnipount, tchroe sses 0–25 –20 – L1A5TCH = L–1E0– LEB (m–5V) 0 5 03632-0-006 +V /2. The new switching threshold becomes −V /2. The H H Figure 6. Comparator Hysteresis Transfer Function comparator will remain in a 1 state until the threshold −VH/2 is Using Latch Enable Input crossed coming from the positive direction. In this manner, MINIMUM INPUT SLEW RATE REQUIREMENT noise centered on 0 V input will not cause the comparator to switch states unless it exceeds the region bounded by ±V /2. As for all high speed comparators, a minimum slew rate must H be met to ensure that the device does not oscillate when the Positive feedback from the output to the input is often used to input crosses the threshold. This oscillation is due in part to the produce hysteresis in a comparator (see Figure 9). The major high input bandwidth of the comparator and the parasitics of problem with this approach is that the amount of hysteresis the package. Analog Devices recommends a slew rate of 5 V/μs varies with the output logic levels, resulting in a hysteresis that or faster to ensure a clean output transition. If slew rates less is not symmetrical around zero. than 5 V/μs are used, then hysteresis should be added to reduce Another method to implement hysteresis is generated by the oscillation. introducing a differential voltage between LATCH ENABLE and LATCH ENABLE inputs (see Figure 10). Hysteresis generated in this manner is independent of output swing and is symmetrical around zero. The variation of hysteresis with input voltage is shown in Figure 6. Rev. A | Page 10 of 14

Data Sheet ADCMP567 TYPICAL APPLICATION CIRCUITS VIN VIN ADCMP567 OUTPUTS ADCMP567 OUTPUTS VREF LEANTACBHLE VDD– 2V HYSTERESIS 450 VDD– 2V INPUTS VOLTAGE ALL RESISTORS 50 03632-0-007 ALL RESISTORS 50 UNLESS OTHERWISE NOTED 03632-0-010 Figure 7. High Speed Sampling Circuits Figure 10. Hysteresis Using Latch Enable Input +VREF ADCMP567 OUTPUTS VIN 50 50 VIN ADCMP567 50 50 100 100 ADCMP567 –VREF (VDD– 2) 2 03632-0-011 LEANTACBHLE VDD– 2V INPUTS ALL RESISTORS 50 03632-0-008 Figure 8. High Speed Window Comparator Figure 11. How to Interface a PECL Output to an Instrument with a 50 Ω to Ground Input VIN ADCMP567 OUTPUTS VREF R1 R2 VDD– 2V ALL RESISTORS 50 03632-0-009 Figure 9. Hysteresis Using Positive Feedback Rev. A | Page 11 of 14

ADCMP567 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VCC = +5.0 V, VEE = −5.2 V, VDD = +3.3 V, TA = 25°C, unless otherwise noted. 30 23.0 22.9 25 A) 22.8 URRENT (A) 1250 CURRENT (–IN = 0V)222222...657 S C AS 1V, A BI= 22.4 UT BI 10 PUT (+IN 22.3 P N IN 5 +IN I 22.2 22.1 –02N.O5NINVE–R1T.5ING INP–U0T.5 VOLTAG0.E5 (INVERT1.I5NG VOLT2A.5GE = 0.53V).5 03632-0-013 22.0–40 –20 0TEMPER2A0TURE (°4C0) 60 80 03632-0-016 Figure 12. Input Bias Current vs. Input Voltage Figure 15. Input Bias Current vs. Temperature 60 2.0 1.8 50 1.6 mV) 1.4 mV) 40 AGE ( 1.2 SIS ( 30 LT 1.0 RE O E SET V 0.8 HYST 20 F 0.6 F O 0.4 10 0.2 0–40 –20 0TEMPER2A0TURE (°4C0) 60 80 03632-0-014 0–25 –20 – L1A5TCH = L–1E0– LEB (m5V) 0 5 03632-0-017 Figure 13. Input Offset Voltage vs. Temperature Figure 16. Hysteresis vs. ∆Latch 195 195 185 185 175 175 ME (ps) 165 ME (ps) 165 TI 155 TI 155 145 145 135 135 125–40 –30 –20 –10 0 TE1M0PE2R0ATU30RE 4(°0C) 50 60 70 80 90 03632-0-015 125–40 –30 –20 –10 0 TE1M0PE2R0ATU30RE 4(°0C) 50 60 70 80 90 03632-0-018 Figure 14. Rise Time vs. Temperature Figure 17. Fall Time vs. Temperature Rev. A | Page 12 of 14

Data Sheet ADCMP567 240 236 238 235 ps) 236 ps) 234 Y ( Y ( A 234 A EL EL 233 D D N 232 N O O TI TI 232 A A G 230 G A A OP OP 231 R 228 R P P 226 230 224–40 –30 –20 –10 0 TE1M0PE2R0ATU30RE 4(°0C) 50 60 70 80 90 03632-0-019 229–2 –I1NPUT COMM0ON-MODE V1OLTAGE (V)2 3 03632-0-022 Figure 18. Propagation Delay vs. Temperature Figure 21. Propagation Delay vs. Common-Mode Voltage 60 0 –5 s) 50 s) p p R ( R ( –10 O O R 40 R ER ER –15 Y Y A A EL 30 EL –20 D D N N O O –25 ATI 20 ATI G G A A –30 P P O O R 10 R P P –35 00 0.2 0.4OVE0R.6DRIVE0 V.8OLTA1G.0E (V) 1.2 1.4 1.6 03632-0-020 –400.15 2.15 P4U.1L5SEWIDTH6 (.n1s5) 8.15 03632-0-023 Figure 19. Propagation Delay Error vs. Overdrive Voltage Figure 22. Propagation Delay Error vs. Pulse Width 2.5 2.3 V) LL ( 2.1 A F D N A 1.9 E S RI UT 1.7 P T U O 1.5 1.31.0 1.1 1.2 1.3 1.4TIM1E. 5(ns)1.6 1.7 1.8 1.9 2.0 03632-0-021 Figure 20. Rise and Fall of Outputs vs. Time Rev. A | Page 13 of 14

ADCMP567 Data Sheet OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX PIN 1 25 32 INDICATOR 24 1 INDICAPTINO R1 BS4C.7 5SQ B0.S5C0 EXPPOADSED 22..8750 SQ 2.55 17 8 16 9 0.50 TOP VIEW 0.40 BOTTOM VIEW 0.20 MIN 1.00 12° MAX 0.80 MAX 0.30 3.50REF 0.65 TYP 0.85 0.80 0.05 MAX FOR PROPER CONNECTION OF 0.02 NOM THE EXPOSED PAD, REFER TO SEATING 0.30 COPL0A.0N8ARITY TFHUEN CPTINIO CNO DNEFSIGCURRIPATTIOIONNS AND PLANE 0.25 0.20 REF SECTION OF THIS DATA SHEET. 0.1C8OMPLIANTTO JEDEC STANDARDS MO-220-VHHD-2 05-24-2012-A Figure 23. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-8) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADCMP567BCPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-8 1 Z = RoHS Compliant Part ©2003–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03632-0-1/15(A) Rev. A | Page 14 of 14

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-ADCMP567BCPZ ADCMP567BCPZ