SigmaDSP Digital Audio Processor Data Sheet ADAU1452/ADAU1451/ADAU1450 FEATURES I2C and SPI control interfaces (both slave and master) Standalone operation Qualified for automotive applications Self boot from serial EEPROM Fully programmable audio DSP for enhanced sound processing 6-channel, 10-bit SAR auxiliary control ADC Features SigmaStudio, a proprietary graphical programming 14 multipurpose pins for digital controls and outputs tool for the development of custom signal flows On-chip regulator for generating 1.2 V from 3.3 V supply Up to 294.912 MHz, 32-bit SigmaDSP core at 1.2 V 72-lead, 10 mm × 10 mm LFCSP package with 5.3 mm Up to 6144 SIMD instructions per sample at 48 kHz exposed pad Up to 40 kWords of parameter/data RAM Available in two temperature ranges: Up to 800 ms digital audio delay pool at 48 kHz −40°C to +105°C Audio input/output and routing 0°C to +70°C 4 serial input ports, 4 serial output ports 48-channel, 32-bit digital input/output up to a sample rate APPLICATIONS of 192 kHz Automotive audio processing Flexible configuration for TDM, I2S, left and right justified Head units formats, and PCM Navigation systems Up to 8 stereo ASRCs from 1:8 up to 7.75:1 ratio and Rear seat entertainment systems 139 dB DNR DSP amplifiers (sound system amplifiers) Stereo S/PDIF input and output (not on the ADAU1450) Commercial and professional audio processing Four PDM microphone input channels Consumer audio processing Multichannel, byte addressable, TDM serial ports Clock oscillator for generating master clock from crystal Integer PLL and flexible clock generators Integrated die temperature sensor FUNCTIONAL BLOCK DIAGRAM—ADAU1452/ADAU1451 SPI/I2C* SPI/I2C* SELFBOOT MP13 TO MP0 AUXADC5 TOAUXADC0 PLLFILT XTALIN/MCLK XTALOUT ADAU1452/ ADAU1451 VDRIVE REGULATOR THD_P TEMPERATURE SI2LCA/SVPEI MI2ACS/STPEIR AUGXP IAOD/C PLL OSCCILLOLCAKTOR CLKOUT THD_M SENSOR INPUT AUDIO OUTPUT AUDIO ROUTING MATRIX ROUTING MATRIX 294.912MHz2 SPDIFIN RESC/PEDIVIFER PRPORGORCAEMSMSAINBGL EC OARUEDIO TRASN/SPMDIITFTER SPDIFOUT RAM, ROM, WATCHDOG, MEMORY PARITY CHECK SDATA_IN3 DTI(OG4 8IST-CDAHALAT AANU_NDIENIOL0 SINEPRUIAT(× LP4 )DOARTTAS 8 × 2-CHANNEL OSUETRPIUATL PDOARTATS S(D4DI8GA-CITTHAAA_LNO ANUUETDL3I OTO SDATA_OUT0 INPUTS) ASYNCHRONOUS (×4) OUTPUTS) SAMPLE RATE DIGITAL CONVERTERS MIC INPUT BCLK_IN3 TO BCLK_IN0/ INPUT OUTPUT BCLK_OUT3 TO BCLK_OUT0 LRCL(IKN_PIUNT3 CTOLO LCRKC LPKA_IRINS0) DCOL(M×OA4C)INKS CLODCEKJI TGTEENRE ARNADTOR DCOL(M×OA4C)INKS L(ORUCTLPKU_TO UCTL3O CTOK PLRACIRLSK)_OUT0 * SSCPLI/KI2,C S ICNLC,L MUODESSI, ATHDED RF1O, LSLSO, WANINDG A PDIDNR F0U PNICNTSI.ONS: SS_M, MOSI_M, SCL_M, SCLK_M, SDA_M, MISO_M, MISO, SDA, 11486-001 Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADAU1452/ADAU1451/ADAU1450 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Auxiliary ADC ............................................................................ 88 Applications ....................................................................................... 1 SigmaDSP Core .......................................................................... 88 Functional Block Diagram—ADAU1452/ADAU1451 ................. 1 Software Features ....................................................................... 93 Revision History ............................................................................... 3 Pin Drive Strength, Slew Rate, and Pull Configuration ........ 94 Functional Block Diagram—ADAU1450 ...................................... 5 Global RAM and Control Register Map ...................................... 96 General Description ......................................................................... 6 Random Access Memory .......................................................... 96 Differences Between the ADAU1452, ADAU1452-150, Control Registers Overview ...................................................... 97 ADAU1452K, ADAU1451, and ADAU1450 .............................. 6 Control Register Details .............................................................. 107 Specifications ..................................................................................... 7 PLL Configuration Registers .................................................. 107 Electrical Characteristics ........................................................... 11 Clock Generator Registers ...................................................... 112 Timing Specifications ................................................................ 12 Power Reduction Registers ..................................................... 116 Absolute Maximum Ratings .......................................................... 21 Audio Signal Routing Registers .............................................. 119 Thermal Characteristics ............................................................ 21 Serial Port Configuration Registers ....................................... 124 Maximum Power Dissipation ................................................... 21 Flexible TDM Interface Registers ........................................... 128 ESD Caution ................................................................................ 22 DSP Core Control Registers .................................................... 132 Pin Configuration and Function Descriptions ........................... 23 Debug and Reliability Registers .............................................. 137 Theory of Operation ...................................................................... 28 DSP Program Execution Registers ......................................... 146 System Block Diagram ............................................................... 28 Multipurpose Pin Configuration Registers........................... 149 Overview ...................................................................................... 28 ASRC Status and Control Registers ....................................... 154 Initialization ................................................................................ 30 Auxiliary ADC Registers ......................................................... 158 Master Clock, PLL, and Clock Generators.............................. 33 S/PDIF Interface Registers ...................................................... 159 Power Supplies, Voltage Regulator, and Hardware Reset ...... 40 Hardware Interfacing Registers .............................................. 172 Temperature Sensor Diode........................................................ 42 Soft Reset Register .................................................................... 190 Slave Control Ports ..................................................................... 42 Applications Information ............................................................ 191 Master Control Ports .................................................................. 50 PCB Design Considerations ................................................... 191 Self Boot ....................................................................................... 52 Typical Applications Block Diagram ..................................... 192 Audio Signal Routing ................................................................. 54 Example PCB Layout ............................................................... 193 Serial Data Input/Output........................................................... 65 PCB Manufacturing Guidelines ............................................. 194 Flexible TDM Interface .............................................................. 76 Outline Dimensions ..................................................................... 195 Asynchronous Sample Rate Converters .................................. 81 Ordering Guide ........................................................................ 195 Digital PDM Microphone Interface ......................................... 84 Automotive Products ............................................................... 195 Multipurpose Pins ...................................................................... 85 Rev. D | Page 2 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 REVISION HISTORY 7/2018—Rev. C to Rev. D Changes to Table 61 ........................................................................ 92 Changes to Features Section ............................................................ 1 Changes to Software Safeload Section and Table 62 .................. 93 Added Table 1; Renumbered Sequentially ..................................... 4 Changes to Table 65, Table 66, and Table 67 ............................... 96 Changes to General Description Section, Differences Between Changes to Table 68 ...................................................................... 101 the ADAU1452, ADAU1452-150, ADAU1452K, ADAU1451, Changes to PLL Configuration Registers Section ..................... 107 and ADAU1450 Section, and Table 2 ............................................. 4 Changes to Table 74 ...................................................................... 110 Changes to Specifications Section and Table 3.............................. 7 Changes to Clock Generator Registers Section ......................... 112 Changes to Table 4 ............................................................................ 9 Changes to Power Reduction Registers Section ........................ 116 Changes to Table 5 .......................................................................... 11 Changes to Audio Signal Routing Registers Section ................ 119 Changes to Auxiliary ADC Section, Table 6, and Master Clock Changes to Serial Port Configuration Registers Section ......... 124 Input Section .................................................................................... 12 Changes to Flexible TDM Interface Registers Section ............. 128 Changes to Reset Section ............................................................... 13 Changes to Table 97 ...................................................................... 135 Changes to Serial Ports Selection Section and Table 9 ............... 14 Changes to Debug and Reliability Registers Section ................ 137 Changes to Figure 6, Multipurpose Pins Section, Table 10, Added Software Panic Value Register 0 Section, Table 109, S/PDIF Transmitter Section, Table 11, and S/PDIF Receiver Software Panic Value Register 1 Section, and Table 110 .......... 144 Section .............................................................................................. 15 Changes to DSP Program Execution Registers Section ........... 146 Change to I2C Interface—Slave Section ....................................... 16 Changes to Multipurpose Pin Configuration Registers Change I2C Interface—Master Section ......................................... 17 Section ............................................................................................ 149 Change SPI Interface—Slave Section............................................ 18 Changes to ASRC Status and Control Registers Section ......... 154 Change SPI Interface—Master Section ........................................ 19 Changes to Auxiliary ADC Registers Section ........................... 158 Change to PDM Inputs Section ..................................................... 20 Changes to S/PDIF Interface Registers Section ........................ 159 Deleted Table 20; Renumbered Sequentially ............................... 21 Changes to Hardware Interfacing Registers Section ................ 172 Added Table 24 ................................................................................ 21 Changes to Soft Reset Registers Section .................................... 190 Changes to Table 18, Thermal Characteristics Section, Table 20, Changes to Component Placement Section .............................. 191 Table 21, Table 22, and Table 23 .................................................... 21 Changes to Figure 86 .................................................................... 192 Added Table 25 ................................................................................ 22 Changes to Example PCB Layout Section and Figure 88 ........ 193 Changes to Table 26 ........................................................................ 23 Changes to Ordering Guide ......................................................... 195 Changes to Overview Section ........................................................ 28 Changes to Automotive Products Section ................................. 195 Changes to Figure 14 ...................................................................... 31 Changes to Recommended Program/Parameter Loading 7/2014—Rev. B to Rev. C Procedure Section and Table 27 .................................................... 32 Changes to SCL_M/SCLK_M/MP2 Pin Description, Changes to Setting the Master Clock and PLL Mode Section Table 23 ............................................................................................. 19 and Figure 16 ................................................................................... 34 Change to PLL Lock Register Section .......................................... 96 Changes to Example PLL Settings Section and Table 28 ........... 35 Changes to Ordering Guide ......................................................... 180 Changes to PLL Filter Section and Table 29 ................................ 36 Changes to Clock Generators Section and Figure 18 ................. 37 5/2014—Rev. A to Rev. B Deleted Figure 19 ............................................................................ 38 Reorganized Layout ........................................................... Universal Added Figure 19 .............................................................................. 38 Added ADAU1452 and ADAU1451 ................................. Universal Changes to Figure 20 and Figure 21 ............................................. 38 Changes to Features Section ............................................................ 1 Changes to Master Clock Output Section and Figure 22 .......... 39 Moved Revision History Section ..................................................... 3 Moved Figure 23 .............................................................................. 40 Changes to General Description Section ....................................... 4 Changes to Power Supplies Section, Table 31, and Voltage Added Differences Between the ADAU1452, ADAU1451, and Regulator Section ............................................................................ 40 ADAU1450 Section and Table 1, Renumbered Sequentially ....... 4 Change to I2C Slave Port Section .................................................. 44 Added Functional Block Diagram—ADAU1450 Section and Change to SPI Slave Port Section and Table 36 ........................... 47 Figure 2, Renumbered Sequentially ................................................ 5 Changes to I2C Master Interface Section ..................................... 50 Changes to Table 2 ............................................................................ 6 Changes to Table 39 ........................................................................ 51 Changes to Table 3 ............................................................................ 7 Deleted Figure 45 ............................................................................ 57 Changes to Table 6 ............................................................................ 9 Changes to S/PDIF Receiver Inputs to DSP Core Section ......... 57 Changes to Maximum Power Dissipation Section, Table 19, Changes to Digital PDM Microphone Interface Section and and Table 20 ..................................................................................... 17 Figure 72 ........................................................................................... 84 Added Table 21 and Table 22 ......................................................... 17 Changes to Programming the SigmaDSP Core Section ............ 90 Changes to Figure 12 and Table 23 ............................................... 18 Added Table 60 ................................................................................ 91 Changes to Overview Section ........................................................ 22 Rev. D | Page 3 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Change to Clocking Overview Section and Power-Up Changes to Auxiliary Output Mode Section ............................... 70 Sequence Section ............................................................................ 24 Change to Digital PDM Microphone Interface Section ............ 71 Changes to Setting the Master Clock and PLL Mode Section .. 27 Changes to SigmaDSP Core Section ............................................ 76 Changes to Example PLL Settings Section and Table 25 ........... 28 Changes to Soft Reset Function Section ...................................... 81 Changed PLL Loop Filter Section to PLL Filter Section ........... 29 Changes to Random Access Memory Section ............................ 83 Changes to PLL Filter Section, Figure 17 Caption, and Added Table 62 and Table 63 ........................................................ 83 Table 26 ............................................................................................ 29 Changes to Table 84 ..................................................................... 109 Changes to Clock Generators Section ......................................... 30 Changed PLL Loop Filter Section to PLL Filter Section ......... 176 Changes to Master Clock Output Section ................................... 31 Change to EOS/ESD Protection Section ................................... 177 Changes to I2C Slave Port Section ................................................ 35 Change to PCB Manufacturing Guidelines Section ................ 179 Changes to Audio Signal Routing Section .................................. 43 Changes to Ordering Guide ........................................................ 180 Changes to Serial Audio Inputs to DSP Core Section ............... 44 Changes to Asynchronous Sample Rate Converter Input 1/2014—Rev. 0 to Rev. A Routing Section ............................................................................... 49 Changed S/PDIF Transceiver and Receiver Maximum Audio Change to Serial Input Ports Section ........................................... 61 Sample Rate from 192 kHz to 96 kHz; Table 9 and Table 10 ....... 9 Changes to Asynchronous Sample Rate Converters Section .... 68 Changes to S/PDIF Interface Section and S/PDIF Receiver 10/2013—Revision 0: Initial Version Section .............................................................................................. 69 Rev. D | Page 4 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 FUNCTIONAL BLOCK DIAGRAM—ADAU1450 SPI/I2C* SPI/I2C* SELFBOOT MP13 TO MP0 AUXADC5 TOAUXADC0 PLLFILT XTALIN/MCLK XTALOUT ADAU1450 VDRIVE REGULATOR I2C/SPI I2C/SPI GPIO/ CLOCK THD_P TEMPERATURE SLAVE MASTER AUX ADC PLL OSCILLATOR CLKOUT THD_M SENSOR INPUT AUDIO OUTPUT AUDIO ROUTING MATRIX ROUTING MATRIX 147.456MHz PROGRAMMABLE AUDIO PROCESSING CORE RAM, ROM, WATCHDOG, MEMORY PARITY CHECK SDATA_IN3 TO SDATA_IN0 SERIAL DATA SDATA_OUT3 TO SDATA_OUT0 (48-CHANNEL INPUT PORTS SERIAL DATA (48-CHANNEL DIGITAL AUDIO (×4) OUTPUT PORTS DIGITAL AUDIO INPUTS) (×4) OUTPUTS) DIGITAL MIC INPUT BCLK_IN3 TO BCLK_IN0/ INPUT OUTPUT BCLK_OUT3 TO BCLK_OUT0 LRCLK_IN3 TO LRCLK_IN0 CLOCK DEJITTER AND CLOCK LRCLK_OUT3 TO LRCLK_OUT0 (INPUT CLOCK PAIRS) DO(M×A4)INS CLOCK GENERATOR DO(M×A4)INS (OUTPUT CLOCK PAIRS) *SSCPLI/KI2,C S ICNLC,L MUODESSI, ATHDED RF1O, LSLSO, WANINDG A PDIDNR F0U PNICNTSI.ONS: SS_M, MOSI_M, SCL_M, SCLK_M, SDA_M, MISO_M, MISO, SDA, 11486-101 Figure 2. Rev. D | Page 5 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet GENERAL DESCRIPTION The ADAU1452/ADAU1451/ADAU1450 are automotive qualified The power efficient DSP core executes full programs, consumes audio processors that far exceed the digital signal processing only a few hundred milliwatts (mW) of power, and can run at a capabilities of earlier SigmaDSP® devices. The restructured maximum program load while consuming less than a watt, even hardware architecture is optimized for efficient audio processing. in worst case temperatures exceeding 100°C. This relatively low The audio processing algorithms are realized in sample-by-sample power consumption and small footprint make the ADAU1452/ and block-by-block paradigms that can both be executed ADAU1451/ADAU1450 ideal replacements for large, general- simultaneously in a signal processing flow created using the purpose DSPs that consume more power at the same processing graphical programming tool, SigmaStudio™. The restructured load. Note that the ADAU1452K grade device is only specified digital signal processor (DSP) core architecture enables some for the 0°C to 70°C temperature range but is otherwise identical types of audio processing algorithms to be executed using to the ADAU1452. In this data sheet, references to the ADAU1452 significantly fewer instructions than were required on previous refer to the ADAU1452 and the ADAU1452K, except where noted. SigmaDSP generations, leading to vastly improved code DIFFERENCES BETWEEN THE ADAU1452, efficiency. ADAU1452-150, ADAU1452K, ADAU1451, AND The 1.2 V, 32-bit DSP core can run at frequencies of up to ADAU1450 294.912 MHz and execute up to 6144 instructions per sample at the standard sample rate of 48 kHz. However, in addition to This data sheet simplifies the ordering number to the device industry-standard rates, a wide range of sample rates are available. models listed in Table 1. The integer PLL and flexible clock generator hardware can generate Table 1. Product Part Number Conventions up to 15 audio sample rates simultaneously. These clock generators, Model Number Device Number along with the on-board asynchronous sample rate converters ADAU1452WBCPZ ADAU1452 (ASRCs) and a flexible hardware audio routing matrix, make the ADAU1452WBCPZ150 ADAU1452-150 ADAU1452/ADAU1451/ADAU1450 ideal audio hubs that greatly ADAU1451WBCPZ ADAU1451 simplify the design of complex multirate audio systems. ADAU1450WBCPZ ADAU1450 The ADAU1452/ADAU1451/ADAU1450 interface with a wide ADAU1452KCPZ ADAU1452K range of analog-to-digital converters (ADCs), digital-to-analog The five variants of this device are differentiated by memory, converters (DACs), digital audio devices, amplifiers, and DSP core frequency, availability of S/PDIF interfaces, ASRC control circuitry, due to their highly configurable serial ports, configuration, and temperature range. A detailed summary of S/PDIF interfaces (on the ADAU1452 and ADAU1451), and the differences is listed in Table 2. multipurpose input/output pins. The devices can also directly interface with pulse density modulation (PDM) output The ADAU1452, ADAU1452-150, and the ADAU1452K are microelectromechanical (MEMS) microphones, due to referred to as the ADAU1452 throughout this data sheet. Any integrated decimation filters specifically designed for that exceptions are noted in the relevant sections of the data sheet. purpose. Because the ADAU1450 does not contain an S/PDIF receiver or Independent slave and master I2C/serial peripheral interface (SPI) transmitter, the SPDIFIN and SPDIFOUT pins are nonfunctional. control ports allow the ADAU1452/ADAU1451/ADAU1450 not Additionally, the settings of any registers related to the S/PDIF only to be programmed and configured by an external master input or output in the ADAU1450 do not have any effect on the device, but also to act as masters that can program and configure operation of the device. external slave devices directly. This flexibility, combined with self Because the ADAU1450 does not contain ASRCs, the settings of boot functionality, enables the design of standalone systems that any registers related to the ASRCs in the ADAU1450 do not do not require any external input to operate. have any effect on the operation of the device. Table 2. Product Selection Table DSP Core Data Memory Program Memory Frequency S/PDIF Input and Temperature Device Number (kWords) (kWords) (MHz) Output ASRC Configuration Range (°C) ADAU1452 40 8 294.912 Available 16 channels (8 rates × −40 to +105 2 channels per rate) ADAU1452-150 40 8 147.456 Available 16 channels (8 rates × −40 to +105 2 channels per rate) ADAU1452K 40 8 294.912 Available 16 channels (8 rates × 0 to +70 2 channels per rate) ADAU1451 16 8 294.912 Available 16 channels (8 rates × −40 to +105 2 channels per rate) ADAU1450 8 8 147.456 MHz Not available No ASRCs included −40 to +105 Rev. D | Page 6 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 SPECIFICATIONS AVDD = 3.3 V ± 10%, DVDD = 1.2 V ± 5%, PVDD = 3.3 V ± 10%, IOVDD = 1.8 V − 5% to 3.3 V + 10%, T = 25°C, master clock input = A 12.288 MHz, core clock (f ) = 294.912 MHz, I/O pins set to low drive setting, unless otherwise noted. CORE Table 3. Parameter Min Typ Max Unit Test Conditions/Comments POWER Supply Voltage Analog Voltage (AVDD Pin) 2.97 3.3 3.63 V Supply for analog circuitry, including auxiliary ADC Digital Voltage (DVDD Pin) 1.14 1.2 1.26 V Supply for digital circuitry, including the DSP core, ASRCs, and signal routing PLL Voltage (PVDD Pin) 2.97 3.3 3.63 V Supply for phase-locked loop (PLL) circuitry I/O Supply Voltage (IOVDD Pin) 1.71 3.3 3.63 V Supply for input/output circuitry, including pads and level shifters Supply Current Analog Current (AVDD Pin) 1.5 1.73 2 mA Idle State 0 5 40 µA Power applied, chip not programmed Reset State 1.9 6.5 40 µA Power applied, RESET held low PLL Current (PVDD Pin) 9.5 10 13 mA 12.288 MHz MCLK with default PLL settings Idle State 0 7.3 40 µA Power applied, PLL not configured Reset State 3.9 8.5 40 µA Power applied, RESET held low I/O Current (IOVDD Pin) Dependent on the number of active serial ports, clock pins, and characteristics of external loads Operation State 53 mA IOVDD = 3.3 V; all serial ports are clock masters 22 mA IOVDD = 1.8 V; all serial ports are clock masters Power-Down State 0.3 2.5 mA IOVDD = 1.8 V − 5% to 3.3 V + 10% Digital Current (DVDD Pin) Operation State, ADAU1452/ADAU1452K Maximum Program 350 415 mA Typical Program 100 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active Minimal Program 85 mA Test program includes 2-channel I/O, 10-band EQ per channel Operation State, ADAU1452-150 Maximum Program 125 250 mA f = 147.456 MHz CORE Typical Program 75 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active, f = 147.456 MHz CORE Operation State, ADAU1451 Maximum Program 350 415 mA Typical Program 100 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active Minimal Program 85 mA Test program includes 2-channel I/O, 10-band EQ per channel Operation State, ADAU1450 Maximum Program 125 250 mA f = 147.456 MHz CORE Typical Program 65 mA Test program includes 16-channel I/O, 10-band EQ per channel, f = 147.456 MHz CORE Minimal Program 55 mA Test program includes 2-channel I/O, 10-band EQ per channel, f = 147.456 MHz CORE Idle State 20 95 mA Power applied, DSP not enabled Reset State 20 95 mA Power applied, RESET held low ASYNCHRONOUS SAMPLE RATE CONVERTERS Dynamic Range 139 dB A-weighted, 20 Hz to 20 kHz I/O Sample Rate 6 192 kHz I/O Sample Rate Ratio 1:8 7.75:1 THD + N −120 dB Rev. D | Page 7 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments CRYSTAL OSCILLATOR Transconductance 8.3 10.6 13.4 mS REGULATOR DVDD Voltage 1.14 1.2 V Regulator maintains typical output voltage up to a maximum 800 mA load; IOVDD = 1.8 V − 5% to 3.3 V + 10% 1.26 V Regulator maximum output voltage with a minimum 1 mA load; IOVDD = 1.8 V − 5% to 3.3 V + 10% Rev. D | Page 8 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 AVDD = 3.3 V ± 10%, DVDD = 1.2 V ± 5%, PVDD = 3.3 V ± 10%, IOVDD = 1.8 V − 5% to 3.3 V + 10%, T = −40°C to +105°C, A master clock input = 12.288 MHz, core clock (f ) = 294.912 MHz, I/O pins set to low drive setting, unless otherwise noted. CORE Table 4. Parameter Min Typ Max Unit Test Conditions/Comments POWER Supply Voltage Analog Voltage (AVDD Pin) 2.97 3.3 3.63 V Supply for analog circuitry, including auxiliary ADC Digital Voltage (DVDD Pin) 1.14 1.2 1.26 V Supply for digital circuitry, including the DSP core, ASRCs, and signal routing PLL Voltage (PVDD Pin) 2.97 3.3 3.63 V Supply for PLL circuitry IOVDD Voltage (IOVDD Pin) 1.71 3.3 3.63 V Supply for input/output circuitry, including pads and level shifters Supply Current Analog Current (AVDD Pin) 1.44 1.72 2 mA Idle State 0 6.3 40 µA Reset State 0.26 7.1 40 µA PLL Current (PVDD Pin) 6 10.9 15 mA 12.288 MHz master clock; default PLL settings Idle State 0 7.8 40 µA Power applied, PLL not configured Reset State 1.2 9.3 40 µA Power applied, RESET held low I/O Current (IOVDD Pin) Dependent on the number of active serial ports, clock pins, and characteristics of external loads Operation State 47 mA IOVDD = 3.3 V; all serial ports are clock masters 15 mA IOVDD = 1.8 V; all serial ports are clock masters Power-Down State 1.3 2.2 mA IOVDD = 1.8 V − 5% to 3.3 V + 10% Digital Current (DVDD) Operation State, ADAU1452 Maximum Program 500 690 mA Typical Program 200 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active Minimal Program 160 mA Test program includes 2-channel I/O, 10-band EQ per channel Operation State, ADAU1452K T = 0°C to 70°C A Maximum Program 500 690 mA Typical Program 200 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active Minimal Program 160 mA Test program includes 2-channel I/O, 10-band EQ per channel Operation State, ADAU1452-150 Maximum Program 270 635 mA f = 147.456 MHz CORE Typical Program 125 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active, f = 147.456 MHz CORE Operation State, T = −40°C to +85°C A ADAU1452-150 Maximum Program 215 508 mA f = 147.456 MHz CORE Typical Program 100 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active, f = 147.456 MHz CORE Operation State, ADAU1451 Maximum Program 500 690 mA Typical Program 200 mA Test program includes 16-channel I/O, 10-band EQ per channel, all ASRCs active Minimal Program 160 mA Test program includes 2-channel I/O, 10-band EQ per channel Operation State, ADAU1450 Maximum Program 270 635 mA f = 147.456 MHz CORE Typical Program 110 mA Test program includes 16-channel I/O, 10-band EQ per channel, f = 147.456 MHz CORE Rev. D | Page 9 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments Minimal Program 90 mA Test program includes 2-channel I/O, 10-band EQ per channel, f = 147.456 MHz CORE Idle State 315 635 mA Reset State 315 635 mA Idle State, ADAU1452-150 250 508 mA T = −40°C to +85°C A Reset State, ADAU1452-150 250 508 mA T = −40°C to +85°C A ASYNCHRONOUS SAMPLE RATE CONVERTERS Dynamic Range 139 dB A-weighted, 20 Hz to 20 kHz I/O Sample Rate 6 192 kHz I/O Sample Rate Ratio 1:8 7.75:1 THD + N −120 dB CRYSTAL OSCILLATOR Transconductance 8.1 10.6 14.6 mS REGULATOR DVDD Voltage 1.14 1.2 V Regulator maintains typical output voltage up to a maximum 800 mA load; IOVDD = 1.8 V − 5% to 3.3 V + 10% 1.26 V Regulator maximum output voltage with a minimum 1 mA load; IOVDD = 1.8 V − 5% to 3.3 V + 10% Rev. D | Page 10 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 ELECTRICAL CHARACTERISTICS Digital Input/Output Table 5. Parameter Min Typ Max Unit Test Conditions/Comments DIGITAL INPUT Input Voltage High Level (VIH)1 0.7 × V IOVDD Low Level (VIL) 1 0.3 × V IOVDD Input Leakage High Level (IIH) −2 +2 µA Digital input pins with pull-up resistor 2 12 µA Digital input pins with pull-down resistor −2 +2 µA Digital input pins with no pull resistor 0 8 µA MCLK 80 120 µA SPDIFIN Low Level (IIL) at 0 V −12 −2 µA Digital input pins with pull-up resistor −2 +2 µA Digital input pins with pull-down resistor −2 +2 µA Digital input pins with no pull resistor −8 0 µA MCLK −120 −77 µA SPDIFIN Input Capacitance (CI) 2 pF Guaranteed by design DIGITAL OUTPUT Output Voltage High Level (VOH) 0.85 × V IOH = 1 mA IOVDD Low Level (VOL) 0.1 × V IOL = 1 mA IOVDD Digital Output Pins, Output Drive The digital output pins are driving low impedance PCB traces to a high impedance digital input buffer IOVDD = 1.8 V Drive Strength Setting Lowest 1 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly Low 2 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly High 3 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly Highest 5 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly IOVDD = 3.3 V Drive Strength Setting Lowest 2 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly Low 5 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly High 10 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly Highest 15 mA The digital output pins are not designed for static current draw; do not use these pins to drive LEDs directly I2C Sink Current, SDA, SDA_M, and 8 mA SDA slave and master ports and SCL master port; guaranteed by SCL_M Pins design, not characterized I2C PIN SINK RESISTANCE, R-ON SDA Slave and Master Ports and SCL master port Drive Strength Register Setting SDA, SDA_M, and SCL_M pins Lowest (0b00) 108 Ω Guaranteed by design, not characterized Low (0b01) 54 Ω Guaranteed by design, not characterized High (0b10) 27 Ω Guaranteed by design, not characterized Highest (0b11) 18 Ω Guaranteed by design, not characterized 1 Digital input pins except SPDIFIN, which is not a standard digital input. Rev. D | Page 11 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Auxiliary ADC T = −40°C to +105°C, DVDD = 1.2 V ± 5%, AVDD = 3.3 V ± 10%, IOVDD = 1.8 V − 5% to 3.3 V + 10%, unless otherwise noted. A Table 6. Parameter Min Typ Max Unit RESOLUTION 10 Bits FULL-SCALE ANALOG INPUT AVDD V NONLINEARITY Integrated Nonlinearity (INL) −2 +2 LSB Differential Nonlinearity (DNL) −2 +2 LSB GAIN ERROR −2 +2 LSB INPUT IMPEDANCE 200 kΩ SAMPLE RATE f /6144 Hz CORE SAMPLE RATE, ADAU1452-150 and ADAU1450 f /3072 Hz CORE TIMING SPECIFICATIONS Master Clock Input T = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%, unless otherwise noted. A Table 7. Parameter Min Max Unit Description MASTER CLOCK INPUT (MCLK) f 2.375 36 MHz MCLK frequency MCLK t 27.8 421 ns MCLK period MCLK t 25 75 % MCLK duty cycle MCLKD t 0.25 × t 0.75 × t ns MCLK width high MCLKH MCLK MCLK t 0.25 × t 0.75 × t ns MCLK width low MCLKL MCLK MCLK CLKOUT Jitter 12 106 ps Cycle-to-cycle rms average CORE CLOCK f CORE ADAU1452/ADAU1452K and ADAU1451 152 294.912 MHz System (DSP core) clock frequency; PLL feedback divider ranges from 64 to 108 ADAU1452-150 and ADAU1450 76 147.456 MHz System (DSP core) clock frequency; PLL feedback divider ranges from 64 to 108 t CORE ADAU1452 and ADAU1451 3.39 ns System (DSP core) clock period ADAU1452-150 and ADAU1450 6.78 ns System (DSP core) clock period tMCLK MCLK tMCLKH tMCLKL 11486-003 Figure 3. Master Clock Input Timing Specifications Rev. D | Page 12 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Reset T = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%. A Table 8. Parameter Min Max Unit Description RESET t 10 ns Reset pulse width low WRST tWRST RESET 11486-004 Figure 4. Reset Timing Specification Rev. D | Page 13 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Serial Ports T = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%, unless otherwise noted. BCLK in Table 9 refers to A BCLK_OUT3 to BCLK_OUT0 and BCLK_IN3 to BCLK_IN0. LRCLK refers to LRCLK_OUT3 to LRCLK_OUT0 and LRCLK_IN3 to LRCKL_IN0. Table 9. Parameter Min Max Unit Description SERIAL PORT f 192 kHz LRCLK frequency. LRCLK t 5.21 µs LRCLK period. LRCLK f 24.576 MHz BCLK frequency, sample rate ranging from 6 kHz to 192 kHz. BCLK t 40.7 ns BCLK period. BCLK t 10 ns BCLK low pulse width, slave mode; BCLK frequency = 24.576 MHz; BCLK period = 40.6 ns. BIL t 14.5 ns BCLK high pulse width, slave mode; BCLK frequency = 24.576 MHz; BCLK period = 40.6 ns. BIH t 20 ns LRCLK setup to BCLK_INx input rising edge, slave mode; LRCLK frequency = 192 kHz. LIS t 5 ns LRCLK hold from BCLK_INx input rising edge, slave mode; LRCLK frequency = 192 kHz. LIH t 5 ns SDATA_INx setup to BCLK_INx input rising edge. SIS t 5 ns SDATA_INx hold from BCLK_INx input rising edge. SIH t 10 ns BCLK_OUTx output falling edge to LRCLK_OUTx output timing skew, slave. TS t 35 ns SDATA_OUTx delay in slave mode from BCLK_OUTx output falling edge; serial outputs function in slave SODS mode at all valid sample rates, provided that the external circuit design provides sufficient electrical signal integrity. It is not recommended that slave mode of operation be used when operating at IOVDD = 1.8 V nominal at BCLK frequencies over 3.072 MHz. 35 ns IOVDD = 3.3 V ± 10%; slew setting = 0b10; drive strength set to 0b00. 16 ns IOVDD = 3.3 V ± 10%; slew setting = 0b10; drive strength set to 0b01. 9 ns IOVDD = 3.3 V ± 10%; slew setting = 0b10; drive strength set to 0b10. 8 ns IOVDD = 3.3 V ± 10%; slew setting = 0b10; drive strength set to 0b11. t 10 ns SDATA_OUTx delay in master mode from BCLK_OUTx output falling edge. SODM t 5 ns BCLK falling edge to LRCLK timing skew, master. TM tBIH tBCLK tLIH BCLK_INx tBIL tTM tLIS LRCLK_INx tLRCLK tSIS SDATA_INx (SERIAL_BYTE_x_0[4:3L]E, (FDTA JTUAS_TFIMFITE)D = M0bO0D1E) MSB MSB – 1 tSIH SDATA_INx tSIS I2S MODE (SERIAL_BYTE_x_0[4:3], (DATA_FMT) = 0b00) MSB SDATA_INx tSIH (SERIAL_BYTE_x_0R[4IG:3H],T ( DJAUTSATI_FFIMEDT )M =O 0DbE10S tSIS tSIS SERIAL_BYTE_x_0[4:3], (DATA_FMT) = 0b1O1R) MSBtSIH LSBtSIH 11486-005 Figure 5. Serial Input Port Timing Specifications Rev. D | Page 14 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 tBCLK tBIH tTS BCLK_OUTx tBIL LRCLK_OUTx tLRCLK SDATA_OUTx LEFT JUSTIFIED MODE MSB MSB–1 (SERIAL_BYTE_x_0 [4:3](DATA_FMT) = 0b01) SDATA_OUTx I2S MODE MSB (SERIAL_BYTE_x_0 [4:3](DATA_FMT) = 0b00) tSODS tSODM SDATA_OUTx ALL MODES SDATA_OUTx RIGHT JUSTIFIED MODES (SSEERRIIAALL__BBYYTTEE__xx__00 [[44::33]]((DDAATTAA__FFMMTT)) == 00bbO111R0) MSB LSB 11486-006 Figure 6. Serial Output Port Timing Specifications Multipurpose Pins T = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%. A Table 10. Parameter Min Max Unit Description MULTIPURPOSE PINS (MPx) f 1 24.576 MHz MPx maximum switching rate when pin is configured as a general-purpose MP input or general-purpose output t 1 MPIL ADAU1452, 10/t 6144/t sec MPx pin input latency until high/low value is read by core; the duration in the CORE CORE ADAU1452K, and Max column is equal to the period of one audio sample when the DSP is ADAU1451 processing 6144 instructions per sample ADAU1452-150, 10/t 3072/t sec MPx pin input latency until high/low value is read by core; the duration in the CORE CORE ADAU1450 max column is equal to the period of one audio sample when the DSP is processing 3072 instructions per sample 1 Guaranteed by design. S/PDIF Transmitter T = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%. A Table 11. Parameter Min Max Unit Description S/PDIF Transmitter Audio Sample Rate 18 96 kHz Audio sample rate of data output from S/PDIF transmitter S/PDIF Receiver T = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%. A Table 12. Parameter Min Max Unit Description S/PDIF Receiver Audio Sample Rate 18 96 kHz Audio sample rate of data input to S/PDIF receiver Rev. D | Page 15 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet I2C Interface—Slave T = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%, default drive strength (f ) = 400 kHz. A SCL Table 13. Parameter Min Max Unit Description I2C SLAVE PORT f 400 kHz SCL clock frequency SCL t 0.6 µs SCL pulse width high SCLH t 1.3 µs SCL pulse width low SCLL t 0.6 µs Start and repeated start condition setup time SCS t 0.6 µs Start condition hold time SCH t 100 ns Data setup time DS t 0.9 µs Data hold time DH t 300 ns SCL rise time SCLR t 300 ns SCL fall time SCLF t 300 ns SDA rise time SDR t 300 ns SDA fall time SDF t 1.3 µs Bus-free time between stop and start BFT t 0.6 µs Stop condition setup time SUSTO tSCH STOP START tSDR tDS tSCH SDA tSCLH tSDF tBFT tSCLR SCL tSCLL tDH tSCLF tSCS tSUSTO 11486-007 Figure 7. I2C Slave Port Timing Specifications Rev. D | Page 16 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 I2C Interface—Master T = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%. A Table 14 Parameter Min Max Unit Description I2C MASTER PORT f 400 kHz SCL clock frequency SCL t 0.6 µs SCL pulse width high SCLH t 1.3 µs SCL pulse width low SCLL t 0.6 µs Start and repeated start condition setup time SCS t 0.6 µs Start condition hold time SCH t 100 ns Data setup time DS t 0.9 µs Data hold time DH t 300 ns SCL rise time SCLR t 300 ns SCL fall time SCLF t 300 ns SDA rise time SDR t 300 ns SDA fall time SDF t 1.3 µs Bus-free time between stop and start BFT t 0.6 µs Stop condition setup time SUSTO tSCH STOP START tSDR tDS tSCH SDA_M tSCLH tSDF tBFT tSCLR SCL_M tSCLL tDH tSCLF tSCS tSUSTO 11486-008 Figure 8. I2C Master Port Timing Specifications Rev. D | Page 17 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet SPI Interface—Slave T = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%. A Table 15. Parameter Min Max Unit Description SPI SLAVE PORT f 22 MHz SCLK write frequency SCLKWRITE f 22 MHz SCLK read frequency SCLKREAD t 6 ns SCLK pulse width low, SCLK = 22 MHz SCLKPWL t 21 ns SCLK pulse width high, SCLK = 22 MHz SCLKPWH t 1 ns SS setup to SCLK rising edge SSS t 2 ns SS hold from SCLK rising edge SSH t 10 ns SS pulse width high SSPWH t 10 ns SS pulse width low; minimum low pulse width for SS when SSPWL entering SPI mode by toggling the SS pin three times t 1 ns MOSI setup to SCLK rising edge MOSIS t 2 ns MOSI hold from SCLK rising edge MOSIH t 39 ns MISO valid output delay from SCLK falling edge MISOD tSSS tSSH tSSPWH tSCLKPWL SS tSCLKPWH SCLK MOSI tMOSIH tMOSIS MISO tMISOD 11486-009 Figure 9. SPI Slave Port Timing Specifications Rev. D | Page 18 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 SPI Interface—Master T = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%. A Table 16. Parameter Min Max Unit Description SPI MASTER PORT Timing Requirements t 15 ns MISO_M data input valid to SCLK_M edge (data input setup time) SSPIDM t 5 ns SCLK_M last sampling edge to data input not valid (data input hold time) HSPIDM Switching Characteristics t 41.7 ns SPI master clock cycle period SPICLKM f 24 MHz SPI master clock frequency SCLK_M t 17 ns SCLK_M high period (f = 24 MHz) SPICHM SCLK_M t 17 ns SCLK_M low period (f = 24 MHz) SPICLM SCLK_M t 16.9 ns SCLK_M edge to data out valid (data out delay time) (f = 24 MHz) DDSPIDM SCLK_M t 21 ns SCLK_M edge to data out not valid (data out hold time) (f = 24 MHz) HDSPIDM SCLK_M t 36 ns SS_M (SPI device select) low to first SCLK_M edge (f = 24 MHz) SDSCIM SCLK_M t 95 ns Last SCLK_M edge to SS_M high (f = 24 MHz) HDSM SCLK_M SS_M (OUTPUT) tSDSCIM tSPICHM tSPICLM tSPICLKM tHDSM SCLK_M (CP = 0) (OUTPUT) tSPICLM tSPICHM SCLK_M (CP = 1) (OUTPUT) tDDSPIDM tHDSPIDM MOSI_M (OUTPUT) MSB LSB tSSPIDM tSSPIDM CPHASE = 1 tHSPIDM tHSPIDM MISO_M MSB (INPUT) VALID LSB VALID tDDSPIDM tHDSPIDM MOSI_M (OUTPUT) MSB LSB CPHASE = 0 tSSPIDM tHSPIDM M(IINSPOU_TM) MSB VALID LSB VALID 11486-010 Figure 10. SPI Master Port Timing Specifications Rev. D | Page 19 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet PDM Inputs T = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 5% to 3.3 V + 10%. PDM data is latched on both edges of the clock (see Figure A 11). Table 17. Parameter t t Unit Description MIN MAX Timing Requirements t 10 ns Data setup time SETUP t 5 ns Data hold time HOLD PDM_CLK tSETUP tHOLD PDM_DAT R L R L 11486-011 Figure 11. PDM Timing Diagram Rev. D | Page 20 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 ABSOLUTE MAXIMUM RATINGS in a typical use case. Table 24 and Table 25 represent power Table 18. consumption for the ADAU1452-150 under the stated conditions. Parameter Rating DVDD to Ground 0 V to 1.4 V Table 20. Worst Case Maximum Power Dissipation AVDD to Ground 0 V to 4.0 V Test Conditions/ IOVDD to Ground 0 V to 4.0 V Parameter Value Unit Comments PVDD to Ground 0 V to 4.0 V AVDD, DVDD, 960 mW Ambient temperature = 105°C; Digital Inputs DGND − 0.3 V to PVDD During all supplies at maximum; full IOVDD + 0.3 V Operation DSP program using most power intensive calculations; Maximum Ambient Temperature Range measurement does not include W Grade −40°C to +105°C IOVDD K Grade 0°C to +70°C Reset All 570 mW Ambient temperature = 105°C; Maximum Junction Temperature 125°C Supplies all supplies at maximum; reset Storage Temperature Range −65°C to +150°C mode enabled; measurement does not include IOVDD Soldering (10 sec) 300°C Table 21. ADAU1452 and ADAU1452K Typical Power Stresses at or above those listed under Absolute Maximum Dissipation Estimates Ratings may cause permanent damage to the product. This is a Ambient stress rating only; functional operation of the product at these Temperature, T (°C) Full Program (mW) Typical (mW) or any other conditions above those indicated in the operational A 25 420 250 section of this specification is not implied. Operation beyond 85 700 420 the maximum operating conditions for extended periods may 105 885 530 affect product reliability. THERMAL CHARACTERISTICS Table 22. ADAU1451 Typical Power Dissipation Estimates T (°C) Full Program (mW) Typical (mW) θ represents the junction-to-ambient thermal resistance; θ A JA JC represents the junction-to-case thermal resistance. All charac- 25 420 250 teristics are for a 4-layer JEDEC board. The exposed pad has 85 700 420 49 vias that are arranged in a 7 × 7 grid. 105 885 530 Table 19. Thermal Resistance Table 23. ADAU1450 Typical Power Dissipation Estimates Package Type θJA θJC Unit TA (°C) Full Program (mW) Typical (mW) 72-Lead LFCSP 23.38 3.3 °C/W 25 170 100 85 385 230 MAXIMUM POWER DISSIPATION 105 480 290 The characteristics listed in Table 20 show the absolute worst Table 24. Typical ADAU1452-150 Power Dissipation case power dissipation. These tests were conducted at an ambient Estimates, Nominal Device, Includes IOVDD and All temperature of 105°C, with a completely full DSP program that Voltages + 5% executes an endless loop of the most power intensive core calculations, and with all power supplies at their maximum TA (°C) Full DSP Program (mW) Typical DSP Program(mW) values. 25 195 160 85 235 200 The conditions described in Table 20 are intended as a stress test 105 265 230 only and are not representative of realistic device operation in a real-world application. In a system where the operating conditions and limits outlined in the Specifications section of this data sheet are not exceeded, and where the device is mounted to a printed circuit board (PCB) that follows the design recom- mendations in the PCB Design Considerations section of this data sheet, the values that are listed represent the total power consumption of the device. In actual applications, the power consumption of the device is far lower. Table 21, Table 22, and Table 23 show more realistic estimates for power consumption Rev. D | Page 21 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Table 25. Typical ADAU1452-150 Power Dissipation ESD CAUTION Estimates, All Silicon Skews, Includes IOVDD and All Voltages + 5% T (°C) Full DSP Program (mW) Typical DSP Program (mW) A 25 225 190 85 360 325 105 450 415 Rev. D | Page 22 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 3 2 1 0 1 1 1 1 P P P P M M M M N3N3/3N2N2/2 N1N1/1N0N0/0 DGNDDVDDSDATA_ILRCLK_IBCLK_INSDATA_ILRCLK_IBCLK_INTHD_PTHD_MSDATA_ILRCLK_IBCLK_INSDATA_ILRCLK_IBCLK_INIOVDDDGND 210987654321098765 777666666666655555 DGND 1 54 DGND IOVDD 2 53 DVDD VDRIVE 3 52 SDATA_OUT3 SPDIFIN 4 51 BCLK_OUT3 SPDIFOUT 5 50 LRCLK_OUT3/MP9 AGND 6 49 SDATA_OUT2 AVDD 7 48 BCLK_OUT2 AUXADC0 8 ADAU1452/ 47 LRCLK_OUT2/MP8 AUXADC1 9 ADAU1451/ 46 MP7 AUXADC2 10 ADAU1450 45 MP6 AUXADC3 11 44 SDATA_OUT1 AUXADC4 12 TOP VIEW 43 BCLK_OUT1 AUXADC5 13 42 LRCLK_OUT1/MP5 PGND 14 41 SDATA_OUT0 PVDD 15 40 BCLK_OUT0 PLLFILT16 39 LRCLK_OUT0/MP4 DGND 17 38 IOVDD IOVDD18 37 DGND 901234567890123456 122222222223333333 DGNDDVDDXTALIN/MCLKXTALOUTCLKOUTRESETDGNDSS_M/MP0MOSI_M/MP1M/SCLK_M/MP2M/MISO_M/MP3MISO/SDASCLK/SCLMOSI/ADDR1SS/ADDR0SELFBOOTDVDDDGND L_A_ CD SS NOTES 1. THE EXPOSED PAD MUST BE GROUNDED BY SOLDERING IT TO A COPPER SQUARE OATOLFL AE LQ DAUEYIDVEIARCLSAE TONEFTD TS CHIZOEEP B POOENAR RT GHDRE, OC POUCNNBDN. EILDCAETYNEETDRIC BWAYLI TV CHIAOINSP ,TP AHENERD PS TCQHBUE.AYR MESU SMTU BSET CEOXINSNTE OCNTED 11486-002 Figure 12. Pin Configuration Table 26. Pin Function Descriptions Internal Pull Pin No. Mnemonic Resistor Description 1 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. 2 IOVDD None Input/Output Supply, 1.8 V − 5% to 3.3 V + 10%. Bypass this pin with decoupling capacitors to Pin 1 (DGND). 3 VDRIVE None Positive Negative Positive (PNP) Bipolar Junction Transistor-Base Drive Bias Pin for the Digital Supply Regulator. Connect VDRIVE to the base of an external PNP pass transistor. If an external supply is provided directly to DVDD, connect the VDRIVE pin to ground (DGND), or it can be left floating. 4 SPDIFIN None Input to the Integrated Sony/Philips Digital Interface Format Receiver. Leave this pin floating when not in use. This pin is internally biased to IOVDD/2. This pin is nonfunctional on the ADAU1450 and must be left disconnected. If terminations on all pins is required, this pin can be terminated with a 100 nF capacitor to ground. If a lower cost method is desired, this pin can be grounded to DGND. This pin draws approximately 0.1 mA when grounded. 5 SPDIFOUT Configurable Output from the Integrated Sony/Philips Digital Interface Format Transmitter. Disconnect this pin when not in use. This pin is internally biased to IOVDD/2. This pin is nonfunctional on the ADAU1450 and must be left disconnected. 6 AGND None Analog Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. 7 AVDD None Analog (Auxiliary ADC) Supply. Must be 3.3 V ± 10%. Bypass this pin with decoupling capacitors to Pin 6 (AGND). Rev. D | Page 23 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Internal Pull Pin No. Mnemonic Resistor Description 8 AUXADC0 None Auxiliary ADC Input Channel 0. This pin reads an analog input signal and uses its value in the DSP program. This pin can be left floating when not in use. If terminations on all pins are required, this pin can be grounded to AGND. 9 AUXADC1 None Auxiliary ADC Input Channel 1. This pin reads an analog input signal and uses its value in the DSP program. This pin can be left floating when not in use. If terminations on all pins are required, this pin can be grounded to AGND. 10 AUXADC2 None Auxiliary ADC Input Channel 2. This pin reads an analog input signal and uses its value in the DSP program. This pin can be left floating when not in use. If terminations on all pins are required, this pin can be grounded to AGND. 11 AUXADC3 None Auxiliary ADC Input Channel 3. This pin reads an analog input signal and uses its value in the DSP program. This pin can be left floating when not in use. If terminations on all pins are required, this pin can be grounded to AGND. 12 AUXADC4 None Auxiliary ADC Input Channel 4. This pin reads an analog input signal and uses its value in the DSP program. This pin can be left floating when not in use. If terminations on all pins are required, this pin can be grounded to AGND. 13 AUXADC5 None Auxiliary ADC Input Channel 5. This pin reads an analog input signal and uses its value in the DSP program. This pin can be left floating when not in use. If terminations on all pins are required, this pin can be grounded to AGND. 14 PGND None PLL Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. 15 PVDD None PLL Supply. Must be 3.3 V ± 10%. Bypass this pin with decoupling capacitors to Pin 14 (PGND). 16 PLLFILT None PLL Filter. The voltage on the PLLFILT pin, which is internally generated, is typically between 1.65 V and 2.10 V. 17 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. 18 IOVDD None Input/Output Supply, 1.8 V − 5% to 3.3 V + 10%. Bypass this pin to Pin 17 (DGND) with decoupling capacitors. 19 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. 20 DVDD None Digital Supply. Must be 1.2 V ± 5%. This pin can be supplied externally or by using the internal regulator and external pass transistor. Bypass this pin to Pin 19 (DGND) with decoupling capacitors. 21 XTALIN/MCLK None Crystal Oscillator Input (XTALIN)/Master Clock Input to the PLL (MCLK). This pin can be supplied directly or generated by driving a crystal with the internal crystal oscillator via Pin 22 (XTALOUT). If a crystal is used, refer to the circuit shown in Figure 15. 22 XTALOUT None Crystal Oscillator Output for Driving an External Crystal. If a crystal is used, refer to the circuit shown in Figure 15. Disconnect this pin when not in use. 23 CLKOUT Configurable Master Clock Output. This pin drives a master clock signal to other ICs in the system. CLKOUT can be configured to output a clock signal with a frequency of 1×, 2×, 4×, or 8× the frequency of the divided clock signal being input to the PLL. Disconnect this pin when not in use. 24 RESET Pull-down Active Low Reset Input. A reset is triggered on a high-to-low edge and exited on a low- to-high edge. A reset event sets all RAMs and registers to their default values. 25 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. 26 SS_M/MP0 Pull-up; nominally SPI Master/Slave Select Port (SS_M)/Multipurpose, General-Purpose Input/Output 250 kΩ; can be (MP0). When in SPI master mode, this pin acts as the slave select signal to slave devices disabled by a write to on the SPI bus. The pin must go low at the beginning of a master SPI transaction and high control register at the end of a transaction. This pin has an internal pull-up resistor that is nominally 250 kΩ. When the SELFBOOT pin is held high and the RESET pin has a transition from low to high, Pin 26 sets the communications protocol for self boot operation. If this pin is left floating, the SPI communications protocol is used for self boot operation. If this pin has a 10 kΩ pull-down resistor to GND, the I2C communications protocol is used for self boot operation. When self boot operation is not used and this pin is not needed as a general- purpose input or output, leave it disconnected. 27 MOSI_M/MP1 Pull-up; can be SPI Master Data Output Port (MOSI_M)/Multipurpose, General-Purpose Input/Output disabled by a write to (MP1). When in SPI master mode, this pin sends data from the SPI master port to slave control register devices on the SPI bus. Disconnect this pin when not in use. Rev. D | Page 24 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Internal Pull Pin No. Mnemonic Resistor Description 28 SCL_M/ Pull-up; can be I2C Master Serial Clock Port (SCL_M)/SPI Master Mode Serial Clock SCLK_M/MP2 disabled by a write to (SCLK_M)/Multipurpose, General-Purpose Input/Output (MP2). When in I2C master control register mode, this pin functions as an open collector output and drives a serial clock to slave devices on the I2C bus; use a pull-up resistor to IOVDD on the line connected to this pin. When in SPI master mode, this pin drives the clock signal to slave devices on the SPI bus. Disconnect this pin when not in use. 29 SDA_M/ Pull-up; can be I2C Master Port Serial Data (SDA_M)/SPI Master Mode Data Input MISO_M/MP3 disabled by a write to (MISO_M)/Multipurpose, General-Purpose Input/Output (MP3). When in I2C master control register mode, this pin functions as a bi-directional open collector data line between the I2C master port and slave devices on the I2C bus; use a pull-up resistor to IOVDD on the line connected to this pin. When in SPI master mode, this pin receives data from slave devices on the SPI bus. Disconnect this pin when not in use. 30 MISO/SDA Pull-up; can be SPI Slave Data Output Port (MISO)/I2C Slave Serial Data Port (SDA). In SPI slave mode, disabled by a write to this pin outputs data to the master device on the SPI bus. In I2C slave mode, this pin control register functions as a bi-directional open collector data line between the I2C slave port and the master device on the I2C bus; use a pull-up resistor to IOVDD on the line connected to this pin. When this pin is not in use, connect it to IOVDD with a 10.0 kΩ pull-up resistor. 31 SCLK/SCL Pull-up; can be SPI Slave Port Serial Clock (SCLK)/I2C Slave Port Serial Clock (SCL). In SPI slave mode, this disabled by a write to pin receives the serial clock signal from the master device on the SPI bus. In I2C slave control register mode, this pin receives the serial clock signal from the master device on the I2C bus; use a pull-up resistor to IOVDD on the line connected to this pin. When this pin is not in use, connect it to IOVDD with a 10.0 kΩ pull-up resistor. 32 MOSI/ADDR1 Pull-up; can be SPI Slave Port Data Input (MOSI)/I2C Slave Port Address MSB (ADDR1). In SPI slave mode, disabled by a write to this pin receives a data signal from the master device on the SPI bus. In I2C slave mode, control register this pin acts as an input and sets the chip address of the I2C slave port, in conjunction with Pin 33 (SS/ADDR0). 33 SS/ADDR0 Pull-up, nominally 250 SPI Slave Port Slave Select (SS)/I2C Slave Port Address LSB (ADDR0). In SPI slave mode, kΩ; can be disabled this pin receives the slave select signal from the master device on the SPI bus. In I2C slave by a write to control mode, this pin acts as an input and sets the chip address of the I2C slave port in conjunction register with Pin 32 (MOSI/ADDR1). 34 SELFBOOT Pull-up Self Boot Select. This pin allows the device to perform a self boot, in which it loads its RAM and register settings from an external EEPROM. Connecting Pin 34 to logic high (IOVDD) initiates a self boot operation the next time there is a rising edge on Pin 24 (RESET). When this pin is connected to ground, no self boot operation is initiated. This pin can be connected to IOVDD or to ground either directly or pulled up or down with a 1.0 kΩ or larger resistor. 35 DVDD None Digital Supply. Must be 1.2 V ± 5%. This pin can be supplied externally or by using the internal regulator and external pass transistor. Bypass this pin to Pin 36 (DGND) with decoupling capacitors. 36 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. 37 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. 38 IOVDD None Input/Output Supply, 1.8 V − 5% to 3.3 V + 10%. Bypass this pin with decoupling capacitors to Pin 37 (DGND). 39 LRCLK_OUT0/ Configurable Frame Clock, Serial Output Port 0 (LRCLK_OUT0)/Multipurpose, General-Purpose MP4 Input/Output (MP4). This pin is bidirectional, with the direction depending on whether Serial Output Port 0 is a master or slave. Disconnect this pin when not in use. 40 BCLK_OUT0 Configurable Bit Clock, Serial Output Port 0. This pin is bidirectional, with the direction depending on whether the Serial Output Port 0 is a master or slave. Disconnect this pin when not in use. 41 SDATA_OUT0 Configurable Serial Data Output Port 0 (Channel 0 to Channel 15). Capable of 2-channel, 4-channel, 8- channel, and 16-channel modes. Disconnect this pin when not in use. 42 LRCLK_OUT1/ Configurable Frame Clock, Serial Output Port 1 (LRCLK_OUT1)/Multipurpose, General-Purpose MP5 Input/Output (MP5). This pin is bidirectional, with the direction depending on whether Serial Output Port 1 is a master or slave. Disconnect this pin when not in use. 43 BCLK_OUT1 Configurable Bit Clock, Serial Output Port 1. This pin is bidirectional, with the direction depending on whether Output Serial Port 1 is a master or slave. Disconnect this pin when not in use. 44 SDATA_OUT1 Configurable Serial Data Output Port 1 (Channel 16 to Channel 31). Capable of 2-channel, 4-channel, 8- channel, and 16-channel modes. Disconnect this pin when not in use. Rev. D | Page 25 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Internal Pull Pin No. Mnemonic Resistor Description 45 MP6 Configurable Multipurpose, General-Purpose Input/Output 6. Disconnect this pin when not in use. 46 MP7 Configurable Multipurpose, General-Purpose Input/Output 7. Disconnect this pin when not in use. 47 LRCLK_OUT2/ Configurable Frame Clock, Serial Output Port 2 (LRCLK_OUT2)/Multipurpose, General-Purpose MP8 Input/Output (MP8). This pin is bidirectional, with the direction depending on whether Serial Output Port 2 is a master or slave. Disconnect this pin when not in use. 48 BCLK_OUT2 Configurable Bit Clock, Serial Output Port 2. This pin is bidirectional, with the direction depending on whether Serial Output Port 2 is a master or slave. Disconnect this pin when not in use. 49 SDATA_OUT2 Configurable Serial Data Output Port 2 (Channel 32 to Channel 39). Capable of 2-channel, 4-channel, 8- channel, or flexible time division multiplexing (TDM) mode. Disconnect this pin when not in use. 50 LRCLK_OUT3/ Configurable Frame Clock, Serial Output Port 3 (LRCLK_OUT3)/Multipurpose, General-Purpose MP9 Input/Output (MP9). This pin is bidirectional, with the direction depending on whether Serial Output Port 3 is a master or slave. Disconnect this pin when not in use. 51 BCLK_OUT3 Configurable Bit Clock, Serial Output Port 3. This pin is bidirectional, with the direction depending on whether Serial Output Port 3 is a master or slave. Disconnect this pin when not in use. 52 SDATA_OUT3 Configurable Serial Data Output Port 3 (Channel 40 to Channel 47). Capable of 2-channel, 4-channel, 8-channel, and flexible TDM modes. Disconnect this pin when not in use. 53 DVDD None Digital Supply. Must be 1.2 V ± 5%. This pin can be supplied externally or by using the internal regulator and external pass transistor. Bypass Pin 53 with decoupling capacitors to Pin 54 (DGND). 54 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. 55 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. 56 IOVDD None Input/Output Supply, 1.8 V − 5% to 3.3 V + 10%. Bypass this pin with decoupling capacitors to Pin 55 (DGND). 57 BCLK_IN0 Configurable Bit Clock, Serial Input Port 0. This pin is bidirectional, with the direction depending on whether Serial Input Port 0 is a master or slave. Disconnect this pin when not in use. 58 LRCLK_IN0/ Configurable Frame Clock, Serial Input Port 0 (LRCLK_IN0)/Multipurpose, General-Purpose Input/Output MP10 (MP10). This pin is bidirectional, with the direction depending on whether Serial Input Port 0 is a master or slave. Disconnect this pin when not in use. 59 SDATA_IN0 Configurable Serial Data Input Port 0 (Channel 0 to Channel 15). Capable of 2-channel, 4-channel, 8- channel, or 16-channel mode. Disconnect this pin when not in use. 60 BCLK_IN1 Configurable Bit Clock, Serial Input Port 1. This pin is bidirectional, with the direction depending on whether the Serial Input Port 1 is a master or slave. Disconnect this pin when not in use. 61 LRCLK_IN1/ Configurable Frame Clock, Serial Input Port 1 (LRCLK_IN1)/Multipurpose, General-Purpose Input/Output MP11 (MP11). This pin is bidirectional, with the direction depending on whether the Serial Input Port 1 is a master or slave. Disconnect this pin when not in use. 62 SDATA_IN1 Configurable Serial Data Input Port 1 (Channels 16 to Channel 31). Capable of 2-channel, 4-channel, 8- channel, or 16-channel mode. Disconnect this pin when not in use. 63 THD_M None Thermal Diode Negative (−) Input. Connect this pin to the D− pin of an external temperature sensor IC. Disconnect this pin when not in use. 64 THD_P None Thermal Diode Positive (+) Input. Connect this pin to the D+ pin of an external temperature sensor IC. Disconnect this pin when not in use. 65 BCLK_IN2 Configurable Bit Clock, Serial Input Port 2. This pin is bidirectional, with the direction depending on whether the Serial Input Port 2 is a master or slave. Disconnect this pin when not in use. 66 LRCLK_IN2/ Configurable Frame Clock, Input Serial Port 2 (LRCLK_IN2)/Multipurpose, General-Purpose Input/Output MP12 (MP12). This pin is bidirectional, with the direction depending on whether Serial Input Port 2 is a master or slave. Disconnect this pin when not in use. 67 SDATA_IN2 Configurable Serial Data Input Port 2 (Channel 32 to Channel 39). Capable of 2-channel, 4-channel, 8- channel, or flexible TDM mode. Disconnect this pin when not in use. 68 BCLK_IN3 Configurable Bit Clock, Input Serial Port 3. This pin is bidirectional, with the direction depending on whether Input Serial Port 3 is a master or slave. Disconnect this pin when not in use. 69 LRCLK_IN3/ Configurable Frame Clock, Serial Input Port 3 (LRCLK_IN3)/Multipurpose, General-Purpose Input/Output MP13 (MP13). This pin is bidirectional, with the direction depending on whether Serial Input Port 3 is a master or slave. Disconnect this pin when not in use. 70 SDATA_IN3 Configurable Serial Data Input Port 3 (Channel 40 to Channel 47). Capable of 2-channel, 4-channel, 8- channel, or flexible TDM mode. Disconnect this pin when not in use. Rev. D | Page 26 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Internal Pull Pin No. Mnemonic Resistor Description 71 DVDD None Digital Supply. Must be 1.2 V ± 5%. This pin can be supplied externally or by using the internal regulator and external pass transistor. Bypass with decoupling capacitors to Pin 72 (DGND). 72 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common ground plane. EP Exposed Pad None The exposed pad must be grounded by soldering it to a copper square of equivalent size on the PCB. Identical copper squares must exist on all layers of the board, connected by vias, and they must be connected to a dedicated copper ground layer within the PCB. For more detailed information, see Figure 84 and Figure 85. Rev. D | Page 27 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet THEORY OF OPERATION SYSTEM BLOCK DIAGRAM CONTROL CIRCUITRY (PUSH BUTTONS, ROTARY ENCODERS, SYSTEM HOST POTENTIOMETERS) CONTROLLER (MICROCONTROLLER, MICROPROCESSOR) CRYSTAL SELF BOOT PLL RESONATOR MEMORY LOOP FILTER ADAU1452/ ADAU1451/ POWER ADAU1450 SUPPLY REGULATOR I2C/SPI I2C/SPI GPIO/ CLOCK SLAVE MASTER AUX ADC PLL OSCILLATOR TCEOMSNPETENRRSOAOLTRLUERRE TEMSPEENRSAOTRURE AUDIO SOURCES INPUT AUDIO OUTPUT AUDIO AUDIO SINKS ROUTING MATRIX ROUTING MATRIX S/PDIF OPTICAL S/PDIF S/PDIF S/PDIF OPTICAL RECEIVER RECEIVER1 TRANSMITTER1 TRANSMITTER 294.912MHz2 PROGRAMMABLE AUDIO PROCESSING CORE AUDIO AUDIO ADCS SERIAL DATA RAM, ROM, WATCHDOG, DACS INPUT PORTS MEMORY PARITY CHECK SERIAL DATA (×4) OUTPUT PORTS LPF (×4) MEMS DIGITAL DIGITAL MICROPHONES MIC INPUT 8× 2-CHANNEL AUDIO ASYNCHRONOUS SINKS SAMPLE RATE INPUT CONVERTERS1 OUTPUT DIGITAL CLOCK CLOCK AUDIO DOMAINS DOMAINS SOURCES (×4) (×4) DEJITTER AND CLOCK GENERATOR 12TTHHEE AS/DPADUIF1 4R5E0C HEAIVSE AR ,1 4T7H.E45 S6/MPHDzIF P TRROAGNRSAMMITMTAEBRL, EA NADU DTIHOE PARSOYCNECSHSRIONGNO CUOSR SEA .MPLE RATE CONVERTERS ARE NOT PRESENT ON THE ADAU1450. 11486-013 Figure 13. System Block Diagram with Example Connections to External Components OVERVIEW and listening environments, through speaker equalization, multiband compression, limiting, and third party branded The ADAU1452/ADAU1451/ADAU1450 are enhanced audio algorithms. processors with 48 channels of input and output. They include options for the hardware routing of audio signals between the The input audio routing matrix and output audio routing matrix various inputs, outputs, SigmaDSP core, and integrated sample rate allow the user to multiplex inputs from multiple sources that are converters. The SigmaDSP core features full 32-bit processing (that running at various sample rates to or from the SigmaDSP core, is, 64-bit processing in double precision mode) with an 80-bit and then to pass them on to the desired hardware outputs. This arithmetic logic unit (ALU). By using a quadruple multiply drastically reduces the complexity of signal routing and clocking accumulator (MAC) data path, the ADAU1452/ADAU1451 can issues in the audio system. The audio subsystem includes up to execute more than 1.2 billion MAC operations per second, which eight stereo ASRCs, depending on the device model; S/PDIF input allows processing power that far exceeds the predecessors in the and output (available on the ADAU1452/ ADAU1451); and serial SigmaDSP family of products. The powerful DSP core can (I2S) and TDM inputs/outputs. Any of these inputs can be routed process over 3000 double precision biquad filters or 24,000 FIR to the SigmaDSP core or to any of the ASRCs (except on the filter taps per sample at the standard 48 kHz audio sampling rate. ADAU1450, which does not have ASRCs). Similarly, the output The ADAU1452-150/ADAU1450 features half the processing signals can be taken from the SigmaDSP core, any of the ASRC power of the ADAU1452/ADAU1451. Other features, including outputs, the serial inputs, the PDM microphones, or the S/PDIF synchronous parameter loading for ensuring filter stability and receiver. This routing scheme, which can be modified at any time 100% code efficiency with the SigmaStudio tools, reduce using control registers, allows maximum system flexibility without complexity in audio system development. The SigmaStudio library requiring hardware design changes. of audio processing algorithms allows system designers to compensate for real-world limitations of speakers, amplifiers, Rev. D | Page 28 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Two serial input ports and two serial output ports can operate In SigmaStudio, the user can add signal processing cells from the as pairs in a special flexible TDM mode, allowing the user to library by dragging and dropping cells, connect them together in a independently assign byte specific locations to audio streams at flow, compile the design, and load the program and parameter files varying bit depths. This mode ensures compatibility with codecs into memory through the control port. The complicated tasks of that use similar flexible TDM streams. linking, compiling, and downloading the project are all handled automatically by the software. The DSP core is optimized for audio processing, and it can process audio at sample rates of up to 192 kHz. The program and para- Signal processing algorithms that are available in the provided meter/data RAMs can be loaded with a custom audio processing libraries include the following: signal flow, built with the SigmaStudio graphical programming • Single and double precision biquad filter software from Analog Devices, Inc. The values that are stored in • Monochannel and multichannel dynamics processors with the parameter RAM can control individual signal processing peak or rms detection blocks, such as infinite impulse response (IIR) and finite impulse • Mixer and splitter response (FIR) equalization filters, dynamics processors, audio • Tone and noise generator delays, and mixer levels. A software safeload feature allows • Fixed and variable gain transparent parameter updates and prevents clicks on the • Loudness output signals. • Delay Reliability features, such as memory parity checking and a program • Stereo enhancement counter watchdog, help ensure that the system can detect and • Dynamic bass boost recover from any errors related to memory corruption. • Noise and tone source On the ADAU1452/ADAU1451, S/PDIF signals can be routed • Level detector through an ASRC for processing in the DSP or can be sent directly • MPx pin control and conditioning to output on the multipurpose pins (MPx) for recovery of the • Fast fourier transform (FFT) and frequency domain embedded audio signal. Other components of the embedded processing algorithms signal, including status and user bits, are not lost and can be output on the MPx pins as well. The user can also independently Analog Devices continuously develops new processing algorithms program the nonaudio data that is embedded in the output and provides proprietary and third party algorithms for appli- signal of the S/PDIF transmitter. cations such as matrix decoding, bass enhancement, and surround virtualizers. The 14 MPx pins are available for providing a simple user interface without the need for an external microcontroller. These Several power saving mechanisms are available, including MPx pins are available to input external control signals and programmable pad strength for digital I/O pins, and the ability output flags or controls to other devices in the system. As to power down unused subsystems. inputs, the MPx pins can be connected to push-buttons, switches, The ADAU1452WBCPZ, ADAU1452WBCPZ-RL, rotary encoders, or other external control circuitry to control ADAU1452WBCPZ150, ADAU1452WBCPZ150RL, the internal signal processing program. When configured as ADAU1451WBCPZ, ADAU1451WBCPZ-RL, outputs, these pins can be used to drive LEDs (with a buffer), ADAU1450WBCPZ, and ADAU1450WBCPZ-RL models are output flags to a microcontroller, control other ICs, or connect fabricated on a single, monolithic, integrated circuit for operation to other external circuitry in an application. In addition to the over the −40°C to +105°C temperature range, and the device is MPx pins, six dedicated input pins (AUXADC5 to AUXADC0) housed in a 72-lead LFCSP with an exposed pad to assist in heat are connected to an auxiliary ADC for use with analog controls, dissipation. such as potentiometers or system voltages. The ADAU1452KBCPZ, and ADAU1452KBCPZ-RL models are The SigmaStudio software programs and controls the device fabricated on a single, monolithic, integrated circuit for operation through the control port. In addition to designing and tuning over the 0°C to +70°C temperature range, and the device is a signal flow, the software can configure all of the DSP registers housed in a 72-lead LFCSP with an exposed pad. in real time and download a new program and parameters into The device can be controlled in one of two operational modes, the external self boot EEPROM. The SigmaStudio graphical as follows: interface allows anyone with audio processing knowledge to design a DSP signal flow and port it to a target application without • The settings of the chip can be loaded and dynamically the need for writing line level code. The software also provides updated through the SPI/I2C port. enough flexibility and programmability to allow an experienced • The DSP can self boot from an external EEPROM in DSP programmer to have in-depth control of the design. a system with no microcontroller. Rev. D | Page 29 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet The ADAU1452WBCPZ, ADAU1452WBCPZ-RL, When a crystal is in use, the crystal oscillator circuit must ADAU1452WBCPZ150, ADAU1452WBCPZ150RL, provide a stable master clock to the XTALIN/MCLK pin by the ADAU1451WBCPZ, ADAU1451WBCPZ-RL, time the PVDD supply reaches its nominal level. The ADAU1450WBCPZ, and ADAU1450WBCPZ-RL models are XTALIN/MCLK pin is restricted from passing into the PLL qualified for use in automotive applications. circuitry until the DVDD POR signal becomes active and the PVDD to DVDD level shifter is initialized. INITIALIZATION Power-Up Sequence When all four POR circuits signal that the power-on conditions are met, a reset synchronizer circuit releases the internal digital The first step in the initialization sequence is to power up the circuitry from reset, provided the following conditions are met: device. First, apply voltage to the power pins. All power pins can be supplied simultaneously. If the power pins are not supplied • A valid MCLK signal is provided to the digital circuitry simultaneously, then supply IOVDD first because the internal and the PLL. ESD protection diodes are referenced to the IOVDD voltage. • The RESET pin is high. AVDD, DVDD, and PVDD can be supplied at the same time as When the internal digital circuitry becomes active, the DSP core IOVDD or after, but they must not be supplied prior to IOVDD. runs eight lines of initialization code stored in ROM, requiring The order in which AVDD, DVDD, and PVDD are supplied does eight cycles of the MCLK signal. For a 12.288 MHz MCLK input, not matter. this process takes 650 ns. When the internal regulator is not used and DVDD is directly After the ROM program completes its execution, the PLL is supplied, no special sequence is required when providing the ready to be configured using register writes to Register 0xF000 proper voltages to AVDD, DVDD, and PVDD. (PLL_CTRL0), Register 0xF001 (PLL_CTRL1), Register 0xF002 When the internal regulator is used, DVDD is generated by the (PLL_CLK_SRC), and Register 0xF003 (PLL_ENABLE). regulator, in combination with an external pass transistor, after When the PLL is configured and enabled, the PLL starts to lock AVDD, IOVDD, and PVDD are supplied. See the Power Supplies to the incoming master clock signal. The absolute maximum section for more information. PLL lock time is 32 × 1024 = 32,768 clock cycles on the clock Each power supply domain has its own power-on reset (POR) signal (after the input prescaler), which is fed to the input of the circuits (also known as power OK circuits) to ensure that the PLL. In a standard 48 kHz use case, the PLL input clock frequency level shifters attached to each power domain can be initialized after the prescaler is 3.072 MHz; therefore, the maximum PLL lock properly. AVDD and PVDD must reach their nominal level time is 10.666 ms. before the auxiliary ADC and PLL can be used, respectively. Typically, the PLL locks much faster than 10.666 ms. In most However, the AVDD and PVDD supplies have no role in the systems, the PLL locks within about 3.5 ms. The PLL_LOCK rest of the power-up sequence. After AVDD power reaches its register (Address 0xF004) can be polled via the control port until nominal threshold, the regulator becomes active and begins to Bit 0 (PLL_LOCK) goes high, signifying that the PLL lock has charge up the DVDD supply. The DVDD also has a POR circuit to completed successfully. ensure that the level shifters initialize during power-up. When the PLL is attempting to lock to the input clock, the I2C The POR signals are combined into three global level shifter slave and SPI slave control ports are inactive; therefore, no other resets that properly initialize the signal crossings between each registers are accessible over the control port. When the PLL is separate power domain and DVDD. attempting to lock, all attempts to write to the control port fail. The digital circuits remain in reset until the IOVDD to DVDD level shifter reset is released. At that point, the digital circuits exit reset. Rev. D | Page 30 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Figure 14 shows an example power-up sequence with all relevant inside the input and output pins, must be applied first to avoid signals labeled. If possible, apply the required voltage to all four stressing these diodes. PVDD, AVDD, and DVDD can then be power supply domains (IOVDD, AVDD, PVDD, and DVDD) supplied in any order (see the System Initialization Sequence simultaneously. If the power supplies are separate, IOVDD, which section for more information). Note that the gray areas in this is the reference for the ESD protection diodes that are situated figure represent clock signals. STEP 1 2 3 4 5 6 7 8 9 10 11 12 IOVDD PINS PVDD PIN AVDD PIN DVDD PINS IOVDDTO DVDD LEVEL SHIFTER ENABLE (INTERNAL) PVDDTODVDD LEVEL SHIFTER ENABLE (INTERNAL) AVDDTODVDD LEVEL SHIFTER ENABLE (INTERNAL) RESET PIN RESET (INTERNAL) MASTER POWER-ON RESET (INTERNAL) XTALIN/MCLK PIN CLOCK INPUTTO THE PLL PLL OUTPUT CLOCK DESCRIPTION STARTING CONDITIONS.ALL SIGNALSARE LOW. IF POWER SUPPLIESARE SEPARATE,APPLY VOLTAGETO IOVDD FIRST.APPLY MASTER CLOCKSIGNALTO XTALIN/MCLK, UNLESS MASTER CLOCK ISAUTOMATICALLY GENERATEDUSING A CRYSTAL OSCILLATOR CIRCUIT. SUPPLY PVDDAT THE SAME TIME, ORAFTER, IOVDD. DO NOT BRING UP PVDD BEFORE IOVDD. INGUPAVDDBEFORE IOVDD.UPPLYAVDDATTHESAME TIME,ORAFTER, IOVDD.DONOTBRS RED,SUPPLY ITATTHESAME TIMEAS IOVDDANDPVDD,OIFDVDD ISEXTERNALLYSUPPLI BEFORE IOVDD OR PVDD.AFTER PVDD. DO NOT BRING IT UP IVATE,CHTHEIRNOMINALLEVELS,THELEVELSHIFTERSACTAFTERALLSUPPLIESREAALLOWING SIGNALSTOPASS INTERNALLY BETWEEN POWER DOMAINS. TIVE,VELSHIFTERSBECOMEACWHENTHE IOVDDTODVDDANDPVDDTODVDDLESPASSEDTO THEPLL.RCLOCK INPUTSIGNAL ITHEMASTE IF THE RESET PIN IS NOTALREADY HIGH, PULL IT HIGHATANY TIME.(AT THE BEGINNING OFA POWER SEQUENCE, THE STATE OF THE RESET PIN IS DON’T CARE.) THE INTERNAL RESET SIGNAL GOES HIGH WHEN THE FOLLOWING CONDITIONSARE TRUE:ALLVALID,AND THE RESET PIN IS LOGIC HIGH.POWER SUPPLIESARE WHEN THE INTERNAL RESET GOES HIGH, THE DSP CORE RUNS INITIALIZATION CODE, WHICHREQUIRES EIGHT CYCLES OF THE XTALIN/MCLK SIGNAL.AT 12.288MHz,THE PROCESS REQUIRES 650ns. L PORT IS NOWACCESSIBLE. PROGRAM THE PLL USING REGISTER WRITES. THE CONTROTHE PLL THEN LOCKS, REQUIRING A MAXIMUM OF 10.666ms. LOCKS, OTHER REGISTERS CAN BE PROGRAMMED,AFTER THE PLLAND THE DSP CAN START RUNNING. 11486-018 Figure 14. Power Sequencing and POR Timing Diagram for a System with Separate Power Supplies Rev. D | Page 31 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet System Initialization Sequence XTALIN/MCLK pin. When the SS/ADDR0 line rises for the third time, the slave control port is then in SPI mode. Before the IC can process the audio in the DSP, the following 5. Execute the register and memory write sequence that is initialization sequence must be completed. required to configure the device in the proper operating 1. If possible, apply the required voltage to all four power mode. supply domains (IOVDD, AVDD, PVDD, and DVDD) Table 27 contains an example series of register writes used to simultaneously. If simultaneous application is not possible, configure the system at startup. The contents of the data column supply IOVDD first to prevent damage or reduced operating may vary depending on the system configuration. The lifetime. If using the on-board regulator, AVDD and PVDD configuration that is listed in Table 27 represents the default can be supplied in any order, and DVDD is then generated initialization sequence for project files generated in SigmaStudio. automatically. If not using the on-board regulator, AVDD, PVDD, and DVDD can be supplied in any order following Recommended Program/Parameter Loading Procedure IOVDD. When writing large amounts of data to the program or parameter 2. Start providing a master clock signal to the XTALIN/MCLK RAM in direct write mode (when downloading the initial pin, or, if using the crystal oscillator, let the crystal oscillator contents of the RAMs from an external memory), use the start generating a master clock signal. The master clock hibernate register (Address 0xF400) to disable the processor signal must be valid when the DVDD supply stabilizes. core, preventing undesirable noises from appearing at the audio 3. If the SELFBOOT pin is pulled high, a self boot sequence output. See Table 60 in the Programming the SigmaDSP Core initiates on the master control port. Wait until the self boot section for details. When small amounts of data are transmitted operation is complete. during real-time operation of the DSP (such as when updating 4. If SPI slave control mode is desired, toggle the SS/ADDR0 individual parameters), the software safeload mechanism can be pin three times. Ensure that each toggle lasts at least the used (see the Software Safeload section). duration of one cycle of the master clock being input to the Table 27. Example System Initialization Register Write Sequence1 Address Data Register/Memory Description N/A N/A N/A If using I2C, skip the next lines that enable SPI mode by toggling the SS/ADDR0 pin three times. N/A N/A N/A Pull SS/ADDR0 low for at least one MCLK cycle. N/A N/A N/A Set SS/ADDR0 high for at least one MCLK cycle. First toggle is complete. N/A N/A N/A Pull SS/ADDR0 low for at least one MCLK cycle. N/A N/A N/A Set SS/ADDR0 high for at least one MCLK cycle. Second toggle is complete. N/A N/A N/A Pull SS/ADDR0 low for at least one MCLK cycle. N/A N/A N/A Set SS/ADDR0 high for at least one MCLK cycle. Third toggle is complete. The slave communication port is now in SPI mode. 0xF890 0x00, 0x00 SOFT_RESET Enter soft reset. 0xF890 0x00, 0x01 SOFT_RESET Exit soft reset. N/A N/A N/A Wait for at least 650 ns (with MCLK = 12.288 MHz). 0xF400 0x00, 0x00 Hibernate Hibernate off. 0xF400 0x00, 0x01 Hibernate Hibernate on. N/A N/A N/A Wait for at least one sample period. 0xF403 0x00, 0x01 KILL_CORE Stop the core immediately. 0xF000 0x00, 0x60 PLL_CTRL0 Set the feedback divider to the correct setting for the application. In this example, it is set to the power-on default setting of 96. 0xF001 0x00, 0x02 PLL_CTRL1 Set PLL input clock divider to 4. 0xF002 0x00, 0x01 PLL_CLK_SRC Set clock source to PLL clock. 0xF005 0x00, 0x05 MCLK_OUT Enable MCLK output (12.288 MHz). 0xF003 0x00, 0x01 PLL_ENABLE Enable PLL. N/A N/A N/A Wait for PLL lock (see the Power-Up Sequence section); the maximum PLL lock time is 10.666 ms. 0xF050 0x4F, 0xFF POWER_ENABLE0 Enable power for all major systems except Clock Generator 3 (Clock Generator 3 is rarely used in most systems). 0xF051 0x00, 0x00 POWER_ENABLE1 Disable power for subsystems like PDM microphones, S/PDIF, and the ADC if the subsystems are not used in the system. Rev. D | Page 32 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Address Data Register/Memory Description 0xC000 Data generated Program RAM data Download the entire program RAM contents using a block write (data provided by by SigmaStudio SigmaStudio compiler). 0x0000 Data generated DM0 RAM data Download Data Memory DM0 using a block write (data provided by SigmaStudio by SigmaStudio compiler). 0x6000 Data generated DM1 RAM data Download Data Memory DM1 using a block write (data provided by SigmaStudio by SigmaStudio compiler); the start address of DM1 may vary, depending on the SigmaStudio compilation. 0xF404 0x00, 0x00 START_ADDRESS Set program start address as defined by the SigmaStudio compiler. 0xF401 0x00, 0x02 START_PULSE Set DSP core start pulse to internally generated pulse. N/A N/A N/A Configure any other registers that require nondefault values. 0xF403 0x00, 0x00 KILL_CORE Remove the KILL_CORE state to allow the core to be started when the START_CORE sequence is performed. 0xF402 0x00, 0x00 START_CORE Start the low to high transition. 0xF402 0x00, 0x01 START_CORE Start the core. Complete the low to high transition. N/A N/A N/A Wait 50 µs for initialization program to execute. 0xF400 0x00, 0x00 Hibernate Hibernate off. 1 N/A means not applicable small as possible. Calculate the necessary values of the two load MASTER CLOCK, PLL, AND CLOCK GENERATORS capacitors in the circuit from the crystal load capacitance, using Clocking Overview the following equation: To externally supply the master clock, connect the clock source C1×C2 directly to the XTALIN/MCLK pin. Alternatively, use the CL = C1+C2+CSTRAY internal clock oscillator to drive an external crystal. Using the Oscillator where: C1 and C2 are the load capacitors. The ADAU1452/ADAU1451/ADAU1450 can use an on-board C is the stray capacitance in the circuit. C is usually STRAY STRAY oscillator to generate its master clock. However, to complete the assumed to be approximately 2 pF to 5 pF, but it varies oscillator circuit, an external crystal must be attached. The on- depending on the PCB design. board oscillator is designed to work with a crystal that is tuned Short trace lengths in the oscillator circuit decrease stray capaci- to resonate at a frequency of the nominal system clock divided tance, thereby increasing the loop gain of the circuit and helping by 24. For a normal system, where the nominal system clock is to avoid crystal start-up problems. Therefore, place the crystal 294.912 MHz, this frequency is 12.288 MHz. as near to the XTALOUT pin as possible, and on the same side The fundamental frequency of the crystal can be up to 30 MHz. of the PCB. Practically speaking, in most systems, the fundamental frequency of the crystal must range from 3.072 MHz to 24.576 MHz. On the EVAL-ADAU1452MINIZ evaluation board, the C1 and C2 load capacitors are 22 pF. For the external crystal in the circuit, use an AT-cut parallel Do not use XTALOUT to directly drive the crystal signal to resonance device operating at its fundamental frequency. Do not another IC. This signal is an analog sine wave with low drive use ceramic resonators, because of their poor jitter performance. capability and, therefore, is not appropriate to drive an external Quartz crystals are ideal for audio applications. Figure 15 shows digital input. A separate pin, CLKOUT, is provided for this pur- the crystal oscillator circuit that is recommended for proper pose. The CLKOUT pin is set up using the MCLK_OUT register operation. (Address 0xF005). For a more detailed explanation of CLKOUT, 22pF XTALIN/MCLK refer to the Master Clock Output section or the register map description of the MCLK_OUT register (see the CLKOUT 12.288MHz 100Ω Control Register section). XTALOUT 22pF 11486-019 If a clock signal is provided from elsewhere in the system directly Figure 15. Crystal Resonator Circuit to the XTALIN/MCLK pin, the crystal resonator circuit is not necessary, and the XTALOUT pin can remain disconnected. The 100 Ω damping resistor on XTALOUT provides the oscillator with a voltage swing of approximately 3.1 V at the XTALIN/ MCLK pin. The optimal crystal shunt capacitance is 7 pF. The optimal load capacitance of this shunt, as specified by the manu- facturer, must be about 20 pF, although the circuit supports values of up to 25 pF. Ensure that the equivalent series resistance is as Rev. D | Page 33 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Setting the Master Clock and PLL Mode 96 kHz, or 192 kHz audio sample rate, the typical master clock input frequencies are 3.072 MHz, 6.144 MHz, 12.288 MHz, and An integer PLL is available to generate the core system clock 24.576 MHz. Note that the flexibility of the PLL allows a large from the master clock input signal. The PLL generates the nominal range of other clock frequencies. 294.912 MHz core system clock to run the DSP core. As a result of the flexible clock generator circuitry, this nominal core clock The PLL in the ADAU1452 and ADAU1451 has a nominal (and frequency can be used for a variety of audio sample rates. An maximum) output frequency of 294.912 MHz. The PLL output integer prescaler takes the clock signal from the MCLK pin and of the ADAU1452-150 and ADAU1450 is divided to obtain a divides its frequency by 1, 2, 4, or 8 to meet the appropriate system clock frequency at half the rate of the ADAU1452 and frequency range requirements for the PLL itself. The nominal ADAU1451, with a nominal (and maximum) output frequency input frequency to the PLL is 3.072 MHz. For systems with of 147.456 MHz. an 11.2896 MHz input master clock, the input to the PLL is The PLL is configured by setting Register 0xF000 (PLL_CTRL0), 2.8224 MHz. Register 0xF001 (PLL_CTRL1), and Register 0xF002 (PLL_CLK_ 1, 2, 4, (DEFAULT) SRC). After these registers are modified, set Register 0xF003, Bit 0 OR 8 96 XTALIN/ (PLL_ENABLE), forcing the PLL to reset itself and attempt to MCLK ÷ × SYSTEM CLOCK N3O.M07I2NMAHLLzY 11486-020 rweiltohcikn t3o. 5t hme si.n Wcohmeinn tgh cel oPcLkL s liogcnkasl. tToy apnic ianlplyu, tt hcleo PckL La nlodc ckrse ates Figure 16. PLL Functional Block Diagram a stable output clock, a lock flag is set in Register 0xF004, Bit 0 (PLL_LOCK). The master clock input signal ranges in frequency from 2.375 MHz to 36 MHz. For systems that are intended to operate at a 48 kHz, Rev. D | Page 34 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Example PLL Settings overall power consumption of the device. Table 28 shows several example MCLK frequencies and the corresponding PLL settings Depending on the input clock frequency, there are several possible that allow for the highest number of program instructions to be configurations for the PLL. Setting the PLL to generate the highest executed for each audio frame. The settings provide the highest possible system clock, without exceeding the maximum, allows the possible system clock without exceeding the 294.912 MHz upper execution of more DSP program instructions for each audio frame. limit (or 147.456 MHz in the case of the ADAU1452-150 and Alternatively, setting the PLL to generate a lower frequency system ADAU1450). clock allows fewer instructions to be executed and also lowers Table 28. Optimal Predivider and Feedback Divider Settings for Varying Input MCLK Frequencies ADAU1452, ADAU1452K, ADAU1452-150 and Input MCLK Predivider PLL Input Clock Feedback Divider and ADAU1451 System ADAU1450 Frequency (MHz) Setting (MHz) Setting Clock (MHz) System Clock (MHz) 2.8224 1 2.8224 104 293.5296 146.7648 3 1 3 98 294 147 3.072 1 3.072 96 294.912 147.456 3.5 1 3.5 84 294 147 4 1 4 73 292 146 4.5 1 4.5 65 292.5 146.25 5 2 2.5 117 292.5 146.25 5.5 2 2.75 107 294.25 147.125 5.6448 2 2.8224 104 293.5296 146.7648 6 2 3 98 294 147 6.144 2 3.072 96 294.912 147.456 6.5 2 3.25 90 292.5 146.25 7 2 3.5 84 294 147 7.5 2 3.75 78 292.5 146.25 8 2 4 73 292 146 8.5 2 4.25 69 293.25 146.625 9 2 4.5 65 292.5 146.25 9.5 4 2.375 124 294.5 147.25 10 4 2.5 117 292.5 146.25 10.5 4 2.625 112 294 147 11 4 2.75 107 294.25 147.125 11.2896 4 2.8224 104 293.5296 146.7648 11.5 4 2.875 102 293.25 146.625 12 4 3 98 294 147 12.288 4 3.072 96 294.912 147.456 12.5 4 3.125 94 293.75 146.875 13 4 3.25 90 292.5 146.25 13.5 4 3.375 87 293.625 146.8125 14 4 3.5 84 294 147 14.5 4 3.625 81 293.625 146.8125 15 4 3.75 78 292.5 146.25 15.5 4 3.875 76 294.5 147.25 16 4 4 73 292 146 16.5 4 4.125 71 292.875 146.4375 17 4 4.25 69 293.25 146.625 17.5 4 4.375 67 293.125 146.5625 18 4 4.5 65 292.5 146.25 18.5 8 2.3125 127 293.6875 146.84375 19 8 2.375 124 294.5 147.25 19.5 8 2.4375 120 292.5 146.25 20 8 2.5 117 292.5 146.25 20.5 8 2.5625 115 294.6875 147.34375 21 8 2.625 112 294 147 Rev. D | Page 35 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet ADAU1452, ADAU1452K, ADAU1452-150 and Input MCLK Predivider PLL Input Clock Feedback Divider and ADAU1451 System ADAU1450 Frequency (MHz) Setting (MHz) Setting Clock (MHz) System Clock (MHz) 21.5 8 2.6875 109 292.9375 146.46875 22 8 2.75 107 294.25 147.125 22.5 8 2.8125 104 292.5 146.25 22.5792 8 2.8224 104 293.5296 146.7648 23 8 2.875 102 293.25 146.625 23.5 8 2.9375 100 293.75 146.875 24 8 3 98 294 147 24.5 8 3.0625 96 294 147 24.576 8 3.072 96 294.912 147.456 25 8 3.125 94 293.75 146.875 Relationship Between System Clock and Instructions per Table 29. Maximum Instructions per Sample, Depending on Sample System Clock and DSP Core Sample Rate The DSP core executes only a limited number of instructions DSP Core System Sample Rate Maximum Instructions within the span of each audio sample. The number of instructions Clock (MHz) (kHz) per Sample that can be executed is a function of the system clock and the DSP 294.912 8 36,8641 core sample rate. The core sample rate is set by Register 0xF401 294.912 12 24,5761 (START_PULSE), Bits[4:0] (START_PULSE). 294.912 16 18,4321 The number of instructions that can be executed per sample is 294.912 24 12,2881 equal to the system clock frequency divided by the DSP core 294.912 32 92161 sample rate. However, the program RAM size is 8192 words; 294.912 48 6144 therefore, in cases where the maximum instructions per sample 294.912 64 4608 exceeds 8192, subroutines and loops must be utilized to make 294.912 96 3072 use of all available instructions (see Table 29). 294.912 128 2304 PLL Filter 294.912 192 1536 293.5296 11.025 26,6241 An external PLL filter is required to help the PLL maintain 293.5296 22.05 13,3121 stability and to limit the amount of ripple appearing on the phase 293.5296 44.1 6656 detector output of the PLL. For a nominal 3.072 MHz PLL input 293.5296 88.2 3328 and a 294.912 MHz system clock output (or 147.456 MHz in the 293.5296 176.4 1664 case of the ADAU1452-150 and ADAU1450), the recommended 147.456 8 18,4321 filter configuration is shown in Figure 17. This filter works for 147.456 12 12,2881 the full frequency range of the PLL. 147.456 16 92161 5.6nF PVDD 147.456 24 6144 PLLFILT 150pF 4.3kΩ 11486-021 114477..445566 4382 43600782 147.456 64 2304 Figure 17. PLL Filter 147.456 96 1536 Because the center frequency and bandwidth of the loop filter 147.456 128 1152 is determined by the values of the included components, use high 147.456 192 768 accuracy (low tolerance) components. Components that are 146.7648 11.025 13,3121 valued within 10% of the recommended component values and 146.7648 22.05 6656 with a 15% or lower tolerance are suitable for use in the loop 146.7648 44.1 3328 filter circuit. 146.7648 88.2 1664 The voltage on the PLLFILT pin, which is internally generated, 146.7648 176.4 832 is typically between 1.65 V and 2.10 V. 1 The instructions per sample in these cases exceed the program memory size of 8192 words; therefore, to utilize the full number of instructions, subroutines or branches are required in the SigmaStudio program. Rev. D | Page 36 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Clock Generators In addition to the nominal output, four additional output signals are generated at double, quadruple, half, and a quarter of the Three clock generators are available to generate audio clocks for frequency of the nominal output frequency. the serial ports, DSP, ASRCs, and other audio related functional blocks in the system. Each clock generator can be configured to For Clock Generator 1 and Clock Generator 2, the integer numer- generate a base frequency and several fractions or multiples of that ator (N) and the integer denominator (M) are nine bits long, base frequency, creating a total of 15 clock domains available for each. For Clock Generator 3, N and M are each 16 bits long, use in the system. Each of the 15 clock domains can create the allowing a higher precision when generating arbitrary clock appropriate LRCLK (frame clock) and BCLK (bit clock) signals for frequencies. the serial ports. Five BCLK signals are generated at frequencies of Figure 18 shows a basic block diagram of the PLL and clock 32 BCLK/sample, 64 BCLK/sample, 128 BCLK/sample, 256 BCLK/ generators. Each division operator symbolizes that the frequency sample, and 512 BCLK/sample to deal with TDM data. Therefore, of the clock is divided when passing through that block. Each with a single master clock input frequency, 15 different frame clock multiplication operator symbolizes that the frequency of the frequencies and 75 different bit clock frequencies can be clock is multiplied when passing through that block. generated for use in the system. Figure 20 shows an example where the master clock input has a The nominal output of each clock generator is determined by frequency of 12.288 MHz, and the default settings are used for the following formula: the PLL predivider, feedback divider, and Clock Generator 1 Output_Frequency = (Input_Frequency × N)/(1024 × M) and Clock Generator 2. The resulting system clock is as follows: where: 12.288 MHz ÷ 4 × 96 = 294.912 MHz Input_Frequency is the PLL output (nominally 294.912 MHz). The base output of Clock Generator 1 is as follows: Output_Frequency is the frame clock output frequency. 294.912 MHz ÷ 1024 × 1 ÷ 6 = 48 kHz N and M are integers that are configured by writing to the clock generator configuration registers. The base output of Clock Generator 2 is as follows: These calculations are also accurate in the case of the ADAU1452- 294.912 MHz ÷ 1024 × 1 ÷ 9 = 32 kHz 150 and ADAU1450, even though the output rate of its PLL is In this example, Clock Generator 3 is configured with N = 49 and half of that of the ADAU1452/ADAU1451. Figure 19 shows the M = 320; therefore, the resulting base output of Clock Generator 3 is dividers before the clock generators compensate for the as follows: difference in the system clock rate. 294.912 MHz ÷ 1024 × 49 ÷ 320 = 44.1 kHz 1, 2, 4, PROGRAMMABLE OR 8 TYPICALLY 96 XTALIN/ MCLK ÷ × SYSTEM CLOCK DIVIDER FEEDBACK (Default) DIVIDER N = 1, M = 6 ×4 ×2 CLKGEN 1 ÷1024 × N ÷ M ×1 ÷2 (Default) ÷4 N = 1, M = 9 ×4 ×2 CLKGEN 2 ÷1024 × N ÷ M ×1 ÷2 ÷4 ×4 ×2 CLKGEN 3 ÷1024 × N ÷ M ×÷÷241 11486-022 Figure 18. PLL and Clock Generators Block Diagram for 294.912 MHz Nominal System Clock Rate Rev. D | Page 37 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet 1,2,4, PROGRAMMABLE XTMACLLINK/ OR÷8 TYPICA×LLY96 ÷2 1S4Y7S.4T5E6MMHCzLOCK DIVIDER FEEDBACK POST (Default) DIVIDER DIVIDER N=1, M=6 ×4 ×2 CLKGEN1 ÷512 ×N÷M ×1 ÷2 (Default) ÷4 N=1, M=9 ×4 CLKGEN2 ×2 ÷512 ×N÷M ×1 ÷2 ÷4 ×4 CLKGEN3 ×2 ÷512 ×N÷M ÷×÷241 11486-119 Figure 19. PLL and Clock Generators Block Diagram for the ADAU1452-150 and the ADAU1450 4 96 12.288MHz 294.912MHz CLOCK ÷ × SYSTEM CLOCK SOURCE (147.456MHz FOR ADAU1450 DIVIDER FEEDBACK AND ADAU1452-150) DIVIDER N = 1, M = 6 192kHz CLKGEN 1 96kHz ÷1024 × N ÷ M 48kHz 24kHz 12kHz N = 1, M = 9 128kHz CLKGEN 2 64kHz ÷1024 × N ÷ M 32kHz 16kHz 8kHz N = 49, M = 320 176.4kHz CLKGEN 3 88.2kHz ÷1024 × N ÷ M 421421...100k52Hk5HkzHzz 11486-023 Figure 20. PLL and Audio Clock Generators with Default Settings and Resulting Clock Frequencies Labeled, XTALIN/MCLK = 12.288 MHz 11.2896MHz 4 96 270.9504MHz CLOCK ÷ × SYSTEM CLOCK SOURCE (135.4752MHz FOR ADAU1450 DIVIDER FEEDBACK AND ADAU1452-150) DIVIDER N = 1, M = 6 176.4kHz CLKGEN 1 88.2kHz ÷1024 × N ÷ M 44.1kHz 22.05kHz 11.025kHz N = 1, M = 9 117.6kHz CLKGEN 2 58.8kHz ÷1024 × N ÷ M 29.4kHz 14.7kHz 7.35kHz N = 80, M = 441 192kHz CLKGEN 3 96kHz ÷1024 × N ÷ M 421842kkkHHHzzz 11486-024 Figure 21. PLL and Audio Clock Generators with Default Settings and Resulting Clock Frequencies Labeled, XTALIN/MCLK = 11.2896 MHz Rev. D | Page 38 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Figure 21 shows an example where the master clock input has a 1, 2, 4, OR 8 frequency of 11.2896 MHz, and the default settings are used for × CLKOUT the PLL predivider, feedback divider, and Clock Generator 1 and 1O, 2R, 84, TYPICALLY 96 Clock Generator 2. The resulting system clock is as follows: MCLK ÷ × SYSTEM CLOCK DIVIDER FEEDBACK 11.2896 MHz ÷ 4 × 96 = 270.9504 MHz DIVIDER CLKGEN 1 The base output of Clock Generator 1 is as follows: CLKGEN 2 The b2a7s0e. 9o5u0t4p uMt Hofz C ÷l o1c0k2 G4 ×en 1e r÷a t6o r= 2 4 i4s. 1a sk fHolzl ows: CLKGEN 3 11486-025 Figure 22. Clock Output Generator (Simplified) 270.9504 MHz ÷ 1024 × 1 ÷ 9 = 29.4 kHz The CLKOUT pin can drive more than one external slave IC if In this example, Clock Generator 3 is configured with N = 80 the drive strength is sufficient to drive the traces and external and M = 441; therefore, the resulting base output of Clock receiver circuitry. The ability to drive external ICs varies greatly, Generator 3 is as follows: depending on the application and the characteristics of the PCB 270.9504 MHz ÷ 1024 × 80 ÷ 441 = 48 kHz and the slave ICs. The drive strength and slew rate of the Master Clock Output CLKOUT pin is configurable in the CLKOUT_PIN register (Address 0xF7A3), which means that its performance can be The master clock output pin (CLKOUT) is useful in cases where tuned to match the specific application. The CLKOUT pin is not a master clock must be fed to other ICs in the system, such as designed to drive long cables or other high impedance audio codecs. The master clock output frequency is determined transmission lines. Use the CLKOUT pin only to drive signals by the setting of the MCLK_OUT register (Address 0xF005). to other integrated circuits on the same PCB. When changing the Four frequencies are possible: 1×, 2×, 4×, or 8× the frequency settings for the predivider, disable and then reenable the PLL of the predivider output. The CLKOUT signal is taken from the using Register 0xF003 (PLL_ENABLE), allowing the frequency PLL output but the frequency is always 1×, 2×, 4×, or 8× the of the CLKOUT signal to update. frequency after the PLL predivider output. The diagram in Dejitter Circuitry Figure 22 is simplified. • The predivider output × 1 generates a 3.072 MHz output To account for jitter between ICs in the system and to handle interfacing safely between internal and external clocks, dejitter for a nominal system clock of 294.912 MHz. circuits are included to guarantee that jitter related clocking errors • The predivider output × 2 generates a 6.144 MHz output for are avoided. The dejitter circuitry is automated and does not a nominal system clock of 294.912 MHz. require interaction or control from the user. • The predivider output × 4 generates a 12.288 MHz output for a nominal system clock of 294.912 MHz. • The predivider output × 8 generates a 24.576 MHz output for a nominal system clock of 294.912 MHz. Rev. D | Page 39 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Master Clock, PLL, and Clock Generators Registers Voltage Regulator An overview of the registers related to the master clock, PLL, The ADAU1452/ADAU1451/ADAU1450 include a linear and clock generators is listed in Table 30. For a more detailed regulator that can generate the 1.2 V supply required by the description, see the PLL Configuration Registers section and the DSP core and other internal digital circuitry from an external Clock Generator Registers section. supply. Source the linear regulator from the input/output supply (IOVDD), which can range from 1.8 V − 5% to 3.3 V + 10%. A Table 30. Master Clock, PLL, and Clock Generator Registers simplified block diagram of the internal structure of the regulator Address Register Description is shown in Figure 23. 0xF000 PLL_CTRL0 PLL feedback divider IOVDD 0xF001 PLL_CTRL1 PLL prescale divider EXTERNAL 0xF002 PLL_CLK_SRC PLL clock source STABILITY 0xF003 PLL_ENABLE PLL enable RESISTOR 0xF004 PLL_LOCK PLL lock IOVDD VDRIVE EXTERNAL 0xF005 MCLK_OUT CLKOUT control INTERNAL PNP BIPOLAR 1.2V PASS TRANSISTOR 0xF006 PLL_WATCHDOG Analog PLL watchdog control REFERENCE PMOS DEVICE 0xF020 CLK_GEN1_M Denominator (M) for Clock Generator 1 00xxFF002212 CCLLKK__GGEENN12__MN NDuenmoemraitnoart (oNr )( Mfo)r fColro Ccklo Gcek nGeernateorra t1o r 2 GND DVDD 11486-026 0xF023 CLK_GEN2_N Numerator (N) for Clock Generator 2 Figure 23. Simplified Block Diagram of Regulator Internal Structure, 0xF024 CLK_GEN3_M Denominator (M) for Clock Generator 3 Including External Components 0xF025 CLK_GEN3_N Numerator (N) for Clock Generator 3 For proper operation, the linear regulator requires several 0xF026 CLK_GEN3_SRC Input reference for Clock Generator 3 external components. A PNP bipolar junction transistor acts 0xF027 CLK_GEN3_LOCK Lock bit for Clock Generator 3 input reference as an external pass device to bring the higher IOVDD voltage down to the lower DVDD voltage, externally dissipating the POWER SUPPLIES, VOLTAGE REGULATOR, AND power of the IC package. Ensure that the transistor is able to HARDWARE RESET dissipate at least 1 W in the worst case. Place a 1 kΩ resistor Power Supplies between the transistor emitter and base to help stabilize the regulator for varying loads. This resistor placement also The ADAU1452/ADAU1451/ADAU1450 are supplied by four guarantees that current is always flowing into the VDRIVE pin, power supplies: IOVDD, DVDD, AVDD, and PVDD. even for minimal regulator loads. Figure 24 shows the connection • IOVDD (input/output supply) sets the reference voltage of the external components. for all digital input and output pins. It can be any value 10µF ranging from 1.8 V − 5% to 3.3 V + 10%. To use the I2C/SPI + control ports or any of the digital input or output pins, the 1kΩ IOVDD supply must be present. 100nF • DVDD (digital supply) powers the DSP core and supporting digital logic circuitry. It must be 1.2 V ± 5%. • AVDD (analog supply) powers the analog auxiliary ADC cniortc uinit ruys.e I.t must be supplied even if the auxiliary ADCs are DVDD VDRIVE IOVDD 11486-027 • PVDD (PLL supply) powers the PLL and acts as a reference Figure 24. External Components Required for Voltage Regulator Circuit for the voltage controlled oscillator (VCO). It must be supplied In selecting the external pass transistor, the following extreme even if the PLL is not in use. conditions must be accounted for: Table 31. Power Supply Details • Minimum current that can be drawn by the DSP. Externally • Maximum current that can be drawn by the DSP. Supply Voltage Supplied Description For the first condition, the minimum current is approximately IOVDD 1.8 V − 5% to Yes (Input/Output) 3.3 V + 10% 20 mA. For the regulator to supply 20 mA to the DSP, the DVDD (Digital) 1.2 V ± 5% Optional Can be derived VDRIVE current must be a small value. A transistor with a very from IOVDD using small transistor (β) suffices. an internal LDO regulator AVDD (Analog) 3.3 V ± 10% Yes PVDD (PLL) 3.3 V ± 10% Yes Rev. D | Page 40 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 The other extreme condition is more difficult to meet. The maxi- Overview of Power Reduction Registers mum current demands of the DSP are at hot temperatures. This An overview of the registers related to power reduction is shown device has a maximum DVDD current of 635 mA; however, if it is in Table 32. For a more detailed description, refer to the Power possible to for the user to upgrade to a different device in the Reduction Registers section. ADAU1466 family of DSPs, it is recommended to use a device that offers the maximum 940 mA specification. For the regulator to Table 32. Power Reduction Registers produce 940 mA, the transistor (β) must be at least 94 to keep Address Register Description the pass transistor base current below the maximum of 10 mA 0xF050 POWER_ENABLE0 Disables clock generators, serial of current sunk into the VDRIVE pin. However, a beta of 94 ports, and ASRCs allows no margin for the pass transistor and DSP silicon variance 0xF051 POWER_ENABLE1 Disables PDM microphone inputs, S/PDIF interfaces, and auxiliary in addition to temperature differences. Doubling the transistor (β) ADCs minimum is considered good practice because doing this leads to a minimum transistor (β) of approximately 180. The maximum Hardware Reset current demands of the DSP occur at high temperatures, and the An active low hardware reset pin (RESET) is available for β of most transistors increases with temperature. externally triggering a reset of the device. When this pin is tied The bypass capacitors must also be considered for the regulator to ground, all functional blocks in the device are disabled, and design implementation. The regulator design simulations used a the current consumption decreases dramatically. The amount of 10 µF electrolytic bulk capacitor, four 100 nF ceramic bypass current drawn depends on the leakage current of the silicon, which capacitors, and four 10 nF ceramic bypass capacitors. This combi- depends greatly on the ambient temperature and the properties nation produced a phase margin of 71° to 79° of performance of the die. When the RESET pin is connected to IOVDD, all control over all temperatures and skews. If an electrolytic capacitor is registers are reset to their power-on default values. The state of not desired, use of a ceramic capacitor is possible, as long as a the RAM is not guaranteed to be cleared after a reset, so the 0.5 Ω resistor is added in series with the ceramic capacitor to memory must be manually cleared by the DSP program. simulate the effective series resistance (ESR) of an electrolytic The default program generated by SigmaStudio includes code capacitor. The RC combination produces a phase margin of 60° that automatically clears the memory. To ensure that no chatter to 79°, which is crucial to maintaining optimal performance of exists on the RESET signal line, implement an external reset the voltage regulator. generation circuit in the system hardware design. Figure 25 If an external supply is provided to DVDD, ground the shows an example of the ADM811 microprocessor supervisory VDRIVE pin. The regulator continues to draw a small amount circuit with a push-button connected, providing a method for of current (around 100 µA) from the IOVDD supply. Do not use manually generating a clean RESET signal. For reliability purposes the regulator to provide a voltage supply to external ICs. There on the application level, place a weak pull-down resistor (in the are no control registers associated with the regulator. range of several kΩ) on the RESET line to guarantee that the Power Reduction Modes device is held in reset in the event that the reset supervisory circuitry fails. All sections of the IC have clock gating functionality that allows individual functional blocks to be disabled for power savings. 3.3V ADM811 Functional blocks that can optionally be powered down include 100nF 1 GND RESET 2 RESET the following: •• CS/lPoDckI FG erenceeriavtoerr 1, Clock Generator 2, and Clock Generator 3 4 VCC MR 3 11486-028 Figure 25. Example Manual Reset Generation Circuit • S/PDIF transmitter If the hardware reset function is not required in a system, pull • Serial data input and output ports the RESET pin high to the IOVDD supply, using a weak pull-up • Auxiliary ADC resistor (in the range of several kΩ). The device is designed to boot • ASRCs (in two banks of eight channels each) properly even when the RESET pin is permanently pulled high. • PDM microphone inputs and decimation filters Rev. D | Page 41 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet DSP Core Current Consumption Slave Control Port Overview The DSP core draws varying amounts of current, depending To program the DSP and configure the control registers, a slave on the processing load required by the program it is running. port is available that can communicate using either the I2C or SPI Figure 26 shows the relationship between program size and protocols. A separate master communications port can be used digital (DVDD) current draw. The minimum of 0 MIPS signifies to self boot the chip by reading from an external EEPROM, or the case where no program is running in the DSP core, and the to boot or control external ICs by addressing them directly using maximum of 294 MIPS signifies that the DSP core is at full I2C or SPI. The slave communications port defaults to I2C mode; utilization, executing a typical audio processing program. however, it can be put into SPI mode by toggling SS (SS/ADDR0), 160 the slave select pin, low three times. Each toggle must last at least the duration of one clock period of the clock on MCLK 140 (XTALIN/MCLK), the master clock input pin. Until the PLL locks, 120 only the PLL configuration registers (Address 0xF000 to mA) Address 0xF004) are accessible. For this reason, always write to T (100 the PLL registers first after the chip powers up. After the PLL N E RR 80 locks, the remaining registers and the RAM become accessible. U C See the System Initialization Sequence section for more D 60 VD information. D 40 The control port is capable of full read/write operation for all 20 addressable registers. The ADAU1452/ADAU1451/ADAU1450 must have a valid master clock to write to all registers, with the 0 0 50 PR10O0GRAM L1E5N0GTH (M2I0P0S) 250 300 11486-124 ecxacne bpeti oancc oefs Rseedg iisnte br o0txhF 0si0n0g tloe aRdedgriestsesr m 0oxdFe0 0a4n.d A blul rasdt dmreosdsee.s Figure 26. ADAU1452 Typical DVDD Current Draw vs. Program MIPS at an The first byte (Byte 0) of a control port write contains the 7-bit Ambient Temperature of 25°C and a Sample Rate of 48 kHz chip address plus the R/W bit. The next two bytes (Byte 1 and TEMPERATURE SENSOR DIODE Byte 2) together form the subaddress of the register location The chip includes an on-board temperature sensor diode with within the memory maps of the ADAU1452/ADAU1451/ an approximate range of 0°C to 120°C. The temperature sensor ADAU1450. This subaddress must be two bytes long because the function is enabled by the two sides of a diode connected to the memory locations within the devices are directly addressable, and THD_P and THD_M pins. Value processing (calculating the their sizes exceed the range of single byte addressing. All subse- actual temperature based on the current through the diode) is quent bytes (starting with Byte 3) contain the data, such as control handled off chip by an external controller IC. The temperature port data, program data, or parameter data. The number of bytes value is not stored in an internal register; it is available only in per word depends on the type of data that is being written. the external controller IC. The temperature sensor requires an The ADAU1452/ADAU1451/ADAU1450 have several mech- external IC to operate properly. The temperature value cannot anisms for updating signal processing parameters in real time be read by the on-board auxiliary ADC. without causing pops or clicks. 3.3V ADM1032 If large blocks of data must be downloaded, halt the output of the DSP core (using Register 0xF400, HIBERNATE), load new 1 VDD SCLK 8 SCL 100nF THD_P 2 D+ SDATA 7 SDA data, and then restart the device (using Register 0xF402, THD_M 3 D– ALERT 6 START_CORE). This process is typically performed during the 4 THERMGND 5 11486-029 booting sequence at startup or when loading a new program into RAM. Figure 27. Example External Temperature Sensor Circuit When updating a signal processing parameter when the DSP SLAVE CONTROL PORTS core is running, use the software safeload function to avoid A total of four control ports are available: two slave ports and two a situation where a parameter is updated over the boundary of master ports. The slave I2C port and slave SPI port allow an an audio frame, which can lead to an audio artifact such as a external master device to modify the contents of the memory and click or pop sound. For more information, see the Software registers. The master I2C port and master SPI port allow the device Safeload section. to self boot and to send control messages to slave devices on the The slave control port pins are multifunctional, depending on same bus. the mode in which the device is operating. Table 33 describes these multiple functions. Rev. D | Page 42 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Burst Mode Writing and Reading the data-word for the next address can be written immediately without sending its 2-byte address. The control registers in the Burst write and read modes are available for convenience when ADAU1452/ADAU1451/ADAU1450 are two bytes wide, and the writing large amounts of data to contiguous registers. In these memories are four bytes wide. The autoincrement feature modes, the chip and memory addresses are written 1×, and then knows the word length at each subaddress; therefore, it is not a large amount of data can follow uninterrupted. The sub- necessary to manually specify the subaddress for each address in a addresses are automatically incremented at the word boundaries. burst write. This increment happens automatically after a single word write or read unless a stop condition is encountered (I2C mode) or the The subaddresses are automatically incremented by one address, slave select is disabled and brought high (SPI mode). A burst write following each read or write of a data-word, regardless of whether starts like a single word write, but, following the first data-word, there is a valid register or RAM word at that address. Table 33. Control Port Pin Functions Pin Name I2C Slave Mode SPI Slave Mode SS/ADDR0 Address 0 (Bit 1 of the address word, input to the Slave select (input to the ADAU1452/ADAU1451/ADAU1450) ADAU1452/ADAU1451/ADAU1450) CCLK/SCL Clock (input to the ADAU1452/ADAU1451/ADAU1450) Clock (input to the ADAU1452/ADAU1451/ADAU1450) MOSI/ADDR1 Address 1 (Bit 2 of the address word, input to the Data; master out, slave in (input to the ADAU1452/ADAU1451/ ADAU1452/ADAU1451/ADAU1450) ADAU1450) MISO/SDA Data (bidirectional, open collector) Data; master in, slave out (output from the ADAU1452/ADAU1451/ ADAU1450) Rev. D | Page 43 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet I2C Slave Port IOVDD (by setting it to 1) or to GND (by setting it to 0). The The ADAU1452/ADAU1451/ADAU1450 support a 2-wire serial LSB of the address (the R/W bit) specifies either a read or write (I2C-compatible) microprocessor bus driving multiple peripherals. operation. Logic Level 1 corresponds to a read operation; Logic The maximum clock frequency on the I2C slave port is 400 kHz. Level 0 corresponds to a write operation. Two pins, serial data (SDA) and serial clock (SCL), carry Table 34 describes the sequence of eight bits that define the I2C information between the ADAU1452/ADAU1451/ADAU1450 device address byte. and the system I2C master controller. In I2C mode, the ADAU1452/ Table 35 describes the relationship between the state of the address ADAU1451/ADAU1450 are always slaves on the bus, meaning that pins (0 represents logic low and 1 represents logic high) and the they cannot initiate a data transfer. Each slave device is recognized I2C slave address. Ensure that the address pins (SS/ADDR0 and by a unique address. The address bit sequence and the format of MOSI/ADDR1) are hardwired in the design. Do not allow them the read/write byte is shown in Table 34. The address resides in to change states during device is operation. the first seven bits of the I2C write. The two address bits that follow can be set to assign the I2C slave address of the device, as Place a 2 kΩ pull-up resistor on each line connected to the SDA follows: Bit 1 can be set by pulling the SS/ADDR0 pin either to and SCL pins. Ensure that the voltage on these signal lines does IOVDD (by setting it to 1) or to GND (by setting it to 0); and not exceed IOVDD (1.8 V − 5% to 3.3 V + 10%). Bit 2 can be set by pulling the MOSI/ADDR1 pin either to Table 34. Address Bit Sequence Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 1 1 0 ADDR1 (set by the ADDR0 (set by the R/W MOSI/ADDR1 pin) SS/ADDR0 pin) Table 35. I2C Slave Addresses Slave Address (Eight Bits, Slave Address (Seven Bits, MOSI/ADDR1 SS/ADDR0 Read/Write1 Including R/W Bit) Excluding R/W Bit) 0 0 0 0x70 0x38 0 0 1 0x71 0x38 0 1 0 0x72 0x39 0 1 1 0x73 0x39 1 0 0 0x74 0x3A 1 0 1 0x75 0x3A 1 1 0 0x76 0x3B 1 1 1 0x77 0x3B 1 0 = write, 1 = read. Rev. D | Page 44 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Addressing Figure 28 shows the timing of an I2C single word write operation, Figure 29 shows the timing of an I2C burst mode write operation, Initially, each device on the I2C bus is in an idle state and monitors and Figure 30 shows an I2C burst mode read operation. the SDA and SCL lines for a start condition and the proper address. The I2C master initiates a data transfer by establishing a start Stop and start conditions can be detected at any stage during condition, defined by a high-to-low transition on SDA where SCL the data transfer. If these conditions are asserted out of sequence remains high. This indicates that an address/data stream follows. with normal read and write operations, the slave I2C port of the All devices on the bus respond to the start condition and shift ADAU1452/ADAU1451/ADAU1450 immediately jumps to the the next eight bits (the 7-bit address plus the R/W bit), MSB first. idle condition. During a given SCL high period, issue only one The device that recognizes the transmitted address responds by start condition and one stop condition, or a single stop condition pulling the data line low during the ninth clock pulse. This ninth followed by a single start condition. If the user issues an invalid bit is known as an acknowledge bit. All other devices withdraw subaddress, the ADAU1452/ADAU1451/ADAU1450 do not issue from the bus at this point and return to the idle condition. an acknowledge and return to the idle condition. The R/W bit determines the direction of the data. A Logic 0 on Note the following conditions: the LSB of the first byte means that the master writes information • Do not issue an autoincrement (burst) write command that to the peripheral, whereas a Logic 1 means that the master reads exceeds the highest subaddress in the memory. information from the peripheral after writing the subaddress and • Do not issue an autoincrement (burst) write command that repeating the start address. A data transfer occurs until a stop writes to subaddresses that are not defined in the Global condition is encountered. A stop condition occurs when SDA RAM and Control Register Map section. transitions from low to high when SCL is held high. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 SCLK/SCL DEVICE ADDRESS BYTE SUBADDRESS BYTE 1 SUBADDRESS BYTE 2 MISO/SDA 0 1 1 1 0 ADDR1 ADDR0 R/W [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] START ACK ACK ACK (SLAVE) (SLAVE) (SLAVE) 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 SCLK/SCL DATA BYTE 1 DATA BYTE 2 MISO/SDA [7] [6] [5] [4] [3] [2] [1] [0] A(SCLKAVE[7)] [6] [5] [4] [3] [2] [1] [0] A(SCLKAVES)TOP 11486-030 Figure 28. I2C Slave Single Word Write Operation (Two Bytes) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 SCLK/SCL DEVICE ADDRESS BYTE SUBADDRESS BYTE 1 SUBADDRESS BYTE 2 MISO/SDA 0 1 1 1 0 ADDR1 ADDR0 R/W [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] START ACK ACK ACK (SLAVE) (SLAVE) (SLAVE) 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 SCLK/SCL DATA BYTE 1 DATA BYTE 2 DATA BYTE N MISO/SDA [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] A(SCLKAVE) A(SCLKAVE) A(SCLKAVE)STOP 11486-031 Figure 29. I2C Slave Burst Mode Write Operation (N Bytes) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 SCLK/SCL DEVICE ADDRESS BYTE SUBADDRESS BYTE 1 SUBADDRESS BYTE 2 MISO/SDA 0 1 1 1 0 ADDR1 ADDR0 R/W [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] START ACK ACK ACK (SLAVE) (SLAVE) (SLAVE) 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 SCLK/SCL CHIP ADDRESS BYTE DATA BYTE 1 FROM SLAVE DATA BYTE N FROM SLAVE MISO/SDA 0 1 1 1 0 ADDR1 ADDR0R/W [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] RSTEAPRETATED A(SCLKAVE) A(SCLKAVE) A(SCLKAVE)STOP 11486-032 Figure 30. I2C Slave Burst Mode Read Operation (N Bytes) Rev. D | Page 45 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet I2C Read and Write Operations to reverse and begin driving data back to the master. The master then responds every ninth pulse with an acknowledge pulse to Figure 31 shows the format of a single word write operation. the device. Every ninth clock pulse, the ADAU1452/ADAU1451/ADAU1450 issue an acknowledge by pulling SDA low. Figure 34 shows the format of a burst mode read sequence. This figure shows an example of a read from sequential single byte Figure 32 shows the simplified format of a burst mode write registers. The ADAU1452/ADAU1451/ADAU1450 increment sequence. This figure shows an example of a write to sequential the subaddress register after every byte because the requested single byte registers. The ADAU1452/ADAU1451/ADAU1450 subaddress corresponds to a register or memory area with a increment the subaddress register after every byte because the 1-byte word length. The ADAU1452/ADAU1451/ADAU1450 requested subaddress corresponds to a register or memory area always decode the subaddress and set the auto-increment with a 1-byte word length. circuit such that the address increments after the appropriate Figure 33 shows the format of a single word read operation. Note number of bytes. that the first R/W bit is 0, indicating a write operation. This is Figure 31 to Figure 34 use the following abbreviations: because the subaddress still needs to be written to set up the S = start bit internal address. After the ADAU1452/ADAU1451/ADAU1450 P = stop bit acknowledge the receipt of the subaddress, the master must issue AM = acknowledge by master a repeated start command followed by the chip address byte with AS = acknowledge by slave the R/W bit set to 1 (read). This causes the SDA pin of the device S CHIP ADDRESS, AS SUBADDRESS, AS SUBADDRESS, AS DATA AS DATA AS ... DATA AS P R/W = 0 HIGH LOW BYTE 1 BYTE 2 BYTE N SS H=O SWTSA RAT O BNITE,- WP O= RSDT OWPR BITITE,, AWMH E= RAEC EKANCOHW WLEODRGDE H BAYS M NA BSYTTEERS, .AS = ACKNOWLEDGE BY SLAVE. 11486-033 Figure 31. Simplified Single Word I2C Write Sequence S ADDCRHEIPSS, AS SUBAHDIDGRHESS, AS SUBALDODWRESS, AS AS AS AS AS ... AS AS P R/W = 0 DATA-WORD 1, DATA-WORD 1,DATA-WORD 2, DATA-WORD 2, DATA-WORD N, DATA-WORD N, BYTE 1 BYTE 2 BYTE 1 BYTE 2 BYTE 1 BYTE 2 SS H=O SWTSA RATN B NIT-W, PO R= DS TWORPIT BEI,T W, AHME R=E A ECAKCNHO WWLOERDDG HEA BSY T MWAOS TBEYRT,E ASS. ( =O TAHCEKRN OWWOLREDD LGEEN BGYT HSSL AAVREE. POSSIBLE, RANGING FROM ONE TO FIVE BYTES.) 11486-034 Figure 32. Simplified Burst Mode I2C Write Sequence S CHIP ADDRESS, AS SUBADDRESS, AS SUBADDRESS, AS S CHIP ADDRESS, AS DATA AM DATA AM ... DATA AM P R/W = 0 HIGH LOW R/W = 1 BYTE 1 BYTE 2 BYTE N SS H=O SWTSA RAT O BNITE,- WP O= RSDT OWPR BITITE,, AWMH E= RAEC EKANCOHW WLEODRGDE H BAYS M NA BSYTTEERS, .AS = ACKNOWLEDGE BY SLAVE. 11486-035 Figure 33. Simplified Single Word I2C Read Sequence S ADDCRHEIPSS, AS SUBAHDIDGRHESS, AS SUBALDODWRESS, AS S ADDCRHEIPSS, AS AM AM ... AM AM P R/W = 0 R/W = 1 DATA-WORD 1, DATA-WORD 1, DATA-WORD N, DATA-WORD N, BYTE 1 BYTE 2 BYTE 1 BYTE 2 SS H=O SWTSA RATN B NIT-W, PO R= DS TWORPIT BEI,T W, AHME R=E A ECAKCNHO WWLOERDDG HEA BSY T MWAOS TBEYRT,E ASS. ( =O TAHCEKRN OWWOLREDD LGEEN BGYT HSSL AAVREE. POSSIBLE, RANGING FROM ONE TO FIVE BYTES.) 11486-036 Figure 34. Simplified Burst Mode I2C Read Sequence Rev. D | Page 46 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 SPI Slave Port There is only one chip address available in SPI mode. The 7-bit By default, the slave port is in I2C mode, but it can be put into chip address is 0b0000000. The LSB of the first byte of an SPI SPI control mode by pulling SS/ADDR0 low three times. This transaction is an R/W bit. This bit determines whether the can be done either by toggling the SS/ADDR0 successively communication is a read (Logic Level 1) or a write (Logic Level 0). between logic high and logic low states, or by performing three This format is shown in Table 36. dummy writes to the SPI port, writing any arbitrary data to any Table 36. SPI Address and Read/Write Byte Format arbitrary subaddress (the slave port does not acknowledge these Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 three writes). After the SS/ADDR0 is toggled three times, data 0 0 0 0 0 0 0 R/W can be written to or read from the IC. An example of dummy writing is shown in Figure 35. When set in SPI slave mode, the The 16-bit subaddress word is decoded into a location in one of only way to revert back to I2C slave mode is by executing a full the registers. This subaddress is the location of the appropriate hardware reset using the RESET pin, or by power cycling the register. The MSBs of the subaddress are zero padded to bring power supplies. the word to a full 2-byte length. The SPI port uses a 4-wire interface, consisting of the SS, MOSI, The format for the SPI communications slave port is commonly MISO, and SCLK signals, and the SPI port is always a slave port. known as SPI Mode 3, where clock polarity (CPOL) = 1 and The SS signal goes low at the beginning of a transaction and high clock phase (CPHA) = 1 (see Figure 36). The base value of the at the end of a transaction. The SCLK signal latches the MOSI clock is 1. Data is captured on the rising edge of the clock, and signal on a low-to-high transition. MISO data is shifted out of the data is propagated on the falling edge. device on the falling edge of SCLK and must be clocked into a receiving device, such as a microcontroller, on the SCLK rising The maximum read and write speed for the SPI slave port is edge. The MOSI signal carries the serial input data, and the 22 MHz, but this speed is valid only after the PLL is locked. MISO signal carries the serial output data. The MISO signal Before the PLL locks, the maximum clock rate in the chip is remains three-state until a read operation is requested. This limited to the frequency of the input clock to the PLL. Nominally, allows other SPI-compatible peripherals to share the same MISO this frequency is 3.072 MHz. Therefore, the SPI clock must not line. All SPI transactions have the same basic format shown in exceed 3.072 MHz until the PLL lock completes. For an SPI Table 37. A timing diagram is shown in Figure 9. Write all data read, there is also an additional delay before the data is ready to MSBs first. transmit. An SPI read must wait for eight MCLK cycles after the register address is transmitted before transmitting the clocks to read the data. When the PLL is locked, this delay is so small that it can be ignored. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SS/ADDR0 SCLK/SCL MOSI/ADDR1 11486-038 Figure 35. Example of SPI Slave Mode Initialization Sequence Using Dummy Writes Table 37. Generic Control Word Sequence Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 and Subsequent Bytes Chip Address[6:0], R/W Subaddress[15:8] Subaddress[7:0] Data Data Rev. D | Page 47 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet CPOL = 0 SCLK CPOL = 1 SS CYCLE # 1 2 1 2 1 2 1 2 CPHA = 0 MISO Z 1 2 3 4 5 6 7 8 Z MOSI Z 1 2 3 4 5 6 7 8 Z CYCLE # 1 2 3 4 5 6 7 8 CPHA = 1 MISO Z 1 2 3 4 5 6 7 8 Z MOSI Z 1 2 3 4 5 6 7 8 Z 11486-037 Figure 36. Clock Polarity and Phase for SPI Slave Port Rev. D | Page 48 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 A sample timing diagram for a multiple word SPI write operation the addresses and the R/W bit, and subsequent bytes carry the to a register is shown in Figure 37. A sample timing diagram of data. A sample timing diagram of a multiple word SPI read a single word SPI read operation is shown in Figure 38. The operation is shown in Figure 39. In Figure 37 to Figure 39, MISO/SDA pin transitions from being three-state to being driven rising edges on SCLK/SCL are indicated with an arrow, at the beginning of Byte 3. In this example, Byte 0 to Byte 2 contain signifying that the data lines are sampled on the rising edge. 0 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233343536373839 SS/ADDR0 SCLK/SCL MOSI/ADDR1 CHIP ADDRESS[6:0R]/WSUBADDRESS BYTE 1 SUBADDRESS BYTE 2 DATA BYTE 1 DATA BYTE 2 DATA BYTE N 11486-039 Figure 37. SPI Slave Write Clocking (Burst Write Mode, N Bytes) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SS/ADDR0 SCLK/SCL MOSI/ADDR1 CHIP ADDRESS[6:0] SUBADDRESS BYTE 1 SUBADDRESS BYTE 2 R/W MISO/SDA DATA BYTE 1 DATA BYTE 2 11486-040 Figure 38. SPI Slave Read Clocking (Single Word Mode, Two Bytes) 0 1 2 3 4 5 6 7 8 9101112131415161718192021222324252627282930313233343536373839 SS/ADDR0 SCLK/SCL MOSI/ADDR1 CHIP ADDRESS[6:0] SUBADDRESS BYTE 1 SUBADDRESS BYTE 2 R/W MISO/SDA DATA BYTE 1 DATA BYTE 2 DATA BYTE N 11486-041 Figure 39. SPI Slave Read Clocking (Burst Read Mode, N Bytes) Rev. D | Page 49 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet MASTER CONTROL PORTS The SPI master interface has been tested with EEPROM, flash, and serial RAM devices and has been confirmed to work in all cases. The device contains a combined I2C and SPI master control port that is accessible through a common interface. The master port When the data rate is very high on the SPI master interface (at can be enabled through a self boot operation or directly from 10 MHz or higher), a condition may arise where there is a high the DSP core. The master control port can buffer up to 128 bits level of current draw on the IOVDD supply, which can lead to of data per single interrupt period. The smallest data transfer sagging of the internal IOVDD supply. To avoid potential issues, unit for both bus interfaces is one byte, and all transfers are 8-bit design the PCB such that the traces connecting the SPI master aligned. No error detection is supported, and single master interface to external devices are kept as short as possible, and the operation is assumed. Only one bus interface protocol (I2C or slew rate and drive strength for SPI master interface pins are kept SPI) can be used at a time. to a minimum to keep current draw as low as possible. Keeping IOVDD low (2.5 V or 1.8 V) also reduces the IOVDD current The master control port can be used for several purposes, as draw. follows: SigmaStudio generates EEPROM images for self boot systems, • Self boot the ADAU1452/ADAU1451/ADAU1450 from an requiring no manual SPI master port configuration or program- external serial EEPROM. ming on the part of the user. • Boot and control external slave devices such as codecs and I2C Master Interface amplifiers. • Read from and write to an external SPI RAM or flash The I2C master is 7-bit addressable and supports standard and memory. fast mode operation with speeds between 20 kHz and 400 kHz. The serial camera control bus (SCCB) and power management SPI Master Interface bus (PMBus) protocols are not supported. The SPI master supports up to seven slave devices (via the MPx Data transfers are 8-bit aligned. No error detection or correction is pins) and speeds between 2.3 kHz and 20 MHz. SPI Mode 0 implemented. The I2C master interface uses two general-purpose (CPOL = 0, CPHA = 0) and SPI Mode 3 (CPOL = 1, CPHA = 1) input/output pins, MP2 and MP3. See Table 39 for more are supported. Communication is assumed to be half duplex, information. and the SPI master does not support a 3-wire interface. There is no JTAG or SGPIO support. The SPI interface uses a minimum Place a pull-up resistor on each line connected to the SDA and of four general-purpose input/output pins of the processor and SCL pins. The value of the pull-up resistor depends on the bus up to six additional MPx pins for additional slave select signals (SS). capacitance load on the bus. See the standard I2C specifications See Table 38 for more information. document, published by Philips (NXP) Semiconductors, for guidance on resistor selection. A value of 2 kΩ is a good average The SPI master clock frequency can range between 2.3 kHz and value for many systems. Ensure that the voltage on these signal 20 MHz. JTAG and SGPIO are not supported. Data transfers are lines does not exceed IOVDD (1.8 V − 5% to 3.3 V + 10%). 8-bit aligned. By default, the SPI master port is in Mode 3 (CPOL = 1, CPHA = 1), which matches the mode of the SPI slave The SDA master (SDA_M) and SCL master (SCL_M) port pins port. The SPI master port can be configured to operate in Mode 0 can safely sink 8 mA of current in I2C mode, and can properly (CPOL = 0, CPHA = 0) in the DSP program. No error detection operate within the standard I2C specifications. See Table 14 for or handling is implemented. Single master operation is assumed; details. therefore, no other master devices can exist on the same SPI bus. Table 38. SPI Master Interface Pin Functionality SPI Master Pin Name Function Description MOSI_M/MP1 MOSI SPI master port data output. Sends data from the SPI master port to slave devices on the SPI master bus. SCL_M/SCLK_M/MP2 SCLK SPI master port serial clock. Drives the clock signal to slave devices on the SPI master bus. SDA_M/MISO_M/MP3 MISO SPI master port data input. Receives data from slave devices on the SPI master bus. SS_M/MP0 SS SPI master port slave select. Acts as the primary slave select signal to slave device on the SPI master bus. MP4 to MP13 SS SPI master port slave select. These additional MPx pins can be configured to act as secondary slave select signals to additional slave devices on the SPI master bus. Up to seven slave devices, one per pin, are supported. Rev. D | Page 50 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Table 39. I2C Master Interface Pin Functionality I2C Master Pin Name Function Description SCL_M/SCLK_M/MP2 SCL I2C master port serial clock. This pin functions as an open collector output and drives a serial clock to slave devices on the I2C bus. The line connected to this pin must have a pull-up resistor to IOVDD. SDA_M/MISO_M/MP3 SDA I2C master port serial data. This pin functions as a bidirectional open collector data line between the I2C master port and slave devices on the I2C bus. The line connected to this pin must have a pull-up resistor to IOVDD. Rev. D | Page 51 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet SELF BOOT When self booting from I2C, the chip assumes the following: The master control port is capable of booting the device from • The slave EEPROM has I2C Address 0x50. a single EEPROM by connecting the SELFBOOT pin to logic • The slave EEPROM has 16-bit addressing, giving it a size of high (IOVDD) and powering up the power supplies when between 16 kb and 512 kb. the RESET pin is pulled high. This initiates a self boot operation, • The slave EEPROM supports standard mode clock in which the master control port downloads all required frequencies of 100 kHz and lower (a majority of the self boot memory and register settings and automatically starts executing operation uses a much higher clock frequency, but the the DSP program without requiring external intervention or initial transactions are performed at a slower frequency). supervision. A self boot operation can also be triggered when • The data stored in the slave EEPROM follows the format the device is already in operation by initiating a rising edge of described in the EEPROM Self Boot Data Format section. the RESET pin when the SELFBOOT pin is held high. When the • The slave EEPROM can be accessed immediately after it is self boot operation begins, the state of the SS_M/MP0 pin powered, with no manual configuration required. determines whether the SPI master or the I2C master carries out Self Boot Failure the self boot operation. If the SS_M/MP0 pin is connected to logic low, the I2C master port carries out the self boot operation. The SPI or I2C master port attempts to self boot from the Otherwise, connect this pin to the slave select pin of the external EEPROM three times. If all three self boot attempts fail, the slave device. The SPI master port then carries out the self boot SigmaDSP core issues a software panic and then enters a sleep operation. state. During a self boot operation, the panic manager is unable to output a panic flag on a multipurpose pin. Therefore, the When self booting from SPI, the chip assumes the following: only way to debug a self boot failure is by reading back the • The slave EEPROM is selected via the SS_M/MP0 pin. status of Register 0xF427 (PANIC_FLAG) and Register 0xF428 • The slave EEPROM has 16- or 24-bit addressing, giving it (PANIC_CODE). The contents of Register 0xF428 indicate the a total memory size of between 4 kb and 64 Mb. nature of the failure. • The slave EEPROM supports serial clock frequencies down EEPROM Self Boot Data Format to 1 MHz or lower (a majority of the self boot operation uses The self boot EEPROM image is generated using the SigmaStudio a much higher clock frequency, but the initial transactions software; which means that the user does not need to manually are performed at a slower frequency). create the data that is stored in the EEPROM. However, for • The data stored in the slave EEPROM follows the format reference, the details of the data format are described in this described in the EEPROM Self Boot Data Format section. section. • The data is stored in the slave EEPROM with the MSB first. • The slave EEPROM supports SPI Mode 3. The EEPROM self boot format consists of a fixed header, an • The slave EEPROM sequential read operation has the arbitrary number of variable length blocks, and a fixed footer. The blocks themselves consist of a fixed header and a block of command of 0x03. data with a variable length. Each data block can be placed anywhere • The slave EEPROM can be accessed immediately after it is in the DSP memory through configuration of the block header. powered up, with no manual configuration required. Rev. D | Page 52 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Header Format  Two MEM bits that select the target data memory bank (0x0 = Data Memory 0, 0x1 = Data Memory 1, 0x2 = The self boot EEPROM header consists of 16 bytes of data, starting program memory). at the beginning of the internal memory of the slave EEPROM  16-bit base address that sets the memory address at which (Address 0). The header format (see Figure 40) consists of the following: the master port starts writing when loading data from the block into memory.  8-bit Sentinel 0xAA (shown in Figure 40 as 0b10101010)  16-bit data length that defines the number of 4-byte data-  24-bit address indicating the byte address of the header of words to be written. the first block (normally this is 0x000010, which is the  16-bit jump address that tells the DSP core at which address immediately following the header) address in program memory it must begin execution when  64-bit PLL configuration (PLL_CHECKSUM = the self boot operation is complete. The jump address bits PLL_FB_DIV + MCLK_OUT + PLL_DIV) are ignored unless the LST bit is set to 0b1. Data Block Format  Arbitrary number of packets of 32-bit data. The number of packets is defined by the 16-bit data length. Following the header, several data blocks are stored in the EEPROM memory (see Figure 41). Footer Format Each data block consists of eight bytes that configure the length After all the data blocks, a footer signifies the end of the self boot and address of the data, followed by a series of 4-byte data packets. EEPROM memory (see Figure 42). The footer consists of a 64-bit Each block consists of the following: checksum, which is the sum of the header and all blocks and all data as 32-bit words.  One LST bit, which signals the last block before the footer. After the self boot operation completes, the checksum of the down- LST = 0b1 indicates the last block; LST = 0b0 indicates that loaded data is calculated and the panic manager signals if it does additional blocks are still to follow. not match the checksum in the EEPROM. If the checksum is set  13 bits that are reserved for future use. Set these bits to 0b0. to 0 decimal, the checksum checking is disabled. BYTE 0 BYTE 1 BYTE 2 BYTE 3 1 0 1 0 1 0 1 0 ADDRESS OF FIRST BOOT BLOCK BYTE 4 BYTE 5 BYTE 6 BYTE 7 0x00 PLL_DIV 0x00 PLL_FB_DIV BYTE 8 BYTE 9 BYTE 10 BYTE 11 0x00 PLL_CHECKSUM 0x00 MCLK_OUT BYTE 12 BYTE 1E3EPROM SPEED CONFIGURATBIOYTNE 14 BYTE 15 11486-042 Figure 40. Self Boot EEPROM Header Format BYTE 0 BYTE 1 BYTE 2 BYTE 3 LST RESERVED MEM BASE ADDRESS BYTE 4 BYTE 5 BYTE 6 BYTE 7 DATA LENGTH JUMP ADDRESS BYTE 8 BYTE 9 BYTE 10 BYTE 11 DATA-WORD 1 BYTE 12 BYTE 13 BYTE 14 BYTE 15 DATA-WORD 2 CONTINUED UNTIL LAST WORD IS REACHED… FOURTH TO LAST BYTE THIRDDA TTAO-W LAOSRTD BNYTE SECOND TO LAST BYTE LAST BYTE 11486-043 Figure 41. Self Boot EEPROM Data Block Format BYTE 0 BYTE 1 BYTE 2 BYTE 3 FIRST FOUR BYTES OF CHECKSUM BYTE 4 BYTE 5LAST FOUR BYTES OF CHECKBSYUTME 6 BYTE 7 11486-044 Figure 42. Self Boot EEPROM Footer Format Rev. D | Page 53 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Considerations When Using a 1 Mb I2C Self Boot EEPROM AUDIO SIGNAL ROUTING Because of the way I2C addressing works, 1 Mb of I2C EEPROM A large number of audio inputs and outputs are available in the memory can be divided, with a portion of its address space at device, and control registers are available for configuring the way in Chip Address 0x50; another portion of the memory can be located which the audio is routed between different functional blocks. at a different address (for example, Chip Address 0x51). The The ADAU1450 does not include an S/PDIF receiver, S/PDIF memory allocation varies, depending on the EEPROM design. transmitter, or ASRCs, so signals cannot be routed to or from In cases when the EEPROM memory is divided, the memory those subsystems. portion that resides at a different chip address must be handled as though it exists in a separate EEPROM. All input channels are accessible by both the DSP core and the ASRCs. Each ASRC can connect to a pair of audio channels Considerations When Using Multiple EEPROMs on the from any of the input sources or from the DSP_TO_ASRC SPI Master Bus channels of the DSP core. The serial outputs can obtain their When multiple EEPROMs are connected on the same SPI master data from a number of sources, including the DSP core, ASRCs, bus, the self boot mechanism works only with the first EEPROM. PDM microphones, S/PDIF receiver, or directly from the serial inputs. See Figure 43 for an overview of the audio routing matrix with its available audio data connections. To route audio to and from the DSP core, select the appropriate input and output cells in SigmaStudio. These cells can be found in the I/O folder of the SigmaStudio algorithm toolbox. Rev. D | Page 54 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 DSP CORE ADAU1452/ADAU1451 S/PDIF OUT 2 CH DSP CORE S/PDIF SDATA_IN0 SERIAL IINNPPUUTT 01 5TO 16 CH Tx SPDIFOUT INPUT (2 CH TO 16 CH) PORT 0 OUTPUT 0 TO SDATA_IN1 SERIAL IINNPPUUTT 1361 TO 16 CH OUTPUT 15 16 CH INPUT (2 CH TO 16 CH) PORT 1 OSUETRPIAULT SDATA_OUT0 PORT 0 (2 CH TO 16 CH) SDATA_IN2 SINERPUIATL IINNPPUUTT 3329 TO 8 CH OOUUTTPPUUTT 1361 TO 16 CH (2 CH TO 8 CH) PORT 2 SERIAL SDATA_OUT1 OUTPUT SDATA_IN3 SERIAL IINNPPUUTT 4407 TO 8 CH PORT 1 (2 CH TO 16 CH) (2 CH TO 8 CH) PINOPRUTT 3 OOUUTTPPUUTT 3329 TO 8 CH MP6 PMDIMC 4 CH OSPUEOTRRPITAU L2T S(2D CAHT AT_OO 8U CT2H) MP7 INPUT OUTPUT 40 TO OUTPUT 47 8 CH SPDIFIN S/PRDxIF 2 CH OSPUEOTRRPITAU L3T S(2D CAHT AT_OO 8U CT3H) DSP TO ASRC(16 CHANNELS) 16 CH ASRCs 16 CH ASRC TO DSP(16 CHANNELS) ASRC OUTPUTS INPUT 0 TO INPUT 15 INPUT 16 TO INPUT 31 INPUT 32 TO INPUT 39 INPUT 40 TO INPUT 47CROPHONE INPUTSS/PDIF RECEIVER 11668 CCCHHH IINNINPPPUUUTTT 13 620 TTTOOO IIINNNPPPUUUTTT 331195 (×8) A(1S6R CCH OAUNTNPEULTSS) 16 CH PDM MI 8 CH INPUT 40 TO INPUT 47 16 CH PDM MICROPHONE (2 CH × 8 ASRCS) 4 CH INPUTS HHHHHH CCCCCC 2 CH S/PDIF RECEIVER 6 6 8 8 4 2 11 11486-045 Figure 43. Audio Routing Overview Rev. D | Page 55 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Serial Audio Inputs to DSP Core Table 40. Serial Input Pin Mapping to SigmaStudio Input Cells The 48 serial input channels are mapped to four audio input Serial Input Pin Channels in SigmaStudio cells in SigmaStudio. Each input cell corresponds to one of the SDATA_IN0 0 to 15 serial input pins (see Table 40). SDATA_IN1 16 to 31 SDATA_IN2 32 to 39 Depending on whether the serial port is configured in 2-channel, SDATA_IN3 40 to 47 4-channel, 8-channel, or 16-channel mode, the available channels in SigmaStudio change. The channel count for each serial port is configured in the SERIAL_BYTE_x_0 registers, Bits[2:0] (TDM_MODE), at Address 0xF200 to Address 0xF21C (in increments of 0x4). Figure 44 shows how the input pins map to the input cells in SigmaStudio, including their graphical appearance in the software. Table 41. Detailed Serial Input Mapping to SigmaStudio Input Channels1 Position in I2S Stream Input Channel Serial Input Pin (2-Channel) Position in TDM4 Stream Position in TDM8 Stream Position in TDM16 Stream in SigmaStudio SDATA_IN0 Left 0 0 0 0 SDATA_IN0 Right 1 1 1 1 SDATA_IN0 N/A 2 2 2 2 SDATA_IN0 N/A 3 3 3 3 SDATA_IN0 N/A N/A 4 4 4 SDATA_IN0 N/A N/A 5 5 5 SDATA_IN0 N/A N/A 6 6 6 SDATA_IN0 N/A N/A 7 7 7 SDATA_IN0 N/A N/A N/A 8 8 SDATA_IN0 N/A N/A N/A 9 9 SDATA_IN0 N/A N/A N/A 10 10 SDATA_IN0 N/A N/A N/A 11 11 SDATA_IN0 N/A N/A N/A 12 12 SDATA_IN0 N/A N/A N/A 13 13 SDATA_IN0 N/A N/A N/A 14 14 SDATA_IN0 N/A N/A N/A 15 15 SDATA_IN1 Left 0 0 0 16 SDATA_IN1 Right 1 1 1 17 SDATA_IN1 N/A 2 2 2 18 SDATA_IN1 N/A 3 3 3 19 SDATA_IN1 N/A N/A 4 4 20 SDATA_IN1 N/A N/A 5 5 21 SDATA_IN1 N/A N/A 6 6 22 SDATA_IN1 N/A N/A 7 7 23 SDATA_IN1 N/A N/A N/A 8 24 SDATA_IN1 N/A N/A N/A 9 25 SDATA_IN1 N/A N/A N/A 10 26 SDATA_IN1 N/A N/A N/A 11 27 SDATA_IN1 N/A N/A N/A 12 28 SDATA_IN1 N/A N/A N/A 13 29 SDATA_IN1 N/A N/A N/A 14 30 SDATA_IN1 N/A N/A N/A 15 31 SDATA_IN2 Left 0 0 0 32 SDATA_IN2 Right 1 1 1 33 SDATA_IN2 N/A 2 2 2 34 SDATA_IN2 N/A 3 3 3 35 SDATA_IN2 N/A N/A 4 4 36 SDATA_IN2 N/A N/A 5 5 37 SDATA_IN2 N/A N/A 6 6 38 SDATA_IN2 N/A N/A 7 7 39 Rev. D | Page 56 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Position in I2S Stream Input Channel Serial Input Pin (2-Channel) Position in TDM4 Stream Position in TDM8 Stream Position in TDM16 Stream in SigmaStudio SDATA_IN3 Left 0 0 0 40 SDATA_IN3 Right 1 1 1 41 SDATA_IN3 N/A 2 2 2 42 SDATA_IN3 N/A 3 3 3 43 SDATA_IN3 N/A N/A 4 4 44 SDATA_IN3 N/A N/A 5 5 45 SDATA_IN3 N/A N/A 6 6 46 SDATA_IN3 N/A N/A 7 7 47 1 N/A = not applicable. SDATA_IN0 SERIAL INPUT 0 TO INPUT 15 16 CH INPUT (2 CH TO 16 CH) PORT 0 SDATA_IN1 SERIAL INPUT 16 TO INPUT 31 16 CH INPUT (2 CH TO 16 CH) PORT 1 SDATA_IN2 SINEPRUIATL INPUT 32 TO INPUT 39 8 CH (2 CH TO 8 CH) PORT 2 (2 CSHD TAOT A8_ CINH3) SPINEOPRRUITAT L3 INPUT 40 TO INPUT 47 8 CH 11486-046 Figure 44. Serial Port Audio Input Mapping to DSP in SigmaStudio PDM Microphone Inputs to DSP Core S/PDIF Receiver Inputs to DSP Core The PDM microphone inputs are mapped to a single digital micro- The S/PDIF receiver must not be accessed directly in the DSP phone input cell in SigmaStudio (see Table 42 and Figure 45). The core because the S/PDIF receiver input is asynchronous to the corresponding hardware pins are configured in Register 0xF560 DSP core in most applications. Therefore, an ASRC is required. (DMIC_CTRL0) and Register 0xF561 (DMIC_CTRL1). See the Asynchronous Sample Rate Converter Input Routing section for details. Table 42. PDM Microphone Input Mapping to SigmaStudio Channels Table 43. S/PDIF Input Mapping to SigmaStudio Channels PDM Microphone Input Channel in Channel in S/PDIF Receiver S/PDIF Input Channels in PDM Data Channel SigmaStudio Data Stream SigmaStudio Left (DMIC_CTRL0) 0 Left 0 Right (DMIC_CTRL0) 1 Right 1 Left (DMIC_CTRL1) 2 Serial Audio Outputs from DSP Core Right (DMIC_CTRL1) 3 The 48 serial output channels are mapped to 48 separate audio output cells in SigmaStudio. Each audio output cell corresponds to a single output channel. The first 16 channels are mapped to MP6 PDM 4 CH MP7 INMPIUCT 11486-047 tShDeA STDAA_TOAU_TO1U pTin0 .p Tinh.e T fohlel onwexint g1 6ei cghhat ncnhealnsn aerles maraep mpeadp ptoed t htoe Figure 45. PDM Microphone Input Mapping to DSP in SigmaStudio the SDATA_OUT2 pin. The last eight channels are mapped to the SDATA_OUT3 pin (see Table 44 and Figure 46). Rev. D | Page 57 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Table 44. Serial Output Pin Mapping from SigmaStudio Channels1 Position in I2S Stream Position in Position in Position in Channel in SigmaStudio Serial Output Pin (2-Channel) TDM4 Stream TDM8 Stream TDM16 Stream 0 SDATA_OUT0 Left 0 0 0 1 SDATA_OUT0 Right 1 1 1 2 SDATA_OUT0 N/A 2 2 2 3 SDATA_OUT0 N/A 3 3 3 4 SDATA_OUT0 N/A N/A 4 4 5 SDATA_OUT0 N/A N/A 5 5 6 SDATA_OUT0 N/A N/A 6 6 7 SDATA_OUT0 N/A N/A 7 7 8 SDATA_OUT0 N/A N/A N/A 8 9 SDATA_OUT0 N/A N/A N/A 9 10 SDATA_OUT0 N/A N/A N/A 10 11 SDATA_OUT0 N/A N/A N/A 11 12 SDATA_OUT0 N/A N/A N/A 12 13 SDATA_OUT0 N/A N/A N/A 13 14 SDATA_OUT0 N/A N/A N/A 14 15 SDATA_OUT0 N/A N/A N/A 15 16 SDATA_OUT1 Left 0 0 0 17 SDATA_OUT1 Right 1 1 1 18 SDATA_OUT1 N/A 2 2 2 19 SDATA_OUT1 N/A 3 3 3 20 SDATA_OUT1 N/A N/A 4 4 21 SDATA_OUT1 N/A N/A 5 5 22 SDATA_OUT1 N/A N/A 6 6 23 SDATA_OUT1 N/A N/A 7 7 24 SDATA_OUT1 N/A N/A N/A 8 25 SDATA_OUT1 N/A N/A N/A 9 26 SDATA_OUT1 N/A N/A N/A 10 27 SDATA_OUT1 N/A N/A N/A 11 28 SDATA_OUT1 N/A N/A N/A 12 29 SDATA_OUT1 N/A N/A N/A 13 30 SDATA_OUT1 N/A N/A N/A 14 31 SDATA_OUT1 N/A N/A N/A 15 32 SDATA_OUT2 Left 0 0 0 33 SDATA_OUT2 Right 1 1 1 34 SDATA_OUT2 N/A 2 2 2 35 SDATA_OUT2 N/A 3 3 3 36 SDATA_OUT2 N/A N/A 4 4 37 SDATA_OUT2 N/A N/A 5 5 38 SDATA_OUT2 N/A N/A 6 6 39 SDATA_OUT2 N/A N/A 7 7 40 SDATA_OUT3 Left 0 0 0 41 SDATA_OUT3 Right 1 1 1 42 SDATA_OUT3 N/A 2 2 2 43 SDATA_OUT3 N/A 3 3 3 44 SDATA_OUT3 N/A N/A 4 4 45 SDATA_OUT3 N/A N/A 5 5 46 SDATA_OUT3 N/A N/A 6 6 47 SDATA_OUT3 N/A N/A 7 7 1 N/A = not applicable. Rev. D | Page 58 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 OUTPUT 0 TO OUTPUT 15 16CH SERIAL OUTPUT SDATA_OUT0 PORT 0 (2 CH TO 16 CH) OUTPUT 16 TO OUTPUT 31 16CH SERIAL SDATA_OUT1 OUTPUT PORT 1 (2 CH TO 16 CH) OUTPUT 32 TO OUTPUT 39 8CH SERIAL SDATA_OUT2 OUTPUT PORT 2 (2 CH TO 8 CH) OUTPUT 40 TO OUTPUT 47 8CH SERIAL SDATA_OUT3 OUTPUT PORT 3 (2 CH TO 8 CH) FROM SERIAL INPUTS, PDM MICS, S/PDIF RECEIVER, AND ASRCS 11486-049 Figure 46. DSP to Serial Output Mapping in SigmaStudio The data that is output from each serial output pin is also DSP S/PDIF OUT 0 DSP S/PDIF OUT 1 configurable, via the SOUT_SOURCEx registers, to originate S/PDIF Tx 0 fPrDomM omniec orof pthheo nfoel lionwpiuntgs ,s tohuer cSe/sP:D thIeF DreScPe,i tvheer, soerr itahl ei nApSuRtsC, tsh. e SS//PPDDIIFF RRxx 01 S/PDIF Tx 1 S/PTDxIF SPDIFOUT11486-051 These registers can be configured graphically in SigmaStudio, as Figure 48. S/PDIF Transmitter Source Selection shown in Figure 47. When the signal comes from the DSP core, use the S/PDIF SERIAL OUTPUT PORT 0 output cells in SigmaStudio. SOUT SOURCE 0 SOUT SOURCE 1 Table 45. S/PDIF Output Mapping from SigmaStudio Channels SOUT SOURCE 2 S/PDIF Output Channel in Channel in S/PDIF Transmitter SOUT SOURCE 3 SigmaStudio Data Stream SOUT SOURCE 4 0 Left SOUT SOURCE 5 1 Right SOUT SOURCE 6 SOUT SOURCE 7 SDATA_OUT0 11486-050 SD/SPPD2 ICCFHO ORUET Figure 47. Configuring the Serial Output Data Channels (SOUT_SOURCEx S/PDIF Registers) Graphically in SigmaStudio Tx SPDIFOUT ST/hPeD oIuFt Apuutd siiog nOaul topfu thtse fSro/PmD DIFS tPr aCnosrmei tttoe rS /cPaDn IcFo Tmrea nfrsommi tttheer FROM S/PDIF RECEIVER 11486-052 Figure 49. DSP to S/PDIF Transmitter Output Mapping in SigmaStudio DSP core or directly from the S/PDIF receiver. The selection is controlled by Register 0xF1C0 (SPDIFTX_INPUT). Rev. D | Page 59 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Asynchronous Sample Rate Converter Input Routing Any asynchronous input can be routed to the ASRCs to be DSP CORE resynchronized to a desired target sample rate (see Figure 50). S The source signals for any ASRC can come from any of the CH CH PUT srATeehScriRiesaiC lvm eisnr,e ,pae ounarcts sh ta,h waetno idtythai gol tifowt atfoh l1 eP6i nDD cphMSuaPt n -mctnhoiea-clAnrso nScpReahlnCso pa ncnaehsd ais nn ttwpnhueorotl ssou,.u gtTthhphe ute hSrt e/ecP haADraSenIR FenC ieglshs.. t DSP TO ASRC(16 CHANNELS) 16 ASRCs 16 ASRC TO DSP(16 CHANNELS) ASRC OUT H 16 CH INPUT 0 TO INPUT 15 C Asynchronous input signals (either serial inputs, PDM microphone 16 CH INPUT 16 TO INPUT 31 ASRC OUTPUTS 16 inputs, or the S/PDIF input) typically need to be routed to an ASRC 8 CH INPUT 32 TO INPUT 39 (×8) (16 CHANNELS) 8 CH INPUT 40 TO INPUT 47 16 CH and then synchronized to the DSP core rate. They are then available PDM MICROPHONE (2 CH × 8 ASRCS) 4 CH INPUTS fIonr t ihnep euxta tmo pthlee sDhSoPw nco irne Ffoigru prreo 5c1e,s stihneg t.w o channels from the 2 CH S/PDIF RECEIVER AADDAAUU11445521/ 11486-053 S/PDIF receiver are routed to one of the ASRCs and then to the Figure 50. Channel Routing to ASRC Inputs DSP core. For this example, the corresponding ASRC input selector register (Register 0xF100 to Register 0xF107, ASRC_INPUTx), DSP CORE Bits[2:0] (ASRC_SOURCE) is set to 0b011 to take the input from H the S/PDIF receiver. Likewise, the corresponding ASRC output C 6 rOaUte Tse_lRecAtoTrE rxeg, iBstitesr[ (3R:0e]g i(sAteSrR 0CxF_1R4A0T toE )R)e igsi ssteetr t 0ox 0Fb104170, A1 StoR C_ 1 C TO DSPHANNELS) synchronize the ASRC output data to the DSP core sample rate. ASRCs ASR(16 C (×8) 2 CH S/PDIF RECEIVER 11486-054 Figure 51. Example ASRC Routing for Asynchronous Input to the DSP Core Rev. D | Page 60 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 When the outputs of the ASRCs are required for processing in ASRC OUT 0 the SigmaDSP core, the ASRC input block must be selected in ASRC0 SigmaStudio (see Figure 52 and Figure 53). In the case of the ASRC OUT 1 ASRC OUT 2 ADAU1450, which has no ASRCs, the ASRC input cell does not ASRC1 ASRC OUT3 generate any data. ASRC OUT4 ASRC2 ASRC OUT 5 ASRC OUT 6 ASRC3 ASRC OUT 7 ASRC OUT 8 ASRC4 ASRC OUT 9 ASRC OUT 10 ASRC5 ASRC OUT 11 ASRC OUT 12 ASRC6 ASRC OUT 13 ASRC OUT 14 ASRC7 ASRC OUT 15 11486-056 Figure 53. Routing of ASRC Outputs to ASRC-to-DSP Input Cell in SigmaStudio 11486-055 Figure 52. Location of ASRC-to-DSP Input Cell in SigmaStudio Toolbox Rev. D | Page 61 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Asynchronous output signals (for example, serial outputs that 0 4 are slaves to an external, asynchronous device) typically are routed RC RC S S from the DSP core into the ASRCs, where they are synchronized O A O A T T to the serial output port that is acting as a slave to the external asynchronous master device. 1 5 C C R R In the example shown in Figure 54, two (or more) audio channels AS AS O O from the DSP core are routed to one (or more) of the ASRCs T T and then to the serial outputs. For this example, the corresponding ASRC input selector register (Address 0xF100 to Address 0xF107 C2 C6 R R (ASRC_INPUTx), Bits[2:0] (ASRC_SOURCE)) is set to 0b010 to AS AS O O take the data from the DSP core, and the corresponding ASRC T T output rate selector register (Address 0xF140 to Address 0xF147 3 7 (ASRC_OUT_RATEx), Bits[3:0] (ASRC_RATE)) is set to one of RC RC S S th e fo0lblo00w0i1n gto: synchronize the ASRC output data to SDATA_OUT0 TO A TO A 11486-059  0b0010 to synchronize the ASRC output data to SDATA_OUT1 Figure 56. Routing of DSP-to-ASRC Output Cells in SigmaStudio to ASRC Inputs  0b0011 to synchronize the ASRC output data to SDATA_OUT2 0b0100 to synchronize the ASRC output data to SDATA_OUT3 The ASRCs can also be used to take asynchronous inputs and convert them to a different sample rate without doing any Next, the corresponding serial output port data source register processing in the DSP core. (Address 0xF180 to Address 0xF197 (SOUT_SOURCEx), Bits[2:0] ASRCs (SOUT_SOURCE)) must be set to 0b011 to receive the data from the ASRC outputs, and Bits[5:3] (SOUT_ASRC_SELECT) 16 CH INPUT 0 TO INPUT 15 must be configured to select the correct ASRC from which to ASRC OUTPUTS (16 CHANNELS) (×8) receive the output data. 16 CH (2 CH × 8 ASRCs) CH DSP CORE 11486-060 DSP TO ASRC(16 CHANNELS) 16 ASRCs Cinotenrffiagcuer eiFn itg htuhere eA 5S7Si.Rg EmCxa amrSoptuuletd iAniSogR sCroe Rfgotiwusttaienrrges, (Busysepiena sgFs iiang gus irDmeS Pp5 9lCe)o .gr er aphical Asynchronous Sample Rate Converter Output Routing (×8) ASRC OUTPUTS (16 CHANNELS) The outputs of the ASRCs are always available at both the DSP (2 CH 1×6 8 C AHSRCS) 11486-057 croourete a AndS RthCe osuertpiaul to duattpau ttos. sNeroi aml oanuutpaul tr ochuatinnnge ilss ,n ceocnefsisgaurrye. To Figure 54. Example ASRC Routing for Asynchronous Serial Output from Register 0xF180 to Register 0xF197 (SOUT_SOURCEx) the DSP Core accordingly. For more information, see Figure 58 and Table 46. When signals must route from the DSP core to the ASRCs, use DSP CORE the DSP-to-ASRC output cell in SigmaStudio (see Figure 55). In the case of the ADAU1450, which has no ASRCs, data routed 16 CH to the DSP-to-ASRC output cells are lost. PS) ASRCs C TO DSHANNEL RC AS(16 ASRC OUTPUTS (16 CHANNELS) (×8) 16 CH (2 CH × 8 ASRCs) 11486-062 Figure 58. ASRC Outputs 11486-058 Figure 55. Location of DSP-to-ASRC Output Cell in SigmaStudio Toolbox Rev. D | Page 62 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 11486-061 Figure 59. Configuring the ASRC Input Source and Target Rate in SigmaStudio Rev. D | Page 63 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Audio Signal Routing Registers Overview An overview of the registers related to audio routing is listed in Table 46. See the Audio Signal Routing Registers section for details. Table 46. Audio Routing Matrix Registers Address Register Description 0xF100 ASRC_INPUT0 ASRC input selector (ASRC 0, Channel 0 and Channel 1) 0xF101 ASRC_INPUT1 ASRC input selector (ASRC 1, Channel 2 and Channel 3) 0xF102 ASRC_INPUT2 ASRC input selector (ASRC 2, Channel 4 and Channel 5) 0xF103 ASRC_INPUT3 ASRC input selector (ASRC 3, Channel 6 and Channel 7) 0xF104 ASRC_INPUT4 ASRC input selector (ASRC 4, Channel 8 and Channel 9) 0xF105 ASRC_INPUT5 ASRC input selector (ASRC 5, Channel 10 and Channel 11) 0xF106 ASRC_INPUT6 ASRC input selector (ASRC 6, Channel 12 and Channel 13) 0xF107 ASRC_INPUT7 ASRC input selector (ASRC 7, Channel 14 and Channel 15) 0xF140 ASRC_OUT_RATE0 ASRC output rate (ASRC 0, Channel 0 and Channel 1) 0xF141 ASRC_OUT_RATE1 ASRC output rate (ASRC 1, Channel 2 and Channel 3) 0xF142 ASRC_OUT_RATE2 ASRC output rate (ASRC 2, Channel 4 and Channel 5) 0xF143 ASRC_OUT_RATE3 ASRC output rate (ASRC 3, Channel 6 and Channel 7) 0xF144 ASRC_OUT_RATE4 ASRC output rate (ASRC 4, Channel 8 and Channel 9) 0xF145 ASRC_OUT_RATE5 ASRC output rate (ASRC 5, Channel 10 and Channel 11) 0xF146 ASRC_OUT_RATE6 ASRC output rate (ASRC 6, Channel 12 and Channel 13) 0xF147 ASRC_OUT_RATE7 ASRC output rate (ASRC 7, Channel 14 and Channel 15) 0xF180 SOUT_SOURCE0 Source of data for serial output port (Channel 0 and Channel 1) 0xF181 SOUT_SOURCE1 Source of data for serial output port (Channel 2 and Channel 3) 0xF182 SOUT_SOURCE2 Source of data for serial output port (Channel 4 and Channel 5) 0xF183 SOUT_SOURCE3 Source of data for serial output port (Channel 6 and Channel 7) 0xF184 SOUT_SOURCE4 Source of data for serial output port (Channel 8 and Channel 9) 0xF185 SOUT_SOURCE5 Source of data for serial output port (Channel 10 and Channel 11) 0xF186 SOUT_SOURCE6 Source of data for serial output port (Channel 12 and Channel 13) 0xF187 SOUT_SOURCE7 Source of data for serial output port (Channel 14 and Channel 15) 0xF188 SOUT_SOURCE8 Source of data for serial output port (Channel 16 and Channel 17) 0xF189 SOUT_SOURCE9 Source of data for serial output port (Channel 18 and Channel 19) 0xF18A SOUT_SOURCE10 Source of data for serial output port (Channel 20 and Channel 21) 0xF18B SOUT_SOURCE11 Source of data for serial output port (Channel 22 and Channel 23) 0xF18C SOUT_SOURCE12 Source of data for serial output port (Channel 24 and Channel 25) 0xF18D SOUT_SOURCE13 Source of data for serial output port (Channel 26 and Channel 27) 0xF18E SOUT_SOURCE14 Source of data for serial output port (Channel 28 and Channel 29) 0xF18F SOUT_SOURCE15 Source of data for serial output port (Channel 30 and Channel 31) 0xF190 SOUT_SOURCE16 Source of data for serial output port (Channel 32 and Channel 33) 0xF191 SOUT_SOURCE17 Source of data for serial output port (Channel 34 and Channel 35) 0xF192 SOUT_SOURCE18 Source of data for serial output port (Channel 36 and Channel 37) 0xF193 SOUT_SOURCE19 Source of data for serial output port (Channel 38 and Channel 39) 0xF194 SOUT_SOURCE20 Source of data for serial output port (Channel 40 and Channel 41) 0xF195 SOUT_SOURCE21 Source of data for serial output port (Channel 42 and Channel 43) 0xF196 SOUT_SOURCE22 Source of data for serial output port (Channel 44 and Channel 45) 0xF197 SOUT_SOURCE23 Source of data for serial output port (Channel 46 and Channel 47) 0xF1C0 SPDIFTX_INPUT S/PDIF transmitter data selector Rev. D | Page 64 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 SERIAL DATA INPUT/OUTPUT The maximum sample rate for the serial audio data on the serial ports is 192 kHz. The minimum sample rate is 6 kHz. There are four serial data input pins (SDATA_IN3 to SDATA_IN0) and four serial data output pins (SDATA_OUT3 to SDATA_ SDATA_IN2, SDATA_IN3, SDATA_OUT2, and SDATA_OUT3 OUT0). Each pin is capable of 2-channel, 4-channel, or 8-channel are capable of operating in a special mode called flexible TDM mode. In addition, SDATA_IN0, SDATA_IN1, SDATA_OUT0, mode, which allows custom byte addressable configuration, and SDATA_OUT1 are capable of 16-channel mode. where the data for each channel is located in the serial data stream. Flexible TDM mode is not a standard audio interface. Use it only The serial ports have a very flexible configuration scheme that in cases where a customized serial data format is desired. See the allows completely independent and orthogonal configuration of Flexible TDM Interface section for more information. clock pin assignment, clock waveform type, clock polarity, channel count, position of the data bits within the stream, audio word Serial Audio Data Format length, slave or master operation, and sample rate. A detailed The serial data input and output ports are designed to work with description of all possible serial port settings is included in the audio data that is encoded in a linear pulse code modulation Serial Port Configuration Registers section. (PCM) format, based on the common I²S standard. Audio data- The physical serial data input and output pins are connected to words can be 16, 24, or 32 bits in length. The serial ports can functional blocks called serial ports, which deal with handling handle TDM formats with channel counts ranging from two the audio data and clocks as they pass in and out of the device. channels to 16 channels on a single data line. Table 47 describes this relationship. Almost every aspect of the serial audio data format can be con- figured using the SERIAL_BYTE_x_0 and SERIAL_BYTE_x_1 Table 47. Relationship Between Hardware Serial Data Pins registers, and every setting can be configured independently. As a and Serial Input/Output Ports result, there are more than 70,000 valid configurations for each Serial Data Pin Serial Port serial audio port. SDATA_IN0 Serial Input Port 0 Serial Audio Data Timing Diagrams SDATA_IN1 Serial Input Port 1 SDATA_IN2 Serial Input Port 2 Because it is impractical to show timing diagrams for each possible SDATA_IN3 Serial Input Port 3 combination, timing diagrams for the more common configu- SDATA_OUT0 Serial Output Port 0 rations are shown in Figure 60 to Figure 65. Explanatory text SDATA_OUT1 Serial Output Port 1 accompanies each figure. SDATA_OUT2 Serial Output Port 2 SDATA_OUT3 Serial Output Port 3 There are 48 channels of serial audio data inputs and 48 channels of serial audio data outputs. The 48 audio input channels and 48 audio output channels are distributed among the four serial data input pins and the four serial data output pins. This distri- bution is described in Table 48. Table 48. Relationship Between Data Pin, Audio Channels, Clock Pins, and TDM Options Corresponding Clock Pins Maximum Flexible Serial Data Pin Channel Numbering in Master Mode TDM Channels TDM Mode SDATA_IN0 Channel 0 to Channel 15 BCLK_IN0, LRCLK_IN0 16 channels No SDATA_IN1 Channel 16 to Channel 31 BCLK_IN1, LRCLK_IN1 16 channels No SDATA_IN2 Channel 32 to Channel 39 BCLK_IN2, LRCLK_IN2 8 channels Yes SDATA_IN3 Channel 40 to Channel 47 BCLK_IN3, LRCLK_IN3 8 channels Yes SDATA_OUT0 Channel 0 to Channel 15 BCLK_OUT0, LRCLK_OUT0 16 channels No SDATA_OUT1 Channel 16 to Channel 31 BCLK_OUT1, LRCLK_OUT1 16 channels No SDATA_OUT2 Channel 32 to Channel 39 BCLK_OUT2, LRCLK_OUT2 8 channels Yes SDATA_OUT3 Channel 40 to Channel 47 BCLK_OUT3, LRCLK_OUT3 8 channels Yes Rev. D | Page 65 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet 360-68411 6162636460 END OFFRAME 10234 89101112.7. 15.. 10234 0..54321 31..43210 981011127.. 15..1617181920 59 5 13 5 6 5 13 21 58 6 14 6 7 6 14 22 5657 10 0 78 1516 0 78 98 87 1516 2324 55 2 1 9 17 1 9 10 9 17 25 54 3 2 10 18 2 10 11 10 18 26 515253 456 345 111213 192021 345 111213 121314 111213 192021 272829 AUSE 47484950 78910 6789 14151617 2223 102 10 6789 1415 15161718 14151617 22232425 313010 USED BEC 64-BIT CLOCK CYCLESBCLKCYCLE NUMBER12345678910111213141516171819203132333435363738394142434445464021222324252627282930 NEGATIVE POLARITY POSITIVE POLARITY LRCLK50/50, NEGATIVE POLARITY 50/50, POSITIVE POLARITY PULSE, NEGATIVE POLARITY PULSE, POSITIVE POLARITY MIDPOINT OFSTART OFFRAMEDATANEW FRAME 24-BIT, DELAY BY 11112131415161718192021222310234567891011121314151617181920212223 10234567891011121314151617181920212223101112131415161718192021222324-BIT, DELAY BY 0 24-BIT, DELAY BY 818192021222310234567891011121314151617181920212223..0 24-BIT, DELAY BY 16*..81023456789101112131415161718192021222376543210 16-BIT, DELAY BY 110234567891011121314153456789101112131415 16-BIT, DELAY BY 0102345678910111213141523456789101112131415 16-BIT, DELAY BY 81023456789101112131415101112131415 16-BIT, DELAY BY 16..01023456789101112131415 32-BIT, DELAY BY 1*8765432101011121314151617181920212223242526272829319300..119202122232425262728293130 32-BIT, DELAY BY 0543218760..09101112131415161718192021222324252627282931303018192021222324252627282931 654320..832-BIT, DELAY BY 8*71262728293130543218760910111213141516171819202122232425262728293130 32-BIT, DELAY BY 16*..1654328761023456789101112131415910111213141516171819202122232425262728293130 *IT IS POSSIBLE FOR THE USERTO CONFIGURE THE SERIAL PORTSTO OPERATE IN THIS MODE. HOWEVER, IT IS RECOMMENDED THAT THIS MODE NOT BE THEAUDIO DATA CROSSES THE THRESHOLD BETWEEN TWO FRAMES, WHICH MAY VIOLATE THE SPECIFICATIONS OF OTHER DEVICES IN THE SYSTEM. Figure 60. Serial Audio Formats; Two Channels, 32 Bits per Channel Figure 60 shows timing diagrams for possible serial port con- frame clock waveforms and polarities (SERIAL_BYTE_x_0, Bit 9 figurations in 2-channel mode, with 32 cycles of the bit clock (LRCLK_MODE) and Bit 8 (LRCLK_POL)). Excluding flexible signal per channel, for a total of 64 bit clock cycles per frame TDM mode, there are 12 possible combinations of settings for the (see the SERIAL_BYTE_x_0 registers, Bits[2:0] (TDM_MODE) = audio word length (SERIAL_BYTE_x_0, Bits[6:5] (WORD_LEN)) 0b000). Different bit clock polarities are illustrated in Figure 60 and MSB position (SERIAL_BYTE_x_0, Bits[4:3] (DATA_FMT)), (SERIAL_BYTE_x_0, Bit 7 (BCLK_POL)) as well as different all of which are shown in Figure 60. Rev. D | Page 66 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 460-68411 128-BIT CLOCK CYCLES END OFMIDPOINT OFSTART OFNEW FRAMEFRAMEFRAME 8 BITS8 BITS8 BITS8 BITSCHANNEL 2CHANNEL 0CHANNEL 3CHANNEL 1IDLEIDLEIDLEIDLE8 BITS8 BITS8 BITS8 BITSCHANNEL 2CHANNEL 0CHANNEL 3CHANNEL 1IDLEIDLEIDLEIDLE8 BITS8 BITS8 BITS8 BITSCHANNEL 0CHANNEL 1CHANNEL 3CHANNEL 2IDLEIDLEIDLEIDLE8 BITS8 BITS8 BITS8 BITSCHANNEL 2CHANNEL 3CHANNEL 1CHANNEL 3CHANNEL 0IDLEIDLEIDLEIDLE 16 BITS IDLE16 BITS IDLE16 BITS IDLECHANNEL 2CHANNEL 3CHANNEL 0CHANNEL 116 BITS IDLE CHANNEL 3CHANNEL 016 BITS IDLE16 BITS IDLE16 BITS IDLECHANNEL 2CHANNEL 116 BITS IDLE 8 BITS8 BITS16 BITS IDLE16 BITS IDLECHANNEL 2CHANNEL 016 BITS IDLECHANNEL 3CHANNEL 1IDLEIDLE 16 BITS IDLE16 BITS IDLE16 BITS IDLECHANNEL 316 BITS IDLECHANNEL 0CHANNEL 2CHANNEL 1 CHANNEL 2CHANNEL 1CHANNEL 3CHANNEL 0 CHANNEL 2CHANNEL 1CHANNEL 0CHANNEL 3 PREVIOUSCHANNEL 2CHANNEL 1CHANNEL 3CHANNEL 0SAMPLE CHANNEL 2CHANNEL 3CHANNEL 0PREVIOUS SAMPLECHANNEL 1 HE USERTO CONFIGURE THE SERIAL PORTSTO OPERATE IN THIS MODE. HOWEVER, IT IS RECOMMENDED THAT THIS MODE NOT BE USED BECAUSESSES THE THRESHOLD BETWEEN TWO FRAMES, WHICH MAY VIOLATE THE SPECIFICATIONS OF OTHER DEVICES IN THE SYSTEM. BCLK LRCLK DATA24-BIT, DELAY BY 1 24-BIT, DELAY BY 0 24-BIT, DELAY BY 8 24-BIT, DELAY BY 16* 16-BIT, DELAY BY 1 16-BIT, DELAY BY 0 16-BIT, DELAY BY 8 16-BIT, DELAY BY 16 32-BIT, DELAY BY 1* 32-BIT, DELAY BY 0 32-BIT, DELAY BY 8* 32-BIT, DELAY BY 16* *IT IS POSSIBLE FOR TEAUDIO DATA CROTH Figure 61. Serial Audio Data Formats; Four Channels, 32 Bits per Channel Figure 61 shows timing diagrams for possible serial port Excluding flexible TDM mode, there are 12 possible combinations configurations in 4-channel mode, with 32 bit clock cycles per of settings for the audio word length (SERIAL_BYTE_x_0, Bits[6:5] channel, for a total of 128 bit clock cycles per frame (refer to the (WORD_LEN)) and MSB position (SERIAL_BYTE_x_0, Bits[4:3] SERIAL_BYTE_x_0 registers, Bits[2:0] (TDM_MODE) = 0b001). (DATA_FMT)), all of which are shown in Figure 61. The bit clock signal is omitted from the figure. Rev. D | Page 67 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet 560-68411 BCLK256-BIT CLOCK CYCLES LRCLK MIDPOINT OFEND OFSTART OFFRAMEFRAMENEW FRAMEDATA24-BIT, DELAY BY 1CHANNEL 0CHANNEL 1CHANNEL 2CHANNEL 3CHANNEL 4CHANNEL 5CHANNEL 6CHANNEL 7 24-BIT, DELAY BY 0CHANNEL 0CHANNEL 1CHANNEL 2CHANNEL 3CHANNEL 4CHANNEL 5CHANNEL 6CHANNEL 7 CHANNEL 0CHANNEL 1CHANNEL 2CHANNEL 3CHANNEL 4CHANNEL 5CHANNEL 6CHANNEL 724-BIT, DELAY BY 8 CHANNEL 0CHANNEL 1CHANNEL 2CHANNEL 3CHANNEL 4CHANNEL 5CHANNEL 6CHANNEL 7...CH7...24-BIT, DELAY BY 16* 16-BIT, DELAY BY 1CHANNEL 1CHANNEL 2CHANNEL 3CHANNEL 4CHANNEL 5CHANNEL 6CHANNEL 7CHANNEL 0 16-BIT, DELAY BY 0CHANNEL 1CHANNEL 2CHANNEL 3CHANNEL 4CHANNEL 5CHANNEL 6CHANNEL 0CHANNEL 7 CHANNEL 6CHANNEL 0CHANNEL 1CHANNEL 2CHANNEL 3CHANNEL 4CHANNEL 516-BIT, DELAY BY 8CHANNEL 7 CHANNEL 1CHANNEL 2CHANNEL 3CHANNEL 4CHANNEL 5CHANNEL 6CHANNEL 0CHANNEL 716-BIT, DELAY BY 16 32-BIT, DELAY BY 1*CHANNEL 7CHANNEL 6CHANNEL 5CHANNEL 4CHANNEL 3CHANNEL 2CHANNEL 1CHANNEL 0 32-BIT, DELAY BY 0CHANNEL 6CHANNEL 5CHANNEL 4CHANNEL 3CHANNEL 2CHANNEL 1CHANNEL 0CHANNEL 7 PREVIOUS32-BIT, DELAY BY 8*CHANNEL 6CHANNEL 5CHANNEL 4CHANNEL 3CHANNEL 2CHANNEL 0CHANNEL 1CHANNEL 7...SAMPLE PREVIOUS32-BIT, DELAY BY 16*CHANNEL 6CHANNEL 5CHANNEL 4CHANNEL 3CHANNEL 2CHANNEL 1CHANNEL 0CHANNEL 7...SAMPLE *IT IS POSSIBLE FOR THE USERTO CONFIGURE THE SERIAL PORTSTO OPERATE IN THIS MODE. HOWEVER, IT IS RECOMMENDED THAT THIS MODE NOT BE USED BECAUSE THEAUDIO DATA CROSSES THE THRESHOLD BETWEEN TWO FRAMES, WHICH MAY VIOLATE THE SPECIFICATIONS OF OTHER DEVICES IN THE SYSTEM. Figure 62. Serial Audio Data Formats; Eight Channels, 32 Bits per Channel Figure 62 shows timing diagrams for possible serial port con- Excluding flexible TDM mode, there are 12 possible combinations figurations in 8-channel mode, with 32 bit clock cycles per of settings for the audio word length (SERIAL_BYTE_x_0, Bits[6:5] channel, for a total of 256 bit clock cycles per frame (refer to the (WORD_LEN)) and MSB position (SERIAL_BYTE_x_0, Bits[4:3] SERIAL_BYTE_x_0 registers, Bits[2:0] (TDM_MODE) = 0b010). (DATA_FMT)), all of which are shown in Figure 62. The bit clock signal is omitted from the figure. Rev. D | Page 68 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 660-68411 BCLK512-BIT CLOCK CYCLES LRCLK END OFSTART OFMIDPOINT OFFRAMENEW FRAMEFRAMEDATA24-BIT, DELAY BY 1CH 8CH 9CH 10CH 0CH 1CH 2CH 3CH 11CH 13CH 4CH 14CH 5CH 6CH 7CH 15CH 12 CH 8CH 9CH 1024-BIT, DELAY BY 0CH 0CH 1CH 2CH 3CH 11CH 13CH 4CH 14CH 5CH 15CH 6CH 7CH 12 CH 8CH 9CH 10CH 0CH 1CH 2CH 3CH 11CH 13CH 4CH 14CH 5CH 15CH 6CH 7CH 1224-BIT, DELAY BY 8 CH 15...CH 8CH 9CH 10CH 0CH 1CH 2CH 3CH 11CH 13CH 4CH 14CH 5CH 6CH 7..15CH 1224-BIT, DELAY BY 16* 16-BIT, DELAY BY 1CH 0CH 1CH 2CH 10CH 3CH 11CH 4CH 12CH 5CH 6CH 13CH 7CH 14CH 15CH 8CH 9 16-BIT, DELAY BY 0CH 0CH 1CH 2CH 10CH 3CH 11CH 4CH 12CH 5CH 6CH 13CH 7CH 14CH 15CH 8CH 9 CH 0CH 1CH 2CH 10CH 3CH 11CH 4CH 12CH 5CH 6CH 13CH 7CH 14CH 15CH 8CH 916-BIT, DELAY BY 8 CH 0CH 1CH 2CH 10CH 3CH 11CH 4CH 12CH 5CH 6CH 13CH 7CH 14CH 15CH 8CH 916-BIT, DELAY BY 16 32-BIT, DELAY BY 1*CH 0CH 8CH 9CH 10CH 11CH 12CH 13CH 14CH 15CH 1CH 2CH 3CH 4CH 5CH 6CH 7 32-BIT, DELAY BY 0CH 8CH 9CH 10CH 11CH 12CH 13CH 14CH 15CH 0CH 1CH 2CH 3CH 4CH 5CH 6CH 7 PREV32-BIT, DELAY BY 8* 7CH 8CH 9CH 10CH 11CH 12CH 13CH 14CH 15CH 0CH 1CH 2CH 3CH 4CH 5CH 6CHSAMP PREVCH 7CH 8CH 9CH 10CH 11CH 12CH 13CH 15CH 14CH 0CH 1CH 2CH 3CH 4CH 5CH 632-BIT, DELAY BY 16*SAMP *IT IS POSSIBLE FOR THE USERTO CONFIGURE THE SERIAL PORTSTO OPERATE IN THIS MODE. HOWEVER, IT IS RECOMMENDED THAT THIS MODE NOT BE USED BECAUSE THEAUDIO DATA CROSSES THE THRESHOLD BETWEEN TWO FRAMES, WHICH MAY VIOLATE THE SPECIFICATIONS OF OTHER DEVICES IN THE SYSTEM. Figure 63. Serial Audio Data Formats; 16 Channels, 32 Bits per Channel Figure 63 shows some timing diagrams for possible serial port Excluding flexible TDM mode, there are 12 possible combinations configurations in 16-channel mode, with 32 bit clock cycles per of settings for the audio word length (SERIAL_BYTE_x_0, Bits[6:5] channel, for a total of 512 bit clock cycles per frame (refer to the (WORD_LEN)) and MSB position (SERIAL_BYTE_x_0, Bits[4:3] SERIAL_BYTE_x_0 registers, Bits[2:0] (TDM_MODE) = 0b011). (DATA_FMT)), all of which are shown in Figure 63. The bit clock signal is omitted from the figure. Rev. D | Page 69 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet 760-68411 4 6 616263 END OFFRAME ANNEL 3 555657585960 CHANNEL 3 CHANNEL 3 CH CHANNEL 2 4 5 53 SE 2 U 5 A 51 2 EC 47484950 CHANNEL BE USED B 444546 DE NOT YSTEM. 64-BIT CLOCK CYCLES 3132333435363738394142434021222324252627282930 MIDPOINT OFFRAME CHANNEL 1CHANNEL 2 CHANNEL 1CHANNEL 2 CHANNEL 1 CHANNEL 0CHANNEL 1 E IN THIS MODE. HOWEVER, IT IS RECOMMENDED THAT THIS MOMAY VIOLATE THE SPECIFICATIONS OF OTHER DEVICES IN THE S 20 ATH 141516171819 CHANNEL 0 PORTSTO OPERO FRAMES, WHIC 12345678910111213 START OFNEW FRAME CHANNEL 0 CHANNEL 0 PREVIOUS SAMPLE PREVIOUS SAMPLE HE USERTO CONFIGURE THE SERIAL SSES THE THRESHOLD BETWEEN TW BCLK CYCLE NUMBER NEGATIVE POLARITY POSITIVE POLARITY LRCLK DATA16-BIT, DELAY BY 1* 16-BIT, DELAY BY 0 16-BIT, DELAY BY 8* 16-BIT, DELAY BY 16* *IT IS POSSIBLE FOR T THEAUDIO DATA CRO Figure 64. Serial Audio Data Formats; Four Channels, 16 Bits per Channel Figure 64 shows some timing diagrams for possible serial port BYTE_x_0 registers, Bit 7 (BCLK_POL)). The audio word length configurations in 4-channel mode, with 16 bit clock cycles per is fixed at 16 bits (refer to the SERIAL_BYTE_x_0 registers, channel, for a total of 64 bit clock cycles per frame (refer to the Bits[6:5] (WORD_LEN) = 0b01), and there are four possible SERIAL_BYTE_x_0 registers, Bits[2:0] (TDM_MODE) = 0b100). configurations for MSB position (SERIAL_BYTE_x_0, Bits[4:3] Different bit clock polarities are shown (refer to the SERIAL_ (DATA_FMT)), all of which are shown in Figure 64. Rev. D | Page 70 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 860-68411 2 3 31 D OFAME USE 30 ENFR 1 ECA L B 2829 CHANNE BE USED 92021222324252627 CHANNEL 1 CHANNEL 1 CHANNEL 0 RECOMMENDED THAT THIS MODE NOT S OF OTHER DEVICES IN THE SYSTEM. 2-BIT CLOCK CYCLES 151617181 NT OFRAME CHANNEL 0 ODE. HOWEVER, IT IS E THE SPECIFICATION 3 1314 MIDPOIF N THIS MY VIOLAT 12 ATE IH MA 67891011 CHANNEL 0 CHANNEL 0 LE PREVIOUS SAMPLE E SERIAL PORTSTO OPERWEEN TWO FRAMES, WHIC 5 AMP E THBET 4 US S GUROLD 123 START OFNEW FRAME PREVIO USERTO CONFIS THE THRESH HE SSE BCLK CYCLE NUMBER NEGATIVE POLARITY POSITIVE POLARITY LRCLK DATA 16-BIT, DELAY BY 1* 16-BIT, DELAY BY 0 16-BIT, DELAY BY 8* 16-BIT, DELAY BY 16* *IT IS POSSIBLE FOR T THEAUDIO DATA CRO Figure 65. Serial Audio Data Formats; Two Channels, 16 Bits per Channel Figure 65 shows some timing diagrams for possible serial port Different bit clock polarities are illustrated (SERIAL_BYTE_x_0, configurations in two channel mode, with 16 bit clock cycles per Bit 7 (BCLK_POL)). The audio word length is fixed at 16 bits channel, for a total of 32 bit clock cycles per frame (refer to the (SERIAL_BYTE_x_0, Bits[6:5] (WORD_LEN) = 0b01), and SERIAL_BYTE_x_0 registers, Register 0xF200 to Register 0xF21C, there are four possible configurations for MSB position (SERIAL_ Bits[2:0] (TDM_MODE) = 0b101). BYTE_x_0, Bits[4:3] (DATA_FMT)), all of which are shown in Figure 65. Rev. D | Page 71 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Serial Clock Domains domains when it is configured in slave mode (refer to the SERIAL_BYTE_x_0 registers, Bits[15:13] (LRCLK_ SRC), which There are four input clock domains and four output clock can be set to 0b000, 0b001, 0b010, or 0b011; and Bits[12:10] domains. A clock domain consists of a pair of LRCLK_OUTx (BCLK_SRC), which can be set to 0b000, 0b001, 0b010, or 0b011). and LRCLK_INx (frame clock) and BCLK_OUTx and BCLK_INx Any serial data output can be clocked by any output clock (bit clock) pins, which are used to synchronize the transmission domain when the data output is configured in slave mode (see of audio data to and from the device. In master mode (refer to the SERIAL_BYTE_x_0 registers, Bits[15:13] (LRCLK_SRC), the SERIAL_BYTE_x_0 registers, Register 0xF200 to Register which can be set to 0b000, 0b001, 0b010, or 0b011; and 0xF21C, Bits[15:13] (LRCLK_ SRC) = 0b100 and Bits[12:10] Bits[12:10] (BCLK_SRC), which can be set to 0b000, 0b001, (BCLK_SRC) = 0b100), each clock domain corresponds to exactly 0b010, or 0b011). one serial data pin, one frame clock pin, and one bit clock pin. Any serial data input can be clocked by any input clock Table 49. Relationship Between Serial Data Pins and Clock Pins in Master or Slave Mode Serial Data Pin Corresponding Clock Pins in Master Mode Corresponding Clock Pins in Slave Mode SDATA_IN0 BCLK_IN0, LRCLK_IN0 (LRCLK_IN0/MP10) BCLK_IN0, LRCLK_IN0 or BCLK_IN1, LRCLK_IN1 or BCLK_IN2, LRCLK_IN2 or BCLK_IN3, LRCLK_IN3 SDATA_IN1 BCLK_IN1, LRCLK_IN1 (LRCLK_IN1/MP11) BCLK_IN0, LRCLK_IN0 or BCLK_IN1, LRCLK_IN1 or BCLK_IN2, LRCLK_IN2 or BCLK_IN3, LRCLK_IN3 SDATA_IN2 BCLK_IN2, LRCLK_IN2 (LRCLK_IN2/MP12) BCLK_IN0, LRCLK_IN0 or BCLK_IN1, LRCLK_IN1 or BCLK_IN2, LRCLK_IN2 or BCLK_IN3, LRCLK_IN3 SDATA_IN3 BCLK_IN3, LRCLK_IN3 (LRCLK_IN3/MP13) BCLK_IN0, LRCLK_IN0 or BCLK_IN1, LRCLK_IN1 or BCLK_IN2, LRCLK_IN2 or BCLK_IN3, LRCLK_IN3 SDATA_OUT0 BCLK_OUT0, LRCLK_OUT0 (LRCLK_OUT0/MP4) BCLK_OUT0, LRCLK_OUT0 or BCLK_OUT1, LRCLK_OUT1 or BCLK_OUT2, LRCLK_OUT2 or BCLK_OUT3, LRCLK_OUT3 SDATA_OUT1 BCLK_OUT1, LRCLK_OUT1 (LRCLK_OUT1/MP5) BCLK_OUT0, LRCLK_OUT0 or BCLK_OUT1, LRCLK_OUT1 or BCLK_OUT2, LRCLK_OUT2 or BCLK_OUT3, LRCLK_OUT3 SDATA_OUT2 BCLK_OUT2, LRCLK_OUT2 (LRCLK_OUT2/MP8) BCLK_OUT0, LRCLK_OUT0 or BCLK_OUT1, LRCLK_OUT1 or BCLK_OUT2, LRCLK_OUT2 or BCLK_OUT3, LRCLK_OUT3 SDATA_OUT3 BCLK_OUT3, LRCLK_OUT3 (LRCLK_OUT3/MP9) BCLK_OUT0, LRCLK_OUT0 or BCLK_OUT1, LRCLK_OUT1 or BCLK_OUT2, LRCLK_OUT2 or BCLK_OUT3, LRCLK_OUT3 Rev. D | Page 72 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Serial Input Ports Serial Output Ports There is a one-to-one mapping between the serial input ports There is a one-to-one mapping between the serial output ports and the audio input channels in the DSP and the ASRC input and the output audio channels in the DSP (see Table 51). selectors, which is described in Table 50. Table 51. Relationship Between Serial Input Port and Table 50. Relationship Between Serial Input Port and Corresponding DSP Output Channel Numbers Corresponding Channel Numbers on the DSP and ASRC Inputs Serial Input Port Audio Output Channels from the DSP Serial Port Audio Input Channels in the DSP and ASRC Serial Output 0 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and Serial Input 0 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15 15 Serial Input 1 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, Serial Output 1 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, and 31 28, 29, 30, and 31 Serial Input 2 32, 33, 34, 35, 36, 37, 38, and 39 Serial Output 2 32, 33, 34, 35, 36, 37, 38, and 39 Serial Input 3 40, 41, 42, 43, 44, 45, 46, and 47 Serial Output 3 40, 41, 42, 43, 44, 45, 46,and 47 If a serial input port is configured using the SERIAL_BYTE_x_0 If a serial output port is configured using the SERIAL_BYTE_x_0 registers, Bits[2:0] (TDM_MODE) for a number of channels that registers, Bits[2:0] (TDM_MODE), for a number of channels that is less than its maximum channel count, the unused channels carry is less than its maximum channel count, the unused channels zero data. For example, if Serial Input 0 is set in 8-channel (TDM8) are ignored. For example, if Serial Output Port 0 is set in 8-channel mode, the first eight channels (Channel 0 to Channel 7) carry data (TDM8) mode, and data is routed to it from the DSP, the first and the unused channels (Channel 8 to Channel 15) carry no data. eight DSP output channels (Channel 0 through Channel 7) are output on SDATA_OUT0, but the remaining channels (Channel 8 There are four options for the word length of each serial input port: through Channel 15) are not output from the device. 24 bits, 16 bits, 32 bits, or flexible TDM. The flexible TDM option is described in the Flexible TDM Input section. There are four options for the word length of each serial output port: 24 bits, 16 bits, 32 bits, or flexible TDM. See the Flexible In 32-bit mode (see Figure 66), the 32 bits received on the serial TDM Output section for more information. input are mapped directly to a 32-bit word in the DSP core. To use 32-bit mode, the special 32-bit input cells must be used in In 32-bit mode (see Figure 67), all 32 bits from the 8.24 word in SigmaStudio. the DSP core are copied directly to the serial output. To use 32-bit mode, the special 32-bit output cells must be used in SigmaStudio. AUDIO MSB AUDIO MSB MSB AUDIO MSB MSB AUDIO MSB AUDIO MSB AUDIO MSBMSB 24-BIT 24-BIT 24-BIT AUDIO AUDIO AUDIO SAMPLE SAMPLE ROUTING SAMPLE MATRIX 32-BIT ROUTING 32-BIT 32-BIT WORD MATRIX WORD WORD 8-BIT DATA 8-BIT DATA 8-BIT DATA AUDIO LSB AUDIO LSB LSB AUDIO LSB LSB ISNEPRU3ITA2 LS-BTAIRTUEDAIOM FiINgPu3Ur2eT- B 6PI6TO. R3T2-Bit Serial Input ExamDpSleP CORE 11486-069 AUDIO LSB OUATU3PD2UI-OBT ILPTSOBRT OSUETARPU3IUDA2TIL-O BSA ILTTUSRDBEIOALMSB 11486-071 Figure 67. 32-Bit Serial Output Example In 24-bit mode (see Figure 68), the 24-bit audio sample (in 1.23 In 24-bit mode, the top seven MSBs of the 8.24 audio word in format) is padded with eight zeros below its LSB (in 1.31 format) as the DSP core are saturated, and the resulting 1.23 word is output it is input to the routing matrix. Then, the audio data is shifted from the serial port, with eight zeros padded under the LSB (see such that the audio sample has seven sign-extended zeros on Figure 69). top, one padded zero on the bottom, and 24 bits of data in the middle (8.24 format). In 16-bit mode, the top seven MSBs of the 8.24 audio word in the DSP core are saturated, and the resulting 1.23 word is then Where 16-bit mode is similar to 24-bit mode, the 16-bit audio truncated to a 1.15 word by removing the eight LSBs. The data has 16 zeros below its LSB instead of just eight zeros (in the resulting 1.15 word is then zero padded with 16 zeros under the 24-bit case). The resulting 8.24 sample has seven sign extended LSB and output from the serial port. zeros on top, nine padded zeros on the bottom, and 16 bits of data in the middle (8.24 format). Rev. D | Page 73 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet AUDIO MSBMSB AUDIO MSB MSB MSB SIGN EXTENDED AUDIO MSB 1.23 1.23 AUDIO AUDIO SAMPLE SAMPLE ROUTING MATRIX 1.23 AUDIO SAMPLE AUDIO LSB LSB AUDIO LSB 24-BIT SERIAL AUDIO INPUT ZEROS STREAM INP2U4T-B PITORT LSB ZERO DASUPD CIOO RLSEB LSB 11486-070 Figure 68. 24-Bit Serial Input Example +1 –128 –1 +1 x: DSP CORE OUTPUT +127.999... –1 y: SERIAL PORT OUTPUT MSB AUDIO MSB MSB AUDIO MSB MSB 7 MSBs SATURATED AUDIO MSB TO ±1 IF OUTPUT IS >1 1.23 1.23 AUDIO AUDIO SAMPLE SAMPLE SATURATOR/ ROUTING 24-BITS CLIPPER MATRIX AUDIO LSB AUDIO LSB LSB 24-BIT 1 LSB AUDIO LSB 8 ZEROS OSUETRPIUATL SATURDEIOAM TRUNCATED DSP CORE LSB OUT2P4U-BT IPTORTLSB 11486-072 Figure 69. 24-Bit Serial Output Example Rev. D | Page 74 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Serial Port Configuration Registers Overview An overview of the registers related to the serial ports is shown in Table 52. For a more detailed description, see the Serial Port Configuration Registers section. Table 52. Serial Port Registers Address Register Description 0xF200 SERIAL_BYTE_0_0 Serial Port Control 0 (SDATA_IN0 pin) 0xF201 SERIAL_BYTE_0_1 Serial Port Control 1 (SDATA_IN0 pin) 0xF204 SERIAL_BYTE_1_0 Serial Port Control 0 (SDATA_IN1 pin) 0xF205 SERIAL_BYTE_1_1 Serial Port Control 1 (SDATA_IN1 pin) 0xF208 SERIAL_BYTE_2_0 Serial Port Control 0 (SDATA_IN2 pin) 0xF209 SERIAL_BYTE_2_1 Serial Port Control 1 (SDATA_IN2 pin) 0xF20C SERIAL_BYTE_3_0 Serial Port Control 0 (SDATA_IN3 pin) 0xF20D SERIAL_BYTE_3_1 Serial Port Control 1 (SDATA_IN3 pin) 0xF210 SERIAL_BYTE_4_0 Serial Port Control 0 (SDATA_OUT0 pin) 0xF211 SERIAL_BYTE_4_1 Serial Port Control 1 (SDATA_OUT0 pin) 0xF214 SERIAL_BYTE_5_0 Serial Port Control 0 (SDATA_OUT1 pin) 0xF215 SERIAL_BYTE_5_1 Serial Port Control 1 (SDATA_OUT1 pin) 0xF218 SERIAL_BYTE_6_0 Serial Port Control 0 (SDATA_OUT2 pin) 0xF219 SERIAL_BYTE_6_1 Serial Port Control 1 (SDATA_OUT2 pin) 0xF21C SERIAL_BYTE_7_0 Serial Port Control 0 (SDATA_OUT3 pin) 0xF21D SERIAL_BYTE_7_1 Serial Port Control 1 (SDATA_OUT3 pin) Rev. D | Page 75 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet FLEXIBLE TDM INTERFACE There are a total of 64 control registers (FTDM_INx) that can be configured to set up the mapping of input data bytes to the The flexible TDM interface is available as an optional mode of corresponding bytes in the serial input channels. Each byte in operation on the SDATA_IN2 and SDATA_IN3 serial input ports, each serial input channel has a corresponding control register, as well as on the SDATA_OUT2 and SDATA_OUT3 serial output which selects the incoming data byte on the serial input pins ports. To use flexible TDM mode, the corresponding serial ports that must be mapped to it. Figure 70 shows, from left to right, must be set in flexible TDM mode (SERIAL_BYTE_x_0 register, the data streams entering the serial input pins, the serial input Bits[6:5] (WORD_LEN) = 0b11 and SERIAL_BYTE_x_0 register, channels, and the registers (see FTDM_INx, Register 0xF300 to Bits[2:0] = 0b010). Flexible TDM input mode requires that both Register 0xF33F) that correspond to each byte in the serial input SDATA_IN2 and SDATA_IN3 be configured for flexible TDM channels. mode. Likewise, flexible TDM output mode requires that both SDATA_OUT2 and SDATA_OUT3 pins are configured for Flexible TDM Output flexible TDM mode. In flexible TDM output mode, two 256-bit data streams are output The flexible TDM interface provides byte addressable data place- from the SDATA_OUT2 and SDATA_OUT3 pins. These 256 bits ment in the input and output data streams on the corresponding of data compose eight channels of four bytes each, for a total of serial data input/output pins. Each data stream is configured 32 bytes on each pin, and a total of 64 bytes when both input like a standard 8-channel TDM interface, with a total of 256 data pins are combined. The flexible TDM output functional block bits (or 32 bytes) in the span of an audio frame. Because flexible routes the desired byte from the desired serial output channel to TDM mode runs on two pins simultaneously, and each pin has a given byte in the output streams. The serial output channels 32 bytes of data, this means that there are a total of 64 data bytes. In originate from the audio routing matrix, which is configured flexible TDM input mode, each input channel inside the device can using the SOUT_SOURCEx control registers. select its source data from any of the 64 input data bytes. In flexible There are a total of 64 control registers (see FTDM_OUTx, TDM output mode, any serial output channel can be routed to any Register 0xF3880 to Register 0xF3BF) that can be configured of the 64 output data bytes. to set up the mapping of the bytes in the serial output channels Flexible TDM Input and the bytes in the data streams exiting the serial output pins. Each byte in the data streams being output from the serial output In flexible TDM input mode, two 256-bit data streams are input pins has a corresponding control register, which selects the to the SDATA_IN2 and SDATA_IN3 pins. These 256 bits of data desired byte from the desired serial output channel. Figure 71 compose eight channels of four bytes each, for a total of 32 bytes shows, from left to right, the serial output channels originating on each pin, and a total of 64 bytes when both input pins are from the routing matrix, the serial output pins and data streams, combined. The flexible TDM input functional block routes the and the control registers (FTDM_OUTx) that correspond to desired input byte to a given byte in the serial input channels. each byte in the serial output data streams. Those serial input channels are then available as normal audio data in the audio routing matrix. The data can be passed to the DSP core, the ASRC inputs, or the serial outputs as needed. Rev. D | Page 76 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 370-68411 BITS[7:0]FTDM_IN3FTDM_IN7FTDM_IN11FTDM_IN15FTDM_IN19FTDM_IN23FTDM_IN27FTDM_IN31FTDM_IN35FTDM_IN39FTDM_IN43FTDM_IN47FTDM_IN51FTDM_IN55FTDM_IN59FTDM_IN63 BITS[15:8]FTDM_IN2FTDM_IN6FTDM_IN10FTDM_IN14FTDM_IN18FTDM_IN22FTDM_IN26FTDM_IN30FTDM_IN34FTDM_IN38FTDM_IN42FTDM_IN46FTDM_IN50FTDM_IN54FTDM_IN58FTDM_IN62 BITS[23:16]FTDM_IN1FTDM_IN5FTDM_IN9FTDM_IN13FTDM_IN17FTDM_IN21FTDM_IN25FTDM_IN28FTDM_IN33FTDM_IN37FTDM_IN41FTDM_IN45FTDM_IN49FTDM_IN53FTDM_IN57FTDM_IN61 BITS[31:24]FTDM_IN0FTDM_IN4FTDM_IN8FTDM_IN12FTDM_IN16FTDM_IN20FTDM_IN24FTDM_IN28FTDM_IN32FTDM_IN36FTDM_IN40FTDM_IN44FTDM_IN48FTDM_IN52FTDM_IN56FTDM_IN60 2345678901234567 3333333344444444 LLLLLLLLLLLLLLLL NENENENENENENENENENENENENENENENE NNNNNNNNNNNNNNNN AAAAAAAAAAAAAAAA HHHHHHHHHHHHHHHH CCCCCCCCCCCCCCCC TTTTTTTTTTTTTTTT UUUUUUUUUUUUUUUU PPPPPPPPPPPPPPPP NNNNNNNNNNNNNNNN IIIIIIIIIIIIIIII LLLLLLLLLLLLLLLL AAAAAAAAAAAAAAAA RIRIRIRIRIRIRIRIRIRIRIRIRIRIRIRI EEEEEEEEEEEEEEEE SSSSSSSSSSSSSSSS →→→→→→→→→→→→→→→→ KCOLB MDT ELBIXELF 2 3 N N _I _I A A T T A A D D S S NEL 7 23 NEL 7 23 AN 1 AN 1 H H C 0 C 0 NEL 6 23 NEL 6 23 AN 1 AN 1 H H C 0 C 0 NEL 5 23 NEL 5 23 AN 1 AN 1 H H C 0 C 0 NEL 4 23 NEL 4 23 AN 1 AN 1 H H C 0 C 0 NEL 3 23 NEL 3 23 N N A 1 A 1 H H C 0 C 0 NEL 2 23 NEL 2 23 AN 1 AN 1 H H C 0 C 0 NEL 1 23 NEL 1 23 AN 1 AN 1 H H C 0 C 0 NEL 0 23 NEL 0 23 AN 1 AN 1 H H C 0 C 0 Figure 70. Flexible TDM Input Mapping Rev. D | Page 77 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet 470-68411 13TUO_MDTF 36TUO_MDTF EL 7 03TUO_MDTF EL 7 26TUO_MDTF N N AN 92TUO_MDTF AN 16TUO_MDTF H H C 82TUO_MDTF C 06TUO_MDTF 72TUO_MDTF 95TUO_MDTF EL 6 62TUO_MDTF EL 6 85TUO_MDTF N N AN 52TUO_MDTF AN 75TUO_MDTF H H C 42TUO_MDTF C 65TUO_MDTF 32TUO_MDTF 55TUO_MDTF EL 5 22TUO_MDTF EL 5 45TUO_MDTF N N AN 12TUO_MDTF AN 35TUO_MDTF H H C 02TUO_MDTF C 25TUO_MDTF 91TUO_MDTF 15TUO_MDTF EL 4 81TUO_MDTF EL 4 05TUO_MDTF N N AN 71TUO_MDTF AN 94TUO_MDTF H H C 61TUO_MDTF C 84TUO_MDTF 51TUO_MDTF 74TUO_MDTF EL 3 41TUO_MDTF EL 3 64TUO_MDTF N N AN 31TUO_MDTF AN 54TUO_MDTF H H C 21TUO_MDTF C 44TUO_MDTF 11TUO_MDTF 34TUO_MDTF EL 2 01TUO_MDTF EL 2 24TUO_MDTF N N AN 9TUO_MDTF AN 14TUO_MDTF H H C 8TUO_MDTF C 04TUO_MDTF 7TUO_MDTF 93TUO_MDTF EL 1 6TUO_MDTF EL 1 83TUO_MDTF N N AN 5TUO_MDTF AN 73TUO_MDTF H H C 4TUO_MDTF C 63TUO_MDTF 3TUO_MDTF 53TUO_MDTF EL 0 2TUO_MDTF EL 0 43TUO_MDTF N N AN 1TUO_MDTF AN 33TUO_MDTF H H C 0TUO_MDTF C 23TUO_MDTF NNEL BYTE NNEL BYTE A A H H C C M8 M8 D D T T UT2 UT3 O O A_ A_ AT AT D D S S KCOLB MDT ELBIXELF →→→→→→→→→→→→→→→→ BITS[7:0]3333333333333333 BITS[15:8]2222222222222222 BITS[23:16]1111111111111111 BITS[31:24]0000000000000000 2345678901234567 3333333344444444 L L L L L L L L L L L L L L L L EEEEEEEEEEEEEEEE NNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNN AAAAAAAAAAAAAAAA HHHHHHHHHHHHHHHH CCCCCCCCCCCCCCCC T T T T T T T T T T T T T T T T UUUUUUUUUUUUUUUU PPPPPPPPPPPPPPPP TTTTTTTTTTTTTTTT UUUUUUUUUUUUUUUU OOOOOOOOOOOOOOOO L L L L L L L L L L L L L L L L AAAAAAAAAAAAAAAA RIRIRIRIRIRIRIRIRIRIRIRIRIRIRIRI SESESESESESESESESESESESESESESESE Figure 71. Flexible TDM Output Mapping Rev. D | Page 78 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Flexible TDM Interface Registers Overview An overview of the registers related to the flexible TDM interface is shown in Table 53. For details, see the Flexible TDM Interface Registers section. Table 53. Flexible TDM Registers Address Register Description 0xF300 FTDM_IN0 FTDM mapping for the serial inputs (Channel 32, Bits[31:24]) 0xF301 FTDM_IN1 FTDM mapping for the serial inputs (Channel 32, Bits[23:16]) 0xF302 FTDM_IN2 FTDM mapping for the serial inputs (Channel 32, Bits[15:8]) 0xF303 FTDM_IN3 FTDM mapping for the serial inputs (Channel 32, Bits[7:0]) 0xF304 FTDM_IN4 FTDM mapping for the serial inputs (Channel 33, Bits[31:24]) 0xF305 FTDM_IN5 FTDM mapping for the serial inputs (Channel 33, Bits[23:16]) 0xF306 FTDM_IN6 FTDM mapping for the serial inputs (Channel 33, Bits[15:8]) 0xF307 FTDM_IN7 FTDM mapping for the serial inputs Channel 33, Bits[7:0]) 0xF308 FTDM_IN8 FTDM mapping for the serial inputs (Channel 34, Bits[31:24]) 0xF309 FTDM_IN9 FTDM mapping for the serial inputs (Channel 34, Bits[23:16]) 0xF30A FTDM_IN10 FTDM mapping for the serial inputs (Channel 34, Bits[15:8]) 0xF30B FTDM_IN11 FTDM mapping for the serial inputs (Channel 34, Bits[7:0]) 0xF30C FTDM_IN12 FTDM mapping for the serial inputs (Channel 35, Bits[31:24]) 0xF30D FTDM_IN13 FTDM mapping for the serial inputs (Channel 35, Bits[23:16]) 0xF30E FTDM_IN14 FTDM mapping for the serial inputs (Channel 35, Bits[15:8]) 0xF30F FTDM_IN15 FTDM mapping for the serial inputs (Channel 35, Bits[7:0]) 0xF310 FTDM_IN16 FTDM mapping for the serial inputs (Channel 36, Bits[31:24]) 0xF311 FTDM_IN17 FTDM mapping for the serial inputs (Channel 36, Bits[23:16]) 0xF312 FTDM_IN18 FTDM mapping for the serial inputs (Channel 36, Bits[15:8]) 0xF313 FTDM_IN19 FTDM mapping for the serial inputs (Channel 36, Bits[7:0]) 0xF314 FTDM_IN20 FTDM mapping for the serial inputs (Channel 37, Bits[31:24]) 0xF315 FTDM_IN21 FTDM mapping for the serial inputs (Channel 37, Bits[23:16]) 0xF316 FTDM_IN22 FTDM mapping for the serial inputs (Channel 37, Bits[15:8]) 0xF317 FTDM_IN23 FTDM mapping for the serial inputs (Channel 37, Bits[7:0]) 0xF318 FTDM_IN24 FTDM mapping for the serial inputs (Channel 38, Bits[31:24]) 0xF319 FTDM_IN25 FTDM mapping for the serial inputs (Channel 38, Bits[23:16]) 0xF31A FTDM_IN26 FTDM mapping for the serial inputs (Channel 38, Bits[15:8]) 0xF31B FTDM_IN27 FTDM mapping for the serial inputs (Channel 38, Bits[7:0]) 0xF31C FTDM_IN28 FTDM mapping for the serial inputs (Channel 39, Bits[31:24]) 0xF31D FTDM_IN29 FTDM mapping for the serial inputs (Channel 39, Bits[23:16]) 0xF31E FTDM_IN30 FTDM mapping for the serial inputs (Channel 39, Bits[15:8]) 0xF31F FTDM_IN31 FTDM mapping for the serial inputs (Channel 39, Bits[7:0]) 0xF320 FTDM_IN32 FTDM mapping for the serial inputs (Channel 40, Bits[31:24]) 0xF321 FTDM_IN33 FTDM mapping for the serial inputs (Channel 40, Bits[23:16]) 0xF322 FTDM_IN34 FTDM mapping for the serial inputs (Channel 40, Bits[15:8]) 0xF323 FTDM_IN35 FTDM mapping for the serial inputs (Channel 40, Bits[7:0]) 0xF324 FTDM_IN36 FTDM mapping for the serial inputs (Channel 41, Bits[31:24]) 0xF325 FTDM_IN37 FTDM mapping for the serial inputs (Channel 41, Bits[23:16]) 0xF326 FTDM_IN38 FTDM mapping for the serial inputs (Channel 41, Bits[15:8]) 0xF327 FTDM_IN39 FTDM mapping for the serial inputs (Channel 41, Bits[7:0]) 0xF328 FTDM_IN40 FTDM mapping for the serial inputs (Channel 42, Bits[31:24]) 0xF329 FTDM_IN41 FTDM mapping for the serial inputs (Channel 42, Bits[23:16]) 0xF32A FTDM_IN42 FTDM mapping for the serial inputs (Channel 42, Bits[15:8]) 0xF32B FTDM_IN43 FTDM mapping for the serial inputs (Channel 42, Bits[7:0]) 0xF32C FTDM_IN44 FTDM mapping for the serial inputs (Channel 43, Bits[31:24]) 0xF32D FTDM_IN45 FTDM mapping for the serial inputs (Channel 43, Bits[23:16]) 0xF32E FTDM_IN46 FTDM mapping for the serial inputs (Channel 43, Bits[15:8]) 0xF32F FTDM_IN47 FTDM mapping for the serial inputs (Channel 43, Bits[7:0]) Rev. D | Page 79 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Address Register Description 0xF330 FTDM_IN48 FTDM mapping for the serial inputs (Channel 44, Bits[31:24]) 0xF331 FTDM_IN49 FTDM mapping for the serial inputs (Channel 44, Bits[23:16]) 0xF332 FTDM_IN50 FTDM mapping for the serial inputs (Channel 44, Bits[15:8]) 0xF333 FTDM_IN51 FTDM mapping for the serial inputs (Channel 44, Bits[7:0]) 0xF334 FTDM_IN52 FTDM mapping for the serial inputs (Channel 45, Bits[31:24]) 0xF335 FTDM_IN53 FTDM mapping for the serial inputs (Channel 45, Bits[23:16]) 0xF336 FTDM_IN54 FTDM mapping for the serial inputs (Channel 45, Bits[15:8]) 0xF337 FTDM_IN55 FTDM mapping for the serial inputs (Channel 45, Bits[7:0]) 0xF338 FTDM_IN56 FTDM mapping for the serial inputs (Channel 46, Bits[31:24]) 0xF339 FTDM_IN57 FTDM mapping for the serial inputs (Channel 46, Bits[23:16]) 0xF33A FTDM_IN58 FTDM mapping for the serial inputs (Channel 46, Bits[15:8]) 0xF33B FTDM_IN59 FTDM mapping for the serial inputs (Channel 46, Bits[7:0]) 0xF33C FTDM_IN60 FTDM mapping for the serial inputs (Channel 47, Bits[31:24]) 0xF33D FTDM_IN61 FTDM mapping for the serial inputs (Channel 47, Bits[23:16]) 0xF33E FTDM_IN62 FTDM mapping for the serial inputs (Channel 47, Bits[15:8]) 0xF33F FTDM_IN63 FTDM mapping for the serial inputs (Channel 47, Bits[7:0]) 0xF380 FTDM_OUT0 FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[31:24]) 0xF381 FTDM_OUT1 FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[23:16]) 0xF382 FTDM_OUT2 FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[15:8]) 0xF383 FTDM_OUT3 FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[7:0]) 0xF384 FTDM_OUT4 FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[31:24]) 0xF385 FTDM_OUT5 FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[23:16]) 0xF386 FTDM_OUT6 FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[15:8]) 0xF387 FTDM_OUT7 FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[7:0]) 0xF388 FTDM_OUT8 FTDM mapping for the serial outputs (Port 2, Channel 2, Bits[31:24]) 0xF389 FTDM_OUT9 FTDM mapping for the serial outputs (Port 2, Channel 2, Bits[23:16]) 0xF38A FTDM_OUT10 FTDM mapping for the serial outputs (Port 2, Channel 2, Bits[15:8]) 0xF38B FTDM_OUT11 FTDM mapping for the serial outputs (Port 2, Channel 2, Bits[7:0]) 0xF38C FTDM_OUT12 FTDM mapping for the serial outputs (Port 2, Channel 3, Bits[31:24]) 0xF38D FTDM_OUT13 FTDM mapping for the serial outputs (Port 2, Channel 3, Bits[23:16]) 0xF38E FTDM_OUT14 FTDM mapping for the serial outputs (Port 2, Channel 3, Bits[15:8]) 0xF38F FTDM_OUT15 FTDM mapping for the serial outputs (Port 2, Channel 3, Bits[7:0]) 0xF390 FTDM_OUT16 FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[31:24]) 0xF391 FTDM_OUT17 FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[23:16]) 0xF392 FTDM_OUT18 FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[15:8]) 0xF393 FTDM_OUT19 FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[7:0]) 0xF394 FTDM_OUT20 FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[31:24]) 0xF395 FTDM_OUT21 FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[23:16]) 0xF396 FTDM_OUT22 FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[15:8]) 0xF397 FTDM_OUT23 FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[7:0]) 0xF398 FTDM_OUT24 FTDM mapping for the serial outputs (Port 2, Channel 6, Bits[31:24]) 0xF399 FTDM_OUT25 FTDM mapping for the serial outputs (Port 2, Channel 6, Bits[23:16]) 0xF39A FTDM_OUT26 FTDM mapping for the serial outputs (Port 2, Channel 6, Bits[15:8]) 0xF39B FTDM_OUT27 FTDM mapping for the serial outputs (Port 2, Channel 6, Bits[7:0]) 0xF39C FTDM_OUT28 FTDM mapping for the serial outputs (Port 2, Channel 7, Bits[31:24]) 0xF39D FTDM_OUT29 FTDM mapping for the serial outputs (Port 2, Channel 7, Bits[23:16]) 0xF39E FTDM_OUT30 FTDM mapping for the serial outputs (Port 2, Channel 7, Bits[15:8]) 0xF39F FTDM_OUT31 FTDM mapping for the serial outputs (Port 2, Channel 7, Bits[7:0]) 0xF3A0 FTDM_OUT32 FTDM mapping for the serial outputs (Port 3, Channel 0, Bits[31:24]) 0xF3A1 FTDM_OUT33 FTDM mapping for the serial outputs (Port 3, Channel 0, Bits[23:16]) 0xF3A2 FTDM_OUT34 FTDM mapping for the serial outputs (Port 3, Channel 0, Bits[15:8]) 0xF3A3 FTDM_OUT35 FTDM mapping for the serial outputs (Port 3, Channel 0, Bits[7:0]) 0xF3A4 FTDM_OUT36 FTDM mapping for the serial outputs (Port 3, Channel 1, Bits[31:24]) 0xF3A5 FTDM_OUT37 FTDM mapping for the serial outputs (Port 3, Channel 1, Bits[23:16]) Rev. D | Page 80 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Address Register Description 0xF3A6 FTDM_OUT38 FTDM mapping for the serial outputs (Port 3, Channel 1, Bits[15:8]) 0xF3A7 FTDM_OUT39 FTDM mapping for the serial outputs (Port 3, Channel 1, Bits[7:0]) 0xF3A8 FTDM_OUT40 FTDM mapping for the serial outputs (Port 3, Channel 2, Bits[31:24]) 0xF3A9 FTDM_OUT41 FTDM mapping for the serial outputs (Port 3, Channel 2, Bits[23:16]) 0xF3AA FTDM_OUT42 FTDM mapping for the serial outputs (Port 3, Channel 2, Bits[15:8]) 0xF3AB FTDM_OUT43 FTDM mapping for the serial outputs (Port 3, Channel 2, Bits[7:0]) 0xF3AC FTDM_OUT44 FTDM mapping for the serial outputs (Port 3, Channel 3, Bits[31:24]) 0xF3AD FTDM_OUT45 FTDM mapping for the serial outputs (Port 3, Channel 3, Bits[23:16]) 0xF3AE FTDM_OUT46 FTDM mapping for the serial outputs (Port 3, Channel 3, Bits[15:8]) 0xF3AF FTDM_OUT47 FTDM mapping for the serial outputs (Port 3, Channel 3, Bits[7:0]) 0xF3B0 FTDM_OUT48 FTDM mapping for the serial outputs (Port 3, Channel 4, Bits[31:24]) 0xF3B1 FTDM_OUT49 FTDM mapping for the serial outputs (Port 3, Channel 4, Bits[23:16]) 0xF3B2 FTDM_OUT50 FTDM mapping for the serial outputs (Port 3, Channel 4, Bits[15:8]) 0xF3B3 FTDM_OUT51 FTDM mapping for the serial outputs (Port 3, Channel 4, Bits[7:0]) 0xF3B4 FTDM_OUT52 FTDM mapping for the serial outputs (Port 3, Channel 5, Bits[31:24]) 0xF3B5 FTDM_OUT53 FTDM mapping for the serial outputs (Port 3, Channel 5, Bits[23:16]) 0xF3B6 FTDM_OUT54 FTDM mapping for the serial outputs (Port 3, Channel 5, Bits[15:8]) 0xF3B7 FTDM_OUT55 FTDM mapping for the serial outputs (Port 3, Channel 5, Bits[7:0]) 0xF3B8 FTDM_OUT56 FTDM mapping for the serial outputs (Port 3, Channel 6, Bits[31:24]) 0xF3B9 FTDM_OUT57 FTDM mapping for the serial outputs (Port 3, Channel 6, Bits[23:16]) 0xF3BA FTDM_OUT58 FTDM mapping for the serial outputs (Port 3, Channel 6, Bits[15:8]) 0xF3BB FTDM_OUT59 FTDM mapping for the serial outputs (Port 3, Channel 6, Bits[7:0]) 0xF3BC FTDM_OUT60 FTDM mapping for the serial outputs (Port 3, Channel 7, Bits[31:24]) 0xF3BD FTDM_OUT61 FTDM mapping for the serial outputs (Port 3, Channel 7, Bits[23:16]) 0xF3BE FTDM_OUT62 FTDM mapping for the serial outputs (Port 3, Channel 7, Bits[15:8]) 0xF3BF FTDM_OUT63 FTDM mapping for the serial outputs (Port 3, Channel 7, Bits[7:0]) ASYNCHRONOUS SAMPLE RATE CONVERTERS Audio is routed to the sample rate converters using the Sixteen channels of integrated asynchronous sample rate converters ASRC_INPUTx registers, and the target sample rate of each are available in the ADAU1452 and ADAU1451. These sample ASRC is configured using the ASRC_OUT_RATEx registers. rate converters are capable of receiving audio data input signals, A complete description of audio routing is included in the along with their corresponding clocks, and resynchronizing the Audio Signal Routing section. data stream to an arbitrary target sample rate. The sample rate Asynchronous Sample Rate Converter Group Delay converters use some filtering to accomplish this task; therefore, The group delay of the sample rate converter is dependent on the data output from the sample rate converter is not a bit- the input and output sampling frequencies, f and f , accurate representation of the data input. S_IN S_OUT respectively, as described in the following equations: The ADAU1450 has no ASRCs, so any data routed to the ASRCs For f > f , using the audio routing matrix or DSP core are lost. S_OUT S_IN 16 32 The 16 channels of sample rate converters are grouped into eight GDS= + f f stereo sets. These eight stereo sample rate converters are indivi- S_IN S_IN dually configurable and are referred to as ASRC 0 through ASRC 7. For f < f , S_OUT S_IN Channel 0 and Channel 1 belong to ASRC 0, Channel 2 and Channel 3 belong to ASRC 1, Channel 4 and Channel 5 belong 16  32   f  to ASRC 2, Channel 6 and Channel 7 belong to ASRC 3, Channel 8 GDS= + × S_IN  fS_IN  fS_IN   fS_OUT  and Channel 9 belong to ASRC 4, Channel 10 and Channel 11 belong to ASRC 5, Channel 12 and Channel 13 belong to ASRC 6, where GDS is the group delay in seconds. and Channel 14 and Channel 15 belong to ASRC 7. Rev. D | Page 81 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet ASRC Lock S/PDIF Interface Each ASRC monitors the incoming signal and attempts to lock For simplified interfacing on the system level, wire the on-chip on to the clock and data signals. When a valid signal is detected S/PDIF receiver and transmitter data ports directly to other and several consecutive valid samples are received, and there is S/PDIF-compatible equipment. The S/PDIF receiver consists of a valid output target sample rate, the corresponding bit in two audio channels that are input on one hardware pin (SPDIFIN). Register 0xF580 (ASRC_LOCK) signifies that the ASRC has The clock signal is embedded in the data using biphase mark successfully locked to the incoming signal. code. The S/PDIF transmitter consists of two audio channels ASRC Muting that are output on one hardware pin (SPDIFOUT). The clock signal is embedded in the data using biphase mark code. The The ASRC outputs can be manually muted at any time using the S/PDIF input and output word lengths can be independently set corresponding bits in Register 0xF581 (ASRC_MUTE). more to 16, 20, or 24 bits. options are available in the DSP core for creating a smooth The S/PDIF interface meets the S/PDIF consumer performance volume ramp when muting audio signals; therefore, in most specification, but does not meet the Audio Engineering Society cases, using the DSP program to manually mute signals is AES3 professional specification. preferable to using Register 0xF581. Asynchronous Sample Rate Converters Registers The ADAU1450 does not include S/PDIF interfaces, which means that its SPDIFIN and SPDIFOUT pins are nonfunctional An overview of the registers related to the ASRCs is shown in and must remain disconnected. Table 54. For a more detailed description, refer to the ASRC S/PDIF Receiver Status and Control Registers section. The S/PDIF input port is designed to accept both transistor-to- Table 54. Asynchronous Sample Rate Converters Registers transistor logic (TTL) and bipolar signals, provided there is an Address Register Description ac coupling capacitor on the input pin of the chip. Because the 0xF580 ASRC_LOCK ASRC lock status S/PDIF input data is most likely asynchronous to the DSP core, 0xF581 ASRC_MUTE ASRC mute the input data must be routed through an ASRC. 0xF582 ASRC0_RATIO ASRC ratio (ASRC 0, Channel 0 and Channel 1) The S/PDIF receiver works at a wide range of sampling frequencies 0xF583 ASRC1_RATIO ASRC ratio (ASRC 1, Channel 2 and between 18 kHz and 96 kHz. Channel 3) The S/PDIF receiver input is a comparator that is centered at 0xF584 ASRC2_RATIO ASRC ratio (ASRC 2, Channel 4 and IOVDD/2 and requires an input signal level of at least 200 mV p-p Channel 5) to operate properly. 0xF585 ASRC3_RATIO ASRC ratio (ASRC 3, Channel 6 and Channel 7) In addition to audio data, S/PDIF streams contain user data, 0xF586 ASRC4_RATIO ASRC ratio (ASRC 4, Channel 8 and channel status, validity bit, virtual LRCLK, and block start infor- Channel 9) mation. The receiver decodes audio data and sends it to the 0xF587 ASRC5_RATIO ASRC ratio (ASRC 5, Channel 10 and corresponding registers in the control register map, where the Channel 11) information can be read over the I2C or SPI slave port. 0xF588 ASRC6_RATIO ASRC ratio (ASRC 6, Channel 12 and For improved jitter performance, the S/PDIF clock recovery Channel 13) implementation is completely digital. The S/PDIF ports are 0xF589 ASRC7_RATIO ASRC ratio (ASRC 7, Channel 14 and designed to meet the following Audio Engineering Society Channel 15) (AES) and European Broadcasting Union (EBU) specifications: a jitter of 0.25 UI p-p at 8 kHz and higher, a jitter of 10 UI p-p below 200 Hz, and a minimum signal voltage of 200 mV. S/PDIF Transmitter The S/PDIF transmitter outputs two channels of audio data directly from the DSP core at the core rate. The extra nonaudio data bits on the transmitted signal can be copied directly from the S/PDIF receiver or programmed manually, using the corresponding registers in the control register map. Rev. D | Page 82 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Auxiliary Output Mode Table 55. S/PDIF Auxiliary Output Mode, TDM8 Data Format TDM8 The received data on the S/PDIF receiver can be converted to a Channel Description of Data Format TDM8 stream, bypass the SigmaDSP core, and be output directly 0 8 zero bits followed by 24 audio bits, recovered on a serial data output pin. This mode of operation is called from the left audio channel of the S/PDIF stream auxiliary output mode. Configure this mode using Register 0xF608 1 28 zero bits followed by the left parity bit, left (SPDIF_AUX_EN). The TDM8 output from the S/PDIF receiver validity bit, left user data, and left channel status regroups the recovered data in a format that is similar to TDM 2 30 zero bits followed by the compression type bit format, as shown in Table 55. (0b0 = AC3, 0b1 = DTS) and the audio type bit (0 = PCM, 1 = compressed) The S/PDIF receiver, when operating in auxiliary output mode, 3 No data also recovers the embedded BCLK_OUTx and LRCLK_OUTx 4 8 zero bits followed by 24 audio bits, recovered signals in the S/PDIF stream and outputs them on the corre- from the right audio channel of the S/PDIF stream sponding BCLK_OUTx and LRCLK_OUTx pins in master 5 28 zero bits followed by the right parity bit, right mode when Register 0xF608 (SPDIF_AUX_EN), Bits[3:0] validity bit, right user data, and right channel status (TDMOUT), are configured to enable auxiliary output mode. 6 No data The selected BCLK_OUTx signal has a frequency of 256× the 7 31 zero bits followed by the block start signal recovered sample rate, and the LRCLK_OUTx signal is a 50-50 duty cycle square wave that has the same frequency as the audio S/PDIF Interface Registers Overview sample rate (see Table 136). An overview of the registers related to the S/PDIF interface is shown in Table 56. For a more detailed description, refer to the S/PDIF Interface Registers section. Table 56. S/PDIF Interface Registers Address Register Description 0xF600 SPDIF_LOCK_DET S/PDIF receiver lock bit detection 0xF601 SPDIF_RX_CTRL S/PDIF receiver control 0xF602 SPDIF_RX_DECODE Decoded signals from the S/PDIF receiver 0xF603 SPDIF_RX_COMPRMODE Compression mode from the S/PDIF receiver 0xF604 SPDIF_RESTART Automatically resume S/PDIF receiver audio input 0xF605 SPDIF_LOSS_OF_LOCK S/PDIF receiver loss of lock detection 0xF608 SPDIF_AUX_EN S/PDIF receiver auxiliary outputs enable 0xF60F SPDIF_RX_AUXBIT_READY S/PDIF receiver auxiliary bits ready flag 0xF610 to 0xF61B SPDIF_RX_CS_LEFT_x S/PDIF receiver channel status bits (left) 0xF620 to 0xF62B SPDIF_RX_CS_RIGHT_x S/PDIF receiver channel status bits (right) 0xF630 to 0xF63B SPDIF_RX_UD_LEFT_x S/PDIF receiver user data bits (left) 0xF640 to 0xF64B SPDIF_RX_UD_RIGHT_x S/PDIF receiver user data bits (right) 0xF650 to 0xF65B SPDIF_RX_VB_LEFT_x S/PDIF receiver validity bits (left) 0xF660 to 0xF66B SPDIF_RX_VB_RIGHT_x S/PDIF receiver validity bits (right) 0xF670 to 0xF67B SPDIF_RX_PB_LEFT_x S/PDIF receiver parity bits (left) 0xF680 to 0xF68B SPDIF_RX_PB_RIGHT_x S/PDIF receiver parity bits (right) 0xF690 SPDIF_TX_EN S/PDIF transmitter enable 0xF691 SPDIF_TX_CTRL S/PDIF transmitter control 0xF69F SPDIF_TX_AUXBIT_SOURCE S/PDIF transmitter auxiliary bits source select 0xF6A0 to 0xF6AB SPDIF_TX_CS_LEFT_x S/PDIF transmitter channel status bits (left) 0xF6B0 to 0xF6BB SPDIF_TX_CS_RIGHT_x S/PDIF transmitter channel status bits (right) 0xF6C0 to 0xF6CB SPDIF_TX_UD_LEFT_x S/PDIF transmitter user data bits (left) 0xF6D0 to 0xF6DB SPDIF_TX_UD_RIGHT_x S/PDIF transmitter user data bits (right) 0xF6E0 to 0xF6EB SPDIF_TX_VB_LEFT_x S/PDIF transmitter validity bits (left) 0xF6F0 to 0xF6FB SPDIF_TX_VB_RIGHT_x S/PDIF transmitter validity bits (right) 0xF700 to 0xF70B SPDIF_TX_PB_LEFT_x S/PDIF transmitter parity bits (left) 0xF710 to 0xF71B SPDIF_TX_PB_RIGHT_x S/PDIF transmitter parity bits (right) Rev. D | Page 83 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet DIGITAL PDM MICROPHONE INTERFACE Figure 72 shows an example circuit with two INMP522 PDM output MEMS microphones connected to the ADAU1452. Any of Up to four PDM microphones can be connected as audio the BCLK_INx pins or BCLK_OUTx pins can be used to provide inputs. Each pair of microphones can share a single data line; a clock signal to the microphones, and the data output of the therefore, using four PDM microphones requires two GPIO microphones can be connected to any MPx pin that has been pins. Any MPx pin can be used as a microphone data input, configured as a PDM microphone data input. with up to two microphones connected to each pin. This config- uration is set up using the corresponding MPx_MODE and 1.8V TO 3.3V DMIC_CTRLx registers. A bit clock pin from one of the serial input clock domains IOVDD (BCLK_INx) or one of the serial output clock domains (BCLK_ CLK OUTx) must be a master clock source, and its output signal must be connected to the PDM microphones to provide them INMP522 with a clock. VDD DATA 0.1µF ADAU1452/ PDM microphones, such as the INMP522 from InvenSense, L/R SELECT GND ADAU1451/ ADAU1450 typically require a bit clock frequency in the range of 1 MHz to 3.3 MHz, corresponding to audio sample rates of 15.625 kHz BCLK_INx OR to 51.5625 kHz. This means that the serial port corresponding BCLK_OUTx CLK to the BCLK_INx pin or BCLK_OUTx pin driving the PDM microphones must operate in 2-channel mode at a sample rate INMP522 between 16 kHz and 48 kHz. VDD DATA MPx 0.1µF PmDatMio nm fiiclrtoerpsh aornee a inndp uthtse anr ea vaauitloabmlea tfiocra lulys er oaut ttehde tDhrSoPu gcohr de,e cthi-e L/R SELECT GND GND 11486-075 ASRCs, and the serial output ports. Figure 72. Example Stereo PDM Microphone Input Circuit Digital PDM Microphone Interface Registers Overview An overview of the registers related to the digital microphone interface is shown in Table 57. For a more detailed description, see the Digital PDM Microphone Control Register section. Table 57. Digital PDM Microphone Interface Registers Address Register Description 0xF560 DMIC_CTRL0 Digital PDM microphone control (Channel 0 and Channel 1) 0xF561 DMIC_CTRL1 Digital PDM microphone control (Channel 2 and Channel 3) Rev. D | Page 84 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 MULTIPURPOSE PINS A total of 14 pins are available for use as general-purpose inputs/outputs (GPIOs) that are multiplexed with other functions, such as clock inputs/outputs. Because these pins have multiple functions, they are referred to as multipurpose pins, or MPx pins. MPx pins can be configured in several modes using the MPx_MODE registers:  Hardware input from pin  Software input (written via I2C or SPI slave control port)  Hardware output with internal pull-up  Hardware output without internal pull-up  PDM microphone data input  Flag output from panic manager 11486-076  Slave select line for master SPI port Figure 73. General Purpose Input Cell in the SigmaStudio Toolbox When configured in hardware input mode, a debounce circuit General-Purpose Outputs from the DSP Core is available to avoid data glitches. When an MPx pin is configured as a general-purpose output, a When operating in GPIO mode, pin status is updated 1× per Boolean value is output from the DSP program to the corre- sample. This means that the state of an MPx pin cannot change sponding MPx pin. Figure 74 shows the location of the General more than 1× in a sample period. Purpose Output cell within the SigmaStudio toolbox. General-Purpose Inputs to the DSP Core When an MPx pin is configured as a general-purpose input, its value can be used as a control logic signal in the DSP program, which is configured using SigmaStudio. Figure 73 shows the location of the General Purpose Input cell within the SigmaStudio toolbox. The 14 available general-purpose inputs in SigmaStudio map to the corresponding 14 MPx pins, but the general-purpose input data is valid only if the corresponding MPx pin has been configured as an input using the MPx_MODE registers. Figure 75 shows all of the general-purpose inputs as they appear in the SigmaStudio signal flow. 11486-078 Figure 74. General Purpose Output Cell in the SigmaStudio Toolbox 11486-077 Figure 75. Complete Set of General-Purpose Inputs in SigmaStudio Rev. D | Page 85 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet The 14 available general-purpose outputs in SigmaStudio map MPx pin is configured as an output using the MPx_MODE to the corresponding 14 MPx pins, but the general-purpose registers. Figure 76 shows all of the general-purpose outputs as output data is only output to the pin if the corresponding they appear in the SigmaStudio signal flow. 11486-079 Figure 76. Complete Set of General-Purpose Outputs in SigmaStudio Rev. D | Page 86 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Multipurpose Pin Registers Overview An overview of the registers related to GPIO is shown in Table 58. For a more detailed description, refer to the Multipurpose Pin Configuration Registers section. Table 58. Multipurpose Pin Registers Address Register Description 0xF510 MP0_MODE Multipurpose pin mode (SS_M/MP0) 0xF511 MP1_MODE Multipurpose pin mode (MOSI_M/MP1) 0xF512 MP2_MODE Multipurpose pin mode (SCL_M/SCLK_M/MP2) 0xF513 MP3_MODE Multipurpose pin mode (SDA_M/MISO_M/MP3) 0xF514 MP4_MODE Multipurpose pin mode (LRCLK_OUT0/MP4) 0xF515 MP5_MODE Multipurpose pin mode (LRCLK_OUT1/MP5) 0xF516 MP6_MODE Multipurpose pin mode (MP6) 0xF517 MP7_MODE Multipurpose pin mode (MP7) 0xF518 MP8_MODE Multipurpose pin mode (LRCLK_OUT2/MP8) 0xF519 MP9_MODE Multipurpose pin mode (LRCLK_OUT3/MP9) 0xF51A MP10_MODE Multipurpose pin mode (LRCLK_IN0/MP10) 0xF51B MP11_MODE Multipurpose pin mode (LRCLK_IN1/MP11) 0xF51C MP12_MODE Multipurpose pin mode (LRCLK_IN2/MP12) 0xF51D MP13_MODE Multipurpose pin mode (LRCLK_IN3/MP13) 0xF520 MP0_WRITE Multipurpose pin write value (SS_M/MP0) 0xF521 MP1_WRITE Multipurpose pin write value (MOSI_M/MP1) 0xF522 MP2_WRITE Multipurpose pin write value (SCL_M/SCLK_M/MP2) 0xF523 MP3_WRITE Multipurpose pin write value (SDA_M/MISO_M/MP3) 0xF524 MP4_WRITE Multipurpose pin write value (LRCLK_OUT0/MP4) 0xF525 MP5_WRITE Multipurpose pin write value (LRCLK_OUT1/MP5) 0xF526 MP6_WRITE Multipurpose pin write value (MP6) 0xF527 MP7_WRITE Multipurpose pin write value (MP7) 0xF528 MP8_WRITE Multipurpose pin write value (LRCLK_OUT2/MP8) 0xF529 MP9_WRITE Multipurpose pin write value (LRCLK_OUT3/MP9) 0xF52A MP10_WRITE Multipurpose pin write value (LRCLK_IN0/MP10) 0xF52B MP11_WRITE Multipurpose pin write value (LRCLK_IN1/MP11) 0xF52C MP12_WRITE Multipurpose pin write value (LRCLK_IN2/MP12) 0xF52D MP13_WRITE Multipurpose pin write value (LRCLK_IN3/MP13) 0xF530 MP0_READ Multipurpose pin read value (SS_M/MP0) 0xF531 MP1_READ Multipurpose pin read value (MOSI_M/MP1) 0xF532 MP2_READ Multipurpose pin read value (SCL_M/SCLK_M/MP2) 0xF533 MP3_READ Multipurpose pin read value (SDA_M/MISO_M/MP3) 0xF534 MP4_READ Multipurpose pin read value (LRCLK_OUT0/MP4) 0xF535 MP5_READ Multipurpose pin read value (LRCLK_OUT1/MP5) 0xF536 MP6_READ Multipurpose pin read value (MP6) 0xF537 MP7_READ Multipurpose pin read value (MP7) 0xF538 MP8_READ Multipurpose pin read value (LRCLK_OUT2/MP8) 0xF539 MP9_READ Multipurpose pin read value (LRCLK_OUT3/MP9) 0xF53A MP10_READ Multipurpose pin read value (LRCLK_IN0/MP10) 0xF53B MP11_READ Multipurpose pin read value (LRCLK_IN1/MP11) 0xF53C MP12_READ Multipurpose pin read value (LRCLK_IN2/MP12) 0xF53D MP13_READ Multipurpose pin read value (LRCLK_IN3/MP13) Rev. D | Page 87 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet AUXILIARY ADC There are six auxiliary ADC inputs with 10 bits of accuracy. These inputs are intended to be used as control signal inputs, such as potentiometer outputs or battery monitor signals. The auxiliary ADC samples each channel at a frequency of the core system clock divided by 6144. In the case of a default clocking scheme, the system clock is 294.912 MHz. Therefore, the auxiliary ADC sample rate is 48 kHz. If the system clock is scaled down by configuring the PLL to generate a lower output fprreoqpuoerntcioyn, tahteel ya.u xiliary ADC sample rate is scaled down 11486-081 Figure 78. Complete Set of Auxiliary ADC Inputs in SigmaStudio The auxiliary ADC is referenced so that a full-scale input is Auxiliary ADC Registers Overview achieved when the input voltage is equal to AVDD, and an input of zero is achieved when the input is connected to ground. An overview of the registers related to the auxiliary ADC is shown in Table 59. For details, see the Auxiliary ADC Registers The input impedance of the auxiliary ADC is approximately section. 200 kΩ at dc (0 Hz). Auxiliary ADC inputs can be used directly in the DSP program Table 59. Auxiliary ADC Registers (as configured in the SigmaStudio software). The instantaneous Address Register Description value of each ADC is also available in the ADC_READx registers, 0xF5A0 ADC_READ0 Auxiliary ADC read value (AUXADC0) which are accessible via the I2C or SPI slave control port. 0xF5A1 ADC_READ1 Auxiliary ADC read value (AUXADC1) Auxiliary ADC Inputs to the DSP Core 0xF5A2 ADC_READ2 Auxiliary ADC read value (AUXADC2) 0xF5A3 ADC_READ3 Auxiliary ADC read value (AUXADC3) Auxiliary ADC inputs can be used as control signals in the DSP 0xF5A4 ADC_READ4 Auxiliary ADC read value (AUXADC4) program as configured by SigmaStudio. Figure 77 shows the 0xF5A5 ADC_READ5 Auxiliary ADC read value (AUXADC5) location of the Auxiliary ADC Input cell in the SigmaStudio toolbox. SigmaDSP CORE The SigmaDSP core operates at a maximum frequency of 294.912 MHz (or 147.456 MHz in the ADAU1452-150 and ADAU1450), which is equivalent to 6144 clock cycles per sample at a sample rate of 48 kHz (or 3072 clock cycles per sample in the ADAU1452-150 and ADAU1450). For a sample rate of 48 kHz, the largest program possible consists of 6144 program instructions per sample (or 3072 instructions per sample in the ADAU1452-150 and ADAU1450). If the system clock remains at 294.912 MHz but the audio frame rate of the DSP core is decreased, programs consisting of more than 6144 instructions per sample are possible. The program RAM is 8192 words long, which means that the largest program possible (but only at lower sample rates) is 8192 instructions per frame. The core consists of four multipliers and two accumulators. 11486-080 A1.t2 a bni lolipoenr aMtiAngC f orepqeuraetniocyn so pf e2r9 4se.9c1o2n dM. HAtz ,m thaxe icmourem p eefrffiocriemnsc y, Figure 77. Auxiliary ADC Input Cell in the SigmaStudio Toolbox the core processes 3072 IIR biquad filters (single or double The six auxiliary input pins map to the corresponding six precision) per sample at a sample rate of 48 kHz. At maximum auxiliary ADC input cells. Figure 78 shows the complete set of efficiency, the core processes approximately 24,000 FIR filter auxiliary ADC input cells in SigmaStudio. taps per sample at a sample rate of 48 kHz. The instruction set is a single instruction, multiple data (SIMD) computing model. The DSP core is 32-bit fixed-point, with an 8.24 data format for audio. Rev. D | Page 88 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 The four multipliers are 64-bit double precision, capable of multi- Numeric Formats plying an 8.56 format number by an 8.24 number. The multiply DSP systems commonly use a standard numeric format. accumulators consist of 16 registers, with a depth of 80 bits. The Fractional number systems are specified by an A.B format, core can access RAM with a load/store width of 256 bits (eight where A is the number of bits to the left of the decimal point 32-bit words per frame). The two arithmetic/logic units (ALUs) and B is the number of bits to the right of the decimal point. have an 80-bit width and operate on numbers in 24.56 format. The same numeric format is used for both the parameter and The 24.56-bit format provides more than 42 dB of headroom. data values. It is possible to create combinations of time domain and A digital clipper circuit is used within the DSP core before frequency domain processing, using block and sample frame outputting to the serial port outputs, ASRCs, and S/PDIF. This interrupts. Sixteen data address generator (DAG) registers are clips the top seven bits (and the LSB) of the signal to produce a available, and circular buffer addressing is possible. 24-bit output with a range of +1.0 (minus 1 LSB) to −1.0. Many of the signal processing functions are coded using full, Figure 79 shows the maximum signal levels at each point in 64-bit, double precision arithmetic. The serial port input and the data flow in both binary and decibel levels. output word lengths are 24 bits, but eight extra headroom bits are used in the processor to allow internal gains of up to 48 dB without clipping. Additional gains can be achieved by initially scaling down the input signal in the DSP signal flow. DSP CORE 8.24 FORMAT 42dB OF HEADROOM DYNAMIC RANGE = 192dB SERIAL INPUT PORT (HEADROOM) SERIAL OUTPUT PORT 1.23 FORMAT 1.23 FORMAT MAXIMUM 0dBFS MAXIMUM 0dBFS DYNAMIC RANGE = 144dB DYNAMIC RANGE = 144dB 24-BITS 32-BITS 24-BITS (HEADROOM) 11486-082 Figure 79. Signal Range for 1.23 Format (Serial Ports, ASRCs) and 8.24 Format (DSP Core) Numerical Format: 8.24 Linear range: −128.0 to (+128.0 − 1 LSB) Dynamic range (ratio of the largest possible signal level to the smallest possible non-zero signal level): 192 dB Examples: 0b 1000 0000 0000 0000 0000 0000 0000 0000 = 0x80000000 = −128.0 0b 1110 0000 0000 0000 0000 0000 0000 0000 = 0xE0000000 = −32.0 0b 1111 1000 0000 0000 0000 0000 0000 0000 = 0xF8000000 = −8.0 0b 1111 1110 0000 0000 0000 0000 0000 0000 = 0xFE000000 = −2 0b 1111 1111 0000 0000 0000 0000 0000 0000 = 0xFF000000 = −1 0b 1111 1111 1000 0000 0000 0000 0000 0000 = 0xFF800000 = −0.5 0b 1111 1111 1110 0110 0110 0110 0110 0110 = 0xFFE66666 = −0.1 0b 1111 1111 1111 1111 1111 1111 1111 1111 = 0xFFFFFFFF = −0.00000005 (1 LSB below 0.0) 0b 0000 0000 0000 0000 0000 0000 0000 0000 = 0x00000000 = 0.0 0b 0000 0000 0000 0000 0000 0000 0000 0001 = 0x00000001 = 0.00000005 (1 LSB above 0.0) 0b 0000 0000 0001 1001 1001 1001 1001 1001 = 0x00199999 = 0.1 0b 0000 0000 0100 0000 0000 0000 0000 0000 = 0x00400000 = 0.25 0b 0000 0000 1000 0000 0000 0000 0000 0000 = 0x00800000 = 0.5 0b 0000 0001 0000 0000 0000 0000 0000 0000 = 0x01000000 = 1.0 0b 0000 0010 0000 0000 0000 0000 0000 0000 = 0x02000000 = 2.0 0b 0111 1111 1111 1111 1111 1111 1111 1111 = 0x7FFFFFFF = 127.99999994 (1 LSB below 128.0) Rev. D | Page 89 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Numerical Format: 32.0 The 32.0 format is used for logic signals in the DSP program flow that are integers. Linear range: −2,147,483,648 to +2,147,483,647 Dynamic range (ratio of the largest possible signal level to the smallest possible non-zero signal level): 192 dB Examples: 0b 1000 0000 0000 0000 0000 0000 0000 0000 = 0x80000000 = −2147483648 0b 1000 0000 0000 0000 0000 0000 0000 0001 = 0x80000001 = −2147483647 0b 1000 0000 0000 0000 0000 0000 0000 0010 = 0x80000002 = −2147483646 0b 1100 0000 0000 0000 0000 0000 0000 0000 = 0xC0000000 = −1073741824 0b 1110 0000 0000 0000 0000 0000 0000 0000 = 0xE0000000 = −536870912 0b 1111 1111 1111 1111 1111 1111 1111 1100 = 0xFFFFFFFC = −4 0b 1111 1111 1111 1111 1111 1111 1111 1110 = 0xFFFFFFFE = −2 0b 1111 1111 1111 1111 1111 1111 1111 1111 = 0xFFFFFFFF = −1 0b 0000 0000 0000 0000 0000 0000 0000 0000 = 0x00000000 = 0 0b 0000 0000 0000 0000 0000 0000 0000 0001 = 0x00000001 = 1 0b 0000 0000 0000 0000 0000 0000 0000 0010 = 0x00000002 = 2 0b 0000 0000 0000 0000 0000 0000 0000 0011 = 0x00000003 = 3 0b 0000 0000 0000 0000 0000 0000 0000 0100 = 0x00000004 = 4 0b 0111 1111 1111 1111 1111 1111 1111 1110 = 0x7FFFFFFE = 2147483646 0b 0111 1111 1111 1111 1111 1111 1111 1111 = 0x7FFFFFFF = 2147483647 Programming the SigmaDSP Core Hardware Accelerators The SigmaDSP is programmable via the SigmaStudio graphical The core includes accelerators like division, square root, barrel development tools. shifters, base-2 logarithm, base-2 exponential, slew, and a When the SigmaDSP core is running a program and the user needs pseudorandom number generator. This reduces the number of to reprogram the program and data memories during operation instructions required for complex audio processing algorithms. of the device, the core must be stopped when the memory is The division accelerator enables efficient processing for audio being updated to avoid undesired noises on the DSP outputs. algorithms like compression and limiting. The square root accel- For programming the DSP at boot time, or to perform a full erator enables efficient processing for audio algorithms such as reset, see the System Initialization Sequence, Table 27, for loudness, rms envelopes, and filter coefficient calculations. The details. logarithm and exponent accelerators enable efficient processing for audio algorithms involving decibel conversion. The slew For reprogramming the memories during operation without accelerators provide for click-free updates of parameters that must performing a full reset, care must be exercised to stop the DSP change slowly over time, allowing audio processing algorithms to prevent clicks or pops. There are two levels of stopping the such as mixers, crossfaders, dynamic filters, and dynamic DSP. Hibernate mode disables interrupts so that the core stops volume controls. The pseudorandom number generator can processing when all the interrupts have completed, and only efficiently produce white noise, pink noise, and dither. No-Op instructions are executed. Kill core mode fully stops the core and all processing is stopped. To overwrite program memory, the user must fully stop the core. If the user wishes to only update many parameters simultaneously and not update the DSP program, the core can be left in hibernation mode, and there is no need to stop the core (see Table 60 for the procedure). Rev. D | Page 90 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Table 60. Example DSP Reprogramming or Updating During Operation Register Write Sequence Address Data Register/Memory Description 0xF400 0x00, 0x01 Hibernate Hibernate on. Not Applicable Not applicable Not applicable If the DSP is executing a program, wait for the current sample or block to finish processing. For programs with no block processing elements in the signal flow, use the length of one sample. For example, at a sample rate of 48 kHz, one sample is 1/48000 sec, or 20.83 µs. For programs with block processing elements in the signal flow, use the length of one block. For example, at a sample rate of 48 kHz, with a block size of 256 samples, one block is 256/48,000 sec, or 5.33 ms. 0xF403 0x00, 0x01 KILL_CORE If loading in a new DSP program is desired, stop the core immediately using this command. If only loading in new parameters, killing the core is not required. 0xC000 Data generated by Program RAM If updating the program, download the new program RAM contents using a SigmaStudio data block write (data provided by SigmaStudio compiler). 0x0000 Data generated by DM0 RAM data Update Data Memory DM0 using a block write (data provided by SigmaStudio SigmaStudio compiler). 0x6000 Data generated by DM1 RAM data Update Data Memory DM1 using a block write (data provided by SigmaStudio SigmaStudio compiler); the start address of DM1 can vary, depending on the SigmaStudio compilation. 0xF404 0x00, 0x00 START_ADDRESS If a new program was downloaded, program the start address as defined by the SigmaStudio compiler. This step is not required if only updating parameters. 0xF403 0x00, 0x00 KILL_CORE If the core was stopped, remove the KILL_CORE state to allow the core to be started when the START_CORE sequence is performed. Skip this instruction and the following three instructions if only the parameters were changed and the only core was placed in hibernation mode. 0xF402 0x00, 0x00 START_CORE Start the low to high transition. Skip this instruction if the core was not stopped. 0xF402 0x00, 0x01 START_CORE Start the core. Complete the low to high transition. Skip this instruction if the core was not stopped. Not Applicable Not applicable Not applicable Wait 50 µs for the initialization program to execute. Skip this instruction if the core was not stopped. 0xF400 0x00, 0x00 Hibernate Hibernate off. This starts the program running. Rev. D | Page 91 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Reliability Features built in, self test feature that runs automatically when the device is in operation. If a memory corruption is detected, the appropriate Several reliability features are controlled by a panic manager flag is signaled in the panic manager. The program running in subsystem that monitors the state of the SigmaDSP core and the DSP core can monitor the state of the panic manager and memories and generates alerts if error conditions are encountered. can mute the audio outputs if an error is encountered, and external The panic manager indicates error conditions to the user via devices, such as microcontrollers, can poll the panic manager register flags and GPIO outputs. The origin of the error can be registers or monitor the multipurpose pins to perform some traced to different functional blocks such as the watchdog, preprogrammed action, if necessary. memory, stack, software program, and core operation codes. DSP Core and Reliability Registers Overview Although designed mostly as an aid for software development, the panic manager is also useful in monitoring the state of the An overview of the registers related to the DSP core is shown in memories over long periods of time, such as in applications Table 61. For a more detailed description, see the DSP Core where the system operates unattended for an extended period, Control Registers section and the Debug and Reliability and resets are infrequent. The memories in the device have a Registers Table 61. DSP Core and Reliability Registers Address Register Description 0xF400 HIBERNATE Hibernate setting 0xF401 START_PULSE Start pulse selection 0xF402 START_CORE Instruction to start the core 0xF403 KILL_CORE Instruction to stop the core 0xF404 START_ADDRESS Start address of the program 0xF405 CORE_STATUS Core status 0xF421 PANIC_CLEAR Clear the panic manager 0xF422 PANIC_PARITY_MASK Panic parity 0xF423 PANIC_SOFTWARE_MASK Panic Mask 0 0xF424 PANIC_WD_MASK Panic Mask 1 0xF425 PANIC_STACK_MASK Panic Mask 2 0xF426 PANIC_LOOP_MASK Panic Mask 3 0xF427 PANIC_FLAG Panic flag 0xF428 PANIC_CODE Panic code 0xF433 SOFTWARE_VALUE_0 Software Panic Value 0 0xF434 SOFTWARE_VALUE_1 Software Panic Value 1 0xF432 EXECUTE_COUNT Execute stage error program count 0xF443 WATCHDOG_MAXCOUNT Watchdog maximum count 0xF444 WATCHDOG_PRESCALE Watchdog prescale 0xF450 BLOCKINT_EN Enable block interrupts 0xF451 BLOCKINT_VALUE Value for the block interrupt counter 0xF460 PROG_CNTR0 Program counter, Bits[23:16] 0xF461 PROG_CNTR1 Program counter, Bits[15:0] 0xF462 PROG_CNTR_CLEAR Program counter clear 0xF463 PROG_CNTR_LENGTH0 Program counter length, Bits[23:16] 0xF464 PROG_CNTR_LENGTH1 Program counter length, Bits[15:0] 0xF465 PROG_CNTR_MAXLENGTH0 Program counter maximum length, Bits[23:16] Rev. D | Page 92 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 SOFTWARE FEATURES The address_SafeLoad parameter is the target address in parameter Software Safeload RAM. This designates the first address to be written in the safe- load transfer. If more than one word is written, the address To update parameters in real time and avoid pop and click increments automatically for each data-word. noises on the output, a software safeload mechanism has been implemented by default in the SigmaStudio compiler. SigmaStudio The num_SafeLoad parameter designates the number of words automatically sets up the necessary code and parameters for all to be written. For a biquad filter algorithm, the number of words new projects. The safeload code fills the beginning section of to be written is five because there are five coefficients in a biquad the DM1 RAM. In older versions of SigmaStudio (prior to IIR filter. For a simple mono gain algorithm, the number of words Version 3.13), the exact parameter addresses were not fixed; to be written is one. This parameter also serves as the trigger; therefore, the addresses had to be obtained by reading the log when it is written, a safeload write is triggered on the next frame. file generated by the compiler. When recompiling a program The safeload mechanism is software based and executes 1× per compiled with an older version of SigmaStudio, the safeload audio frame. System designers must take care when designing the address is still configured by the compiler and can reside in communication protocol. A delay that is ≥ than the sampling different addresses if the program is changed. This process is to period (the inverse of the sampling frequency) is required between prevent the compiler from moving the safeload memory address each safeload write. At a sample rate of 48 kHz, this equates to a when an archived program is recompiled to only make minor delay of ≥20.83 μs. Not observing this delay corrupts the down- adjustments to parameters. If there is a microcontroller in the loaded data. system, the safeload address changes and that requires that the In older programs generated by older revisions of the compiler, the microcontroller code also be changed. With SigmaStudio, Version compiler has control over the addresses used for software safeload, 4.0 and newer, it is possible to change a project developed on an the addresses assigned to each parameter may differ from the earlier version over to a fixed Safeload memory location. The default values in Table 62. The compiler generates a file named checkbox for this setting can be found in the Advance compiler_output.log in the project folder where the SigmaStudio Framework Configuration menu. project is stored on the hard drive. In this file, the addresses For recent versions of SigmaStudio, Version 3.14 and newer, the assigned to the software safeload parameters can be confirmed. safeload memory addresses are located as outlined in Table 62. Figure 80 shows an example of the software safeload parameter Table 62. Software Safeload Memory Address Defaults definitions in an excerpt from the compiler_output.log file. Address (Hex) Parameter Function To execute a software safeload operation, take the following steps: 0x6000 data_SafeLoad[0] Safeload Data Slot 0 1. Confirm that no safeload operation has been executed in 0x6001 data_SafeLoad[1] Safeload Data Slot 1 the span of the last audio sample. 0x6002 data_SafeLoad[2] Safeload Data Slot 2 2. Write the desired data to the data_SafeLoad, Bit x 0x6003 data_SafeLoad[3] Safeload Data Slot 3 parameters, starting at data_SafeLoad, Bit 0, and 0x6004 data_SafeLoad[4] Safeload Data Slot 4 incrementing, as needed, up to a maximum of five 0x6005 address_SafeLoad Target address for safeload transfer parameters. 0x6006 num_SafeLoad Number of words to write/ 3. Write the desired starting target address to the safeload trigger address_SafeLoad parameter. 4. Write the number of words to be transferred to the The first five addresses in Table 62 are the five data_SafeLoad num_SafeLoad parameter. The minimum write length is parameters, which are slots for storing the data that is going to one word, and the maximum write length is five words. be transferred into another target memory location. The safeload 5. Wait one audio frame for the safeload operation to complete. parameter space contains five data slots, by default, because most standard signal processing algorithms have five parameters or fewer. Rev. D | Page 93 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet 11486-083 Figure 80. Compiler Log Output Excerpt with Safeload Module Definitions PIN DRIVE STRENGTH, SLEW RATE, AND PULL Soft Reset Function CONFIGURATION The soft reset function allows the device to enter a state similar to when the hardware RESET pin is connected to ground. All control Every digital output pin has configurable drive strength and slew rate, which allows the current sourcing ability of the driver registers are reset to their default values, except the PLL registers, to be modified to fit the application circuit. In general, higher as follows: Register 0xF000 (PLL_CTRL0), Register 0xF001 drive strength is needed to improve signal integrity when driving (PLL_CTRL1), Register 0xF002 (PLL_CLK_SRC), Register 0xF003 high frequency clocks over long distances. Lower drive strength (PLL_ENABLE), Register 0xF004 (PLL_LOCK), Register 0xF005 can be used for lower frequency clock signals, shorter traces, or (MCLK_OUT), and Register 0xF006 (PLL_WATCHDOG), as in cases where reduced system electromagnetic interference (EMI) well as the registers related to the panic manager. is desired. Slew rate can be increased if the edges of the clock Table 63 gives an overview of the register related to the soft reset signal have rise or fall times that are too long. To achieve adequate function. For more details, see the Soft Reset Register section. signal integrity and minimize electromagnetic emissions, use Table 63. Soft Reset Register the drive strength and slew rate settings in combination with Address Name Description good mixed-signal PCB design practices. 0xF890 SOFT_RESET Software reset Pin Drive Strength, Slew Rate, and Pull Configuration Registers An overview of the registers related to pin drive strength, slew rate, and pull configuration is listed in Table 64. For a more detailed description, see the Hardware Interfacing Registers section. Table 64. Pin Drive Strength, Slew Rate, and Pull Configuration Registers Address Register Description 0xF780 BCLK_IN0_PIN BCLK input pin drive strength and slew rate (BCLK_IN0) 0xF781 BCLK_IN1_PIN BCLK input pin drive strength and slew rate (BCLK_IN1) 0xF782 BCLK_IN2_PIN BCLK input pin drive strength and slew rate (BCLK_IN2) 0xF783 BCLK_IN3_PIN BCLK input pin drive strength and slew rate (BCLK_IN3) 0xF784 BCLK_OUT0_PIN BCLK output pin drive strength and slew rate (BCLK_OUT0) 0xF785 BCLK_OUT1_PIN BCLK output pin drive strength and slew rate (BCLK_OUT1) 0xF786 BCLK_OUT2_PIN BCLK output pin drive strength and slew rate (BCLK_OUT2) 0xF787 BCLK_OUT3_PIN BCLK output pin drive strength and slew rate (BCLK_OUT3) 0xF788 LRCLK_IN0_PIN LRCLK input pin drive strength and slew rate (LRCLK_IN0) 0xF789 LRCLK_IN1_PIN LRCLK input pin drive strength and slew rate (LRCLK_IN1) 0xF78A LRCLK_IN2_PIN LRCLK input pin drive strength and slew rate (LRCLK_IN2) 0xF78B LRCLK_IN3_PIN LRCLK input pin drive strength and slew rate (LRCLK_IN3) 0xF78C LRCLK_OUT0_PIN LRCLK output pin drive strength and slew rate (LRCLK_OUT0) 0xF78D LRCLK_OUT1_PIN LRCLK output pin drive strength and slew rate (LRCLK_OUT1) 0xF78E LRCLK_OUT2_PIN LRCLK output pin drive strength and slew rate (LRCLK_OUT2) Rev. D | Page 94 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Address Register Description 0xF78F LRCLK_OUT3_PIN LRCLK output pin drive strength and slew rate (LRCLK_OUT3) 0xF790 SDATA_IN0_PIN SDATA input pin drive strength and slew rate (SDATA_IN0) 0xF791 SDATA_IN1_PIN SDATA input pin drive strength and slew rate (SDATA_IN1) 0xF792 SDATA_IN2_PIN SDATA input pin drive strength and slew rate (SDATA_IN2) 0xF793 SDATA_IN3_PIN SDATA input pin drive strength and slew rate (SDATA_IN3) 0xF794 SDATA_OUT0_PIN SDATA output pin drive strength and slew rate (SDATA_OUT0) 0xF795 SDATA_OUT1_PIN SDATA output pin drive strength and slew rate (SDATA_OUT1) 0xF796 SDATA_OUT2_PIN SDATA output pin drive strength and slew rate (SDATA_OUT2) 0xF797 SDATA_OUT3_PIN SDATA output pin drive strength and slew rate (SDATA_OUT3) 0xF798 SPDIF_TX_PIN S/PDIF transmitter pin drive strength and slew rate 0xF799 SCLK_SCL_PIN SCLK/SCL pin drive strength and slew rate 0xF79A MISO_SDA_PIN MISO/SDA pin drive strength and slew rate 0xF79B SS_PIN SS/ADDR0 pin drive strength and slew rate 0xF79C MOSI_ADDR1_PIN MOSI/ADDR1 pin drive strength and slew rate 0xF79D SCLK_SCL_M_PIN SCL_M/SCLK_M/MP2 pin drive strength and slew rate 0xF79E MISO_SDA_M_PIN SDA_M/MISO_M/MP3 pin drive strength and slew rate 0xF79F SS_M_PIN SS_M/MP0 pin drive strength and slew rate 0xF7A0 MOSI_M_PIN MOSI_M/MP1 pin drive strength and slew rate 0xF7A1 MP6_PIN MP6 pin drive strength and slew rate 0xF7A2 MP7_PIN MP7 pin drive strength and slew rate 0xF7A3 CLKOUT_PIN CLKOUT pin drive strength and slew rate Rev. D | Page 95 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet GLOBAL RAM AND CONTROL REGISTER MAP The complete set of addresses accessible via the slave I2C/SPI when they are detected. Modulo memory addressing is used in control port is described in this section. The addresses are several audio processing algorithms. The boundaries between divided into two main parts: memory and registers. the fixed and rotating memories are set in SigmaStudio by the compiler, and these boundaries require no action on the part of RANDOM ACCESS MEMORY the user. The ADAU1452 has 1.28 Mb of data (40 kWords storing 32-bit Data and parameters assignment to the different memory spaces data). The ADAU1451 has 512 kb of data (16 kWords storing are handled in software. The modulo boundary locations are 32-bit data). The ADAU1450 has 256 kb of data (8 kWords flexible. storing 32-bit data). A ROM table (of over seven kWords), containing a set of The ADAU1452/ADAU1451/ADAU1450 have eight kWords of commonly used constants, can be accessed by the DSP core. program memory. Program memory consists of 32 bit words. This memory is used to increase the efficiency of audio processing Op codes for the DSP core are either 32 bits or 64 bits; therefore, algorithm development. The table includes information such as program instructions can take up one or two addresses in trigonometric tables, including sine, cosine, tangent and hyper- memory. The program memory has parity bit protection. The bolic tangent, twiddle factors for frequency domain processing, panic manager flags parity errors when they are detected. real mathematical constants, such as π and factors of 2, and Program memory can only be written or read when the core complex constants. The ROM table is not accessible from the is stopped. The program memory is hardware protected so it I2C or SPI slave control port. cannot be accidentally overwritten or corrupted at run time. All memory addresses store 32 bits (four bytes) of data. The The DSP core is able to directly access all memory and registers. memory spaces for the ADAU1452 are defined in Table 65. The Data memory acts as a storage area for both audio data and signal memory spaces for the ADAU1451 are defined in Table 66. The processing parameters, such as filter coefficients. The data memory memory spaces for the ADAU1450 are defined in Table 67. has parity bit protection. The panic manager flags parity errors Table 65. ADAU1452 Memory Map Address Range Length Memory Data-Word Size 0x0000 to 0x4FFF 20480 words DM0 (Data Memory 0) 32 bits 0x6000 to 0xAFFF 20480 words DM1 (Data Memory 1) 32 bits 0xC000 to 0xDFFF 8192 words Program memory 32 bits Table 66. ADAU1451 Memory Map Address Range Length Memory Data-Word Size 0x0000 to 0x3FFF 8192 words DM0 (Data Memory 0) 32 bits 0x6000 to 0x9FFF 8192 words DM1 (Data Memory 1) 32 bits 0xC000 to 0xDFFF 8192 words Program memory 32 bits Table 67. ADAU1450 Memory Map Address Range Length Memory Data-Word Size 0x0000 to 0x1FFF 4096 words DM0 (Data Memory 0) 32 bits 0x6000 to 0x7FFF 4096 words DM1 (Data Memory 1) 32 bits 0xC000 to 0xDFFF 8192 words Program memory 32 bits Rev. D | Page 96 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 CONTROL REGISTERS OVERVIEW All control registers store 16 bits (two bytes) of data. The register map for the ADAU1452/ADAU1451/ADAU1450 is defined in Table 68. Table 68. Control Register Summary Address Register Name Description Reset RW 0xF000 PLL_CTRL0 PLL feedback divider 0x0060 RW 0xF001 PLL_CTRL1 PLL prescale divider 0x0000 RW 0xF002 PLL_CLK_SRC PLL clock source 0x0000 RW 0xF003 PLL_ENABLE PLL enable 0x0000 RW 0xF004 PLL_LOCK PLL lock 0x0000 R 0xF005 MCLK_OUT CLKOUT control 0x0000 RW 0xF006 PLL_WATCHDOG Analog PLL watchdog control 0x0001 RW 0xF020 CLK_GEN1_M Denominator (M) for Clock Generator 1 0x0006 RW 0xF021 CLK_GEN1_N Numerator (N) for Clock Generator 1 0x0001 RW 0xF022 CLK_GEN2_M Denominator (M) for Clock Generator 2 0x0009 RW 0xF023 CLK_GEN2_N Numerator (N) for Clock Generator 2 0x0001 RW 0xF024 CLK_GEN3_M Denominator (M) for Clock Generator 3 0x0000 RW 0xF025 CLK_GEN3_N Numerator for (N) Clock Generator 3 0x0000 RW 0xF026 CLK_GEN3_SRC Input Reference for Clock Generator 3 0x000E RW 0xF027 CLK_GEN3_LOCK Lock Bit for Clock Generator 3 input reference 0x0000 R 0xF050 POWER_ENABLE0 Power Enable 0 0x0000 RW 0xF051 POWER_ENABLE1 Power Enable 1 0x0000 RW 0xF100 ASRC_INPUT0 ASRC input selector (ASRC 0, Channel 0 and Channel 1) 0x0000 RW 0xF101 ASRC_INPUT1 ASRC input selector (ASRC 1, Channel 2 and Channel 3) 0x0000 RW 0xF102 ASRC_INPUT2 ASRC input selector (ASRC 2, Channel 4 and Channel 5) 0x0000 RW 0xF103 ASRC_INPUT3 ASRC input selector (ASRC 3, Channel 6 and Channel 7) 0x0000 RW 0xF104 ASRC_INPUT4 ASRC input selector (ASRC 4, Channel 8 and Channel 9) 0x0000 RW 0xF105 ASRC_INPUT5 ASRC input selector (ASRC 5, Channel 10 and Channel 11) 0x0000 RW 0xF106 ASRC_INPUT6 ASRC input selector (ASRC 6, Channel 12 and Channel 13) 0x0000 RW 0xF107 ASRC_INPUT7 ASRC input selector (ASRC 7, Channel 14 and Channel 15) 0x0000 RW 0xF140 ASRC_OUT_RATE0 ASRC output rate (ASRC 0, Channel 0 and Channel 1) 0x0000 RW 0xF141 ASRC_OUT_RATE1 ASRC output rate (ASRC 1, Channel 2 and Channel 3) 0x0000 RW 0xF142 ASRC_OUT_RATE2 ASRC output rate (ASRC 2, Channel 4 and Channel 5) 0x0000 RW 0xF143 ASRC_OUT_RATE3 ASRC output rate (ASRC 3, Channel 6 and Channel 7) 0x0000 RW 0xF144 ASRC_OUT_RATE4 ASRC output rate (ASRC 4, Channel 8 and Channel 9) 0x0000 RW 0xF145 ASRC_OUT_RATE5 ASRC output rate (ASRC 5, Channel 10 and Channel 11) 0x0000 RW 0xF146 ASRC_OUT_RATE6 ASRC output rate (ASRC 6, Channel 12 and Channel 13) 0x0000 RW 0xF147 ASRC_OUT_RATE7 ASRC output rate (ASRC 7, Channel 14 and Channel 15) 0x0000 RW 0xF180 SOUT_SOURCE0 Source of data for serial output ports (Channel 0 and Channel 1) 0x0000 RW 0xF181 SOUT_SOURCE1 Source of data for serial output ports (Channel 2 and Channel 3) 0x0000 RW 0xF182 SOUT_SOURCE2 Source of data for serial output ports (Channel 4 and Channel 5) 0x0000 RW 0xF183 SOUT_SOURCE3 Source of data for serial output ports (Channel 6 and Channel 7) 0x0000 RW 0xF184 SOUT_SOURCE4 Source of data for serial output ports (Channel 8 and Channel 9) 0x0000 RW 0xF185 SOUT_SOURCE5 Source of data for serial output ports (Channel 10 and Channel 11) 0x0000 RW 0xF186 SOUT_SOURCE6 Source of data for serial output ports (Channel 12 and Channel 13) 0x0000 RW 0xF187 SOUT_SOURCE7 Source of data for serial output ports (Channel 14 and Channel 15) 0x0000 RW 0xF188 SOUT_SOURCE8 Source of data for serial output ports (Channel 16 and Channel 17) 0x0000 RW 0xF189 SOUT_SOURCE9 Source of data for serial output ports (Channel 18 and Channel 19) 0x0000 RW 0xF18A SOUT_SOURCE10 Source of data for serial output ports (Channel 20 and Channel 21) 0x0000 RW 0xF18B SOUT_SOURCE11 Source of data for serial output ports (Channel 22 and Channel 23) 0x0000 RW 0xF18C SOUT_SOURCE12 Source of data for serial output ports (Channel 24 and Channel 25) 0x0000 RW 0xF18D SOUT_SOURCE13 Source of data for serial output ports (Channel 26 and Channel 27) 0x0000 RW 0xF18E SOUT_SOURCE14 Source of data for serial output ports (Channel 28 and Channel 29) 0x0000 RW 0xF18F SOUT_SOURCE15 Source of data for serial output ports (Channel 30 and Channel 31) 0x0000 RW 0xF190 SOUT_SOURCE16 Source of data for serial output ports (Channel 32 and Channel 33) 0x0000 RW Rev. D | Page 97 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Address Register Name Description Reset RW 0xF191 SOUT_SOURCE17 Source of data for serial output ports (Channel 34 and Channel 35) 0x0000 RW 0xF192 SOUT_SOURCE18 Source of data for serial output ports (Channel 36 and Channel 37) 0x0000 RW 0xF193 SOUT_SOURCE19 Source of data for serial output ports (Channel 38 and Channel 39) 0x0000 RW 0xF194 SOUT_SOURCE20 Source of data for serial output ports (Channel 40 and Channel 41) 0x0000 RW 0xF195 SOUT_SOURCE21 Source of data for serial output ports (Channel 42 and Channel 43) 0x0000 RW 0xF196 SOUT_SOURCE22 Source of data for serial output ports (Channel 44 and Channel 45) 0x0000 RW 0xF197 SOUT_SOURCE23 Source of data for serial output ports (Channel 46 and Channel 47) 0x0000 RW 0xF1C0 SPDIFTX_INPUT S/PDIF transmitter data selector 0x0000 RW 0xF200 SERIAL_BYTE_0_0 Serial Port Control 0 (SDATA_IN0) 0x0000 RW 0xF201 SERIAL_BYTE_0_1 Serial Port Control 1 (SDATA_IN0) 0x0002 RW 0xF204 SERIAL_BYTE_1_0 Serial Port Control 0 (SDATA_IN1) 0x0000 RW 0xF205 SERIAL_BYTE_1_1 Serial Port Control 1 (SDATA_IN1) 0x0002 RW 0xF208 SERIAL_BYTE_2_0 Serial Port Control 0 (SDATA_IN2) 0x0000 RW 0xF209 SERIAL_BYTE_2_1 Serial Port Control 1 (SDATA_IN2) 0x0002 RW 0xF20C SERIAL_BYTE_3_0 Serial Port Control 0 (SDATA_IN3) 0x0000 RW 0xF20D SERIAL_BYTE_3_1 Serial Port Control 1 (SDATA_IN3) 0x0002 RW 0xF210 SERIAL_BYTE_4_0 Serial Port Control 0 (SDATA_OUT0) 0x0000 RW 0xF211 SERIAL_BYTE_4_1 Serial Port Control 1 (SDATA_OUT0) 0x0002 RW 0xF214 SERIAL_BYTE_5_0 Serial Port Control 0 (SDATA_OUT1) 0x0000 RW 0xF215 SERIAL_BYTE_5_1 Serial Port Control 1 (SDATA_OUT1) 0x0002 RW 0xF218 SERIAL_BYTE_6_0 Serial Port Control 0 (SDATA_OUT2) 0x0000 RW 0xF219 SERIAL_BYTE_6_1 Serial Port Control 1 (SDATA_OUT2) 0x0002 RW 0xF21C SERIAL_BYTE_7_0 Serial Port Control 0 (SDATA_OUT3) 0x0000 RW 0xF21D SERIAL_BYTE_7_1 Serial Port Control 1 (SDATA_OUT3) 0x0002 RW 0xF300 FTDM_IN0 FTDM mapping for the serial inputs (Channel 32, Bits[31:24]) 0x0000 RW 0xF301 FTDM_IN1 FTDM mapping for the serial inputs (Channel 32, Bits[23:16]) 0x0000 RW 0xF302 FTDM_IN2 FTDM mapping for the serial inputs (Channel 32, Bits[15:8]) 0x0000 RW 0xF303 FTDM_IN3 FTDM mapping for the serial inputs (Channel 32, Bits[7:0]) 0x0000 RW 0xF304 FTDM_IN4 FTDM mapping for the serial inputs (Channel 33, Bits[31:24]) 0x0000 RW 0xF305 FTDM_IN5 FTDM mapping for the serial inputs (Channel 33, Bits[23:16]) 0x0000 RW 0xF306 FTDM_IN6 FTDM mapping for the serial inputs (Channel 33, Bits[15:8]) 0x0000 RW 0xF307 FTDM_IN7 FTDM mapping for the serial inputs (Channel 33, Bits[7:0]) 0x0000 RW 0xF308 FTDM_IN8 FTDM mapping for the serial inputs (Channel 34, Bits[31:24]) 0x0000 RW 0xF309 FTDM_IN9 FTDM mapping for the serial inputs (Channel 34, Bits[23:16]) 0x0000 RW 0xF30A FTDM_IN10 FTDM mapping for the serial inputs (Channel 34, Bits[15:8]) 0x0000 RW 0xF30B FTDM_IN11 FTDM mapping for the serial inputs (Channel 34, Bits[7:0]) 0x0000 RW 0xF30C FTDM_IN12 FTDM mapping for the serial inputs (Channel 35, Bits[31:24]) 0x0000 RW 0xF30D FTDM_IN13 FTDM mapping for the serial inputs (Channel 35, Bits[23:16]) 0x0000 RW 0xF30E FTDM_IN14 FTDM mapping for the serial inputs (Channel 35, Bits[15:8]) 0x0000 RW 0xF30F FTDM_IN15 FTDM mapping for the serial inputs (Channel 35, Bits[7:0]) 0x0000 RW 0xF310 FTDM_IN16 FTDM mapping for the serial inputs (Channel 36, Bits[31:24]) 0x0000 RW 0xF311 FTDM_IN17 FTDM mapping for the serial inputs (Channel 36, Bits[23:16]) 0x0000 RW 0xF312 FTDM_IN18 FTDM mapping for the serial inputs (Channel 36, Bits[15:8]) 0x0000 RW 0xF313 FTDM_IN19 FTDM mapping for the serial inputs (Channel 36, Bits[7:0]) 0x0000 RW 0xF314 FTDM_IN20 FTDM mapping for the serial inputs (Channel 37, Bits[31:24]) 0x0000 RW 0xF315 FTDM_IN21 FTDM mapping for the serial inputs (Channel 37, Bits[23:16]) 0x0000 RW 0xF316 FTDM_IN22 FTDM mapping for the serial inputs (Channel 37, Bits[15:8]) 0x0000 RW 0xF317 FTDM_IN23 FTDM mapping for the serial inputs (Channel 37, Bits[7:0]) 0x0000 RW 0xF318 FTDM_IN24 FTDM mapping for the serial inputs (Channel 38, Bits[31:24]) 0x0000 RW 0xF319 FTDM_IN25 FTDM mapping for the serial inputs (Channel 38, Bits[23:16]) 0x0000 RW 0xF31A FTDM_IN26 FTDM mapping for the serial inputs (Channel 38, Bits[15:8]) 0x0000 RW 0xF31B FTDM_IN27 FTDM mapping for the serial inputs (Channel 38, Bits[7:0]) 0x0000 RW 0xF31C FTDM_IN28 FTDM mapping for the serial inputs (Channel 39, Bits[31:24]) 0x0000 RW 0xF31D FTDM_IN29 FTDM mapping for the serial inputs (Channel 39, Bits[23:16]) 0x0000 RW Rev. D | Page 98 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Address Register Name Description Reset RW 0xF31E FTDM_IN30 FTDM mapping for the serial inputs (Channel 39, Bits[15:8]) 0x0000 RW 0xF31F FTDM_IN31 FTDM mapping for the serial inputs (Channel 39, Bits[7:0]) 0x0000 RW 0xF320 FTDM_IN32 FTDM mapping for the serial inputs (Channel 40, Bits[31:24]) 0x0000 RW 0xF321 FTDM_IN33 FTDM mapping for the serial inputs (Channel 40, Bits[23:16]) 0x0000 RW 0xF322 FTDM_IN34 FTDM mapping for the serial inputs (Channel 40, Bits[15:8]) 0x0000 RW 0xF323 FTDM_IN35 FTDM mapping for the serial inputs (Channel 40, Bits[7:0]) 0x0000 RW 0xF324 FTDM_IN36 FTDM mapping for the serial inputs (Channel 41, Bits[31:24]) 0x0000 RW 0xF325 FTDM_IN37 FTDM mapping for the serial inputs (Channel 41, Bits[23:16]) 0x0000 RW 0xF326 FTDM_IN38 FTDM mapping for the serial inputs (Channel 41, Bits[15:8]) 0x0000 RW 0xF327 FTDM_IN39 FTDM mapping for the serial inputs (Channel 41, Bits[7:0]) 0x0000 RW 0xF328 FTDM_IN40 FTDM mapping for the serial inputs (Channel 42, Bits[31:24]) 0x0000 RW 0xF329 FTDM_IN41 FTDM mapping for the serial inputs (Channel 42, Bits[23:16]) 0x0000 RW 0xF32A FTDM_IN42 FTDM mapping for the serial inputs (Channel 42, Bits[15:8]) 0x0000 RW 0xF32B FTDM_IN43 FTDM mapping for the serial inputs (Channel 42, Bits[7:0]) 0x0000 RW 0xF32C FTDM_IN44 FTDM mapping for the serial inputs (Channel 43, Bits[31:24]) 0x0000 RW 0xF32D FTDM_IN45 FTDM mapping for the serial inputs (Channel 43, Bits[23:16]) 0x0000 RW 0xF32E FTDM_IN46 FTDM mapping for the serial inputs (Channel 43, Bits[15:8]) 0x0000 RW 0xF32F FTDM_IN47 FTDM mapping for the serial inputs (Channel 43, Bits[7:0]) 0x0000 RW 0xF330 FTDM_IN48 FTDM mapping for the serial inputs (Channel 44, Bits[31:24]) 0x0000 RW 0xF331 FTDM_IN49 FTDM mapping for the serial inputs (Channel 44, Bits[23:16]) 0x0000 RW 0xF332 FTDM_IN50 FTDM mapping for the serial inputs (Channel 44, Bits[15:8]) 0x0000 RW 0xF333 FTDM_IN51 FTDM mapping for the serial inputs (Channel 44, Bits[7:0]) 0x0000 RW 0xF334 FTDM_IN52 FTDM mapping for the serial inputs (Channel 45, Bits[31:24]) 0x0000 RW 0xF335 FTDM_IN53 FTDM mapping for the serial inputs (Channel 45, Bits[23:16]) 0x0000 RW 0xF336 FTDM_IN54 FTDM mapping for the serial inputs (Channel 45, Bits[15:8]) 0x0000 RW 0xF337 FTDM_IN55 FTDM mapping for the serial inputs (Channel 45, Bits[7:0]) 0x0000 RW 0xF338 FTDM_IN56 FTDM mapping for the serial inputs (Channel 46, Bits[31:24]) 0x0000 RW 0xF339 FTDM_IN57 FTDM mapping for the serial inputs (Channel 46, Bits[23:16]) 0x0000 RW 0xF33A FTDM_IN58 FTDM mapping for the serial inputs (Channel 46, Bits[15:8]) 0x0000 RW 0xF33B FTDM_IN59 FTDM mapping for the serial inputs (Channel 46, Bits[7:0]) 0x0000 RW 0xF33C FTDM_IN60 FTDM mapping for the serial inputs (Channel 47, Bits[31:24]) 0x0000 RW 0xF33D FTDM_IN61 FTDM mapping for the serial inputs (Channel 47, Bits[23:16]) 0x0000 RW 0xF33E FTDM_IN62 FTDM mapping for the serial inputs (Channel 47, Bits[15:8]) 0x0000 RW 0xF33F FTDM_IN63 FTDM mapping for the serial inputs (Channel 47, Bits[7:0]) 0x0000 RW 0xF380 FTDM_OUT0 FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[31:24]) 0x0000 RW 0xF381 FTDM_OUT1 FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[23:16]) 0x0000 RW 0xF382 FTDM_OUT2 FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[15:8]) 0x0000 RW 0xF383 FTDM_OUT3 FTDM mapping for the serial outputs (Port 2, Channel 0, Bits[7:0]) 0x0000 RW 0xF384 FTDM_OUT4 FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[31:24]) 0x0000 RW 0xF385 FTDM_OUT5 FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[23:16]) 0x0000 RW 0xF386 FTDM_OUT6 FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[15:8]) 0x0000 RW 0xF387 FTDM_OUT7 FTDM mapping for the serial outputs (Port 2, Channel 1, Bits[7:0]) 0x0000 RW 0xF388 FTDM_OUT8 FTDM mapping for the serial outputs (Port 2, Channel 2, Bits[31:24]) 0x0000 RW 0xF389 FTDM_OUT9 FTDM mapping for the serial outputs (Port 2, Channel 2, Bits[23:16]) 0x0000 RW 0xF38A FTDM_OUT10 FTDM mapping for the serial outputs (Port 2, Channel 2, Bits[15:8]) 0x0000 RW 0xF38B FTDM_OUT11 FTDM mapping for the serial outputs (Port 2, Channel 2, Bits[7:0]) 0x0000 RW 0xF38C FTDM_OUT12 FTDM mapping for the serial outputs (Port 2, Channel 3, Bits[31:24]) 0x0000 RW 0xF38D FTDM_OUT13 FTDM mapping for the serial outputs (Port 2, Channel 3, Bits[23:16]) 0x0000 RW 0xF38E FTDM_OUT14 FTDM mapping for the serial outputs (Port 2, Channel 3, Bits[15:8]) 0x0000 RW 0xF38F FTDM_OUT15 FTDM mapping for the serial outputs (Port 2, Channel 3, Bits[7:0]) 0x0000 RW 0xF390 FTDM_OUT16 FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[31:24]) 0x0000 RW 0xF391 FTDM_OUT17 FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[23:16]) 0x0000 RW 0xF392 FTDM_OUT18 FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[15:8]) 0x0000 RW 0xF393 FTDM_OUT19 FTDM mapping for the serial outputs (Port 2, Channel 4, Bits[7:0]) 0x0000 RW Rev. D | Page 99 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Address Register Name Description Reset RW 0xF394 FTDM_OUT20 FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[31:24]) 0x0000 RW 0xF395 FTDM_OUT21 FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[23:16]) 0x0000 RW 0xF396 FTDM_OUT22 FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[15:8]) 0x0000 RW 0xF397 FTDM_OUT23 FTDM mapping for the serial outputs (Port 2, Channel 5, Bits[7:0]) 0x0000 RW 0xF398 FTDM_OUT24 FTDM mapping for the serial outputs (Port 2, Channel 6, Bits[31:24]) 0x0000 RW 0xF399 FTDM_OUT25 FTDM mapping for the serial outputs (Port 2, Channel 6, Bits[23:16]) 0x0000 RW 0xF39A FTDM_OUT26 FTDM mapping for the serial outputs (Port 2, Channel 6, Bits[15:8]) 0x0000 RW 0xF39B FTDM_OUT27 FTDM mapping for the serial outputs (Port 2, Channel 6, Bits[7:0]) 0x0000 RW 0xF39C FTDM_OUT28 FTDM mapping for the serial outputs (Port 2, Channel 7, Bits[31:24]) 0x0000 RW 0xF39D FTDM_OUT29 FTDM mapping for the serial outputs (Port 2, Channel 7, Bits[23:16]) 0x0000 RW 0xF39E FTDM_OUT30 FTDM mapping for the serial outputs (Port 2, Channel 7, Bits[15:8]) 0x0000 RW 0xF39F FTDM_OUT31 FTDM mapping for the serial outputs (Port 2, Channel 7, Bits[7:0]) 0x0000 RW 0xF3A0 FTDM_OUT32 FTDM mapping for the serial outputs (Port 3, Channel 0, Bits[31:24]) 0x0000 RW 0xF3A1 FTDM_OUT33 FTDM mapping for the serial outputs (Port 3, Channel 0, Bits[23:16]) 0x0000 RW 0xF3A2 FTDM_OUT34 FTDM mapping for the serial outputs (Port 3, Channel 0, Bits[15:8]) 0x0000 RW 0xF3A3 FTDM_OUT35 FTDM mapping for the serial outputs (Port 3, Channel 0, Bits[7:0]) 0x0000 RW 0xF3A4 FTDM_OUT36 FTDM mapping for the serial outputs (Port 3, Channel 1, Bits[31:24]) 0x0000 RW 0xF3A5 FTDM_OUT37 FTDM mapping for the serial outputs (Port 3, Channel 1, Bits[23:16]) 0x0000 RW 0xF3A6 FTDM_OUT38 FTDM mapping for the serial outputs (Port 3, Channel 1, Bits[15:8]) 0x0000 RW 0xF3A7 FTDM_OUT39 FTDM mapping for the serial outputs (Port 3, Channel 1, Bits[7:0]) 0x0000 RW 0xF3A8 FTDM_OUT40 FTDM mapping for the serial outputs (Port 3, Channel 2, Bits[31:24]) 0x0000 RW 0xF3A9 FTDM_OUT41 FTDM mapping for the serial outputs (Port 3, Channel 2, Bits[23:16]) 0x0000 RW 0xF3AA FTDM_OUT42 FTDM mapping for the serial outputs (Port 3, Channel 2, Bits[15:8]) 0x0000 RW 0xF3AB FTDM_OUT43 FTDM mapping for the serial outputs (Port 3, Channel 2, Bits[7:0]) 0x0000 RW 0xF3AC FTDM_OUT44 FTDM mapping for the serial outputs (Port 3, Channel 3, Bits[31:24]) 0x0000 RW 0xF3AD FTDM_OUT45 FTDM mapping for the serial outputs (Port 3, Channel 3, Bits[23:16]) 0x0000 RW 0xF3AE FTDM_OUT46 FTDM mapping for the serial outputs (Port 3, Channel 3, Bits[15:8]) 0x0000 RW 0xF3AF FTDM_OUT47 FTDM mapping for the serial outputs (Port 3, Channel 3, Bits[7:0]) 0x0000 RW 0xF3B0 FTDM_OUT48 FTDM mapping for the serial outputs (Port 3, Channel 4, Bits[31:24]) 0x0000 RW 0xF3B1 FTDM_OUT49 FTDM mapping for the serial outputs (Port 3, Channel 4, Bits[23:16]) 0x0000 RW 0xF3B2 FTDM_OUT50 FTDM mapping for the serial outputs (Port 3, Channel 4, Bits[15:8]) 0x0000 RW 0xF3B3 FTDM_OUT51 FTDM mapping for the serial outputs (Port 3, Channel 4, Bits[7:0]) 0x0000 RW 0xF3B4 FTDM_OUT52 FTDM mapping for the serial outputs (Port 3, Channel 5, Bits[31:24]) 0x0000 RW 0xF3B5 FTDM_OUT53 FTDM mapping for the serial outputs (Port 3, Channel 5, Bits[23:16]) 0x0000 RW 0xF3B6 FTDM_OUT54 FTDM mapping for the serial outputs (Port 3, Channel 5, Bits[15:8]) 0x0000 RW 0xF3B7 FTDM_OUT55 FTDM mapping for the serial outputs (Port 3, Channel 5, Bits[7:0]) 0x0000 RW 0xF3B8 FTDM_OUT56 FTDM mapping for the serial outputs (Port 3, Channel 6, Bits[31:24]) 0x0000 RW 0xF3B9 FTDM_OUT57 FTDM mapping for the serial outputs (Port 3, Channel 6, Bits[23:16]) 0x0000 RW 0xF3BA FTDM_OUT58 FTDM mapping for the serial outputs (Port 3, Channel 6, Bits[15:8]) 0x0000 RW 0xF3BB FTDM_OUT59 FTDM mapping for the serial outputs (Port 3, Channel 6, Bits[7:0]) 0x0000 RW 0xF3BC FTDM_OUT60 FTDM mapping for the serial outputs (Port 3, Channel 7, Bits[31:24]) 0x0000 RW 0xF3BD FTDM_OUT61 FTDM mapping for the serial outputs (Port 3, Channel 7, Bits[23:16]) 0x0000 RW 0xF3BE FTDM_OUT62 FTDM mapping for the serial outputs (Port 3, Channel 7, Bits[15:8]) 0x0000 RW 0xF3BF FTDM_OUT63 FTDM mapping for the serial outputs (Port 3, Channel 7, Bits[7:0]) 0x0000 RW 0xF400 HIBERNATE Hibernate setting 0x0000 RW 0xF401 START_PULSE Start pulse selection 0x0002 RW 0xF402 START_CORE Instruction to start the core 0x0000 RW 0xF403 KILL_CORE Instruction to stop the core 0x0000 RW 0xF404 START_ADDRESS Start address of the program 0x0000 RW 0xF405 CORE_STATUS Core status 0x0000 R 0xF421 PANIC_CLEAR Clear the panic manager 0x0000 RW 0xF422 PANIC_PARITY_MASK Panic parity 0x0003 RW 0xF423 PANIC_SOFTWARE_MASK Panic Mask 0 0x0000 RW 0xF424 PANIC_WD_MASK Panic Mask 1 0x0000 RW Rev. D | Page 100 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Address Register Name Description Reset RW 0xF425 PANIC_STACK_MASK Panic Mask 2 0x0000 RW 0xF426 PANIC_LOOP_MASK Panic Mask 3 0x0000 RW 0xF427 PANIC_FLAG Panic flag 0x0000 R 0xF428 PANIC_CODE Panic code 0x0000 R 0xF432 EXECUTE_COUNT Execute stage error program count 0x0000 R 0xF433 SOFTWARE_VALUE_0 Software Panic Value 0 0x0000 RW 0xF434 SOFTWARE_VALUE_1 Software Panic Value 1 0x0000 RW 0xF443 WATCHDOG_MAXCOUNT Watchdog maximum count 0x0000 RW 0xF444 WATCHDOG_PRESCALE Watchdog prescale 0x0000 RW 0xF450 BLOCKINT_EN Enable block interrupts 0x0000 RW 0xF451 BLOCKINT_VALUE Value for the block interrupt counter 0x0000 RW 0xF460 PROG_CNTR0 Program counter, Bits[23:16] 0x0000 R 0xF461 PROG_CNTR1 Program counter, Bits[15:0] 0x0000 R 0xF462 PROG_CNTR_CLEAR Program counter clear 0x0000 RW 0xF463 PROG_CNTR_LENGTH0 Program counter length, Bits[23:16] 0x0000 R 0xF464 PROG_CNTR_LENGTH1 Program counter length, Bits[15:0] 0x0000 R 0xF465 PROG_CNTR_MAXLENGTH0 Program counter max length, Bits[23:16] 0x0000 R 0xF466 PROG_CNTR_MAXLENGTH1 Program counter max length, Bits[15:0] 0x0000 R 0xF510 MP0_MODE Multipurpose pin mode (SS_M/MP0) 0x0000 RW 0xF511 MP1_MODE Multipurpose pin mode (MOSI_M/MP1) 0x0000 RW 0xF512 MP2_MODE Multipurpose pin mode (SCL_M/SCLK_M/MP2) 0x0000 RW 0xF513 MP3_MODE Multipurpose pin mode (SDA_M/MISO_M/MP3) 0x0000 RW 0xF514 MP4_MODE Multipurpose pin mode (LRCLK_OUT0/MP4) 0x0000 RW 0xF515 MP5_MODE Multipurpose pin mode (LRCLK_OUT1/MP5) 0x0000 RW 0xF516 MP6_MODE Multipurpose pin mode (MP6) 0x0000 RW 0xF517 MP7_MODE Multipurpose pin mode (MP7) 0x0000 RW 0xF518 MP8_MODE Multipurpose pin mode (LRCLK_OUT2/MP8) 0x0000 RW 0xF519 MP9_MODE Multipurpose pin mode (LRCLK_OUT3/MP9) 0x0000 RW 0xF51A MP10_MODE Multipurpose pin mode (LRCLK_IN0/MP10) 0x0000 RW 0xF51B MP11_MODE Multipurpose pin mode (LRCLK_IN1/MP11) 0x0000 RW 0xF51C MP12_MODE Multipurpose pin mode (LRCLK_IN2/MP12) 0x0000 RW 0xF51D MP13_MODE Multipurpose pin mode (LRCLK_IN3/MP13) 0x0000 RW 0xF520 MP0_WRITE Multipurpose pin write value (SS_M/MP0) 0x0000 RW 0xF521 MP1_WRITE Multipurpose pin write value (MOSI_M/MP1) 0x0000 RW 0xF522 MP2_WRITE Multipurpose pin write value SCL_M/SCLK_M/MP2) 0x0000 RW 0xF523 MP3_WRITE Multipurpose pin write value (SDA_M/MISO_M/MP3) 0x0000 RW 0xF524 MP4_WRITE Multipurpose pin write value (LRCLK_OUT0/MP4) 0x0000 RW 0xF525 MP5_WRITE Multipurpose pin write value (LRCLK_OUT1/MP5) 0x0000 RW 0xF526 MP6_WRITE Multipurpose pin write value (MP6) 0x0000 RW 0xF527 MP7_WRITE Multipurpose pin write value (MP7) 0x0000 RW 0xF528 MP8_WRITE Multipurpose pin write value (LRCLK_OUT2/MP8) 0x0000 RW 0xF529 MP9_WRITE Multipurpose pin write value (LRCLK_OUT3/MP9) 0x0000 RW 0xF52A MP10_WRITE Multipurpose pin write value (LRCLK_IN0/MP10) 0x0000 RW 0xF52B MP11_WRITE Multipurpose pin write value (LRCLK_IN1/MP11) 0x0000 RW 0xF52C MP12_WRITE Multipurpose pin write value (LRCLK_IN2/MP12) 0x0000 RW 0xF52D MP13_WRITE Multipurpose pin write value (LRCLK_IN3/MP13) 0x0000 RW 0xF530 MP0_READ Multipurpose pin read value (SS_M/MP0) 0x0000 R 0xF531 MP1_READ Multipurpose pin read value (MOSI_M/MP1) 0x0000 R 0xF532 MP2_READ Multipurpose pin read value (SCL_M/SCLK_M/MP2) 0x0000 R 0xF533 MP3_READ Multipurpose pin read value (SDA_M/MISO_M/MP3) 0x0000 R 0xF534 MP4_READ Multipurpose pin read value (LRCLK_OUT0/MP4) 0x0000 R 0xF535 MP5_READ Multipurpose pin read value (LRCLK_OUT1/MP5) 0x0000 R 0xF536 MP6_READ Multipurpose pin read value (MP6) 0x0000 R 0xF537 MP7_READ Multipurpose pin read value (MP7) 0x0000 R Rev. D | Page 101 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Address Register Name Description Reset RW 0xF538 MP8_READ Multipurpose pin read value (LRCLK_OUT2/MP8) 0x0000 R 0xF539 MP9_READ Multipurpose pin read value (LRCLK_OUT3/MP9) 0x0000 R 0xF53A MP10_READ Multipurpose pin read value (LRCLK_IN0/MP10) 0x0000 R 0xF53B MP11_READ Multipurpose pin read value (LRCLK_IN1/MP11) 0x0000 R 0xF53C MP12_READ Multipurpose pin read value (LRCLK_IN2/MP12) 0x0000 R 0xF53D MP13_READ Multipurpose pin read value (LRCLK_IN3/MP13) 0x0000 R 0xF560 DMIC_CTRL0 Digital PDM microphone control (Channel 0 and Channel 1) 0x4000 RW 0xF561 DMIC_CTRL1 Digital PDM microphone control (Channel 2 and Channel 3) 0x4000 RW 0xF580 ASRC_LOCK ASRC lock status 0x0000 R 0xF581 ASRC_MUTE ASRC mute 0x0000 RW 0xF582 ASRC0_RATIO ASRC ratio (ASRC 0, Channel 0 and Channel 1) 0x0000 R 0xF583 ASRC1_RATIO ASRC ratio (ASRC 1, Channel 2 and Channel 3) 0x0000 R 0xF584 ASRC2_RATIO ASRC ratio (ASRC 2, Channel 4 and Channel 5) 0x0000 R 0xF585 ASRC3_RATIO ASRC ratio (ASRC 3, Channel 6 and Channel 7) 0x0000 R 0xF586 ASRC4_RATIO ASRC ratio (ASRC 4, Channel 8 and Channel 9) 0x0000 R 0xF587 ASRC5_RATIO ASRC ratio (ASRC 5, Channel 10 and Channel 11) 0x0000 R 0xF588 ASRC6_RATIO ASRC ratio (ASRC 6, Channel 12 and Channel 13) 0x0000 R 0xF589 ASRC7_RATIO ASRC ratio (ASRC 7, Channel 14 and Channel 15) 0x0000 R 0xF5A0 ADC_READ0 Auxiliary ADC read value (AUXADC0) 0x0000 R 0xF5A1 ADC_READ1 Auxiliary ADC read value (AUXADC1) 0x0000 R 0xF5A2 ADC_READ2 Auxiliary ADC read value (AUXADC2) 0x0000 R 0xF5A3 ADC_READ3 Auxiliary ADC read value (AUXADC3) 0x0000 R 0xF5A4 ADC_READ4 Auxiliary ADC read value (AUXADC4) 0x0000 R 0xF5A5 ADC_READ5 Auxiliary ADC read value (AUXADC5) 0x0000 R 0xF600 SPDIF_LOCK_DET S/PDIF receiver lock bit detection 0x0000 R 0xF601 SPDIF_RX_CTRL S/PDIF receiver control 0x0000 RW 0xF602 SPDIF_RX_DECODE Decoded signals from the S/PDIF receiver 0x0000 R 0xF603 SPDIF_RX_COMPRMODE Compression mode from the S/PDIF receiver 0x0000 R 0xF604 SPDIF_RESTART Automatically resume S/PDIF receiver audio input 0x0000 RW 0xF605 SPDIF_LOSS_OF_LOCK S/PDIF receiver loss of lock detection 0x0000 R 0xF608 SPDIF_AUX_EN S/PDIF receiver auxiliary outputs enable 0x0000 RW 0xF60F SPDIF_RX_AUXBIT_READY S/PDIF receiver auxiliary bits ready flag 0x0000 R 0xF610 SPDIF_RX_CS_LEFT_0 S/PDIF receiver channel status bits (left) 0x0000 R 0xF611 SPDIF_RX_CS_LEFT_1 S/PDIF receiver channel status bits (left) 0x0000 R 0xF612 SPDIF_RX_CS_LEFT_2 S/PDIF receiver channel status bits (left) 0x0000 R 0xF613 SPDIF_RX_CS_LEFT_3 S/PDIF receiver channel status bits (left) 0x0000 R 0xF614 SPDIF_RX_CS_LEFT_4 S/PDIF receiver channel status bits (left) 0x0000 R 0xF615 SPDIF_RX_CS_LEFT_5 S/PDIF receiver channel status bits (left) 0x0000 R 0xF616 SPDIF_RX_CS_LEFT_6 S/PDIF receiver channel status bits (left) 0x0000 R 0xF617 SPDIF_RX_CS_LEFT_7 S/PDIF receiver channel status bits (left) 0x0000 R 0xF618 SPDIF_RX_CS_LEFT_8 S/PDIF receiver channel status bits (left) 0x0000 R 0xF619 SPDIF_RX_CS_LEFT_9 S/PDIF receiver channel status bits (left) 0x0000 R 0xF61A SPDIF_RX_CS_LEFT_10 S/PDIF receiver channel status bits (left) 0x0000 R 0xF61B SPDIF_RX_CS_LEFT_11 S/PDIF receiver channel status bits (left) 0x0000 R 0xF620 SPDIF_RX_CS_RIGHT_0 S/PDIF receiver channel status bits (right) 0x0000 R 0xF621 SPDIF_RX_CS_RIGHT_1 S/PDIF receiver channel status bits (right) 0x0000 R 0xF622 SPDIF_RX_CS_RIGHT_2 S/PDIF receiver channel status bits (right) 0x0000 R 0xF623 SPDIF_RX_CS_RIGHT_3 S/PDIF receiver channel status bits (right) 0x0000 R 0xF624 SPDIF_RX_CS_RIGHT_4 S/PDIF receiver channel status bits (right) 0x0000 R 0xF625 SPDIF_RX_CS_RIGHT_5 S/PDIF receiver channel status bits (right) 0x0000 R 0xF626 SPDIF_RX_CS_RIGHT_6 S/PDIF receiver channel status bits (right) 0x0000 R 0xF627 SPDIF_RX_CS_RIGHT_7 S/PDIF receiver channel status bits (right) 0x0000 R 0xF628 SPDIF_RX_CS_RIGHT_8 S/PDIF receiver channel status bits (right) 0x0000 R 0xF629 SPDIF_RX_CS_RIGHT_9 S/PDIF receiver channel status bits (right) 0x0000 R Rev. D | Page 102 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Address Register Name Description Reset RW 0xF62A SPDIF_RX_CS_RIGHT_10 S/PDIF receiver channel status bits (right) 0x0000 R 0xF62B SPDIF_RX_CS_RIGHT_11 S/PDIF receiver channel status bits (right) 0x0000 R 0xF630 SPDIF_RX_UD_LEFT_0 S/PDIF receiver user data bits (left) 0x0000 R 0xF631 SPDIF_RX_UD_LEFT_1 S/PDIF receiver user data bits (left) 0x0000 R 0xF632 SPDIF_RX_UD_LEFT_2 S/PDIF receiver user data bits (left) 0x0000 R 0xF633 SPDIF_RX_UD_LEFT_3 S/PDIF receiver user data bits (left) 0x0000 R 0xF634 SPDIF_RX_UD_LEFT_4 S/PDIF receiver user data bits (left) 0x0000 R 0xF635 SPDIF_RX_UD_LEFT_5 S/PDIF receiver user data bits (left) 0x0000 R 0xF636 SPDIF_RX_UD_LEFT_6 S/PDIF receiver user data bits (left) 0x0000 R 0xF637 SPDIF_RX_UD_LEFT_7 S/PDIF receiver user data bits (left) 0x0000 R 0xF638 SPDIF_RX_UD_LEFT_8 S/PDIF receiver user data bits (left) 0x0000 R 0xF639 SPDIF_RX_UD_LEFT_9 S/PDIF receiver user data bits (left) 0x0000 R 0xF63A SPDIF_RX_UD_LEFT_10 S/PDIF receiver user data bits (left) 0x0000 R 0xF63B SPDIF_RX_UD_LEFT_11 S/PDIF receiver user data bits (left) 0x0000 R 0xF640 SPDIF_RX_UD_RIGHT_0 S/PDIF receiver user data bits (right) 0x0000 R 0xF641 SPDIF_RX_UD_RIGHT_1 S/PDIF receiver user data bits (right) 0x0000 R 0xF642 SPDIF_RX_UD_RIGHT_2 S/PDIF receiver user data bits (right) 0x0000 R 0xF643 SPDIF_RX_UD_RIGHT_3 S/PDIF receiver user data bits (right) 0x0000 R 0xF644 SPDIF_RX_UD_RIGHT_4 S/PDIF receiver user data bits (right) 0x0000 R 0xF645 SPDIF_RX_UD_RIGHT_5 S/PDIF receiver user data bits (right) 0x0000 R 0xF646 SPDIF_RX_UD_RIGHT_6 S/PDIF receiver user data bits (right) 0x0000 R 0xF647 SPDIF_RX_UD_RIGHT_7 S/PDIF receiver user data bits (right) 0x0000 R 0xF648 SPDIF_RX_UD_RIGHT_8 S/PDIF receiver user data bits (right) 0x0000 R 0xF649 SPDIF_RX_UD_RIGHT_9 S/PDIF receiver user data bits (right) 0x0000 R 0xF64A SPDIF_RX_UD_RIGHT_10 S/PDIF receiver user data bits (right) 0x0000 R 0xF64B SPDIF_RX_UD_RIGHT_11 S/PDIF receiver user data bits (right) 0x0000 R 0xF650 SPDIF_RX_VB_LEFT_0 S/PDIF receiver validity bits (left) 0x0000 R 0xF651 SPDIF_RX_VB_LEFT_1 S/PDIF receiver validity bits (left) 0x0000 R 0xF652 SPDIF_RX_VB_LEFT_2 S/PDIF receiver validity bits (left) 0x0000 R 0xF653 SPDIF_RX_VB_LEFT_3 S/PDIF receiver validity bits (left) 0x0000 R 0xF654 SPDIF_RX_VB_LEFT_4 S/PDIF receiver validity bits (left) 0x0000 R 0xF655 SPDIF_RX_VB_LEFT_5 S/PDIF receiver validity bits (left) 0x0000 R 0xF656 SPDIF_RX_VB_LEFT_6 S/PDIF receiver validity bits (left) 0x0000 R 0xF657 SPDIF_RX_VB_LEFT_7 S/PDIF receiver validity bits (left) 0x0000 R 0xF658 SPDIF_RX_VB_LEFT_8 S/PDIF receiver validity bits (left) 0x0000 R 0xF659 SPDIF_RX_VB_LEFT_9 S/PDIF receiver validity bits (left) 0x0000 R 0xF65A SPDIF_RX_VB_LEFT_10 S/PDIF receiver validity bits (left) 0x0000 R 0xF65B SPDIF_RX_VB_LEFT_11 S/PDIF receiver validity bits (left) 0x0000 R 0xF660 SPDIF_RX_VB_RIGHT_0 S/PDIF receiver validity bits (right) 0x0000 R 0xF661 SPDIF_RX_VB_RIGHT_1 S/PDIF receiver validity bits (right) 0x0000 R 0xF662 SPDIF_RX_VB_RIGHT_2 S/PDIF receiver validity bits (right) 0x0000 R 0xF663 SPDIF_RX_VB_RIGHT_3 S/PDIF receiver validity bits (right) 0x0000 R 0xF664 SPDIF_RX_VB_RIGHT_4 S/PDIF receiver validity bits (right) 0x0000 R 0xF665 SPDIF_RX_VB_RIGHT_5 S/PDIF receiver validity bits (right) 0x0000 R 0xF666 SPDIF_RX_VB_RIGHT_6 S/PDIF receiver validity bits (right) 0x0000 R 0xF667 SPDIF_RX_VB_RIGHT_7 S/PDIF receiver validity bits (right) 0x0000 R 0xF668 SPDIF_RX_VB_RIGHT_8 S/PDIF receiver validity bits (right) 0x0000 R 0xF669 SPDIF_RX_VB_RIGHT_9 S/PDIF receiver validity bits (right) 0x0000 R 0xF66A SPDIF_RX_VB_RIGHT_10 S/PDIF receiver validity bits (right) 0x0000 R 0xF66B SPDIF_RX_VB_RIGHT_11 S/PDIF receiver validity bits (right) 0x0000 R 0xF670 SPDIF_RX_PB_LEFT_0 S/PDIF receiver parity bits (left) 0x0000 R 0xF671 SPDIF_RX_PB_LEFT_1 S/PDIF receiver parity bits (left) 0x0000 R 0xF672 SPDIF_RX_PB_LEFT_2 S/PDIF receiver parity bits (left) 0x0000 R 0xF673 SPDIF_RX_PB_LEFT_3 S/PDIF receiver parity bits (left) 0x0000 R Rev. D | Page 103 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Address Register Name Description Reset RW 0xF674 SPDIF_RX_PB_LEFT_4 S/PDIF receiver parity bits (left) 0x0000 R 0xF675 SPDIF_RX_PB_LEFT_5 S/PDIF receiver parity bits (left) 0x0000 R 0xF676 SPDIF_RX_PB_LEFT_6 S/PDIF receiver parity bits (left) 0x0000 R 0xF677 SPDIF_RX_PB_LEFT_7 S/PDIF receiver parity bits (left) 0x0000 R 0xF678 SPDIF_RX_PB_LEFT_8 S/PDIF receiver parity bits (left) 0x0000 R 0xF679 SPDIF_RX_PB_LEFT_9 S/PDIF receiver parity bits (left) 0x0000 R 0xF67A SPDIF_RX_PB_LEFT_10 S/PDIF receiver parity bits (left) 0x0000 R 0xF67B SPDIF_RX_PB_LEFT_11 S/PDIF receiver parity bits (left) 0x0000 R 0xF680 SPDIF_RX_PB_RIGHT_0 S/PDIF receiver parity bits (right) 0x0000 R 0xF681 SPDIF_RX_PB_RIGHT_1 S/PDIF receiver parity bits (right) 0x0000 R 0xF682 SPDIF_RX_PB_RIGHT_2 S/PDIF receiver parity bits (right) 0x0000 R 0xF683 SPDIF_RX_PB_RIGHT_3 S/PDIF receiver parity bits (right) 0x0000 R 0xF684 SPDIF_RX_PB_RIGHT_4 S/PDIF receiver parity bits (right) 0x0000 R 0xF685 SPDIF_RX_PB_RIGHT_5 S/PDIF receiver parity bits (right) 0x0000 R 0xF686 SPDIF_RX_PB_RIGHT_6 S/PDIF receiver parity bits (right) 0x0000 R 0xF687 SPDIF_RX_PB_RIGHT_7 S/PDIF receiver parity bits (right) 0x0000 R 0xF688 SPDIF_RX_PB_RIGHT_8 S/PDIF receiver parity bits (right) 0x0000 R 0xF689 SPDIF_RX_PB_RIGHT_9 S/PDIF receiver parity bits (right) 0x0000 R 0xF68A SPDIF_RX_PB_RIGHT_10 S/PDIF receiver parity bits (right) 0x0000 R 0xF68B SPDIF_RX_PB_RIGHT_11 S/PDIF receiver parity bits (right) 0x0000 R 0xF690 SPDIF_TX_EN S/PDIF transmitter enable 0x0000 RW 0xF691 SPDIF_TX_CTRL S/PDIF transmitter control 0x0000 RW 0xF69F SPDIF_TX_AUXBIT_SOURCE S/PDIF transmitter auxiliary bits source select 0x0000 RW 0xF6A0 SPDIF_TX_CS_LEFT_0 S/PDIF transmitter channel status bits (left) 0x0000 RW 0xF6A1 SPDIF_TX_CS_LEFT_1 S/PDIF transmitter channel status bits (left) 0x0000 RW 0xF6A2 SPDIF_TX_CS_LEFT_2 S/PDIF transmitter channel status bits (left) 0x0000 RW 0xF6A3 SPDIF_TX_CS_LEFT_3 S/PDIF transmitter channel status bits (left) 0x0000 RW 0xF6A4 SPDIF_TX_CS_LEFT_4 S/PDIF transmitter channel status bits (left) 0x0000 RW 0xF6A5 SPDIF_TX_CS_LEFT_5 S/PDIF transmitter channel status bits (left) 0x0000 RW 0xF6A6 SPDIF_TX_CS_LEFT_6 S/PDIF transmitter channel status bits (left) 0x0000 RW 0xF6A7 SPDIF_TX_CS_LEFT_7 S/PDIF transmitter channel status bits (left) 0x0000 RW 0xF6A8 SPDIF_TX_CS_LEFT_8 S/PDIF transmitter channel status bits (left) 0x0000 RW 0xF6A9 SPDIF_TX_CS_LEFT_9 S/PDIF transmitter channel status bits (left) 0x0000 RW 0xF6AA SPDIF_TX_CS_LEFT_10 S/PDIF transmitter channel status bits (left) 0x0000 RW 0xF6AB SPDIF_TX_CS_LEFT_11 S/PDIF transmitter channel status bits (left) 0x0000 RW 0xF6B0 SPDIF_TX_CS_RIGHT_0 S/PDIF transmitter channel status bits (right) 0x0000 RW 0xF6B1 SPDIF_TX_CS_RIGHT_1 S/PDIF transmitter channel status bits (right) 0x0000 RW 0xF6B2 SPDIF_TX_CS_RIGHT_2 S/PDIF transmitter channel status bits (right) 0x0000 RW 0xF6B3 SPDIF_TX_CS_RIGHT_3 S/PDIF transmitter channel status bits (right) 0x0000 RW 0xF6B4 SPDIF_TX_CS_RIGHT_4 S/PDIF transmitter channel status bits (right) 0x0000 RW 0xF6B5 SPDIF_TX_CS_RIGHT_5 S/PDIF transmitter channel status bits (right)) 0x0000 RW 0xF6B6 SPDIF_TX_CS_RIGHT_6 S/PDIF transmitter channel status bits (right)) 0x0000 RW 0xF6B7 SPDIF_TX_CS_RIGHT_7 S/PDIF transmitter channel status bits (right) 0x0000 RW 0xF6B8 SPDIF_TX_CS_RIGHT_8 S/PDIF transmitter channel status bits (right) 0x0000 RW 0xF6B9 SPDIF_TX_CS_RIGHT_9 S/PDIF transmitter channel status bits (right) 0x0000 RW 0xF6BA SPDIF_TX_CS_RIGHT_10 S/PDIF transmitter channel status bits (right) 0x0000 RW 0xF6BB SPDIF_TX_CS_RIGHT_11 S/PDIF transmitter channel status bits (right) 0x0000 RW 0xF6C0 SPDIF_TX_UD_LEFT_0 S/PDIF transmitter user data bits (left) 0x0000 RW 0xF6C1 SPDIF_TX_UD_LEFT_1 S/PDIF transmitter user data bits (left) 0x0000 RW 0xF6C2 SPDIF_TX_UD_LEFT_2 S/PDIF transmitter user data bits (left) 0x0000 RW 0xF6C3 SPDIF_TX_UD_LEFT_3 S/PDIF transmitter user data bits (left) 0x0000 RW 0xF6C4 SPDIF_TX_UD_LEFT_4 S/PDIF transmitter user data bits (left) 0x0000 RW 0xF6C5 SPDIF_TX_UD_LEFT_5 S/PDIF transmitter user data bits (left) 0x0000 RW 0xF6C6 SPDIF_TX_UD_LEFT_6 S/PDIF transmitter user data bits (left) 0x0000 RW Rev. D | Page 104 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Address Register Name Description Reset RW 0xF6C7 SPDIF_TX_UD_LEFT_7 S/PDIF transmitter user data bits (left) 0x0000 RW 0xF6C8 SPDIF_TX_UD_LEFT_8 S/PDIF transmitter user data bits (left) 0x0000 RW 0xF6C9 SPDIF_TX_UD_LEFT_9 S/PDIF transmitter user data bits (left) 0x0000 RW 0xF6CA SPDIF_TX_UD_LEFT_10 S/PDIF transmitter user data bits (left)) 0x0000 RW 0xF6CB SPDIF_TX_UD_LEFT_11 S/PDIF transmitter user data bits (left) 0x0000 RW 0xF6D0 SPDIF_TX_UD_RIGHT_0 S/PDIF transmitter user data bits (right) 0x0000 RW 0xF6D1 SPDIF_TX_UD_RIGHT_1 S/PDIF transmitter user data bits (right) 0x0000 RW 0xF6D2 SPDIF_TX_UD_RIGHT_2 S/PDIF transmitter user data bits (right) 0x0000 RW 0xF6D3 SPDIF_TX_UD_RIGHT_3 S/PDIF transmitter user data bits (right) 0x0000 RW 0xF6D4 SPDIF_TX_UD_RIGHT_4 S/PDIF transmitter user data bits (right) 0x0000 RW 0xF6D5 SPDIF_TX_UD_RIGHT_5 S/PDIF transmitter user data bits (right) 0x0000 RW 0xF6D6 SPDIF_TX_UD_RIGHT_6 S/PDIF transmitter user data bits (right) 0x0000 RW 0xF6D7 SPDIF_TX_UD_RIGHT_7 S/PDIF transmitter user data bits (right) 0x0000 RW 0xF6D8 SPDIF_TX_UD_RIGHT_8 S/PDIF transmitter user data bits (right) 0x0000 RW 0xF6D9 SPDIF_TX_UD_RIGHT_9 S/PDIF transmitter user data bits (right) 0x0000 RW 0xF6DA SPDIF_TX_UD_RIGHT_10 S/PDIF transmitter user data bits (right) 0x0000 RW 0xF6DB SPDIF_TX_UD_RIGHT_11 S/PDIF transmitter user data bits (right) 0x0000 RW 0xF6E0 SPDIF_TX_VB_LEFT_0 S/PDIF transmitter validity bits (left) 0x0000 RW 0xF6E1 SPDIF_TX_VB_LEFT_1 S/PDIF transmitter validity bits (left) 0x0000 RW 0xF6E2 SPDIF_TX_VB_LEFT_2 S/PDIF transmitter validity bits (left) 0x0000 RW 0xF6E3 SPDIF_TX_VB_LEFT_3 S/PDIF transmitter validity bits (left) 0x0000 RW 0xF6E4 SPDIF_TX_VB_LEFT_4 S/PDIF transmitter validity bits (left) 0x0000 RW 0xF6E5 SPDIF_TX_VB_LEFT_5 S/PDIF transmitter validity bits (left) 0x0000 RW 0xF6E6 SPDIF_TX_VB_LEFT_6 S/PDIF transmitter validity bits (left) 0x0000 RW 0xF6E7 SPDIF_TX_VB_LEFT_7 S/PDIF transmitter validity bits (left) 0x0000 RW 0xF6E8 SPDIF_TX_VB_LEFT_8 S/PDIF transmitter validity bits (left) 0x0000 RW 0xF6E9 SPDIF_TX_VB_LEFT_9 S/PDIF transmitter validity bits (left) 0x0000 RW 0xF6EA SPDIF_TX_VB_LEFT_10 S/PDIF transmitter validity bits (left) 0x0000 RW 0xF6EB SPDIF_TX_VB_LEFT_11 S/PDIF transmitter validity bits (left) 0x0000 RW 0xF6F0 SPDIF_TX_VB_RIGHT_0 S/PDIF transmitter validity bits (right) 0x0000 RW 0xF6F1 SPDIF_TX_VB_RIGHT_1 S/PDIF transmitter validity bits (right) 0x0000 RW 0xF6F2 SPDIF_TX_VB_RIGHT_2 S/PDIF transmitter validity bits (right) 0x0000 RW 0xF6F3 SPDIF_TX_VB_RIGHT_3 S/PDIF transmitter validity bits (right) 0x0000 RW 0xF6F4 SPDIF_TX_VB_RIGHT_4 S/PDIF transmitter validity bits (right) 0x0000 RW 0xF6F5 SPDIF_TX_VB_RIGHT_5 S/PDIF transmitter validity bits (right) 0x0000 RW 0xF6F6 SPDIF_TX_VB_RIGHT_6 S/PDIF transmitter validity bits (right) 0x0000 RW 0xF6F7 SPDIF_TX_VB_RIGHT_7 S/PDIF transmitter validity bits (right) 0x0000 RW 0xF6F8 SPDIF_TX_VB_RIGHT_8 S/PDIF transmitter validity bits (right) 0x0000 RW 0xF6F9 SPDIF_TX_VB_RIGHT_9 S/PDIF transmitter validity bits (right) 0x0000 RW 0xF6FA SPDIF_TX_VB_RIGHT_10 S/PDIF transmitter validity bits (right) 0x0000 RW 0xF6FB SPDIF_TX_VB_RIGHT_11 S/PDIF transmitter validity bits (right) 0x0000 RW 0xF700 SPDIF_TX_PB_LEFT_0 S/PDIF transmitter parity bits (left) 0x0000 RW 0xF701 SPDIF_TX_PB_LEFT_1 S/PDIF transmitter parity bits (left) 0x0000 RW 0xF702 SPDIF_TX_PB_LEFT_2 S/PDIF transmitter parity bits (left) 0x0000 RW 0xF703 SPDIF_TX_PB_LEFT_3 S/PDIF transmitter parity bits (left) 0x0000 RW 0xF704 SPDIF_TX_PB_LEFT_4 S/PDIF transmitter parity bits (left) 0x0000 RW 0xF705 SPDIF_TX_PB_LEFT_5 S/PDIF transmitter parity bits (left) 0x0000 RW 0xF706 SPDIF_TX_PB_LEFT_6 S/PDIF transmitter parity bits (left) 0x0000 RW 0xF707 SPDIF_TX_PB_LEFT_7 S/PDIF transmitter parity bits (left) 0x0000 RW 0xF708 SPDIF_TX_PB_LEFT_8 S/PDIF transmitter parity bits (left) 0x0000 RW 0xF709 SPDIF_TX_PB_LEFT_9 S/PDIF transmitter parity bits (left) 0x0000 RW 0xF70A SPDIF_TX_PB_LEFT_10 S/PDIF transmitter parity bits (left) 0x0000 RW 0xF70B SPDIF_TX_PB_LEFT_11 S/PDIF transmitter parity bits (left) 0x0000 RW 0xF710 SPDIF_TX_PB_RIGHT_0 S/PDIF transmitter parity bits (right) 0x0000 RW Rev. D | Page 105 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Address Register Name Description Reset RW 0xF711 SPDIF_TX_PB_RIGHT_1 S/PDIF transmitter parity bits (right) 0x0000 RW 0xF712 SPDIF_TX_PB_RIGHT_2 S/PDIF transmitter parity bits (right) 0x0000 RW 0xF713 SPDIF_TX_PB_RIGHT_3 S/PDIF transmitter parity bits (right) 0x0000 RW 0xF714 SPDIF_TX_PB_RIGHT_4 S/PDIF transmitter parity bits (right) 0x0000 RW 0xF715 SPDIF_TX_PB_RIGHT_5 S/PDIF transmitter parity bits (right) 0x0000 RW 0xF716 SPDIF_TX_PB_RIGHT_6 S/PDIF transmitter parity bits (right) 0x0000 RW 0xF717 SPDIF_TX_PB_RIGHT_7 S/PDIF transmitter parity bits (right) 0x0000 RW 0xF718 SPDIF_TX_PB_RIGHT_8 S/PDIF transmitter parity bits (right) 0x0000 RW 0xF719 SPDIF_TX_PB_RIGHT_9 S/PDIF transmitter parity bits (right) 0x0000 RW 0xF71A SPDIF_TX_PB_RIGHT_10 S/PDIF transmitter parity bits (right) 0x0000 RW 0xF71B SPDIF_TX_PB_RIGHT_11 S/PDIF transmitter parity bits (right) 0x0000 RW 0xF780 BCLK_IN0_PIN BCLK input pins drive strength and slew rate (BCLK_IN0) 0x0018 RW 0xF781 BCLK_IN1_PIN BCLK input pins drive strength and slew rate (BCLK_IN1) 0x0018 RW 0xF782 BCLK_IN2_PIN BCLK input pins drive strength and slew rate (BCLK_IN2) 0x0018 RW 0xF783 BCLK_IN3_PIN BCLK input pins drive strength and slew rate (BCLK_IN3) 0x0018 RW 0xF784 BCLK_OUT0_PIN BCLK output pins drive strength and slew rate (BCLK_OUT0) 0x0018 RW 0xF785 BCLK_OUT1_PIN BCLK output pins drive strength and slew rate (BCLK_OUT1) 0x0018 RW 0xF786 BCLK_OUT2_PIN BCLK output pins drive strength and slew rate (BCLK_OUT2) 0x0018 RW 0xF787 BCLK_OUT3_PIN BCLK output pins drive strength and slew rate (BCLK_OUT3) 0x0018 RW 0xF788 LRCLK_IN0_PIN LRCLK input pins drive strength and slew rate (LRCLK_IN0) 0x0018 RW 0xF789 LRCLK_IN1_PIN LRCLK input pins drive strength and slew rate (LRCLK_IN1) 0x0018 RW 0xF78A LRCLK_IN2_PIN LRCLK input pins drive strength and slew rate LRCLK_IN2) 0x0018 RW 0xF78B LRCLK_IN3_PIN LRCLK input pins drive strength and slew rate (LRCLK_IN3) 0x0018 RW 0xF78C LRCLK_OUT0_PIN LRCLK output pins drive strength and slew rate (LRCLK_OUT0) 0x0018 RW 0xF78D LRCLK_OUT1_PIN LRCLK output pins drive strength and slew rate (LRCLK_OUT1) 0x0018 RW 0xF78E LRCLK_OUT2_PIN LRCLK output pins drive strength and slew rate (LRCLK_OUT2) 0x0018 RW 0xF78F LRCLK_OUT3_PIN LRCLK output pins drive strength and slew rate (LRCLK_OUT3) 0x0018 RW 0xF790 SDATA_IN0_PIN SDATA input pins drive strength and slew rate (SDATA_IN0) 0x0018 RW 0xF791 SDATA_IN1_PIN SDATA input pins drive strength and slew rate (SDATA_IN1) 0x0018 RW 0xF792 SDATA_IN2_PIN SDATA input pins drive strength and slew rate (SDATA_IN2) 0x0018 RW 0xF793 SDATA_IN3_PIN SDATA input pins drive strength and slew rate (SDATA_IN3) 0x0018 RW 0xF794 SDATA_OUT0_PIN SDATA output pins drive strength and slew rate (SDATA_OUT0) 0x0008 RW 0xF795 SDATA_OUT1_PIN SDATA output pins drive strength and slew rate (SDATA_OUT1) 0x0008 RW 0xF796 SDATA_OUT2_PIN SDATA output pins drive strength and slew rate (SDATA_OUT2) 0x0008 RW 0xF797 SDATA_OUT3_PIN SDATA output pins drive strength and slew rate (SDATA_OUT3) 0x0008 RW 0xF798 SPDIF_TX_PIN S/PDIF transmitter pin drive strength and slew rate 0x0008 RW 0xF799 SCLK_SCL_PIN SCLK/SCL pin drive strength and slew rate 0x0008 RW 0xF79A MISO_SDA_PIN MISO/SDA pin drive strength and slew rate 0x0008 RW 0xF79B SS_PIN SS/ADDR0 pin drive strength and slew rate 0x0018 RW 0xF79C MOSI_ADDR1_PIN MOSI/ADDR1 pin drive strength and slew rate 0x0018 RW 0xF79D SCLK_SCL_M_PIN SCL_M/SCLK_M/MP2 pin drive strength and slew rate 0x0008 RW 0xF79E MISO_SDA_M_PIN SDA_M/MISO_M/MP3 pin drive strength and slew rate 0x0008 RW 0xF79F SS_M_PIN SS_M/MP0 pin drive strength and slew rate 0x0018 RW 0xF7A0 MOSI_M_PIN MOSI_M/MP1 pin drive strength and slew rate 0x0018 RW 0xF7A1 MP6_PIN MP6 pin drive strength and slew rate 0x0018 RW 0xF7A2 MP7_PIN MP7 pin drive strength and slew rate 0x0018 RW 0xF7A3 CLKOUT_PIN CLKOUT pin drive strength and slew rate 0x0008 RW 0xF890 SOFT_RESET Soft reset 0x0001 RW Rev. D | Page 106 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 CONTROL REGISTER DETAILS This section describes the settings of the control registers. PLL CONFIGURATION REGISTERS PLL Feedback Divider Register Address: 0xF000, Reset: 0x0060, Name: PLL_CTRL0 This register is the value of the feedback divider in the PLL. This value effectively multiplies the frequency of the input clock to the PLL, creating the output system clock, which clocks the DSP core and other digital circuit blocks. The format of the value stored in this register is binary integer in 7.0 format. For example, the default feedback divider value of 96 is stored as 0x60. The value written to this register does not take effect until Register 0xF003 (PLL_ENABLE), Bit 0 (PLL_ENABLE) changes state from 0b0 to 0b1. Table 69. Bit Descriptions for PLL_CTRL0 Bits Bit Name Settings1 Description Reset Access [15:7] RESERVED N/A Reserved. 0x0 RW [6:0] PLL_FBDIVIDER N/A PLL feedback divider. This is the value of the feedback divider in the PLL, which 0x60 RW effectively multiplies the frequency of the input clock to the PLL, creating the output system clock, which clocks the DSP core and other digital circuit blocks. The format of the value stored in this register is binary integer in 7.0 format. For example, the default feedback divider value of 96 is stored as 0x60. 1 N/A means not applicable. PLL Prescale Divider Register Address: 0xF001, Reset: 0x0000, Name: PLL_CTRL1 This register sets the input prescale divider for the PLL. The value written to this register does not take effect until Register 0xF003 (PLL_ENABLE), Bit 0 (PLL_ENABLE) changes state from 0b0 to 0b1. Table 70. Bit Descriptions for PLL_CTRL1 Bits Bit Name Settings1 Description Reset Access [15:2] RESERVED N/A Reserved 0x0 RW [1:0] PLL_DIV PLL input clock divider. This prescale clock divider creates the PLL input 0x0 RW clock from the externally input master clock. The nominal frequency of the PLL input is 3.072 MHz. Therefore, if the input master clock frequency is 3.072 MHz, set the prescale clock divider to divide by 1. If the input clock is 12.288 MHz, set the prescale clock divider to divide by 4. The goal is to make the input to the PLL as close to 3.072 MHz as possible. 00 Divide by 1. 01 Divide by 2. 10 Divide by 4. 11 Divide by 8. 1 N/A means not applicable. Rev. D | Page 107 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet PLL Clock Source Register Address: 0xF002, Reset: 0x0000, Name: PLL_CLK_SRC This register selects the source of the clock used for input to the core and the clock generators. The clock can either be taken directly from the signal on the XTALIN/MCLK pin or from the output of the PLL. In almost every case, use the PLL clock. The value written to this register does not take effect until Register 0xF003 (PLL_ENABLE), Bit 0 (PLL_ENABLE) changes state from 0b0 to 0b1. Table 71. Bit Descriptions for PLL_CLK_SRC Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved 0x0 RW 0 CLKSRC Clock source select. The PLL output is nominally 294.912 MHz, which is the 0x0 RW nominal operating frequency of the core and the clock generator inputs. In most use cases, do not use the direct XTALIN/MCLK input option because the range of allowable frequencies on the XTALIN/MCLK pin is has an upper limit that is significantly lower in frequency than the nominal system clock frequency. 0 Direct from XTALIN/MCLK pin. 1 PLL clock. 1 N/A means not applicable. PLL Enable Register Address: 0xF003, Reset: 0x0000, Name: PLL_ENABLE This register enables or disables the PLL. The PLL does not attempt to lock to an incoming clock until Bit 0 (PLL_ENABLE) is enabled. When Bit 0 (PLL_ENABLE) is set to 0b0, the PLL does not output a clock signal, causing all other clock circuits in the device that rely on the PLL to become idle. When Bit 0 (PLL_ENABLE) transitions from 0b0 to 0b1, the settings in Register 0xF000 (PLL_CTRL0), Register 0xF001 (PLL_CTRL1), Register 0xF002 (PLL_CLK_SRC), and Register 0xF005 (MCLK_OUT) are activated. Table 72. Bit Descriptions for PLL_ENABLE Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 PLL_ENABLE PLL enable. Load the values of Register 0xF000, Register 0xF001, 0x0 RW Register 0xF002, and Register 0xF005 when this bit transitions from 0b0 to 0b1. 0 PLL disabled. 1 PLL enabled. 1 N/A means not applicable. Rev. D | Page 108 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 PLL Lock Register Address: 0xF004, Reset: 0x0000, Name: PLL_LOCK This register contains a flag that represents the lock status of the PLL. The lock status has four prerequisites: a stable input clock is being routed to the PLL, the related PLL registers (Register 0xF000 (PLL_CTRL0), Register 0xF001 (PLL_CTRL1), and Register 0xF002 (PLL_CLK_SRC) are set appropriately, the PLL is enabled (Register 0xF003 (PLL_ENABLE), Bit 0 (PLL_ENABLE) = 0b1), and the PLL has adequate time to adjust its feedback path and provide a stable output clock to the rest of the device. The amount of time required to achieve lock to a new input clock signal varies based on system conditions, which means that Bit 0 (PLL_LOCK) provides a clear indication of when lock has been achieved. Table 73. Bit Descriptions for PLL_LOCK Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 PLL_LOCK PLL lock flag (read only). 0x0 R 0 PLL unlocked. 1 PLL locked. 1 N/A means not applicable. Rev. D | Page 109 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet CLKOUT Control Register Address: 0xF005, Reset: 0x0000, Name: MCLK_OUT This register enables and configures the signal output from the CLKOUT pin. The value written to this register does not take effect until Register 0xF003 (PLL_ENABLE), Bit 0 (PLL_ENABLE), changes state from 0b0 to 0b1. Table 74. Bit Descriptions for MCLK_OUT Bits Bit Name Settings1 Description Reset Access [15:3] RESERVED N/A Reserved 0x0 RW [2:1] CLKOUT_RATE Frequency of CLKOUT. Frequency of the signal output from the CLKOUT pin. These 0x0 RW bits set the frequency of the signal on the CLKOUT pin. The frequencies documented in Table 74 are examples that are valid for a master clock input that is a binary multiple of 3.072 MHz. In this case, the options for output rates are 3.072 MHz, 6.144 MHz, 12.288 MHz, or 24.576 MHz. If the input master clock is scaled down (for example, to a binary multiple of 2.8224 MHz), the possible output rates are 2.8224 MHz, 5.6448 MHz, 11.2896 MHz, or 22.5792 MHz. 00 Predivider output. This is 3.072 MHz for a nominal system clock. 01 Double the predivider output. This is 6.144 MHz for a nominal system clock. 10 4× the predivider output. This is 12.288 MHz for a nominal system clock. 11 8× the predivider output. This is 24.576 MHz for a nominal system clock. 0 CLKOUT_ENABLE CLKOUT enable. When this bit is enabled, a clock signal is output from the 0x0 RW CLKOUT pin of the device. When disabled, the CLKOUT pin is high impedance. 0 CLKOUT pin disabled. 1 CLKOUT pin enabled. 1 N/A means not applicable. Rev. D | Page 110 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Analog PLL Watchdog Control Register Address: 0xF006, Reset: 0x0001, Name: PLL_WATCHDOG The PLL watchdog is a feature that monitors the PLL and automatically resets the PLL in the event that the PLL reaches an unstable condition. The PLL resets itself and automatically attempts to lock to the incoming clock signal again, with the same settings as before the unstable condition occured. This functionality requires no interaction from the user. Ensure that the PLL watchdog is enabled at all times. Table 75. Bit Descriptions for PLL_WATCHDOG Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved 0x0 RW 0 PLL_WATCHDOG PLL watchdog. 0x1 RW 0 PLL watchdog disabled. 1 PLL watchdog enabled. 1 N/A means not applicable. Rev. D | Page 111 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet CLOCK GENERATOR REGISTERS Denominator (M) for Clock Generator 1 Register Address: 0xF020, Reset: 0x0006, Name: CLK_GEN1_M This register holds the denominator (M) for Clock Generator 1. Table 76. Bit Descriptions for CLK_GEN1_M Bits Bit Name Settings1 Description Reset Access [15:9] RESERVED N/A Reserved. 0x0 RW [8:0] CLOCKGEN1_M Clock Generator 1 M (denominator). Format is binary integer. 0x006 RW 1 N/A means not applicable. Numerator (N) for Clock Generator 1 Register Address: 0xF021, Reset: 0x0001, Name: CLK_GEN1_N This register holds the numerator (N) for Clock Generator 1. Table 77. Bit Descriptions for CLK_GEN1_N Bits Bit Name Settings1 Description Reset Access [15:9] RESERVED N/A Reserved. 0x0 RW [8:0] CLOCKGEN1_N Clock Generator 1 N (numerator). Format is binary integer. 0x001 RW 1 N/A means not applicable. Denominator (M) for Clock Generator 2 Register Address: 0xF022, Reset: 0x0009, Name: CLK_GEN2_M This register holds the denominator (M) for Clock Generator 2. Table 78. Bit Descriptions for CLK_GEN2_M Bits Bit Name Settings1 Description Reset Access [15:9] RESERVED Reserved. 0x0 RW [8:0] CLOCKGEN2_M Clock Generator 2 M (denominator). Format is binary integer. 0x009 RW 1 N/A means not applicable. Rev. D | Page 112 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Numerator (N) for Clock Generator 2 Register Address: 0xF023, Reset: 0x0001, Name: CLK_GEN2_N This register holds the numerator (N) for Clock Generator 2. Table 79. Bit Descriptions for CLK_GEN2_N Bits Bit Name Settings1 Description Reset Access [15:9] RESERVED N/A Reserved. 0x0 RW [8:0] CLOCKGEN2_N N/A Clock Generator 2 N (numerator). Format is binary integer. 0x001 RW 1 N/A means not applicable. Denominator (M) for Clock Generator 3 Register Address: 0xF024, Reset: 0x0000, Name: CLK_GEN3_M This register holds the denominator (M) for Clock Generator 3. Table 80. Bit Descriptions for CLK_GEN3_M Bits Bit Name Settings1 Description Reset Access [15:0] CLOCKGEN3_M N/A Clock Generator 3 M (denominator). Format is binary integer. 0x0000 RW 1 N/A means not applicable. Numerator for (N) Clock Generator 3 Register Address: 0xF025, Reset: 0x0000, Name: CLK_GEN3_N This register holds the numerator (N) for Clock Generator 3. Table 81. Bit Descriptions for CLK_GEN3_N Bits Bit Name Settings1 Description Reset Access [15:0] CLOCKGEN3_N N/A Clock Generator 3 N (numerator). Format is binary integer. 0x0000 RW 1 N/A means not applicable. Rev. D | Page 113 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Input Reference for Clock Generator 3 Register Address: 0xF026, Reset: 0x000E, Name: CLK_GEN3_SRC Clock Generator 3 can generate audio clocks using the PLL output (system clock) as a reference, or can optionally use a reference clock entering the device from an external source either on an MPx pin or the S/PDIF receiver. This register determines the source of the reference signal. Table 82. Bit Descriptions for CLK_GEN3_SRC Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 CLK_GEN3_SRC Reference source for Clock Generator 3. This bit selects the reference of Clock 0x0 RW Generator 3. If set to use an external reference clock, Bits[3:0] define the source pin. Otherwise, the PLL output is used as the reference clock. When an external reference clock is used for Clock Generator 3, the resulting base output frequency of Clock Generator 3 is the frequency of the input reference clock multiplied by the Clock Generator 3 numerator, divided by 1024. For example: if Bit 4 (CLK_GEN3_SRC) = 0b1 (an external reference clock is used); Bits[3:0] (FREF_PIN) = 0b1110 (the input signal of the S/PDIF receiver is used as the reference source); the sample rate of the S/PDIF input signal = 48 kHz; and the numerator of Clock Generator 3 = 2048; the resulting base output sample rate of Clock Generator 3 is 48 kHz × 2048/1024 = 96 kHz. 0 Reference signal provided by PLL output; multiply the frequency of this signal by M and divide by N. 1 Reference signal provided by the signal input to the hardware pin defined by Bits[3:0] (FREF_PIN); multiply the frequency of that signal by N, and then divide by 1024 to get the resulting sample rate; M is ignored. [3:0] FREF_PIN Input reference for Clock Generator 3. If Clock Generator 3 is set up to lock to 0xE RW an external reference clock (Bit 4 (CLK_GEN3_SRC) = 0b1), these bits allow the user to specify which pin is receiving the reference clock. The signal input to the corresponding pin is a 50% duty cycle square wave clock representing the reference sample rate. 0000 Input reference source is SS_M/MP0. 0001 Input reference source is MOSI_M/MP1. 0010 Input reference source is SCL_M/SCLK_M/MP2. 0011 Input reference source is SDA_M/MISO_M/MP3. 0100 Input reference source is LRCLK_OUT0/MP4. 0101 Input reference source is LRCLK_OUT1/MP5. 0110 Input reference source is MP6. 0111 Input reference source is MP7. 1000 Input reference source is LRCLK_OUT2/MP8. 1001 Input reference source is LRCLK_OUT3/MP9. 1010 Input reference source is LRCLK_IN0/MP10. 1011 Input reference source is LRCLK_IN1/MP11. 1100 Input reference source is LRCLK_IN2/MP12. 1101 Input reference source is LRCLK_IN3/MP13. 1110 Input reference source is S/PDIF receiver (recovered frame clock). 1 N/A means not applicable. Rev. D | Page 114 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Lock Bit for Clock Generator 3 Input Reference Register Address: 0xF027, Reset: 0x0000, Name: CLK_GEN3_LOCK This register monitors whether or not Clock Generator 3 has locked to its reference clock source, regardless of whether it is coming from the PLL output or from an external reference signal, which is configured in Register 0xF026, Bit 4 (CLK_GEN3_SRC). Table 83. Bit Descriptions for CLK_GEN3_LOCK Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 GEN3_LOCK Lock bit. 0x0 R 0 Not locked. 1 Locked. 1 N/A means not applicable. Rev. D | Page 115 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet POWER REDUCTION REGISTERS Power Enable 0 Register Address: 0xF050, Reset: 0x0000, Name: POWER_ENABLE0 For the purpose of power saving, this register allows the clock generators, ASRCs, and serial ports to be disabled when not in use. When these functional blocks are disabled, the current draw on the corresponding supply pins decreases. Table 84. Bit Descriptions for POWER_ENABLE0 Bits Bit Name Settings1 Description Reset Access [15:13] RESERVED N/A Reserved. 0x0 RW 12 CLK_GEN3_PWR High precision clock generator (Clock Generator 3) power enable. When 0x0 RW this bit is disabled, Clock Generator 3 is disabled and ceases to output audio clocks. Any functional block in hardware, including the DSP core, that has been configured to be clocked by Clock Generator 3 ceases to function when this bit is disabled. 0 Power disabled. 1 Power enabled. 11 CLK_GEN2_PWR Clock Generator 2 power enable. When this bit is disabled, Clock Generator 2 0x0 RW is disabled and ceases to output audio clocks. Any LRCLK_OUTx, LRCLK_INx, or BCLK_OUTx, BCLK_INx pins that are configured to output clocks generated by the Clock Generator 2 output a logic low signal when Clock Generator 2 is disabled. Any functional block in hardware, including the DSP core, that is configured to be clocked by Clock Generator 2 ceases to function when this bit is disabled. 0 Power disabled. 1 Power enabled. Rev. D | Page 116 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Bits Bit Name Settings1 Description Reset Access 10 CLK_GEN1_PWR Clock Generator 1 power enable. When this bit is disabled, Clock Generator 1 0x0 RW is disabled and ceases to output audio clocks. Any LRCLK_OUTx, LRCLK_INx, BCLK_OUTx, or BCLK_INx pins that are configured to output clocks generated by Clock Generator 1 output a logic low signal when Clock Generator 1 is disabled. Any functional block in hardware, including the DSP core, that is configured to be clocked by Clock Generator 1 ceases to function when this bit is disabled. 0 Power disabled. 1 Power enabled. 9 ASRCBANK1_PWR ASRC 4, ASRC 5, ASRC 6, and ASRC 7 power enable. When this bit is disabled, 0x0 RW ASRC Channel 8 to Channel 15 are disabled, and their output data streams cease. 0 Power disabled. 1 Power enabled. 8 ASRCBANK0_PWR ASRC 0, ASRC 1, ASRC 2, and ASRC 3 power enable. When this bit is disabled, 0x0 RW ASRC Channel 0 to Channel 7 are disabled, and their output data streams cease. 0 Power disabled. 1 Power enabled. 7 SOUT3_PWR SDATA_OUT3 power enable. When this bit is disabled, the SDATA_OUT3 0x0 RW pin and associated serial port circuitry are also disabled. LRCLK_OUT3 and BCLK_OUT3 are not affected. 0 Power disabled. 1 Power enabled. 6 SOUT2_PWR SDATA_OUT2 power enable. When this bit is disabled, the SDATA_OUT2 0x0 RW pin and associated serial port circuitry is disabled. LRCLK_OUT2 and BCLK_OUT2 are not affected. 0 Power disabled. 1 Power enabled. 5 SOUT1_PWR SDATA_OUT1 power enable. When this bit is disabled, the SDATA_OUT1 0x0 RW pin and associated serial port circuitry are also disabled. LRCLK_OUT1 and BCLK_OUT1 are not affected. 0 Power disabled. 1 Power enabled. 4 SOUT0_PWR SDATA_OUT0 power enable. When this bit is disabled, the SDATA_OUT0 0x0 RW pin and associated serial port circuitry are disabled. LRCLK_OUT0 and BCLK_OUT0 are not affected. 0 Power disabled. 1 Power enabled. 3 SIN3_PWR SDATA_IN3 power enable. When this bit is disabled, the SDATA_IN3 pin 0x0 RW and associated serial port circuitry are disabled. LRCLK_IN3 and BCLK_IN3 are not affected. 0 Power disabled. 1 Power enabled. 2 SIN2_PWR SDATA_IN2 power enable. When this bit is disabled, the SDATA_IN2 pin 0x0 RW and associated serial port circuitry are disabled. LRCLK_IN2 and BCLK_IN2 are not affected. 0 Power disabled. 1 Power enabled. 1 SIN1_PWR SDATA_IN1 power enable. When this bit is disabled, the SDATA_IN1 pin 0x0 RW and associated serial port circuitry are disabled. The LRCLK_IN1 and BCLK_IN1 pins are not affected. 0 Power disabled. 1 Power enabled. Rev. D | Page 117 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Bits Bit Name Settings1 Description Reset Access 0 SIN0_PWR SDATA_IN0 power enable. When this bit is disabled, the SDATA_IN0 pin 0x0 RW and associated serial port circuitry are disabled. The LRCLK_IN0 and BCLK_IN0 pins are not affected. 0 Power disabled. 1 Power enabled. 1 N/A means not applicable. Power Enable 1 Register Address: 0xF051, Reset: 0x0000, Name: POWER_ENABLE1 For the purpose of power saving, this register allows the PDM microphone interfaces, S/PDIF interfaces, and auxiliary ADCs to be disabled when not in use. When these functional blocks are disabled, the current draw on the corresponding supply pins decreases. Table 85. Bit Descriptions for POWER_ENABLE1 Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 PDM1_PWR PDM Microphone Channel 2 and PDM Microphone Channel 3 power enable. 0x0 RW When this bit is disabled, PDM Microphone Channel 2 and PDM Microphone Channel 3 and their associated circuitry are disabled, and their data values cease to update. 0 Power disabled. 1 Power enabled. 3 PDM0_PWR PDM Microphone Channel 0 and PDM Microphone Channel 1 power enable. 0x0 RW When this bit is disabled, PDM Microphone Channel 0 and PDM Microphone Channel 1 and their associated circuitry are disabled, and their data values cease to update. 0 Power disabled. 1 Power enabled. 2 TX_PWR S/PDIF transmitter power enable. This bit disables the S/PDIF transmitter 0x0 RW circuit. Clock and data ceases to output from the S/PDIF transmitter pin, and the output is held at logic low as long as this bit is disabled. 0 Power disabled. 1 Power enabled. 1 RX_PWR S/PDIF receiver power enable. This bit disables the S/PDIF receiver circuit. 0x0 RW Clock and data recovery from the S/PDIF input stream ceases until this bit is reenabled. 0 Power disabled. 1 Power enabled. 0 ADC_PWR Auxiliary ADC power enable. When this bit is disabled, the auxiliary ADCs are 0x0 RW powered down, their outputs cease to update, and the ADCs hold their last value. 0 Power disabled. 1 Power enabled. 1 N/A means not applicable. Rev. D | Page 118 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 AUDIO SIGNAL ROUTING REGISTERS ASRC Input Selector Register Address: 0xF100 to Address 0xF107 (Increments of 0x1), Reset: 0x0000, Name: ASRC_INPUTx These eight registers configure the input signal to the corresponding eight stereo ASRCs on the ADAU1452 and ADAU1451. ASRC_INPUT0 configures ASRC Channel 0 and ASRC Channel 1, ASRC_INPUT1 configures ASRC Channel 2 and ASRC Channel 3, and so on. Valid input signals to the ASRCs include Serial Input Channel 0 to Serial Input Channel 47, the PDM Microphone Input Channel 0 to PDM Microphone Input Channel 3, and the S/PDIF Receiver Channel 0 to S/PDIF Receiver Channel 1. Table 86. Bit Descriptions for ASRC_INPUTx Bits Bit Name Settings1 Description Reset Access [15:8] RESERVED N/A Reserved 0x0 RW [7:3] ASRC_SIN_CHANNEL If Bits[2:0] (ASRC_SOURCE) = 0b001, these bits select which serial input channel 0x00 RW is routed to the ASRC. 00000 Serial Input Channel 0 and Serial Input Channel 1. 00001 Serial Input Channel 2 and Serial Input Channel 3. 00010 Serial Input Channel 4 and Serial Input Channel 5. 00011 Serial Input Channel 6 and Serial Input Channel 7. 00100 Serial Input Channel 8 and Serial Input Channel 9. 00101 Serial Input Channel 10 and Serial Input Channel 11. 00110 Serial Input Channel 12 and Serial Input Channel 13. 00111 Serial Input Channel 14 and Serial Input Channel 15. 01000 Serial Input Channel 16 and Serial Input Channel 17. 01001 Serial Input Channel 18 and Serial Input Channel 19. 01010 Serial Input Channel 20 and Serial Input Channel 21. 01011 Serial Input Channel 22 and Serial Input Channel 23. 01100 Serial Input Channel 24 and Serial Input Channel 25. 01101 Serial Input Channel 26 and Serial Input Channel 27. 01110 Serial Input Channel 28 and Serial Input Channel 29. 01111 Serial Input Channel 30 and Serial Input Channel 31. 10000 Serial Input Channel 32 and Serial Input Channel 33. 10001 Serial Input Channel 34 and Serial Input Channel 35. 10010 Serial Input Channel 36 and Serial Input Channel 37. 10011 Serial Input Channel 38 and Serial Input Channel 39. 10100 Serial Input Channel 40 and Serial Input Channel 41. 10101 Serial Input Channel 42 and Serial Input Channel 43. 10110 Serial Input Channel 44 and Serial Input Channel 45. 10111 Serial Input Channel 46 and Serial Input Channel 47. Rev. D | Page 119 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Bits Bit Name Settings1 Description Reset Access [2:0] ASRC_SOURCE ASRC source select. 0x0 RW 000 Not used. 001 Select from serial input ports; select channels using Bits[7:3] (ASRC_SIN_CHANNEL). 010 Select from DSP core outputs. 011 Select from S/PDIF receiver. 100 Select from digital PDM Microphone Input Channel 0 and PDM Microphone Input Channel 1. 101 Select from digital PDM Microphone Input Channel 2 and PDM Microphone Input Channel 3. 1 N/A means not applicable. Rev. D | Page 120 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 ASRC Output Rate Selector Register Address: 0xF140 to Address 0xF147 (Increments of 0x1), Reset: 0x0000, Name: ASRC_OUT_RATEx These eight registers configure the target output sample rates of the corresponding eight stereo ASRCs on the ADAU1452 and ADAU1451. The ASRC takes any arbitrary input sample rate and automatically attempts to resample the data in that signal and output the data at the target sample rate as configured by these registers. Each of the eight registers corresponds to one of the eight stereo ASRCs. ASRC_OUT_RATE0 configures ASRC Channel 0 and ASRC Channel 1, ASRC_INPUT1 configures ASRC Channel 2 and ASRC Channel 3, ASRC_OUT_RATE2 configures ASRC Channel 4 and ASRC Channel 5, ASRC_OUT_RATE3 configures ASRC Channel 6 and ASRC Channel 7, ASRC_OUT_ RATE4 configures ASRC Channel 8 and ASRC Channel 9, ASRC_OUT_RATE5 configures ASRC Channel 10 and ASRC Channel 11, ASRC_OUT_RATE6 configures ASRC Channel 12 and ASRC Channel 13, and ASRC_OUT_RATE7 configures ASRC Channel 14 and ASRC Channel 15. The ASRCs lock their output frequencies to the audio sample rates of any of the serial output ports, the DSP start pulse rate of the core, or one of several internally generated sample rates coming from the clock generators. Table 87. Bit Descriptions for ASRC_OUT_RATEx Bits Bit Name Settings1 Description Reset Access [15:4] RESERVED N/A Reserved. 0x0 RW [3:0] ASRC_RATE ASRC target audio output sample rate. The corresponding ASRC can lock its output to a 0x0 RW serial output port, the DSP core, or an internally generated rate. 0000 No output rate selected. 0001 Use sample rate of SDATA_OUT0 (Register 0xF211 (SERIAL_BYTE_4_1), Bits[4:0]). 0010 Use sample rate of SDATA_OUT1 (Register 0xF215 (SERIAL_BYTE_5_1), Bits[4:0]). 0011 Use sample rate of SDATA_OUT2 (Register 0xF219 (SERIAL_BYTE_6_1), Bits[4:0]). 0100 Use sample rate of SDATA_OUT3 (Register 0xF21D (SERIAL_BYTE_7_1), Bits[4:0]). 0101 Use DSP core audio sampling rate (Register 0xF401 (START_PULSE), Bits[4:0]). 0110 Internal rate (the base output rate of Clock Generator 1); see Register 0xF020 (CLK_GEN1_M) and Register 0xF021 (CLK_GEN1_N). 0111 Internal rate × 2 (the doubled output rate of Clock Generator 1); see Register 0xF020 (CLK_GEN1_M) and Register 0xF021 (CLK_GEN1_N). 1000 Internal rate × 4 (the quadrupled output rate of Clock Generator 1); see Register 0xF020 (CLK_GEN1_M) and Register 0xF021 (CLK_GEN1_N). 1001 Internal rate × (1/2) the halved output rate of Clock Generator 1); see Register 0xF020 (CLK_GEN1_M) and Register 0xF021 (CLK_GEN1_N). 1010 Internal rate × (1/3) (halved output of Clock Generator 2); see Register 0xF022 (CLK_GEN2_M) and Register 0xF023 (CLK_GEN2_N). 1011 Internal rate × (1/4) (quartered output of Clock Generator 1); see Register 0xF020 (CLK_GEN1_M) and Register 0xF021 (CLK_GEN1_N). 1100 Internal rate × (1/6) (quartered output of Clock Generator 2); see Register 0xF022 (CLK_GEN2_M) and Register 0xF023 (CLK_GEN2_N). 1 N/A means not applicable. Rev. D | Page 121 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Source of Data for Serial Output Ports Register Address: 0xF180 to 0xF197 (Increments of 0x1), Reset: 0x0000, Name: SOUT_SOURCEx These 24 registers correspond to the 24 pairs of output channels used by the serial output ports. Each register corresponds to two audio channels. SOUT_SOURCE0 corresponds to Channel 0 and Channel 1, SOUT_SOURCE1 corresponds to Channel 2 and Channel 3, and so on. SOUT_SOURCE0 to SOUT_SOURCE7 map to the 16 total channels (Channel 0 to Channel 15) that are fed to SDATA_OUT0. SOUT_SOURCE8 to SOUT_SOURCE15 map to the 16 total channels (Channel 16 to Channel 31) that are fed to SDATA_OUT1. SOUT_SOURCE16 to SOUT_SOURCE19 map to the eight total channels (Channel 32 to Channel 39) that are fed to SDATA_OUT2. SOUT_SOURCE20 to SOUT_SOURCE23 map to the eight total channels (Channel 40 to Channel 47) that are fed to SDATA_OUT3. Data originates from several places, including directly from the corresponding input audio channels from the serial input ports, from the corresponding audio output channels of the DSP core, from an ASRC output pair, or directly from the PDM microphone inputs. Table 88. Bit Descriptions for SOUT_SOURCEx Bits Bit Name Settings1 Description Reset Access [15:6] RESERVED N/A Reserved. 0x000 RW [5:3] SOUT_ASRC_SELECT ASRC output channels. If Bits[2:0] (SOUT_SOURCE) are set to 0b011, these bits 0x0 RW select which ASRC channels are routed to the serial output channels. 000 ASRC 0 (Channel 0 and Channel 1) on the ADAU1452 and ADAU1451. 001 ASRC 1 (Channel 2 and Channel 3) on the ADAU1452 and ADAU1451. 010 ASRC 2 (Channel 4 and Channel 5) on the ADAU1452 and ADAU1451. 011 ASRC 3 (Channel 6 and Channel 7) on the ADAU1452 and ADAU1451. 100 ASRC 4 (Channel 8 and Channel 9) on the ADAU1452 and ADAU1451. 101 ASRC 5 (Channel 10 and Channel 11) on the ADAU1452 and ADAU1451. 110 ASRC 6 (Channel 12 and Channel 13) on the ADAU1452 and ADAU1451. 111 ASRC 7 (Channel 14 and Channel 15) on the ADAU1452 and ADAU1451. [2:0] SOUT_SOURCE Audio data source for these serial audio output channels. If these bits are set to 0x0 RW 0b001, the corresponding output channels output a copy of the data from the corresponding input channels. For example, if Address 0xF180, Bits[2:0] are set to 0b001, Serial Input Channel 0 and Serial Input Channel 1 copy to Serial Out-put Channel 0 and Serial Output Channel 1, respectively. If these bits are set to 0b010, DSP Output Channel 0 and DSP Output Channel 1 copy to Serial Out-put Channel 0 and Serial Output Channel 1, respectively. If these bits are set to 0b011, Bits[5:3] (SOUT_ASRC_SELECT) must be configured to select the desired ASRC output. 000 Disabled; these output channels are not used. 001 Direct copy of data from the corresponding serial input channels. 010 Data from the corresponding DSP core output channels. 011 From ASRC (select channel using Bits[5:3], SOUT_ASRC_SELECT) on the ADAU1452 and the ADAU1451. 100 Digital PDM Microphone Input Channel 0 and Digital PDM Microphone Input Channel 1. 101 Digital PDM Microphone Input Channel 2 and Digital PDM Microphone Input Channel 3. 1 N/A means not applicable. Rev. D | Page 122 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 S/PDIF Transmitter Data Selector Register Address: 0xF1C0, Reset: 0x0000, Name: SPDIFTX_INPUT This register configures which data source feeds the S/PDIF transmitter on the ADAU1452 and ADAU1451. Data can originate from the S/PDIF outputs of the DSP core or directly from the S/PDIF receiver. Table 89. Bit Descriptions for SPDIFTX_INPUT Bits Bit Name Settings1 Description Reset Access [15:2] RESERVED N/A Reserved. 0x0 RW [1:0] SPDIFTX_SOURCE S/PDIF transmitter source. 0x0 RW 00 Disables the S/PDIF transmitter. 01 Data originates from S/PDIF Output Channel 0 and S/PDIF Output Channel 1 of the DSP core, as configured in the DSP program. 10 Data copied directly from S/PDIF Receiver Channel 0 and S/PDIF Receiver Channel 1 to S/PDIF Transmitter Channel 0 and S/PDIF Transmitter Channel 1, respectively. 1 N/A means not applicable. Rev. D | Page 123 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet SERIAL PORT CONFIGURATION REGISTERS Serial Port Control 0 Register Address: 0xF200 to 0xF21C (Increments of 0x4), Reset: 0x0000, Name: SERIAL_BYTE_x_0 These eight registers configure several settings for the corresponding serial input and serial output ports. Channel count, MSB position, data-word length, clock polarity, clock sources, and clock type are configured with these registers. On the input side, Register 0xF200 (SERIAL_BYTE_0_0) corresponds to SDATA_IN0, Register 0xF204 (SERIAL_BYTE_1_0) corresponds to SDATA_IN1, Register 0xF208 (SERIAL_BYTE_2_0) corresponds to SDATA_IN2, and Register 0xF20C (SERIAL_BYTE_3_0) corresponds to SDATA_IN3. On the output side, Register 0xF210 (SERIAL_BYTE_4_0) corresponds to SDATA_OUT0, Register 0xF214 (SERIAL_BYTE_5_0) corresponds to SDATA_OUT1, Register 0xF218 (SERIAL_BYTE_6_0) corresponds to SDATA_OUT2, and Register 0xF21C (SERIAL_BYTE_7_0) corresponds to SDATA_OUT3. Rev. D | Page 124 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Table 90. Bit Descriptions for SERIAL_BYTE_x_0 Bits Bit Name Settings Description Reset Access [15:13] LRCLK_SRC LRCLK pin selection. These bits configure whether the corresponding 0x0 RW serial port is a frame clock master or slave. When configured as a master, the corresponding LRCLK pin (LRCLK_INx for SDATA_IN pins and LRCLK_OUTx for SDATA_OUT pins) with the same number as the serial port (for example, LRCLK_OUT0 for SDATA_OUT0) actively drives out a clock signal. When configured as a slave, the serial port can receive the clock signal from any of the four corresponding LRCLK pins (LRCLK_INx pins for SDATA_INx pins or LRCLK_OUTx pins for SDATA_OUTx pins). 000 Slave from LRCLK_IN0 or LRCLK_OUT0. 001 Slave from LRCLK_IN1 or LRCLK_OUT1. 010 Slave from LRCLK_IN2 or LRCLK_OUT2. 011 Slave from LRCLK_IN3 or LRCLK_OUT3. 100 Master mode; corresponding LRCLK pin actively outputs a clock signal. [12:10] BCLK_SRC BCLK pin selection. These bits configure whether the corresponding serial 0x0 RW port is a bit clock master or slave. When configured as a master, the corresponding BCLK pin (BCLK_INx for SDATA_INx pins and BCLK_OUTx for SDATA_OUTx pins) with the same number as the serial port (for example, BCLK_OUT0 for SDATA_OUT0) actively drives out a clock signal. When configured as a slave, the serial port can receive the clock signal from any of the four corresponding BCLK pins (BCLK_INx pins for SDATA_INx pins or BCLK_OUTx pins for SDATA_OUTx pins). 000 Slave from BCLK_IN0 or BCLK_OUT0. 001 Slave from BCLK_IN1 or BCLK_OUT1. 010 Slave from BCLK_IN2 or BCLK_OUT2. 011 Slave from BCLK_IN3 or BCLK_OUT3. 100 Master mode; corresponding BCLK pin actively outputs a clock signal. 9 LRCLK_MODE LRCLK waveform type. The frame clock can be a 50/50 duty cycle square 0x0 RW wave or a short pulse. 0 50% duty cycle clock (square wave). 1 Pulse with a width equal to one bit clock cycle. 8 LRCLK_POL LRCLK polarity. This bit sets the frame clock polarity on the corresponding 0x0 RW serial port. Negative polarity means that the frame starts on the falling edge of the frame clock, which conforms to the I2S standard audio format. 0 Negative polarity; frame starts on falling edge of frame clock. 1 Positive polarity; frame starts on rising edge of frame clock. 7 BCLK_POL BCLK polarity. This bit sets the bit clock polarity on the corresponding 0x0 RW serial port. Negative polarity means that the data signal transitions on the falling edge of the bit clock, which conforms to the I2S standard audio format. 0 Negative polarity; the data transitions on falling edge of bit clock. 1 Positive polarity; the data transitions on rising edge of bit clock. [6:5] WORD_LEN Audio data-word length. These bits set the word length of the audio data 0x0 RW channels on the corresponding serial port. For serial input ports, if the input data has more words than the length as configured by these bits, the extra data bits are ignored. For output serial ports, if the word length as configured by these bits is shorter than the data length that comes from the data source (the DSP, ASRCs, S/PDIF receiver, PDM inputs, or serial inputs), the extra data bits are truncated and output as 0s. If Bits[6:5] (WORD_LEN) are set to 0b10 for 32-bit mode, the corresponding 32-bit input or output cells are required in SigmaStudio. 00 24 bits. 01 16 bits. 10 32 bits. 11 Flexible TDM mode (configure using Register 0xF300 to Register 0xF33F, FTDM_INx, and Register 0xF380 to Register 0xF3BF, FTDM_OUTx). Rev. D | Page 125 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Bits Bit Name Settings Description Reset Access [4:3] DATA_FMT MSB position. These bits set the positioning of the data in the frame on 0x0 RW the corresponding serial port. 00 I2S (delay data by one BCLK cycle). 01 Left justified (delay data by zero BCLK cycles). 10 Right justified for 24-bit data (delay data by 8 BCLK cycles). 11 Right justified for 16-bit data (delay data by 16 BCLK cycles) [2:0] TDM_MODE Channels per frame and BCLK cycles per channel. These bits set the number 0x0 RW of channels per frame and the number of bit clock cycles per frame on the corresponding serial port. 000 2 channels, 32 bit clock cycles per channel, 64 bit clock cycles per frame. 001 4 channels, 32 bit clock cycles per channel, 128 bit clock cycles per frame. 010 8 channels, 32 bit clock cycles per channel, 256 bit clock cycles per frame. 011 16 channels, 32 bit clock cycles per channel, 512 bit clock cycles per frame. 100 4 channels, 16 bit clock cycles per channel, 64 bit clock cycles per frame. 101 2 channels, 16 bit clock cycles per channel, 32 bit clock cycles per frame. Serial Port Control 1 Register Address: 0xF201 to 0xF21D (Increments of 0x4), Reset: 0x0002, Name: SERIAL_BYTE_x_1 These eight registers configure several settings for the corresponding serial input and serial output ports. Clock generator, sample rate, and behavior during inactive channels are configured with these registers. On the input side, Register 0xF201 (SERIAL_BYTE_0_1) corresponds to SDATA_IN0, Register 0xF205 (SERIAL_BYTE_1_1) corresponds to SDATA_IN1, Register 0xF209 (SERIAL_BYTE_2_1) corresponds to SDATA_IN2, and Register 0xF20D (SERIAL_BYTE_3_1) corresponds to SDATA_IN3. On the output side, Register 0xF211 (SERIAL_BYTE_4_1) corresponds to SDATA_OUT0, Register 0xF215 (SERIAL_BYTE_5_1) corresponds to SDATA_OUT1, Register 0xF219 (SERIAL_BYTE_6_1) corresponds to SDATA_OUT2; and Register 0xF21D (SERIAL_BYTE_7_1) corresponds to SDATA_OUT3. Table 91. Bit Descriptions for SERIAL_BYTE_x_1 Bits Bit Name Settings1 Description Reset Access [15:6] RESERVED N/A Reserved. 0x000 RW 5 TRISTATE Tristate unused output channels. This bit has no effect on serial input ports. 0x0 RW 1 The corresponding serial data output pin is high impedance during unused output channels. 0 Drive every output channel. [4:3] CLK_DOMAIN Selects the clock generator to use for the serial port. These bits select the 0x0 RW clock generator to use for this serial port when it is configured as a clock master. This setting is valid only when Bits[15:13] (LRCLK_SRC) of the corresponding SERIAL_BYTE_x_0 register are set to 0b100 (master mode) and Bits[12:10] (BCLK_SRC) are set to 0b100 (master mode). 00 Clock Generator 1. 01 Clock Generator 2. 10 Clock Generator 3 (high precision clock generator). Rev. D | Page 126 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Bits Bit Name Settings1 Description Reset Access [2:0] FS Sample rate. These bits set the sample rate to use for the serial port when 0x2 RW it is configured as a clock master. This setting is valid only when Bits[15:13] (LRCLK_SRC) of the corresponding SERIAL_BYTE_x_0 register are set to 0b100 (master mode) and Bits[12:10] BCLK_SRC are set to 0b100 (master mode). Bits[4:3] (CLK_DOMAIN) select which clock generator to use, and Bits[2:0] (FS) select which of the five clock generator outputs to use. 000 Quarter rate of selected clock generator. 001 Half rate of selected clock generator. 010 Base rate of selected clock generator. 011 Double rate of selected clock generator. 100 Quadruple rate of selected clock generator. 1 N/A means not applicable. Rev. D | Page 127 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet FLEXIBLE TDM INTERFACE REGISTERS FTDM Mapping for the Serial Inputs Register Address: 0xF300 to 0xF33F (Increments of 0x1), Reset: 0x0000, Name: FTDM_INx These 64 registers correspond to the 64 bytes of data that combine to form the 16 audio channels derived from the data streams being input to the SDATA_IN2 and SDATA_IN3 pins. Table 92. Bit Descriptions for FTDM_INx Bits Bit Name Settings1 Description Reset Access [15:8] RESERVED N/A Reserved. 0x0 RW 7 SLOT_ENABLE_IN Enables the corresponding input byte. This bit determines whether or 0x0 RW not the slot is active. If active, valid data is input from the corresponding data slot on the selected channel of the selected input pin. If disabled, input data from the corresponding data slot on the selected channel of the selected input pin is ignored. 0 Disable byte. 1 Enable byte. 6 REVERSE_IN_BYTE Reverses the order of bits in the byte (big endian or little endian). This bit 0x0 RW changes the endianness of the data bits within the byte by optionally reversing the order of the bits from MSB to LSB. 0 Do not reverse bits (big endian). 1 Reverse bits (little endian). 5 SERIAL_IN_SEL Serial input pin selector (SDATA_IN2 or SDATA_IN3). If this bit = 0b0, the 0x0 RW slot is mapped to Audio Channel 32 to Audio Channel 39. If this bit = 0b1, the slot is mapped to Audio Channel 40 to Audio Channel 47. The exact channel assignment is determined by Bits[4:2] (CHANNEL_IN_POS). 0 Select data from the flexible TDM stream on the SDATA_IN2 pin. 1 Select data from the flexible TDM stream on the SDATA_IN3 pin. [4:2] CHANNEL_IN_POS Source channel selector. These bits map the slot to an audio input 0x0 RW channel. If Bit 5 (SERIAL_IN_SEL) = 0b0, Position 0 maps to Channel 32, Position 1 maps to Channel 33, and so on. If Bit 5 (SERIAL_IN_SEL) = 0b1, Position 0 maps to Channel 40, Position 1 maps to Channel 41, and so on. 000 Channel 0 (in the TDM8 stream). 001 Channel 1 (in the TDM8 stream). Rev. D | Page 128 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Bits Bit Name Settings1 Description Reset Access 010 Channel 2 (in the TDM8 stream). 011 Channel 3 (in the TDM8 stream). 100 Channel 4 (in the TDM8 stream). 101 Channel 5 (in the TDM8 stream). 110 Channel 6 (in the TDM8 stream). 111 Channel 7 (in the TDM8 stream). [1:0] BYTE_IN_POS Byte selector for source channel. These bits determine which byte the 0x0 RW slot fills in the channel selected by Bit 5 (SERIAL_IN_SEL) and Bits[4:2] (CHANNEL_IN_POS). Each channel consists of four bytes that are selectable by the four options available in this bit field. 00 Byte 0; Bits[31:24]. 01 Byte 1; Bits[23:16]. 10 Byte 2; Bits[15:8]. 11 Byte 3; Bits[7:0]. 1 N/A means not applicable. Rev. D | Page 129 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet FTDM Mapping for the Serial Outputs Register Address: 0xF380 to 0xF3BF (Increments of 0x1), Reset: 0x0000, Name: FTDM_OUTx These 64 registers correspond to the 64 data slots for the flexible TDM output modes on the SDATA_OUT2 and SDATA_OUT3 pins. Slot 0 to Slot 31 are available for use on SDATA_OUT2, and Slot 32 to Slot 63 are available for use on SDATA_OUT3. Each slot can potentially hold one byte of data. Slots are mapped to corresponding audio channels in the serial ports by Bits[5:0] in these registers. Table 93. Bit Descriptions for FTDM_OUTx Bits Bit Name Settings1 Description Reset Access [15:8] RESERVED N/A Reserved. 0x0 RW 7 SLOT_ENABLE_OUT Enables the corresponding output byte. This bit determines whether or 0x0 RW not the slot is active. If Bit 7 (SLOT_ENABLE_OUT) = 0b0 and Bit 5 (TRISTATE) of the corresponding serial output port = 0b1, the corresponding output pin is high impedance during the period in which the corresponding flexible TDM slot is output. If Bit 7 (SLOT_ENABLE_OUT) = 0b0, and Bit 5 (TRISTATE) of the corresponding serial output port = 0b0, the corre- sponding output pin drives logic low during the period in which the corresponding flexible TDM slot is output. If Bit 7 (SLOT_ENABLE_OUT) = 0b1, the corresponding serial output pin outputs valid data during the period in which the corresponding flexible TDM slot is output. 0 Disable byte. 1 Enable byte. 6 REVERSE_OUT_BYTE Reverses the bits in the byte (big endian or little endian). This bit changes 0x0 RW the endianness of the data bits within the corresponding flexible TDM slot by optionally reversing the order of the bits from MSB to LSB. 0 Do not reverse byte (big endian). 1 Reverse byte (little endian). Rev. D | Page 130 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Bits Bit Name Settings1 Description Reset Access 5 SERIAL_OUT_SEL Source serial output channel group. This bit, together with Bits[4:2] 0x0 RW (CHANNEL_OUT_POS), selects which serial output channel is the source of data for the corresponding flexible TDM output slot. 0 Serial Output Channel 32 to Serial Output Channel 39. 1 Serial Output Channel 40 to Serial Output Channel 47. [4:2] CHANNEL_OUT_POS Source serial output channel. These bits, along with Bit 5 (SERIAL_OUT_SEL), 0x0 RW select which serial output channel is the source of data for the corre- sponding flexible TDM output slot. If Bit 5 (SERIAL_OUT_SEL) = 0b0, Bits[4:2] (CHANNEL_OUT_POS) select serial output channels between Serial Output Channel 32 and Serial Output Channel 39. If Bit 5 (SERIAL_OUT_SEL) = 0b1, Bits[4:2] (CHANNEL_OUT_POS) selects serial output channels between Serial Output Channel 40 and Serial Output Channel 47. 000 Serial Output Channel 32 or Serial Output Channel 40. 001 Serial Output Channel 33 or Serial Output Channel 41. 010 Serial Output Channel 34 or Serial Output Channel 42. 011 Serial Output Channel 35 or Serial Output Channel 43. 100 Serial Output Channel 36 or Serial Output Channel 44. 101 Serial Output Channel 37 or Serial Output Channel 45. 110 Serial Output Channel 38 or Serial Output Channel 46. 111 Serial Output Channel 39 or Serial Output Channel 47. [1:0] BYTE_OUT_POS Source data byte. These bits determine which data byte is used from the 0x0 RW corresponding serial output channel (selected by setting Bit 5 (SERIAL_ OUT_SEL) and Bits[4:2] (CHANNEL_OUT_POS)). Because there can be up to 32 bits in the data-word, four bytes are available. 00 Byte 0; Bits[31:24]. 01 Byte 1; Bits[23:16]. 10 Byte 2; Bits[15:8]. 11 Byte 3; Bits[7:0]. 1 N/A means not applicable. Rev. D | Page 131 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet DSP CORE CONTROL REGISTERS Hibernate Setting Register Address: 0xF400, Reset: 0x0000, Name: HIBERNATE When hibernation mode is activated, the DSP core continues processing the current audio sample or block, and then enters a low power hibernation state. If Bit 0 (HIBERNATE) is set to 0b1 when the DSP core is processing audio, wait at least the duration of one sample before attempting to modify any other control registers. If Bit 0 (HIBERNATE) is set to 0b1 when the DSP core is processing audio, and block processing is used in the signal flow, wait at least the duration of one block plus the duration of one sample before attempting to modify any other control registers. During hibernation, interrupts to the core are disabled. This prevents audio from flowing into or out of the DSP core. Because DSP processing ceases when hibernation is active, there is a significant drop in the current consumption on the DVDD supply. Table 94. Bit Descriptions for Hibernate Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 HIBERNATE Enter hibernation mode. This bit disables incoming interrupts and tells the 0x0 RW DSP core to go to a low power sleep mode after the next audio sample or block has finished processing and causes the DSP to enter hibernation mode by masking all interrupts. 0 Not hibernating; interrupts enabled. 1 Enter hibernation; interrupts disabled. 1 N/A means not applicable. Rev. D | Page 132 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Start Pulse Selection Register Address: 0xF401, Reset: 0x0002, Name: START_PULSE This register selects the start pulse that marks the beginning of each audio frame in the DSP core, which effectively sets the sample rate of the audio going through the DSP. This start pulse can originate from either an internally generated pulse (from Clock Generator 1 or Clock Generator 2) or from an external clock that is received on one of the LRCLK pins of one of the serial ports. Any audio input or output from the DSP core that is asynchronous to this DSP start pulse rate must go through an ASRC. If asynchronous audio signals (that is, signals that are not synchronized to whatever start pulse is selected) are input to the DSP without first going through an ASRC, samples are skipped or doubled, leading to distortion and audible artifacts in the audio signal. Table 95. Bit Descriptions for START_PULSE Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW [4:0] START_PULSE Start pulse selection. 0x02 RW 00000 Base sample rate ÷ 4 (12 kHz for 48 kHz base sample rate) (1/4 output of Clock Generator 1). 00001 Base sample rate ÷ 2 (24 kHz for 48 kHz base sample rate) (1/2 output of Clock Generator 1). 00010 Base sample rate (48 kHz for 48 kHz base sample rate) (×1 output of Clock Generator 1). 00011 Base sample rate × 2 (96 kHz for 48 kHz base sample rate) (×2 output of Clock Generator 1). 00100 Base sample rate × 4 (192 kHz for 48 kHz base sample rate) (×4 output of Clock Generator 1). 00101 Base sample rate ÷ 6 (8 kHz for 48 kHz base sample rate) (1/4 output of Clock Generator 2). 00110 Base sample rate ÷ 3 (16 kHz for 48 kHz base sample rate) (1/2 output of Clock Generator 2). 00111 2× base sample rate ÷ 3 (32 kHz for 48 kHz base sample rate) (×1 output of Clock Generator 2). 01000 Serial Input Port 0 sample rate (Register 0xF201 (SERIAL_BYTE_0_1), Bits[4:0]). 01001 Serial Input Port 1 sample rate (Register 0xF205 (SERIAL_BYTE_1_1), Bits[4:0]). 01010 Serial Input Port 2 sample rate (Register 0xF209 (SERIAL_BYTE_2_1), Bits[4:0]). 01011 Serial Input Port 3 sample rate (Register 0xF20D (SERIAL_BYTE_3_1), Bits[4:0]). 01100 Serial Output Port 0 sample rate (Register 0xF211 (SERIAL_BYTE_4_1), Bits[4:0]). 01101 Serial Output Port 1 sample rate (Register 0xF215 (SERIAL_BYTE_5_1), Bits[4:0]). 01110 Serial Output Port 2 sample rate (Register 0xF219 (SERIAL_BYTE_6_1), Bits[4:0]). 01111 Serial Output Port 3 sample rate (Register 0xF21D (SERIAL_BYTE_7_1), Bits[4:0]). 10000 S/PDIF receiver sample rate (derived from the S/PDIF input stream). 1 N/A means not applicable. Rev. D | Page 133 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Instruction to Start the Core Register Address: 0xF402, Reset: 0x0000, Name: START_CORE This register enables the DSP core and initiates the program counter, which then begins incrementing through the program memory and executing instruction codes. This register is edge triggered, meaning that a rising edge on Bit 0 (START_CORE), that is, a transition from 0b0 to 0b1, initiates the program counter. A falling edge on Bit 0 (START_CORE), that is, a transition from 0b1 to 0b0, has no effect. To stop the DSP core, use Register 0xF400 (HIBERNATE), Bit 0 (HIBERNATE). Table 96. Bit Descriptions for START_CORE Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 START_CORE A transition of this bit from 0b0 to 0b1 enables the DSP core to start executing 0x0 RW its program. A transition from 0b1 to 0b0 does not affect the DSP core. 0 A transition from 0b0 to 0b1 enables the DSP core to start program execution. 1 A transition from 0b1 to 0b0 does not affect the DSP core. Rev. D | Page 134 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Instruction to Stop the Core Register Address: 0xF403, Reset: 0x0000, Name: KILL_CORE Bit 0 (KILL_CORE) halts the DSP core immediately, even when it is in an undefined state. Because halting the DSP core immediately can lead to memory corruption, it must be used only in debugging situations or when a full reset and reprogramming are required. This register immediately halts the core on a transition from 0b0 to 0b1 and keeps the core halted as long as this bit remains high. A transition on Bit 0 (KILL_CORE) from 0b1 to 0b0 has no effect, except to allow the core to be restarted with the START_CORE register. To stop the DSP core after the next audio frame or block, use Register 0xF400 (HIBERNATE), Bit 0 (HIBERNATE). Table 97. Bit Descriptions for KILL_CORE Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 KILL_CORE Immediately halts the core. When this bit transitions from 0b0 to 0b1, the 0x0 RW core immediately halts, which can bring about undesired effects and must be used only in debugging or when a full reset and reprogramming are required. To stop the core when it is running, use Register 0xF400 (HIBERNATE) to halt the core in a controlled manner. 0 Core is allowed to run and is not halted. A transition from 0b1 to 0b0 has no effect except to allow the core to be restarted when the START_CORE register is used. 1 Core is halted. A transition from 0b0 to 0b1 immediately halts the core and keeps the core stopped as long as this bit is high (0b1). 1 N/A means not applicable. Start Address of the Program Register Address: 0xF404, Reset: 0x0000, Name: START_ADDRESS This register sets the program address where the program counter begins after the DSP core is enabled, using Register 0xF402, Bit 0 (START_CORE). The SigmaStudio compiler automatically sets the program start address, which means that the user is not required to manually modify the value of this register. Table 98. Bit Descriptions for START_ADDRESS Bits Bit Name Settings Description Reset Access [15:0] START_ADDRESS Not applicable Program start address. 0x0000 RW Rev. D | Page 135 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Core Status Register Address: 0xF405, Reset: 0x0000, Name: CORE_STATUS This read only register allows the user to check the status of the DSP core. To manually modify the core status, use Register 0xF400 (HIBERNATE), Register 0xF402 (START_CORE), and Register 0xF403 (KILL_CORE). Table 99. Bit Descriptions for CORE_STATUS Bits Bit Name Settings1 Description Reset Access [15:3] RESERVED N/A Reserved. 0x0 RW [2:0] CORE_STATUS DSP core status. These bits display the status of the DSP core at the 0x0 RW moment the value is read. 000 Core is not running. This is the default state when the device boots. When the core is manually stopped using Register 0xF403 (KILL_CORE), the core returns to this state. 001 Core is running normally. 010 Core is paused. The clock signal is cut off from the core, preserving its state until the clock resumes. This state occurs only if a pause instruction is explicitly defined in the DSP program. 011 Core is in sleep mode (the core may be actively running a program, but it has finished executing instructions and is waiting in an idle state for the next audio sample to arrive). This state occurs only if a sleep instruction is explicitly called in the DSP program. 100 Core is stalled. This occurs when the DSP core is attempting to service more than one request, and it must stop execution for a few cycles to do so in a timely manner. The core continues execution immediately after the requests are serviced. 1 N/A means not applicable. Rev. D | Page 136 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 DEBUG AND RELIABILITY REGISTERS Clear the Panic Manager Register Address: 0xF421, Reset: 0x0000, Name: PANIC_CLEAR When Register 0xF427 (PANIC_FLAG) signals that an error has occurred, use Register 0xF421 (PANIC_CLEAR) to reset it. Toggle Bit 0 (PANIC_CLEAR) of this register from 0b0 to 0b1 and then back to 0b0 again to clear the flag and reset the state of the panic manager. Table 100. Bit Descriptions for PANIC_CLEAR Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 PANIC_CLEAR Clear the panic manager. To reset the PANIC_FLAG register, toggle this bit 0x0 RW on and then off again. 0 Panic manager is not cleared. 1 Clear panic manager (on a rising edge of this bit). 1 N/A means not applicable. Rev. D | Page 137 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Panic Parity Register Address: 0xF422, Reset: 0x0003, Name: PANIC_PARITY_MASK The panic manager checks and reports memory parity mask errors. Register 0xF422 (PANIC_PARITY_MASK) allows the user to configure which memories, if any, is subject to error reporting. Note that the internal structure of DM0 and DM1 have four banks, BANK0 to BANK3. These are normally transparent to the user but can be masked here individually. ASRC memory is organized into two ARSC memory banks, ARSC Memory Bank 1 and ARSC Memory Bank 2. Stereo ARSC0 to Stereo ARSC3 are used with ARSC Memory Bank 1, and Stereo ARSC4 to Stereo ARSC7 is used with ARSC Memory Bank 2. Table 101. Bit Descriptions for PANIC_PARITY_MASK Bits Bit Name Settings1 Description Reset Access [15:12] RESERVED N/A Reserved. 0x0 RW 11 DM1_BANK3_MASK DM1 Bank 3 mask. 0x0 RW 0 Report DM1_BANK3 parity mask errors. 1 Do not report DM1_BANK3 parity mask errors. 10 DM1_BANK2_MASK DM1 Bank 2 mask. 0x0 RW 0 Report DM1_BANK2 parity mask errors. 1 Do not report DM1_BANK2 parity mask errors. 9 DM1_BANK1_MASK DM1 Bank 1 mask. 0x0 RW 0 Report DM1_BANK1 parity mask errors. 1 Do not report DM1_BANK1 parity mask errors. Rev. D | Page 138 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Bits Bit Name Settings1 Description Reset Access 8 DM1_BANK0_MASK DM1 Bank 0 mask. 0x0 RW 0 Report DM1_BANK0 parity mask errors. 1 Do not report DM1_BANK0 parity mask errors. 7 DM0_BANK3_MASK DM0 Bank 3 mask. 0x0 RW 0 Report DM0_BANK3 parity mask errors. 1 Do not report DM0_BANK3 parity mask errors. 6 DM0_BANK2_MASK DM0 Bank 2 mask. 0x0 RW 0 Report DM0_BANK2 parity mask errors. 1 Do not report DM0_BANK2 parity mask errors. 5 DM0_BANK1_MASK DM0 Bank 1 mask. 0x0 RW 0 Report DM0_BANK1 parity mask errors. 1 Do not report DM0_BANK1 parity mask errors. 4 DM0_BANK0_MASK DM0 Bank 0 mask. 0x0 RW 0 Report DM0_BANK0 parity mask errors. 1 Do not report DM0_BANK0 parity mask errors. 3 PM1_MASK PM1 parity mask. 0x0 RW 0 Report PM1 parity mask errors. 1 Do not report PM1 parity mask errors. 2 PM0_MASK PM0 parity mask. 0x0 RW 0 Report PM0 parity mask errors. 1 Do not report PM0 parity mask errors. 1 ASRC1_MASK ASRC 1 parity mask. 0x1 RW 0 Report ASRC 1 parity mask errors. 1 Do not report ASRC 1 parity mask errors. 0 ASRC0_MASK ASRC 0 parity mask. 0x1 RW 0 Report ASRC 0 parity mask errors. 1 Do not report ASRC 0 parity mask errors. 1 N/A means not applicable. Panic Mask 0 Register Address: 0xF423, Reset: 0x0000, Name: PANIC_SOFTWARE_MASK The panic manager checks and reports software errors. Register 0xF423 (PANIC_SOFTWARE_MASK) allows the user to configure whether software errors are reported to the panic manager or ignored. Table 102. Bit Descriptions for PANIC_SOFTWARE_MASK Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved 0x0 RW 0 PANIC_SOFTWARE Software mask. 0x0 RW 0 Report parity errors. 1 Do not report parity errors. 1 N/A means not applicable. Rev. D | Page 139 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Panic Mask 1 Register Address: 0xF424, Reset: 0x0000, Name: PANIC_WD_MASK The panic manager checks and reports watchdog errors. Register 0xF424 (PANIC_WD_MASK) allows the user to configure whether watchdog errors are reported to the panic manager or ignored. Table 103. Bit Descriptions for PANIC_WD_MASK Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 PANIC_WD Watchdog mask. 0x0 RW 0 Report watchdog errors. 1 Do not report watchdog errors. 1 N/A means not applicable. Panic Mask 2 Register Address: 0xF425, Reset: 0x0000, Name: PANIC_STACK_MASK The panic manager checks and reports stack errors. Register 0xF425 (PANIC_STACK_MASK) allows the user to configure whether stack errors are reported to the panic manager or ignored. Table 104. Bit Descriptions for PANIC_STACK_MASK Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 PANIC_STACK Stack mask. 0x0 RW 0 Report stack errors. 1 Do not report stack errors. 1 N/A means not applicable. Rev. D | Page 140 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Panic Mask 3 Register Address: 0xF426, Reset: 0x0000, Name: PANIC_LOOP_MASK The panic manager checks and reports software errors related to looping code sections. Register 0xF426 (PANIC_LOOP_MASK) allows the user to configure whether loop errors are reported to the panic manager or ignored. Table 105. Bit Descriptions for PANIC_LOOP_MASK Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 PANIC_LOOP Loop mask. 0x0 RW 0 Report loop errors. 1 Do not report loop errors. 1 N/A means not applicable. Panic Flag Register Address: 0xF427, Reset: 0x0000, Name: PANIC_FLAG This register acts as the master error flag for the panic manager. If any error is encountered in any functional block whose panic manager mask is disabled, this register logs that an error has occurred. Individual functional block masks are configured using Register 0xF422 (PANIC_PARITY_MASK), Register 0xF423 (PANIC_SOFTWARE_MASK), Register 0xF424 (PANIC_WD_MASK), Register 0xF425 (PANIC_STACK_MASK), and Register 0xF426 (PANIC_LOOP_MASK). Table 106. Bit Descriptions for PANIC_FLAG Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 PANIC_FLAG Error flag from panic manager. This error flag bit is sticky. When an error is 0x0 R reported, this bit goes high, and it stays high until the user resets it using Register 0xF421 (PANIC_CLEAR). 0 No error. 1 Error. 1 N/A means not applicable. Rev. D | Page 141 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Panic Code Register Address: 0xF428, Reset: 0x0000, Name: PANIC_CODE When Register 0xF427 (PANIC_FLAG) indicates that an error has occurred, this register provides details that reveals which subsystem is reporting an error. If several errors occur, this register reports only the first error that occurs. Subsequent errors are ignored until the register is cleared by toggling Register 0xF421 (PANIC_CLEAR). Table 107. Bit Descriptions for PANIC_CODE Bits Bit Name Settings Description Reset Access 15 ERR_SOFT Error from software panic. 0x0 R 0 No error from the software panic. 1 Error from the software panic. 14 ERR_LOOP Error from loop overrun. 0x0 R 0 No error from the loop overrun. 1 Error from the loop overrun. 13 ERR_STACK Error from stack overrun. 0x0 R 0 No error from the stack overrun. 1 Error from the stack overrun. 12 ERR_WATCHDOG Error from the watchdog counter. 0x0 R 0 No error from the watchdog counter. 1 Error from the watchdog counter. 11 ERR_DM1B3 Error in DM1 Bank 3. 0x0 R 0 No error in DM1 Bank 3. 1 Error in DM1 Bank 3. 10 ERR_DM1B2 Error in DM1 Bank 2. 0x0 R 0 No error in DM1 Bank 2. 1 Error in DM1 Bank 2. Rev. D | Page 142 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Bits Bit Name Settings Description Reset Access 9 ERR_DM1B1 Error in DM1 Bank 1. 0x0 R 0 No error in DM1 Bank 1. 1 Error in DM1 Bank 1. 8 ERR_DM1B0 Error in DM1 Bank 0. 0x0 R 0 No error in DM1 Bank 0. 1 Error in DM1 Bank 0. 7 ERR_DM0B3 Error in DM0 Bank 3. 0x0 R 0 No error in DM0 Bank 3 1 Error in DM0 Bank 3. 6 ERR_DM0B2 Error in DM0 Bank 2. 0x0 R 0 No error in DM0 Bank 2. 1 Error in DM0 Bank 2. 5 ERR_DM0B1 Error in DM0 Bank 1. 0x0 R 0 No error in DM0 Bank 1. 1 Error in DM0 Bank 1. 4 ERR_DM0B0 Error in DM0 Bank 0. 0x0 R 0 No error in DM0 Bank 0. 1 Error in DM0 Bank 0. 3 ERR_PM1 Error in PM1. 0x0 R 0 No error in PM1. 1 Error in PM1. 2 ERR_PM0 Error in PM0. 0x0 R 0 No error in PM0. 1 Error in PM0. 1 ERR_ASRC1 Error in ASRC 1. 0x0 R 0 No error in ASRC 1. 1 Error in ASRC 1. 0 ERR_ASRC0 Error in ASRC 0. 0x0 R 0 No error in ASRC 0. 1 Error in ASRC 0. Execute Stage Error Program Count Register Address: 0xF432, Reset: 0x0000, Name: EXECUTE_COUNT When a software error occurs, this register logs the program instruction count at the time when the error occurred for software debugging purposes. Table 108. Bit Descriptions for EXECUTE_COUNT Bits Bit Name Settings Description Reset Access [15:0] EXECUTE_COUNT Not applicable Program count in the execute stage when the error occurred. 0x0000 RW Rev. D | Page 143 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Software Panic Value Register 0 Address: 0xF433, Reset: 0x0000, Name: SOFTWARE_VALUE_0 When a software error occurs, this register can be populated with an error code if the software error trap is programmed to store an error code. Table 109. Bit Descriptions for SOFTWARE_VALUE_0 Bits Bit Name Settings Description Reset Access [15:0] SOFTWARE_VALUE_0 Not applicable Error code. 0x0000 RW Software Panic Value Register 1 Address: 0xF434, Reset: 0x0000, Name: SOFTWARE_VALUE_1 When a software error occurs, this register can be populated with an error code if the software error trap is programmed to store an error code. Table 110. Bit Descriptions for SOFTWARE_VALUE_1 Bits Bit Name Settings Description Reset Access [15:0] SOFTWARE_VALUE_1 Not applicable Error code. 0x0000 RW Watchdog Maximum Count Register Address: 0xF443, Reset: 0x0000, Name: WATCHDOG_MAXCOUNT This register is designed to start counting at a specified number and decrement by 1 for each clock cycle of the system clock in the core. The counter is reset to the maximum value each time the program counter jumps to the beginning of the program to begin processing another audio frame (this is implemented in the DSP program code generated by SigmaStudio). If the counter reaches 0, a watchdog error flag is raised in the panic manager. The watchdog is typically set to begin counting from a number slightly larger than the maximum number of instructions expected to execute in the program, such that an error occurs if the program does not finish in time for the next incoming sample. Table 111. Bit Descriptions for WATCHDOG_MAXCOUNT Bits Bit Name Settings Description Reset Access [15:13] RESERVED Not applicable Reserved. 0x0 RW [12:0] WD_MAXCOUNT Not applicable Value from which the watchdog counter begins counting down. 0x0000 RW Rev. D | Page 144 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Watchdog Prescale Register Address: 0xF444, Reset: 0x0000, Name: WATCHDOG_PRESCALE The watchdog prescaler is a number that is multiplied by the setting in Register 0xF443 (WATCHDOG_MAXCOUNT) to achieve very large counts for the watchdog, if necessary. Using the largest prescale factor of 128 × 1024 and the largest watchdog maximum count of 64 × 1024, a very large watchdog counter, on the order of 8.5 billion clock cycles, can be achieved. Table 112. Bit Descriptions for WATCHDOG_PRESCALE Bits Bit Name Settings1 Description Reset Access [15:4] RESERVED N/A Reserved. 0x0 RW [3:0] WD_PRESCALE Watchdog counter prescale setting. 0x0 RW 0000 Increment every 64 clock cycles. 0001 Increment every 128 clock cycles. 0010 Increment every 256 clock cycles. 0011 Increment every 512 clock cycles. 0100 Increment every 1024 clock cycles. 0101 Increment every 2048 clock cycles. 0110 Increment every 4096 clock cycles. 0111 Increment every 8192 clock cycles. 1000 Increment every 16,384 clock cycles. 1001 Increment every 32,768 clock cycles. 1010 Increment every 65,536 clock cycles. 1011 Increment every 131,072 clock cycles. 1 N/A means not applicable. Rev. D | Page 145 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet DSP PROGRAM EXECUTION REGISTERS Enable Block Interrupts Register Address: 0xF450, Reset: 0x0000, Name: BLOCKINT_EN This register enables block interrupts, which are necessary when frequency domain processing is required in the audio processing program. If block processing algorithms are used in SigmaStudio, SigmaStudio automatically sets this register accordingly. The user does not need to manually change the value of this register after SigmaStudio has configured it. Table 113. Bit Descriptions for BLOCKINT_EN Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 BLOCKINT_EN Enable block interrupts. 0x0 RW 0 Disable block interrupts. 1 Enable block interrupts. 1 N/A means not applicable. Value for the Block Interrupt Counter Register Address: 0xF451, Reset: 0x0000, Name: BLOCKINT_VALUE This 16-bit register controls the duration in audio frames of a block. A counter increments each time a new frame start pulse is received by the DSP core. When the counter reaches the value determined by this register, a block interrupt is generated and the counter is reset. If block processing algorithms are used in SigmaStudio, SigmaStudio automatically sets this register accordingly. The user does not need to manually change the value of this register after SigmaStudio has configured the register. Table 114. Bit Descriptions for BLOCKINT_VALUE Bits Bit Name Settings Description Reset Access [15:0] BLOCKINT_VALUE Not applicable Value for the block interrupt counter. 0x0000 RW Program Counter, Bits[23:16] Register Address: 0xF460, Reset: 0x0000, Name: PROG_CNTR0 This register, in combination with Register 0xF461 (PROG_CNTR1), stores the current value of the program counter. Table 115. Bit Descriptions for PROG_CNTR0 Bits Bit Name Settings Description Reset Access [15:8] RESERVED Not applicable Reserved. 0x0 RW [7:0] PROG_CNTR_MSB Not applicable Program counter, Bits[23:16]. 0x00 R Rev. D | Page 146 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Program Counter, Bits[15:0] Register Address: 0xF461, Reset: 0x0000, Name: PROG_CNTR1 This register, in combination with Register 0xF460 (PROG_CNTR0), stores the current value of the program counter. Table 116. Bit Descriptions for PROG_CNTR1 Bits Bit Name Settings Description Reset Access [15:0] PROG_CNTR_LSB Not applicable Program counter, Bits[15:0]. 0x0000 R Program Counter Clear Register Address: 0xF462, Reset: 0x0000, Name: PROG_CNTR_CLEAR Enabling and disabling Bit 0 (PROG_CNTR_CLEAR) resets Register 0xF465 (PROG_CNTR_MAXLENGTH0) and Register 0xF466 (PROG_CNTR_MAXLENGTH1). Table 117. Bit Descriptions for PROG_CNTR_CLEAR Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 PROG_CNTR_CLEAR Clears the program counter. 0x0 RW 0 Allow the program counter to update itself. 1 Clear the program counter and disable it from updating itself. 1 N/A means not applicable. Program Counter Length, Bits[23:16] Register Address: 0xF463, Reset: 0x0000, Name: PROG_CNTR_LENGTH0 This register, in combination with Register 0xF464 (PROG_CNTR_LENGTH1), keeps track of the peak value reached by the program counter during the last audio frame or block. It can be cleared using Register 0xF462 (PROG_CNTR_CLEAR). Table 118. Bit Descriptions for PROG_CNTR_LENGTH0 Bits Bit Name Settings Description Reset Access [15:8] RESERVED Not applicable Reserved. 0x0 RW [7:0] PROG_LENGTH_MSB Not applicable Program counter length, Bits[23:16]. 0x00 R Rev. D | Page 147 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Program Counter Length, Bits[15:0] Register Address: 0xF464, Reset: 0x0000, Name: PROG_CNTR_LENGTH1 This register, in combination with Register 0xF463 (PROG_CNTR_LENGTH0), keeps track of the peak value reached by the program counter during the last audio frame or block. This counter can be cleared using Register 0xF462 (PROG_CNTR_CLEAR). Table 119. Bit Descriptions for PROG_CNTR_LENGTH1 Bits Bit Name Settings Description Reset Access [15:0] PROG_LENGTH_LSB Not applicable Program counter length, Bits[15:0]. 0x0000 R Program Counter Max Length, Bits[23:16] Register Address: 0xF465, Reset: 0x0000, Name: PROG_CNTR_MAXLENGTH0 This register, in combination with Register 0xF466 (PROG_CNTR_MAXLENGTH1), keeps track of the highest peak value reached by the program counter from when the DSP core started. This counter can be cleared using Register 0xF462 (PROG_CNTR_CLEAR). Table 120. Bit Descriptions for PROG_CNTR_MAXLENGTH0 Bits Bit Name Settings Description Reset Access [15:8] RESERVED Not applicable Reserved. 0x0 RW [7:0] PROG_MAXLENGTH_MSB Not applicable Program counter maximum length, Bits[23:16]. 0x00 R Program Counter Max Length, Bits[15:0] Register Address: 0xF466, Reset: 0x0000, Name: PROG_CNTR_MAXLENGTH1 This register, in combination with Register 0xF465 (PROG_CNTR_MAXLENGTH0), keeps track of the highest peak value reached by the program counter from when the DSP core started. This counter can be cleared using Register 0xF462 (PROG_CNTR_CLEAR). Table 121. Bit Descriptions for PROG_CNTR_MAXLENGTH1 Bits Bit Name Settings Description Reset Access [15:0] PROG_MAXLENGTH_LSB Not applicable Program counter maximum length, Bits[15:0]. 0x0000 R Rev. D | Page 148 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 MULTIPURPOSE PIN CONFIGURATION REGISTERS Multipurpose Pin Mode Register Address: 0xF510 to 0xF51D (Increments of 0x1), Reset: 0x0000, Name: MPx_MODE These 14 registers configure the MPx pins. Certain MPx pins can function as audio clock pins, control bus pins, or GPIO pins. Table 122. Bit Descriptions for MPx_MODE Bits Bit Name Settings1 Description Reset Access [15:11] RESERVED N/A Reserved. 0x0 RW [10:8] SS_SELECT Master port slave select channel selection. If the pin is configured as a slave 0x0 RW select line (Bits[3:1] (MP_MODE) = 0b110), these bits configure which slave select channel the pin corresponds to, which allows multiple slave devices to be connected to the SPI master port, all using different slave select lines. The first slave select signal (Slave Select 0) is always routed to the SS_M/ MP0 pin. The remaining six slave select lines can be routed to any MPx pin that has been configured as a slave select output. 000 Slave Select Channel 1. 001 Slave Select Channel 2. 010 Slave Select Channel 3. 011 Slave Select Channel 4. 100 Slave Select Channel 5. 101 Slave Select Channel 6. [7:4] DEBOUNCE_VALUE Debounce circuit setting. These bits configure the duration of the debounce 0x0 RW circuitry when the corresponding pin is configured as an input (Bits[3:1] (MP_MODE) = 0b000). 0001 0.3 ms debounce. 0010 0.6 ms debounce. 0011 0.9 ms debounce. 0100 5.0 ms debounce. 0101 10.0 ms debounce. 0110 20.0 ms debounce. 0111 40.0 ms debounce. 0000 No debounce. Rev. D | Page 149 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Bits Bit Name Settings1 Description Reset Access [3:1] MP_MODE Pin mode (when multipurpose function is enabled). These bits select the 0x0 RW function of the corresponding pin if it is enabled in multipurpose mode (Bit 0 (MP_ENABLE) = 0b1). 000 General-purpose digital input 001 General-purpose input, driven by control port; sends the input value to the DSP core, but that value can be overwritten by a direct register write 010 General-purpose output with pull-up. 011 General-purpose output without pull-up. 100 PDM microphone data input. 101 Panic manager error flag output . 110 Slave select line for the master SPI port. 0 MP_ENABLE Function selection (multipurpose or clock/control). This bit selects 0x0 RW whether the corresponding pin is used as an MPx pin or as its primary function (which could be either an audio clock or control bus pin). 0 Audio clock or control port function enabled; the settings of the MPx_MODE, MPx_WRITE, and MPx_READ registers are ignored. 1 Multipurpose function enabled. 1 N/A means not applicable. Multipurpose Pin Write Value Register Address: 0xF520 to 0xF52D (Increments of 0x1), Reset: 0x0000, Name: MPx_WRITE If an MPx pin is configured as an output driven by the control port (the corresponding Bits[3:1] (MP_MODE) = 0b001), the value that is output from the DSP core can be configured by directly writing to these registers. Table 123. Bit Descriptions for MPx_WRITE Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 W 0 MP_REG_WRITE MPx pin output state when pin is configured as an output written by the 0x0 W control port. This register configures the value seen by the DSP core for the corresponding MPx pin input. The pin can have two states: logic low (off) or logic high (on). 0 MPx pin output low. 1 MPx pin output high. 1 N/A means not applicable. Rev. D | Page 150 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Multipurpose Pin Read Value Registers Address: 0xF530 to 0xF53D (Increments of 0x1), Reset: 0x0000, Name: MPx_READ These registers log the current state of the MPx pins when they are configured as inputs. The pins can have two states: logic low (off) or logic high (on). Table 124. Bit Descriptions for MPx_READ Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 R 0 MP_REG_READ MPx pin read value. 0x0 R 0 MPx pin input low. 1 MPx pin input high. 1 N/A means not applicable. Rev. D | Page 151 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Digital PDM Microphone Control Register Address: 0xF560 to 0xF561 (Increments of 0x1), Reset: 0x4000, Name: DMIC_CTRLx These registers configure the digital PDM microphone interface. Two registers are used to control up to four PDM microphones: Register 0xF560 (DMIC_CTRL0) configures PDM Microphone Channel 0 and PDM Microphone Channel 1, and Register 0xF561 (DMIC_CTRL1) configures PDM Microphone Channel 2 and PDM Microphone Channel 3. Table 125. Bit Descriptions for DMIC_CTRLx Bits Bit Name Settings1 Description Reset Access 15 RESERVED N/A Reserved. 0x0 RW [14:12] CUTOFF High-pass filter cutoff frequency. These bits configure the cutoff frequency of 0x4 RW an optional high-pass filter designed to remove dc components from the microphone data signal(s). To use these bits, Bit 3 (HPF), must be enabled. 000 59.9 Hz. 001 29.8 Hz. 010 14.9 Hz. 011 7.46 Hz. 100 3.73 Hz. 101 1.86 Hz. 110 0.93 Hz. Rev. D | Page 152 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Bits Bit Name Settings1 Description Reset Access [11:8] MIC_DATA_SRC Digital PDM microphone data source pin. These bits configure which hardware 0x0 RW pin acts as a data input from the PDM microphone(s). Up to two microphones can be connected to a single pin. 0000 SS_M/MP0. 0001 MOSI_M/MP1. 0010 SCL_M/SCLK_M/MP2. 0011 SDA_M/MISO_M/MP3. 0100 LRCLK_OUT0/MP4. 0101 LRCLK_OUT1/MP5. 0110 MP6. 0111 MP7. 1000 LRCLK_OUT2/MP8. 1001 LRCLK_OUT3/MP9. 1010 LRCLK_IN0/MP10. 1011 LRCLK_IN1/MP11. 1100 LRCLK_IN2/MP12. 1101 LRCLK_IN3/MP13. 7 RESERVED N/A Reserved. 0x0 RW [6:4] DMIC_CLK Digital PDM microphone clock select. A valid bit clock signal must be 0x0 RW assigned to the PDM microphones. Any of the four BCLK_INPUTx or four BCLK_OUTPUTx signals can be used. A trace must connect the selected pin to the clock input pin on the corresponding PDM microphone(s). If the corresponding BCLK_x pin is not configured in master mode, use an external clock source, with the BCLK_x pin and the PDM microphone acting as slaves. 000 BCLK_IN0. 001 BCLK_IN1. 010 BCLK_IN2. 011 BCLK_IN3. 100 BCLK_OUT0. 101 BCLK_OUT1. 110 BCLK_OUT2. 111 BCLK_OUT3. 3 HPF High-pass filter enable. This bit enables or disables a high-pass filter to 0x0 RW remove dc components from the microphone data signals. The cutoff of the filter is controlled by Bits[14:12] (CUTOFF). 0 HPF disabled. 1 HPF enabled. 2 DMPOL Data polarity swap. When this bit is set to 0b0, a logic high data input is 0x0 RW treated as logic high, and a logic low data input is treated as logic low. When this bit is set to 0b1, the opposite is true: a logic high data input is treated as a logic low, and a logic low data input is treated as logic high. This effectively inverts the amplitude of the incoming audio data. 0 Data polarity normal. 1 Data polarity inverted. 1 DMSW Digital PDM microphone channel swap. In DMIC_CTRL0, this bit swaps PDM 0x0 RW Microphone Channel 0 and PDM Microphone Channel 1. In the DMIC_CTRL1 register, this bit swaps PDM Microphone Channel 2 and PDM Microphone Channel 3. 0 Normal. 1 Swap left and right channels. 0 DMIC_EN Digital PDM microphone enable. This bit enables or disables the data input 0x0 RW from the PDM microphones. 0 Digital PDM microphone disabled. 1 Digital PDM microphone enabled. 1 N/A means not applicable. Rev. D | Page 153 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet ASRC STATUS AND CONTROL REGISTERS ASRC Lock Status Register Address: 0xF580, Reset: 0x0000, Name: ASRC_LOCK This register contains eight bits that represent the lock status of each ASRC stereo pair on the ADAU1452 and the ADAU1451. The lock status requires three conditions: the output target rate is set, the input rate is steady and has been detected, and the ratio between input and output rates has been calculated. If all of these conditions are true for a given stereo ASRC, the corresponding lock bit is high. If any of these conditions is not true, the corresponding lock bit is low. Table 126. Bit Descriptions for ASRC_LOCK Bits Bit Name Settings1 Description Reset Access [15:8] RESERVED N/A Reserved. 0x0 RW 7 ASRC7L ASRC 7 lock status. 0x0 R 0 Unlocked. 1 Locked. 6 ASRC6L ASRC 6 lock status. 0x0 R 0 Unlocked. 1 Locked. 5 ASRC5L ASRC 5 lock status. 0x0 R 0 Unlocked. 1 Locked. 4 ASRC4L ASRC 4 lock status. 0x0 R 0 Unlocked. 1 Locked. 3 ASRC3L ASRC 3 lock status. 0x0 R 0 Unlocked. 1 Locked. 2 ASRC2L ASRC 2 lock status. 0x0 R 0 Unlocked. 1 Locked. 1 ASRC1L ASRC 1 lock status. 0x0 R 0 Unlocked. 1 Locked. 0 ASRC0L ASRC 0 lock status. 0x0 R 0 Unlocked. 1 Locked. 1 N/A means not applicable. Rev. D | Page 154 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 ASRC Mute Register Address: 0xF581, Reset: 0x0000, Name: ASRC_MUTE This register contains controls related to the muting of audio on ASRC channels. Bits[7:0] (ASRCxM) are individual mute controls for each stereo ASRC on the ADAU1452 and ADAU1451. Bit 8 (ASRC_RAMP0) and Bit 9 (ASRC_RAMP1) enable or disable an optional volume ramp-up and ramp-down to smoothly transition between muted and unmuted states. The mute and unmute ramps are linear. The duration of the ramp is determined by the sample rate of the DSP core, which is set by Register 0xF401 (START_PULSE). The ramp takes exactly 2048 input samples to complete. For example, if the sample rate of audio entering an ASRC channel is 48 kHz, the duration of the ramp is 2048/48,000 = 42.7 ms. If the sample rate of audio entering an ASRC channel is 6 kHz, the duration of the ramp is 2048/6000 = 341.3 ms. Bit 10 (LOCKMUTE) allows the ASRCs to automatically mute themselves in the event that lock status is lost or not attained. Table 127. Bit Descriptions for ASRC_MUTE Bits Bit Name Settings1 Description Reset Access [15:11] RESERVED N/A Reserved. 0x0 RW 10 LOCKMUTE Mutes ASRCs when lock is lost. When this bit is enabled, individual stereo 0x0 RW ASRCs automatically mute in the event that lock status is lost (for example, if the sample rate of the input suddenly changes and the ASRC needs to reattain lock), provided that the corresponding ASRC_RAMPx bit is set to 0b0 (enabled). This automatic mute uses a volume ramp instead of an instantaneous mute to avoid click-and-pop noises on the output. When lock status is attained again (and the corresponding ASRC_RAMPx and ASRCxM bits are set to 0b0 (enabled) and 0b0 (unmuted), respectively), the ASRC automatically unmutes using a volume ramp. However, because there is a period of uncertainty when the ASRC is attaining lock, there can still be noise on the ASRC outputs when the input signal returns. Measures must be taken in the DSP program to delay the unmuting of the ASRC output signals if this noise is not desired. The individual ASRCxM mute bits override the automatic LOCKMUTE behavior. 0 Do not mute when lock is lost. 1 Mute when lock is lost and unmute when lock is reattained. Rev. D | Page 155 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Bits Bit Name Settings1 Description Reset Access 9 ASRC_RAMP1 ASRC 7 to ASRC 4 mute disable. ASRC 7 to ASRC 4 (Channel 15 to Channel 8) 0x0 RW are defined as ASRC Block 1. This bit enables or disables mute ramping for all ASRCs in Block 1. If this bit is 0b1, Bit 7 (ASRC7M), Bit 6 (ASRC6M), Bit 5 (ASRC5M), and Bit 4 (ASRC4M) are ignored, and the outputs of ASRC 7 to ASRC 4 are active at all times. 0 Enabled. 1 Disabled; ASRC 7 to ASRC 4 never mute automatically and cannot be muted manually. 8 ASRC_RAMP0 ASRC 3 to ASRC 0 mute disable. ASRC 3 to ASRC 0 (Channel 7 to Channel 0) 0x0 RW are defined as ASRC Block 0. This bit enables or disables mute ramping for all ASRCs in Block 0. If this bit is 0b1, Bit 3 (ASRC3M), Bit 2 (ASRC2M), Bit 1 (ASRC1M), and Bit 0 (ASRC0M) are ignored, and the outputs of ASRC 3 to ASRC 0 are active at all times. 0 Enabled. 1 Disabled; ASRC 3 to ASRC 0 never mute automatically and cannot be muted manually. 7 ASRC7M ASRC 7 manual mute. 0x0 RW 0 Not muted. 1 Muted. 6 ASRC6M ASRC 6 manual mute. 0x0 RW 0 Not muted. 1 Muted. 5 ASRC5M ASRC 5 manual mute. 0x0 RW 0 Not muted. 1 Muted. 4 ASRC4M ASRC 4 manual mute. 0x0 RW 0 Not muted. 1 Muted. 3 ASRC3M ASRC 3 manual mute. 0x0 RW 0 Not muted. 1 Muted. 2 ASRC2M ASRC 2 manual mute. 0x0 RW 0 Not muted. 1 Muted. 1 ASRC1M ASRC 1 manual mute. 0x0 RW 0 Not muted. 1 Muted. 0 ASRC0M ASRC 0 manual mute. 0x0 RW 0 Not muted. 1 Muted. 1 N/A means not applicable. Rev. D | Page 156 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 ASRC Ratio Registers Address: 0xF582 to 0xF589 (Increments of 0x1), Reset: 0x0000, Name: ASRCx_RATIO These eight read only registers contain the sample rate conversion ratio of the corresponding ASRC on the ADAU1452 and the ADAU1451, which is calculated as the ratio between the detected input rate and the selected target output rate. The format of the value stored in these registers is 4.12 format. For example, a ratio of 1 is shown as 0b0001000000000000 (0x1000). A ratio of 2 is shown as 0b0010000000000000 (0x2000). A ratio of 0.5 is shown as 0b0000100000000000 (0x0800). Table 128. Bit Descriptions for ASRCx_RATIO Bits Bit Name Settings Description Reset Access [15:0] ASRC_RATIO Not applicable Output rate of the ASRC in 4.12 format. The value of this register represents the 0x0000 RW input to output rate of the corresponding ASRC. It is stored in 4.12 format. Rev. D | Page 157 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet AUXILIARY ADC REGISTERS Auxiliary ADC Read Value Register Address: 0xF5A0 to 0xF5A5 (Increments of 0x1), Reset: 0x0000, Name: ADC_READx These six registers contain the output data of the auxiliary ADC for the corresponding channel. Each of the six channels of the ADC are updated 1× per audio frame. The format for the value in this register is 6.10 format, but the top six bits are always zero, meaning that the effective format is 0.10 format. If, for example, the input to the corresponding auxiliary ADC channel is equal to AVDD (the full-scale analog input voltage), this register reads its maximum value of 0b0000001111111111 (0x3FF). If the input to the auxiliary ADC channel is AVDD/2, this register reads 0b0000001000000000 (0x200). If the input to the auxiliary ADC channel is AVDD/4, this register reads 0b0000000100000000 (0x100). Table 129. Bit Descriptions for ADC_READx Bits Bit Name Settings Description Reset Access [15:0] ADC_VALUE Not applicable ADC input value in 0.10 format, as a proportion of AVDD. Instantaneous value 0x0000 RW of the sampled data on the ADC input. The top six bits are not used, and the least significant 10 bits contain the value of the ADC input. The minimum value of 0 maps to 0 V, and the maximum value of 1023 maps to 3.3 V ± 10% (equal to the AVDD supply). Values between 0 and 1023 are linearly mapped to dc voltages between 0 V and AVDD. Rev. D | Page 158 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 S/PDIF INTERFACE REGISTERS S/PDIF Receiver Lock Bit Detection Register Address: 0xF600, Reset: 0x0000, Name: SPDIF_LOCK_DET This register contains a flag that monitors the S/PDIF receiver on the ADAU1452 and the ADAU1451 and provides a way to check the validity of the input signal. Table 130. Bit Descriptions for SPDIF_LOCK_DET Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 LOCK S/PDIF input lock. 0x0 R 0 No lock acquired; no valid input stream detected. 1 Successful lock to input stream. 1 N/A means not applicable. S/PDIF Receiver Control Register Address: 0xF601, Reset: 0x0000, Name: SPDIF_RX_CTRL This register provides controls that govern the behavior of the S/PDIF receiver on the ADAU1452 and the ADAU1451. Table 131. Bit Descriptions for SPDIF_RX_CTRL Bits Bit Name Settings1 Description Reset Access [15:4] RESERVED N/A Reserved. 0x0 RW 3 FASTLOCK S/PDIF receiver locking speed. 0x0 RW 0 Normal (locks after 64 consecutive valid samples). 1 Fast (locks after eight consecutive valid samples). 2 FSOUTSTRENGTH S/PDIF receiver behavior in the event that lock is lost. FSOUTSTRENGTH applies 0x0 RW to the output of the recovered frame clock from the S/PDIF receiver. 0 Strong; output is continued as well as is possible when the receiver notices a loss of lock condition, which may result in some data corruption. 1 Weak; output is interrupted as soon as receiver notices a loss of lock condition. Rev. D | Page 159 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Bits Bit Name Settings1 Description Reset Access [1:0] RX_LENGTHCTRL S/PDIF receiver audio word length. 0x0 RW 00 24 bits. 01 20 bits. 10 16 bits. 11 Automatic (determined by channel status bits detected in the input stream) 1 N/A means not applicable. Decoded Signals from the S/PDIF Receiver Register Address: 0xF602, Reset: 0x0000, Name: SPDIF_RX_DECODE This register monitors the embedded nonaudio data bits in the incoming S/PDIF stream on the ADAU1452 and the ADAU1451 and decodes them, providing insight into the data format of the S/PDIF input stream. Table 132. Bit Descriptions for SPDIF_RX_DECODE Bits Bit Name Settings1 Description Reset Access [15:10] RESERVED N/A Reserved. 0x0 RW [9:6] RX_WORDLENGTH_R S/PDIF receiver detected word length in the right channel. 0x0 R 0010 16 bit word (maximum 20 bits). 1100 17 bit word (maximum 20 bits). 0100 18 bit word (maximum 20 bits). 1000 19 bit word (maximum 20 bits). 1010 20 bit word (maximum 20 bits). 1101 21 bit word (maximum 24 bits). 0101 22 bit word (maximum 24 bits). 1001 23 bit word (maximum 24 bits). 1011 24 bit word (maximum 24 bits). 0011 20 bit word (maximum 24 bits) [5:2] RX_WORDLENGTH_L S/PDIF receiver detected word length in the left channel. 0x0 R 0010 16 bit word (maximum 20 bits). 1100 17 bit word (maximum 20 bits). 0100 18 bit word (maximum 20 bits). 1000 19 bit word (maximum 20 bits). 1010 20 bit word (maximum 20 bits). 1101 21 bit word (maximum 24 bits). Rev. D | Page 160 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 Bits Bit Name Settings1 Description Reset Access 0101 22 bit word (maximum 24 bits). 1001 23 bit word (maximum 24 bits). 1011 24 bit word (maximum 24 bits). 0011 20 bit word (maximum 24 bits). 1 COMPR_TYPE AC3 or DTS compression (valid only if Bit 0 (AUDIO_TYPE) = 0b1 0x0 R (compressed). 0 AC3. 1 DTS. 0 AUDIO_TYPE Linear PCM or compressed audio. 0x0 R 0 Linear PCM. 1 Compressed. 1 N/A means not applicable. Compression Mode from the S/PDIF Receiver Register Address: 0xF603, Reset: 0x0000, Name: SPDIF_RX_COMPRMODE If the incoming S/PDIF data on the ADAU1452 and the ADAU1451 has been encoded using a compression algorithm, this register displays the 16-bit code that represents the type of compression being used. Table 133. Bit Descriptions for SPDIF_RX_COMPRMODE Bits Bit Name Settings Description Reset Access [15:0] COMPR_MODE Not applicable Compression mode detected by the S/PDIF receiver. 0x0000 R Rev. D | Page 161 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Automatically Resume S/PDIF Receiver Audio Input Register Address: 0xF604, Reset: 0x0000, Name: SPDIF_RESTART When the S/PDIF receiver on the ADAU1452 and the ADAU1451 loses lock on the incoming S/PDIF signal, which can occur due to issues with signal integrity, the receiver automatically mutes itself. This register determines whether the S/PDIF receiver then automatically resumes outputting data if the S/PDIF receiver subsequently begins to receive valid data and a lock condition is reattained. By default, the S/PDIF receiver does not automatically resume audio when lock is lost (Register 0xF604 (SPDIF_RESTART), Bit 0 (RESTART_AUDIO) = 0b0). Therefore, the user must manually reset the S/PDIF receiver by toggling Register 0xF604 (SPDIF_RESTART), Bit 0 (RESTART_AUDIO), from 0b0 to 0b1 and then back to 0b0 again. To ensure that the S/PDIF receiver always begins outputting data when a valid input signal is detected, set Register 0xF604 (SPDIF_RESTART), Bit 0 (RESTART_AUDIO), to 0b1 at all times. Table 134. Bit Descriptions for SPDIF_RESTART Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 RESTART_AUDIO Allows the S/PDIF receiver to automatically resume outputting audio 0x0 RW when it successfully recovers from a loss of lock. 0 Do not automatically restart the audio when a relock occurs. 1 Restarts the audio automatically when a relock occurs, and resets Register 0xF605 (SPDIF_LOSS_OF_LOCK), Bit 0 (LOSS_OF_LOCK). 1 N/A means not applicable. Rev. D | Page 162 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 S/PDIF Receiver Loss of Lock Detection Register Address: 0xF605, Reset: 0x0000, Name: SPDIF_LOSS_OF_LOCK This bit monitors the S/PDIF lock status and checks if the lock is lost during operation of the S/PDIF receiver on the ADAU1452 and the ADAU1451. This condition can arise when, for example, a valid S/PDIF input signal was present for an extended period of time, but signal integrity worsened for a brief period, causing the receiver to then lose its lock to the input signal. In this case, Bit 0 (LOSS_OF_LOCK) transitions from 0b0 to 0b1 and remains set at 0b1 indefinitely. This indicates that, at some point during the operation of the device, lock to the input stream was lost. Bit 0 (LOSS_OF_LOCK) stays high at 0b1 until Register 0xF604 (SPDIF_RESTART), Bit 0 (RESTART_AUDIO), is set to 0b1, which clears Bit 0 (LOSS_OF_LOCK) back to 0b0. At this point, Register 0xF604 (SPDIF_RESTART), Bit 0 (RESTART_AUDIO), can be reset to 0b0 if required. Table 135. Bit Descriptions for SPDIF_LOSS_OF_LOCK Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 LOSS_OF_LOCK S/PDIF loss of lock detection (sticky bit). 0x0 R 0 S/PDIF receiver is locked to the input stream and has not lost lock after acquiring the input signal. 1 S/PDIF receiver acquired a lock on the input stream but subsequently lost lock. 1 N/A means not applicable. Rev. D | Page 163 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet S/PDIF Receiver Auxiliary Outputs Enable Register Address: 0xF608, Reset: 0x0000, Name: SPDIF_AUX_EN The S/PDIF receiver on the ADAU1452 and the ADAU1451 decodes embedded nonaudio data bits on the incoming data stream, including channel status, user data, validity bits, and parity bits. This information, together with the decoded audio data, can optionally be output on one of the SDATA_OUTx pins using Register 0xF608 (SPDIF_AUX_EN). The serial output port selected by Bits[3:0] (TDMOUT) outputs an 8-channel TDM stream containing this decoded information. Channel 0 in the TDM8 stream contains the 24 audio bits from the left S/PDIF input channel, followed by eight zero bits. Channel 1 in the TDM8 stream contains 20 zero bits, the parity bit, validity bit, user data bit, and the channel status bit from the left S/PDIF input channel, followed by eight zero bits. Channel 2 in the TDM8 stream contains 22 zero bits, followed by the compression type bit (0b0 represents AC3 and 0b1 represents DTS) and the audio type bit (0b0 represents PCM and 0b1 represents compressed), followed by eight zero bits. Channel 3 in the TDM8 stream contains 32 zero bits. Channel 4 in the TDM8 stream contains the 24 audio bits from the right S/PDIF input channel, followed by eight zero bits. Channel 5 in the TDM8 stream contains 20 zero bits followed by the parity bit, validity bit, user data bit, and the channel status bit from the right S/PDIF input channel, followed by eight zero bits. Channel 6 in the TDM8 stream contains 32 zero bits. Channel 7 in the TDM8 stream contains 23 zero bits, the block start bit, and eight zero bits. Table 136. Bit Descriptions for SPDIF_AUX_EN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 TDMOUT_CLK S/PDIF TDM clock source. When Bits[3:0] (TDMOUT) are configured to output S/PDIF 0x0 RW receiver data on one of the SDATA_OUTx pins, the corresponding serial port must be set in master mode; and Bit 4 (TDMOUT_CLK) configures which clock signals are used on the corresponding BCLK_OUTx and LRCLK_OUTx pins. If Bit 4 (TDMOUT_CLK) = 0b0, the clock signals recovered from the S/PDIF input signal are used to clock the serial output. If Bit 4 (TDMOUT_CLK) = 0b1, the output of Clock Generator 3 is used to clock serial output; and Register 0xF026 (CLK_GEN3_SRC), Bits[3:0] (FREF_PIN), must be 0b1110, and Register 0xF026 (CLK_GEN3_SRC), Bit 4 (CLK_GEN3_SRC), must be 0b1. 0 Use clocks derived from S/PDIF receiver stream. 1 Use filtered clocks from internal clock generator. [3:0] TDMOUT S/PDIF TDM output channel selection. 0x0 RW 0001 Output on SDATA_OUT0. 0010 Output on SDATA_OUT1. 0100 Output on SDATA_OUT2. 1000 Output on SDATA_OUT3. 0000 Disable S/PDIF TDM output. 1 N/A means not applicable. Rev. D | Page 164 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 S/PDIF Receiver Auxiliary Bits Ready Flag Register Address: 0xF60F, Reset: 0x0000, Name: SPDIF_RX_AUXBIT_READY The decoded channel status, user data, validity, and parity bits are recovered from the input signal one frame at a time until a full block of 192 frames is received on the ADAU1452 and the ADAU1451. When all of the 192 frames are received and decoded, Bit 0 (AUXBITS_READY), changes state from 0b0 to 0b1, indicating that the full block of data has been recovered and is available to be read from the corresponding registers. Table 137. Bit Descriptions for SPDIF_RX_AUXBIT_READY Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 AUXBITS_READY Auxiliary bits are ready flag. 0x0 R 0 Auxiliary bits are not ready to be output. 1 Auxiliary bits are ready to be output. 1 N/A means not applicable. S/PDIF Receiver Channel Status Bits (Left) Register Address: 0xF610 to 0xF61B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_CS_LEFT_x These 12 registers store the 192 channel status bits decoded from the left channel of the S/PDIF input stream on the ADAU1452 and the ADAU1451. Table 138. Bit Descriptions for SPDIF_RX_CS_LEFT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_RX_CS_LEFT Not applicable S/PDIF receiver channel status bits (left). 0x0000 R S/PDIF Receiver Channel Status Bits (Right) Register Address: 0xF620 to 0xF62B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_CS_RIGHT_x These 12 registers store the 192 channel status bits decoded from the right channel of the S/PDIF input stream on the ADAU1452 and the ADAU1451. Table 139. Bit Descriptions for SPDIF_RX_CS_RIGHT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_RX_CS_RIGHT Not applicable S/PDIF receiver channel status bits (right). 0x0000 R Rev. D | Page 165 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet S/PDIF Receiver User Data Bits (Left) Register Address: 0xF630 to 0xF63B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_UD_LEFT_x These 12 registers store the 192 user data bits decoded from the left channel of the S/PDIF input stream on the ADAU1452 and the ADAU1451. Table 140. Bit Descriptions for SPDIF_RX_UD_LEFT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_RX_UD_LEFT Not applicable S/PDIF receiver user data bits (left). 0x0000 R S/PDIF Receiver User Data Bits (Right) Register Address: 0xF640 to 0xF64B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_UD_RIGHT_x These 12 registers store the 192 user data bits decoded from the right channel of the S/PDIF input stream on the ADAU1452 and the ADAU1451. Table 141. Bit Descriptions for SPDIF_RX_UD_RIGHT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_RX_UD_RIGHT Not applicable S/PDIF receiver user data bits (right). 0x0000 R S/PDIF Receiver Validity Bits (Left) Register Address: 0xF650 to 0xF65B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_VB_LEFT_x These 12 registers store the 192 validity bits decoded from the left channel of the S/PDIF input stream on the ADAU1452 and the ADAU1451. Table 142. Bit Descriptions for SPDIF_RX_VB_LEFT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_RX_VB_LEFT Not applicable S/PDIF receiver validity bits (left). 0x0000 R S/PDIF Receiver Validity Bits (Right) Register Address: 0xF660 to 0xF66B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_VB_RIGHT_x These 12 registers store the 192 validity bits decoded from the left channel of the S/PDIF input stream on the ADAU1452 and the ADAU1451. Table 143. Bit Descriptions for SPDIF_RX_VB_RIGHT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_RX_VB_RIGHT Not applicable S/PDIF receiver validity bits (right). 0x0000 R Rev. D | Page 166 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 S/PDIF Receiver Parity Bits (Left) Register Address: 0xF670 to 0xF67B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_PB_LEFT_x These 12 registers store the 192 parity bits decoded from the left channel of the S/PDIF input stream on the ADAU1452 and the ADAU1451. Table 144. Bit Descriptions for SPDIF_RX_PB_LEFT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_RX_PB_LEFT Not applicable S/PDIF receiver parity bits (left). 0x0000 R S/PDIF Receiver Parity Bits (Right) Register Address: 0xF680 to 0xF68B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_RX_PB_RIGHT_x These 12 registers store the 192 parity bits decoded from the right channel of the S/PDIF input stream on the ADAU1452 and ADAU1451. Table 145. Bit Descriptions for SPDIF_RX_PB_RIGHT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_RX_PB_RIGHT Not applicable S/PDIF receiver parity bits (right). 0x0000 R S/PDIF Transmitter Enable Register Address: 0xF690, Reset: 0x0000, Name: SPDIF_TX_EN This register enables or disables the S/PDIF transmitter on the ADAU1452 and the ADAU1451. When the transmitter is disabled, it outputs a constant stream of zero data. When the S/PDIF transmitter is disabled, it still consumes power. To power down the S/PDIF transmitter for the purpose of power savings, set Register 0xF051 (POWER_ENABLE1), Bit 2 (TX_PWR) = 0b0. Table 146. Bit Descriptions for SPDIF_TX_EN Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 TXEN S/PDIF transmitter output enable. 0x0 RW 0 Disabled. 1 Enabled. 1 N/A means not applicable. Rev. D | Page 167 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet S/PDIF Transmitter Control Register Address: 0xF691, Reset: 0x0000, Name: SPDIF_TX_CTRL This register controls the length of the audio data-words output by the S/PDIF transmitter on the ADAU1452 and the ADAU1451. The maximum word length is 24 bits. If a shorter word length is selected using Bits[1:0] (TX_LENGTHCTRL), the extraneous bits are truncated, starting with the LSB. If Bits[1:0] (TX_LENGTHCTRL) = 0b11, the decoded channel status bits on the input stream of the S/PDIF receiver automatically set the word length on the S/PDIF transmitter. Table 147. Bit Descriptions for SPDIF_TX_CTRL Bits Bit Name Settings1 Description Reset Access [15:2] RESERVED N/A Reserved. 0x0 RW [1:0] TX_LENGTHCTRL S/PDIF transmitter audio word length. 0x0 RW 00 24 bits. 01 20 bits. 10 16 bits. 11 Automatic (determined by channel status bits detected in the S/PDIF input stream). 1 N/A means not applicable. S/PDIF Transmitter Auxiliary Bits Source Select Register Address: 0xF69F, Reset: 0x0000, Name: SPDIF_TX_AUXBIT_SOURCE This register configures whether the encoded nonaudio data bits in the output data stream of the S/PDIF transmitter on the ADAU1452 and the ADAU1451 are copied directly from the S/PDIF receiver or set manually using the corresponding control registers. If the data is configured manually, all channel status, parity, user data, and validity bits can be manually set using the following registers: SPDIF_TX_CS_LEFT_x, SPDIF_TX_CS_RIGHT_x, SPDIF_TX_UD_LEFT_x, SPDIF_TX_UD_RIGHT_x, SPDIF_TX_VB_LEFT_x, SPDIF_TX_VB_RIGHT_x, SPDIF_TX_PB_LEFT_x, and SPDIF_TX_PB_RIGHT_x. Table 148. Bit Descriptions for SPDIF_TX_AUXBIT_SOURCE Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 TX_AUXBITS_SOURCE Auxiliary bits source. 0x0 RW 0 Source from register map (user programmable). 1 Source from S/PDIF receiver (derived from input data stream). 1 N/A means not applicable. Rev. D | Page 168 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 S/PDIF Transmitter Channel Status Bits (Left) Register Address: 0xF6A0 to 0xF6AB (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_CS_LEFT_x These 12 registers allow the 192 channel status bits encoded on the left channel of the output data stream of the S/PDIF transmitter on the ADAU1452 and the ADAU1451 to be manually configured. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F (SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 149. Bit Descriptions for SPDIF_TX_CS_LEFT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_TX_CS_LEFT Not applicable S/PDIF transmitter channel status bits (left). 0x0000 RW S/PDIF Transmitter Channel Status Bits (Right) Register Address: 0xF6B0 to 0xF6BB (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_CS_RIGHT_x These 12 registers allow the 192 channel status bits encoded on the right channel of the output data stream of the S/PDIF transmitter on the ADAU1452 and the ADAU1451 to be manually configured. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F (SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 150. Bit Descriptions for SPDIF_TX_CS_RIGHT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_TX_CS_RIGHT Not applicable S/PDIF receiver channel status bits (right). 0x0000 RW S/PDIF Transmitter User Data Bits (Left) Register Address: 0xF6C0 to 0xF6CB (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_UD_LEFT_x These 12 registers allow the 192 user data bits encoded on the left channel of the output data stream of the S/PDIF transmitter on the ADAU1452 and the ADAU1451 to be manually configured. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F (SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 151. Bit Descriptions for SPDIF_TX_UD_LEFT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_TX_UD_LEFT Not applicable S/PDIF transmitter user data bits (left). 0x0000 RW Rev. D | Page 169 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet S/PDIF Transmitter User Data Bits (Right) Register Address: 0xF6D0 to 0xF6DB (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_UD_RIGHT_x These 12 registers allow the 192 user data bits encoded on the right channel of the output data stream of the S/PDIF transmitter on the ADAU1452 and the ADAU1451 to be manually configured. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F (SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 152. Bit Descriptions for SPDIF_TX_UD_RIGHT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_TX_UD_RIGHT Not applicable S/PDIF transmitter user data bits (right). 0x0000 RW S/PDIF Transmitter Validity Bits (Left) Register Address: 0xF6E0 to 0xF6EB (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_VB_LEFT_x These 12 registers allow the 192 validity bits encoded on the left channel of the output data stream of the S/PDIF transmitter on the ADAU1452 and the ADAU1451 to be manually configured. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F (SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 153. Bit Descriptions for SPDIF_TX_VB_LEFT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_TX_VB_LEFT Not applicable S/PDIF transmitter validity bits (left). 0x0000 RW S/PDIF Transmitter Validity Bits (Right) Register Address: 0xF6F0 to 0xF6FB (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_VB_RIGHT_x These 12 registers allow the 192 validity bits encoded on the right channel of the output data stream of the S/PDIF transmitter on the ADAU1452 and the ADAU1451 to be manually configured. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F (SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 154. Bit Descriptions for SPDIF_TX_VB_RIGHT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_TX_VB_RIGHT Not applicable S/PDIF transmitter validity bits (right). 0x0000 RW Rev. D | Page 170 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 S/PDIF Transmitter Parity Bits (Left) Register Address: 0xF700 to Address 0xF70B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_PB_LEFT_x These 12 registers allow the 192 parity bits encoded on the left channel of the output data stream of the S/PDIF transmitter on the ADAU1452 and the ADAU1451 to be manually configured. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F (SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 155. Bit Descriptions for SPDIF_TX_PB_LEFT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_TX_PB_LEFT Not applicable S/PDIF transmitter parity bits (left). 0x0000 RW S/PDIF Transmitter Parity Bits (Right) Register Address: 0xF710 to Address 0xF71B (Increments of 0x1), Reset: 0x0000, Name: SPDIF_TX_PB_RIGHT_x These 12 registers allow the 192 parity bits encoded on the right channel of the output data stream of the S/PDIF transmitter on the ADAU1452 and the ADAU1451 to be manually configured. For these bits to be output properly on the S/PDIF transmitter, Register 0xF69F (SPDIF_TX_AUXBIT_SOURCE), Bit 0 (TX_AUXBITS_SOURCE), must be set to 0b0. Table 156. Bit Descriptions for SPDIF_TX_PB_RIGHT_x Bits Bit Name Settings Description Reset Access [15:0] SPDIF_TX_PB_RIGHT Not applicable S/PDIF transmitter parity bits (right). 0x0000 RW Rev. D | Page 171 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet HARDWARE INTERFACING REGISTERS BCLK Input Pins Drive Strength and Slew Rate Register Address: 0xF780 to 0xF783 (Increments of 0x1), Reset: 0x0018, Name: BCLK_INx_PIN These registers configure the drive strength, slew rate, and pull resistors for the BCLK_INx pins. Register 0xF780 corresponds to BCLK_IN0, Register 0xF781 corresponds to BCLK_IN1, Register 0xF782 corresponds to BCLK_IN2, and Register 0xF783 corresponds to BCLK_IN3. Table 157. Bit Descriptions for BCLK_INx_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 BCLK_IN_PULL BCLK_INx pull-down. 0x1 RW 0 Pull-down disabled. 1 Pull-down enabled. [3:2] BCLK_IN_SLEW BCLK_INx slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] BCLK_IN_DRIVE BCLK_INx drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 172 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 BCLK Output Pins Drive Strength and Slew Rate Register Address: 0xF784 to 0xF787 (Increments of 0x1), Reset: 0x0018, Name: BCLK_OUTx_PIN These registers configure the drive strength, slew rate, and pull resistors for the BCLK_OUTx pins. Register 0xF784 corresponds to BCLK_OUT0, Register 0xF785 corresponds to BCLK_OUT1, Register 0xF786 corresponds to BCLK_OUT2, and Register 0xF787 corresponds to BCLK_OUT3. Table 158. Bit Descriptions for BCLK_OUTx_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 BCLK_OUT_PULL BCLK_OUTx pull-down. 0x1 RW 0 Pull-down disabled. 1 Pull-down enabled. [3:2] BCLK_OUT_SLEW BCLK_OUTx slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] BCLK_OUT_DRIVE BCLK_OUTx drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 173 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet LRCLK Input Pins Drive Strength and Slew Rate Register Address: 0xF788 to 0xF78B (Increments of 0x1), Reset: 0x0018, Name: LRCLK_INx_PIN These registers configure the drive strength, slew rate, and pull resistors for the LRCLK_INx pins. Register 0xF788 corresponds to LRCLK_IN0/MP10, Register 0xF789 corresponds to LRCLK_IN1/MP11, Register 0xF78A corresponds to LRCLK_IN2/MP12, and Register 0xF78B corresponds to LRCLK_IN3/MP13. Table 159. Bit Descriptions for LRCLK_INx_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 LRCLK_IN_PULL LRCLK_INx pull-down. 0x1 RW 0 Pull-down disabled. 1 Pull-down enabled. [3:2] LRCLK_IN_SLEW LRCLK_INx slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] LRCLK_IN_DRIVE LRCLK_INx drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 174 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 LRCLK Output Pins Drive Strength and Slew Rate Register Address: 0xF78C to 0xF78F (Increments of 0x1), Reset: 0x0018, Name: LRCLK_OUTx_PIN These registers configure the drive strength, slew rate, and pull resistors for the LRCLK_OUTx pins. Register 0xF78C corresponds to LRCLK_OUT0/MP4, Register 0xF78D corresponds to LRCLK_OUT1/MP5, Register 0xF78E corresponds to LRCLK_OUT2/MP8, and Register 0xF78F corresponds to LRCLK_OUT3/MP9. Table 160. Bit Descriptions for LRCLK_OUTx_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 LRCLK_OUT_PULL LRCLK_OUTx pull-down. 0x1 RW 0 Pull-down disabled. 1 Pull-down enabled. [3:2] LRCLK_OUT_SLEW LRCLK_OUTx slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] LRCLK_OUT_DRIVE LRCLK_OUTx drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 175 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet SDATA Input Pins Drive Strength and Slew Rate Register Address: 0xF790 to 0xF793 (Increments of 0x1), Reset: 0x0018, Name: SDATA_INx_PIN These registers configure the drive strength, slew rate, and pull resistors for the SDATA_INx pins. Register 0xF790 corresponds to SDATA_IN0, Register 0xF791 corresponds to SDATA_IN1, Register 0xF792 corresponds to SDATA_IN2, and Register 0xF793 corresponds to SDATA_IN3. Table 161. Bit Descriptions for SDATA_INx_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 SDATA_IN_PULL SDATA_INx pull-down. 0x1 RW 0 Pull-down disabled. 1 Pull-down enabled. [3:2] SDATA_IN_SLEW SDATA_INx slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] SDATA_IN_DRIVE SDATA_INx drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 176 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 SDATA Output Pins Drive Strength and Slew Rate Register Address: 0xF794 to 0xF797 (Increments of 0x1), Reset: 0x0008, Name: SDATA_OUTx_PIN These registers configure the drive strength, slew rate, and pull resistors for the SDATA_OUTx pins. Register 0xF794 corresponds to SDATA_OUT0, Register 0xF795 corresponds to SDATA_OUT1, Register 0xF796 corresponds to SDATA_OUT2, and Register 0xF797 corresponds to SDATA_OUT3. Table 162. Bit Descriptions for SDATA_OUTx_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 SDATA_OUT_PULL SDATA_OUTx pull-down. 0x0 RW 0 Pull-down disabled. 1 Pull-down enabled. [3:2] SDATA_OUT_SLEW SDATA_OUTx slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] SDATA_OUT_DRIVE SDATA_OUTx drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 177 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet S/PDIF Transmitter Pin Drive Strength and Slew Rate Register Address: 0xF798, Reset: 0x0008, Name: SPDIF_TX_PIN This register configures the drive strength, slew rate, and pull resistors for the SPDIFOUT pin on the ADAU1452 and theADAU1451. Table 163. Bit Descriptions for SPDIF_TX_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 SPDIF_TX_PULL SPDIFOUT pull-down. 0x0 RW 0 Pull-down disabled. 1 Pull-down enabled. [3:2] SPDIF_TX_SLEW SPDIFOUT slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] SPDIF_TX_DRIVE SPDIFOUT drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 178 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 SCLK/SCL Pin Drive Strength and Slew Rate Register Address: 0xF799, Reset: 0x0008, Name: SCLK_SCL_PIN This register configures the drive strength, slew rate, and pull resistors for the SCLK/SCL pin. Table 164. Bit Descriptions for SCLK_SCL_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 SCLK_SCL_PULL SCLK/SCL pull-up. 0x0 RW 0 Pull-up disabled. 1 Pull-up enabled. [3:2] SCLK_SCL_SLEW SCLK/SCL slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] SCLK_SCL_DRIVE SCLK/SCL drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 179 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet MISO/SDA Pin Drive Strength and Slew Rate Register Address: 0xF79A, Reset: 0x0008, Name: MISO_SDA_PIN This register configures the drive strength, slew rate, and pull resistors for the MISO/SDA pin. Table 165. Bit Descriptions for MISO_SDA_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 MISO_SDA_PULL MISO/SDA pull-up. 0x0 RW 0 Pull-up disabled. 1 Pull-up enabled. [3:2] MISO_SDA_SLEW MISO/SDA slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] MISO_SDA_DRIVE MISO/SDA drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 180 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 SS/ADDR0 Pin Drive Strength and Slew Rate Register Address: 0xF79B, Reset: 0x0018, Name: SS_PIN This register configures the drive strength, slew rate, and pull resistors for the SS/ADDR0 pin. Table 166. Bit Descriptions for SS_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 SS_PULL SS/ADDR0 pull-up. 0x1 RW 0 Pull-up disabled. 1 Pull-up enabled. [3:2] SS_SLEW SS/ADDR0 slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] SS_DRIVE SS/ADDR0 drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 181 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet MOSI/ADDR1 Pin Drive Strength and Slew Rate Register Address: 0xF79C, Reset: 0x0018, Name: MOSI_ADDR1_PIN This register configures the drive strength, slew rate, and pull resistors for the MOSI/ADDR1 pin. Table 167. Bit Descriptions for MOSI_ADDR1_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 MOSI_ADDR1_PULL MOSI/ADDR1 pull-up. 0x1 RW 0 Pull-up disabled. 1 Pull-up enabled. [3:2] MOSI_ADDR1_SLEW MOSI/ADDR1 slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] MOSI_ADDR1_DRIVE MOSI/ADDR1 drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 182 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 SCL_M/SCLK_M/MP2 Pin Drive Strength and Slew Rate Register Address: 0xF79D, Reset: 0x0008, Name: SCLK_SCL_M_PIN This register configures the drive strength, slew rate, and pull resistors for the SCL_M/SCLK_M/MP2 pin. Table 168. Bit Descriptions for SCLK_SCL_M_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 SCLK_SCL_M_PULL SCL_M/SCLK_M/MP2 pull-up. 0x0 RW 0 Pull-up disabled. 1 Pull-up enabled. [3:2] SCLK_SCL_M_SLEW SCL_M/SCLK_M/MP2 slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] SCLK_SCL_M_DRIVE SCL_M/SCLK_M/MP2 drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 183 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet SDA_M/MISO_M/MP3 Pin Drive Strength and Slew Rate Register Address: 0xF79E, Reset: 0x0008, Name: MISO_SDA_M_PIN This register configures the drive strength, slew rate, and pull resistors for the SDA_M/MISO_M/MP3 pin. Table 169. Bit Descriptions for MISO_SDA_M_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 MISO_SDA_M_PULL SDA_M/MISO_M/MP3 pull-up. 0x0 RW 0 Pull-up disabled. 1 Pull-up enabled. [3:2] MISO_SDA_M_SLEW SDA_M/MISO_M/MP3 slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] MISO_SDA_M_DRIVE SDA_M/MISO_M/MP3 drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 184 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 SS_M/MP0 Pin Drive Strength and Slew Rate Register Address: 0xF79F, Reset: 0x0018, Name: SS_M_PIN This register configures the drive strength, slew rate, and pull resistors for the SS_M/MP0 pin. Table 170. Bit Descriptions for SS_M_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 SS_M_PULL SS_M/MP0 pull-up. 0x1 RW 0 Pull-up disabled. 1 Pull-up enabled. [3:2] SS_M_SLEW SS_M/MP0 slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] SS_M_DRIVE SS_M/MP0 drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 185 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet MOSI_M/MP1 Pin Drive Strength and Slew Rate Register Address: 0xF7A0, Reset: 0x0018, Name: MOSI_M_PIN This register configures the drive strength, slew rate, and pull resistors for the MOSI_M/MP1 pin. Table 171. Bit Descriptions for MOSI_M_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 MOSI_M_PULL MOSI_M/MP1 pull-up. 0x1 RW 0 Pull-up disabled. 1 Pull-up enabled. [3:2] MOSI_M_SLEW MOSI_M/MP1 slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] MOSI_M_DRIVE MOSI_M/MP1 drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 186 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 MP6 Pin Drive Strength and Slew Rate Register Address: 0xF7A1, Reset: 0x0018, Name: MP6_PIN This register configures the drive strength, slew rate, and pull resistors for the MP6 pin. Table 172. Bit Descriptions for MP6_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 MP6_PULL MP6 pull-down. 0x1 RW 0 Pull-down disabled. 1 Pull-down enabled. [3:2] MP6_SLEW MP6 slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] MP6_DRIVE MP6 drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 187 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet MP7 Pin Drive Strength and Slew Rate Register Address: 0xF7A2, Reset: 0x0018, Name: MP7_PIN This register configures the drive strength, slew rate, and pull resistors for the MP7 pin. Table 173. Bit Descriptions for MP7_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 MP7_PULL MP7 pull-down. 0x1 RW 0 Pull-down disabled. 1 Pull-down enabled. [3:2] MP7_SLEW MP7 slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] MP7_DRIVE MP7 drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 188 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 CLKOUT Pin Drive Strength and Slew Rate Register Address: 0xF7A3, Reset: 0x0008, Name: CLKOUT_PIN This register configures the drive strength, slew rate, and pull resistors for the CLKOUT pin. Table 174. Bit Descriptions for CLKOUT_PIN Bits Bit Name Settings1 Description Reset Access [15:5] RESERVED N/A Reserved. 0x0 RW 4 CLKOUT_PULL CLKOUT pull-down. 0x0 RW 0 Pull-down disabled. 1 Pull-down enabled. [3:2] CLKOUT_SLEW CLKOUT slew rate. 0x2 RW 00 Slowest. 01 Slow. 10 Fast. 11 Fastest. [1:0] CLKOUT_DRIVE CLKOUT drive strength. 0x0 RW 00 Lowest. 01 Low. 10 High. 11 Highest. 1 N/A means not applicable. Rev. D | Page 189 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet SOFT RESET REGISTER Address: 0xF890, Reset: 0x0001, Name: SOFT_RESET SOFT_RESET provides the capability to reset all control registers in the device or put it into a state similar to a hardware reset, where the RESET pin is pulled low to ground. All control registers are reset to their default values, except for the PLL registers: Register 0xF000 (PLL_CTRL0), Register 0xF001 (PLL_CTRL1), Register 0xF002 (PLL_CLK_SRC), Register 0xF003 (PLL_ENABLE), Register 0xF004 (PLL_LOCK), Register 0xF005 (MCLK_OUT), and Register 0xF006 (PLL_WATCHDOG), as well as registers related to the panic manager. The I2C and SPI slave ports remain operational, and the user can write new values to the PLL registers when the soft reset is active. If SPI slave mode is enabled, the device remains in SPI slave mode during and after the soft reset state. To reset the device to I2C slave mode, the device must undergo a hardware reset by pulling the RESET pin low to ground. Bit 0 (SOFT_RESET) is active low, meaning that setting this bit to 0b1 enables normal operation and setting it to 0b0 enables the soft reset state. Table 175. Bit Descriptions for SOFT_RESET Bits Bit Name Settings1 Description Reset Access [15:1] RESERVED N/A Reserved. 0x0 RW 0 SOFT_RESET Soft reset. 0x1 RW 0 Soft reset enabled. 1 Soft reset disabled; normal operation. 1 N/A means not applicable. Rev. D | Page 190 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 APPLICATIONS INFORMATION PCB DESIGN CONSIDERATIONS Component Placement A solid ground plane is a necessity for maintaining signal integrity Place all 100 nF bypass capacitors, which are recommended for and minimizing EMI radiation. If the PCB has two ground planes, every analog, digital, and PLL power ground pair, as near as they can be stitched together using vias that are spread evenly possible to the ADAU1452/ADAU1451/ADAU1450. Bypass each throughout the board. of the AVDD, DVDD, PVDD, and IOVDD supply signals on the board with an additional single bulk capacitor (10 μF to 47 μF). Power Supply Bypass Capacitors Note that for the DVDD bulk capacitor, an electrolytic or Bypass each power supply pin to its nearest appropriate ground ceramic capacitor can be used. If a ceramic capacitor is used pin with a single 100 nF capacitor and, optionally, with an addi- along with the internal voltage regulator, a 0.5 Ω resistor must tional 10 nF capacitor in parallel. Make the connections to each be added in series with the capacitor. See the Voltage Regulator side of the capacitor as short as possible, and keep the trace on section for more details. a single layer with no vias. For maximum effectiveness, place the Keep all traces in the crystal resonator circuit (see Figure 15) as capacitor either equidistant from the power and ground pins or, short as possible to minimize stray capacitance. Do not connect when equidistant placement is not possible, slightly nearer to any long board traces to the crystal oscillator circuit components the power pin (see Figure 81). Establish the thermal connections because such traces can affect crystal startup and operation. to the planes on the far side of the capacitor. Grounding POWER GROUND Use a single ground plane in the application layout. Place all components in an analog signal path away from digital signals. Exposed Pad PCB Design CAPACITOR The device package includes an exposed pad for improved heat dissipation. When designing a board for such a package, give special consideration to the following: TO POWER  Place a copper layer, equal in size to the exposed pad, on all TO GROUND 11486-087 llaayyeerrss otof tah de ebdoiacradte, dfr ocomp ptoepr tboo barodtt olamye. rC (osneen eFcigt uthree c8o4p).p er Figure 81. Recommended Power Supply Bypass Capacitor Layout Typically, a single 100 nF capacitor for each power ground pin TOP pair is sufficient. However, if there is excessive high frequency GROUND POWER n(soeies eF iignu trhee 8 s2y)s.t Ienm t,h uiss ec aasne ,a dpldaictieo tnhael 1100 nnFF ccaappaacciittoorr bine tpwaereanll el VIAS COPPERSQUAREBSOTTOM 11486-090 the devices and the 100 nF capacitor, and establish the thermal Figure 84. Exposed Pad Layout Example—Side View connections on the far side of the 100 nF capacitor.  Place vias such that all layers of copper are connected, VIA TO VIA TO allowing efficient heat and energy conductivity. See Figure 85, POWER PLANE GROUND PLANE which shows 49 vias arranged in a 7 × 7 grid in the pad 100nF area. 10nF DVDD DGND 11486-088 Figure 82. Layout for Multiple Power Supply Bypass Capacitors Tuose p ar o1v0i dμeF ac acpuarcreitnotr rfeosre ervacohir ninam caesde soufp spuldyd (eDnV cDurDre, nAtV sDpiDke, s, 11486-091 PVDD, and IOVDD) as shown in Figure 83. Figure 85. Exposed Pad Layout Example—Top View BULK BYPASS CAPACITORS PLL Filter 3.3V AVDD PVDD IOVDD DVDD To minimize jitter, connect the single resistor and two capacitors + + + + in the PLL filter to the PLLFILT and PVDD pins with short traces. 10µF 10µF 10µF 10µF 11486-089 Figure 83. Bulk Capacitor Schematic Rev. D | Page 191 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet Power Supply Isolation with Ferrite Beads EOS/ESD Protection Ferrite beads can be used for supply isolation. When using Although the ADAU1452/ADAU1451/ADAU1450 has robust ferrite beads, always place the beads outside the local high internal protection circuitry against overvoltages and electrostatic frequency decoupling capacitors, as shown in Figure 86. If the discharge, an external transient voltage suppressor (TVS) is ferrite beads are placed between the supply pin and the decoupling recommended for all systems to prevent damage to the IC. For capacitor, high frequency noise is reflected back into the IC examples, see the AN-311 Application Note. because there is no suitable return path to ground. As a result, EMI increases, creating noisy supplies. DGND IOVDD VDRIVE DVDD DGND 1 2 3 71 72 10nF 100nF (BYPASS) (BYPASS) 1kΩ 100nF (BYPASS) FERRITE MAIN BEAD 0.5Ω IF 10µF CERAMIC 3.3V SUPPLY RESOERR 4V1.O07µµIRFF + IO3V.3DVD D1V.2DVD RESERV1O0µIRF + 11486-092 Figure 86. Ferrite Bead Power Supply Isolation Circuit Example TYPICAL APPLICATIONS BLOCK DIAGRAM ANALOG MICROPHONES ADAU1977 HUENAITD F Rx MICRAODPCHONE PDI CLASS AB/D I2C SPI S 4-CHANNEL AMPLIFIER SPEAKERS ADAU1452/ 0 ADAU1451/ AD1938/ TRANCSACNEIVER AN ADAU1450 AD1939 CLASS AB/D C CODEC 4-CHANNEL 8-CHANNEL AMPLIFIER us DAC B AN MICRO- C CONTROLLER A DI E M PDM TI SPI SPI PDM MICROPHONES L U M eFLASH 11486-095 Figure 87. Automotive Infotainment Amplifier Block Diagram Rev. D | Page 192 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 EXAMPLE PCB LAYOUT The digital (DVDD) supply pins each have up to three local bypass capacitors, as follows: Several external components, such as capacitors, resistors, and a transistor, are required for proper operation of the device. • The 10 nF bypass capacitor, placed closest to the pin, acts An example of the connection and layout of these components as a return path for very high frequency currents resulting is shown in Figure 88. Thick black lines represent traces, gray from the nominal 294 MHz operating frequency of the rectangles represent components, and white circles with a thick DSP core. black ring represent thermal via connections to power or ground • The 100 nF bypass capacitor acts as a return path for high planes. If a 1.2 V supply is available in the system, the transistor frequency currents from the DSP and other digital circuitry. circuit (including the associated 1 kΩ resistor) can be removed, • The 1 μF bypass capacitor is required to provide a local and 1.2 V can be connected directly to the DVDD power net, current supply for sudden spikes in current that occur at with the VDRIVE pin left floating. the beginning of each audio frame when the DSP core The analog (AVDD), PLL (PVDD), and interface (IOVDD) switches from idle mode to operating mode. supply pins each have local 100 nF bypass capacitors to provide • Of these bypass capacitors, the most important is the 100 nF high frequency return currents with a short path to ground. bypass capacitor, which is required for proper power supply bypassing. The 10 nF can optionally be used to improve the EMI/EMC performance of the system. The 10 µF capacitor for the DVDD can be an electrolytic type. If a ceramic 10 µF capacitor is used, a 0.5 Ω series resistor must be added to compensate for the missing ESR of the electrolytic capacitor. 10μF DVDD 10μF IOVDD CURRENT CURRENT 100nF RESERVOIR RESERVOIR 100nF BYPASS 10μF 10μF 10nF 1B0YnPFASS BY1P0A0SnSF 100nF 100nF S S 0.5Ω C TD2805T4 CE 1kΩ BYP100nFASS DIOGVNDDDDGND DVDD IOVDD DGNDDVDD 10nF10nFBYPAS100nF100nFBYPAS S PIN1 B VDRIVE DVDD REGULATOR 10μF 100nF AAVGDNDD 10μF DVDDCURRENTRESERVOIR 100nFBYPASS AAADDDAAAUUU111444555210// (TOP VIEW) 10μF PVDD CURRENT RESERVOIR 100nF BYPASS 10μF 100nF PGND F 150pF PVDD n 6 5. 4.3kΩ PLLFILT B1Y0P0AnSFS PLL LOOP FILTER 100nF IDOGVNDDDD D D DIDOGVNDDD 100nF N D D N 100nF G V V G BYPASS D D D D 10nF 1B0YnPFASS 10nF 1B0YnPFASS 100nF 1B0Y0PnAFSS 100nF 1B0Y0PnAFSS 11486-093 Figure 88. Supporting Component Placement and Layout Rev. D | Page 193 of 195

ADAU1452/ADAU1451/ADAU1450 Data Sheet PCB MANUFACTURING GUIDELINES The soldering profile in Figure 89 is recommended for the LFCSP package. See the AN-772 Application Note for more information about PCB manufacturing guidelines. RAMP UP 60 SETCOONDS 3°C/SECOND MAX 150 SECONDS 260°C ± 5°C 217°C C) E (° 150°C TO 200°C R U AT RAMP DOWN R 6°C/SECOND MAX E P M E T 60 SETCOONDS TIME (Second) 180 SECONDS 20 SECONDS 480 SECONDS MAX 40 SETCOONDS 11486-094 Figure 89. Soldering Profile 0.30mm × 0.55mm 10mm ANALOG DEVICES LFCSP_VQ (CP-72-6) REV A 8.5mm 10mm 0.5mm 0.55mm × 0.30mm 0.5mm 5.25mm 11486-097 Figure 90. PCB Decal Dimensions Rev. D | Page 194 of 195

Data Sheet ADAU1452/ADAU1451/ADAU1450 OUTLINE DIMENSIONS 10.10 0.60 0.30 10.00 SQ 0.60 0.42 0.23 9.90 0.42 0.24 0.18 PIN 1 0.24 5455 721 INDICATOR PIN 1 INDICATOR 9.85 0.50 9.75 SQ BSC 5.45 9.65 EXPOSED 5.30 SQ PAD 5.15 0.50 0.40 18 TOP VIEW 0.30 3367 BOTTOM VIEW 19 0.25 MIN 1.00 12° MAX 0.80 MAX 8.50 REF 0.65 TYP 0.85 0.80 0.05 MAX FOR PROPER CONNECTION OF 0.02 NOM THE EXPOSED PAD, REFER TO COPLANARITY THE PIN CONFIGURATION AND SEPALTAINNGE COMPLIANT TO0 .J2E0D REECF STAND0.A0R8DS MO-220-VNND-4 FSUENCCTITOIONN O DFE TSHCISR IDPATTIOAN SSHEET. 06-25-2012-C Figure 91. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm × 10 mm Body, Very Thin Quad (CP-72-6) Dimensions shown in millimeters ORDERING GUIDE Temperature Package Model1, 2 Range Package Description Option ADAU1452WBCPZ −40°C to +105°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-72-6 ADAU1452WBCPZ-RL −40°C to +105°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 13” Tape and Reel CP-72-6 ADAU1452WBCPZ150 −40°C to +105°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-72-6 ADAU1452WBCPZ150RL −40°C to +105°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 13” Tape and Reel CP-72-6 ADAU1451WBCPZ −40°C to +105°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-72-6 ADAU1451WBCPZ-RL −40°C to +105°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 13” Tape and Reel CP-72-6 ADAU1450WBCPZ −40°C to +105°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-72-6 ADAU1450WBCPZ-RL −40°C to +105°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 13” Tape and Reel CP-72-6 ADAU1452KCPZ 0°C to +70°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-72-6 ADAU1452KCPZRL 0°C to +70°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 13” Tape and Reel CP-72-6 EVAL-ADAU1452MINIZ Evaluation Board 1 Z = RoHS compliant part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADAU1452W/ADAU1452W150/ADAU1451W/ADAU1450W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2013–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11486-0-7/18(D) Rev. D | Page 195 of 195

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-ADAU1452MINIZ ADAU1452WBCPZ ADAU1450WBCPZ ADAU1451WBCPZ ADAU1452WBCPZ-RL ADAU1450WBCPZ-RL ADAU1451WBCPZ-RL ADAU1452KCPZ ADAU1452KCPZRL