ESDAXLC6-1BT2 Single-line bidirectional ESD protection for high speed interface Datasheet - production data Features  Bidirectional device  Multiple ESD strike sustainability  Extra low diode capacitance: 0.4 pF  Low leakage current  Thin SOD882 package - 0402 size compatible  Ultra small: 0.6 mm2  RoHS compliant SOD882T Complies with the following standards: ESDAXLC6-1BT2  IEC 61000-4-2 level 4 – 15 kV (air discharge) Figure 1. Functional diagram (top view) – 8 kV (contact discharge) Pin1 Applications Where transient overvoltage protection in ESD sensitive equipment is required, such as:  Smartphones, mobile phone and accessories  Tablets, netbooks and notebooks  Portable multimedia players and accessories  Digital cameras and camcorders  Communication systems Description The ESDAXLC6-1BT2 is a bidirectional single line TVS diode designed to protect the data lines or other I/O ports against ESD transients. The device is ideal for applications where both reduced line capacitance and board space saving are required. August 2013 DocID023680 Rev 2 1/10 This is information on a product in full production. www.st.com

Characteristics ESDAXLC6-1BT2 1 Characteristics T able 1. Absolute maximum ratings (T = 25 °C) amb Symbol Parameter Value Unit Peak pulse voltage: V IEC 61000-4-2 contact discharge ± 16 kV PP IEC 61000-4-2 air discharge ± 25 P Peak pulse power (8/20 µs) 40 W PP I Peak pulse current (8/20 µs) 1.3 A PP T Operating junction temperature range - 40 to +150 °C j T Storage temperature range - 65 to +150 °C stg T Maximum lead temperature for soldering during 10 s 260 °C L Note: For a surge greater than the maximum values, the diode will fail in short-circuit Figure 2. Electrical characteristics (definitions) Symbol Parameter V = Breakdown voltage BR V = Stand-off voltage RM I = Leakage current @V RM RM I = Peak pulse current PP R = Dynamic impedance d αT = Voltage temperature coefficient C = Parasite capacitance Table 2. Electrical characteristics (values, T = 25 °C) amb Symbol Test condition Min. Typ. Max. Unit V I = 1 mA 6 V BR R I V = 3 V 70 nA RM RM V I = 1 A, 8/20 µA 17 V CL PP C F= (200 MHz- 3000 MHz), V = 0 V 0.4 0.5 pF line R 2/10 DocID023680 Rev 2

ESDAXLC6-1BT2 Characteristics Figure 3. Leakage current versus junction Figure 4. Junction capacitance versus applied temperature (typical values) voltage (typical values) IR(nA) C(pF) 10 0.8 0.7 0.6 1 0.5 0.4 0.3 0.1 0.2 Tj(°C) 0.1 VR(V) 0.01 0 25 50 75 100 125 150 0 1 2 3 4 5 Figure 5. ESD response to IEC 61000-4-2 Figure 6. ESD response to IEC 61000-4-2 (+8 kV contact discharge) (-8 kV contact discharge) 50V/div 50V/div 4123VVVVCCCCLLLL::::Pcccllleaaaammmkppp ciiinnnlagggm vvvpoooilllntttaaagggg eeev oaaaltttta 361g000e 0nn ssns 3-25V 4-18V 2-36V 1156V 2236V 330V 415V 1-159V 4123VVVVCCCCLLLL::::Pcccllleaaaammmkppp ciiinnnlagggm vvvpoooilllntttaaagggg eeev oaaaltttta 361g000e 0nn ssns 20 ns/div 20 ns/div Figure 7. Attenuation versus frequency S21(dB) 0.00 -1.00 dB -2.00 -3.00 -4.00 -5.00 -6.00 F(Hz) -7.00 100.0M 300.0M 1.0G 3.0G 10.0G 30.0G ESDAXLC6--1BT2 DocID023680 Rev 2 3/10 10

Package information ESDAXLC6-1BT2 2 Package information  Epoxy meets UL94, V0  Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 8. SOD882 thin dimension definitions L1 L2 b1 b2 PIN # 1 ID e A A1 E D Table 3. SOD882 thin dimension values Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.30 0.40 0.012 0.016 A1 0.00 0.05 0.000 0.002 b1 0.45 0.50 0.55 0.018 0.020 0.022 b2 0.45 0.50 0.55 0.018 0.020 0.022 D 0.55 0.60 0.65 0.022 0.024 0.026 E 0.95 1.00 1.05 0.037 0.039 0.041 e 0.60 0.65 0.70 0.024 0.026 0.028 L1 0.20 0.25 0.30 0.008 0.010 0.012 L2 0.20 0.25 0.30 0.008 0.010 0.012 4/10 DocID023680 Rev 2

ESDAXLC6-1BT2 Package information Figure 9. Footprint dimension in mm (inches) 0.55 0.55 (0.022) (0.022) 0.50 0.020 0.40 (0.016) Figure 10. Marking T Pin2 Pin 1 Note: Product marking may be rotated by multiples of 180° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 11. Tape and reel specifications Bar indicates Pin1 Ø 1.50 ± 0.1 1 2.0 ± 0.05 4.0 ± 0.1 0. ± 0.20 ± 0.2 5 7 1. 5 0. 5 0.3 / - 0.1 1.15 ± 3.5 ± 0.0 + 0 8. TywwxxzST TywwxxzST TywwxxzST TywwxxzST TywwxxzST TywwxxzST 0.70 ± 0.5 4.0 ± 0.1 0.47 ± 0.5 All dimensions are in mm User direction of unreeling DocID023680 Rev 2 5/10 10

Recommendation on PCB assembly ESDAXLC6-1BT2 3 Recommendation on PCB assembly 3.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 12. Stencil opening dimensions L T W b) General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = -----1,5 T LW Aspect Area = ----------------------------0,66 2TL+W 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c) Stencil opening for leads: Opening to footprint ratio is 90%. Figure 13. Recommended stencil window position Package footprint Leadfootprinton PCB 0.055 mm Leadfootprinton PCB Stencilwindow Stencilwindow position 0.39 mm position 0.45 mm 0.05 mm 0.05 mm 6/10 DocID023680 Rev 2

ESDAXLC6-1BT2 Recommendation on PCB assembly 3.2 Solder paste 1. Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste recommended. 3. Offers a high tack force to resist component displacement during PCB movement. 4. Use solder paste with fine particles: powder particle size 20-45 µm. 3.3 Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 3.4 PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. DocID023680 Rev 2 7/10 10

Recommendation on PCB assembly ESDAXLC6-1BT2 3.5 Reflow profile Figure 14. ST ECOPACK® recommended soldering reflow profile for PCB mounting 240-245 °C Temperature (°C) -2°C/s 250 2 - 3 °C/s 200 60sec (90max) -3°C/s 150 -6°C/s 100 0.9 °C/s 50 Time (s) 0 30 60 90 120 150 180 210 240 270 300 Note: Minimize air convection currents in the reflow oven to avoid component movement. Maximum soldering profile corresponds to the latest IPC/JEDEC J-STD-020. 8/10 DocID023680 Rev 2

ESDAXLC6-1BT2 Ordering information 4 Ordering information Figure 15. Ordering information scheme ESDA XLC 6 - 1B T2 ESDA array Extra low capacitance Breakdown voltage 6 = 6V min Direction B = Bidirectional Package T2 =Thin SOD882 (SOD882T) Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode ESDAXLC6-1BT2 T(1) SOD882T 0.8 mg 12000 Tape and reel 1. The marking can be rotated by multiples of 180° to differentiate assembly location 5 Revision history Table 5. Document revision history Date Revision Changes 04-Sep-2012 1 Initial release. 12-Aug-2013 2 Updated Figure4, Figure5, Figure6, Figure11 and Table4. DocID023680 Rev 2 9/10 10

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