ESDA6V1M6, ESDA6V1-5M6 4- and 5-line Transil™ arrays for ESD protection Features ■ High ESD protection level ■ High integration ■ Suitable for high density boards ■ 4 unidirectional Transil diodes Micro QFN package (ESDA6V1M6) ■ 5 unidirectional Transil diodes Figure 1. Functional diagram (ESDA6V1-5M6) ■ Breakdown Voltage V = 6.1 V min BR ESDA6V1M6 ■ High peak power dissipation: 100 Watts 8/20µs I/O1 1 6 I/O5 ■ Low leakage current < 500 nA GND 2 5 GND ■ Low diode capacitance (70 pF typ at 0 V) ■ Very small PCB area: 1.45 mm² I/O2 3 4 I/O3 ■ 500 microns pitch ■ Lead-free package ESDA6V1-5M6 Complies with the following standards: I/O1 1 6 I/O5 ■ IEC 61000-4-2 GND 2 5 I/O4 – 15 kV (air discharge) – 8 kV (contact discharge) I/O2 3 4 I/O3 ■ MIL STD 883G- Method 3015-7: class 3B – > 8 kV (human body model) Description Applications The ESDA6V1xxM6 are monolithic arrays Where transient overvoltage protection in ESD designed to protect up to 4 or 5 lines against ESD sensitive equipment is required, such as: transients. ■ Computers The device is ideal for applications where both reduced print circuit board space and power ■ Printers absorption capability are required. ■ Communication systems ■ Cellular phone handsets and accessories ■ Video equipment TM: Transil is a trademark of STMicroelectronics February 2008 Rev 4 1/11 www.st.com 11

Characteristics ESDA6V1M6, ESDA6V1-5M6 1 Characteristics T able 1. Absolute maximum ratings (T = 25 °C) amb Symbol Parameter Value Unit ESD IEC 61000-4-2, air discharge ±15 VPP ESD IEC 61000-4-2, contact discharge ±11 kV MIL STD 883G- Method 3015-7: class 3B, (human body model) 25 PPP Peak pulse power dissipation (8/20 µs)(1) Tj initial = Tamb 100 W Ipp Repetitive peak pulse current typical value (8/20 µs) 8 A Tj Junction temperature 125 °C Tstg Storage temperature range -55 to +150 °C Maximum lead temperature for soldering during 10 s at 5 mm for TL case 260 °C TOP Operating temperature range -40 to +125 °C 1. For a surge greater than the maximum values, the diode will fail in short-circuit. T able 2. Electrical characteristics (T = 25 °C) amb Symbol Parameter I VRM Stand-off voltage IF VBR Breakdown voltage VCL Clamping voltage VCLVBR VRM VF VVVVVV IRM Leakage current @ VRM IRM IR IPP Peak pulse current Slope= 1/Rd αT Voltage temperature coefficient IPP VF Forward voltage drop Symbol Test Condition Min Typ Max Unit VBR IR = 1 mA 6.1 7.2 V IRM VRM = 3 V 500 nA VF IF = 10 mA 1 V Rd 1 Ω αT(1) IR = 1 mA 5 10-4/ °C C V =0 V DC, F= 1 MHz, V = 30 mV 70 pF R osc RMS 1. ΔV = αT * (T - 25 °C) * V (25 °C) BR amb BR 2/11

ESDA6V1M6, ESDA6V1-5M6 Characteristics Figure 2. R elative variation of peak pulse Figure 3. Peak pulse power versus power versus initial junction exponential pulse duration temperature PPP[Tjinitial]/PPP[Tjinitial=25°C] PPP(W) 1.1 1000 1.0 Tjinitial = 25°C 0.9 0.8 0.7 0.6 100 0.5 0.4 0.3 0.2 0.1 Tj(°C) tP(µs) 0.0 10 0 25 50 75 100 125 150 1 10 100 Figure 4. C lamping voltage versus peak Figure 5. Forward voltage drop versus peak pulse current (typical values, forward current (typical values) 8/20 µs waveform) IPP(A) IFM(A) 100.0 1.E+00 8/20µs Tjinitial =25°C 10.0 1.E-01 Tj=125°C Tj=25°C 1.0 1.E-02 VCL(V) VFM(V) 0.1 1.E-03 0 10 20 30 40 50 60 70 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Figure 6. J unction capacitance versus Figure 7. Relative variation of leakage reverse voltage applied (typical current versus junction values) temperature (typical values) C(pF) IR[Tj]/IR[Tj=25°C] 80 100 70 VOSFC==13M0mHVzRMS VR=3V 60 Tj=25°C 50 40 10 30 20 10 VR(V) Tj(°C) 0 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 25 50 75 100 125 3/11

Ordering information scheme ESDA6V1M6, ESDA6V1-5M6 Figure 8. S 21 attenuation measurement Figure 9. Analog crosstalk measurements results of each channel between channels dB dB 0.00 0.00 -10.00 -30.00 -20.00 -60.00 -30.00 -90.00 f/Hz f/Hz -40.00 -120.00 100.0k 1.0M 10.0M 100.0M 1.0G 100.0k 1.0M 10.0M 100.0M 1.0G Figure 10. E SD response to IEC 6100-4-2 Figure 11. ESD response to IEC 6100-4-2 (+15 kV air discharge) on each (-15 kV air discharge) on each channel channel 2 Ordering information scheme Figure 12. Ordering information scheme ESDA 6V1 xx M6 ESD array Breakdown voltage 6V1 = 6.1Volts min Number of lines blank = 4 line -5 = 5 line protection Package M6 = Micro QFN 6 leads 4/11

ESDA6V1M6, ESDA6V1-5M6 Package information 3 Package information ● Epoxy meets UL94, V0 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. T able 3. Package dimensions Dimensions D N Ref Millimeters Inches E Min Typ Max Min Typ Max 1 2 A 0.50 0.55 0.60 0.020 0.022 0.024 A1 0.00 0.02 0.05 0.000 0.001 0.002 A b 0.18 0.25 0.30 0.007 0.010 0.012 A1 D(1) 1.45 0.057 1 2 L E(1) 1.00 0.039 k e(2) 0.50 0.020 b k 0.20 0.008 e L 0.30 0.35 0.40 0.012 0.014 0.016 1. ± 0.1 mm 2. ± 0.05 mm Figure 13. Footprint dimensions in mm [inches] 0.50 0.25 [0.020] [0.010] 0.65 [0.026] 0.30 1.60 [0.012] [0.063] 5/11

Package information ESDA6V1M6, ESDA6V1-5M6 Figure 14. Tape and reel specification DDoottiiddeennttiiffyyiinnggPPiinnAA11llooccaattiioonn 22..00++//--00..0055 44..0000++//--00..11 φφ11..55++//--00..11 11 .7.7 55 ++ /-/- 00 .1.1 33 .5.5 ++ /-/- 8.08.0 0.030.03 +/-0.3+/-0.3 1.651.65 XXX XX XXX 00..7755 11..2200 44..0000 UUsseerrddiirreeccttiioonnooffuunnrreeeelliinngg XX:: MMaarrkkiinngg Note: Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin1 mark is to be used for this purpose. 6/11

ESDA6V1M6, ESDA6V1-5M6 Recommendation on PCB assembly 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 15. Stencil opening dimensions L T W b) General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = -----≥1.5 T L× W Aspect Area = ----------------------------≥0.66 2T(L+W) 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for leads: Opening to footprint ratio is 90%. Figure 16. Recommended stencil window position 7µm 7µm 15µm 650µm 620µm 236µm 15µm Footprint 250µm Stencilwindow Footprint 7/11

Recommendation on PCB assembly ESDA6V1M6, ESDA6V1-5M6 4.2 Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm. 4.3 Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 4.4 PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. 8/11

ESDA6V1M6, ESDA6V1-5M6 Recommendation on PCB assembly 4.5 Reflow profile Figure 17. ST ECOPACK® recommended soldering reflow profile for PCB mounting TTeemmppeerraattuurree ((°°CC)) 226600°°CC mmaaxx 225555°°CC 222200°°CC 118800°°CC 112255 °°CC 2°C/s 2r°eCc/osm remceonmdmedended 3°C/s max 6°C/s max 6°C/s max 3°C/s max 00 00 11 22 33 44 55 66 77 1100--3300 sseecc TTiimmee ((mmiinn)) 9900 ttoo 115500 sseecc 9900 sseecc mmaaxx Note: Minimize air convection currents in the reflow oven to avoid component movement. 9/11

Ordering information ESDA6V1M6, ESDA6V1-5M6 5 Ordering information T able 4. Ordering information Order code Marking Package Weight Base qty Delivery mode ESDA6V1M6 I(1) Micro QFN 2.2 mg 3000 Tape and reel ESDA6V1-5M6 J(1) Micro QFN 2.2 mg 3000 Tape and reel 1. The marking can be rotated by 90° to differentiate assembly location 6 Revision history T able 5. Document revision history Date Revision Changes 19-Sep-2005 1 Initial release. 10-Oct-2005 2 Package title changed from DFN to QFN. No technical changes. Reformatted to current standard. 01-Feb-2007 3 Added note on marking rotation in section 3. Package information. Reformatted to current standards. Corrected inch measurements in 18-Feb-2008 4 Table3 on page5. Added Section4: Recommendation on PCB assembly. 10/11

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