ESD7104 ESD Protection Diode Low Capacitance ESD Protection Diode for High Speed Data Line The ESD7104 surge protection is designed to protect high speed data lines from ESD. Ultra−low capacitance and low ESD clamping www.onsemi.com voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. The flow−through style package MARKING allows for easy PCB layout and matched trace lengths necessary to DIAGRAM maintain consistent impedance between high speed differential lines UDFN10 7M M(cid:2) such as USB 3.0 and HDMI. CASE 517BB (cid:2) Features • 7M = Specific Device Code (tbd) Low Capacitance (0.3 pF Typical, I/O to GND) M = Date Code • Low ESD Clamping Voltage (cid:2) = Pb−Free Package • Protection for the Following IEC Standards: (Note: Microdot may be in either location) IEC 61000−4−2 (Level 4) • UL Flammability Rating of 94 V−0 WDFNW10 • XXX M SZESD7104MTWTAG − Wettable Flank Package for optimal CASE 515AH Automated Optical Inspection (AOI) • SZ Prefix for Automotive and Other Applications Requiring Unique XX = Specific Device Code Site and Control Change Requirements; AEC−Q101 Qualified and M = Date Code PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS PIN CONFIGURATION Compliant AND SCHEMATIC Typical Applications N/C N/C GND N/C N/C • USB 3.0 • 10 9 8 7 6 eSATA 3.0 • Thunderbolt (Light Peak) • 1 2 3 4 5 HDMI 1.3/1.4 • Display Port I/O I/O GND I/O I/O I/O I/O I/O I/O MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Pin 1 Pin 2 Pin 4 Pin 5 Rating Symbol Value Unit Operating Junction Temperature Range TJ −55 to +125 °C Storage Temperature Range Tstg −55 to +150 °C Lead Solder Temperature − TL 260 °C Maximum (10 Seconds) GND Pin 3 IEC 61000−4−2 Contact (ESD) ESD ±15 kV IEC 61000−4−2 Air (ESD) ESD ±15 kV Stresses exceeding those listed in the Maximum Ratings table may damage the = device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. See Application Note AND8308/D for further description of survivability specs. This document contains information on some products that are still under development. ORDERING INFORMATION ON Semiconductor reserves the right to change or discontinue these products without See detailed ordering, marking and shipping information in the notice. package dimensions section on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: June, 2019 − Rev. 5 ESD7104/D

ESD7104 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit Reverse Working Voltage VRWM I/O Pin to GND 5.0 V Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 5.5 V Reverse Leakage Current IR VRWM = 5 V, I/O Pin to GND 1.0 (cid:2)A Clamping Voltage (Note 1) VC IPP = 1 A, I/O Pin to GND (8 x 20 (cid:2)s pulse) 10 V Clamping Voltage (Note 2) VC IEC61000−4−2, ±8 KV Contact See Figures 1 and 2 V Clamping Voltage (Note 3) VC IPP = ±8 A 14.1 V IPP = ±16 A 19.5 Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins 0.2 0.3 pF Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND 0.3 0.35 pF Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Surge current waveform per Figure 5. 2. For test procedure see Figures 3 and 4 and application note AND8307/D. 3. ANSI/ESD STM5.5.1 − 2008 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 (cid:3), tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. 80 10 70 0 60 −10 50 −20 V) V) E ( 40 E ( −30 G G A A T 30 T −40 L L O O V 20 V −50 10 −60 0 −70 −10 −80 −20 0 20 40 60 80 100 120 140 −20 0 20 40 60 80 100 120 140 TIME (ns) TIME (ns) Figure 1. IEC61000−4−2 +8 KV Contact Figure 2. IEC61000−4−2 −8 KV Contact Clamping Voltage Clamping Voltage www.onsemi.com 2

ESD7104 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak First Peak Test Volt- Current Current at Current at 100% Level age (kV) (A) 30 ns (A) 60 ns (A) 90% 1 2 7.5 4 2 2 4 15 8 4 I @ 30 ns 3 6 22.5 12 6 4 8 30 16 8 I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec Device Under ESD Gun Oscilloscope Test 50 (cid:2) 50 (cid:2) Cable Figure 4. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note systems such as cell phones or laptop computers it is not AND8308/D − Interpretation of Datasheet Parameters clearly defined in the spec how to specify a clamping voltage for ESD Devices. at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD ESD Voltage Clamping protection diode over the time domain of an ESD pulse in the For sensitive circuit elements it is important to limit the form of an oscilloscope screenshot, which can be found on voltage that an IC will be exposed to during an ESD event the datasheets for all ESD protection diodes. For more to as low a voltage as possible. The ESD clamping voltage information on how ON Semiconductor creates these is the voltage drop across the ESD protection diode during screenshots and how to interpret them please refer to an ESD event per the IEC61000−4−2 waveform. Since the AND8307/D. IEC61000−4−2 was written as a pass/fail spec for larger 100 tr PEAK VALUE IRSM @ 8 (cid:2)s T 90 N E 80 PULSE WIDTH (tP) IS DEFINED R AS THAT POINT WHERE THE R U 70 PEAK CURRENT DECAY = 8 (cid:2)s C E 60 ULS 50 HALF VALUE IRSM/2 @ 20 (cid:2)s P K 40 A E P 30 F tP O 20 % 10 0 0 20 40 60 80 t, TIME ((cid:2)s) Figure 5. 8 x 20 (cid:2)s Pulse Waveform www.onsemi.com 3

ESD7104 22 −22 20 −20 18 −18 16 −16 A) 14 A) −14 NT ( 12 NT ( −12 E E R 10 R −10 R R U 8 U −8 C C 6 −6 4 −4 2 −2 0 0 0 2 4 6 8 10 12 14 16 18 20 22 24 0 −2 −4 −6 −8 −10 −12 −14 −16 −18 −20 −22 −24 VOLTAGE (V) VOLTAGE (V) Figure 6. Positive TLP I−V Curve Figure 7. Negative TLP I−V Curve Transmission Line Pulse (TLP) Measurement L S Attenuator 50 (cid:3) Coax Transmission Line Pulse (TLP) provides current versus Cable ÷ voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged 50 (cid:3) Coax transmission line. A simplified schematic of a typical TLP Cable 10 M(cid:3) IM VM system is shown in Figure 8. TLP I−V curves of ESD protection devices accurately demonstrate the product’s DUT ESD capability because the 10s of amps current levels and VC under 100 ns time scale match those of an ESD event. This Oscilloscope is illustrated in Figure 9 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at Figure 8. Simplified Schematic of a Typical TLP 8 A and 16 A. A TLP I−V curve shows the voltage at which System the device turns on as well as how well the device clamps voltage over a range of current levels. Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms www.onsemi.com 4

ESD7104 Without ESD With ESD7104 Figure 10. USB3.0 Eye Diagram with and without ESD7104. 5.0 Gb/s, 400 mV PP Without ESD With ESD7104 Figure 11. HDMI1.4 Eye Diagram with and without ESD7104. 3.4 Gb/s, 400 mV PP Without ESD With ESD7104 Figure 12. ESATA3.0 Eye Diagram with and without ESD7104. 6 Gb/s, 400 mV PP www.onsemi.com 5

ESD7104 4 ESD7104 IO−GND B) 2 d S ( S 0 O L N −2 O TI R −4 E S 1 IN −6 2 S −8 −10 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 FREQUENCY (Hz) Figure 13. ESD7104 Insertion Loss www.onsemi.com 6

ESD7104 USB 3.0 Type A Connector StdA_SSTX+ Vbus StdA_SSTX− ESD7104 D− ESD7L5.0 GND_DRAIN D+ StdA_SSRX+ GND StdA_SSRX− Figure 14. USB3.0 Standard A Connector Layout Diagram USB 3.0 Micro B Connector ESD7104 Vbus D− D+ ID GND ESD7104 MicB_SSTX− MicB_SSTX+ GND_DRAIN MicB_SSRX− MicB_SSRX+ Figure 15. USB3.0 Micro B Connector Layout Diagram www.onsemi.com 7

ESD7104 HDMI Type A Connector ESD7104 D2+ GND D2− D1+ GND D1− ESD7104 D0+ GND D0− CLK+ GND CLK− CEC N/C (or HEC_DAT – HDMI1.4) SCL SDA GND 5V HPD (and HEC_DAT – HDMI1.4) NUP4114 Figure 16. HDMI Layout Diagram eSATA Connector GND A+ ESD7104 A− GND B− B+ GND Figure 17. eSATA Layout Diagram www.onsemi.com 8

ESD7104 DEVICE ORDERING INFORMATION Device Marking Package Shipping† ESD7104MUTAG 7M UDFN10 3000 / Tape & Reel (Pb−Free) SZESD7104MUTAG 7M UDFN10 3000 / Tape & Reel (Pb−Free) SZESD7104MTWTAG TBD WDFNW10 3000 / Tape & Reel (In Development) (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 9

ESD7104 PACKAGE DIMENSIONS UDFN10 2.5 x 1, 0.5P CASE 517BB ISSUE O L L NOTES: 1. DIMENSIONING AND TOLERANCING PER D A B ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. L1 3. DIMENSION b APPLIES TO PLATED PIN ONE DETAIL A TERMINAL AND IS MEASURED BETWEEN REFERENCE ÍÍÍ 0.15 AND 0.30mm FROM TERMINAL. E OPTIONAL 2X 0.10 C ÍÍÍ CONSTRUCTIONS MILLIMETERS DIM MIN MAX A 0.45 0.55 2X 0.10 C A1 0.00 0.05 TOP VIEW EXPOSED Cu MOLD CMPD A3 0.13 REF ÇÇÇ b 0.15 0.25 b2 0.35 0.45 DETAIL B A3 A ÇÉÇÉÇÉ A3 D 2.50 BSC 0.10 C E 1.00 BSC ÉÉÉ e 0.50 BSC L 0.30 0.40 A1 L1 --- 0.05 10X 0.08 C A1 DETAIL B OPTIONAL SIDE VIEW C SPELAATNIENG CONSTRUCTION RECOMMENDED SOLDERING FOOTPRINT* 2X b2 10X L DETAIL A 1 5 10X 2X0.45 0.50 10 6 1.30 e 8Xb 0.10 C A B PACKAGE OUTLINE BOTTOM VIEW 0.05 C NOTE 3 0.50 8X0.25 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 10

ESD7104 PACKAGE DIMENSIONS WDFNW10 2.5x1.0, 0.5P CASE 515AH ISSUE O ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada For additional information, please contact your local Email: orderlit@onsemi.com Sales Representative ◊ www.onsemi.com ESD7104/D 11

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