TVS Diode Transient Voltage Suppressor Diodes ESD207-B1-02 Series Ultra Low Clamping Bi-directional ESD / Transient / Surge Protection Diodes ESD207-B1-02ELS ESD207-B1-02EL Data Sheet Revision 1.3, 2013-12-19 Final Power Management & Multimarket

ESD207-B1-02 Series Revision History: Revision 1.2, 2013-11-15 Page or Item Subjects (major changes since previous revision) Revision 1.3, 2013-12-19 5 Table2-2) updated Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLIDFLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYOYUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2010-10-26 FinalData Sheet 2 Revision 1.3, 2013-12-19

ESD207-B1-02 Series Ultra Low Clamping Bi-directional ESD / Transient / Surge Protection Diodes 1 Ultra Low Clamping Bi-directional ESD / Transient / Surge Protection Diodes 1.1 Features • ESD / transient / surge protection of one data / V line exceding standard: bus – IEC61000-4-2 (ESD): ±30kV (air/contact discharge) – IEC61000-4-4 (EFT): ±50A (5/50ns) – IEC61000-4-5 (surge): ±8A (8/20μs) • Bi-directional, symmetrical working voltage up to V =±3.3V RWM • Medium capacitance: C =14pF (typ.) L • Ultra low clamping voltage V =7V (typ.) @ I =16A (TLP) CL PP • Ultra low dynamic resistance R =0.13Ω typ. DYN • Pb-free (RoHS compliant) and halogen free package 1.2 Application Examples • Audio Line, Speaker, Headset, Microphone Protection • Human Interface Devices (Keyboard, Touchpad, Buttons) 1.3 Product Description Pin 1 Pin 2 Pin 1 Pin 1 marking (lasered) TSLP-2 Pin 1 Pin 2 Pin 2 TSSLP-2 a) Pin configuration b) Schematic diagram PG-TS(S)LP-2_Dual_Diode_Serie_PinConf_and_SchematicDiag.vsd Figure1-1 Pin Configuration and Schematic Diagram Table1-1 Ordering Information Type Package Configuration Marking code ESD207-B1-02ELS TSSLP-2-3 1 line, bi-directional Y ESD207-B1-02EL TSLP-2-19 1 line, bi-directional A FinalData Sheet 3 Revision 1.3, 2013-12-19

ESD207-B1-02 Series Characteristics 2 Characteristics Table2-1 Maximum Ratings at T = 25°C, unless otherwise specified1) A Parameter Symbol Values Unit Min. Typ. Max. ESD contact discharge2) V – – 30 kV ESD Peak pulse current (t = 8/20μs)3) I – – 8 A p PP Peak pulse power (t = 8/20μs)3) P – – 65 W p PK Operating temperature range T -40 – 125 °C OP Storage temperature T -65 – 150 °C stg 1) Device is electrically symmetrical 2) V according to IEC61000-4-2 ESD 3) I according to IEC61000-4-5 PP Attention:Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 2.1 Electrical Characteristics at T = 25 °C, unless otherwise specified A (cid:10)(cid:5) (cid:10) (cid:17)(cid:17) (cid:10) (cid:15)(cid:16)(cid:17) (cid:11)(cid:2) (cid:11)(cid:2) (cid:2)(cid:5) (cid:19)(cid:19)(cid:19) (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13) (cid:7)(cid:12)(cid:13)(cid:14) (cid:11)(cid:10) (cid:10)(cid:5) (cid:19)(cid:19)(cid:19) (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:16)(cid:17)(cid:4)(cid:4)(cid:13)(cid:18)(cid:11) (cid:11)(cid:10) (cid:2)(cid:7) (cid:19)(cid:19)(cid:19) (cid:14)(cid:13)(cid:9)(cid:13)(cid:4)(cid:15)(cid:13)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13) (cid:10)(cid:7) (cid:19)(cid:19)(cid:19) (cid:14)(cid:13)(cid:9)(cid:13)(cid:4)(cid:15)(cid:13)(cid:8)(cid:16)(cid:17)(cid:4)(cid:4)(cid:13)(cid:18)(cid:11) (cid:2) (cid:7)(cid:18) (cid:2)(cid:15)(cid:16)(cid:17)(cid:2)(cid:3)(cid:4) (cid:2)(cid:6) (cid:2)(cid:7)(cid:8)(cid:9) (cid:10)(cid:7)(cid:8)(cid:9) (cid:2)(cid:7) (cid:2)(cid:5) (cid:10)(cid:7)(cid:8)(cid:9) (cid:2)(cid:7)(cid:8)(cid:9) (cid:2)(cid:6) (cid:2)(cid:3)(cid:4) (cid:2)(cid:5)(cid:18) (cid:2) (cid:15)(cid:16)(cid:17) (cid:7)(cid:12)(cid:13)(cid:14) (cid:19)(cid:19)(cid:19) (cid:19)(cid:20)(cid:18)(cid:6)(cid:21)(cid:22)(cid:16)(cid:8)(cid:4)(cid:13)(cid:15)(cid:22)(cid:15)(cid:11)(cid:6)(cid:18)(cid:16)(cid:13) (cid:2)(cid:7)(cid:8)(cid:9)(cid:19)(cid:19)(cid:19) (cid:14)(cid:13)(cid:9)(cid:13)(cid:4)(cid:15)(cid:13)(cid:8)(cid:5)(cid:3)(cid:4)(cid:26)(cid:22)(cid:18)(cid:12)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13)(cid:8)(cid:21)(cid:6)(cid:27)(cid:28) (cid:2)(cid:3)(cid:4) (cid:19)(cid:19)(cid:19) (cid:25)(cid:4)(cid:22)(cid:12)(cid:12)(cid:13)(cid:4)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13) (cid:11)(cid:10) (cid:2)(cid:6) (cid:19)(cid:19)(cid:19) (cid:24)(cid:3)(cid:10)(cid:7)(cid:22)(cid:18)(cid:12)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13) (cid:2)(cid:5)(cid:18) (cid:19)(cid:19)(cid:19) (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:16)(cid:10)(cid:6)(cid:21)(cid:23)(cid:22)(cid:18)(cid:12)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13) (cid:11)(cid:2) (cid:7) (cid:2)(cid:7)(cid:18) (cid:19)(cid:19)(cid:19) (cid:14)(cid:13)(cid:9)(cid:13)(cid:4)(cid:15)(cid:13)(cid:8)(cid:16)(cid:10)(cid:6)(cid:21)(cid:23)(cid:22)(cid:18)(cid:12)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13) (cid:11)(cid:2) (cid:12)(cid:13)(cid:14) (cid:11)(cid:10) (cid:2)(cid:15)(cid:16)(cid:17) (cid:19)(cid:19)(cid:19) (cid:25)(cid:29)(cid:30)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13) (cid:10)(cid:17)(cid:17) (cid:10)(cid:7)(cid:8)(cid:9) (cid:19)(cid:19)(cid:19) (cid:14)(cid:13)(cid:9)(cid:13)(cid:4)(cid:15)(cid:13)(cid:8)(cid:5)(cid:3)(cid:4)(cid:26)(cid:22)(cid:18)(cid:12)(cid:8)(cid:16)(cid:17)(cid:4)(cid:4)(cid:13)(cid:18)(cid:11)(cid:8)(cid:21)(cid:6)(cid:27)(cid:28) (cid:10) (cid:10)(cid:17)(cid:17) (cid:19)(cid:19)(cid:19) (cid:30)(cid:13)(cid:6)(cid:26)(cid:8)(cid:23)(cid:17)(cid:10)(cid:15)(cid:13)(cid:8)(cid:16)(cid:17)(cid:4)(cid:4)(cid:13)(cid:18)(cid:11) (cid:15)(cid:16)(cid:17) (cid:10)(cid:15)(cid:16)(cid:17) (cid:19)(cid:19)(cid:19) (cid:25)(cid:29)(cid:30)(cid:8)(cid:16)(cid:17)(cid:4)(cid:4)(cid:13)(cid:18)(cid:11) (cid:10)(cid:7) (cid:19)(cid:22)(cid:3)(cid:7)(cid:13)(cid:31) !(cid:6)(cid:4)(cid:6)(cid:16)(cid:11)(cid:13)(cid:4)(cid:22)(cid:15)(cid:11)(cid:22)(cid:16)(cid:31) (cid:17)(cid:4)(cid:9)(cid:13)(cid:31)(cid:5)(cid:22)(cid:11)!(cid:31)(cid:15)(cid:18)(cid:6)(cid:23)"(cid:6)(cid:16)(cid:26)(cid:31)#(cid:22)$(cid:7)(cid:22)(cid:4)(cid:13)(cid:16)(cid:11)(cid:22)(cid:3)(cid:18)(cid:6)(cid:10)(cid:28)(cid:15)(cid:9)(cid:12) Figure2-1 Definitions of electrical characteristics FinalData Sheet 4 Revision 1.3, 2013-12-19

ESD207-B1-02 Series Characteristics Table2-2 DC Characteristics at T = 25°C, unless otherwise specified1) A Parameter Symbol Values Unit Note / TestCondition Min. Typ. Max. Reverse working voltage V – – 3.3 V RWM Reverse current I – – 50 nA V =3.3V R R Trigger voltage V 3.65 – – V t1 Holding voltage V 3.65 4.4 – V I =10mA h R 1) Device is electrically symmetrical Table2-3 AC Characteristics at T = 25°C, unless otherwise specified A Parameter Symbol Values Unit Note / TestCondition Min. Typ. Max. Line capacitance C – 14 20 pF V = 0V, f = 1MHz L R Table2-4 ESD and Surge Characteristics at T = 25°C, unless otherwise specified A Parameter Symbol Values Unit Note / TestCondition Min. Typ. Max. Clamping voltage1) Pin 1 to GND V – 7 – V I =16A CL TLP – 9 – I =30A TLP Clamping voltage1) GND to Pin 1 – 7.5 – I =16A TLP – 9 – I =30A TLP Clamping voltage2) – 4.5 5.8 I =1A PP – 6.8 8.1 I =8A PP Dynamic resistance1) R – 0.13 – Ω DYN 1) ANSI/ESD STM5.5.1 - Electrostatic Discharge Sensitive Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z =50Ω, t =100ns, t =0.6ns, I and V averaging window: t =30ns to t =60ns, extraction of 0 p r, TLP TLP 1 2 dynamic resistance using least squares fit of TLP characteristic between I =5A and I =40A. Please refer to TLP1 TLP2 Application Note AN210 [1] 2) I according to IEC61000-4-5 (t =8/20 µs) PP p FinalData Sheet 5 Revision 1.3, 2013-12-19

ESD207-B1-02 Series Characteristics 2.2 Typical Characteristics at T = 25 °C, unless otherwise specified A -5 10 -6 10 -7 10 -8 10 ] A [ R -9 I 10 -10 10 -11 10 -12 10 -4 -3 -2 -1 0 1 2 3 4 V [V] R Figure2-2 Reverse current: I =f(V ) R R 1000 100 ] A n 10 [ R I 1 0.1 -50 -25 0 25 50 75 100 125 T [°C] A Figure2-3 Reverse current: I =f(T ), V =3.3V R A R FinalData Sheet 6 Revision 1.3, 2013-12-19

ESD207-B1-02 Series Characteristics 20 15 ] F p [ L C 10 5 -4 -3 -2 -1 0 1 2 3 4 V [V] R Figure2-4 Line capacitance: C =f(V ), f=1MHz L R FinalData Sheet 7 Revision 1.3, 2013-12-19

ESD207-B1-02 Series Characteristics 60 30 ESD207-B1-02series R DYN 50 25 40 20 30 15 R = 0.13 Ω DYN 20 10 ] 10 5 V k [ C ] E A VI [ 0 0 P t L n T e I al v -10 -5 ui q E -20 -10 R = 0.14 Ω DYN -30 -15 -40 -20 -50 -25 -60 -30 -20 -15 -10 -5 0 5 10 15 20 V [V] TLP Figure2-5 Clamping voltage (TLP): I =f(V ) according ANSI/ESD STM5.5.1-Electrostatic Discharge TLP TLP Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z =50Ω, 0 t =100ns, t =0.6ns, I and V averaging window: t =ns to t =60ns, extraction of p r TLP TLP 1 2 dynamic resistance using squares fit to TLP characteristics between I =5A and TLP1 I =40A. Please refer to Application Note AN210 [1] TLP2 FinalData Sheet 8 Revision 1.3, 2013-12-19

ESD207-B1-02 Series Characteristics 11 ESD207-B1-02series R 10 DYN 9 8 7 6 5 4 R = 0.3 Ω DYN 3 2 1 ] A [ 0 P P I -1 -2 -3 -4 R = 0.4 Ω DYN -5 -6 -7 -8 -9 -10 -11 -15 -10 -5 0 5 10 15 V [V] CL Figure2-6 Pulse current (IEC61000-4-5) versus clamping voltage: I =f(V ) PP CL FinalData Sheet 9 Revision 1.3, 2013-12-19

ESD207-B1-02 Series Characteristics 40 30 V = 38.1 [V] CL-max-peak 20 ] V = 7.7 [V] V CL-30ns-peak [ L C 10 V 0 -10 -100 0 100 200 300 400 500 600 700 800 900 t [ns] p Figure2-7 IEC61000-4-2 : V =f(t), 8kV positive pulse from pin 1 to pin 2 CL 10 0 V] -10 [ CL VCL-max-peak = -37.5 [V] V -20 V = -6.9 [V] CL-30ns-peak -30 -40 -100 0 100 200 300 400 500 600 700 800 900 t [ns] p Figure2-8 IEC61000-4-2 : V =f(t), 8kV negative pulse from pin 1 to pin 2 CL FinalData Sheet 10 Revision 1.3, 2013-12-19

ESD207-B1-02 Series Characteristics 70 60 50 40 V = 61.3 [V] CL-max-peak 30 ] V = 8.3 [V] V CL-30ns-peak [ 20 L C V 10 0 -10 -20 -30 -100 0 100 200 300 400 500 600 700 800 900 t [ns] p Figure2-9 IEC61000-4-2 : V =f(t), 15kV positive pulse from pin 1 to pin 2 CL 30 20 10 0 -10 ] V [ -20 L C V = -65.0 [V] V CL-max-peak -30 V = -7.6 [V] CL-30ns-peak -40 -50 -60 -70 -100 0 100 200 300 400 500 600 700 800 900 t [ns] p Figure2-10 IEC61000-4-2 : V =f(t), 15kV negative pulse from pin 1 to pin 2 CL FinalData Sheet 11 Revision 1.3, 2013-12-19

ESD207-B1-02 Series Application Information 3 Application Information e g a t ol Time V +Vcc Audio_out single ended ESD-strike ESD-strike Audio_in Headset PCB line cable tne e o Audio Amp. s dh ap de er- Ha o -Vcc i E D Headset con. Charge D +Vcc e.g. 3.5mm jack Pump S E ESD3V3S1B-02LS_Application.vsd Figure3-1 Single line, bi-directional ESD / Transient protection FinalData Sheet 12 Revision 1.3, 2013-12-19

ESD207-B1-02 Series Package Information 4 Package Information 4.1 TSSLP-2-3 Top view Bottom view 0.31+-00..0021 0.32±0.05 2 5 55 ±0.0 0.3 62 0. 1 Cathode 0.05 MAX. 0.26±0.0351) 1)35 0 marking 0. ± 2 0. 1) Dimension applies to plated terminals TSSLP-2-3, -4-PO V01 Figure4-1 TSSLP-2-3: Package overview (dimension in mm) 0.32 0.24 0.27 0.19 4 1 0. 2 7 6 5 0. 0. 9 1 9 0. 0.24 0.1 Copper Solder mask Stencil apertures TSSLP-2-3, -4-FP V02 Figure4-2 TSSLP-2-3: Footprint (dimension in mm) g 4 0.35 Tape type Ex Ey Punched Tape 0.43 0.73 y E Embossed Tape 0.37 0.67 8 Deliveries can be both tape types (no selection possible). Specification allows identical processing (pick & place) by users. Cathode Ex marking TSSLP-2-3, -4-TP V03 Figure4-3 TSSLP-2-3: Tape information (dimension in mm) Type code 1 Cathode marking TSSLP-2-3, -4-MK V01 Figure4-4 TSSLP-2-3: Marking (example) FinalData Sheet 13 Revision 1.3, 2013-12-19

ESD207-B1-02 Series Package Information 4.2 TSLP-2-19 Top view Bottom view 0.31+0.01 -0.02 0.05 MAX. 0.6±0.05 5 2 0 0.65±0. 1 1±0.05 Cathode 0.5±0.0351) 1)35 0 marking 0. ± 5 2 1) Dimension applies to plated terminals 0. TSLP-2-19,-20-PO V01 Figure4-5 TSLP-2-19: Package outline(dimension in mm), proposal 0.6 5 0.45 8 3 2 0. 0. 3 0. 3 1 9 0. 8 3 0.35 0.28 0. Copper Solder mask Stencil apertures TSLP-2-19, -20-FP V01 Figure4-6 TSLP-2-19: Footprint (dimension in mm), proposal 4 0.4 Cathode marking 16 1. 8 0.76 TSLP-2-19, -20-TP V02 Figure4-7 TSLP-2-19: Tape information (dimension in mm), proposal Type code 12 Cathode marking TSLP-2-19, -20-MK V01 Figure4-8 TSLP-2-19: Marking (example) FinalData Sheet 14 Revision 1.3, 2013-12-19

ESD207-B1-02 Series References References [1] Infineon AG - Application Note AN210: Effective ESD Protection design at System Level Using VF-TLP Characterization Methodology [2] Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages FinalData Sheet 15 Revision 1.3, 2013-12-19

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