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ESD105B102ELSE6327XTSA1产品简介:
ICGOO电子元器件商城为您提供ESD105B102ELSE6327XTSA1由Infineon设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 ESD105B102ELSE6327XTSA1价格参考。InfineonESD105B102ELSE6327XTSA1封装/规格:TVS - 二极管, 14V Clamp 5A (8/20µs) Ipp Tvs Diode Surface Mount TSSLP-2-4。您可以下载ESD105B102ELSE6327XTSA1参考资料、Datasheet数据手册功能说明书,资料中有ESD105B102ELSE6327XTSA1 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | |
描述 | TVS DIODE 5.5VWM 14VC TSSLP2-4 |
产品分类 | |
品牌 | Infineon Technologies |
数据手册 | http://www.infineon.com/dgdl/ESD105_B1_02series_rev_1_0.pdf?folderId=db3a30431f848401011fcbf2ab4c04c4&fileId=db3a30434358307d01437c468ff01c72 |
产品图片 | |
产品型号 | ESD105B102ELSE6327XTSA1 |
rohs | 无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | - |
不同频率时的电容 | 0.3pF @ 1MHz |
产品培训模块 | http://www.digikey.cn/PTM/IndividualPTM.page?site=cn&lang=zhs&ptm=30476 |
供应商器件封装 | TSSLP-2-4 |
其它名称 | ESD105B102ELSE6327XTSA1CT |
功率-峰值脉冲 | 70W |
包装 | 剪切带 (CT) |
单向通道 | - |
双向通道 | 1 |
安装类型 | 表面贴装 |
封装/外壳 | 2-XFDFN |
工作温度 | -55°C ~ 125°C |
应用 | 以太网, HDMI |
标准包装 | 1 |
电压-击穿(最小值) | 6.1V |
电压-反向关态(典型值) | 5.5V(最小值) |
电压-箝位(最大值)@Ipp | 14V |
电流-峰值脉冲(10/1000µs) | 5A (8/20µs) |
电源线路保护 | 无 |
类型 | 齐纳 |
TVS Diodes Transient Voltage Suppressor Diodes ESD105-B1-02 Series Low Capacitance & Low Clamping Bi-directional ESD / Transient Protection Diodes ESD105-B1-02ELS ESD105-B1-02EL Data Sheet Revision 1.0, 2013-12-12 Final Power Management & Multimarket
ESD105-B1-02 Series Revision History: Rev. 04, 2013-09-24 Page or Item Subjects (major changes since previous revision) Revision 1.0, 2013-12-12 All Status change to Final Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, COMNEON™, C166™, CROSSAVE™, CanPAK™, CIPOS™, CoolMOS™, CoolSET™, CORECONTROL™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, EUPEC™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, I²RF™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PROFET™, PRO-SIL™, PRIMARION™, PrimePACK™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SMARTi™, SmartLEWIS™, TEMPFET™, thinQ!™, TriCore™, TRENCHSTOP™, X-GOLD™, XMM™, X-PMU™, XPOSYS™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, PRIMECELL™, REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYOYUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2010-06-09 Final Data Sheet 2 Revision 1.0, 2013-12-12
ESD105-B1-02 Series Low Capacitance & Low Clamping Bi-directional ESD / Transient Protection 1 Low Capacitance & Low Clamping Bi-directional ESD / Transient Protection Diodes 1.1 Features • ESD / Transient protection of signal lines exceeding standard: – IEC61000-4-2 (ESD): ±30kV air / ±25kV contact discharge – IEC61000-4-4 (EFT): ±50A (5/50ns) – IEC61000-4-5 (Surge): ±5A (8/20μs) • One-line diode with ultra-small form factor down to 0.62x0.32x0.31mm² (0201) package size • Bi-directional, symmetrical working voltage up to: V =±5.5V RWM • Low capacitance C =0.3pF (typical) L • Very low clamping voltage, low dynamic resistance: R =0.36Ω (typ.) DYN • Pb-free package (RoHS compliant) and halogen free package 1.2 Application Examples • USB 3.0. 10/100/1000 Ethernet, Firewire, DVI, HDMI, S-ATA, Display Ports • Mobile HDMI Link, MDDI, MIPI, SWP, NFC 1.3 Product Description Pin 1 Pin 2 Pin 1 Pin 1 marking (lasered) TSLP-2 Pin 1 Pin 2 Pin 2 TSSLP-2 a) Pin configuration b) Schematic diagram PG-TS(S)LP-2_Dual_Diode_Serie_PinConf_and_SchematicDiag.vsd Figure1 Pin configuration and Schematic diagram Table1 Ordering Information Type Package Configuration Marking code ESD105-B1-02ELS TSSLP-2-4 1 line, bi-directional N ESD105-B1-02EL TSLP-2-20 1 line, bi-directional N Final Data Sheet 3 Revision 1.0, 2013-12-12
ESD105-B1-02 Series Characteristics 2 Characteristics Table2 Maximum Ratings at T =25°C, unless otherwise specified1) A Parameter Symbol Values Unit Min. Typ. Max. ESD2) V kV ESD air discharge – – 30 contact discharge – – 25 Peak pulse current (t = 8 / 20μs)3) I – – 5 A p PP Peak pulse power3) P W PK t = 8 / 20μs – – 70 p Operating temperature T -55 – 125 °C OP Storage temperature T -65 – 150 °C stg 1) Device is electrically symmetrical 2) V according to IEC61000-4-2 ESD 3) I according to IEC61000-4-5 PP Attention:Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 2.1 Electrical Characteristics at T = 25 °C, unless otherwise specified A (cid:10)(cid:5) (cid:10) (cid:17)(cid:17) (cid:10) (cid:15)(cid:16)(cid:17) (cid:11)(cid:2) (cid:11)(cid:2) (cid:2)(cid:5) (cid:19)(cid:19)(cid:19) (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13) (cid:7)(cid:12)(cid:13)(cid:14) (cid:11)(cid:10) (cid:10)(cid:5) (cid:19)(cid:19)(cid:19) (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:16)(cid:17)(cid:4)(cid:4)(cid:13)(cid:18)(cid:11) (cid:11)(cid:10) (cid:2)(cid:7) (cid:19)(cid:19)(cid:19) (cid:14)(cid:13)(cid:9)(cid:13)(cid:4)(cid:15)(cid:13)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13) (cid:10)(cid:7) (cid:19)(cid:19)(cid:19) (cid:14)(cid:13)(cid:9)(cid:13)(cid:4)(cid:15)(cid:13)(cid:8)(cid:16)(cid:17)(cid:4)(cid:4)(cid:13)(cid:18)(cid:11) (cid:2) (cid:7)(cid:18) (cid:2)(cid:15)(cid:16)(cid:17)(cid:2)(cid:3)(cid:4) (cid:2)(cid:6) (cid:2)(cid:7)(cid:8)(cid:9) (cid:10)(cid:7)(cid:8)(cid:9) (cid:2)(cid:7) (cid:2)(cid:5) (cid:10)(cid:7)(cid:8)(cid:9) (cid:2)(cid:7)(cid:8)(cid:9) (cid:2)(cid:6) (cid:2)(cid:3)(cid:4) (cid:2)(cid:5)(cid:18) (cid:2) (cid:15)(cid:16)(cid:17) (cid:7)(cid:12)(cid:13)(cid:14) (cid:19)(cid:19)(cid:19) (cid:19)(cid:20)(cid:18)(cid:6)(cid:21)(cid:22)(cid:16)(cid:8)(cid:4)(cid:13)(cid:15)(cid:22)(cid:15)(cid:11)(cid:6)(cid:18)(cid:16)(cid:13) (cid:2)(cid:7)(cid:8)(cid:9)(cid:19)(cid:19)(cid:19) (cid:14)(cid:13)(cid:9)(cid:13)(cid:4)(cid:15)(cid:13)(cid:8)(cid:5)(cid:3)(cid:4)(cid:26)(cid:22)(cid:18)(cid:12)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13)(cid:8)(cid:21)(cid:6)(cid:27)(cid:28) (cid:2)(cid:3)(cid:4) (cid:19)(cid:19)(cid:19) (cid:25)(cid:4)(cid:22)(cid:12)(cid:12)(cid:13)(cid:4)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13) (cid:11)(cid:10) (cid:2)(cid:6) (cid:19)(cid:19)(cid:19) (cid:24)(cid:3)(cid:10)(cid:7)(cid:22)(cid:18)(cid:12)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13) (cid:2)(cid:5)(cid:18) (cid:19)(cid:19)(cid:19) (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7)(cid:8)(cid:16)(cid:10)(cid:6)(cid:21)(cid:23)(cid:22)(cid:18)(cid:12)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13) (cid:11)(cid:2) (cid:7) (cid:2)(cid:7)(cid:18) (cid:19)(cid:19)(cid:19) (cid:14)(cid:13)(cid:9)(cid:13)(cid:4)(cid:15)(cid:13)(cid:8)(cid:16)(cid:10)(cid:6)(cid:21)(cid:23)(cid:22)(cid:18)(cid:12)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13) (cid:11)(cid:2) (cid:12)(cid:13)(cid:14) (cid:11)(cid:10) (cid:2)(cid:15)(cid:16)(cid:17) (cid:19)(cid:19)(cid:19) (cid:25)(cid:29)(cid:30)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:6)(cid:12)(cid:13) (cid:10)(cid:17)(cid:17) (cid:10)(cid:7)(cid:8)(cid:9) (cid:19)(cid:19)(cid:19) (cid:14)(cid:13)(cid:9)(cid:13)(cid:4)(cid:15)(cid:13)(cid:8)(cid:5)(cid:3)(cid:4)(cid:26)(cid:22)(cid:18)(cid:12)(cid:8)(cid:16)(cid:17)(cid:4)(cid:4)(cid:13)(cid:18)(cid:11)(cid:8)(cid:21)(cid:6)(cid:27)(cid:28) (cid:10) (cid:10)(cid:17)(cid:17) (cid:19)(cid:19)(cid:19) (cid:30)(cid:13)(cid:6)(cid:26)(cid:8)(cid:23)(cid:17)(cid:10)(cid:15)(cid:13)(cid:8)(cid:16)(cid:17)(cid:4)(cid:4)(cid:13)(cid:18)(cid:11) (cid:15)(cid:16)(cid:17) (cid:10)(cid:15)(cid:16)(cid:17) (cid:19)(cid:19)(cid:19) (cid:25)(cid:29)(cid:30)(cid:8)(cid:16)(cid:17)(cid:4)(cid:4)(cid:13)(cid:18)(cid:11) (cid:10)(cid:7) (cid:19)(cid:22)(cid:3)(cid:7)(cid:13)(cid:31) !(cid:6)(cid:4)(cid:6)(cid:16)(cid:11)(cid:13)(cid:4)(cid:22)(cid:15)(cid:11)(cid:22)(cid:16)(cid:31) (cid:17)(cid:4)(cid:9)(cid:13)(cid:31)(cid:5)(cid:22)(cid:11)!(cid:31)(cid:15)(cid:18)(cid:6)(cid:23)"(cid:6)(cid:16)(cid:26)(cid:31)#(cid:22)$(cid:7)(cid:22)(cid:4)(cid:13)(cid:16)(cid:11)(cid:22)(cid:3)(cid:18)(cid:6)(cid:10)(cid:28)(cid:15)(cid:9)(cid:12) Figure2 Definitions of electrical characteristics Final Data Sheet 4 Revision 1.0, 2013-12-12
ESD105-B1-02 Series Characteristics Table3 DC Characteristics at T =25°C, unless otherwise specified1) A Parameter Symbol Values Unit Note / TestCondition Min. Typ. Max. Reverse working voltage V – – 5.5 V RWM Reverse current I – <1 20 nA V =5.5V R R Trigger voltage V 6.1 – – V t1 Holding voltage V 6.1 8 – V I =1mA h R 1) Device is electrically symmetrical Table4 AC Characteristics at T =25°C, unless otherwise specified A Parameter Symbol Values Unit Note / TestCondition Min. Typ. Max. Line capacitance C – 0.3 0.45 pF V =0V, f=1MHz L R – 0.3 0.45 V =0V, f=1GHz R Table5 ESD and Surge Characteristics at T = 25°C, unless otherwise specified1) A Parameter Symbol Values Unit Note / TestCondition Min. Typ. Max. Clamping voltage 2) V – 13 16 V I =16A, CL TLP t =100ns p – 19 22 I =30A, TLP t =100ns p Clamping voltage3) – 8.5 11.5 I =2A, t =8/20µs PP p – 11 14 I =5A, t =8/20µs PP p Dynamic resistance2) R – 0.36 0.45 Ω t =100ns DYN p 1) Device is electrically symmetrical 2) Please refer to Application Note AN210 [1]. TLP parameter: Z = 50Ω , t = 100ns, t = 300ps, averaging window: t = 30ns 0 p r 1 to t = 60ns, extraction of dynamic resistance using least squares fit of TLP characteristics between I =10A and 2 TLP1 I =50A. TLP2 3) I according to IEC61000-4-5 (t =8/20µs) PP p Final Data Sheet 5 Revision 1.0, 2013-12-12
ESD105-B1-02 Series Typical Characteristics at T = 25°C, unless otherwise specified A 3 Typical Characteristics at T = 25 °C, unless otherwise specified A -7 10 -8 10 ] A -9 10 [ R I -10 10 -11 10 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 V [V] R Figure3 Reverse current: I =f (V ) R R -5 10 -6 10 -7 10 -8 10 ] A [ R -9 I 10 -10 10 -11 10 -12 10 30 40 50 60 70 80 90 100 110 120 T [°C] A Figure4 Reverse current: I =f(T ), V =5.5V R A R Final Data Sheet 6 Revision 1.0, 2013-12-12
ESD105-B1-02 Series Typical Characteristics at T = 25°C, unless otherwise specified A 0.45 0.4 0.35 ] F p [ L f = 1 MHz C 0.3 f = 1 GHz 0.25 0.2 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 V [V] R Figure5 Line capacitance: C =f (V ), f=1MHz L R 700 600 500 400 ] W [ K P 300 P 200 100 0 -7 -6 -5 10 10 10 t [s] p Figure6 Peak pulse power: P =f (t ) PK p Final Data Sheet 7 Revision 1.0, 2013-12-12
ESD105-B1-02 Series Typical Characteristics at T = 25°C, unless otherwise specified A 60 30 ESD105-B1-02series R DYN 50 25 40 20 30 15 20 10 R = 0.36 Ω DYN ] 10 5 V k [ C ] E A VI [ 0 0 P t L n T e I al v -10 -5 ui q E R = 0.36 Ω DYN -20 -10 -30 -15 -40 -20 -50 -25 -60 -30 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 V [V] TLP Figure7 Clamping voltage (TLP): I =f(V ) according ANSI/ESD STM5.5.1-Electrostatic Discharge TLP TLP Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z =50Ω, 0 t =100ns, t =0.6ns, I and V averaging window: t =ns to t =60ns, extraction of p r TLP TLP 1 2 dynamic resistance using squares fit to TLP characteristics between I =10A and TLP1 I =50A. Please refer to Application Note AN210[1] TLP2 Final Data Sheet 8 Revision 1.0, 2013-12-12
ESD105-B1-02 Series Typical Characteristics at T = 25°C, unless otherwise specified A 7 ESD105-B1-02series R DYN 6 5 4 3 R = 0.9 Ω DYN 2 1 ] A [ 0 P P I -1 -2 -3 R = 0.9 Ω DYN -4 -5 -6 -7 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 V [V] CL Figure8 Pulse current (IEC61000-4-5) versus clamping voltage: I =f(V ) PP CL Final Data Sheet 9 Revision 1.0, 2013-12-12
ESD105-B1-02 Series Typical Characteristics at T = 25°C, unless otherwise specified A 150 Scope: 6 GHz, 20 GS/s 125 100 V = 135 V CL-max-peak 75 ] V [ L C V = 10 V V 50 CL-30ns-peak 25 0 -25 -50 0 50 100 150 200 250 300 350 400 450 t [ns] p Figure9 IEC61000-4-2: V =f (t), 8kV positive pulse from pin 1 to pin 2 CL 25 Scope: 6 GHz, 20 GS/s 0 -25 -50 ] V [ L C V -75 V = -134 V CL-max-peak -100 V = -11 V CL-30ns-peak -125 -150 -50 0 50 100 150 200 250 300 350 400 450 t [ns] p Figure10 IEC61000-4-2: V =f (t), 8kV negative pulse from pin 1 to pin 2 CL Final Data Sheet 10 Revision 1.0, 2013-12-12
ESD105-B1-02 Series Typical Characteristics at T = 25°C, unless otherwise specified A 200 Scope: 6 GHz, 20 GS/s 175 150 125 V = 183 V 100 CL-max-peak ] V [ 75 L C V = 14 V V CL-30ns-peak 50 25 0 -25 -50 -50 0 50 100 150 200 250 300 350 400 450 t [ns] p Figure11 IEC61000-4-2: V =f (t), 15kV positive pulse from pin 1 to pin 2 CL 50 Scope: 6 GHz, 20 GS/s 25 0 -25 -50 ] V [ -75 L C V -100 V = -185 V CL-max-peak -125 -150 V = -14 V CL-30ns-peak -175 -200 -50 0 50 100 150 200 250 300 350 400 450 t [ns] p Figure12 IEC61000-4-2: V =f (t), 15kV negative pulse from pin 1 to pin 2 CL Final Data Sheet 11 Revision 1.0, 2013-12-12
ESD105-B1-02 Series Application Information 4 Application Information Insertion Loss Networkanalysor Networkanalysor in the application 50 Ohm port1 50 Ohm port2 Line Line ESD105-B1-02series ESD105-B1-02series_insertion_loss.vsd Figure13 Insertion loss measured in 50Ω environment 0 -1 ] B d [ -2 s s o L n o ti -3 r e s n I -4 ESD105-B1-TSLP 0V / 3dB @ 14410MHz ESD105-B1-TSSLP 0V / 3dB @ 18142MHz -5 1 10 100 1000 10000 f [MHz] Figure14 Insertion loss vs. frequency of ESD105-B1-02xx in a 50Ω system Final Data Sheet 12 Revision 1.0, 2013-12-12
ESD105-B1-02 Series Application Information r cto Protected signal line ESD e I/O sensitive n n o device C 1 The protection diode should be placed very close to the location where the ESD or other transients can occur to keep loops and inductances as small as possible . Pin 2(or pin 1) should be connected directly to a ground plane on the board. 2 Application_ESD5V3S1B-02LS.vsd Figure15 Single line, bi-directional ESD / Transient protection Final Data Sheet 13 Revision 1.0, 2013-12-12
ESD105-B1-02 Series Package Information 5 Package Information 5.1 TSSLP-2-4 Top view Bottom view 0.31+-00..0021 0.32±0.05 2 5 55 ±0.0 0.3 62 0. 1 Cathode 0.05 MAX. 0.26±0.0351) 1)35 0 marking 0. ± 2 0. 1) Dimension applies to plated terminals TSSLP-2-3-PO V01 Figure16 TSSLP-2-4 Package outline 0.32 0.24 0.27 0.19 4 1 0. 2 7 6 5 0. 0. 9 1 9 0. 0.24 0.1 Copper Solder mask Stencil apertures TSSLP-2-3-FP V02 Figure17 TSSLP-2-4 Footprint 4 0.35 Tape type Ex Ey Punched Tape 0.43 0.73 Ey Embossed Tape 0.37 0.67 8 Deliveries can be both tape types (no selection possible). Specification allows identical processing (pick & place) by users. Cathode Ex marking TSSLP-2-3-TP V03 Figure18 TSSLP-2-4 Packing (cid:16)(cid:17)(cid:18)(cid:7)(cid:8)(cid:19)(cid:6)(cid:7)(cid:7) (cid:15) (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:7)(cid:8)(cid:9)(cid:3)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14) Figure19 TSSLP-2-4 Marking (example) Final Data Sheet 14 Revision 1.0, 2013-12-12
ESD105-B1-02 Series Package Information 5.2 TSLP-2-20 Top view Bottom view 0.31+0.01 -0.02 0.05 MAX. 0.6±0.05 5 2 0 0.65±0. 1 1±0.05 Cathode 0.5±0.0351) 1)35 0 marking 0. ± 5 2 1) Dimension applies to plated terminals 0. TSLP-2-19, -20-PO V01 Figure20 TSLP-2-20 Package outline 0.6 5 0.45 8 3 2 0. 0. 3 0. 3 1 9 0. 8 3 0.35 0.28 0. Copper Solder mask Stencil apertures TSLP-2-19, -20-FP V01 Figure21 TSLP-2-20 Footprint 4 0.4 Cathode marking 16 1. 8 0.76 TSLP-2-19, -20-TP V02 Figure22 TSLP-2-20 Packing Type code 12 Cathode marking TSLP-2-19, -20-MK V01 Figure23 TSLP-2-20 Marking (example) Final Data Sheet 15 Revision 1.0, 2013-12-12
ESD105-B1-02 Series References References [1] Infineon Technologies AG, “Effective ESD Protection Design at System Level Using VF-TLP Characterization Methodology”, Application Note 210, RF and Protection Devices, April 22, 2010, Rev.1.0 [2] Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages Final Data Sheet 16 Revision 1.0, 2013-12-12
w w w . i n f i n e o n . c o m Published by Infineon Technologies AG