MAX 7000A Includes MAX 7000AE Programmable Logic ® Device September 2003, ver. 4.5 Data Sheet Features... ■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table1) ■ 3.3-V in-system programmability (ISP) through the built-in IEEEStd.1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532 – EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532 ■ Built-in boundary-scan test (BST) circuitry compliant with IEEEStd.1149.1 ■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71 ■ Enhanced ISP features – Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices) – ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices) – Pull-up resistor on I/O pins during in-system programming ■ Pin-compatible with the popular 5.0-V MAX7000S devices ■ High-density PLDs ranging from 600 to 10,000 usable gates ■ Extended temperature range f For information on in-system programmable 5.0-V MAX 7000 or 2.5-V MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet. Altera Corporation 1 DS-M7000A-4.5

MAX 7000A Programmable Logic Device Data Sheet Table 1.MAX7000A Device Features Feature EPM7032AE EPM7064AE EPM7128AE EPM7256AE EPM7512AE Usable gates 600 1,250 2,500 5,000 10,000 Macrocells 32 64 128 256 512 Logic array blocks 2 4 8 16 32 Maximum user I/O 36 68 100 164 212 pins t (ns) 4.5 4.5 5.0 5.5 7.5 PD t (ns) 2.9 2.8 3.3 3.9 5.6 SU t (ns) 2.5 2.5 2.5 2.5 3.0 FSU t (ns) 3.0 3.1 3.4 3.5 4.7 CO1 f (MHz) 227.3 222.2 192.3 172.4 116.3 CNT ...and More ■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3MHz Features ■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels ■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space- saving FineLine BGATM, and plastic J-lead chip carrier (PLCC) packages ■ Supports hot-socketing in MAX 7000AE devices ■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance ■ PCI-compatible ■ Bus-friendly architecture, including programmable slew-rate control ■ Open-drain output option ■ Programmable macrocell registers with individual clear, preset, clock, and clock enable controls ■ Programmable power-up states for macrocell registers in MAX 7000AE devices ■ Programmable power-saving mode for 50% or greater power reduction in each macrocell ■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell ■ Programmable security bit for protection of proprietary designs ■ 6 to 10 pin- or logic-driven output enable signals ■ Two global clock signals with optional inversion ■ Enhanced interconnect resources for improved routability ■ Fast input setup times provided by a dedicated path from I/O pin to macrocell registers ■ Programmable output slew-rate control ■ Programmable ground pins 2 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet ■ Software design support and automatic place-and-route provided by Altera’s development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest ■ Programming support with Altera’s Master Programming Unit (MPU), MasterBlasterTM serial/universal serial bus (USB) communications cable, ByteBlasterMVTM parallel port download cable, and BitBlasterTM serial download cable, as well as programming hardware from third-party manufacturers and any JamTM STAPL File (.jam), Jam Byte-Code File (.jbc), or Serial Vector Format File- (.svf) capable in-circuit tester General MAX 7000A (including MAX 7000AE) devices are high-density, high- performance devices based on Altera’s second-generation MAX Description architecture. Fabricated with advanced CMOS technology, the EEPROM- based MAX7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCILocal Bus Specification, Revision2.2. See Table2. Table 2.MAX7000A Speed Grades Device Speed Grade -4 -5 -6 -7 -10 -12 EPM7032AE v v v EPM7064AE v v v EPM7128A v v v v EPM7128AE v v v EPM7256A v v v v EPM7256AE v v v EPM7512AE v v v Altera Corporation 3

MAX 7000A Programmable Logic Device Data Sheet The MAX7000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density integration of SSI, MSI, and LSI logic functions. It easily integrates multiple devices including PALs, GALs, and 22V10s devices. MAX7000A devices are available in a wide range of packages, including PLCC, BGA, FineLineBGA, Ultra FineLine BGA, PQFP, and TQFP packages. See Table3 and Table4. Table 3.MAX7000A Maximum User I/O Pins Note (1) Device 44-Pin PLCC 44-Pin TQFP 49-Pin Ultra 84-Pin PLCC 100-Pin 100-Pin FineLine TQFP FineLine BGA (2) BGA (3) EPM7032AE 36 36 EPM7064AE 36 36 41 68 68 EPM7128A 68 84 84 EPM7128AE 68 84 84 EPM7256A 84 EPM7256AE 84 84 EPM7512AE Table 4.MAX7000A Maximum User I/O Pins Note (1) Device 144-Pin TQFP 169-Pin Ultra 208-Pin PQFP 256-Pin BGA 256-Pin FineLine FineLine BGA (2) BGA (3) EPM7032AE EPM7064AE EPM7128A 100 100 EPM7128AE 100 100 100 EPM7256A 120 164 164 EPM7256AE 120 164 164 EPM7512AE 120 176 212 212 Notes to tables: (1) When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O pins become JTAG pins. (2) All Ultra FineLine BGA packages are footprint-compatible via the SameFrameTM feature. Therefore, designers can design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 15 for more details. (3) All FineLine BGA packages are footprint-compatible via the SameFrame feature. Therefore, designers can design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 15 for more details. 4 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet MAX7000A devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX7000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. MAX7000A devices contain from 32 to 512 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and high- speed parallel expander product terms, providing up to 32 product terms per macrocell. MAX7000A devices provide programmable speed/power optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX7000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. The output drivers of all MAX7000A devices can be set for 2.5V or 3.3V, and all input pins are 2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX7000A devices to be used in mixed-voltage systems. MAX7000A devices are supported by Altera development systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX-workstation-based EDA tools. The software runs on Windows-based PCs, as well as Sun SPARCstation, and HP9000 Series 700/800 workstations. f For more information on development tools, see the MAX+PLUSII Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet. Altera Corporation 5

MAX 7000A Programmable Logic Device Data Sheet Functional The MAX7000A architecture includes the following elements: Description ■ Logic array blocks (LABs) ■ Macrocells ■ Expander product terms (shareable and parallel) ■ Programmable interconnect array ■ I/O control blocks The MAX7000A architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure1 shows the architecture of MAX7000A devices. 6 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Figure 1. MAX7000A Device Block Diagram INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 INPUT/GCLRn 6 or 10 Output Enables (1) 6 or 10 Output Enables (1) 2 to 16 LAB A LAB B 2 to 16 I/O 2 to 16 Macrocells 36 36 Macrocells 2 to 16 I/O 2 to 16 I/O Control 1 to 16 17 to 32 Control 2 to 16 I/O Block Block 16 16 6 2 to 16 2 to 16 6 2 to 16 LAB C PIA LAB D 2 to 16 2 to 16 I/O CoI/nOtrol 2 to 16 M3a3c rtooc 4e8lls 36 36 M4a9c rtooc 6e4lls 2 to 16 CoI/nOtrol 2 to 16 I/O Block Block 16 16 6 2 to 16 2 to 16 6 Note: (1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enables. EPM7512AE devices have 10 output enables. Logic Array Blocks The MAX7000A device architecture is based on the linking of high-performance LABs. LABs consist of 16-macrocell arrays, as shown in Figure1. Multiple LABs are linked together via the PIA, a global bus that is fed by all dedicated input pins, I/O pins, and macrocells. Each LAB is fed by the following signals: ■ 36 signals from the PIA that are used for general logic inputs ■ Global controls that are used for secondary register functions ■ Direct input paths from I/O pins to the registers that are used for fast setup times Altera Corporation 7

MAX 7000A Programmable Logic Device Data Sheet Macrocells MAX7000A macrocells can be individually configured for either sequential or combinatorial logic operation. The macrocells consist of three functional blocks: the logic array, the product-term select matrix, and the programmable register. Figure2 shows a MAX7000A macrocell. Figure 2. MAX7000A Macrocell Global Global LAB Local Array Clear Clocks From 2 I/O pin Parallel Logic Expanders Fast Input Programmable (from other Select Register macrocells) Register Bypass To I/O Control PRN Block D/T Q Product- Clock/ Term Enable ENA Select Select CLRN Matrix VCC Clear Select To PIA Shared Logic Expanders 36 Signals 16 Expander from PIA Product Terms Combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. The product-term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocell’s register preset, clock, and clock enable control functions. Two kinds of expander product terms (“expanders”) are available to supplement macrocell logic resources: ■ Shareable expanders, which are inverted product terms that are fed back into the logic array ■ Parallel expanders, which are product terms borrowed from adjacent macrocells The Altera development system automatically optimizes product-term allocation according to the logic requirements of the design. 8 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes: ■ Global clock signal. This mode achieves the fastest clock-to-output performance. ■ Global clock signal enabled by an active-high clock enable. A clock enable is generated by a product term. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. ■ Array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. Two global clock signals are available in MAX7000A devices. As shown in Figure1, these global clock signals can be the true or the complement of either of the global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figure2, the product-term select matrix allocates product terms to control these operations. Although the product-term-driven preset and clear from the register are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active-low dedicated global clear pin (GCLRn). Upon power-up, each register in a MAX 7000AE device may be set to either a high or low state. This power-up state is specified at design entry. Upon power-up, each register in EPM7128A and EPM7256A devices are set to a low state. All MAX7000A I/O pins have a fast input path to a macrocell register. This dedicated path allows a signal to bypass the PIA and combinatorial logic and be clocked to an input D flipflop with an extremely fast (as low as 2.5ns) input setup time. Altera Corporation 9

MAX 7000A Programmable Logic Device Data Sheet Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, more complex logic functions require additional product terms. Another macrocell can be used to supply the required logic resources. However, the MAX7000A architecture also offers both shareable and parallel expander product terms that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. A small delay (t ) is incurred when SEXP shareable expanders are used. Figure3 shows how shareable expanders can feed multiple macrocells. Figure 3. MAX 7000A Shareable Expanders Shareable expanders can be shared by any or all macrocells in an LAB. Macrocell Product-Term Logic Product-Term Select Matrix Macrocell Product-Term Logic 36 Signals 16 Shared from PIA Expanders 10 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. The compiler can allocate up to three sets of up to fiveparallel expanders to the macrocells that require additional product terms. Each set of five parallel expanders incurs a small, incremental timing delay (t ). For PEXP example, if a macrocell requires 14 product terms, the compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms, and the second set includes fourproduct terms, increasing the total delay by 2×t . PEXP Two groups of eight macrocells within each LAB (e.g., macrocells 1 through 8 and 9through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lower- numbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of eight, the lowest-numbered macrocell can only lend parallel expanders, and the highest-numbered macrocell can only borrow them. Figure4 shows how parallel expanders can be borrowed from a neighboring macrocell. Altera Corporation 11

MAX 7000A Programmable Logic Device Data Sheet Figure 4. MAX 7000A Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. From Previous Macrocell Preset Product- Macrocell Term Select Product- Matrix Term Logic Clock Clear Preset Product- Macrocell Term Product- Select Term Logic Matrix Clock Clear To Next Macrocell 36 Signals 16 Shared from PIA Expanders Programmable Interconnect Array Logic is routed between LABs on the PIA. This global bus is a programmable path that connects any signal source to any destination on the device. All MAX7000A dedicated inputs, I/O pins, and macrocell outputs feed the PIA, which makes the signals available throughout the entire device. Only the signals required by each LAB are actually routed from the PIA into the LAB. Figure5 shows how the PIA signals are routed into the LAB. An EEPROM cell controls one input to a 2-input AND gate, which selects a PIA signal to drive into the LAB. 12 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Figure 5. MAX 7000A PIA Routing To LAB PIA Signals While the routing delays of channel-based routing schemes in masked or FPGAs are cumulative, variable, and path-dependent, the MAX7000A PIA has a predictable delay. The PIA makes a design’s timing performance easy to predict. I/O Control Blocks The I/O control block allows each I/O pin to be individually configured for input, output, or bidirectional operation. All I/O pins have a tri-state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or V . Figure6 shows the I/O CC control block for MAX7000A devices. The I/O control block has 6 or 10global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins, or a subset of the I/O macrocells. Altera Corporation 13

MAX 7000A Programmable Logic Device Data Sheet Figure 6. I/O Control Block of MAX7000A Devices 6 or 10 Global Output Enable Signals(1) PIA OE Select Multiplexer VCC To Other I/O Pins GND From Macrocell Open-Drain Output Slew-Rate Control Fast Input to Macrocell Register To PIA Note: (1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enable signals. EPM7512AE devices have 10 output enable signals. When the tri-state buffer control is connected to ground, the output is tri-stated (high impedance) and the I/O pin can be used as a dedicated input. When the tri-state buffer control is connected to V , the output is CC enabled. The MAX7000A architecture provides dual I/O feedback, in which macrocell and pin feedbacks are independent. When an I/O pin is configured as an input, the associated macrocell can be used for buried logic. 14 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet SameFrame MAX 7000A devices support the SameFrame pin-out feature for FineLine BGA packages. The SameFrame pin-out feature is the Pin-Outs arrangement of balls on FineLine BGA packages such that the lower-ball- count packages form a subset of the higher-ball-count packages. SameFrame pin-outs provide the flexibility to migrate not only from device to device within the same package, but also from one package to another. A given printed circuit board (PCB) layout can support multiple device density/package combinations. For example, a single board layout can support a range of devices from an EPM7128AE device in a 100-pin FineLine BGA package to an EPM7512AE device in a 256-pin FineLineBGA package. The Altera design software provides support to design PCBs with SameFrame pin-out devices. Devices can be defined for present and future use. The software generates pin-outs describing how to lay out a board to take advantage of this migration (see Figure7). Figure 7. SameFrame Pin-Out Example Printed Circuit Board Designed for 256-Pin FineLine BGA Package 100-Pin 256-Pin FineLine FineLine BGA BGA 100-Pin FineLine BGA Package 256-Pin FineLine BGA Package (Reduced I/O Count or (Increased I/O Count or Logic Requirements) Logic Requirements) Altera Corporation 15

MAX 7000A Programmable Logic Device Data Sheet In-System MAX7000A devices can be programmed in-system via an industry- standard 4-pin IEEE Std. 1149.1 (JTAG) interface. ISP offers quick, efficient Programma- iterations during design development and debugging cycles. The bility MAX7000A architecture internally generates the high programming voltages required to program EEPROM cells, allowing in-system programming with only a single 3.3-V power supply. During in-system programming, the I/O pins are tri-stated and weakly pulled-up to eliminate board conflicts. The pull-up value is nominally 50 kΩ. MAX7000AE devices have an enhanced ISP algorithm for faster programming. These devices also offer an ISP_Done bit that provides safe operation when in-system programming is interrupted. This ISP_Done bit, which is the last bit programmed, prevents all I/O pins from driving until the bit is programmed. This feature is only available in EPM7032AE, EPM7064AE, EPM7128AE, EPM7256AE, and EPM7512AE devices. ISP simplifies the manufacturing flow by allowing devices to be mounted on a PCB with standard pick-and-place equipment before they are programmed. MAX7000A devices can be programmed by downloading the information via in-circuit testers, embedded processors, the Altera MasterBlaster serial/USB communications cable, ByteBlasterMV parallel port download cable, and BitBlaster serial download cable. Programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., QFP packages) due to device handling. MAX7000A devices can be reprogrammed after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem. In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. A constant algorithm uses a pre- defined (non-adaptive) programming sequence that does not take advantage of adaptive algorithm programming time improvements. Some in-circuit testers cannot program using an adaptive algorithm. Therefore, a constant algorithm must be used. MAX 7000AE devices can be programmed with either an adaptive or constant (non-adaptive) algorithm. EPM7128A and EPM7256A device can only be programmed with an adaptive algorithm; users programming these two devices on platforms that cannot use an adaptive algorithm should use EPM7128AE and EPM7256AE devices. The Jam Standard Test and Programming Language (STAPL), JEDEC standard JESD 71, can be used to program MAX 7000A devices with in- circuit testers, PCs, or embedded processors. 16 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet f For more information on using the Jam STAPL language, see Application Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor) and Application Note 122 (Using Jam STAPL for ISP & ICR via an Embedded Processor). ISP circuitry in MAX 7000AE devices is compliant with the IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors. Programming Sequence During in-system programming, instructions, addresses, and data are shifted into the MAX 7000A device through the TDI input pin. Data is shifted out through the TDO output pin and compared against the expected data. Programming a pattern into the device requires the following six ISP stages. A stand-alone verification of a programmed pattern involves only stages 1, 2, 5, and 6. 1. Enter ISP. The enter ISP stage ensures that the I/O pins transition smoothly from user mode to ISP mode. The enter ISP stage requires 1ms. 2. Check ID. Before any program or verify process, the silicon ID is checked. The time required to read this silicon ID is relatively small compared to the overall programming time. 3. Bulk Erase. Erasing the device in-system involves shifting in the instructions to erase the device and applying one erase pulse of 100ms. 4. Program. Programming the device in-system involves shifting in the address and data and then applying the programming pulse to program the EEPROM cells. This process is repeated for each EEPROM address. 5. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address. 6. Exit ISP. An exit ISP stage ensures that the I/O pins transition smoothly from ISP mode to user mode. The exit ISP stage requires 1ms. Altera Corporation 17

MAX 7000A Programmable Logic Device Data Sheet Programming Times The time required to implement each of the six programming stages can be broken into the following two elements: ■ A pulse time to erase, program, or read the EEPROM cells. ■ A shifting time based on the test clock (TCK) frequency and the number of TCK cycles to shift instructions, address, and data into the device. By combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the TCK frequency, the number of devices, and specific target device(s). Because different ISP-capable devices have a different number of EEPROM cells, both the total fixed and total variable times are unique for a single device. Programming a Single MAX 7000A Device The time required to program a single MAX 7000A device in-system can be calculated from the following formula: Cycle PTCK t = t +-------------------------------- PROG PPULSE f TCK where: t = Programming time PROG t = Sum of the fixed times to erase, program, and PPULSE verify the EEPROM cells Cycle = Number of TCK cycles to program a device PTCK f = TCK frequency TCK The ISP times for a stand-alone verification of a single MAX 7000A device can be calculated from the following formula: Cycle VTCK t = t +-------------------------------- VER VPULSE f TCK where: t = Verify time VER t = Sum of the fixed times to verify the EEPROM cells VPULSE Cycle = Number of TCK cycles to verify a device VTCK 18 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet The programming times described in Tables5 through 7 are associated with the worst-case method using the enhanced ISP algorithm. Table 5.MAX 7000A t & Cycle Values PULSE TCK Device Programming Stand-Alone Verification t (s) Cycle t (s) Cycle PPULSE PTCK VPULSE VTCK EPM7032AE 2.00 55,000 0.002 18,000 EPM7064AE 2.00 105,000 0.002 35,000 EPM7128AE 2.00 205,000 0.002 68,000 EPM7256AE 2.00 447,000 0.002 149,000 EPM7512AE 2.00 890,000 0.002 297,000 EPM7128A(1) 5.11 832,000 0.03 528,000 EPM7256A(1) 6.43 1,603,000 0.03 1,024,000 Tables6 and 7 show the in-system programming and stand alone verification times for several common test clock frequencies. Table 6.MAX 7000A In-System Programming Times for Different Test Clock Frequencies Device f Units TCK 10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz EPM7032AE 2.01 2.01 2.03 2.06 2.11 2.28 2.55 3.10 s EPM7064AE 2.01 2.02 2.05 2.11 2.21 2.53 3.05 4.10 s EPM7128AE 2.02 2.04 2.10 2.21 2.41 3.03 4.05 6.10 s EPM7256AE 2.05 2.09 2.23 2.45 2.90 4.24 6.47 10.94 s EPM7512AE 2.09 2.18 2.45 2.89 3.78 6.45 10.90 19.80 s EPM7128A(1) 5.19 5.27 5.52 5.94 6.77 9.27 13.43 21.75 s EPM7256A(1) 6.59 6.75 7.23 8.03 9.64 14.45 22.46 38.49 s Altera Corporation 19

MAX 7000A Programmable Logic Device Data Sheet Table 7.MAX 7000A Stand-Alone Verification Times for Different Test Clock Frequencies Device f Units TCK 10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz EPM7032AE 0.00 0.01 0.01 0.02 0.04 0.09 0.18 0.36 s EPM7064AE 0.01 0.01 0.02 0.04 0.07 0.18 0.35 0.70 s EPM7128AE 0.01 0.02 0.04 0.07 0.14 0.34 0.68 1.36 s EPM7256AE 0.02 0.03 0.08 0.15 0.30 0.75 1.49 2.98 s EPM7512AE 0.03 0.06 0.15 0.30 0.60 1.49 2.97 5.94 s EPM7128A(1) 0.08 0.14 0.29 0.56 1.09 2.67 5.31 10.59 s EPM7256A(1) 0.13 0.24 0.54 1.06 2.08 5.15 10.27 20.51 s Note to tables: (1) EPM7128A and EPM7256A devices can only be programmed with an adaptive algorithm; users programming these two devices on platforms that cannot use an adaptive algorithm should use EPM7128AE and EPM7256AE devices. Programming MAX7000A devices can be programmed on Windows-based PCs with an Altera Logic Programmer card, the MPU, and the appropriate device with External adapter. The MPU performs continuity checks to ensure adequate Hardware electrical contact between the adapter and the device. f For more information, see the Altera Programming Hardware Data Sheet. The Altera software can use text- or waveform-format test vectors created with the Altera Text Editor or Waveform Editor to test the programmed device. For added design verification, designers can perform functional testing to compare the functional device behavior with the results of simulation. Data I/O, BP Microsystems, and other programming hardware manufacturers provide programming support for Altera devices. f For more information, see Programming Hardware Manufacturers. IEEE Std. MAX7000A devices include the JTAG BST circuitry defined by IEEE Std. 1149.1. Table8 describes the JTAG instructions supported by MAX7000A 1149.1 (JTAG) devices. The pin-out tables, available from the Altera web site Boundary-Scan (http://www.altera.com), show the location of the JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are Support available as user I/O pins. 20 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Table 8.MAX 7000A JTAG Instructions JTAG Instruction Description SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation IDCODE Selects the IDCODE register and places it between the TDI and TDO pins, allowing the IDCODE to be serially shifted out of TDO USERCODE Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE value to be shifted out of TDO. The USERCODE instruction is available for MAX 7000AE devices only UESCODE These instructions select the user electronic signature (UESCODE) and allow the UESCODE to be shifted out of TDO. UESCODE instructions are available for EPM7128A and EPM7256A devices only. ISP Instructions These instructions are used when programming MAX7000A devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, or BitBlaster download cable, or using a Jam STAPL File, JBC File, or SVF File via an embedded processor or test equipment. Altera Corporation 21

MAX 7000A Programmable Logic Device Data Sheet The instruction register length of MAX 7000A devices is 10 bits. The user electronic signature (UES) register length in MAX 7000A devices is 16 bits. The MAX 7000AE USERCODE register length is 32 bits. Tables9 and 10 show the boundary-scan register length and device IDCODE information for MAX 7000A devices. Table 9.MAX 7000A Boundary-Scan Register Length Device Boundary-Scan Register Length EPM7032AE 96 EPM7064AE 192 EPM7128A 288 EPM7128AE 288 EPM7256A 480 EPM7256AE 480 EPM7512AE 624 Table 10.32-Bit MAX 7000A Device IDCODE Note (1) Device IDCODE (32 Bits) Version Part Number (16 Bits) Manufacturer’s 1 (1 Bit) (4 Bits) Identity (11 Bits) (2) EPM7032AE 0001 0111 0000 0011 0010 00001101110 1 EPM7064AE 0001 0111 0000 0110 0100 00001101110 1 EPM7128A 0000 0111 0001 0010 1000 00001101110 1 EPM7128AE 0001 0111 0001 0010 1000 00001101110 1 EPM7256A 0000 0111 0010 0101 0110 00001101110 1 EPM7256AE 0001 0111 0010 0101 0110 00001101110 1 EPM7512AE 0001 0111 0101 0001 0010 00001101110 1 Notes: (1) The most significant bit (MSB) is on the left. (2) The least significant bit (LSB) for all JTAG IDCODEs is 1. f See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) for more information on JTAG BST. 22 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Figure8 shows timing information for the JTAG signals. Figure 8. MAX 7000A JTAG Waveforms TMS TDI tJCP tJCH tJCL tJPSU tJPH TCK tJPZX tJPCO tJPXZ TDO t t JSSU JSH Signal to Be Captured tJSZX tJSCO tJSXZ Signal to Be Driven Table11 shows the JTAG timing parameters and values for MAX7000A devices. Table 11.JTAG Timing Parameters & Values for MAX7000A Devices Note (1) Symbol Parameter Min Max Unit t TCK clock period 100 ns JCP t TCK clock high time 50 ns JCH t TCK clock low time 50 ns JCL t JTAG port setup time 20 ns JPSU t JTAG port hold time 45 ns JPH t JTAG port clock to output 25 ns JPCO t JTAG port high impedance to valid output 25 ns JPZX t JTAG port valid output to high impedance 25 ns JPXZ t Capture register setup time 20 ns JSSU t Capture register hold time 45 ns JSH t Update register clock to output 25 ns JSCO t Update register high impedance to valid output 25 ns JSZX t Update register valid output to high impedance 25 ns JSXZ Note: (1) Timing parameters shown in this table apply for all specified VCCIO levels. Altera Corporation 23

MAX 7000A Programmable Logic Device Data Sheet Programmable MAX7000A devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. This Speed/Power feature allows total power dissipation to be reduced by 50% or more Control because most logic applications require only a small fraction of all gates to operate at maximum frequency. The designer can program each individual macrocell in a MAX7000A device for either high-speed (i.e., with the Turbo BitTM option turned on) or low-power operation (i.e., with the Turbo Bit option turned off). As a result, speed-critical paths in the design can run at high speed, while the remaining paths can operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (t ) for the t , t , t , LPA LAD LAC IC t , t , t , and t parameters. EN SEXP ACL CPPW Output MAX7000A device outputs can be programmed to meet a variety of system-level requirements. Configuration MultiVolt I/O Interface The MAX7000A device architecture supports the MultiVolt I/O interface feature, which allows MAX7000A devices to connect to systems with differing supply voltages. MAX7000A devices in all packages can be set for 2.5-V, 3.3-V, or 5.0-V I/O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). The VCCIO pins can be connected to either a 3.3-V or 2.5-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 2.5-V power supply, the output levels are compatible with 2.5-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is at 3.3V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with V levels lower than 3.0V CCIO incur a slightly greater timing delay of t instead of t . Inputs can OD2 OD1 always be driven by 2.5-V, 3.3-V, or 5.0-V signals. Table12 describes the MAX 7000A MultiVolt I/O support. Table 12.MAX 7000A MultiVolt I/O Support V Voltage Input Signal (V) Output Signal (V) CCIO 2.5 3.3 5.0 2.5 3.3 5.0 2.5 v v v v 3.3 v v v v v 24 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Open-Drain Output Option MAX7000A devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. This output can also provide an additional wired-OR plane. Open-drain output pins on MAX 7000A devices (with a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high V . When the open-drain pin is active, it will drive low. When the pin is IH inactive, the resistor will pull up the trace to 5.0 V to meet CMOS V OH requirements. The open-drain pin will only drive low or tri-state; it will never drive high. The rise time is dependent on the value of the pull-up resistor and load impedance. The I current specification should be OL considered when selecting a pull-up resistor. Programmable Ground Pins Each unused I/O pin on MAX 7000A devices may be used as an additional ground pin. In EPM7128A and EPM7256A devices, utilizing unused I/O pins as additional ground pins requires using the associated macrocell. In MAX 7000AE devices, this programmable ground feature does not require the use of the associated macrocell; therefore, the buried macrocell is still available for user logic. Slew-Rate Control The output buffer for each MAX7000A I/O pin has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. When the configuration cell is turned off, the slew rate is set for low-noise performance. Each I/O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate on a pin-by-pin basis. The slew rate control affects both the rising and falling edges of the output signal. Altera Corporation 25

MAX 7000A Programmable Logic Device Data Sheet Power Because MAX 7000A devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up Sequencing & sequence. The V and V power planes can be powered in any CCIO CCINT Hot-Socketing order. Signals can be driven into MAX 7000AE devices before and during power- up (and power-down) without damaging the device. Additionally, MAX7000AE devices do not drive out during power-up. Once operating conditions are reached, MAX 7000AE devices operate as specified by the user. MAX 7000AE device I/O pins will not source or sink more than 300 µA of DC current during power-up. All pins can be driven up to 5.75 V during hot-socketing, except the OE1 and GLCRn pins. The OE1 and GLCRn pins can be driven up to 3.6 V during hot-socketing. After V and V CCINT CCIO reach the recommended operating conditions, these two pins are 5.0-V tolerant. EPM7128A and EPM7256A devices do not support hot-socketing and may drive out during power-up. Design Security All MAX7000A devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security because programmed data within EEPROM cells is invisible. The security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. Generic Testing MAX7000A devices are fully tested. Complete testing of each programmable EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in Figure9. Test patterns can be used and then erased during early stages of the production flow. 26 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Figure 9. MAX7000A AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions VCC of multiple outputs should be avoided for accurate measurement. Threshold tests 703 Ω must not be performed under AC [521 Ω] conditions. Large-amplitude, fast-ground- Device To Test current transients normally occur as the Output System device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between 586 Ω the device ground pin and the test system [481 Ω] C1 (includes jig ground, significant reductions in capacitance) observable noise immunity can result. Device input rise and fall Numbers in brackets are for 2.5-V times < 2 ns outputs. Numbers without brackets are for 3.3-V outputs. Operating Tables13 through 16 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and Conditions capacitance for MAX 7000A devices. Table 13.MAX7000A Device Absolute Maximum Ratings Note (1) Symbol Parameter Conditions Min Max Unit V Supply voltage With respect to ground (2) –0.5 4.6 V CC V DC input voltage –2.0 5.75 V I I DC output current, per pin –25 25 mA OUT T Storage temperature No bias –65 150 ° C STG T Ambient temperature Under bias –65 135 ° C A T Junction temperature BGA, FineLine BGA, PQFP, and 135 ° C J TQFP packages, under bias Altera Corporation 27

MAX 7000A Programmable Logic Device Data Sheet Table 14.MAX7000A Device Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit V Supply voltage for internal logic (3), (13) 3.0 3.6 V CCINT and input buffers V Supply voltage for output (3) 3.0 3.6 V CCIO drivers, 3.3-V operation Supply voltage for output (3) 2.3 2.7 V drivers, 2.5-V operation V Supply voltage during in- 3.0 3.6 V CCISP system programming V Input voltage (4) –0.5 5.75 V I V Output voltage 0 V V O CCIO T Ambient temperature Commercial range 0 70 ° C A Industrial range(5) –40 85 ° C T Junction temperature Commercial range 0 90 ° C J Industrial range(5) –40 105 ° C Extended range(5) –40 130 ° C t Input rise time 40 ns R t Input fall time 40 ns F 28 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Table 15.MAX7000A Device DC Operating Conditions Note (6) Symbol Parameter Conditions Min Max Unit V High-level input voltage 1.7 5.75 V IH V Low-level input voltage –0.5 0.8 V IL V 3.3-V high-level TTL output I = –8 mA DC, V = 3.00 V (7) 2.4 V OH OH CCIO voltage 3.3-V high-level CMOS output I = –0.1 mA DC, V = 3.00 V V – 0.2 V OH CCIO CCIO voltage (7) 2.5-V high-level output voltage I = –100 µA DC, V = 2.30 V 2.1 V OH CCIO (7) I = –1 mA DC, V = 2.30 V (7) 2.0 V OH CCIO I = –2 mA DC, V = 2.30 V (7) 1.7 V OH CCIO V 3.3-V low-level TTL output I = 8 mA DC, V = 3.00 V (8) 0.45 V OL OL CCIO voltage 3.3-V low-level CMOS output I = 0.1 mA DC, V = 3.00 V (8) 0.2 V OL CCIO voltage 2.5-V low-level output voltage I = 100 µA DC, V = 2.30 V (8) 0.2 V OL CCIO I = 1 mA DC, V = 2.30 V (8) 0.4 V OL CCIO I = 2 mA DC, V = 2.30 V (8) 0.7 V OL CCIO I Input leakage current V = –0.5 to 5.5 V (9) –10 10 µA I I I Tri-state output off-state V = –0.5 to 5.5 V (9) –10 10 µA OZ I current R Value of I/O pin pull-up resistor V = 3.0 to 3.6 V (10) 20 50 kΩ ISP CCIO during in-system programming V = 2.3 to 2.7 V (10) 30 80 kΩ CCIO or during power-up V = 2.3 to 3.6 V (11) 20 74 kΩ CCIO Table 16.MAX7000A Device Capacitance Note (12) Symbol Parameter Conditions Min Max Unit C Input pin capacitance V = 0 V, f = 1.0 MHz 8 pF IN IN C I/O pin capacitance V = 0 V, f = 1.0 MHz 8 pF I/O OUT Altera Corporation 29

MAX 7000A Programmable Logic Device Data Sheet Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) For EPM7128A and EPM7256A devices only, VCC must rise monotonically. (4) In MAX 7000AE devices, all pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before VCCINT and VCCIO are powered. (5) These devices support in-system programming for –40° to 100° C. For in-system programming support between –40° and 0° C, contact Altera Applications. (6) These values are specified under the recommended operating conditions shown in Table14 on page28. (7) The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers to high-level TTL or CMOS output current. (8) The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to low-level TTL or CMOS output current. (9) This value is specified for normal device operation. For MAX 7000AE devices, the maximum leakage current during power-up is ±300 µA. For EPM7128A and EPM7256A devices, leakage current during power-up is not specified. (10) For EPM7128A and EPM7256A devices, this pull-up exists while a device is programmed in-system. (11) For MAX 7000AE devices, this pull-up exists while devices are programmed in-system and in unprogrammed devices during power-up. (12) Capacitance is measured at 25 °C and is sample-tested only. The OE1 pin (high-voltage pin during programming) has a maximum capacitance of 20 pF. (13) The POR time for MAX 7000AE devices (except MAX 7128A and MAX 7256A devices) does not exceed 100 µs. The sufficient VCCINT voltage level for POR is 3.0 V. The device is fully initialized within the POR time after VCCINT reaches the sufficient POR voltage level. 30 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Figure10 shows the typical output drive characteristics of MAX7000A devices. Figure 10. Output Drive Characteristics of MAX7000A Devices 3.3 V MAX 7000AE Devices 2.5 V MAX 7000AE Devices 150 150 IOL IOL 100 100 TOCyuuprtirpceuantl tI (O m A) VVTeCCmCCIIpONeT = r= a3 t3.u3.r3 eV V= 25 O C TOCyuuprtirpceuantl tI (O m A) VVTeCCmCCIIpNOeT = r= a2 t3.u5.r3 eV V= 25 O C 50 50 IOH IOH 00 1 2 3 4 5 00 1 2 3 4 5 VO Output Voltage (V) VO Output Voltage (V) 3.3 V EPM7128A & EPM7256A Devices 2.5 V EPM7128A & EPM7256A Devices 120 120 IOL IOL 80 80 TOCyuuprtirpceuantl tI (O m A) VVTeCCmCCIIpONeT = r= a3 t3.u3.r3 eV V = 25 O C TOCyuuprtirpceuantl tI (O m A) VVTeCCmCCIINOpTe = r= a2 t3.u5.r3 eV V = 25 O C 40 40 IOH IOH 0 0 0 1 2 3 4 5 1 2 3 4 5 VO Output Voltage (V) VO Output Voltage (V) Timing Model MAX7000A device timing can be analyzed with the Altera software, a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure11. MAX7000A devices have predictable internal delays that enable the designer to determine the worst-case timing of any design. The software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for device-wide performance evaluation. Altera Corporation 31

MAX 7000A Programmable Logic Device Data Sheet Figure 11. MAX7000A Timing Model Internal Output Enable Delay tIOE Input Global Control Delay Delay tIN tGLOB Parallel RDegeilsatyer ODuetlpauyt DtPePIlIAaAy CLooRngDtettttriogLIEceLCAAN lilA saCDDtryerearlayy ExpantPdEeXrP Delay ttttttttSHPCRCFFSHURLDORUEMB tttttttOOOXZZZZXXXDDD123321 I/O Shared Delay Fast Expander Delay Input Delay tIO tSEXP tFIN The timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. External timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. Figure12 shows the timing relationship between internal and external delay parameters. f See Application Note 94 (Understanding MAX 7000 Timing) for more information. 32 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Figure 12. MAX 7000A Switching Waveforms tR & tF < 2 ns. Inputs are Combinatorial Mode driven at 3 V for a logic high and 0 V for a logic tIN low. All timing Input Pin characteristics are tIO measured at 1.5 V. I/O Pin tPIA PIA Delay tSEXP Shared Expander Delay tLAC , tLAD Logic Array Input tPEXP Parallel Expander Delay tCOMB Logic Array Output tOD Output Pin Global Clock Mode Global tR tCH tCL tF Clock Pin tIN Global Clock tGLOB at Register tSU tH Data or Enable (Logic Array Output) Array Clock Mode tR tACH tACL tF Input or I/O Pin tIN tIO Clock into PIA Clock into tPIA Logic Array Clock at tIC Register tSU tH Data from Logic Array tRD tPIA tCLR , tPRE tPIA Register to PIA to Logic Array tOD tOD Register Output to Pin Altera Corporation 33

MAX 7000A Programmable Logic Device Data Sheet Tables17 through 30 show EPM7032AE, EPM7064AE, EPM7128AE, EPM7256AE, EPM7512AE, EPM7128A, and EPM7256A timing information. Table 17.EPM7032AE External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit -4 -7 -10 Min Max Min Max Min Max t Input to non-registered C1 = 35 pF (2) 4.5 7.5 10 ns PD1 output t I/O input to non-registered C1 = 35 pF (2) 4.5 7.5 10 ns PD2 output t Global clock setup time (2) 2.9 4.7 6.3 ns SU t Global clock hold time (2) 0.0 0.0 0.0 ns H t Global clock setup time of 2.5 3.0 3.0 ns FSU fast input t Global clock hold time of 0.0 0.0 0.0 ns FH fast input t Global clock to output delay C1 = 35 pF 1.0 3.0 1.0 5.0 1.0 6.7 ns CO1 t Global clock high time 2.0 3.0 4.0 ns CH t Global clock low time 2.0 3.0 4.0 ns CL t Array clock setup time (2) 1.6 2.5 3.6 ns ASU t Array clock hold time (2) 0.3 0.5 0.5 ns AH t Array clock to output delay C1 = 35 pF (2) 1.0 4.3 1.0 7.2 1.0 9.4 ns ACO1 t Array clock high time 2.0 3.0 4.0 ns ACH t Array clock low time 2.0 3.0 4.0 ns ACL t Minimum pulse width for (3) 2.0 3.0 4.0 ns CPPW clear and preset t Minimum global clock (2) 4.4 7.2 9.7 ns CNT period f Maximum internal global (2), (4) 227.3 138.9 103.1 MHz CNT clock frequency t Minimum array clock period (2) 4.4 7.2 9.7 ns ACNT f Maximum internal array (2), (4) 227.3 138.9 103.1 MHz ACNT clock frequency 34 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Table 18.EPM7032AE Internal Timing Parameters (Part 1 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -4 -7 -10 Min Max Min Max Min Max t Input pad and buffer delay 0.7 1.2 1.5 ns IN t I/O input pad and buffer 0.7 1.2 1.5 ns IO delay t Fast input delay 2.3 2.8 3.4 ns FIN t Shared expander delay 1.9 3.1 4.0 ns SEXP t Parallel expander delay 0.5 0.8 1.0 ns PEXP t Logic array delay 1.5 2.5 3.3 ns LAD t Logic control array delay 0.6 1.0 1.2 ns LAC t Internal output enable delay 0.0 0.0 0.0 ns IOE t Output buffer and pad C1 = 35 pF 0.8 1.3 1.8 ns OD1 delay, slow slew rate = off V = 3.3 V CCIO t Output buffer and pad C1 = 35 pF 1.3 1.8 2.3 ns OD2 delay, slow slew rate=off (5) V = 2.5 V CCIO t Output buffer and pad C1 = 35 pF 5.8 6.3 6.8 ns OD3 delay, slow slew rate = on V = 2.5 V or 3.3 V CCIO t Output buffer enable delay, C1 = 35 pF 4.0 4.0 5.0 ns ZX1 slow slew rate = off V = 3.3 V CCIO t Output buffer enable delay, C1 = 35 pF 4.5 4.5 5.5 ns ZX2 slow slew rate = off (5) V = 2.5 V CCIO t Output buffer enable delay, C1 = 35 pF 9.0 9.0 10.0 ns ZX3 slow slew rate = on V = 3.3 V CCIO t Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 ns XZ t Register setup time 1.3 2.0 2.8 ns SU t Register hold time 0.6 1.0 1.3 ns H t Register setup time of fast 1.0 1.5 1.5 ns FSU input t Register hold time of fast 1.5 1.5 1.5 ns FH input t Register delay 0.7 1.2 1.5 ns RD t Combinatorial delay 0.6 1.0 1.3 ns COMB Altera Corporation 35

MAX 7000A Programmable Logic Device Data Sheet Table 18.EPM7032AE Internal Timing Parameters (Part 2 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -4 -7 -10 Min Max Min Max Min Max t Array clock delay 1.2 2.0 2.5 ns IC t Register enable time 0.6 1.0 1.2 ns EN t Global control delay 0.8 1.3 1.9 ns GLOB t Register preset time 1.2 1.9 2.6 ns PRE t Register clear time 1.2 1.9 2.6 ns CLR t PIA delay (2) 0.9 1.5 2.1 ns PIA t Low-power adder (6) 2.5 4.0 5.0 ns LPA 36 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Table 19.EPM7064AE External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit -4 -7 -10 Min Max Min Max Min Max t Input to non- C1 = 35 pF 4.5 7.5 10.0 ns PD1 registered output (2) t I/O input to non- C1 = 35 pF 4.5 7.5 10.0 ns PD2 registered output (2) t Global clock setup (2) 2.8 4.7 6.2 ns SU time t Global clock hold time (2) 0.0 0.0 0.0 ns H t Global clock setup 2.5 3.0 3.0 ns FSU time of fast input t Global clock hold time 0.0 0.0 0.0 ns FH of fast input t Global clock to output C1 = 35 pF 1.0 3.1 1.0 5.1 1.0 7.0 ns CO1 delay t Global clock high time 2.0 3.0 4.0 ns CH t Global clock low time 2.0 3.0 4.0 ns CL t Array clock setup time (2) 1.6 2.6 3.6 ns ASU t Array clock hold time (2) 0.3 0.4 0.6 ns AH t Array clock to output C1 = 35 pF 1.0 4.3 1.0 7.2 1.0 9.6 ns ACO1 delay (2) t Array clock high time 2.0 3.0 4.0 ns ACH t Array clock low time 2.0 3.0 4.0 ns ACL t Minimum pulse width (3) 2.0 3.0 4.0 ns CPPW for clear and preset t Minimum global clock (2) 4.5 7.4 10.0 ns CNT period f Maximum internal (2), (4) 222.2 135.1 100.0 MHz CNT global clock frequency t Minimum array clock (2) 4.5 7.4 10.0 ns ACNT period f Maximum internal (2), (4) 222.2 135.1 100.0 MHz ACNT array clock frequency Altera Corporation 37

MAX 7000A Programmable Logic Device Data Sheet Table 20.EPM7064AE Internal Timing Parameters (Part 1 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -4 -7 -10 Min Max Min Max Min Max t Input pad and buffer delay 0.6 1.1 1.4 ns IN t I/O input pad and buffer 0.6 1.1 1.4 ns IO delay t Fast input delay 2.5 3.0 3.7 ns FIN t Shared expander delay 1.8 3.0 3.9 ns SEXP t Parallel expander delay 0.4 0.7 0.9 ns PEXP t Logic array delay 1.5 2.5 3.2 ns LAD t Logic control array delay 0.6 1.0 1.2 ns LAC t Internal output enable delay 0.0 0.0 0.0 ns IOE t Output buffer and pad C1 = 35 pF 0.8 1.3 1.8 ns OD1 delay, slow slew rate = off V = 3.3 V CCIO t Output buffer and pad C1 = 35 pF 1.3 1.8 2.3 ns OD2 delay, slow slew rate=off (5) V = 2.5 V CCIO t Output buffer and pad C1 = 35 pF 5.8 6.3 6.8 ns OD3 delay, slow slew rate = on V = 2.5 V or 3.3 V CCIO t Output buffer enable delay, C1 = 35 pF 4.0 4.0 5.0 ns ZX1 slow slew rate = off V = 3.3 V CCIO t Output buffer enable delay, C1 = 35 pF 4.5 4.5 5.5 ns ZX2 slow slew rate = off (5) V = 2.5 V CCIO t Output buffer enable delay, C1 = 35 pF 9.0 9.0 10.0 ns ZX3 slow slew rate = on V = 3.3 V CCIO t Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 ns XZ t Register setup time 1.3 2.0 2.9 ns SU t Register hold time 0.6 1.0 1.3 ns H t Register setup time of fast 1.0 1.5 1.5 ns FSU input t Register hold time of fast 1.5 1.5 1.5 ns FH input t Register delay 0.7 1.2 1.6 ns RD t Combinatorial delay 0.6 0.9 1.3 ns COMB t Array clock delay 1.2 1.9 2.5 ns IC 38 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Table 20.EPM7064AE Internal Timing Parameters (Part 2 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -4 -7 -10 Min Max Min Max Min Max t Register enable time 0.6 1.0 1.2 ns EN t Global control delay 1.0 1.5 2.2 ns GLOB t Register preset time 1.3 2.1 2.9 ns PRE t Register clear time 1.3 2.1 2.9 ns CLR t PIA delay (2) 1.0 1.7 2.3 ns PIA t Low-power adder (6) 3.5 4.0 5.0 ns LPA Altera Corporation 39

MAX 7000A Programmable Logic Device Data Sheet Table 21.EPM7128AE External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit -5 -7 -10 Min Max Min Max Min Max t Input to non- C1 = 35 pF 5.0 7.5 10 ns PD1 registered output (2) t I/O input to non- C1 = 35 pF 5.0 7.5 10 ns PD2 registered output (2) t Global clock setup (2) 3.3 4.9 6.6 ns SU time t Global clock hold time (2) 0.0 0.0 0.0 ns H t Global clock setup 2.5 3.0 3.0 ns FSU time of fast input t Global clock hold time 0.0 0.0 0.0 ns FH of fast input t Global clock to output C1 = 35 pF 1.0 3.4 1.0 5.0 1.0 6.6 ns CO1 delay t Global clock high time 2.0 3.0 4.0 ns CH t Global clock low time 2.0 3.0 4.0 ns CL t Array clock setup time (2) 1.8 2.8 3.8 ns ASU t Array clock hold time (2) 0.2 0.3 0.4 ns AH t Array clock to output C1 = 35 pF 1.0 4.9 1.0 7.1 1.0 9.4 ns ACO1 delay (2) t Array clock high time 2.0 3.0 4.0 ns ACH t Array clock low time 2.0 3.0 4.0 ns ACL t Minimum pulse width (3) 2.0 3.0 4.0 ns CPPW for clear and preset t Minimum global clock (2) 5.2 7.7 10.2 ns CNT period f Maximum internal (2), (4) 192.3 129.9 98.0 MHz CNT global clock frequency t Minimum array clock (2) 5.2 7.7 10.2 ns ACNT period f Maximum internal (2), (4) 192.3 129.9 98.0 MHz ACNT array clock frequency 40 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Table 22.EPM7128AE Internal Timing Parameters (Part 1 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -5 -7 -10 Min Max Min Max Min Max t Input pad and buffer delay 0.7 1.0 1.4 ns IN t I/O input pad and buffer 0.7 1.0 1.4 ns IO delay t Fast input delay 2.5 3.0 3.4 ns FIN t Shared expander delay 2.0 2.9 3.8 ns SEXP t Parallel expander delay 0.4 0.7 0.9 ns PEXP t Logic array delay 1.6 2.4 3.1 ns LAD t Logic control array delay 0.7 1.0 1.3 ns LAC t Internal output enable delay 0.0 0.0 0.0 ns IOE t Output buffer and pad C1 = 35 pF 0.8 1.2 1.6 ns OD1 delay, slow slew rate = off V = 3.3 V CCIO t Output buffer and pad C1 = 35 pF 1.3 1.7 2.1 ns OD2 delay, slow slew rate=off (5) V = 2.5 V CCIO t Output buffer and pad C1 = 35 pF 5.8 6.2 6.6 ns OD3 delay, slow slew rate = on V = 2.5 V or 3.3 V CCIO t Output buffer enable delay, C1 = 35 pF 4.0 4.0 5.0 ns ZX1 slow slew rate = off V = 3.3 V CCIO t Output buffer enable delay, C1 = 35 pF 4.5 4.5 5.5 ns ZX2 slow slew rate = off (5) V = 2.5 V CCIO t Output buffer enable delay, C1 = 35 pF 9.0 9.0 10.0 ns ZX3 slow slew rate = on V = 3.3 V CCIO t Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 ns XZ t Register setup time 1.4 2.1 2.9 ns SU t Register hold time 0.6 1.0 1.3 ns H t Register setup time of fast 1.1 1.6 1.6 ns FSU input t Register hold time of fast 1.4 1.4 1.4 ns FH input t Register delay 0.8 1.2 1.6 ns RD t Combinatorial delay 0.5 0.9 1.3 ns COMB t Array clock delay 1.2 1.7 2.2 ns IC Altera Corporation 41

MAX 7000A Programmable Logic Device Data Sheet Table 22.EPM7128AE Internal Timing Parameters (Part 2 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -5 -7 -10 Min Max Min Max Min Max t Register enable time 0.7 1.0 1.3 ns EN t Global control delay 1.1 1.6 2.0 ns GLOB t Register preset time 1.4 2.0 2.7 ns PRE t Register clear time 1.4 2.0 2.7 ns CLR t PIA delay (2) 1.4 2.0 2.6 ns PIA t Low-power adder (6) 4.0 4.0 5.0 ns LPA 42 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Table 23.EPM7256AE External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit -5 -7 -10 Min Max Min Max Min Max t Input to non- C1 = 35 pF 5.5 7.5 10 ns PD1 registered output (2) t I/O input to non- C1 = 35 pF 5.5 7.5 10 ns PD2 registered output (2) t Global clock setup (2) 3.9 5.2 6.9 ns SU time t Global clock hold time (2) 0.0 0.0 0.0 ns H t Global clock setup 2.5 3.0 3.0 ns FSU time of fast input t Global clock hold time 0.0 0.0 0.0 ns FH of fast input t Global clock to output C1 = 35 pF 1.0 3.5 1.0 4.8 1.0 6.4 ns CO1 delay t Global clock high time 2.0 3.0 4.0 ns CH t Global clock low time 2.0 3.0 4.0 ns CL t Array clock setup time (2) 2.0 2.7 3.6 ns ASU t Array clock hold time (2) 0.2 0.3 0.5 ns AH t Array clock to output C1 = 35 pF 1.0 5.4 1.0 7.3 1.0 9.7 ns ACO1 delay (2) t Array clock high time 2.0 3.0 4.0 ns ACH t Array clock low time 2.0 3.0 4.0 ns ACL t Minimum pulse width (3) 2.0 3.0 4.0 ns CPPW for clear and preset t Minimum global clock (2) 5.8 7.9 10.5 ns CNT period f Maximum internal (2), (4) 172.4 126.6 95.2 MHz CNT global clock frequency t Minimum array clock (2) 5.8 7.9 10.5 ns ACNT period f Maximum internal (2), (4) 172.4 126.6 95.2 MHz ACNT array clock frequency Altera Corporation 43

MAX 7000A Programmable Logic Device Data Sheet Table 24.EPM7256AE Internal Timing Parameters (Part 1 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -5 -7 -10 Min Max Min Max Min Max t Input pad and buffer delay 0.7 0.9 1.2 ns IN t I/O input pad and buffer 0.7 0.9 1.2 ns IO delay t Fast input delay 2.4 2.9 3.4 ns FIN t Shared expander delay 2.1 2.8 3.7 ns SEXP t Parallel expander delay 0.3 0.5 0.6 ns PEXP t Logic array delay 1.7 2.2 2.8 ns LAD t Logic control array delay 0.8 1.0 1.3 ns LAC t Internal output enable delay 0.0 0.0 0.0 ns IOE t Output buffer and pad C1 = 35 pF 0.9 1.2 1.6 ns OD1 delay, slow slew rate = off V = 3.3 V CCIO t Output buffer and pad C1 = 35 pF 1.4 1.7 2.1 ns OD2 delay, slow slew rate=off (5) V = 2.5 V CCIO t Output buffer and pad C1 = 35 pF 5.9 6.2 6.6 ns OD3 delay, slow slew rate = on V = 2.5 V or 3.3 V CCIO t Output buffer enable delay, C1 = 35 pF 4.0 4.0 5.0 ns ZX1 slow slew rate = off V = 3.3 V CCIO t Output buffer enable delay, C1 = 35 pF 4.5 4.5 5.5 ns ZX2 slow slew rate = off (5) V = 2.5 V CCIO t Output buffer enable delay, C1 = 35 pF 9.0 9.0 10.0 ns ZX3 slow slew rate = on V = 3.3 V CCIO t Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 ns XZ t Register setup time 1.5 2.1 2.9 ns SU t Register hold time 0.7 0.9 1.2 ns H t Register setup time of fast 1.1 1.6 1.6 ns FSU input t Register hold time of fast 1.4 1.4 1.4 ns FH input t Register delay 0.9 1.2 1.6 ns RD t Combinatorial delay 0.5 0.8 1.2 ns COMB 44 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Table 24.EPM7256AE Internal Timing Parameters (Part 2 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -5 -7 -10 Min Max Min Max Min Max t Array clock delay 1.2 1.6 2.1 ns IC t Register enable time 0.8 1.0 1.3 ns EN t Global control delay 1.0 1.5 2.0 ns GLOB t Register preset time 1.6 2.3 3.0 ns PRE t Register clear time 1.6 2.3 3.0 ns CLR t PIA delay (2) 1.7 2.4 3.2 ns PIA t Low-power adder (6) 4.0 4.0 5.0 ns LPA Altera Corporation 45

MAX 7000A Programmable Logic Device Data Sheet Table 25.EPM7512AE External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit -7 -10 -12 Min Max Min Max Min Max t Input to non- C1 = 35 pF 7.5 10.0 12.0 ns PD1 registered output (2) t I/O input to non- C1 = 35 pF 7.5 10.0 12.0 ns PD2 registered output (2) t Global clock setup (2) 5.6 7.6 9.1 ns SU time t Global clock hold time (2) 0.0 0.0 0.0 ns H t Global clock setup 3.0 3.0 3.0 ns FSU time of fast input t Global clock hold time 0.0 0.0 0.0 ns FH of fast input t Global clock to output C1 = 35 pF 1.0 4.7 1.0 6.3 1.0 7.5 ns CO1 delay t Global clock high time 3.0 4.0 5.0 ns CH t Global clock low time 3.0 4.0 5.0 ns CL t Array clock setup time (2) 2.5 3.5 4.1 ns ASU t Array clock hold time (2) 0.2 0.3 0.4 ns AH t Array clock to output C1 = 35 pF 1.0 7.8 1.0 10.4 1.0 12.5 ns ACO1 delay (2) t Array clock high time 3.0 4.0 5.0 ns ACH t Array clock low time 3.0 4.0 5.0 ns ACL t Minimum pulse width (3) 3.0 4.0 5.0 ns CPPW for clear and preset t Minimum global clock (2) 8.6 11.5 13.9 ns CNT period f Maximum internal (2), (4) 116.3 87.0 71.9 MHz CNT global clock frequency t Minimum array clock (2) 8.6 11.5 13.9 ns ACNT period f Maximum internal (2), (4) 116.3 87.0 71.9 MHz ACNT array clock frequency 46 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Table 26.EPM7512AE Internal Timing Parameters (Part 1 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -7 -10 -12 Min Max Min Max Min Max t Input pad and buffer delay 0.7 0.9 1.0 ns IN t I/O input pad and buffer 0.7 0.9 1.0 ns IO delay t Fast input delay 3.1 3.6 4.1 ns FIN t Shared expander delay 2.7 3.5 4.4 ns SEXP t Parallel expander delay 0.4 0.5 0.6 ns PEXP t Logic array delay 2.2 2.8 3.5 ns LAD t Logic control array delay 1.0 1.3 1.7 ns LAC t Internal output enable delay 0.0 0.0 0.0 ns IOE t Output buffer and pad C1 = 35 pF 1.0 1.5 1.7 ns OD1 delay, slow slew rate = off V = 3.3 V CCIO t Output buffer and pad C1 = 35 pF 1.5 2.0 2.2 ns OD2 delay, slow slew rate=off (5) V = 2.5 V CCIO t Output buffer and pad C1 = 35 pF 6.0 6.5 6.7 ns OD3 delay, slow slew rate = on V = 2.5 V or 3.3 V CCIO t Output buffer enable delay, C1 = 35 pF 4.0 5.0 5.0 ns ZX1 slow slew rate = off V = 3.3 V CCIO t Output buffer enable delay, C1 = 35 pF 4.5 5.5 5.5 ns ZX2 slow slew rate = off (5) V = 2.5 V CCIO t Output buffer enable delay, C1 = 35 pF 9.0 10.0 10.0 ns ZX3 slow slew rate = on V = 3.3 V CCIO t Output buffer disable delay C1 = 5 pF 4.0 5.0 5.0 ns XZ t Register setup time 2.1 3.0 3.5 ns SU t Register hold time 0.6 0.8 1.0 ns H t Register setup time of fast 1.6 1.6 1.6 ns FSU input t Register hold time of fast 1.4 1.4 1.4 ns FH input t Register delay 1.3 1.7 2.1 ns RD t Combinatorial delay 0.6 0.8 1.0 ns COMB Altera Corporation 47

MAX 7000A Programmable Logic Device Data Sheet Table 26.EPM7512AE Internal Timing Parameters (Part 2 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -7 -10 -12 Min Max Min Max Min Max t Array clock delay 1.8 2.3 2.9 ns IC t Register enable time 1.0 1.3 1.7 ns EN t Global control delay 1.7 2.2 2.7 ns GLOB t Register preset time 1.0 1.4 1.7 ns PRE t Register clear time 1.0 1.4 1.7 ns CLR t PIA delay (2) 3.0 4.0 4.8 ns PIA t Low-power adder (6) 4.5 5.0 5.0 ns LPA 48 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Table 27.EPM7128A External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit -6 -7 -10 -12 Min Max Min Max Min Max Min Max t Input to non-registered C1 = 35 pF 6.0 7.5 10.0 12.0 ns PD1 output (2) t I/O input to non- C1 = 35 pF 6.0 7.5 10.0 12.0 ns PD2 registered output (2) t Global clock setup time (2) 4.2 5.3 7.0 8.5 ns SU t Global clock hold time (2) 0.0 0.0 0.0 0.0 ns H t Global clock setup time 2.5 3.0 3.0 3.0 ns FSU of fast input t Global clock hold time of 0.0 0.0 0.0 0.0 ns FH fast input t Global clock to output C1 = 35 pF 1.0 3.7 1.0 4.6 1.0 6.1 1.0 7.3 ns CO1 delay t Global clock high time 3.0 3.0 4.0 5.0 ns CH t Global clock low time 3.0 3.0 4.0 5.0 ns CL t Array clock setup time (2) 1.9 2.4 3.1 3.8 ns ASU t Array clock hold time (2) 1.5 2.2 3.3 4.3 ns AH t Array clock to output C1 = 35 pF 1.0 6.0 1.0 7.5 1.0 10.0 1.0 12.0 ns ACO1 delay (2) t Array clock high time 3.0 3.0 4.0 5.0 ns ACH t Array clock low time 3.0 3.0 4.0 5.0 ns ACL t Minimum pulse width for (3) 3.0 3.0 4.0 5.0 ns CPPW clear and preset t Minimum global clock (2) 6.9 8.6 11.5 13.8 ns CNT period f Maximum internal global (2), (4) 144.9 116.3 87.0 72.5 MHz CNT clock frequency t Minimum array clock (2) 6.9 8.6 11.5 13.8 ns ACNT period f Maximum internal array (2), (4) 144.9 116.3 87 72.5 MHz ACNT clock frequency Altera Corporation 49

MAX 7000A Programmable Logic Device Data Sheet Table 28.EPM7128A Internal Timing Parameters (Part 1 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -6 -7 -10 -12 Min Max Min Max Min Max Min Max t Input pad and buffer delay 0.6 0.7 0.9 1.1 ns IN t I/O input pad and buffer 0.6 0.7 0.9 1.1 ns IO delay t Fast input delay 2.7 3.1 3.6 3.9 ns FIN t Shared expander delay 2.5 3.2 4.3 5.1 ns SEXP t Parallel expander delay 0.7 0.8 1.1 1.3 ns PEXP t Logic array delay 2.4 3.0 4.1 4.9 ns LAD t Logic control array delay 2.4 3.0 4.1 4.9 ns LAC t Internal output enable 0.0 0.0 0.0 0.0 ns IOE delay t Output buffer and pad C1 = 35 pF 0.4 0.6 0.7 0.9 ns OD1 delay, slow slew rate = off V = 3.3 V CCIO t Output buffer and pad C1 = 35 pF 0.9 1.1 1.2 1.4 ns OD2 delay, slow slew rate=off (5) V = 2.5 V CCIO t Output buffer and pad C1 = 35 pF 5.4 5.6 5.7 5.9 ns OD3 delay, slow slew rate = on V = 2.5 V or 3.3 V CCIO t Output buffer enable C1 = 35 pF 4.0 4.0 5.0 5.0 ns ZX1 delay, slow slew rate = off V = 3.3 V CCIO t Output buffer enable C1 = 35 pF 4.5 4.5 5.5 5.5 ns ZX2 delay, slow slew rate = off (5) V = 2.5 V CCIO t Output buffer enable C1 = 35 pF 9.0 9.0 10.0 10.0 ns ZX3 delay, slow slew rate = on V = 3.3 V CCIO t Output buffer disable C1 = 5 pF 4.0 4.0 5.0 5.0 ns XZ delay t Register setup time 1.9 2.4 3.1 3.8 ns SU t Register hold time 1.5 2.2 3.3 4.3 ns H t Register setup time of fast 0.8 1.1 1.1 1.1 ns FSU input t Register hold time of fast 1.7 1.9 1.9 1.9 ns FH input 50 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Table 28.EPM7128A Internal Timing Parameters (Part 2 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -6 -7 -10 -12 Min Max Min Max Min Max Min Max t Register delay 1.7 2.1 2.8 3.3 ns RD t Combinatorial delay 1.7 2.1 2.8 3.3 ns COMB t Array clock delay 2.4 3.0 4.1 4.9 ns IC t Register enable time 2.4 3.0 4.1 4.9 ns EN t Global control delay 1.0 1.2 1.7 2.0 ns GLOB t Register preset time 3.1 3.9 5.2 6.2 ns PRE t Register clear time 3.1 3.9 5.2 6.2 ns CLR t PIA delay (2) 0.9 1.1 1.5 1.8 ns PIA t Low-power adder (6) 11.0 10.0 10.0 10.0 ns LPA Altera Corporation 51

MAX 7000A Programmable Logic Device Data Sheet Table 29.EPM7256A External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit -6 -7 -10 -12 Min Max Min Max Min Max Min Max t Input to non-registered C1 = 35 pF 6.0 7.5 10.0 12.0 ns PD1 output (2) t I/O input to non- C1 = 35 pF 6.0 7.5 10.0 12.0 ns PD2 registered output (2) t Global clock setup time (2) 3.7 4.6 6.2 7.4 ns SU t Global clock hold time (2) 0.0 0.0 0.0 0.0 ns H t Global clock setup time 2.5 3.0 3.0 3.0 ns FSU of fast input t Global clock hold time of 0.0 0.0 0.0 0.0 ns FH fast input t Global clock to output C1 = 35 pF 1.0 3.3 1.0 4.2 1.0 5.5 1.0 6.6 ns CO1 delay t Global clock high time 3.0 3.0 4.0 4.0 ns CH t Global clock low time 3.0 3.0 4.0 4.0 ns CL t Array clock setup time (2) 0.8 1.0 1.4 1.6 ns ASU t Array clock hold time (2) 1.9 2.7 4.0 5.1 ns AH t Array clock to output C1 = 35 pF 1.0 6.2 1.0 7.8 1.0 10.3 1.0 12.4 ns ACO1 delay (2) t Array clock high time 3.0 3.0 4.0 4.0 ns ACH t Array clock low time 3.0 3.0 4.0 4.0 ns ACL t Minimum pulse width for (3) 3.0 3.0 4.0 4.0 ns CPPW clear and preset t Minimum global clock (2) 6.4 8.0 10.7 12.8 ns CNT period f Maximum internal global (2), (4) 156.3 125.0 93.5 78.1 MHz CNT clock frequency t Minimum array clock (2) 6.4 8.0 10.7 12.8 ns ACNT period f Maximum internal array (2), (4) 156.3 125.0 93.5 78.1 MHz ACNT clock frequency 52 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Table 30.EPM7256A Internal Timing Parameters (Part 1 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -6 -7 -10 -12 Min Max Min Max Min Max Min Max t Input pad and buffer delay 0.3 0.4 0.5 0.6 ns IN t I/O input pad and buffer 0.3 0.4 0.5 0.6 ns IO delay t Fast input delay 2.4 3.0 3.4 3.8 ns FIN t Shared expander delay 2.8 3.5 4.7 5.6 ns SEXP t Parallel expander delay 0.5 0.6 0.8 1.0 ns PEXP t Logic array delay 2.5 3.1 4.2 5.0 ns LAD t Logic control array delay 2.5 3.1 4.2 5.0 ns LAC t Internal output enable 0.2 0.3 0.4 0.5 ns IOE delay t Output buffer and pad C1 = 35 pF 0.3 0.4 0.5 0.6 ns OD1 delay, slow slew rate = off V = 3.3 V CCIO t Output buffer and pad C1 = 35 pF 0.8 0.9 1.0 1.1 ns OD2 delay, slow slew rate = off (5) V = 2.5 V CCIO t Output buffer and pad C1 = 35 pF 5.3 5.4 5.5 5.6 ns OD3 delay slow slew rate = on V = 2.5 V or 3.3 V CCIO t Output buffer enable C1 = 35 pF 4.0 4.0 5.0 5.0 ns ZX1 delay slow slew rate = off V = 3.3 V CCIO t Output buffer enable C1 = 35 pF 4.5 4.5 5.5 5.5 ns ZX2 delay slow slew rate = off (5) V = 2.5 V CCIO t Output buffer enable C1 = 35 pF 9.0 9.0 10.0 10.0 ns ZX3 delay slow slew rate = on V = 2.5 V or 3.3 V CCIO t Output buffer disable C1 = 5 pF 4.0 4.0 5.0 5.0 ns XZ delay t Register setup time 1.0 1.3 1.7 2.0 ns SU t Register hold time 1.7 2.4 3.7 4.7 ns H t Register setup time of fast 1.2 1.4 1.4 1.4 ns FSU input t Register hold time of fast 1.3 1.6 1.6 1.6 ns FH input t Register delay 1.6 2.0 2.7 3.2 ns RD Altera Corporation 53

MAX 7000A Programmable Logic Device Data Sheet Table 30.EPM7256A Internal Timing Parameters (Part 2 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit -6 -7 -10 -12 Min Max Min Max Min Max Min Max t Combinatorial delay 1.6 2.0 2.7 3.2 ns COMB t Array clock delay 2.7 3.4 4.5 5.4 ns IC t Register enable time 2.5 3.1 4.2 5.0 ns EN t Global control delay 1.1 1.4 1.8 2.2 ns GLOB t Register preset time 2.3 2.9 3.8 4.6 ns PRE t Register clear time 2.3 2.9 3.8 4.6 ns CLR t PIA delay (2) 1.3 1.6 2.1 2.6 ns PIA t Low-power adder (6) 11.0 10.0 10.0 10.0 ns LPA Notes to tables: (1) These values are specified under the recommended operating conditions shown in Table14 on page28. See Figure12 for more information on switching waveforms. (2) These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. (3) This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. (4) This parameter is measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. (5) Operating conditions: VCCIO = 2.5 ± 0.2 V for commercial and industrial use. (6) The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in low-power mode. Power Supply power (P) versus frequency (f , in MHz) for MAX7000A MAX devices is calculated with the following equation: Consumption P = P + P = I × V + P INT IO CCINT CC IO The P value, which depends on the device output load characteristics IO and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices). The I value depends on the switching frequency and the application CCINT logic. The I value is calculated with the following equation: CCINT I = CCINT (A × MC ) + [B × (MC – MC )] + (C × MC × f × tog ) TON DEV TON USED MAX LC 54 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet The parameters in this equation are: MC = Number of macrocells with the Turbo Bit option turned TON on, as reported in the MAX+PLUSII Report File (.rpt) MC = Number of macrocells in the device DEV MC = Total number of macrocells in the design, as reported in USED the Report File f = Highest clock frequency to the device MAX tog = Average percentage of logic cells toggling at each clock LC (typically 12.5%) A, B, C = Constants, shown in Table31 Table 31.MAX 7000A I Equation Constants CC Device A B C EPM7032AE 0.71 0.30 0.014 EPM7064AE 0.71 0.30 0.014 EPM7128A 0.71 0.30 0.014 EPM7128AE 0.71 0.30 0.014 EPM7256A 0.71 0.30 0.014 EPM7256AE 0.71 0.30 0.014 EPM7512AE 0.71 0.30 0.014 This calculation provides an I estimate based on typical conditions CC using a pattern of a 16-bit, loadable, enabled, up/down counter in each LAB with no output load. Actual I should be verified during operation CC because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. Altera Corporation 55

MAX 7000A Programmable Logic Device Data Sheet Figure13 shows the typical supply current versus frequency for MAX7000A devices. Figure 13. I vs. Frequency for MAX 7000A Devices (Part 1 of 2) CC EPM7032AE EPM7064AE 40 80 35 VRCoCo m= 3Te.3m Vperature 227.3 MHz 70 RVCoCo m= 3Te.3m Vperature 222.2 MHz 30 60 25 High Speed 50 High Speed TAycptiivcea l( mI C A C ) 20 TAycptiivcea l( mI C A C ) 40 15 144.9 MHz 30 125.0 MHz 10 Low Power 20 Low Power 5 10 0 50 100 150 200 250 0 50 100 150 200 250 Frequency (MHz) Frequency (MHz) EPM7128A & EPM7128AE 160 VCC = 3.3 V 140 Room Temperature 192.3 MHz 120 100 High Speed Typical I C C Active (mA) 80 60 108.7 MHz 40 Low Power 20 0 50 100 150 200 250 Frequency (MHz) 56 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Figure 13. I vs. Frequency for MAX 7000A Devices (Part 2 of 2) CC EPM7256A & EPM7256AE EPM7512AE 300 600 VCC = 3.3 V VCC = 3.3 V Room Temperature Room Temperature 250 500 172.4 MHz 116.3 MHz 200 400 High Speed Typical I C C Typical I C C High Speed Active (mA)150 Active (mA)300 100 102.0 MHz 200 76.3 MHz Low Power 50 Low Power 100 0 50 100 150 200 0 20 40 60 80 100 120 140 Frequency (MHz) Frequency (MHz) Device See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. Pin-Outs Figures14 through 23 show the package pin-out diagrams for MAX7000Adevices. Figure 14. 44-Pin PLCC/TQFP Package Pin-Out Diagram Package outlines not drawn to scale. I/OI/OI/OVCC INPUT/OE2/GCLK2INPUT/GCLRnINPUT/OE1nINPUT/GCLK1GNDI/OI/O Pin 1 I/O I/O I/O VCC INPUT/OE2/GCLK2 INPUT/GCLRn INPUT/OE1n INPUT/GCLK1 GND I/O I/O Pin 34 6 5 4 3 2 1 44 43 42 41 40 I/O/TDI 7 39 I/O I/O/TDI I/O I/O 8 38 I/O/TDO I/O I/O/TDO I/O 9 37 I/O I/O I/O GND 10 36 I/O GND I/O I/O 11 EPM7032AE 35 VCC I/O EPM7032AE VCC I/O 12 EPM7064AE 34 I/O I/O EPM7064AE I/O I/O/TMS 13 33 I/O I/O 14 32 I/O/TCK I/O/TMS I/O VCC 15 31 I/O I/O I/O/TCK I/O 16 30 GND VCC I/O I/O 17 29 I/O I/O GND I/O I/O 18 19 20 21 22 23 24 25 26 27 28 I/OI/OI/OI/OGNDVCCI/OI/OI/OI/OI/O Pin 12 I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O Pin 23 44-Pin PLCC 44-Pin TQFP Altera Corporation 57

MAX 7000A Programmable Logic Device Data Sheet Figure 15. 49-Pin Ultra FineLine BGA Package Pin-Out Diagram Package outlines not drawn to scale. A1 Ball Pad Corner Indicates location of A Ball A1 B C D E EPM7064AE F G 7 6 5 4 3 2 1 Figure 16. 84-Pin PLCC Package Pin-Out Diagram Package outline not drawn to scale. I/OI/OI/OI/OGNDI/OI/OI/OVCCINTINPUT/OE2/GCLK2INPUT/GLCRnINPUT/OE1INPUT/GCLK1GNDI/OI/OI/OVCCIOI/OI/OI/O 111098765432184838281807978777675 I/O 12 74 I/O VCCIO 13 73 I/O I/O/TDI 14 72 GND I/O 15 71 I/O/TDO I/O 16 70 I/O I/O 17 69 I/O I/O 18 68 I/O GND 19 67 I/O I/O 20 66 VCCIO I/O 21 65 I/O I/O 22 64 I/O I/O/TMS 23 EPM7128A 63 I/O I/O 24 62 I/O/TCK I/O 25 EPM7128AE 61 I/O VCCIO 26 60 I/O I/O 27 59 GND I/O 28 58 I/O I/O 29 57 I/O I/O 30 56 I/O I/O 31 55 I/O GND 32 54 I/O 333435363738394041424344454647484950515253 I/OI/OI/OI/OI/OVCCIOI/OI/OI/OGNDVCCINTI/OI/OI/OGNDI/OI/OI/OI/OI/OVCCIO 58 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Figure 17. 100-Pin TQFP Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin 76 EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE Pin 26 Pin 51 Figure 18. 100-Pin FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. A1 Ball Pad Corner Indicates location of A Ball A1 B C D E F EPM7064AE G EPM7128A H EPM7128AE EPM7256AE J K 10 9 8 7 6 5 4 3 2 1 Altera Corporation 59

MAX 7000A Programmable Logic Device Data Sheet Figure 19. 144-Pin TQFP Package Pin-Out Diagram Package outline not drawn to scale. Indicates location of Pin 1 Pin 1 Pin 109 EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE Pin 37 Pin 73 Figure 20. 169-Pin Ultra FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. A1 Ball Pad Corner Indicates location of A Ball A1 B C D E F EPM7064AE G EPM7128A H EPM7128AE EPM7256AE J K 10 9 8 7 6 5 4 3 2 1 60 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Figure 21. 208-Pin PQFP Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin 157 EPM7256A EPM7256AE EPM7512AE Pin 53 Pin 105 Altera Corporation 61

MAX 7000A Programmable Logic Device Data Sheet Figure 22. 256-Pin BGA Package Pin-Out Diagram Package outline not drawn to scale. A1 Ball Pad Corner Indicates A Location of B Ball A1 C D E F G H J K L EPM7512AE M N P R T U V W Y 2019181716151413121110 9 8 7 6 5 4 3 2 1 62 Altera Corporation

MAX 7000A Programmable Logic Device Data Sheet Figure 23. 256-Pin FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. A1 Ball Pad Corner A Indicates Location of B Ball A1 C D E F G H J EPM7128A EPM7128AE K EPM7256A L EPM7256AE M EPM7512AE N P R T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Revision The information contained in the MAX 7000A Programmable Logic Device Data Sheet version 4.5 supersedes information published in previous History versions. Version 4.5 The following changes were made in the MAX 7000A Programmable Logic Device Data Sheet version 4.5: ■ Updated text in the “Power Sequencing & Hot-Socketing” section. Version 4.4 The following changes were made in the MAX 7000A Programmable Logic Device Data Sheet version 4.4: ■ Added Tables5 through 7. ■ Added “Programming Sequence” on page 17 and “Programming Times” on page 18. Altera Corporation 63

MAX 7000A Programmable Logic Device Data Sheet Version 4.3 The following changes were made in the MAX 7000A Programmable Logic Device Data Sheet version 4.3: ■ Added extended temperature devices to document ■ Updated Table14. Version 4.2 The following changes were made in the MAX 7000A Programmable Logic Device Data Sheet version 4.2: ■ Removed Note (1) from Table2. ■ Removed Note (4) from Tables3 and 4. Version 4.1 The following changes were made in the MAX 7000A Programmable Logic Device Data Sheet version 4.1: ■ Updated leakage current information in Table15. ■ Updated Note (9) of Table15. ■ Updated Note (1) of Tables17 through 30. ® Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the 101 Innovation Drive stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera San Jose, CA 95134 Corporation in the U.S. and other countries. All other product or service names are the property of their (408) 544-7000 respective holders. Altera products are protected under numerous U.S. and foreign patents and pending http://www.altera.com applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right Applications Hotline: to make changes to any products and services at any time without notice. Altera assumes no (800) 800-EPLD responsibility or liability arising out of the application or use of any information, product, or Literature Services: service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before lit_req@altera.com relying on any published information and before placing orders for products or services. 64 Altera Corporation

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: I ntel: EPM7064AETC100-7N EPM7128AEFC100-10 EPM7256AEFC100-7N EPM7064AEFC100-4N EPM7256AEFI256- 7N EPM7512AEFC256-10 EPM7128AETC144-10 EPM7512AETC144-7 EPM7128AEFC100-5N EPM7256AETC144- 7N EPM7064AELC44-7 EPM7128AELC84-5 EPM7064AETI44-7N EPM7512AEQC208-12 EPM7032AELC44-4N EPM7032AETC44-4N EPM7256AETC100-10N EPM7064AETC100-4 EPM7512AEFC256-7 EPM7064AEFC100-10N EPM7256AEFI100-7 EPM7128AETC144-7 EPM7128AETC100-5N EPM7512AETC144-10N EPM7256AETC144-5 EPM7064AETI100-7 EPM7128AEFC256-5 EPM7128AETC100-10 EPM7064AEFC100-7N EPM7256AEQI208-7 EPM7512AEBC256-7 EPM7256AEQC208-7N EPM7032AETC44-10 EPM7512AETC144-10 EPM7256AEFC256-7N EPM7512AETC144-12N EPM7256AEFC100-10 EPM7512AEBC256-12 EPM7064AETI44-7 EPM7512AEQC208-10N EPM7512AEFC256-12N EPM7064AETC44-4 EPM7128AEFI100-7 EPM7128AETA144-10N EPM7256AEFC256-5 EPM7256AETC100-7 EPM7064AETA100-10N EPM7064AEFC100-10 EPM7128AEFC256-10 EPM7064TC44-15 EPM7512AEQC208-7N EPM7064AEFC100-4 EPM7256AETC144-10 EPM7032AETC44-7N EPM7032AELC44-4 EPM7256AETC100-5N EPM7064AETA44-10N EPM7128AETC100-7N EPM7512AETC144-7N EPM7032BUC49-3N EPM7128AETI144-7N EPM7128AEFC100-7 EPM7256AETI144-7N EPM7128AELC84-7 EPM7256AETC100-5 EPM7128AELC84-10 EPM7512AEFC256-10N EPM7064AETC44-7N EPM7128AETI144-7 EPM7512AEBI256-10 EPM7256AETC144-5N EPM7256AEQI208-7N EPM7064AETC100-4N EPM7256AEFC100-5 EPM7512AETC144-12 EPM7512AEBC256-10N EPM7128AETA100-10N EPM7128AETC100-10N EPM7512AEFC256-7N EPM7064AETC100-10 EPM7128AETC144-7N EPM7128AEFC100-7N EPM7512AEBI256-7 EPM7256AETC100-10 EPM7256AEFC256-10N EPM7128AEFC100-5 EPM7128AETC144-5 EPM7512AEFC256-12 EPM7512AEQC208- 12N EPM7032AETI44-7N EPM7064AETC44-4N EPM7064AELI44-7 EPM7032AELC44-10N EPM7032AETC44-7 EPM7128AETC100-7 EPM7064AETC100-10N EPM7128AETC100-5 EPM7064AEFC100-7 EPM7064AETC100-7 EPM7128AETC144-5N