FLEX 8000 Programmable Logic ® Device Family January 2003, ver. 11.1 Data Sheet 1Features... ■ Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see Table1) – 2,500 to 16,000 usable gates – 282 to 1,500 registers ■ System-level features – In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller – Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 5.0-V operation – Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices 3 – MultiVoltTM I/O interface enabling device core to run at 5.0V, while I/O pins are compatible with 5.0-V and 3.3-V logic levels – Low power consumption (typical specification is 0.5 mA or less in F standby mode) L ■ Flexible interconnect EX – FastTrack® Interconnect continuous routing structure for fast, 80 predictable interconnect delays 00 – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) – Tri-state emulation that implements internal tri-state nets ■ Powerful I/O pins ■ Programmable output slew-rate control reduces switching noise Table 1.FLEX8000 Device Features Feature EPF8282A EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A EPF8282AV Usable gates 2,500 4,000 6,000 8,000 12,000 16,000 Flipflops 282 452 636 820 1,188 1,500 Logic array blocks (LABs) 26 42 63 84 126 162 Logic elements (LEs) 208 336 504 672 1,008 1,296 Maximum user I/O pins 78 120 136 152 184 208 Altera Corporation 1 DS-F8000-11.1

FLEX 8000 Programmable Logic Device Family Data Sheet JTAG BST circuitry Yes No Yes Yes No Yes ...and More ■ Peripheral register for fast setup and clock-to-output delay ■ Fabricated on an advanced SRAM process Features ■ Available in a variety of packages with 84 to 304 pins (see Table2) ■ Software design support and automatic place-and-route provided by the Altera® MAX+PLUS® II development system for Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations ■ Additional design entry and simulation support provided by EDIF 200 and 300 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and Veribest Table 2.FLEX8000 Package Options & I/O Pin Count Note (1) Device 84- 100- 144- 160- 160- 192- 208- 225- 232- 240- 280- 304- Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin PLCC TQFP TQFP PQFP PGA PGA PQFP BGA PGA PQFP PGA RQFP EPF8282A 68 78 EPF8282AV 78 EPF8452A 68 68 120 120 EPF8636A 68 118 136 136 EPF8820A 112 120 152 152 152 EPF81188A 148 184 184 EPF81500A 181 208 208 Note: (1) FLEX8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages. General Altera’s Flexible Logic Element MatriX (FLEX®) family combines the benefits of both erasable programmable logic devices (EPLDs) and field- Description programmable gate arrays (FPGAs). The FLEX8000 device family is ideal for a variety of applications because it combines the fine-grained architecture and high register count characteristics of FPGAs with the high speed and predictable interconnect delays of EPLDs. Logic is implemented in LEs that include compact 4-input look-up tables (LUTs) and programmable registers. High performance is provided by a fast, continuous network of routing resources. 2 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet FLEX8000 devices provide a large number of storage elements for applications such as digital signal processing (DSP), wide-data-path manipulation, and data transformation. These devices are an excellent choice for bus interfaces, TTL integration, coprocessor functions, and high-speed controllers. The high-pin-count packages can integrate multiple 32-bit buses into a single device. Table3 shows FLEX8000 performance and LE requirements for typical applications. Table 3.FLEX8000 Performance Application LEs Used Speed Grade Units A-2 A-3 A-4 16-bit loadable counter 16 125 95 83 MHz 16-bit up/down counter 16 125 95 83 MHz 24-bit accumulator 24 87 67 58 MHz 16-bit address decode 4 4.2 4.9 6.3 ns 16-to-1 multiplexer 10 6.6 7.9 9.5 ns 3 All FLEX8000 device packages provide four dedicated inputs for synchronous control signals with large fan-outs. Each I/O pin has an F L associated register on the periphery of the device. As outputs, these E X registers provide fast clock-to-output times; as inputs, they offer quick 8 setup times. 00 0 The logic and interconnections in the FLEX8000 architecture are configured with CMOS SRAM elements. FLEX8000 devices are configured at system power-up with data stored in an industry-standard parallel EPROM or an Altera serial configuration devices, or with data provided by a system controller. Altera offers the EPC1, EPC1213, EPC1064, and EPC1441 configuration devices, which configure FLEX8000 devices via a serial data stream. Configuration data can also be stored in an industry-standard 32K × 8bit or larger configuration device, or downloaded from system RAM. After a FLEX8000 device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Because reconfiguration requires less than 100 ms, real- time changes can be made during system operation. For information on how to configure FLEX8000 devices, go to the following documents: ■ Configuration Devices for APEX & FLEX Devices Data Sheet ■ BitBlaster Serial Download Cable Data Sheet ■ ByteBlasterMV Parallel Port Download Cable Data Sheet ■ Application Note 33 (Configuring FLEX8000 Devices) ■ Application Note 38 (Configuring Multiple FLEX8000 Devices) Altera Corporation 3

FLEX 8000 Programmable Logic Device Family Data Sheet FLEX8000 devices contain an optimized microprocessor interface that permits the microprocessor to configure FLEX8000 devices serially, in parallel, synchronously, or asynchronously. The interface also enables the microprocessor to treat a FLEX8000 device as memory and configure the device by writing to a virtual memory location, making it very easy for the designer to create configuration software. The FLEX8000 family is supported by Altera’s MAX+PLUSII development system, a single, integrated package that offers schematic, text—including the Altera Hardware Description Language (AHDL), VHDL, and Verilog HDL—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUSII software provides EDIF 2 0 0 and 3 0 0, library of parameterized modules (LPM), VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry- standard PC- and UNIX workstation-based EDA tools. The MAX+PLUSII software runs on Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. The MAX+PLUSII software interfaces easily with common gate array EDA tools for synthesis and simulation. For example, the MAX+PLUSII software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the MAX+PLUSII software contains EDA libraries that use device-specific features such as carry chains, which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the MAX+PLUSII development system includes DesignWare functions that are optimized for the FLEX 8000 architecture. f For more information on the MAX+PLUSII software, go to the MAX+PLUSII Programmable Logic Development System & Software Data Sheet. Functional The FLEX8000 architecture incorporates a large matrix of compact building blocks called logic elements (LEs). Each LE contains a 4-input Description LUT that provides combinatorial logic capability and a programmable register that offers sequential logic capability. The fine-grained structure of the LE provides highly efficient logic implementation. Eight LEs are grouped together to form a logic array block (LAB). Each FLEX8000 LAB is an independent structure with common inputs, interconnections, and control signals. The LAB architecture provides a coarse-grained structure for high device performance and easy routing. 4 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Figure1 shows a block diagram of the FLEX8000 architecture. Each group of eight LEs is combined into an LAB; LABs are arranged into rows and columns. The I/O pins are supported by I/O elements (IOEs) located at the ends of rows and columns. Each IOE contains a bidirectional I/O buffer and a flipflop that can be used as either an input or output register. Figure 1. FLEX8000 Device Block Diagram I/O Element IOE IOE IOE IOE (IOE) IOE IOE IOE IOE FastTrack Interconnect Logic Array Block (LAB) 3 IOE IOE IOE IOE F L E X Logic 8 Element (LE) 0 0 0 IOE IOE IOE IOE Signal interconnections within FLEX8000 devices and between device pins are provided by the FastTrack Interconnect, a series of fast, continuous channels that run the entire length and width of the device. IOEs are located at the end of each row (horizontal) and column (vertical) FastTrack Interconnect path. Altera Corporation 5

FLEX 8000 Programmable Logic Device Family Data Sheet Logic Array Block A logic array block (LAB) consists of eight LEs, their associated carry and cascade chains, LAB control signals, and the LAB local interconnect. The LAB provides the coarse-grained structure of the FLEX8000 architecture. This structure enables FLEX8000 devices to provide efficient routing, high device utilization, and high performance. Figure2 shows a block diagram of the FLEX8000 LAB. Figure 2. FLEX8000 Logic Array Block Dedicated Inputs Row Interconnect 24 4 8 LAB Local Interconnect 4 See Figure 8 (32 channels) Carry-In and for details. Cascade-In from LAB 8 16 on Left LAB Control 4 2 Signals Column-to-Row Interconnect 4 LE1 Column 4 LE2 Interconnect 4 LE3 4 LE4 4 LE5 4 LE6 4 LE7 4 LE8 8 2 Carry-Out and Cascade-Out to LAB on Right 6 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Each LAB provides four control signals that can be used in all eight LEs. Two of these signals can be used as clocks, and the other two for clear/preset control. The LAB control signals can be driven directly from a dedicated input pin, an I/O pin, or any internal signal via the LAB local interconnect. The dedicated inputs are typically used for global clock, clear, or preset signals because they provide synchronous control with very low skew across the device. FLEX8000 devices support up to four individual global clock, clear, or preset control signals. If logic is required on a control signal, it can be generated in one or more LEs in any LAB and driven into the local interconnect of the target LAB. Logic Element The logic element (LE) is the smallest unit of logic in the FLEX8000 architecture, with a compact size that provides efficient logic utilization. Each LE contains a 4-input LUT, a programmable flipflop, a carry chain, and cascade chain. Figure3 shows a block diagram of an LE. Figure 3. FLEX8000 LE 3 Carry-In Cascade-In F L E X DATA1 DFF 8 DDAATTAA23 Lo(TLoaUkb-TlUe)p CChaarriyn CCashcaainde DPRNQ LE-Out 000 DATA4 CLRN Clear/ LABCTRL1 Preset LABCTRL2 Logic Clock Select LABCTRL3 LABCTRL4 Carry-Out Cascade-Out The LUT is a function generator that can quickly compute any function of four variables. The programmable flipflop in the LE can be configured for D, T, JK, or SR operation. The clock, clear, and preset control signals on the flipflop can be driven by dedicated input pins, general-purpose I/O pins, or any internal logic. For purely combinatorial functions, the flipflop is bypassed and the output of the LUT goes directly to the output of the LE. Altera Corporation 7

FLEX 8000 Programmable Logic Device Family Data Sheet The FLEX8000 architecture provides two dedicated high-speed data paths—carry chains and cascade chains—that connect adjacent LEs without using local interconnect paths. The carry chain supports high- speed counters and adders; the cascade chain implements wide-input functions with minimum delay. Carry and cascade chains connect all LEs in an LAB and all LABs in the same row. Heavy use of carry and cascade chains can reduce routing flexibility. Therefore, the use of carry and cascade chains should be limited to speed-critical portions of a design. Carry Chain The carry chain provides a very fast (less than 1 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit moves forward into the higher-order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature allows the FLEX8000 architecture to implement high-speed counters and adders of arbitrary width. The MAX+PLUSII Compiler can create carry chains automatically during design processing; designers can also insert carry chain logic manually during design entry. Figure4 shows how an n-bit full adder can be implemented in n+1 LEs with the carry chain. One portion of the LUT generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the LE. The register is typically bypassed for simple adders, but can be used for an accumulator function. Another portion of the LUT and the carry chain logic generate the carry-out signal, which is routed directly to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to another LE, where it can be used as a general-purpose signal. In addition to mathematical functions, carry chain logic supports very fast counters and comparators. 8 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Figure 4. FLEX8000 Carry Chain Operation Carry-In a1 LU Register s1 b1 Carry LE1 a2 LUT Register s2 b2 Carry Chain LE2 3 an LUT Register sn FL bn EX 8 0 0 Carry Chain 0 LEn LUT Register Carry-Out Carry Chain LEn + 1 Cascade Chain With the cascade chain, the FLEX8000 architecture can implement functions that have a very wide fan-in. Adjacent LUTs can be used to compute portions of the function in parallel; the cascade chain serially connects the intermediate values. The cascade chain can use a logical AND or logical OR (via De Morgan’s inversion) to connect the outputs of adjacent LEs. Each additional LE provides four more inputs to the effective width of a function, with a delay as low as 0.6ns per LE. Altera Corporation 9

FLEX 8000 Programmable Logic Device Family Data Sheet The MAX+PLUSII Compiler can create cascade chains automatically during design processing; designers can also insert cascade chain logic manually during design entry. Cascade chains longer than eight LEs are automatically implemented by linking LABs together. The last LE of an LAB cascades to the first LE of the next LAB. Figure5 shows how the cascade function can connect adjacent LEs to form functions with a wide fan-in. These examples show functions of 4n variables implemented with n LEs. For a device with an A-2 speed grade, the LE delay is 2.4 ns; the cascade chain delay is 0.6 ns. With the cascade chain, 4.2ns is needed to decode a 16-bit address. Figure 5. FLEX8000 Cascade Chain Operation AND Cascade Chain OR Cascade Chain LE1 LE1 d[3..0] LUT d[3..0] LUT LE2 LE2 d[7..4] LUT d[7..4] LUT LEn LEn d[(4n-1)..4(n-1)] LUT d[(4n-1)..4(n-1)] LUT LE Operating Modes The FLEX8000 LE can operate in one of four modes, each of which uses LE resources differently. See Figure6. In each mode, seven of the ten available inputs to the LE—the four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous LE—are directed to different destinations to implement the desired logic function. The three remaining inputs to the LE provide clock, clear, and preset control for the register. The MAX+PLUSII software automatically chooses the appropriate mode for each application. Design performance can also be enhanced by designing for the operating mode that supports the desired application. 10 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Figure 6. FLEX8000 LE Operating Modes Normal Mode Carry-In Cascade-In LE-Out data1 PRN D Q data2 4-Input LUT data3 CLRN Cascade-Out data4 Arithmetic Mode Carry-In Cascade-In LE-Out PRN D Q data1 data2 3-Input LUT CLRN 3-Input Cascade-Out 3 LUT Carry-Out F Up/Down Counter Mode L E X Carry-In Cascade-In 8 0 0 0 data1(ena) PRN data2(nclr) 3-Input 1 D Q LE-Out LUT 0 data3(data) CLRN 3-Input LUT data4(nload) Carry-Out Cascade-Out Clearable Counter Mode Carry-In data1(ena) PRN data2(nclr) 3-Input 1 D Q LE-Out LUT 0 data3(data) CLRN 3-Input LUT data4(nload) Carry-Out Cascade-Out Altera Corporation 11

FLEX 8000 Programmable Logic Device Family Data Sheet Normal Mode The normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in signal are the inputs to a 4-input LUT. Using a configurable SRAM bit, the MAX+PLUSII Compiler automatically selects the carry-in or the DATA3 signal as an input. The LUT output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal. The LE-Out signal—the data output of the LE—is either the combinatorial output of the LUT and cascade chain, or the data output (Q)of the programmable register. Arithmetic Mode The arithmetic mode offers two 3-input LUTs that are ideal for implementing adders, accumulators, and comparators. One LUT provides a 3-bit function; the other generates a carry bit. As shown in Figure6, the first LUT uses the carry-in signal and two data inputs from the LAB local interconnect to generate a combinatorial or registered output. For example, in an adder, this output is the sum of three bits: a, b, and the carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports a cascade chain. Up/Down Counter Mode The up/down counter mode offers counter enable, synchronous up/down control, and data loading options. These control signals are generated by the data inputs from the LAB local interconnect, the carry-in signal, and output feedback from the programmable register. Two 3-input LUTs are used: one generates the counter data, and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading. Data can also be loaded asynchronously with the clear and preset register control signals, without using the LUT resources. Clearable Counter Mode The clearable counter mode is similar to the up/down counter mode, but supports a synchronous clear instead of the up/down control; the clear function is substituted for the cascade-in signal in the up/down counter mode. Two 3-input LUTs are used: one generates the counter data, and the other generates the fast carry bit. Synchronous loading is provided by a 2-to-1 multiplexer, and the output of this multiplexer is ANDed with a synchronous clear. 12 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Internal Tri-State Emulation Internal tri-state emulation provides internal tri-stating without the limitations of a physical tri-state bus. In a physical tri-state bus, the tri-state buffers’ output enable signals select the signal that drives the bus. However, if multiple output enable signals are active, contending signals can be driven onto the bus. Conversely, if no output enable signals are active, the bus will float. Internal tri-state emulation resolves contending tri-state buffers to a low value and floating buses to a high value, thereby eliminating these problems. The MAX+PLUSII software automatically implements tri-state bus functionality with a multiplexer. Clear & Preset Logic Control Logic for the programmable register’s clear and preset functions is controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The clear and preset control structure of the LE is used to asynchronously load signals into a register. The register can be set up so that LABCTRL1 implements an asynchronous load. The data to be loaded is driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the register. 3 During compilation, the MAX+PLUSII Compiler automatically selects the best control signal implementation. Because the clear and preset F L functions are active-low, the Compiler automatically assigns a logic high E X to an unused clear or preset. 8 0 0 0 The clear and preset logic is implemented in one of the following six asynchronous modes, which are chosen during design entry. LPM functions that use registers will automatically use the correct asynchronous mode. See Figure7. ■ Clear only ■ Preset only ■ Clear and preset ■ Load with clear ■ Load with preset ■ Load without clear or preset Altera Corporation 13

FLEX 8000 Programmable Logic Device Family Data Sheet Figure 7. FLEX8000 LE Asynchronous Clear & Preset Modes Asynchronous Clear Asynchronous Preset Asynchronous Clear & Preset VCC LABCTRL1 or LABCTRL1 LABCTRL2 PRN PRN PRN D Q D Q D Q CLRN CLRN CLRN LABCTRL1 or LABCTRL2 LABCTRL2 Asynchronous Load with Clear LABCTRL1 NOT (Asynchronous Load) DATA3 PRN (Data) D Q NOT CLRN LABCTRL2 (Clear) Asynchronous Load with Preset LABCTRL1 NOT (Asynchronous Load) LABCTRL2 (Preset) PRN D Q DATA3 (Data) CLRN NOT Asynchronous Load without Clear or Preset NOT LABCTRL1 (Asynchronous Load) PRN DATA3 D Q (Data) CLRN NOT 14 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Asynchronous Clear A register is cleared by one of the two LABCTRL signals. When the CLRn port receives a low signal, the register is set to zero. Asynchronous Preset An asynchronous preset is implemented as either an asynchronous load or an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRLl asynchronously loads a 1 into the register. Alternatively, the MAX+PLUSII software can provide preset control by using the clear and inverting the input and output of the register. Inversion control is available for the inputs to both LEs and IOEs. Therefore, if a register is preset by only one of the two LABCTRL signals, the DATA3 input is not needed and can be used for one of the LE operating modes. Asynchronous Clear & Preset When implementing asynchronous clear and preset, LABCTRL1 controls the preset and LABCTRL2 controls the clear. The DATA3 input is tied to VCC; therefore, asserting LABCTRL1 asynchronously loads a 1 into the register, 3 effectively presetting the register. Asserting LABCTRL2 clears the register. F Asynchronous Load with Clear L E X When implementing an asynchronous load with the clear, LABCTRL1 8 0 implements the asynchronous load of DATA3 by controlling the register 0 0 preset and clear. LABCTRL2 implements the clear by controlling the register clear. Asynchronous Load with Preset When implementing an asynchronous load in conjunction with a preset, the MAX+PLUSII software provides preset control by using the clear and inverting the input and output of the register. Asserting LABCTRL2 clears the register, while asserting LABCTRL1 loads the register. The MAX+PLUSII software inverts the signal that drives the DATA3 signal to account for the inversion of the register’s output. Asynchronous Load without Clear or Preset When implementing an asynchronous load without the clear or preset, LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear. Altera Corporation 15

FLEX 8000 Programmable Logic Device Family Data Sheet FastTrack Interconnect In the FLEX8000 architecture, connections between LEs and device I/O pins are provided by the FastTrack Interconnect, a series of continuous horizontal (row) and vertical (column) routing channels that traverse the entire FLEX8000 device. This device-wide routing structure provides predictable performance even in complex designs. In contrast, the segmented routing structure in FPGAs requires switch matrices to connect a variable number of routing paths, which increases the delays between logic resources and reduces performance. The LABs within FLEX8000 devices are arranged into a matrix of columns and rows. Each row of LABs has a dedicated row interconnect that routes signals both into and out of the LABs in the row. The row interconnect can then drive I/O pins or feed other LABs in the device. Figure8 shows how an LE drives the row and column interconnect. Figure 8. FLEX8000 LAB Connections to Row & Column Interconnect 16 Column Channels Row Channels (1) Each LE drives one row channel. LE1 LE2 to Local to Local Each LE drives up to Feedback Feedback two column channels. Note: (1) See Table4 for the number of row channels. 16 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Each LE in an LAB can drive up to two separate column interconnect channels. Therefore, all 16 available column channels can be driven by the LAB. The column channels run vertically across the entire device, and share access to LABs in the same column but in different rows. The MAX+PLUSII Compiler chooses which LEs must be connected to a column channel. A row interconnect channel can be fed by the output of the LE or by two column channels. These three signals feed a multiplexer that connects to a specific row channel. Each LE is connected to one 3-to-1 multiplexer. In an LAB, the multiplexers provide all 16 column channels with access to 8 row channels. Each column of LABs has a dedicated column interconnect that routes signals out of the LABs into the column. The column interconnect can then drive I/O pins or feed into the row interconnect to route the signals to other LABs in the device. A signal from the column interconnect, which can be either the output of an LE or an input from an I/O pin, must transfer to the row interconnect before it can enter an LAB. Table4 summarizes the FastTrack Interconnect resources available in each FLEX8000 device. 3 Table 4.FLEX8000 FastTrack Interconnect Resources F Device Rows Channels per Row Columns Channels per Column L E X EPF8282A 2 168 13 16 8 0 EPF8282AV 0 0 EPF8452A 2 168 21 16 EPF8636A 3 168 21 16 EPF8820A 4 168 21 16 EPF81188A 6 168 21 16 EPF81500A 6 216 27 16 Figure9 shows the interconnection of four adjacent LABs, with row, column, and local interconnects, as well as the associated cascade and carry chains. Altera Corporation 17

FLEX 8000 Programmable Logic Device Family Data Sheet Figure 9. FLEX8000 Device Interconnect Resources Each LAB is named according to its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device. See Figure 12 for details. IOE IOE IOE IOE Column See Figure 11 Interconnect Row for details. Interconnect 1 IOE IOE 1 8 IOE IOE 8 LAB LAB A1 A2 1 IOE IOE 1 8 IOE IOE 8 LAB LAB B1 B2 LAB Local Interconnect Cascade & Carry Chain IOE IOE IOE IOE I/O Element An IOE contains a bidirectional I/O buffer and a register that can be used either as an input register for external data that requires a fast setup time, or as an output register for data that requires fast clock-to-output performance. IOEs can be used as input, output, or bidirectional pins. The MAX+PLUSII Compiler uses the programmable inversion option to automatically invert signals from the row and column interconnect where appropriate. Figure10 shows the IOE block diagram. 18 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Figure 10. FLEX8000 IOE Numbers in parentheses are for EPF81500A devices only. I/O Controls To Row or Column 6 Interconnect (6) Programmable Inversion VCC From Row or Column Interconnect D Q CLRN Slew-Rate Control VCC 3 F L E X 8 0 CLR0R1/OE0CLK0K1/OE1OE2OE3 E [4..9]) 00 CL CL (O Row-to-IOE Connections Figure11 illustrates the connection between row interconnect channels and IOEs. An input signal from an IOE can drive two separate row channels. When an IOE is used as an output, the signal is driven by an n-to-1 multiplexer that selects the row channels. The size of the multiplexer varies with the number of columns in a device. EPF81500A devices use a 27-to-1 multiplexer; EPF81188A, EPF8820A, EPF8636A, and EPF8452A devices use a 21-to-1 multiplexer; and EPF8282A and EPF8282AV devices use a 13-to-1 multiplexer. Eight IOEs are connected to each side of the row channels. Altera Corporation 19

FLEX 8000 Programmable Logic Device Family Data Sheet Figure 11. FLEX8000 Row-to-IOE Connections Numbers in parentheses are for EPF81500A devices. See Note (1). 2 2 2 2 Each IOE can drive n IOE 1 up to two row channels. IOE 2 n 2 2 2 2 n IOE 3 n IOE 4 Row Interconnect 168 (216) n IOE 5 168 (216) 2 2 2 2 n IOE 6 Each IOE is driven by an n-to-1 n IOE 7 multiplexer. n IOE 8 2 2 2 2 Note: (1) n = 13 for EPF8282A and EPF8282AV devices. n = 21 for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices. n = 27 for EPF81500A devices. Column-to-IOE Connections Two IOEs are located at the top and bottom of the column channels (see Figure12). When an IOE is used as an input, it can drive up to two separate column channels. The output signal to an IOE can choose from 8 of the 16 column channels through an 8-to-1 multiplexer. 20 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Figure 12. FLEX8000 Column-to-IOE Connections Each IOE is Each IOE can drive driven by an IOE IOE up to two column 8-to-1 signals. multiplexer. 8 8 16 Column Interconnect 3 In addition to general-purpose I/O pins, FLEX8000 devices have four dedicated input pins. These dedicated inputs provide low-skew, device- wide signal distribution, and are typically used for global clock, clear, and F preset control signals. The signals from the dedicated inputs are available L E as control signals for all LABs and I/O elements in the device. The X 8 dedicated inputs can also be used as general-purpose data inputs because 0 0 they can feed the local interconnect of each LAB in the device. 0 Signals enter the FLEX8000 device either from the I/O pins that provide general-purpose input capability or from the four dedicated inputs. The IOEs are located at the ends of the row and column interconnect channels. I/O pins can be used as input, output, or bidirectional pins. Each I/O pin has a register that can be used either as an input register for external data that requires fast setup times, or as an output register for data that requires fast clock-to-output performance. The MAX+PLUSII Compiler uses the programmable inversion option to invert signals automatically from the row and column interconnect when appropriate. The clock, clear, and output enable controls for the IOEs are provided by a network of I/O control signals. These signals can be supplied by either the dedicated input pins or by internal logic. The IOE control-signal paths are designed to minimize the skew across the device. All control-signal sources are buffered onto high-speed drivers that drive the signals around the periphery of the device. This “peripheral bus” can be configured to provide up to four output enable signals (10 in EPF81500A devices), and up to two clock or clear signals. Figure13 on page22 shows how two output enable signals are shared with one clock and one clear signal. Altera Corporation 21

FLEX 8000 Programmable Logic Device Family Data Sheet The signals for the peripheral bus can be generated by any of the four dedicated inputs or signals on the row interconnect channels, as shown in Figure13. The number of row channels in a row that can drive the peripheral bus correlates to the number of columns in the FLEX8000 device. EPF8282A and EPF8282AV devices use 13 channels; EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices use 21 channels; and EPF81500A devices use 27 channels. The first LE in each LAB is the source of the row channel signal. The six peripheral control signals (12 in EPF81500A devices) can be accessed by each IOE. Figure 13. FLEX8000 Peripheral Bus Numbers in parentheses are for EPF81500A devices. Peripheral Control Signals Programmable Inversion Dedicated 4 Inputs 1 2 Row Channels n(1) CLR0 CLR1/OE0 CLK0CLK1/OE1 OE2 OE3(OE[4..9]) Note: (1) n = 13 for EPF8282A and EPF8282AV devices. n = 21 for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices. n = 27 for EPF81500A devices. 22 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Table5 lists the source of the peripheral control signal for each FLEX8000 device by row. Table 5.Row Sources of FLEX8000 Peripheral Control Signals Peripheral EPF8282A EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A Control Signal EPF8282AV CLK0 Row A Row A Row A Row A Row E Row E CLK1/OE1 Row B Row B Row C Row C Row B Row B CLR0 Row A Row A Row B Row B Row F Row F CLR1/OE0 Row B Row B Row C Row D Row C Row C OE2 Row A Row A Row A Row A Row D Row A OE3 Row B Row B Row B Row B Row A Row A OE4 – – – – – Row B OE5 – – – – – Row C OE6 – – – – – Row D 3 OE7 – – – – – Row D OE8 – – – – – Row E F OE9 – – – – – Row F L E X Output This section discusses slew-rate control and MultiVolt I/O interface 80 0 operation for FLEX8000 devices. 0 Configuration Slew-Rate Control The output buffer in each IOE has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A slow slew rate reduces system noise by slowing signal transitions, adding a maximum delay of 3.5 ns. The slow slew-rate setting affects only the falling edge of a signal. The fast slew rate should be used for speed-critical outputs in systems that are adequately protected against noise. Designers can specify the slew rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a global basis. f For more information on high-speed system design, go to Application Note75 (High-Speed Board Designs). Altera Corporation 23

FLEX 8000 Programmable Logic Device Family Data Sheet MultiVolt I/O Interface The FLEX8000 device architecture supports the MultiVolt I/O interface feature, which allows EPF81500A, EPF81188A, EPF8820A, and EPF8636A devices to interface with systems with differing supply voltages. These devices in all packages—except for EPF8636A devices in 84-pin PLCC packages—can be set for 3.3-V or 5.0-V I/O pin operation. These devices have one set of V pins for internal operation and input buffers CC (VCCINT), and another set for I/O output drivers (VCCIO). The VCCINT pins must always be connected to a 5.0-V power supply. With a 5.0-V V level, input voltages are at TTL levels and are therefore CCINT compatible with 3.3-V and 5.0-V inputs. The VCCIO pins can be connected to either a 3.3-V or 5.0-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 5.0-V power supply, the output levels are compatible with 5.0-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is at 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with V levels lower than 4.75 V CCIO incur a nominally greater timing delay of t instead of t . See Table8 OD2 OD1 on page26. IEEE Std. The EPF8282A, EPF8282AV, EPF8636A, EPF8820A, and EPF81500A devices provide JTAG BST circuitry. FLEX8000 devices with JTAG 1149.1 (JTAG) circuitry support the JTAG instructions shown in Table6. Boundary-Scan Support Table 6.EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Instructions JTAG Instruction Description SAMPLE/PRELOAD Allows a snapshot of the signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through the selected device to adjacent devices during normal device operation. 24 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet The instruction register length for FLEX 8000 devices is three bits. Table7 shows the boundary-scan register length for FLEX 8000 devices. Table 7.FLEX 8000 Boundary-Scan Register Length Device Boundary-Scan Register Length EPF8282A, EPF8282AV 273 EPF8636A 417 EPF8820A 465 EPF81500A 645 FLEX8000 devices that support JTAG include weak pull-ups on the JTAG pins. Figure14 shows the timing requirements for the JTAG signals. Figure 14. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Waveforms TMS 3 TDI F L E tJCP X 8 tJCH tJCL tJPSU tJPH 00 0 TCK tJPZX tJPCO tJPXZ TDO tJSSU tJSH Signal to Be Captured tJSZX tJSCO tJSXZ Signal to Be Driven Table8 shows the timing parameters and values for EPF8282A, EPF8282AV, EPF8636A, EPF8820A, and EPF81500A devices. Altera Corporation 25

FLEX 8000 Programmable Logic Device Family Data Sheet Table 8. JTAG Timing Parameters & Values Symbol Parameter EPF8282A Unit EPF8282AV EPF8636A EPF8820A EPF81500A Min Max t TCK clock period 100 ns JCP t TCK clock high time 50 ns JCH t TCK clock low time 50 ns JCL t JTAG port setup time 20 ns JPSU t JTAG port hold time 45 ns JPH t JTAG port clock to output 25 ns JPCO t JTAG port high-impedance to valid output 25 ns JPZX t JTAG port valid output to high-impedance 25 ns JPXZ t Capture register setup time 20 ns JSSU t Capture register hold time 45 ns JSH t Update register clock to output 35 ns JSCO t Update register high-impedance to valid output 35 ns JSZX t Update register valid output to high-impedance 35 ns JSXZ f For detailed information on JTAG operation in FLEX8000 devices, refer to Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices). Generic Testing Each FLEX8000 device is functionally tested and specified by Altera. Complete testing of each configurable SRAM bit and all logic functionality ensures 100% configuration yield. AC test measurements for FLEX8000 devices are made under conditions equivalent tothose shown in Figure15. Designers can use multiple test patterns to configure devices during all stages of the production flow. 26 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Figure 15. FLEX8000 AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for VCC accurate measurement. Threshold tests 464 Ω must not be performed under AC (703 Ω) conditions. Large-amplitude, fast-ground- current transients normally occur as the Device To Test Output System device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between 250 Ω the device ground pin and the test system (8.06 KΩ) C1 (includes ground, significant reductions in JIG capacitance) observable noise immunity can result. Device input Numbers in parentheses are for 3.3-V rise and fall devices or outputs. Numbers without times < 3 ns parentheses are for 5.0-V devices or outputs. Operating Tables9 through 12 provide information on absolute maximum ratings, 3 recommended operating conditions, operating conditions, and Conditions capacitance for 5.0-V FLEX8000 devices. F L Table 9.FLEX8000 5.0-V Device Absolute Maximum Ratings Note (1) EX 8 0 Symbol Parameter Conditions Min Max Unit 0 0 V Supply voltage With respect to ground (2) –2.0 7.0 V CC V DC input voltage –2.0 7.0 V I I DC output current, per pin –25 25 mA OUT T Storage temperature No bias –65 150 ° C STG T Ambient temperature Under bias –65 135 ° C AMB T Junction temperature Ceramic packages, under bias 150 ° C J PQFP and RQFP, under bias 135 ° C Altera Corporation 27

FLEX 8000 Programmable Logic Device Family Data Sheet Table 10.FLEX8000 5.0-V Device Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit V Supply voltage for internal logic (3), (4) 4.75 (4.50) 5.25 (5.50) V CCINT and input buffers V Supply voltage for output (3), (4) 4.75 (4.50) 5.25 (5.50) V CCIO buffers, 5.0-V operation Supply voltage for output (3), (4) 3.00 (3.00) 3.60 (3.60) V buffers, 3.3-V operation V Input voltage –0.5 V + 0.5 V I CCINT V Output voltage 0 V V O CCIO T Operating temperature For commercial use 0 70 ° C A For industrial use –40 85 ° C t Input rise time 40 ns R t Input fall time 40 ns F Table 11.FLEX8000 5.0-V Device DC Operating Conditions Notes (5), (6) Symbol Parameter Conditions Min Typ Max Unit V High-level input voltage 2.0 V + 0.5 V IH CCINT V Low-level input voltage –0.5 0.8 V IL V 5.0-V high-level TTL output I = –4 mA DC (7) 2.4 V OH OH voltage V = 4.75 V CCIO 3.3-V high-level TTL output I = –4 mA DC (7) 2.4 V OH voltage V = 3.00 V CCIO 3.3-V high-level CMOS output I = –0.1 mA DC (7) V – 0.2 V OH CCIO voltage V = 3.00 V CCIO V 5.0-V low-level TTL output I = 12 mA DC (7) 0.45 V OL OL voltage V = 4.75 V CCIO 3.3-V low-level TTL output I = 12 mA DC (7) 0.45 V OL voltage V = 3.00 V CCIO 3.3-V low-level CMOS output I = 0.1 mA DC (7) 0.2 V OL voltage V = 3.00 V CCIO I Input leakage current V = V or ground –10 10 µA I I CC I Tri-state output off-state V = V or ground –40 40 µA OZ O CC current I V supply current (standby) V = ground, no load 0.5 10 mA CC0 CC I 28 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Table 12.FLEX8000 5.0-V Device Capacitance Note (8) Symbol Parameter Conditions Min Max Unit C Input capacitance V = 0 V, f = 1.0 MHz 10 pF IN IN C Output capacitance V = 0 V, f = 1.0 MHz 10 pF OUT OUT Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) The maximum VCC rise time is 100ms. (4) Numbers in parentheses are for industrial-temperature-range devices. (5) Typical values are for TA = 25° C and VCC = 5.0 V. (6) These values are specified in Table10 on page28. (7) The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL or CMOS output current. (8) Capacitance is sample-tested only. Tables13 through 16 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for 3.3-V FLEX8000 devices. 3 Table 13.FLEX8000 3.3-V Device Absolute Maximum Ratings Note (1) F L E Symbol Parameter Conditions Min Max Unit X 8 0 VCC Supply voltage With respect to ground (2) –2.0 5.3 V 00 V DC input voltage –2.0 5.3 V I I DC output current, per pin –25 25 mA OUT T Storage temperature No bias –65 150 ° C STG T Ambient temperature Under bias –65 135 ° C AMB T Junction temperature Plastic packages, under bias 135 ° C J Table 14.FLEX8000 3.3-V Device Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit V Supply voltage (3) 3.0 3.6 V CC V Input voltage –0.3 V + 0.3 V I CC V Output voltage 0 V V O CC T Operating temperature For commercial use 0 70 ° C A t Input rise time 40 ns R t Input fall time 40 ns F Altera Corporation 29

FLEX 8000 Programmable Logic Device Family Data Sheet Table 15.FLEX8000 3.3-V Device DC Operating Conditions Note (4) Symbol Parameter Conditions Min Typ Max Unit V High-level input voltage 2.0 V + 0.3 V IH CC V Low-level input voltage –0.3 0.8 V IL V High-level output voltage I = –0.1 mA DC (5) V – 0.2 V OH OH CC V Low-level output voltage I = 4 mA DC (5) 0.45 V OL OL I Input leakage current V = V or ground –10 10 µA I I CC I Tri-state output off-state current V = V or ground –40 40 µA OZ O CC I V supply current (standby) V = ground, no load (6) 0.3 10 mA CC0 CC I Table 16.FLEX8000 3.3-V Device Capacitance Note (7) Symbol Parameter Conditions Min Max Unit C Input capacitance V = 0 V, f = 1.0 MHz 10 pF IN IN C Output capacitance V = 0 V, f = 1.0 MHz 10 pF OUT OUT Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Minimum DC input voltage is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.3V for input currents less than 100 mA and periods shorter than 20 ns. (3) The maximum VCC rise time is 100 ms. VCC must rise monotonically. (4) These values are specified in Table14 on page29. (5) The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current. (6) Typical values are for TA = 25° C and VCC = 3.3 V. (7) Capacitance is sample-tested only. Figure16 shows the typical output drive characteristics of 5.0-V FLEX8000 devices. The output driver is compliant with PCI Local Bus Specification, Revision 2.2. 30 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Figure 16. Output Drive Characteristics of 5.0-V FLEX8000 Devices (Except EPF8282A) 200 200 150 IOL 150 IOL TOyuptpicuatl IO Typical IO Output Current (mA) Current (mA) 100 VCCINT = 5.0 V 100 VCCINT = 5.0 V VCCIO = 5.0 V VCCIO = 3.3 V Room Temperature Room Temperature I I OH 50 OH 50 1 2 3 4 5 1 2 3 4 Output Voltage (V) Output Voltage (V) Figure17 shows the typical output drive characteristics of 5.0-V EPF8282A devices. The output driver is compliant with PCI Local Bus 3 Specification, Revision 2.2. Figure 17. Output Drive Characteristics of EPF8282A Devices with 5.0-V VCCIO F L E X 150 IOL 8 0 0 0 120 V = 5.0 V CC Typical IO Room Temperature Output 90 Current (mA) I OH 60 30 1 2 3 4 5 Output Voltage (V) Figure18 shows the typical output drive characteristics of EPF8282AV devices. Altera Corporation 31

FLEX 8000 Programmable Logic Device Family Data Sheet Figure 18. Output Drive Characteristics of EPF8282AV Devices 100 I 75 OL Typical IO Output 50 VCC = 3.3 V Current (mA) Room Temperature I OH 25 1 2 3 4 Output Voltage (V) Timing Model The continuous, high-performance FastTrack Interconnect routing structure ensures predictable performance and accurate simulation and timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and hence have unpredictable performance. Timing simulation and delay prediction are available with the MAX+PLUSII Simulator and Timing Analyzer, or with industry-standard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post- synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer provides point-to-point timing delay information, setup and hold time prediction, and device-wide performance analysis. Tables17 through 20 describe the FLEX8000 timing parameters and their symbols. 32 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Table 17.FLEX8000 Internal Timing Parameters Note (1) Symbol Parameter t IOE register data delay IOD t IOE register control signal delay IOC t Output enable delay IOE t IOE register clock-to-output delay IOCO t IOE combinatorial delay IOCOMB t IOE register setup time before clock; IOE register recovery time after asynchronous clear IOSU t IOE register hold time after clock IOH t IOE register clear delay IOCLR t Input pad and buffer delay IN t Output buffer and pad delay, slow slew rate = off, V = 5.0 V C1 = 35 pF (2) OD1 CCIO t Output buffer and pad delay, slow slew rate = off, V = 3.3 V C1 = 35 pF (2) OD2 CCIO t Output buffer and pad delay, slow slew rate = on, C1 = 35 pF (3) OD3 t Output buffer disable delay, C1 = 5 pF XZ t Output buffer enable delay, slow slew rate = off, V = 5.0 V, C1 = 35 pF (2) 3 ZX1 CCIO t Output buffer enable delay, slow slew rate = off, V = 3.3 V, C1 = 35 pF (2) ZX2 CCIO t Output buffer enable delay, slow slew rate = on, C1 = 35 pF (3) ZX3 F L E X Table 18.FLEX8000 LE Timing Parameters Note (1) 8 0 0 0 Symbol Parameter t LUT delay for data-in LUT t LUT delay for carry-in CLUT t LUT delay for LE register feedback RLUT t Cascade gate delay GATE t Cascade chain routing delay CASC t Carry-in to carry-out delay CICO t Data-in to carry-out delay CGEN t LE register feedback to carry-out delay CGENR t LE register control signal delay C t LE register clock high time CH t LE register clock low time CL t LE register clock-to-output delay CO t Combinatorial delay COMB t LE register setup time before clock; LE register recovery time after asynchronous preset, clear, or SU load t LE register hold time after clock H t LE register preset delay PRE t LE register clear delay CLR Altera Corporation 33

FLEX 8000 Programmable Logic Device Family Data Sheet Table 19.FLEX8000 Interconnect Timing Parameters Note (1) Symbol Parameter t Cascade delay between LEs in different LABs LABCASC t Carry delay between LEs in different LABs LABCARRY t LAB local interconnect delay LOCAL t Row interconnect routing delay (4) ROW t Column interconnect routing delay COL t Dedicated input to LE control delay DIN_C t Dedicated input to LE data delay (4) DIN_D t Dedicated input to IOE control delay DIN_IO Table 20.FLEX8000 External Reference Timing Characteristics Note (5) Symbol Parameter t Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local interconnects (6) DRR t Output data hold time after clock (7) ODH Notes to tables: (1) Internal timing parameters cannot be measured explicitly. They are worst-case delays based on testable and external parameters specified by Altera. Internal timing parameters should be used for estimating device performance. Post-compilation timing simulation or timing analysis is required to determine actual worst-case performance. (2) These values are specified in Table10 on page28 or Table14 on page29. (3) For the tOD3 and tZX3 parameters, VCCIO = 3.3 V or 5.0 V. (4) The tROW and tDIN_D delays are worst-case values for typical applications. Post-compilation timing simulation or timing analysis is required to determine actual worst-case performance. (5) External reference timing characteristics are factory-tested, worst-case values specified by Altera. A representative subset of signal paths is tested to approximate typical device applications. (6) For more information on test conditions, see Application Note 76 (Understanding FLEX8000 Timing). (7) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies to global and non-global clocking, and for LE and I/O element registers. The FLEX8000 timing model shows the delays for various paths and functions in the circuit. See Figure19. This model contains three distinct parts: the LE; the IOE; and the interconnect, including the row and column FastTrack Interconnect, LAB local interconnect, and carry and cascade interconnect paths. Each parameter shown in Figure19 is expressed as a worst-case value in Tables22 through 49. Hand-calculations that use the FLEX8000 timing model and these timing parameters can be used to estimate FLEX8000 device performance. Timing simulation or timing analysis after compilation is required to determine the final worst-case performance. Table21 summarizes the interconnect paths shown in Figure19. f For more information on timing parameters, go to Application Note 76 (Understanding FLEX8000 Timing). 34 Altera Corporation

A F lte igu ra re C 1 o 9 rpo tROW . FL ratio CPraervryio-Iuns f rLoEm CPraesvciaodues -LInE from EX8 n 0 0 LE IOE 0 T Cascade Register Output Data I/O Register Output im LUT Delay Gate Delay Delays Delay Delays Delays in tLUT g M tLOCAL CtttCRaCLLrGDrUUEyeTTN lCahyain tGATE ttttttCCSHPCUROOLREMB LE-Out tCOL I/OC tRoIOtneIDOtgrCioslter tttttIIIIIOOOOOCCSHCUOOLRMB tttttttOOOXZZZXXXZDDD123123 I/O Pin odel tCGENR F L tCICO tIOE EX 8 Input 0 Register Delay 00 Control P r tIN og tC tCASC CRoausctiandg eDelay ramm Data-In a b le L o g Dedicated ic Input Delays D tDIN_D tLABCARRY tLABCASC ev tDIN_C ice tDIN_IO Fa Carry-Out Carry-Out Cascade-Out Cascade-Out m tiLnoA SNBaemxte LE tiLnoA NNBeexxtt LE tNoe Nxte LxtA LBE in tSoa Nmeex tL LAEB in ily D a ta S h 35 eet 0008 XELF 3

FLEX 8000 Programmable Logic Device Family Data Sheet Table 21.FLEX8000 Timing Model Interconnect Paths Source Destination Total Delay LE-Out LE in same LAB tLOCAL LE-Out LE in same row, different LAB tROW + tLOCAL LE-Out LE in different row tCOL + tROW + tLOCAL LE-Out IOE on column tCOL LE-Out IOE on row tROW IOE on row LE in same row tROW + tLOCAL IOE on column Any LE tCOL + tROW + tLOCAL Tables22 through 49 show the FLEX8000 internal and external timing parameters. Table 22.EPF8282A Internal I/O Element Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 0.7 0.8 0.9 ns IOD t 1.7 1.8 1.9 ns IOC t 1.7 1.8 1.9 ns IOE t 1.0 1.0 1.0 ns IOCO t 0.3 0.2 0.1 ns IOCOMB t 1.4 1.6 1.8 ns IOSU t 0.0 0.0 0.0 ns IOH t 1.2 1.2 1.2 ns IOCLR t 1.5 1.6 1.7 ns IN t 1.1 1.4 1.7 ns OD1 t – – – ns OD2 t 4.6 4.9 5.2 ns OD3 t 1.4 1.6 1.8 ns XZ t 1.4 1.6 1.8 ns ZX1 t – – – ns ZX2 t 4.9 5.1 5.3 ns ZX3 36 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Table 23.EPF8282A Interconnect Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 0.3 0.3 0.4 ns LABCASC t 0.3 0.3 0.4 ns LABCARRY t 0.5 0.6 0.8 ns LOCAL t 4.2 4.2 4.2 ns ROW t 2.5 2.5 2.5 ns COL t 5.0 5.0 5.5 ns DIN_C t 7.2 7.2 7.2 ns DIN_D t 5.0 5.0 5.5 ns DIN_IO 3 F L E X 8 0 0 0 Altera Corporation 37

FLEX 8000 Programmable Logic Device Family Data Sheet Table 24.EPF8282A LE Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 2.0 2.5 3.2 ns LUT t 0.0 0.0 0.0 ns CLUT t 0.9 1.1 1.5 ns RLUT t 0.0 0.0 0.0 ns GATE t 0.6 0.7 0.9 ns CASC t 0.4 0.5 0.6 ns CICO t 0.4 0.5 0.7 ns CGEN t 0.9 1.1 1.5 ns CGENR t 1.6 2.0 2.5 ns C t 4.0 4.0 4.0 ns CH t 4.0 4.0 4.0 ns CL t 0.4 0.5 0.6 ns CO t 0.4 0.5 0.6 ns COMB t 0.8 1.1 1.2 ns SU t 0.9 1.1 1.5 ns H t 0.6 0.7 0.8 ns PRE t 0.6 0.7 0.8 ns CLR Table 25.EPF8282A External Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 15.8 19.8 24.8 ns DRR t 1.0 1.0 1.0 ns ODH 38 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Table 26.EPF8282AV I/O Element Timing Parameters Symbol Speed Grade Unit A-3 A-4 Min Max Min Max t 0.9 2.2 ns IOD t 1.9 2.0 ns IOC t 1.9 2.0 ns IOE t 1.0 2.0 ns IOCO t 0.1 0.0 ns IOCOMB t 1.8 2.8 ns IOSU t 0.0 0.2 ns IOH t 1.2 2.3 ns IOCLR t 1.7 3.4 ns IN t 1.7 4.1 ns OD1 tOD2 – – ns 3 t 5.2 7.1 ns OD3 t 1.8 4.3 ns XZ tZX1 1.8 4.3 ns FL E t – – ns X ZX2 8 t 5.3 8.3 ns 0 ZX3 0 0 Table 27.EPF8282AV Interconnect Timing Parameters Symbol Speed Grade Unit A-3 A-4 Min Max Min Max t 0.4 1.3 ns LABCASC t 0.4 0.8 ns LABCARRY t 0.8 1.5 ns LOCAL t 4.2 6.3 ns ROW t 2.5 3.8 ns COL t 5.5 8.0 ns DIN_C t 7.2 10.8 ns DIN_D t 5.5 9.0 ns DIN_IO Altera Corporation 39

FLEX 8000 Programmable Logic Device Family Data Sheet Table 28.EPF8282AV Logic Element Timing Parameters Symbol Speed Grade Unit A-3 A-4 Min Max Min Max t 3.2 7.3 ns LUT t 0.0 1.4 ns CLUT t 1.5 5.1 ns RLUT t 0.0 0.0 ns GATE t 0.9 2.8 ns CASC t 0.6 1.5 ns CICO t 0.7 2.2 ns CGEN t 1.5 3.7 ns CGENR t 2.5 4.7 ns C t 4.0 6.0 ns CH t 4.0 6.0 ns CL t 0.6 0.9 ns CO t 0.6 0.9 ns COMB t 1.2 2.4 ns SU t 1.5 4.6 ns H t 0.8 1.3 ns PRE t 0.8 1.3 ns CLR Table 29.EPF8282AV External Timing Parameters Symbol Speed Grade Unit A-3 A-4 Min Max Min Max t 24.8 50.1 ns DRR t 1.0 1.0 ns ODH 40 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Table 30.EPF8452A I/O Element Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 0.7 0.8 0.9 ns IOD t 1.7 1.8 1.9 ns IOC t 1.7 1.8 1.9 ns IOE t 1.0 1.0 1.0 ns IOCO t 0.3 0.2 0.1 ns IOCOMB t 1.4 1.6 1.8 ns IOSU t 0.0 0.0 0.0 ns IOH t 1.2 1.2 1.2 ns IOCLR t 1.5 1.6 1.7 ns IN tOD1 1.1 1.4 1.7 ns 3 t – – – ns OD2 t 4.6 4.9 5.2 ns OD3 t 1.4 1.6 1.8 ns F XZ L E tZX1 1.4 1.6 1.8 ns X 8 tZX2 – – – ns 00 t 4.9 5.1 5.3 ns 0 ZX3 Table 31.EPF8452A Interconnect Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 0.3 0.4 0.4 ns LABCASC t 0.3 0.4 0.4 ns LABCARRY t 0.5 0.5 0.7 ns LOCAL t 5.0 5.0 5.0 ns ROW t 3.0 3.0 3.0 ns COL t 5.0 5.0 5.5 ns DIN_C t 7.0 7.0 7.5 ns DIN_D t 5.0 5.0 5.5 ns DIN_IO Altera Corporation 41

FLEX 8000 Programmable Logic Device Family Data Sheet Table 32.EPF8452A LE Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 2.0 2.3 3.0 ns LUT t 0.0 0.2 0.1 ns CLUT t 0.9 1.6 1.6 ns RLUT t 0.0 0.0 0.0 ns GATE t 0.6 0.7 0.9 ns CASC t 0.4 0.5 0.6 ns CICO t 0.4 0.9 0.8 ns CGEN t 0.9 1.4 1.5 ns CGENR t 1.6 1.8 2.4 ns C t 4.0 4.0 4.0 ns CH t 4.0 4.0 4.0 ns CL t 0.4 0.5 0.6 ns CO t 0.4 0.5 0.6 ns COMB t 0.8 1.0 1.1 ns SU t 0.9 1.1 1.4 ns H t 0.6 0.7 0.8 ns PRE t 0.6 0.7 0.8 ns CLR Table 33.EPF8452A External Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 16.0 20.0 25.0 ns DRR t 1.0 1.0 1.0 ns ODH 42 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Table 34.EPF8636A I/O Element Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 0.7 0.8 0.9 ns IOD t 1.7 1.8 1.9 ns IOC t 1.7 1.8 1.9 ns IOE t 1.0 1.0 1.0 ns IOCO t 0.3 0.2 0.1 ns IOCOMB t 1.4 1.6 1.8 ns IOSU t 0.0 0.0 0.0 ns IOH t 1.2 1.2 1.2 ns IOCLR t 1.5 1.6 1.7 ns IN t 1.1 1.4 1.7 ns OD1 tOD2 1.6 1.9 2.2 ns 3 t 4.6 4.9 5.2 ns OD3 t 1.4 1.6 1.8 ns XZ tZX1 1.4 1.6 1.8 ns FL E t 1.9 2.1 2.3 ns X ZX2 8 t 4.9 5.1 5.3 ns 0 ZX3 0 0 Table 35.EPF8636A Interconnect Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 0.3 0.4 0.4 ns LABCASC t 0.3 0.4 0.4 ns LABCARRY t 0.5 0.5 0.7 ns LOCAL t 5.0 5.0 5.0 ns ROW t 3.0 3.0 3.0 ns COL t 5.0 5.0 5.5 ns DIN_C t 7.0 7.0 7.5 ns DIN_D t 5.0 5.0 5.5 ns DIN_IO Altera Corporation 43

FLEX 8000 Programmable Logic Device Family Data Sheet Table 36.EPF8636A LE Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 2.0 2.3 3.0 ns LUT t 0.0 0.2 0.1 ns CLUT t 0.9 1.6 1.6 ns RLUT t 0.0 0.0 0.0 ns GATE t 0.6 0.7 0.9 ns CASC t 0.4 0.5 0.6 ns CICO t 0.4 0.9 0.8 ns CGEN t 0.9 1.4 1.5 ns CGENR t 1.6 1.8 2.4 ns C t 4.0 4.0 4.0 ns CH t 4.0 4.0 4.0 ns CL t 0.4 0.5 0.6 ns CO t 0.4 0.5 0.6 ns COMB t 0.8 1.0 1.1 ns SU t 0.9 1.1 1.4 ns H t 0.6 0.7 0.8 ns PRE t 0.6 0.7 0.8 ns CLR Table 37.EPF8636A External Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 16.0 20.0 25.0 ns DRR t 1.0 1.0 1.0 ns ODH 44 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Table 38.EPF8820A I/O Element Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 0.7 0.8 0.9 ns IOD t 1.7 1.8 1.9 ns IOC t 1.7 1.8 1.9 ns IOE t 1.0 1.0 1.0 ns IOCO t 0.3 0.2 0.1 ns IOCOMB t 1.4 1.6 1.8 ns IOSU t 0.0 0.0 0.0 ns IOH t 1.2 1.2 1.2 ns IOCLR t 1.5 1.6 1.7 ns IN t 1.1 1.4 1.7 ns OD1 tOD2 1.6 1.9 2.2 ns 3 t 4.6 4.9 5.2 ns OD3 t 1.4 1.6 1.8 ns XZ tZX1 1.4 1.6 1.8 ns FL E t 1.9 2.1 2.3 ns X ZX2 8 t 4.9 5.1 5.3 ns 0 ZX3 0 0 Table 39.EPF8820A Interconnect Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 0.3 0.3 0.4 ns LABCASC t 0.3 0.3 0.4 ns LABCARRY t 0.5 0.6 0.8 ns LOCAL t 5.0 5.0 5.0 ns ROW t 3.0 3.0 3.0 ns COL t 5.0 5.0 5.5 ns DIN_C t 7.0 7.0 7.5 ns DIN_D t 5.0 5.0 5.5 ns DIN_IO Altera Corporation 45

FLEX 8000 Programmable Logic Device Family Data Sheet Table 40.EPF8820A LE Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 2.0 2.5 3.2 ns LUT t 0.0 0.0 0.0 ns CLUT t 0.9 1.1 1.5 ns RLUT t 0.0 0.0 0.0 ns GATE t 0.6 0.7 0.9 ns CASC t 0.4 0.5 0.6 ns CICO t 0.4 0.5 0.7 ns CGEN t 0.9 1.1 1.5 ns CGENR t 1.6 2.0 2.5 ns C t 4.0 4.0 4.0 ns CH t 4.0 4.0 4.0 ns CL t 0.4 0.5 0.6 ns CO t 0.4 0.5 0.6 ns COMB t 0.8 1.1 1.2 ns SU t 0.9 1.1 1.5 ns H t 0.6 0.7 0.8 ns PRE t 0.6 0.7 0.8 ns CLR Table 41.EPF8820A External Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 16.0 20.0 25.0 ns DRR t 1.0 1.0 1.0 ns ODH 46 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Table 42.EPF81188A I/O Element Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 0.7 0.8 0.9 ns IOD t 1.7 1.8 1.9 ns IOC t 1.7 1.8 1.9 ns IOE t 1.0 1.0 1.0 ns IOCO t 0.3 0.2 0.1 ns IOCOMB t 1.4 1.6 1.8 ns IOSU t 0.0 0.0 0.0 ns IOH t 1.2 1.2 1.2 ns IOCLR t 1.5 1.6 1.7 ns IN t 1.1 1.4 1.7 ns OD1 tOD2 1.6 1.9 2.2 ns 3 t 4.6 4.9 5.2 ns OD3 t 1.4 1.6 1.8 ns XZ tZX1 1.4 1.6 1.8 ns FL E t 1.9 2.1 2.3 ns X ZX2 8 t 4.9 5.1 5.3 ns 0 ZX3 0 0 Table 43.EPF81188A Interconnect Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 0.3 0.3 0.4 ns LABCASC t 0.3 0.3 0.4 ns LABCARRY t 0.5 0.6 0.8 ns LOCAL t 5.0 5.0 5.0 ns ROW t 3.0 3.0 3.0 ns COL t 5.0 5.0 5.5 ns DIN_C t 7.0 7.0 7.5 ns DIN_D t 5.0 5.0 5.5 ns DIN_IO Altera Corporation 47

FLEX 8000 Programmable Logic Device Family Data Sheet Table 44.EPF81188A LE Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 2.0 2.5 3.2 ns LUT t 0.0 0.0 0.0 ns CLUT t 0.9 1.1 1.5 ns RLUT t 0.0 0.0 0.0 ns GATE t 0.6 0.7 0.9 ns CASC t 0.4 0.5 0.6 ns CICO t 0.4 0.5 0.7 ns CGEN t 0.9 1.1 1.5 ns CGENR t 1.6 2.0 2.5 ns C t 4.0 4.0 4.0 ns CH t 4.0 4.0 4.0 ns CL t 0.4 0.5 0.6 ns CO t 0.4 0.5 0.6 ns COMB t 0.8 1.1 1.2 ns SU t 0.9 1.1 1.5 ns H t 0.6 0.7 0.8 ns PRE t 0.6 0.7 0.8 ns CLR Table 45.EPF81188A External Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 16.0 20.0 25.0 ns DRR t 1.0 1.0 1.0 ns ODH 48 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Table 46.EPF81500A I/O Element Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 0.7 0.8 0.9 ns IOD t 1.7 1.8 1.9 ns IOC t 1.7 1.8 1.9 ns IOE t 1.0 1.0 1.0 ns IOCO t 0.3 0.2 0.1 ns IOCOMB t 1.4 1.6 1.8 ns IOSU t 0.0 0.0 0.0 ns IOH t 1.2 1.2 1.2 ns IOCLR t 1.5 1.6 1.7 ns IN t 1.1 1.4 1.7 ns OD1 tOD2 1.6 1.9 2.2 ns 3 t 4.6 4.9 5.2 ns OD3 t 1.4 1.6 1.8 ns XZ tZX1 1.4 1.6 1.8 ns FL E t 1.9 2.1 2.3 ns X ZX2 8 t 4.9 5.1 5.3 ns 0 ZX3 0 0 Table 47.EPF81500A Interconnect Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 0.3 0.3 0.4 ns LABCASC t 0.3 0.3 0.4 ns LABCARRY t 0.5 0.6 0.8 ns LOCAL t 6.2 6.2 6.2 ns ROW t 3.0 3.0 3.0 ns COL t 5.0 5.0 5.5 ns DIN_C t 8.2 8.2 8.7 ns DIN_D t 5.0 5.0 5.5 ns DIN_IO Altera Corporation 49

FLEX 8000 Programmable Logic Device Family Data Sheet Table 48.EPF81500A LE Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 2.0 2.5 3.2 ns LUT t 0.0 0.0 0.0 ns CLUT t 0.9 1.1 1.5 ns RLUT t 0.0 0.0 0.0 ns GATE t 0.6 0.7 0.9 ns CASC t 0.4 0.5 0.6 ns CICO t 0.4 0.5 0.7 ns CGEN t 0.9 1.1 1.5 ns CGENR t 1.6 2.0 2.5 ns C t 4.0 4.0 4.0 ns CH t 4.0 4.0 4.0 ns CL t 0.4 0.5 0.6 ns CO t 0.4 0.5 0.6 ns COMB t 0.8 1.1 1.2 ns SU t 0.9 1.1 1.5 ns H t 0.6 0.7 0.8 ns PRE t 0.6 0.7 0.8 ns CLR Table 49.EPF81500A External Timing Parameters Symbol Speed Grade Unit A-2 A-3 A-4 Min Max Min Max Min Max t 16.1 20.1 25.1 ns DRR t 1.0 1.0 1.0 ns ODH 50 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Power The supply power (P) for FLEX8000 devices can be calculated with the following equation: Consumption P = PINT + PIO = [(ICCSTANDBY + ICCACTIVE) × VCC] + PIO Typical I values are shown as I in Table11 on page28 and CCSTANDBY CC0 Table15 on page30. The P value, which depends on the device output IO load characteristics and switching frequency, can be calculated using the guidelines given in Application Note74 (Evaluating Power for Altera Devices). The I value depends on the switching frequency and CCACTIVE the application logic. This value can be calculated based on the amount of current that each LE typically consumes. The following equation shows the general formula for calculating I : CCACTIVE ICCACTIVE = K×fMAX×N×togLC×M------H----µ--z--A--×-----L----E--- The parameters in this equation are shown below: 3 f = Maximum operating frequency in MHz MAX N = Total number of logic cells used in the device tog = Average percentage of logic cells toggling at each clock F LC L K = Constant, shown in Table50 E X 8 0 0 Table 50.Values for Constant K 0 Device K 5.0-V FLEX8000 devices 75 3.3-V FLEX8000 devices 60 This calculation provides an I estimate based on typical conditions CC with no output load. The actual I value should be verified during CC operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. Figure20 shows the relationship between I and operating frequency CC for several LE utilization values. Altera Corporation 51

FLEX 8000 Programmable Logic Device Family Data Sheet Figure 20. FLEX8000 I vs. Operating Frequency CCACTIVE 5.0-V FLEX8000 Devices 1,000 1,500 LEs 800 600 ICC Supply 1,000 LEs Current (mA) 400 500 LEs 200 0 30 60 Frequency (MHz) 3.3-V FLEX8000 Devices 100 90 200 LEs 80 70 150 LEs 60 ICCuCr rSeunpt p(mlyA) 50 100 LEs 40 30 50 LEs 20 10 0 30 60 Frequency (MHz) Configuration & The FLEX8000 architecture supports several configuration schemes to load a design into the device(s) on the circuit board. This section Operation summarizes the device operating modes and available device configuration schemes. f For more information, go to Application Note 33 (Configuring FLEX8000 Devices) and Application Note 38 (Configuring Multiple FLEX8000 Devices). 52 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Operating Modes The FLEX8000 architecture uses SRAM elements that require configuration data to be loaded whenever the device powers up and begins operation. The process of physically loading the SRAM programming data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. The configuration and initialization processes together are called command mode; normal device operation is called user mode. SRAM elements allow FLEX8000 devices to be reconfigured in-circuit with new programming data that is loaded into the device. Real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different programming data, reinitializing the device, and resuming user-mode operation. The entire reconfiguration process requires less than 100ms and can be used to dynamically reconfigure an entire system. In-field upgrades can be performed by distributing new configuration files. 3 Configuration Schemes F L The configuration data for a FLEX8000 device can be loaded with one of E X six configuration schemes, chosen on the basis of the target application. 8 0 Both active and passive schemes are available. In the active configuration 0 0 schemes, the FLEX8000 device functions as the controller, directing the loading operation, controlling external configuration devices, and completing the loading process. The clock source for all active configuration schemes is an oscillator on the FLEX8000 device that operates between 2 MHz and 6 MHz. In the passive configuration schemes, an external controller guides the FLEX8000device. Table51 shows the data source for each of the six configuration schemes. Table 51.Data Source for Configuration Configuration Scheme Acronym Data Source Active serial AS Altera configuration device Active parallel up APU Parallel configuration device Active parallel down APD Parallel configuration device Passive serial PS Serial data path Passive parallel synchronous PPS Intelligent host Passive parallel asynchronous PPA Intelligent host Altera Corporation 53

FLEX 8000 Programmable Logic Device Family Data Sheet Device Tables52 through 54 show the pin names and numbers for the dedicated pins in each FLEX8000 device package. Pin-Outs Table 52.FLEX8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part 1 of 3) Pin Name 84-Pin 84-Pin 100-Pin 100-Pin 144-Pin 160-Pin 160-Pin PLCC PLCC TQFP TQFP TQFP PGA PQFP EPF8282A EPF8452A EPF8282A EPF8452A EPF8820A EPF8452A EPF8820A EPF8636A EPF8282AV (1) nSP (2) 75 75 75 76 110 R1 1 MSEL0 (2) 74 74 74 75 109 P2 2 MSEL1 (2) 53 53 51 51 72 A1 44 nSTATUS (2) 32 32 24 25 37 C13 82 nCONFIG (2) 33 33 25 26 38 A15 81 DCLK (2) 10 10 100 100 143 P14 125 CONF_DONE (2) 11 11 1 1 144 N13 124 nWS 30 30 22 23 33 F13 87 nRS 48 48 42 45 31 C6 89 RDCLK 49 49 45 46 12 B5 110 nCS 29 29 21 22 4 D15 118 CS 28 28 19 21 3 E15 121 RDYnBUSY 77 77 77 78 20 P3 100 CLKUSR 50 50 47 47 13 C5 107 ADD17 51 51 49 48 75 B4 40 ADD16 36 55 28 54 76 E2 39 ADD15 56 56 55 55 77 D1 38 ADD14 57 57 57 57 78 E1 37 ADD13 58 58 58 58 79 F3 36 ADD12 60 60 59 60 83 F2 32 ADD11 61 61 60 61 85 F1 30 ADD10 62 62 61 62 87 G2 28 ADD9 63 63 62 64 89 G1 26 ADD8 64 64 64 65 92 H1 22 ADD7 65 65 65 66 94 H2 20 ADD6 66 66 66 67 95 J1 18 ADD5 67 67 67 68 97 J2 16 ADD4 69 69 68 70 102 K2 11 ADD3 70 70 69 71 103 K1 10 ADD2 71 71 71 72 104 K3 8 ADD1 76 72 76 73 105 M1 7 54 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Table 52.FLEX8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part 2 of 3) Pin Name 84-Pin 84-Pin 100-Pin 100-Pin 144-Pin 160-Pin 160-Pin PLCC PLCC TQFP TQFP TQFP PGA PQFP EPF8282A EPF8452A EPF8282A EPF8452A EPF8820A EPF8452A EPF8820A EPF8636A EPF8282AV (1) ADD0 78 76 78 77 106 N3 6 DATA7 3 2 90 89 131 P8 140 DATA6 4 4 91 91 132 P10 139 DATA5 6 6 92 95 133 R12 138 DATA4 7 7 95 96 134 R13 136 DATA3 8 8 97 97 135 P13 135 DATA2 9 9 99 98 137 R14 133 DATA1 13 13 4 4 138 N15 132 DATA0 14 14 5 5 140 K13 129 SDOUT (3) 79 78 79 79 23 P4 97 TDI (4) 55 45 (5) 54 – 96 – 17 3 TDO (4) 27 27 (5) 18 – 18 – 102 TCK (4), (6) 72 44 (5) 72 – 88 – 27 TMS (4) 20 43 (5) 11 – 86 – 29 F L TRST (7) 52 52 (8) 50 – 71 – 45 EX Dedicated 12, 31, 54, 12, 31, 54, 3, 23, 53, 73 3, 24, 53, 9, 26, 82, C3, D14, 14, 33, 94, 80 0 Inputs (10) 73 73 74 99 N2, R15 113 0 VCCINT 17, 38, 59, 17, 38, 59, 6, 20, 37, 56, 9, 32, 49, 8, 28, 70, B2, C4, D3, 3, 24, 46, 80 80 70, 87 59, 82 90, 111 D8, D12, 92, 114, G3, G12, 160 H4, H13, J3, J12, M4, M7, M9, M13, N12 VCCIO – – – – 16, 40, 60, – 23, 47, 57, 69, 91, 69, 79, 112, 122, 104, 127, 141 137, 149, 159 Altera Corporation 55

FLEX 8000 Programmable Logic Device Family Data Sheet Table 52.FLEX8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part 3 of 3) Pin Name 84-Pin 84-Pin 100-Pin 100-Pin 144-Pin 160-Pin 160-Pin PLCC PLCC TQFP TQFP TQFP PGA PQFP EPF8282A EPF8452A EPF8282A EPF8452A EPF8820A EPF8452A EPF8820A EPF8636A EPF8282AV (1) GND 5, 26, 47, 68 5, 26, 47, 2, 13, 30, 44, 19, 44, 69, 7, 17, 27, C12, D4, 12, 13, 34, 68 52, 63, 80, 94 39, 54, D7, D9, 35, 51, 63, 94 80, 81, D13, G4, 75, 80, 83, 100,101, G13, H3, 93, 103, 128, 142 H12, J4, 115, 126, J13, L1, 131, 143, M3, M8, 155 M12, M15, N4 No Connect – – – 2, 6, 13, 30, – – – (N.C.) 37, 42, 43, 50, 52, 56, 63, 80, 87, 92, 93, 99 Total User I/O 64 64 74 64 108 116 116 Pins (9) 56 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Table 53. FLEX8000 160-, 192- & 208-Pin Package Pin-Outs (Part 1 of 2) Pin Name 160-Pin 160-Pin 192-Pin PGA 208-Pin 208-Pin 208-Pin PQFP PQFP EPF8636A PQFP PQFP PQFP EPF8452A EPF8636A EPF8820A EPF8636A (1) EPF8820A (1) EPF81188A (1) nSP (2) 120 1 R15 207 207 5 MSEL0 (2) 117 3 T15 4 4 21 MSEL1 (2) 84 38 T3 49 49 33 nSTATUS (2) 37 83 B3 108 108 124 nCONFIG (2) 40 81 C3 103 103 107 DCLK (2) 1 120 C15 158 158 154 CONF_DONE 4 118 B15 153 153 138 (2) nWS 30 89 C5 114 114 118 nRS 71 50 B5 66 116 121 RDCLK 73 48 C11 64 137 137 nCS 29 91 B13 116 145 142 3 CS 27 93 A16 118 148 144 RDYnBUSY 125 155 A8 201 127 128 F CLKUSR 76 44 A10 59 134 134 L E ADD17 78 43 R5 57 43 46 X 8 ADD16 91 33 U3 43 42 45 0 0 0 ADD15 92 31 T5 41 41 44 ADD14 94 29 U4 39 40 39 ADD13 95 27 R6 37 39 37 ADD12 96 24 T6 31 35 36 ADD11 97 23 R7 30 33 31 ADD10 98 22 T7 29 31 30 ADD9 99 21 T8 28 29 29 ADD8 101 20 U9 24 25 26 ADD7 102 19 U10 23 23 25 ADD6 103 18 U11 22 21 24 ADD5 104 17 U12 21 19 18 ADD4 105 13 R12 14 14 17 ADD3 106 11 U14 12 13 16 ADD2 109 9 U15 10 11 10 ADD1 110 7 R13 8 10 9 ADD0 123 157 U16 203 9 8 DATA7 144 137 H17 178 178 177 DATA6 150 132 G17 172 176 175 DATA5 152 129 F17 169 174 172 Altera Corporation 57

FLEX 8000 Programmable Logic Device Family Data Sheet Table 53. FLEX8000 160-, 192- & 208-Pin Package Pin-Outs (Part 2 of 2) Pin Name 160-Pin 160-Pin 192-Pin PGA 208-Pin 208-Pin 208-Pin PQFP PQFP EPF8636A PQFP PQFP PQFP EPF8452A EPF8636A EPF8820A EPF8636A (1) EPF8820A (1) EPF81188A (1) DATA4 154 127 E17 165 172 170 DATA3 157 124 G15 162 171 168 DATA2 159 122 F15 160 167 166 DATA1 11 115 E16 149 165 163 DATA0 12 113 C16 147 162 161 SDOUT (3) 128 152 C7 (11) 198 124 119 TDI (4) – 55 R11 72 20 – TDO (4) – 95 B9 120 129 – TCK (4), (6) – 57 U8 74 30 – TMS (4) – 59 U7 76 32 – TRST (7) – 40 R3 54 54 – Dedicated 5, 36, 85, 116 6, 35, 87, 116 A5, U5, U13, 7, 45, 112, 17, 36, 121, 13, 41, 116, Inputs (10) A13 150 140 146 VCCINT 21, 41, 53, 67, 4, 5, 26, 85, C8, C9, C10, 5, 6, 33, 110, 5, 6, 27, 48, 4, 20, 35, 48, (5.0 V) 80, 81, 100, 121, 106 R8, R9, R10, 137 119, 141 50, 102, 114, 133, 147, 160 R14 131, 147 VCCIO – 25, 41, 60, 70, D3, D4, D9, 32, 55, 78, 91, 26, 55, 69, 87, 3, 19, 34, 49, (5.0 V or 80, 107, 121, D14, D15, G4, 102, 138, 159, 102, 131, 159, 69, 87, 106, 3.3 V) 140, 149, 160 G14, L4, L14, 182, 193, 206 173, 191, 206 123, 140, 156, P4, P9, P14 174, 192 GND 13, 14, 28, 46, 15, 16, 36, 37, C4, D7, D8, 19, 20, 46, 47, 15, 16, 37, 38, 11, 12, 27, 28, 60, 75, 93, 107, 45, 51, 75, 84, D10, D11, H4, 60, 67, 96, 60, 78, 96, 42, 43, 60, 78, 108, 126, 140, 86, 96, 97, H14, K4, K14, 109, 111, 124, 109, 110, 120, 96, 105, 115, 155 117, 126, 131, P7, P8, P10, 125, 151, 164, 130, 142, 152, 122, 132, 139, 154 P11 171, 200 164, 182, 200 148, 155, 159, 165, 183, 201 No Connect 2, 3, 38, 39, 70, 2, 39, 82, 119 C6, C12, C13, 1, 2, 3, 16, 17, 1, 2, 3, 50, 51, 1, 2, 51, 52, 53, (N.C.) 82, 83, 118, 119, C14, E3, E15, 18, 25, 26, 27, 52, 53, 104, 54, 103, 104, 148 F3, J3, J4, 34, 35, 36, 50, 105, 106, 107, 157, 158, 207, J14, J15, N3, 51, 52, 53, 154, 155, 156, 208 N15, P3, P15, 104, 105, 106, 157, 208 R4 (12) 107, 121, 122, 123, 130, 131, 132, 139, 140, 141, 154, 155, 156, 157, 208 Total User 116 114 132, 148 (13) 132 148 144 I/O Pins (9) 58 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Table 54.FLEX8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 1 of 3) Pin Name 225-Pin 232-Pin 240-Pin 240-Pin 280-Pin 304-Pin BGA PGA PQFP PQFP PGA RQFP EPF8820A EPF81188A EPF81188A EPF81500A EPF81500A EPF81500A nSP (2) A15 C14 237 237 W1 304 MSEL0 (2) B14 G15 21 19 N1 26 MSEL1 (2) R15 L15 40 38 H3 51 nSTATUS (2) P2 L3 141 142 G19 178 nCONFIG (2) R1 R4 117 120 B18 152 DCLK (2) B2 C4 184 183 U18 230 CONF_DONE (2) A1 G3 160 161 M16 204 nWS L4 P1 133 134 F18 167 nRS K5 N1 137 138 G18 171 RDCLK F1 G2 158 159 M17 202 nCS D1 E2 166 167 N16 212 CS C1 E3 169 170 N18 215 3 RDYnBUSY J3 K2 146 147 J17 183 CLKUSR G2 H2 155 156 K19 199 F ADD17 M14 R15 58 56 E3 73 L E ADD16 L12 T17 56 54 E2 71 X 8 ADD15 M15 P15 54 52 F4 69 0 0 0 ADD14 L13 M14 47 45 G1 60 ADD13 L14 M15 45 43 H2 58 ADD12 K13 M16 43 41 H1 56 ADD11 K15 K15 36 34 J3 47 ADD10 J13 K17 34 32 K3 45 ADD9 J15 J14 32 30 K4 43 ADD8 G14 J15 29 27 L1 34 ADD7 G13 H17 27 25 L2 32 ADD6 G11 H15 25 23 M1 30 ADD5 F14 F16 18 16 N2 20 ADD4 E13 F15 16 14 N3 18 ADD3 D15 F14 14 12 N4 16 ADD2 D14 D15 7 5 U1 8 ADD1 E12 B17 5 3 U2 6 ADD0 C15 C15 3 1 V1 4 DATA7 A7 A7 205 199 W13 254 DATA6 D7 D8 203 197 W14 252 DATA5 A6 B7 200 196 W15 250 Altera Corporation 59

FLEX 8000 Programmable Logic Device Family Data Sheet Table 54.FLEX8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 2 of 3) Pin Name 225-Pin 232-Pin 240-Pin 240-Pin 280-Pin 304-Pin BGA PGA PQFP PQFP PGA RQFP EPF8820A EPF81188A EPF81188A EPF81500A EPF81500A EPF81500A DATA4 A5 C7 198 194 W16 248 DATA3 B5 D7 196 193 W17 246 DATA2 E6 B5 194 190 V16 243 DATA1 D5 A3 191 189 U16 241 DATA0 C4 A2 189 187 V17 239 SDOUT (3) K1 N2 135 136 F19 169 TDI F15 (4) – – 63 (14) B1 (14) 80 (14) TDO J2 (4) – – 117 C17 149 TCK (6) J14 (4) – – 116 (14) A19 (14) 148 (14) TMS J12 (4) – – 64 (14) C2 (14) 81 (14) TRST (7) P14 – – 115 (14) A18 (14) 145 (14) Dedicated Inputs F4, L1, K12, C1, C17, R1, 10, 51, 130, 8, 49, 131, F1, F16, P3, 12, 64, 164, (10) E15 R17 171 172 P19 217 VCCINT F5, F10, E1, E4, H4, L4, 20, 42, 64, 66, 18, 40, 60, 62, B17, D3, D15, 24, 54, 77, (5.0 V) L2, K4, M12, P12, L14, 114, 128, 150, 91, 114, 129, E8, E10, E12, 144, 79, 115, P15, H13, H14, E14, 172, 236 151, 173, 209, E14, R7, R9, 162, 191, 218, H14, B15, R14, U1 236 R11, R13, 266, 301 C13 R14, T14 VCCIO H3, H2, P6, N10, M13, 19, 41, 65, 81, 17, 39, 61, 78, D14, E7, E9, 22, 53, 78, 99, (5.0 V or 3.3 V) R6, P10, N10, M5, K13, K5, 99, 116, 140, 94, 108, 130, E11, E13, R6, 119, 137, 163, R14, N13, H13, H5, F5, 162, 186, 202, 152, 174, 191, R8, R10, R12, 193, 220, 244, H15, H12, E10, E8, N8, 220, 235 205, 221, 235 T13, T15 262, 282, 300 D12, A14, F13 B10, A10, B6, C6, A2, C3, M4, R2 60 Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet Table 54.FLEX8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 3 of 3) Pin Name 225-Pin 232-Pin 240-Pin 240-Pin 280-Pin 304-Pin BGA PGA PQFP PQFP PGA RQFP EPF8820A EPF81188A EPF81188A EPF81500A EPF81500A EPF81500A GND B1, D4, E14, A1, D6, E11, 8, 9, 30, 31, 6, 7, 28, 29, D4, D5, D16, 9, 11, 36, 38, F7, F8, F9, E7, E9, G4, 52, 53, 72, 90, 50, 51, 71, 85, E4, E5, E6, 65, 67, 90, F12, G6, G7, G5, G13, 108, 115, 129, 92, 101, 118, E15, E16, F5, 108, 116, G8, G9, G10, G14, J5, J13, 139, 151, 161, 119, 140, 141, F15, G5, G15, 128,150, H1, H4, H5, K4, K14, L5, 173, 185, 187, 162, 163, 184, H5, H15, J5, 151, 175, 177, H6, H7, H8, L13, N4, N7, 193, 211, 229 185, 186, 198, J15, K5, K15, 206, 208, 231, H9, H10, H11, N9, N11, N14 208, 214, 228 L5, L15, M5, 232, 237, 253, J6, J7, J8, J9, M15, N5, 265, 273, 291 J10, K6, K7, N15, P4, P5, K8, K9, K11, P15, P16, R4, L15, N3, P1 R5, R15, R16, T4, T5, T16, U17 3 No Connect – – 61, 62, 119, – – 10, 21, 23, 25, (N.C.) 120, 181, 182, 35, 37, 39, 40, 239, 240 41, 42, 52, 55, F 66, 68, 146, L E 147, 161, 173, X 174, 176, 187, 80 0 188, 189, 190, 0 192, 194, 195, 205, 207, 219, 221, 233, 234, 235, 236, 302, 303 Total User I/O 148 180 180 177 204 204 Pins (9) Altera Corporation 61

FLEX 8000 Programmable Logic Device Family Data Sheet Notes to tables: (1) Perform a complete thermal analysis before committing a design to this device package. See Application Note 74 (Evaluating Power for Altera Devices) for more information. (2) This pin is a dedicated pin and is not available as a user I/O pin. (3) SDOUT will drive out during configuration. After configuration, it may be used as a user I/O pin. By default, the MAX+PLUSII software will not use SDOUT as a user I/O pin; the user can override the MAX+PLUSII software and use SDOUT as a user I/O pin. (4) If the device is not configured to use the JTAG BST circuitry, this pin is available as a user I/O pin. (5) JTAG pins are available for EPF8636A devices only. These pins are dedicated user I/O pins. (6) If this pin is used as an input in user mode, ensure that it does not toggle before or during configuration. (7) TRST is a dedicated input pin for JTAG use. This pin must be grounded if JTAG BST is not used. (8) Pin 52 is a VCC pin on EPF8452A devices only. (9) The user I/O pin count includes dedicated input pins and all I/O pins. (10) Unused dedicated inputs should be tied to ground on the board. (11) SDOUT does not exist in the EPF8636GC192 device. (12) These pins are no connect (N.C.) pins for EPF8636A devices only. They are user I/O pins in EPF8820A devices. (13) EPF8636A devices have 132 user I/O pins; EPF8820A devices have 148 user I/O pins. (14) For EPF81500A devices, these pins are dedicated JTAG pins and are not available as user I/O pins. If JTAG BST is not used, TDI, TCK, TMS, and TRST should be tied to GND. Revision The information contained in the FLEX 8000 Programmable Logic Device Family Data Sheet version 11.1 supersedes information published in History previous versions. The FLEX 8000 Programmable Logic Device Family Data Sheet version 11.1 contains the following change: minor textual updates. 62 Altera Corporation