FLEX 6000 Programmable Logic ® Device Family March 2001, ver. 4.1 Data Sheet Features... ■ Provides an ideal low-cost, programmable alternative to high- volume gate array applications and allows fast design changes during prototyping or design testing ■ Product features – Register-rich, look-up table- (LUT-) based architecture – OptiFLEX® architecture that increases device area efficiency – Typical gates ranging from 5,000 to 24,000 gates (see Table1) – Built-in low-skew clock distribution tree – 100% functional testing of all devices; test vectors or scan chains are not required ■ System-level features – In-circuit reconfigurability (ICR) via external configuration device or intelligent controller – 5.0-V devices are fully compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision2.2 – Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic – MultiVoltTM I/O interface operation, allowing a device to bridge between systems operating at different voltages – Low power consumption (typical specification less than 0.5 mA in standby mode) – 3.3-V devices support hot-socketing Table 1.FLEX 6000 Device Features Feature EPF6010A EPF6016 EPF6016A EPF6024A Typical gates (1) 10,000 16,000 16,000 24,000 Logic elements (LEs) 880 1,320 1,320 1,960 Maximum I/O pins 102 204 171 218 Supply voltage (V ) 3.3 V 5.0 V 3.3 V 3.3 V CCINT Note: (1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates. Altera Corporation 1 A-DS-F6000-04.1

FLEX 6000 Programmable Logic Device Family Data Sheet ...and More ■ Powerful I/O pins – Individual tri-state output enable control for each pin Features – Programmable output slew-rate control to reduce switching noise – Fast path from register to I/O pin for fast clock-to-output time ■ Flexible interconnect – FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – Dedicated cascade chain that implements high-speed, high-fan- in logic functions (automatically used by software tools and megafunctions) – Tri-state emulation that implements internal tri-state networks – Four low-skew global paths for clock, clear, preset, or logic signals ■ Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 ■ Flexible package options – Available in a variety of packages with 100 to 256 pins, including the innovative FineLine BGATM packages (see Table2) – SameFrameTM pin-compatibility (with other FLEX® 6000 devices) across device densities and pin counts – Thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and ball-grid array (BGA) packages (see Table2) – Footprint- and pin-compatibility with other FLEX 6000 devices in the same package ■ Additional design entry and simulation support provided by EDIF20 0 and 3 0 0 netlist files, the library of parameterized modules (LPM), Verilog HDL, VHDL, DesignWare components, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic Table 2.FLEX 6000 Package Options & I/O Pin Count Device 100-Pin 100-Pin 144-Pin 208-Pin 240-Pin 256-Pin 256-pin TQFP FineLine BGA TQFP PQFP PQFP BGA FineLine BGA EPF6010A 71 102 EPF6016 117 171 199 204 EPF6016A 81 81 117 171 171 EPF6024A 117 171 199 218 219 2 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet General The Altera® FLEX 6000 programmable logic device (PLD) family provides a low-cost alternative to high-volume gate array designs. FLEX6000 Description devices are based on the OptiFLEX architecture, which minimizes die size while maintaining high performance and routability. The devices have reconfigurable SRAM elements, which give designers the flexibility to quickly change their designs during prototyping and design testing. Designers can also change functionality during operation via in-circuit reconfiguration. FLEX 6000 devices are reprogrammable, and they are 100% tested prior to shipment. As a result, designers are not required to generate test vectors for fault coverage purposes, allowing them to focus on simulation and design verification. In addition, the designer does not need to manage inventories of different gate array designs. FLEX 6000 devices are configured on the board for the specific functionality required. Table3 shows FLEX 6000 performance for some common designs. All performance values shown were obtained using Synopsys DesignWare or LPM functions. Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file. Table 3.FLEX 6000 Device Performance for Common Designs Application LEs Used Performance Units -1 Speed -2 Speed -3 Speed Grade Grade Grade 16-bit loadable counter 16 172 153 133 MHz 16-bit accumulator 16 172 153 133 MHz 24-bit accumulator 24 136 123 108 MHz 16-to-1 multiplexer (pin-to-pin) (1) 10 12.1 13.4 16.6 ns 16 × 16 multiplier with a 4-stage pipeline 592 84 67 58 MHz Note: (1) This performance value is measured as a pin-to-pin delay. Altera Corporation 3

FLEX 6000 Programmable Logic Device Family Data Sheet Table4 shows FLEX 6000 performance for more complex designs. Table 4.FLEX 6000 Device Performance for Complex Designs Note (1) Application LEs Used Performance Units -1 Speed -2 Speed -3 Speed Grade Grade Grade 8-bit, 16-tap parallel finite impulse response 599 94 80 72 MSPS (FIR) filter 8-bit, 512-point fast Fourier transform (FFT) 1,182 75 89 109 µS function 63 53 43 MHz a16450 universal asynchronous 487 36 30 25 MHz receiver/transmitter (UART) PCI bus target with zero wait states 609 56 49 42 MHz Note: (1) The applications in this table were created using Altera MegaCoreTM functions. FLEX6000 devices are supported by Altera development systems; a single, integrated package that offers schematic, text (including AHDL), and waveform design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, and device configuration. The Altera software provides EDIF200 and 300, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX workstation-based EDA tools. The Altera software works easily with common gate array EDA tools for synthesis and simulation. For example, the Altera software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the Altera software contains EDA libraries that use device- specific features such as carry chains which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the Altera development systems include DesignWare functions that are optimized for the FLEX 6000 architecture. The Altera development system runs on Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800. f See the MAX+PLUSII Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet for more information. 4 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Functional The FLEX 6000 OptiFLEX architecture consists of logic elements (LEs). Each LE includes a 4-input look-up table (LUT), which can implement any Description 4-input function, a register, and dedicated paths for carry and cascade chain functions. Because each LE contains a register, a design can be easily pipelined without consuming more LEs. The specified gate count for FLEX 6000 devices includes all LUTs and registers. LEs are combined into groups called logic array blocks (LABs); each LAB contains 10 LEs. The Altera software automatically places related LEs into the same LAB, minimizing the number of required interconnects. Each LAB can implement a medium-sized block of logic, such as a counter or multiplexer. Signal interconnections within FLEX 6000 devices—and to and from device pins—are provided via the routing structure of the FastTrack Interconnect. The routing structure is a series of fast, continuous row and column channels that run the entire length and width of the device. Any LE or pin can feed or be fed by any other LE or pin via the FastTrack Interconnect. See “FastTrack Interconnect” on page17 of this data sheet for more information. Each I/O pin is fed by an I/O element (IOE) located at the end of each row and column of the FastTrack Interconnect. Each IOE contains a bidirectional I/O buffer. Each IOE is placed next to an LAB, where it can be driven by the local interconnect of that LAB. This feature allows fast clock-to-output times of less than 8 ns when a pin is driven by any of the 10 LEs in the adjacent LAB. Also, any LE can drive any pin via the row and column interconnect. I/O pins can drive the LE registers via the row and column interconnect, providing setup times as low as 2 ns and hold times of 0ns. IOEs provide a variety of features, such as JTAG BST support, slew-rate control, and tri-state buffers. Figure1 shows a block diagram of the FLEX 6000 OptiFLEX architecture. Each group of ten LEs is combined into an LAB, and the LABs are arranged into rows and columns. The LABs are interconnected by the FastTrack Interconnect. IOEs are located at the end of each FastTrack Interconnect row and column. Altera Corporation 5

FLEX 6000 Programmable Logic Device Family Data Sheet Figure 1. OptiFLEX Architecture Block Diagram IOEs Row FastTrack Interconnect Row FastTrack Interconnect IOEs Column FastTrack Interconnect Column FastTrack Interconnect Local Interconnect (Each LAB accesses two local interconnect areas.) Logic Elements FLEX 6000 devices provide four dedicated, global inputs that drive the control inputs of the flipflops to ensure efficient distribution of high- speed, low-skew control signals. These inputs use dedicated routing channels that provide shorter delays and lower skews than the FastTrack Interconnect. These inputs can also be driven by internal logic, providing an ideal solution for a clock divider or an internally generated asynchronous clear signal that clears many registers in the device. The dedicated global routing structure is built into the device, eliminating the need to create a clock tree. Logic Array Block An LAB consists of ten LEs, their associated carry and cascade chains, the LAB control signals, and the LAB local interconnect. The LAB provides the coarse-grained structure of the FLEX 6000 architecture, and facilitates efficient routing with optimum device utilization and high performance. 6 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet The interleaved LAB structure—an innovative feature of the FLEX6000 architecture—allows each LAB to drive two local interconnects. This feature minimizes the use of the FastTrack Interconnect, providing higher performance. An LAB can drive 20 LEs in adjacent LABs via the local interconnect, which maximizes fitting flexibility while minimizing die size. See Figure2. Figure 2. Logic Array Block The row interconnect is bidirectionally connected LEs can directly drive the row Row Interconnect to the local interconnect. and column interconnect. To/From To/From Adjacent Adjacent LAB or IOEs LAB or IOEs Local Interconnect The 10 LEs in the LAB are driven by two Column Interconnect local interconnect areas. The LAB can drive two local interconnect areas. In most designs, the registers only use global clock and clear signals. However, in some cases, other clock or asynchronous clear signals are needed. In addition, counters may also have synchronous clear or load signals. In a design that uses non-global clock and clear signals, inputs from the first LE in an LAB are re-routed to drive the control signals for that LAB. See Figure3. Altera Corporation 7

FLEX 6000 Programmable Logic Device Family Data Sheet Figure 3. LAB Control Signals The dedicated input signals can drive the clock and asynchronous clear signals. Dedicated Inputs 4 Input signals to the first LE in an LAB (i.e., LE 1) can be rerouted to drive LE 1 LABCTRL1/ LABCTRL2 control signals within SYNCLR the LAB. CLK1/SYNLOAD CLK2 LAB-wide control signals (SYNCLR and SYNLOAD signals are used in counter mode). Logic Element An LE, the smallest unit of logic in the FLEX 6000 architecture, has a compact size that provides efficient logic usage. Each LE contains a four- input LUT, which is a function generator that can quickly implement any function of four variables. An LE contains a programmable flipflop, carry and cascade chains. Additionally, each LE drives both the local and the FastTrack Interconnect. See Figure4. 8 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Figure 4. Logic Element Register Bypass Programmable Carry-In Cascade-In Register data1 ddaattaa23 Lo(TLaoUbk-TleU)p CChaarriyn CaCshcaainde DPRNQ LE-Out data4 CLRN labctrl1 Clear/ Preset labctrl2 Chip-Wide Reset Logic Clock Select labctrl3 labctrl4 Carry-Out Cascade-Out The programmable flipflop in the LE can be configured for D, T, JK, or SR operation. The clock and clear control signals on the flipflop can be driven by global signals, general-purpose I/O pins, or any internal logic. For combinatorial functions, the flipflop is bypassed and the output of the LUT drives the outputs of the LE. The LE output can drive both the local interconnect and the FastTrack Interconnect. The FLEX 6000 architecture provides two types of dedicated high-speed data paths that connect adjacent LEs without using local interconnect paths: carry chains and cascade chains. A carry chain supports high-speed arithmetic functions such as counters and adders, while a cascade chain implements wide-input functions such as equivalent comparators with minimum delay. Carry and cascade chains connect LEs 2 through 10 in an LAB and all LABs in the same half of the row. Because extensive use of carry and cascade chains can reduce routing flexibility, these chains should be limited to speed-critical portions of a design. Altera Corporation 9

FLEX 6000 Programmable Logic Device Family Data Sheet Carry Chain The carry chain provides a very fast (0.1 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit drives forward into the higher-order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature allows the FLEX 6000 architecture to implement high-speed counters, adders, and comparators of arbitrary width. Carry chain logic can be created automatically by the Altera software during design processing, or manually by the designer during design entry. Parameterized functions such as LPM and DesignWare functions automatically take advantage of carry chains for the appropriate functions. Because the first LE of each LAB can generate control signals for that LAB, the first LE in each LAB is not included in carry chains. In addition, the inputs of the first LE in each LAB may be used to generate synchronous clear and load enable signals for counters implemented with carry chains. Carry chains longer than nine LEs are implemented automatically by linking LABs together. For enhanced fitting, a long carry chain skips alternate LABs in a row. A carry chain longer than one LAB skips either from an even-numbered LAB to another even-numbered LAB, or from an odd-numbered LAB to another odd-numbered LAB. For example, the last LE of the first LAB in a row carries to the second LE of the third LAB in the row. In addition, the carry chain does not cross the middle of the row. For instance, in the EPF6016 device, the carry chain stops at the 11th LAB in a row and a new carry chain begins at the 12th LAB. Figure5 shows how an n-bit full adder can be implemented in n + 1 LEs with the carry chain. One portion of the LUT generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the LE. Although the register can be bypassed for simple adders, it can be used for an accumulator function. Another portion of the LUT and the carry chain logic generates the carry-out signal, which is routed directly to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is driven onto the FastTrack Interconnect. 10 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Figure 5. Carry Chain Operation Carry-In a1 LUT Register s1 b1 Carry Chain LE 2 a2 LUT Register s2 b2 Carry Chain LE 3 an LUT Register sn bn Carry Chain LEn + 1 LUT Register Carry-Out Carry Chain LEn + 2 Altera Corporation 11

FLEX 6000 Programmable Logic Device Family Data Sheet Cascade Chain The cascade chain enables the FLEX 6000 architecture to implement very wide fan-in functions. Adjacent LUTs can be used to implement portions of the function in parallel; the cascade chain serially connects the intermediate values. The cascade chain can use a logical AND or logical ORgate (via De Morgan’s inversion) to connect the outputs of adjacent LEs. Each additional LE provides four more inputs to the effective width of a function, with a delay as low as 0.5 ns per LE. Cascade chain logic can be created automatically by the Altera software during design processing, or manually by the designer during design entry. Parameterized functions such as LPM and DesignWare functions automatically take advantage of cascade chains for the appropriate functions. A cascade chain implementing an AND gate can use the register in the last LE; a cascade chain implementing an OR gate cannot use this register because of the inversion required to implement the OR gate. Because the first LE of an LAB can generate control signals for that LAB, the first LE in each LAB is not included in cascade chains. Moreover, cascade chains longer than nine bits are automatically implemented by linking several LABs together. For easier routing, a long cascade chain skips every other LAB in a row. A cascade chain longer than one LAB skips either from an even-numbered LAB to another even-numbered LAB, or from an odd-numbered LAB to another odd-numbered LAB. For example, the last LE of the first LAB in a row cascades to the second LE of the third LAB. The cascade chain does not cross the center of the row. For example, in an EPF6016 device, the cascade chain stops at the 11th LAB in a row and a new cascade chain begins at the 12th LAB. Figure6 shows how the cascade function can connect adjacent LEs to form functions with a wide fan-in. In this example, functions of 4n variables are implemented with n LEs. The cascade chain requires 3.4ns to decode a 16-bit address. 12 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Figure 6. Cascade Chain Operation AND Cascade Chain OR Cascade Chain LE 2 LE 2 d[3..0] LUT d[3..0] LUT LE 3 LE 3 d[7..4] LUT d[7..4] LUT LEn + 1 LEn + 1 d[(4n-1)..4(n-1)] LUT d[(4n-1)..4(n-1)] LUT LE Operating Modes The FLEX 6000 LE can operate in one of the following three modes: ■ Normal mode ■ Arithmetic mode ■ Counter mode Each of these modes uses LE resources differently. In each mode, seven available inputs to the LE—the four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous LE—are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, synchronous clear, and synchronous load control for the register. The Altera software, in conjunction with parameterized functions such as LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers. If required, the designer can also create special-purpose functions to use an LE operating mode for optimal performance. Figure7 shows the LE operating modes. Altera Corporation 13

FLEX 6000 Programmable Logic Device Family Data Sheet Figure 7. LE Operating Modes Normal Mode Carry-In Cascade-In LE-Out data1 data2 PRN 4-Input D Q data3 LUT data4 CLRN Cascade-Out Arithmetic Mode Carry-In Cascade-In LE-Out PRN ddaattaa12 3-Input D Q LUT CLRN 3-Input LUT Cascade-Out Carry-Out Counter Mode LAB-Wide Synchronous LAB-Wide Synchronous Carry-In Cascade-In Load (3) Clear (3) (1) ddaattaa21 ((22)) 3-Input DPRNQ LE-Out LUT data3 (data) CLRN 3-Input LUT Carry-Out Cascade-Out Notes: (1) The register feedback multiplexer is available on LE 2 of each LAB. (2) The data1 and data2 input signals can supply a clock enable, up or down control, or register feedback signals for all LEs other than the second LE in an LAB. (3) The LAB-wide synchronous clear and LAB-wide synchronous load affect all registers in an LAB. 14 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Normal Mode The normal mode is suitable for general logic applications, combinatorial functions, or wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in are inputs to a 4-input LUT. The Altera software automatically selects the carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT output can be combined with the cascade- in signal to form a cascade chain through the cascade-out signal. Arithmetic Mode The arithmetic mode is ideal for implementing adders, accumulators, and comparators. An LE in arithmetic mode uses two 3-input LUTs. One LUT computes a 3-input function; the other generates a carry output. As shown in Figure7, the first LUT uses the carry-in signal and two data inputs from the LAB local interconnect to generate a combinatorial or registered output. For example, when implementing an adder, this output is the sum of three signals: DATA1, DATA2, and carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports simultaneous use of the cascade chain. The Altera software implements logic functions to use the arithmetic mode automatically where appropriate; the designer does not have to decide how the carry chain will be used. Counter Mode The counter mode offers counter enable, synchronous up/down control, synchronous clear, and synchronous load options. The counter enable and synchronous up/down control signals are generated from the data inputs of the LAB local interconnect. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. Consequently, if any of the LEs in a LAB use counter mode, other LEs in that LAB must be used as part of the same counter or be used for a combinatorial function. In addition, the Altera software automatically places registers that are not in the counter into other LABs. The counter mode uses two 3-input LUTs: one generates the counter data and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading, and another AND gate provides synchronous clearing. If the cascade function is used by an LE in counter mode, the synchronous clear or load will override any signal carried on the cascade chain. The synchronous clear overrides the synchronous load. Altera Corporation 15

FLEX 6000 Programmable Logic Device Family Data Sheet Either the counter enable or the up/down control may be used for a given counter. Moreover, the synchronous load can be used as a count enable by routing the register output into the data input automatically when requested by the designer. The second LE of each LAB has a special function for counter mode; the carry-in of the LE can be driven by a fast feedback path from the register. This function gives a faster counter speed for counter carry chains starting in the second LE of an LAB. The Altera software implements functions to use the counter mode automatically where appropriate. The designer does not have to decide how the carry chain will be used. Internal Tri-State Emulation Internal tri-state emulation provides internal tri-states without the limitations of a physical tri-state bus. In a physical tri-state bus, the tri-state buffers’ output enable (OE) signals select which signal drives the bus. However, if multiple OE signals are active, contending signals can be driven onto the bus. Conversely, if no OE signals are active, the bus will float. Internal tri-state emulation resolves contending tri-state buffers to a low value and floating buses to a high value, thereby eliminating these problems. The Altera software automatically implements tri-state bus functionality with a multiplexer. Clear & Preset Logic Control Logic for the programmable register’s clear and preset functions is controlled by the LAB-wide signals LABCTRL1 and LABCTRL2. The LE register has an asynchronous clear that can implement an asynchronous preset. Either LABCTRL1 or LABCTRL2 can control the asynchronous clear or preset. Because the clear and preset functions are active-low, the Altera software automatically assigns a logic high to an unused clear or preset signal. The clear and preset logic is implemented in either the asynchronous clear or asynchronous preset mode, which is chosen during design entry (see Figure8). 16 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Figure 8. LE Clear & Preset Modes Asynchronous Clear Asynchronous Preset labctrl1 or labctrl2 D Q Chip-Wide Reset PRN CLRN D Q labctrl1 or labctrl2 Chip-Wide Reset Asynchronous Clear The flipflop can be cleared by either LABCTRL1 or LABCTRL2. Asynchronous Preset An asynchronous preset is implemented with an asynchronous clear. The Altera software provides preset control by using the clear and inverting the input and output of the register. Inversion control is available for the inputs to both LEs and IOEs. Therefore, this technique can be used when a register drives logic or drives a pin. In addition to the two clear and preset modes, FLEX 6000 devices provide a chip-wide reset pin (DEV_CLRn) that can reset all registers in the device. The option to use this pin is set in the Altera software before compilation. The chip-wide reset overrides all other control signals. Any register with an asynchronous preset will be preset when the chip-wide reset is asserted because of the inversion technique used to implement the asynchronous preset. The Altera software can use a programmable NOT-gate push-back technique to emulate simultaneous preset and clear or asynchronous load. However, this technique uses an additional three LEs per register. FastTrack Interconnect In the FLEX 6000 OptiFLEX architecture, connections between LEs and device I/Opins are provided by the FastTrack Interconnect, a series of continuous horizontal and vertical routing channels that traverse the device. This global routing structure provides predictable performance, even for complex designs. In contrast, the segmented routing in FPGAs requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. Altera Corporation 17

FLEX 6000 Programmable Logic Device Family Data Sheet The FastTrack Interconnect consists of column and row interconnect channels that span the entire device. Each row of LABs is served by a dedicated row interconnect, which routes signals between LABs in the same row, and also routes signals from I/O pins to LABs. Additionally, the local interconnect routes signals between LEs in the same LAB and in adjacent LABs. The column interconnect routes signals between rows and routes signals from I/Opins to rows. LEs 1 through 5 of an LAB drive the local interconnect to the right, while LEs 6 through 10 drive the local interconnect to the left. The DATA1 and DATA3 inputs of each LE are driven by the local interconnect to the left; DATA2 and DATA4 are driven by the local interconnect to the right. The local interconnect also routes signals from LEs to I/O pins. Figure9 shows an overview of the FLEX 6000 interconnect architecture. LEs in the first and last columns have drivers on both sides so that all LEs in the LAB can drive I/O pins via the local interconnect. Figure 9. FastTrack Interconnect Architecture Row Interconnect (n Channels) (1) 2 2 5 22 5 10 5 22 5 10 2 2 20 20 5 5 5 5 5 5 5 5 10 10 5 10 LE 1 5 10 LE 1 5 10 through through To/From 10 10 LE 5 10 10 LE 5 10 To/From Adjacent 5 Adjacent LAB 10 5 LE 6 10 5 LE 6 10 10 LAB through through 10 LE 10 10 LE 10 Local Interconnect (32 Channels) Column Interconnect (m Channels) (1) Note: (1) For EPF6010A, EPF6016, and EPF6016A devices, n = 144 channels and m = 20 channels; for EPF6024A devices, n=186 channels and m = 30 channels. 18 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet A row channel can be driven by an LE or by one of two column channels. These three signals feed a 3-to-1 multiplexer that connects to six specific row channels. Row channels drive into the local interconnect via multiplexers. Each column of LABs is served by a dedicated column interconnect. The LEs in an LAB can drive the column interconnect. The LEs in an LAB, a column IOE, or a row interconnect can drive the column interconnect. The column interconnect can then drive another row’s interconnect to route the signals to other LABs in the device. A signal from the column interconnect must be routed to the row interconnect before it can enter an LAB. Each LE has a FastTrack Interconnect output and a local output. The FastTrack interconnect output can drive six row and two column lines directly; the local output drives the local interconnect. Each local interconnect channel driven by an LE can drive four row and two column channels. This feature provides additional flexibility, because each LE can drive any of ten row lines and four column lines. In addition, LEs can drive global control signals. This feature is useful for distributing internally generated clock, asynchronous clear, and asynchronous preset signals. A pin-driven global signal can also drive data signals, which is useful for high-fan-out data signals. Each LAB drives two groups of local interconnects, which allows an LE to drive two LABs, or 20 LEs, via the local interconnect. The row-to-local multiplexers are used more efficiently, because the multiplexers can now drive two LABs. Figure10 shows how an LAB connects to row and column interconnects. Altera Corporation 19

FLEX 6000 Programmable Logic Device Family Data Sheet Figure 10. LAB Connections to Row & Column Interconnects Each LE FastTrack Interconnect output can drive six row channels. Each local channel driven by an LE can Each LE output signal driving drive two column the FastTrack Interconnect can channels. drive two column channels. At each intersection, four row channels can Row drive column channels. Interconnect Each local channel driven by an LE can drive four row channels. Row interconnect drives the local LE interconnect. From Adjacent LE Local Interconnect Local Interconnect Column Interconnect Any column channel can drive six row channels. An LE can be driven by any signal from two local interconnect areas. For improved routability, the row interconnect consists of full-length and half-length channels. The full-length channels connect to all LABs in a row; the half-length channels connect to the LABs in half of the row. In addition to providing a predictable, row-wide interconnect, this architecture provides increased routing resources. Two neighboring LABs can be connected using a half-length channel, which saves the other half of the channel for the other half of the row. One-third of the row channels are half-length channels. 20 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Table5 summarizes the FastTrack Interconnect resources available in each FLEX 6000 device. Table 5.FLEX 6000 FastTrack Interconnect Resources Device Rows Channels per Columns Channels per Row Column EPF6010A 4 144 22 20 EPF6016 6 144 22 20 EPF6016A EPF6024A 7 186 28 30 In addition to general-purpose I/O pins, FLEX 6000 devices have four dedicated input pins that provide low-skew signal distribution across the device. These four inputs can be used for global clock and asynchronous clear control signals. These signals are available as control signals for all LEs in the device. The dedicated inputs can also be used as general- purpose data inputs because they can feed the local interconnect of each LAB in the device. Using dedicated inputs to route data signals provides a fast path for high fan-out signals. The local interconnect from LABs located at either end of two rows can drive a global control signal. For instance, in an EPF6016 device, LABs C1, D1, C22, and D22 can all drive global control signals. When an LE drives a global control signal, the dedicated input pin that drives that signal cannot be used. Any LE in the device can drive a global control signal by driving the FastTrack Interconnect into the appropriate LAB. To minimize delay, however, the Altera software places the driving LE in the appropriate LAB. The LE-driving-global signal feature is optimized for speed for control signals; regular data signals are better routed on the FastTrack Interconnect and do not receive any advantage from being routed on global signals. This LE-driving-global control signal feature is controlled by the designer and is not used automatically by the Altera software. See Figure11. Altera Corporation 21

FLEX 6000 Programmable Logic Device Family Data Sheet Figure 11. Global Clock & Clear Distribution Note (1) (2) 4 (3) (4) LAB LAB C1 (Repeated LAB C22 Across Device) Dedicated Dedicated Inputs Inputs (2) (4) LAB D1 LAB D22 Notes: (1) The global clock and clear distribution signals are shown for EPF6016 and EPF6016A devices. In EPF6010A devices, LABs in rows B and C drive global signals. In EPF6024A devices, LABs in rows C and E drive global signals. (2) The local interconnect from LABs C1 and D1 can drive two global control signals on the left side. (3) Global signals drive into every LAB as clock, asynchronous clear, preset, and data signals. (4) The local interconnect from LABs C22 and D22 can drive two global control signals on the right side. 22 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet I/O Elements An IOE contains a bidirectional I/O buffer and a tri-state buffer. IOEs can be used as input, output, or bidirectional pins. An IOE receives its data signals from the adjacent local interconnect, which can be driven by a row or column interconnect (allowing any LE in the device to drive the IOE) or by an adjacent LE (allowing fast clock-to-output delays). A FastFLEXTM I/O pin is a row or column output pin that receives its data signals from the adjacent local interconnect driven by an adjacent LE. The IOE receives its output enable signal through the same path, allowing individual output enables for every pin and permitting emulation of open-drain buffers. The Altera Compiler uses programmable inversion to invert the data or output enable signals automatically where appropriate. Open- drain emulation is provided by driving the data input low and toggling the OE of each IOE. This emulation is possible because there is one OE per pin. A chip-wide output enable feature allows the designer to disable all pins of the device by asserting one pin (DEV_OE). This feature is useful during board debugging or testing. Figure12 shows the IOE block diagram. Figure 12. IOE Block Diagram To Row or Column Interconnect Delay Chip-Wide Output Enable From LAB Local Interconnect From LAB Local Interconnect Slew-Rate Control Altera Corporation 23

FLEX 6000 Programmable Logic Device Family Data Sheet Each IOE drives a row or column interconnect when used as an input or bidirectional pin. A row IOE can drive up to six row lines; a column IOE can drive up to two column lines. The input path from the I/O pad to the FastTrack Interconnect has a programmable delay element that can be used to guarantee a zero hold time. Depending on the placement of the IOE relative to what it is driving, the designer may choose to turn on the programmable delay to ensure a zero hold time. Figure13 shows how an IOE connects to a row interconnect, and Figure14 shows how an IOE connects to a column interconnect. Figure 13. IOE Connection to Row Interconnect Row Interconnect Any LE can drive a pin through the Up to 10 IOEs are on either row and local IOE side of a row. Each IOE can interconnect. drive up to six row LAB channels, and each IOE data and OE signal is driven by IOE the local interconnect. FastFLEX I/O: An LE can drive a pin through the local interconnect for faster clock-to-output times. 24 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Figure 14. IOE Connection to Column Interconnect Each IOE can drive two column interconnect channels. Each IOE data and OE signal is driven to a local interconnect. IOE IOE FastFLEX I/O: An LE can drive a pin through a local interconnect for faster clock-to-output times. LAB Any LE can drive a pin through the row Column Interconnect and local interconnect. Row Interconnect SameFrame 3.3-V FLEX 6000 devices support the SameFrame pin-out feature for FineLine BGA packages. The SameFrame pin-out feature is the Pin-Outs arrangement of balls on FineLine BGA packages such that the lower-ball- count packages form a subset of the higher-ball-count packages. SameFrame pin-outs provide the flexibility to migrate not only from device to device within the same package, but also from one package to another. A given printed circuit board (PCB) layout can support multiple device density/package combinations. For example, a single board layout can support an EPF6016A device in a 100-pin FineLine BGA package or an EPF6024A device in a 256-pin FineLine BGA package. The Altera software packages provide support to design PCBs with SameFrame pin-out devices. Devices can be defined for present and future use. The Altera software packages generate pin-outs describing how to lay out a board to take advantage of this migration (seeFigure15). Altera Corporation 25

FLEX 6000 Programmable Logic Device Family Data Sheet Figure 15. SameFrame Pin-Out Example Printed Circuit Board Designed for 256-Pin FineLine BGA Package 100-Pin 256-Pin FineLine FineLine BGA BGA 100-Pin FineLine BGA Package 256-Pin FineLine BGA Package (Reduced I/O Count or (Increased I/O Count or Logic Requirements) Logic Requirements) Table6 lists the 3.3-V FLEX 6000 devices with the SameFrame pin-out feature. Table 6.3.3-V FLEX 6000 Devices with SameFrame Pin-Outs Device 100-Pin FineLine BGA 256-Pin FineLine BGA EPF6016A v v EPF6024A v Output This section discusses slew-rate control, the MultiVolt I/O interface, power sequencing, and hot-socketing for FLEX 6000 devices. Configuration Slew-Rate Control The output buffer in each IOE has an adjustable output slew-rate that can be configured for low-noise or high-speed performance. A slower slew-rate reduces system noise and adds a maximum delay of 6.8ns. The fast slew-rate should be used for speed-critical outputs in systems that are adequately protected against noise. Designers can specify the slew-rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a device-wide basis. The slew-rate setting affects only the falling edge of the output. 26 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet MultiVolt I/O Interface The FLEX 6000 device architecture supports the MultiVolt I/O interface feature, which allows FLEX 6000 devices to interface with systems of differing supply voltages. The EPF6016 device can be set for 3.3-V or 5.0-V I/O pin operation. This device has one set of V pins for internal CC operation and input buffers (VCCINT), and another set for output drivers (VCCIO). The VCCINT pins on 5.0-V FLEX6000 devices must always be connected to a 5.0-V power supply. With a 5.0-V V level, input voltages are at CCINT TTL levels and are therefore compatible with 3.3-V and 5.0-V inputs. The VCCIO pins on 5.0-V FLEX6000 devices can be connected to either a 3.3-V or 5.0-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 5.0-V power supply, the output levels are compatible with 5.0-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with V levels lower than 4.75 V incur a nominally greater timing delay of CCIO t instead of t . OD2 OD1 On 3.3-V FLEX 6000 devices, the VCCINT pins must be connected to a 3.3-V power supply. Additionally, 3.3-V FLEX 6000A devices can interface with 2.5-V, 3.3-V, or 5.0-V systems when the VCCIO pins are tied to 2.5 V. The output can drive 2.5-V systems, and the inputs can be driven by 2.5- V, 3.3-V, or 5.0-V systems. When the VCCIO pins are tied to 3.3 V, the output can drive 3.3-V or 5.0-V systems. MultiVolt I/Os are not supported on 100-pin TQFP or 100-pin FineLine BGA packages. Table7 describes FLEX 6000 MultiVolt I/O support. Table 7.FLEX 6000 MultiVolt I/O Support V V Input Signal (V) Output Signal (V) CCINT CCIO (V) (V) 2.5 3.3 5.0 2.5 3.3 5.0 3.3 2.5 v v v v 3.3 3.3 v v v v (1) v v 5.0 3.3 v v v v 5.0 5.0 v v v Note: (1) When VCCIO = 3.3 V, a FLEX 6000 device can drive a 2.5-V device that has 3.3-V tolerant inputs. Altera Corporation 27

FLEX 6000 Programmable Logic Device Family Data Sheet Open-drain output pins on 5.0-V or 3.3-V FLEX 6000 devices (with a pull- up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a V of 3.5 V. When the open-drain pin is active, it will drive low. IH When the pin is inactive, the trace will be pulled up to 5.0 V by the resistor. The open-drain pin will only drive low or tri-state; it will never drive high. The rise time is dependent on the value of the pull-up resistor and load impedance. The I current specification should be considered when OL selecting a pull-up resistor. Output pins on 5.0-V FLEX 6000 devices with V = 3.3 V or 5.0 V (with CCIO a pull-up resistor to the 5.0-V supply) can also drive 5.0-V CMOS input pins. In this case, the pull-up transistor will turn off when the pin voltage exceeds 3.3 V. Therefore, the pin does not have to be open-drain. Power Sequencing & Hot-Socketing Because FLEX 6000 family devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. The V and V power planes can be powered CCIO CCINT in any order. Signals can be driven into 3.3-V FLEX 6000 devices before and during power up without damaging the device. Additionally, FLEX 6000 devices do not drive out during power up. Once operating conditions are reached, FLEX6000 devices operate as specified by the user. IEEE Std. All FLEX 6000 devices provide JTAG BST circuitry that comply with the IEEE Std. 1149.1-1990 specification. Table8 shows JTAG instructions for 1149.1 (JTAG) FLEX 6000 devices. JTAG BST can be performed before or after Boundary-Scan configuration, but not during configuration (except when you disable JTAG support in user mode). Support 1 See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) for more information on JTAG BST circuitry. Table 8.FLEX 6000 JTAG Instructions JTAG Instruction Description SAMPLE/PRELOAD Allows a snapshot of the signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test result at the input pins. BYPASS Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through the selected device to adjacent devices during normal device operation. 28 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet The instruction register length for FLEX 6000 devices is three bits. Table9 shows the boundary-scan register length for FLEX 6000 devices. Table 9.FLEX 6000 Device Boundary-Scan Register Length Device Boundary-Scan Register Length EPF6010A 522 EPF6016 621 EPF6016A 522 EPF6024A 666 FLEX 6000 devices include a weak pull-up on JTAG pins. f See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) for more information. Figure16 shows the timing requirements for the JTAG signals. Figure 16. JTAG Waveforms TMS TDI tJCP tJCH tJCL tJPSU tJPH TCK tJPZX tJPCO tJPXZ TDO t t JSSU JSH Signal to Be Captured tJSZX tJSCO tJSXZ Signal to Be Driven Table10 shows the JTAG timing parameters and values for FLEX 6000 devices. Altera Corporation 29

FLEX 6000 Programmable Logic Device Family Data Sheet Table 10.JTAG Timing Parameters & Values Symbol Parameter Min Max Unit t TCK clock period 100 ns JCP t TCK clock high time 50 ns JCH t TCK clock low time 50 ns JCL t JTAG port setup time 20 ns JPSU t JTAG port hold time 45 ns JPH t JTAG port clock-to-output 25 ns JPCO t JTAG port high impedance to valid output 25 ns JPZX t JTAG port valid output to high impedance 25 ns JPXZ t Capture register setup time 20 ns JSSU t Capture register hold time 45 ns JSH t Update register clock-to-output 35 ns JSCO t Update register high impedance to valid 35 ns JSZX output t Update register valid output to high 35 ns JSXZ impedance Generic Testing Each FLEX 6000 device is functionally tested. Complete testing of each configurable SRAM bit and all logic functionality ensures 100% configuration yield. AC test measurements for FLEX 6000 devices are made under conditions equivalent to those shown in Figure17. Multiple test patterns can be used to configure devices during all stages of the production flow. Figure 17. AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs VCC should be avoided for accurate 464 Ω measurement. Threshold tests must (703 Ω) not be performed under AC conditions. [521 Ω] Large-amplitude, fast-ground-current transients normally occur as the Device To Test device outputs discharge the load Output System capacitances. When these transients flow through the parasitic inductance between the device 250 Ω ground pin and the test system ground, (8.06 kΩ) C1 (includes significant reductions in observable [481 Ω] JIG capacitance) noise immunity can result. Numbers without parentheses are for 5.0-V Device input devices or outputs. Numbers in rise and fall parentheses are for 3.3-V devices or times < 3 ns outputs. Numbers in brackets are for 2.5-V devices or outputs. 30 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Operating Tables11 through 18 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and Conditions capacitance for 5.0-V and 3.3-V FLEX 6000 devices. Table 11.FLEX 6000 5.0-V Device Absolute Maximum Ratings Note (1) Symbol Parameter Conditions Min Max Unit VCC Supply voltage With respect to ground (2) –2.0 7.0 V VI DC input voltage –2.0 7.0 V IOUT DC output current, per pin –25 25 mA TSTG Storage temperature No bias –65 150 ° C TAMB Ambient temperature Under bias –65 135 ° C TJ Junction temperature PQFP, TQFP, and BGA packages 135 ° C Table 12.FLEX 6000 5.0-V Device Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit VCCINT Supply voltage for internal logic (3), (4) 4.75 (4.50) 5.25 (5.50) V and input buffers VCCIO Supply voltage for output buffers, (3), (4) 4.75 (4.50) 5.25 (5.50) V 5.0-V operation Supply voltage for output buffers, (3), (4) 3.00 (3.00) 3.60 (3.60) V 3.3-V operation VI Input voltage –0.5 VCCINT + 0.5 V VO Output voltage 0 VCCIO V TJ Operating temperature For commercial use 0 85 ° C For industrial use –40 100 ° C tR Input rise time 40 ns tF Input fall time 40 ns Altera Corporation 31

FLEX 6000 Programmable Logic Device Family Data Sheet Table 13.FLEX 6000 5.0-V Device DC Operating Conditions Notes (5), (6) Symbol Parameter Conditions Min Typ Max Unit VIH High-level input voltage 2.0 VCCINT + 0.5 V VIL Low-level input voltage –0.5 0.8 V VOH 5.0-V high-level TTL output IOH = –8 mA DC, VCCIO = 4.75 V (7) 2.4 V voltage 3.3-V high-level TTL output IOH = –8 mA DC, VCCIO = 3.00 V (7) 2.4 V voltage 3.3-V high-level CMOS output IOH = –0.1 mA DC, VCCIO = 3.00 V (7) VCCIO–0.2 V voltage VOL 5.0-V low-level TTL output IOL = 8 mA DC, VCCIO = 4.75 V (8) 0.45 V voltage 3.3-V low-level TTL output IOL = 8 mA DC, VCCIO = 3.00 V (8) 0.45 V voltage 3.3-V low-level CMOS output IOL = 0.1 mA DC, VCCIO = 3.00 V (8) 0.2 V voltage II Input pin leakage current VI = VCC or ground (8) –10 10 µA IOZ Tri-stated I/O pin leakage current VO = VCC or ground (8) –40 40 µA ICC0 VCC supply current (standby) VI = ground, no load 0.5 5 mA Table 14.FLEX 6000 5.0-V Device Capacitance Note (9) Symbol Parameter Conditions Min Max Unit CIN Input capacitance for I/O pin VIN = 0 V, f = 1.0MHz 8 pF CINCLK Input capacitance for dedicated input VIN = 0 V, f = 1.0MHz 12 pF COUT Output capacitance VOUT = 0 V, f = 1.0MHz 8 pF Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Minimum DC input is –0.5V. During transitions, the inputs may undershoot to –2.0V or overshoot to 7.0V for input currents less than 100 mA and periods shorter than 20ns. (3) Numbers in parentheses are for industrial-temperature-range devices. (4) Maximum VCC rise time to 100 ms. VCC must rise monotonically. (5) Typical values are for TA = 25° C and VCC = 5.0V. (6) These values are specified under the FLEX 6000 Recommended Operating Conditions shown in Table12 on page31. (7) The IOH parameter refers to high-level TTL or CMOS output current. (8) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins as well as output pins. (9) Capacitance is sample-tested only. 32 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Table 15.FLEX 6000 3.3-V Device Absolute Maximum Ratings Note (1) Symbol Parameter Conditions Min Max Unit VCC Supply voltage With respect to ground (2) –0.5 4.6 V VI DC input voltage –2.0 5.75 V IOUT DC output current, per pin –25 25 mA TSTG Storage temperature No bias –65 150 ° C TAMB Ambient temperature Under bias –65 135 ° C TJ Junction temperature PQFP, PLCC, and BGA packages 135 ° C Table 16.FLEX 6000 3.3-V Device Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit VCCINT Supply voltage for internal logic and (3), (4) 3.00 (3.00) 3.60 (3.60) V input buffers VCCIO Supply voltage for output buffers, (3), (4) 3.00 (3.00) 3.60 (3.60) V 3.3-V operation Supply voltage for output buffers, (3), (4) 2.30 (2.30) 2.70 (2.70) V 2.5-V operation VI Input voltage –0.5 5.75 V VO Output voltage 0 VCCIO V TJ Operating temperature For commercial use 0 85 ° C For industrial use –40 100 ° C tR Input rise time 40 ns tF Input fall time 40 ns Altera Corporation 33

FLEX 6000 Programmable Logic Device Family Data Sheet Table 17.FLEX 6000 3.3-V Device DC Operating Conditions Notes (5), (6) Symbol Parameter Conditions Min Typ Max Unit VIH High-level input voltage 1.7 5.75 V VIL Low-level input voltage –0.5 0.8 V VOH 3.3-V high-level TTL output IOH = –8 mA DC, VCCIO = 3.00 V (7) 2.4 V voltage 3.3-V high-level CMOS output IOH = –0.1 mA DC, VCCIO = 3.00 V (7) VCCIO–0.2 V voltage 2.5-V high-level output voltage IOH = –100 µA DC, VCCIO = 2.30 V (7) 2.1 V IOH = –1 mA DC, VCCIO = 2.30 V (7) 2.0 V IOH = –2 mA DC, VCCIO = 2.30 V (7) 1.7 V VOL 3.3-V low-level TTL output IOL = 8 mA DC, VCCIO = 3.00 V (8) 0.45 V voltage 3.3-V low-level CMOS output IOL = 0.1 mA DC, VCCIO = 3.00 V (8) 0.2 V voltage 2.5-V low-level output voltage IOL = 100 µA DC, VCCIO = 2.30 V (8) 0.2 V IOL = 1 mA DC, VCCIO = 2.30 V (8) 0.4 V IOL = 2 mA DC, VCCIO = 2.30 V (8) 0.7 V II Input pin leakage current VI = 5.3 V to ground (8) –10 10 µA IOZ Tri-stated I/O pin leakage current VO = 5.3 V to ground (8) –10 10 µA ICC0 VCC supply current (standby) VI = ground, no load 0.5 5 mA Table 18.FLEX 6000 3.3-V Device Capacitance Note (9) Symbol Parameter Conditions Min Max Unit CIN Input capacitance for I/O pin VIN = 0 V, f = 1.0MHz 8 pF CINCLK Input capacitance for dedicated input VIN = 0 V, f = 1.0MHz 12 pF COUT Output capacitance VOUT = 0 V, f = 1.0MHz 8 pF Notes to tables: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) The minimum DC input voltage is –0.5V. During transitions, the inputs may undershoot to –2.0V or overshoot to 5.75V for input currents less than 100 mA and periods shorter than 20ns. (3) Numbers in parentheses are for industrial-temperature-range devices. (4) Maximum VCC rise time is 100 ms. VCC must rise monotonically. (5) Typical values are for TA = 25° C and VCC = 3.3V. (6) These values are specified under Table16 on page33. (7) The IOH parameter refers to high-level TTL or CMOS output current. (8) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins as well as output pins. (9) Capacitance is sample-tested only. 34 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Figure18 shows the typical output drive characteristics of 5.0-V and 3.3-V FLEX6000 devices with 5.0-V, 3.3-V, and 2.5-V V . When CCIO V =5.0V on EPF6016 devices, the output driver is compliant with the CCIO PCI Local Bus Specification, Revision2.2 for 5.0-V operation. When V = 3.3 V on the EPF6010A and EPF6016A devices, the output driver CCIO is compliant with the PCI Local Bus Specification, Revision2.2 for 3.3-V operation. Figure 18. Output Drive Characteristics EPF6010A EPF6010A EPF6016A EPF6016A VCCINT = 3.3 V VCCINT = 3.3 V 100 VCCIO = 3.3 V 100 VCCIO = 2.5 V Room Temperature Room Temperature TOyuptipcuatl IO 75 IOL TOyuptipcuatl IO 75 IOL Current (mA) Current (mA) 50 50 IOH IOH 25 25 1 2 3 4 5 1 2 3 4 5 VO Output Voltage (V) VO Output Voltage (V) EPF6016 EPF6016 150 150 IOL IOL 120 120 VCCINT = 5.0 V TOyuptipcuatl IO 90 VCCINT = 5.0 V TOyuptipcuatl IO 90 VRCoCoImO =T e3m.3p Verature Current (mA) VCCIO = 5.0 V Current (mA) 60 Room Temperature 60 IOH 30 IOH 30 1 2 3 4 5 1 2 33.3 4 5 VO Output Voltage (V) VO Output Voltage (V) EPF6024A EPF6024A 100 VCCINT = 3.3 V 100 VCCINT = 3.3 V VCCIO = 3.3 V VCCIO = 2.5 V Room Temperature Room Temperature Typical IO 75 Typical IO 75 Output Output Current (mA) IOL Current (mA) IOL 50 50 25 25 IOH IOH 1 2 3 4 5 1 2 3 4 5 VO Output Voltage (V) VO Output Voltage (V) Altera Corporation 35

FLEX 6000 Programmable Logic Device Family Data Sheet Timing Model The continuous, high-performance FastTrack Interconnect routing resources ensure predictable performance and accurate simulation and timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and therefore have unpredictable performance. Device performance can be estimated by following the signal path from a source, through the interconnect, to the destination. For example, the registered performance between two LEs on the same row can be calculated by adding the following parameters: ■ LE register clock-to-output delay (t t ) CO+ REG_TO_OUT ■ Routing delay (t t ) ROW+ LOCAL ■ LE LUT delay (t ) DATA_TO_REG ■ LE register setup time (t ) SU The routing delay depends on the placement of the source and destination LEs. A more complex registered path may involve multiple combinatorial LEs between the source and destination LEs. Timing simulation and delay prediction are available with the Simulator and Timing Analyzer, or with industry-standard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer provides point-to-point timing delay information, setup and hold time analysis, and device-wide performance analysis. Figure19 shows the overall timing model, which maps the possible routing paths to and from the various elements of the FLEX6000 device. 36 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Figure 19. FLEX 6000 Timing Model t ROW Carry-In from Cascade-In from Previous LE Previous LE t CASC_TO_OUT t CARRY_TO_OUT t DATA_TO_OUT tLOCAL ttttRCCDEAAATGSRACR__T_YTOT_OOT__OR_RRE_EREGGGEG ttttSHCCUOLR tREG_TO_OUT t COL t C t LD_CLR t LEGLOBAL tCARRY_TO_CARRY tCARRY_TO_CASC tREG_TO_CARRY tCASC_TO_CASC tDATA_TO_CARRY tREG_TO_CASC t DATA_TO_CASC LE tDIN_D tLABCARRY tLABCASC t DIN_C Carry-out to Carry-out to Cascade-out Cascade-out Next LE in Next LE in to Next LE in to Next LE in Same LAB Next LAB Same LAB Next LAB t I/O Pin OD1 t OD2 t OD3 t XZ tIOE tZX1 t ZX2 t ZX3 t IN t IN_DELAY IOE Altera Corporation 37

FLEX 6000 Programmable Logic Device Family Data Sheet Tables19 through 21 describe the FLEX6000 internal timing microparameters, which are expressed as worst-case values. Using hand calculations, these parameters can be used to estimate design performance. However, before committing designs to silicon, actual worst-case performance should be modeled using timing simulation and timing analysis. Tables22 and 23 describe FLEX6000 external timing parameters. Table 19.LE Timing Microparameters Note (1) Symbol Parameter Conditions t LUT delay for LE register feedback in carry chain REG_TO_REG t Cascade-in to register delay CASC_TO_REG t Carry-in to register delay CARRY_TO_REG t LE input to register delay DATA_TO_REG t Cascade-in to LE output delay CASC_TO_OUT t Carry-in to LE output delay CARRY_TO_OUT t LE input to LE output delay DATA_TO_OUT t Register output to LE output delay REG_TO_OUT t LE register setup time before clock; LE register recovery time after SU asynchronous clear t LE register hold time after clock H t LE register clock-to-output delay CO t LE register clear delay CLR t LE register control signal delay C t Synchronous load or clear delay in counter mode LD_CLR t Carry-in to carry-out delay CARRY_TO_CARRY t Register output to carry-out delay REG_TO_CARRY t LE input to carry-out delay DATA_TO_CARRY t Carry-in to cascade-out delay CARRY_TO_CASC t Cascade-in to cascade-out delay CASC_TO_CASC t Register-out to cascade-out delay REG_TO_CASC t LE input to cascade-out delay DATA_TO_CASC t LE register clock high time CH t LE register clock low time CL 38 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Table 20.IOE Timing Microparameters Note (1) Symbol Parameter Conditions t Output buffer and pad delay, slow slew rate = off, V = V C1=35 pF (2) OD1 CCIO CCINT t Output buffer and pad delay, slow slew rate = off, V = low voltage C1=35 pF (3) OD2 CCIO t Output buffer and pad delay, slow slew rate = on C1=35 pF (4) OD3 t Output buffer disable delay C1=5 pF XZ t Output buffer enable delay, slow slew rate = off, V = V C1=35 pF (2) ZX1 CCIO CCINT t Output buffer enable delay, slow slew rate = off, V = low voltage C1=35 pF (3) ZX2 CCIO t IOE output buffer enable delay, slow slew rate = on C1=35 pF (4) ZX3 t Output enable control delay IOE t Input pad and buffer to FastTrack Interconnect delay IN t Input pad and buffer to FastTrack Interconnect delay with additional delay IN_DELAY turned on Table 21.Interconnect Timing Microparameters Note (1) Symbol Parameter Conditions t LAB local interconnect delay LOCAL t Row interconnect routing delay (5) ROW t Column interconnect routing delay (5) COL t Dedicated input to LE data delay (5) DIN_D t Dedicated input to LE control delay DIN_C t LE output to LE control via internally-generated global signal delay (5) LEGLOBAL t Routing delay for the carry-out of an LE driving the carry-in signal of a LABCARRY different LE in a different LAB t Routing delay for the cascade-out signal of an LE driving the cascade-in LABCASC signal of a different LE in a different LAB Table 22.External Reference Timing Parameters Symbol Parameter Conditions t Register-to-register test pattern (6) 1 t Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local (7) DRR interconnects Altera Corporation 39

FLEX 6000 Programmable Logic Device Family Data Sheet Table 23.External Timing Parameters Symbol Parameter Conditions t Setup time with global clock at LE register (8) INSU t Hold time with global clock at LE register (8) INH t Clock-to-output delay with global clock with LE register using FastFLEX I/O (8) OUTCO pin Notes to tables: (1) Microparameters are timing delays contributed by individual architectural elements and cannot be measured explicitly. (2) Operating conditions: VCCIO = 5.0V ± 5% for commercial use in 5.0-V FLEX 6000 devices. VCCIO = 5.0V ± 10% for industrial use in 5.0-V FLEX 6000 devices. VCCIO = 3.3V ± 10% for commercial or industrial use in 3.3-V FLEX 6000 devices. (3) Operating conditions: VCCIO = 3.3V ± 10% for commercial or industrial use in 5.0-V FLEX 6000 devices. VCCIO = 2.5V ± 0.2 V for commercial or industrial use in 3.3-V FLEX 6000 devices. (4) Operating conditions: VCCIO = 2.5 V, 3.3V, or 5.0V. (5) These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing analysis are required to determine actual worst-case performance. (6) This timing parameter shows the delay of a register-to-register test pattern and is used to determine speed grades. There are 12 LEs, including source and destination registers. The row and column interconnects between the registers vary in length. (7) This timing parameter is shown for reference and is specified by characterization. (8) This timing parameter is specified by characterization. Tables24 through 28 show the timing information for EPF6010A and EPF6016A devices. Table 24.LE Timing Microparameters for EPF6010A & EPF6016A Devices (Part 1 of 2) Parameter Speed Grade Unit -1 -2 -3 Min Max Min Max Min Max t 1.2 1.3 1.7 ns REG_TO_REG t 0.9 1.0 1.2 ns CASC_TO_REG t 0.9 1.0 1.2 ns CARRY_TO_REG t 1.1 1.2 1.5 ns DATA_TO_REG t 1.3 1.4 1.8 ns CASC_TO_OUT t 1.6 1.8 2.3 ns CARRY_TO_OUT t 1.7 2.0 2.5 ns DATA_TO_OUT t 0.4 0.4 0.5 ns REG_TO_OUT t 0.9 1.0 1.3 ns SU t 1.4 1.7 2.1 ns H 40 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Table 24.LE Timing Microparameters for EPF6010A & EPF6016A Devices (Part 2 of 2) Parameter Speed Grade Unit -1 -2 -3 Min Max Min Max Min Max t 0.3 0.4 0.4 ns CO t 0.4 0.4 0.5 ns CLR t 1.8 2.1 2.6 ns C t 1.8 2.1 2.6 ns LD_CLR t 0.1 0.1 0.1 ns CARRY_TO_CARRY t 1.6 1.9 2.3 ns REG_TO_CARRY t 2.1 2.5 3.0 ns DATA_TO_CARRY t 1.0 1.1 1.4 ns CARRY_TO_CASC t 0.5 0.6 0.7 ns CASC_TO_CASC t 1.4 1.7 2.1 ns REG_TO_CASC t 1.1 1.2 1.5 ns DATA_TO_CASC t 2.5 3.0 3.5 ns CH t 2.5 3.0 3.5 ns CL Table 25.IOE Timing Microparameters for EPF6010A & EPF6016A Devices Parameter Speed Grade Unit -1 -2 -3 Min Max Min Max Min Max t 1.9 2.2 2.7 ns OD1 t 4.1 4.8 5.8 ns OD2 t 5.8 6.8 8.3 ns OD3 t 1.4 1.7 2.1 ns XZ t 1.4 1.7 2.1 ns XZ1 t 3.6 4.3 5.2 ns XZ2 t 5.3 6.3 7.7 ns XZ3 t 0.5 0.6 0.7 ns IOE t 3.6 4.1 5.1 ns IN t 4.8 5.4 6.7 ns IN_DELAY Altera Corporation 41

FLEX 6000 Programmable Logic Device Family Data Sheet Table 26.Interconnect Timing Microparameters for EPF6010A & EPF6016A Devices Parameter Speed Grade Unit -1 -2 -3 Min Max Min Max Min Max t 0.7 0.7 1.0 ns LOCAL t 2.9 3.2 3.2 ns ROW t 1.2 1.3 1.4 ns COL t 5.4 5.7 6.4 ns DIN_D t 4.3 5.0 6.1 ns DIN_C t 2.6 3.0 3.7 ns LEGLOBAL t 0.7 0.8 0.9 ns LABCARRY t 1.3 1.4 1.8 ns LABCASC Table 27.External Reference Timing Parameters for EPF6010A & EPF6016A Devices Parameter Device Speed Grade Unit -1 -2 -3 Min Max Min Max Min Max t EPF6010A 37.6 43.6 53.7 ns 1 EPF6016A 38.0 44.0 54.1 ns Table 28.External Timing Parameters for EPF6010A & EPF6016A Devices Parameter Speed Grade Unit -1 -2 -3 Min Max Min Max Min Max t 2.1 (1) 2.4 (1) 3.3 (1) ns INSU t 0.2 (2) 0.3 (2) 0.1 (2) ns INH t 2.0 7.1 2.0 8.2 2.0 10.1 ns OUTCO Notes: (1) Setup times are longer when the Increase Input Delay option is turned on. The setup time values are shown with the Increase Input Delay option turned off. (2) Hold time is zero when the Increase Input Delay option is turned on. 42 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Tables29 through 33 show the timing information for EPF6016 devices. Table 29.LE Timing Microparameters for EPF6016 Devices Parameter Speed Grade Unit -2 -3 Min Max Min Max t 2.2 2.8 ns REG_TO_REG t 0.9 1.2 ns CASC_TO_REG t 1.6 2.1 ns CARRY_TO_REG t 2.4 3.0 ns DATA_TO_REG t 1.3 1.7 ns CASC_TO_OUT t 2.4 3.0 ns CARRY_TO_OUT t 2.7 3.4 ns DATA_TO_OUT t 0.3 0.5 ns REG_TO_OUT t 1.1 1.6 ns SU t 1.8 2.3 ns H t 0.3 0.4 ns CO t 0.5 0.6 ns CLR t 1.2 1.5 ns C t 1.2 1.5 ns LD_CLR t 0.2 0.4 ns CARRY_TO_CARRY t 0.8 1.1 ns REG_TO_CARRY t 1.7 2.2 ns DATA_TO_CARRY t 1.7 2.2 ns CARRY_TO_CASC t 0.9 1.2 ns CASC_TO_CASC t 1.6 2.0 ns REG_TO_CASC t 1.7 2.1 ns DATA_TO_CASC t 4.0 4.0 ns CH t 4.0 4.0 ns CL Table 30.IOE Timing Microparameters for EPF6016 Devices Parameter Speed Grade Unit -2 -3 Min Max Min Max t 2.3 2.8 ns OD1 t 4.6 5.1 ns OD2 Altera Corporation 43

FLEX 6000 Programmable Logic Device Family Data Sheet Table 30.IOE Timing Microparameters for EPF6016 Devices Parameter Speed Grade Unit -2 -3 Min Max Min Max t 4.7 5.2 ns OD3 t 2.3 2.8 ns XZ t 2.3 2.8 ns ZX1 t 4.6 5.1 ns ZX2 t 4.7 5.2 ns ZX3 t 0.5 0.6 ns IOE t 3.3 4.0 ns IN t 4.6 5.6 ns IN_DELAY Table 31.Interconnect Timing Microparameters for EPF6016 Devices Parameter Speed Grade Unit -2 -3 Min Max Min Max t 0.8 1.0 ns LOCAL t 2.9 3.3 ns ROW t 2.3 2.5 ns COL t 4.9 6.0 ns DIN_D t 4.8 6.0 ns DIN_C t 3.1 3.9 ns LEGLOBAL t 0.4 0.5 ns LABCARRY t 0.8 1.0 ns LABCASC Table 32.External Reference Timing Parameters for EPF6016 Devices Parameter Speed Grade Unit -2 -3 Min Max Min Max t 53.0 65.0 ns 1 t 16.0 20.0 ns DRR 44 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Table 33.External Timing Parameters for EPF6016 Devices Parameter Speed Grade Unit -2 -3 Min Max Min Max t 3.2 4.1 ns INSU t 0.0 0.0 ns INH t 2.0 7.9 2.0 9.9 ns OUTCO Tables34 through 38 show the timing information for EPF6024A devices. Table 34.LE Timing Microparameters for EPF6024A Devices Parameter Speed Grade Unit -1 -2 -3 Min Max Min Max Min Max t 1.2 1.3 1.6 ns REG_TO_REG t 0.7 0.8 1.0 ns CASC_TO_REG t 1.6 1.8 2.2 ns CARRY_TO_REG t 1.3 1.4 1.7 ns DATA_TO_REG t 1.2 1.3 1.6 ns CASC_TO_OUT t 2.0 2.2 2.6 ns CARRY_TO_OUT t 1.8 2.1 2.6 ns DATA_TO_OUT t 0.3 0.3 0.4 ns REG_TO_OUT t 0.9 1.0 1.2 ns SU t 1.3 1.4 1.7 ns H t 0.2 0.3 0.3 ns CO t 0.3 0.3 0.4 ns CLR t 1.9 2.1 2.5 ns C t 1.9 2.1 2.5 ns LD_CLR t 0.2 0.2 0.3 ns CARRY_TO_CARRY t 1.4 1.6 1.9 ns REG_TO_CARRY t 1.3 1.4 1.7 ns DATA_TO_CARRY t 1.1 1.2 1.4 ns CARRY_TO_CASC t 0.7 0.8 1.0 ns CASC_TO_CASC t 1.4 1.6 1.9 ns REG_TO_CASC t 1.0 1.1 1.3 ns DATA_TO_CASC t 2.5 3.0 3.5 ns CH t 2.5 3.0 3.5 ns CL Altera Corporation 45

FLEX 6000 Programmable Logic Device Family Data Sheet Table 35.IOE Timing Microparameters for EPF6024A Devices Parameter Speed Grade Unit -1 -2 -3 Min Max Min Max Min Max t 1.9 2.1 2.5 ns OD1 t 4.0 4.4 5.3 ns OD2 t 7.0 7.8 9.3 ns OD3 t 4.3 4.8 5.8 ns XZ t 4.3 4.8 5.8 ns XZ1 t 6.4 7.1 8.6 ns XZ2 t 9.4 10.5 12.6 ns XZ3 t 0.5 0.6 0.7 ns IOE t 3.3 3.7 4.4 ns IN t 5.3 5.9 7.0 ns IN_DELAY Table 36.Interconnect Timing Microparameters for EPF6024A Devices Parameter Speed Grade Unit -1 -2 -3 Min Max Min Max Min Max t 0.8 0.8 1.1 ns LOCAL t 3.0 3.1 3.3 ns ROW t 3.0 3.2 3.4 ns COL t 5.4 5.6 6.2 ns DIN_D t 4.6 5.1 6.1 ns DIN_C t 3.1 3.5 4.3 ns LEGLOBAL t 0.6 0.7 0.8 ns LABCARRY t 0.3 0.3 0.4 ns LABCASC Table 37.External Reference Timing Parameters for EPF6024A Devices Parameter Speed Grade Unit -1 -2 -3 Min Max Min Max Min Max t 45.0 50.0 60.0 ns 1 46 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Table 38.External Timing Parameters for EPF6024A Devices Parameter Speed Grade Unit -1 -2 -3 Min Max Min Max Min Max t 2.0 (1) 2.2 (1) 2.6 (1) ns INSU t 0.2 (2) 0.2 (2) 0.3 (2) ns INH t 2.0 7.4 2.0 8.2 2.0 9.9 ns OUTCO Notes: (1) Setup times are longer when the Increase Input Delay option is turned on. The setup time values are shown with the Increase Input Delay option turned off. (2) Hold time is zero when the Increase Input Delay option is turned on. Power The supply power (P) for FLEX 6000 devices can be calculated with the following equations: Consumption P = P + P INT IO P = (I + I ) × V + P CCSTANDBY CCACTIVE CC IO Typical I values are shown as I in the “FLEX 6000 Device CCSTANDBY CC0 DC Operating Conditions” table on pages31 and 33 of this data sheet. The I value depends on the switching frequency and the application CCACTIVE logic. This value is based on the amount of current that each LE typically consumes. The P value, which depends on the device output load IO characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices). The I value can be calculated with the following equation: CCACTIVE I = K × f × N × tog × -----------µ----A-------------- CCACTIVE MAX LC MHz× LE Where: f = Maximum operating frequency in MHz MAX N = Total number of LEs used in a FLEX 6000 device tog = Average percentage of LEs toggling at each clock LC (typically 12.5%) K = Constant, shown in Table39 Table 39.K Constant Values Device K Value EPF6010A 14 EPF6016 88 EPF6016A 14 EPF6024A 14 Altera Corporation 47

FLEX 6000 Programmable Logic Device Family Data Sheet This calculation provides an I estimate based on typical conditions with CC no output load. The actual I should be verified during operation CC because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. To better reflect actual designs, the power model (and the constant K in the power calculation equations shown above) for continuous interconnect FLEX devices assumes that LEs drive FastTrack Interconnect channels. In contrast, the power model of segmented FPGAs assumes that all LEs drive only one short interconnect segment. This assumption may lead to inaccurate results, compared to measured power consumption for an actual design in a segmented interconnect FPGA. Figure20 shows the relationship between the current and operating frequency for EPF6010A, EPF6016, EPF6016A, and EPF6024Adevices. 48 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Figure 20. I vs. Operating Frequency CCACTIVE EPF6010A EPF6016 1000 200 800 150 ICC Supply ICC Supply 600 Current Current (mA) 100 (mA) 400 50 200 0 50 100 0 30 60 Frequency (MHz) Frequency (MHz) EPF6016A EPF6024A 250 400 200 300 ICC Supply 150 ICC Supply Current Current (mA) (mA) 200 100 100 50 0 50 100 0 50 100 Frequency (MHz) Frequency (MHz) Device The FLEX 6000 architecture supports several configuration schemes to load a design into the device(s) on the circuit board. This section Configuration & summarizes the device operating modes and available device Operation configuration schemes. f See Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000 Devices) for detailed information on configuring FLEX 6000 devices, including sample schematics, timing diagrams, configuration options, pins names, and timing parameters. Altera Corporation 49

FLEX 6000 Programmable Logic Device Family Data Sheet Operating Modes The FLEX 6000 architecture uses SRAM configuration elements that require configuration data to be loaded every time the circuit powers up. This process of physically loading the SRAM data into a FLEX 6000 device is known as configuration. During initialization—a process that occurs immediately after configuration—the device resets registers, enables I/Opins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. The configuration and initialization processes of a device are referred to as command mode; normal device operation is called user mode. SRAM configuration elements allow FLEX 6000 devices to be reconfigured in-circuit by loading new configuration data into the device. Real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different configuration data, reinitializing the device, and resuming user- mode operation. The entire reconfiguration process requires less than 100 ms and is used to dynamically reconfigure an entire system. Also, in-field system upgrades can be performed by distributing new configuration files. Configuration Schemes The configuration data for a FLEX 6000 device can be loaded with one of three configuration schemes, which is chosen on the basis of the target application. An EPC1 or EPC1441 configuration device or intelligent controller can be used to control the configuration of a FLEX6000 device, allowing automatic configuration on system power-up. Multiple FLEX 6000 devices can be configured in any of the three configuration schemes by connecting the configuration enable input (nCE) and configuration enable output (nCEO) pins on each device. Table40 shows the data sources for each configuration scheme. Table 40.Configuration Schemes Configuration Scheme Data Source Configuration device EPC1 or EPC1441 configuration device Passive serial (PS) BitBlasterTM, ByteBlasterMVTM, or MasterBlasterTM download cables, or serial data source Passive serial asynchronous BitBlaster, ByteBlasterMV, or MasterBlaster (PSA) download cables, or serial data source 50 Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet Device Pin- See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. Outs Altera Corporation 51

FLEX 6000 Programmable Logic Device Family Data Sheet Altera, BitBlaster, ByteBlasterMV, FastFlex, FastTrack, FineLine BGA, FLEX, MasterBlaster, MAX+PLUS II, MegaCore, MultiVolt, OptiFLEX, Quartus, SameFrame, and specific device designations are trademarks and/or service marks of Altera Corporation in the United States and other countries. Altera acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, specifically: Verilog is a registered trademark of and Verilog-XL is a trademarks of Cadence Design Systems, Inc. DATA I/O is a registered trademark of Data I/O Corporation. HP is a registered trademark of Hewlett- ® Packard Company. Exemplar Logic is a registered trademark of Exemplar Logic, Inc. Pentium is a registered trademark of Intel Corporation. Mentor Graphics is a registered trademark of Mentor Graphics Corporation. 101 Innovation Drive OrCAD is a registered trademark of OrCAD Systems, Corporation. SPARCstation is a registered trademark of San Jose, CA 95134 SPARC International, Inc. and is licensed exclusively to Sun Microsystems, Inc. Sun Workstation is a registered trademark of, and Sun is a registered trademark of Sun Microsystems, Inc. Synopsys is a registered trademark (408) 544-7000 and DesignTime, HDL Compiler, and DesignWare are trademarks of Synopsys, Inc. VeriBest is a registered http://www.altera.com trademark of Viewlogic Systems, Inc. Viewlogic is a registered trademark of Viewlogic Systems, Inc. Altera Applications Hotline: products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in (800) 800-EPLD accordance with Altera’s standard warranty, but reserves the right to make changes to any products and Customer Marketing: services at any time without notice. Altera assumes no responsibility or liability arising out (408) 544-7104 of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to Literature Services: obtain the latest version of device specifications before relying on any published (888) 3-ALTERA information and before placing orders for products or services. lit_req@altera.com Copyright © 2001 Altera Corporation. All rights reserved. 52 Altera Corporation Printed on Recycled Paper.