EMIF06-1005M12 6-line IPAD™ low capacitance EMI filter and ESD protection in micro QFN package Features 12 1 ■ EMI symmetrical (I/O) low-pass filter 11 2 ■ High efficiency in EMI filtering: -34 dB at 10 3 frequencies from 900 MHz to 1.8 GHz GND 9 4 ■ Very low PCB space consumption: 8 5 2.5 mm x 1.5 mm 7 6 ■ Very thin package: 0.6 mm max Micro QFN 2.5 mm x 1.5 mm ■ High efficiency in ESD suppression on inputs (bottom view) pins (IEC 61000-4-2 level 4) ■ High reliability offered by monolithic integration Figure 1. Pin configuration (top view) ■ High reduction of parasitic elements through integration and wafer level packaging 1 Input Output 12 ■ Lead-free package 2 Input Output 11 Complies with following standards: ■ IEC 61000-4-2 level 4 input and output pins 3 Input Output 10 – 15 kV (air discharge) – 8 kV (contact discharge) 4 Input Output 9 ■ MIL STD 883G - Method 3015-7 Class 3B (all pins) 5 Input Output 8 Applications 6 Input Output 7 Where EMI filtering in ESD sensitive equipment is required: Figure 2. Basic cell configuration ■ LCD and camera for mobile phones ■ Computers and printers 100Ω Input Output ■ Communication systems ■ MCU boards Description Typical line capacitance = 45 pF @ 0V EMIF06-1005M12 is a 6-line, highly integrated device designed to suppress EMI/RFI noise in all systems exposed to electromagnetic interference. This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 15 kV on the input pins. TM: IPAD is a trademark of STMicroelectronics February 2008 Rev 3 1/10 www.st.com

Characteristics EMIF06-1005M12 1 Characteristics Table 1. A bsolute ratings (limiting values at T = 25 °C unless otherwise specified) amb Symbol Parameter Value Unit ESD IEC 61000-4-2, air discharge 15 V kV PP ESD IEC 61000-4-2, contact discharge 15 T Junction temperature 125 °C j T Operating temperature range -40 to + 85 °C op T Storage temperature range -55 to +150 °C stg Table 2. E lectrical characteristics (T = 25 °C) amb Symbol Parameter I V Breakdown voltage BR IF I Leakage current @ V RM RM V Stand-off voltage RM VCL Clamping voltage VCVLBR VRM VF V IRM Rd Dynamic resistance IR I Peak pulse current PP R Series resistance between Input & Output I/O IPP C Input capacitance per line line Symbol Test conditions Min. Typ. Max. Unit V I = 1 mA 6 8 10 V BR R V I = 10 mA 0.5 1.0 1.5 F F I V = 3 V per line 200 nA RM RM R Tolerance ± 10% 90 100 110 Ω I/O C V = 0 V dc, V = 30 mV, F = 1 MHz 38 45 52 pF line LINE OSC Figure 3. S 21 attenuation measurement Figure 4. Analog cross talk measurements dB dB 0.00 0.00 -10.00 -20.00 -10.00 -30.00 -40.00 -20.00 -50.00 -60.00 -70.00 -30.00 -80.00 F (Hz) -90.00 F (Hz) -40.00 -100.00 100.0k 1.0M 10.0M 100.0M 1.0G 1.0M 3.0M 10.0M 30.0M 100.0M300.0M 1.0G 3.0G 2/10

EMIF06-1005M12 Ordering information scheme Figure 5. E SD response to IEC 61000-4-2 Figure 6. ESD response to IEC 61000-4-2 (+15 kV air discharge) on one input (-15 kV air discharge) on one input (V ) and on one output (V ) (V ) and on one output (V ) in out in out Figure 7. Line capacitance versus reverse voltage applied (typical value) C (pF) 50.00 LINE 45.00 40.00 35.00 30.00 25.00 20.00 15.00 10.00 5.00 V (V) LINE 0.00 0 1 2 3 4 5 2 Ordering information scheme Figure 8. Ordering information scheme EMIF yy - xxx z Mx EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) Package Mx = Micro QFN x leads 3/10

Package information EMIF06-1005M12 3 Package information ● Epoxy meets UL94, V0 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. T able 3. QFN 2.5 x 1.5 package dimensions Dimensions D N Ref Millimeters inches E MIN TYP MAX MIN TYP MAX A 0.50 0.55 0.60 0.20 0.22 0.24 1 2 A1 0.00 0.02 0.05 0.00 0.01 0.02 A b 0.15 0.18 0.25 0.06 0.07 0.10 A1 D 2.50 0.98 D2 D2 1.70 1.80 1.90 0.67 0.71 0.75 1 2 E 1.50 0.59 L E2 0.30 0.40 0.50 0.12 0.16 0.24 E2 k e 0.40 0.16 N b k 0.20 0.08 e L 0.25 0.30 0.35 0.10 0.12 0.14 F igure 9. Footprint Figure 10. Marking 0.40 0.20 Dot:Pin 1 Identification X=Marking 0.60 YWW=Data code 0.25 (Y=year XXYY 0.40 2.10 WW= week wwww 1.80 4/10

EMIF06-1005M12 Package information Figure 11. Tape and reel specification 22..00++//--00..0055 44..0000++//--00..11 ff11..55 ++//--00..11 11 .7.7 55 ++ /-/- 00 .1.1 33 .5.5 ++ /-/- 8.18.1 0.050.05 +/-+/- 22 XXXYYY XXXYYY XXXYYY 0.10.1 .70.70 wwwwww wwwwww wwwwww 00..7755 11..7700 44..0000 UUsseerr ddiirreeccttiioonn ooff uunnrreeeelliinngg Note: Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin1 mark is to be used for this purpose. 5/10

Recommendation on PCB assembly EMIF06-1005M12 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 12. Stencil opening dimensions L T W b) General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = -----≥1.5 T L×W Aspect Area = ----------------------------≥0.66 2T(L+W) 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c) Stencil opening for leads: Opening to footprint ratio is 90%. Figure 13. Recommended stencil window position 5µm 5µm 15µm 600µm 570µm 0.40 0.20 0.60 190µm 0.25 15µm 0.40 2.10 200µm 1800µm 50µm 1.80 m µ 400µm 0 0 3 1224µm Footprint 50µm Stencilwindow 288µm 288µm Footprint 6/10

EMIF06-1005M12 Recommendation on PCB assembly 4.2 Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed 4. Solder paste with fine particles: powder particle size is 20-45 µm. 4.3 Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 4.4 PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. 7/10

Recommendation on PCB assembly EMIF06-1005M12 4.5 Reflow profile Figure 14. ST ECOPACK® recommended soldering reflow profile for PCB mounting TTeemmppeerraattuurree ((°°CC)) 226600°°CC mmaaxx 225555°°CC 222200°°CC 118800°°CC 112255 °°CC 2°C/s 2r°eCc/osm remceonmdmedended 3°C/s max 6°C/s max 6°C/s max 3°C/s max 00 00 11 22 33 44 55 66 77 1100--3300 sseecc TTiimmee ((mmiinn)) 9900 ttoo 115500 sseecc 9900 sseecc mmaaxx Note: Minimize air convection currents in the reflow oven to avoid component movement. 8/10

EMIF06-1005M12 Ordering information 5 Ordering information T able 4. Ordering information Order code Marking Package Weight Base qty Delivery mode EMIF06-1005M12 F(1) Micro QFN 6 mg 3000 Tape and reel (7”) 1. The marking can be rotated by 90° to differentiate assembly location 6 Revision history T able 5. Document revision history Date Revision Changes 3-Jul-2006 1 Initial release. 1-Feb-2007 2 Added note on marking rotation in section 3. Package information. Reformatted to current standards. Updated ECOPACK statement. 04-Feb-2008 3 Updated Section4: Recommendation on PCB assembly. 9/10

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