DATASHEET EL5120, EL5220, EL5420 FN7186 12MHz Rail-to-Rail Input-Output Op Amps Rev 8.00 October 15, 2015 The EL5120, EL5220, and EL5420 are low power, high Features voltage, rail-to-rail input-output amplifiers. The EL5120 • 12MHz -3dB Bandwidth contains a single amplifier, the EL5220 contains two amplifiers, and the EL5420 contains four amplifiers. • Supply Voltage = 4.5V to 16.5V Operating on supplies ranging from 5V to 15V, while • Low Supply Current (per Amplifier) = 500µA consuming only 500µA per amplifier, the EL5120, EL5220, and EL5420 have a bandwidth of 12MHz (-3dB). They also • High Slew Rate = 10V/µs provide common mode input ability beyond the supply rails, • Unity-Gain Stable as well as rail-to-rail output capability. This enables these amplifiers to offer maximum dynamic range at any supply • Beyond the Rails Input Capability voltage. • Rail-to-Rail Output Swing The EL5120, EL5220, and EL5420 also feature fast slewing • Ultra-Small Package and settling times, as well as a high output drive capability of • Pb-Free Available (RoHS Compliant) 30mA (sink and source). These features make these amplifiers ideal for use as voltage reference buffers in Thin Applications Film Transistor Liquid Crystal Displays (TFT-LCD). Other applications include battery power, portable devices, and • TFT-LCD Drive Circuits anywhere low power consumption is important. • Electronics Notebooks The EL5420 is available in the space-saving 14 Ld TSSOP • Electronics Games package, the industry-standard 14 Ld SOIC package, as well • Touch-Screen Displays as the 16 Ld QFN package. The EL5220 is available in the 8Ld MSOP package and the 8Ld DFN package. The • Personal Communication Devices EL5120 is available in the 5 Ld TSOT package. All feature a • Personal Digital Assistants (PDA) standard operational amplifier pin out. These amplifiers are specified for operation with an ambient and junction • Portable Instrumentation temperature range of -40°C to +125°C. • Sampling ADC Amplifiers • Wireless LANs • Office Automation • Active Filters • ADC/DAC Buffer FN7186 Rev 8.00 Page 1 of 21 October 15, 2015

EL5120, EL5220, EL5420 Ordering Information PART NUMBER PART TEMP. RANGE (Note 3) MARKING (°C) PACKAGE PKG. DWG. # EL5120IWT-T7 (Notes 1, 4) (No longer K -40 to +125 5 Ld TSOT Tape and Reel MDP0049 available or supported) EL5220ILZ-T13 (Notes 1, 2, 4) (No 20Z -40 to +125 8 Ld DFN Tape and Reel (Pb-Free) L8.2x3 longer available or supported) EL5220CYZ (Note 2) BBAAA -40 to +125 8 Ld MSOP (Pb-Free) MDP0043 EL5220CYZ-T7 (Notes 1, 2) BBAAA -40 to +125 8 Ld MSOP Tape and Reel (Pb-Free) MDP0043 EL5220CYZ-T13 (Notes 1, 2) BBAAA -40 to +125 8 Ld MSOP Tape and Reel (Pb-Free) MDP0043 EL5420CLZ (Note 2) (No longer 5420CLZ -40 to +125 16 Ld QFN (Pb-Free) MDP0046 available or supported) EL5420CSZ (Note 2) 5420CSZ -40 to +125 14 Ld SOIC (Pb-Free) MDP0027 EL5420CSZ-T7 (Notes 1, 2) 5420CSZ -40 to +125 14 Ld SOIC Tape and Reel (Pb-Free) MDP0027 EL5420CSZ-T13 (Notes 1, 2) 5420CSZ -40 to +125 14 Ld SOIC Tape and Reel (Pb-Free) MDP0027 EL5420CR (Note 4) (No longer 5420CR -40 to +125 14 Ld TSSOP MDP0044 available or supported) EL5420CRZ (Note 2) 5420CRZ -40 to +125 14 Ld TSSOP (Pb-Free) M14.173 EL5420CRZ-T7 (Notes 1, 2) 5420CRZ -40 to +125 14 Ld TSSOP Tape and Reel (Pb-Free) M14.173 EL5420CRZ-T13 (Notes 1, 2) 5420CRZ -40 to +125 14 Ld TSSOP Tape and Reel (Pb-Free) M14.173 NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for EL5120, EL5220, EL5420. For more information on MSL please see tech brief TB363. 4. Not recommended for new designs. Refer to EL5x20T for possible substitutions. FN7186 Rev 8.00 Page 2 of 21 October 15, 2015

EL5120, EL5220, EL5420 Pinouts EL5220 EL5220 (8 LD DFN) (8 LD MSOP) TOP VIEW TOP VIEW D E RT VOVIUNTAA- 12 - 87 VVOS+UTB VOUTA 1 O R SUPP O 8 VS+ + VINA- 2 THEBRLEM AL 7 VOUTB A VINA+ 3 - 6 VINB- VINA+ 3 AVAIL PAD 6 VINB- R VS- 4 + 5 VINB+ VS- 4G E 5 VINB+ N O O L N THERMAL PAD CONNECTS TO VS- EL5120 EL5420 EL5420 (5 LD TSOT) D (14 LD TSSOP, SOIC) (16 LD QFN) E TOP VIEW RT TOP VIEW TOP VIEW O UPP VVOVIUNST+-G E123R AVAILA B+LE -O R S 54 VVSIN+- VVOVIINUNATAA+- 123 - + + - 111432VVVIIONNUDDT-+D VINA- 1 16NC 15VOUTA 14VOUTD U13NCPP O1R2TEVD IND- N O LO N VS+ 4 11 VS- VINA+ 2 THERBLME AOLR S 11 VIND+ A VINB+ 5 10VINC+ VS+ 3 AVAILPAD 10VS- R VINB- 6 - + + - 9 VINC- VINB+ 4N G E 9 VINC+ O O L VOUTB 7 8 VOUTC N 5 6 7 8 NB- UTB UTC NC- VI O O VI V V THERMAL PAD CONNECTS TO VS- FN7186 Rev 8.00 Page 3 of 21 October 15, 2015

EL5120, EL5220, EL5420 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS+ and VS-. . . . . . . . . . . . . . . . . . . .+18V Thermal Resistance (Typical) JA (°C/W) Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS +0.5V 5 Ld TSOT (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . 214 Maximum Continuous Output Current. . . . . . . . . . . . . . . . . . . 30mA 8 Ld DFN (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8 Ld MSOP (Note 5). . . . . . . . . . . . . . . . . . . . . . . . . 115 16 Ld QFN (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . 44 14 Ld SOIC (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . 82 14 Ld TSSOP (Note 5). . . . . . . . . . . . . . . . . . . . . . . 93 Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature Range . . . . . . . . . .-40°C to +125° Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications VS+ = +5V, VS- = -5V, RL = 10k and CL = 10pF to 0V, TA = +25°C, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 0V 2 12 mV TCVOS Average Offset Voltage Drift (Note 7) 5 µV/°C IB Input Bias Current VCM = 0V 2 50 nA RIN Input Impedance 1 G CIN Input Capacitance 1.35 pF CMIR Common-Mode Input Range -5.5 +5.5 V CMRR Common-Mode Rejection Ratio for VIN from -5.5V to +5.5V 50 70 dB AVOL Open Loop Gain -4.5V VOUT 4.5V 75 95 dB OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA -4.92 -4.85 V VOH Output Swing High IL = 5mA 4.85 4.92 V ISC Short Circuit Current ±120 mA IOUT Output Current ±30 mA POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from ±2.25V to ±7.75V 60 80 dB IS Supply Current (Per Amplifier) No load 500 750 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 8) -4.0V VOUT 4.0V, 20% to 80% 10 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns BW -3dB Bandwidth RL = 10k, CL = 10pF 12 MHz GBWP Gain-Bandwidth Product RL = 10k, CL = 10pF 8 MHz PM Phase Margin RL = 10k, CL = 10pF 50 ° CS Channel Separation f = 5MHz (EL5220 and EL5420 only) 75 dB NOTES: 7. Measured over operating temperature range. 8. Slew rate is measured on rising and falling edges. FN7186 Rev 8.00 Page 4 of 21 October 15, 2015

EL5120, EL5220, EL5420 Electrical Specifications VS+ = +5V, VS- = 0V, RL = 10k and CL = 10pF to 2.5V, TA = +25°C, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 2.5V 2 10 mV TCVOS Average Offset Voltage Drift (Note 9) 5 µV/°C IB Input Bias Current VCM = 2.5V 2 50 nA RIN Input Impedance 1 G CIN Input Capacitance 1.35 pF CMIR Common-Mode Input Range -0.5 +5.5 V CMRR Common-Mode Rejection Ratio for VIN from -0.5V to +5.5V 45 66 dB AVOL Open Loop Gain 0.5V VOUT 4.5V 75 95 dB OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA 80 150 mV VOH Output Swing High IL = +5mA 4.85 4.92 V ISC Short Circuit Current ±120 mA IOUT Output Current ±30 mA POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V 60 80 dB IS Supply Current (Per Amplifier) No load 500 750 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 10) 1V VOUT 4V, 20% to 80% 10 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns BW -3dB Bandwidth RL = 10k, CL = 10pF 12 MHz GBWP Gain-Bandwidth Product RL = 10k, CL = 10pF 8 MHz PM Phase Margin RL = 10k, CL = 10pF 50 ° CS Channel Separation f = 5MHz (EL5220 and EL5420 only) 75 dB NOTES: 9. Measured over operating temperature range. 10. Slew rate is measured on rising and falling edges. FN7186 Rev 8.00 Page 5 of 21 October 15, 2015

EL5120, EL5220, EL5420 Electrical Specifications VS+ = +15V, VS- = 0V, RL = 10k and CL = 10pF to 7.5V, TA = +25°C, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 7.5V 2 14 mV TCVOS Average Offset Voltage Drift (Note 11) 5 µV/°C IB Input Bias Current VCM = 7.5V 2 50 nA RIN Input Impedance 1 G CIN Input Capacitance 1.35 pF CMIR Common-Mode Input Range -0.5 +15.5 V CMRR Common-Mode Rejection Ratio for VIN from -0.5V to +15.5V 53 72 dB AVOL Open Loop Gain 0.5V VOUT 14.5V 75 95 dB OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA 80 150 mV VOH Output Swing High IL = +5mA 14.85 14.92 V ISC Short Circuit Current ±120 mA IOUT Output Current ±30 mA POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V 60 80 dB IS Supply Current (Per Amplifier) No load 500 750 µA DYNAMIC PERFORMANCE SR Slew Rate (Note 12) 1V VOUT 14V, 20% to 80% 10 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 500 ns BW -3dB Bandwidth RL = 10k, CL = 10pF 12 MHz GBWP Gain-Bandwidth Product RL = 10k, CL = 10pF 8 MHz PM Phase Margin RL = 10k, CL = 10pF 50 ° CS Channel Separation f = 5MHz (EL5220 and EL5420 only) 75 dB NOTES: 11. Measured over operating temperature range 12. Slew rate is measured on rising and falling edges FN7186 Rev 8.00 Page 6 of 21 October 15, 2015

EL5120, EL5220, EL5420 Typical Performance Curves 1800 70 VS = ±5V TYPICAL VS = ±5V TYPICAL RS) 11640000 TA = +25°C PDRISOTDRUIBCUTTIOIONN RS) 60 PDRISOTDRUIBCUTTIOIONN MPLIFIE 11200000 MPLIFIE 5400 A A NTITY ( 860000 NTITY ( 3200 A A U 400 U Q Q 10 200 0 0 12 10 -8 -6 -4 -2 -0 2 4 6 8 10 12 1 3 5 7 9 11 13 15 17 19 21 - - INPUT OFFSET VOLTAGE (mV) INPUT OFFSET VOLTAGE DRIFT, TCVOS (µV/°C) FIGURE 1. EL5420 INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE 2. EL5420 INPUT OFFSET VOLTAGE DRIFT V) 10 VS = ±5V VS = ±5V m A) 2.0 GE ( T (n A 5 N T VOLT CURRE 0.0 SE 0 S F A T OF UT BI U -5 P NP IN -2.0 I -50 0 50 100 150 -50 0 50 100 150 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE 4.97 -4.91 VS = ±5V VS = ±5V GE (V) 4.96 IOUT = 5mA GE (V) -4.92 IOUT = -5mA OLTA OLTA -4.93 H V 4.95 W V -4.94 G HI LO T T -4.95 U U P 4.94 P T T U U -4.96 O O 4.93 -4.97 -50 0 50 100 150 -50 0 50 100 150 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 5. OUTPUT HIGH VOLTAGE vs TEMPERATURE FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE FN7186 Rev 8.00 Page 7 of 21 October 15, 2015

EL5120, EL5220, EL5420 Typical Performance Curves (Continued) 100 VRSL == 1±50kV 10.40 VS = ±5V B) GAIN (d 90 E (V/µs) 10.35 LOOP W RAT 10.30 N E OPE 80 SL 10.25 -50 0 50 100 150 -50 0 50 100 150 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 7. OPEN LOOP GAIN vs TEMPERATURE FIGURE 8. SLEW RATE vs TEMPERATURE 700 VS = ±5V TA = +25°C mA) 0.55 µA) 600 T ( T ( N N E E R R R R 500 U 0.5 U C C Y Y L L P P P P 400 U U S S 0.45 300 -50 0 50 100 150 0 5 10 15 20 TEMPERATURE (°C) SUPPLY VOLTAGE (V) FIGURE 9. EL5420 SUPPLY CURRENT PER AMPLIFIER vs FIGURE 10. EL5420 SUPPLY CURRENT PER AMPLIFIER vs TEMPERATURE SUPPLY VOLTAGE 200 20 5 B) d 150 -30 D) ( 10k PHASE E 0 Z 1k LI GAIN (dB) 15000 --81030 PHASE (°) E (NORMA -5 560 D 0 VRSL == ±150Vk, T tAo =G +N2D5°C GAIN -180 GNITU -10 CAVL == 110pF 150 -50 CL = 12pF to GND -230 MA -15 VS = ±5V 10 100 1k 10k 100k 1M 10M 100M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 11. OPEN LOOP GAIN AND PHASE vs FREQUENCY FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS RL FN7186 Rev 8.00 Page 8 of 21 October 15, 2015

EL5120, EL5220, EL5420 Typical Performance Curves (Continued) 20 200 B) RL = 10k AV = 1 ED) (d 10 AVVS == 1±5V E () 160 VTAS == +±255V°C Z 12pF C LI N A 0 A 120 M D R 50pF E O P N M E ( -10 100pF T I 80 D U U 1000pF P NIT -20 OUT 40 G A M -30 0 100k 1M 10M 100M 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS CL FIGURE 14. CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY 12 80 )P P- V 10 G ( 60 N WI 8 B) S d UT 6 R ( 40 P R OUT 4 VTAS == +±255V°C CM M AV = 1 20 AXIMU 2 RCDiLLs ==to 11rt20ipkoFn <1% VTAS == +±255V°C M 0 0 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 15. MAXIMUM OUTPUT SWING vs FREQUENCY FIGURE 16. CMRR vs FREQUENCY 80 600 PSRR+ z) H 60 PSRR- V/ 100 n B) E ( d S PSRR ( 40 GE NOI 10 A T 20 L O V VS = ±5V TA = +25°C 0 1 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 17. PSRR vs FREQUENCY FIGURE 18. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY FN7186 Rev 8.00 Page 9 of 21 October 15, 2015

EL5120, EL5220, EL5420 Typical Performance Curves (Continued) 0.010 -60 DUAL MEASURED CHANNEL A TO B 0.009 QUAD MEASURED CHANNEL A TO D OR B TO C 0.008 -80 OTHER COMBINATIONS YIELD %) 0.007 dB) IMPROVED REJECTION N ( 0.006 K ( -100 D+ 0.005 AL TH 00..000034 VRSL == 1±50Vk X-T -120 VRSL == ±150Vk AV = 1 AV = 1 0.002 VIN = 1VRMS VIN = 220mVRMS 0.001 -140 1k 10k 100k 1k 10k 100k 1M 6M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 19. TOTAL HARMONIC DISTORTION + NOISE vs FIGURE 20. CHANNEL SEPARATION vs FREQUENCY FREQUENCY RESPONSE 90 VAVS == 1±5V 4 VAVS == 1±5V RL = 10k 3 RL = 10k OT (%) 70 VTAIN = = + ±2550°mCV E (V) 21 CTAL == +1225p°FC 0.1% O Z H 50 SI 0 OVERS 30 STEP --21 0.1% -3 10 -4 10 100 1k 0 200 400 600 800 LOAD CAPACITANCE (pF) SETTLING TIME (ns) FIGURE 21. SMALL SIGNAL OVERSHOOT vs LOAD FIGURE 22. SETTLING TIME vs STEP SIZE CAPACITANCE 1V 1µs 50mV 200ns VS = ±5V VS = ±5V TA = +25°C TA = +25°C AV = 1 AV = 1 RL = 10k RL = 10k CL = 12pF CL = 12pF FIGURE 23. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 24. SMALL SIGNAL TRANSIENT RESPONSE FN7186 Rev 8.00 Page 10 of 21 October 15, 2015

EL5120, EL5220, EL5420 Pin Descriptions EL5120 EL5220 EL5420 5 LD 8 LDMSOP, 14 LD TSSOP, 16 LD TSOT 8LD DFN 14 LD SOIC QFN PIN NAME PIN FUNCTION EQUIVALENT CIRCUIT 13, 16 NC No Connect IN+ Amplifier Non-Inverting Input (Reference Circuit 1) IN- Amplifier Inverting Input (Reference Circuit 1) OUT Amplifier Output (Reference Circuit 2) 3 VIN+ Amplifier Non-Inverting Input (Reference Circuit 1) 4 VIN- Amplifier Inverting Input (Reference Circuit 1) 1 VOUT Amplifier Output (Reference Circuit 2) 1 1 15 VOUTA Amplifier A Output (Reference Circuit 2) 2 2 1 VINA- Amplifier A Inverting Input (Reference Circuit 1) 3 3 2 VINA+ Amplifier A Non-Inverting Input (Reference Circuit 1) 5 8 4 3 VS+ Positive Power Supply 5 5 4 VINB+ Amplifier B Non-Inverting Input (Reference Circuit 1) 6 6 5 VINB- Amplifier B Inverting Input (Reference Circuit 1) 7 7 6 VOUTB Amplifier B Output (Reference Circuit 2) 8 7 VOUTC Amplifier C Output (Reference Circuit 2) 9 8 VINC- Amplifier C Inverting Input (Reference Circuit 1) 10 9 VINC+ Amplifier C Non-Inverting Input (Reference Circuit 1) 2 4 11 10 VS- Negative Power Supply 12 11 VIND+ Amplifier D Non-Inverting Input (Reference Circuit 1) 13 12 VIND- Amplifier D Inverting Input (Reference Circuit 1) 14 14 VOUTD Amplifier D Output (Reference Circuit 2) VS+ VS+ VS- VS- GND CIRCUIT 1 CIRCUIT 2 FN7186 Rev 8.00 Page 11 of 21 October 15, 2015

EL5120, EL5220, EL5420 Applications Information indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is Product Description maintained if the output continuous current never exceeds The EL5120, EL5220, and EL5420 voltage feedback ±30mA. This limit is set by the design of the internal metal amplifiers are fabricated using a high voltage CMOS interconnects. process. They exhibit rail-to-rail input and output capability, Output Phase Reversal they are unity gain stable, and have low power consumption (500µA per amplifier). These features make the EL5120, The EL5120, EL5220, and EL5420 are immune to phase EL5220, and EL5420 ideal for a wide range of general- reversal as long as the input voltage is limited from (VS-) purpose applications. Connected in voltage follower mode -0.5V to (VS+) +0.5V. Figure 26 shows a photo of the output and driving a load of 10k and 12pF, the EL5120, EL5220, of the device with the input voltage driven beyond the supply and EL5420 have a -3dB bandwidth of 12MHz while rails. Although the device's output will not change phase, the maintaining a 10V/µs slew rate. The EL5120 is a single input's overvoltage should be avoided. If an input voltage amplifier, the EL5220 is a dual amplifier, and the EL5420 is a exceeds supply voltage by more than 0.6V, electrostatic quad amplifier. protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. Operating Voltage, Input, and Output The EL5120, EL5220, and EL5420 are specified with a 1V 100µs single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5120, EL5220, and EL5420 specifications are stable over both the full supply range and operating junction temperature range of -40°C to +125°C. Parameter variations VS = ±2.5V with operating voltage and/or temperature are shown in the TA = +25°C typical performance curves. AV = 1 1V VIN = 6VP-P The input common-mode voltage range of the EL5120, EL5220, and EL5420 extends 500mV beyond the supply FIGURE 26. OPERATION WITH BEYOND-THE-RAILS INPUT rails. The output swings of the EL5120, EL5220, and EL5420 typically extend to within 80mV of positive and Power Dissipation negative supply rails with load currents of 5mA. Decreasing With the high-output drive capability of the EL5120, EL5220, load currents will extend the output voltage range even and EL5420 amplifiers, it is possible to exceed the +125°C closer to the supply rails. Figure 25 shows the input and maximum operating junction temperature under certain load output waveforms for the device in the unity-gain current conditions. Therefore, it is important to calculate the configuration. Operation is from ±5V supply with a 10k load maximum junction temperature for the application to connected to GND. The input is a 10VP-P sinusoid. The determine if load conditions need to be modified for the output voltage is approximately 9.985VP-P. amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is VS = ±5V TA = +25°C determined according to Equation 1: AV = 1 VIN = 10VP-P TJMAX–TAMAX P = --------------------------------------------- DMAX  (EQ. 1) T JA U P N where: I • TJMAX = Maximum junction temperature T U TP • TAMAX = Maximum ambient temperature U O • JA = Thermal resistance of the package • PDMAX = Maximum power dissipation in the package FIGURE 25. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power Short Circuit Current Limit The EL5120, EL5220, and EL5420 will limit the short circuit current to ±120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted FN7186 Rev 8.00 Page 12 of 21 October 15, 2015

EL5120, EL5220, EL5420 supply voltage, plus the power in the IC due to the loads as 10k with just 1.5dB of peaking, and 100pF with 6.4dB of shown in Equation 2: peaking. If less peaking is desired in these applications, a small series resistor (usually between 5 and 50) can be P = iV I +V +–V iI i DMAX S SMAX S OUT LOAD (EQ. 2) placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is when sourcing, and: to add a “snubber” circuit at the output. A snubber is a shunt PDMAX = iVSISMAX+VOUTi–VS-ILOADi (EQ. 3) load consisting of a resistor in series with a capacitor. Values of 150 and 10nF are typical. The advantage of a snubber is that when sinking. it does not draw any DC load current or reduce the gain where: Power Supply Bypassing and Printed Circuit Board Layout • i = 1 to 2 for dual and 1 to 4 for quad The EL5120, EL5220, and EL5420 can provide gain at high • VS = Total supply voltage frequency. As with any high-frequency device, good printed • ISMAX = Maximum supply current per amplifier circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead • VOUTi = Maximum output voltage of the application lengths should be as short as possible and the power supply • ILOADi = Load current pins must be well bypassed to reduce the risk of oscillation. For If we set the two PDMAX equations equal to each other, we can normal single supply operation, where the VS- pin is solve for RLOADi to avoid device overheat. Figure 27 provide a connected to ground, a 0.1µF ceramic capacitor should be convenient way to see if the device will overheat. The maximum placed from VS+ to pin to VS- pin. A 4.7µF tantalum capacitor safe power dissipation can be found graphically, based on the should then be connected in parallel, placed in the region of package type and the ambient temperature. By using the the amplifier. One 4.7µF capacitor may be used for multiple previous equation, it is a simple matter to see if PDMAX exceeds devices. This same capacitor combination should be placed at the device's power derating curves. To ensure proper operation, each supply pin to ground if split supplies are to be used. it is important to observe the recommended derating curves in Figure 27. JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 3.0 QFN16 ON (W) 22..05 21..2870WW JA = 44°C/W JAS D=O F5INC58°1C4/W ATI JA = 82°C/W DISSIP 1.5 1.22W JTAS =S 9O3P°1C4/W R 1.0 MSOP8 WE 870mW JA = 115°C/W O 0.5 TSOT5 P 467mW JA = 214°C/W 0.0 0 25 50 75 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Unused Amplifiers It is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground plane. Driving Capacitive Loads The EL5120, EL5220, and EL5420 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking will increase. The amplifiers drive 10pF loads in parallel with FN7186 Rev 8.00 Page 13 of 21 October 15, 2015

EL5120, EL5220, EL5420 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE October 15, 2015 FN7186.8 - Updated Ordering Information Table on page2. - Added Revision History. - Added About Intersil Verbiage. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2004-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7186 Rev 8.00 Page 14 of 21 October 15, 2015

EL5120, EL5220, EL5420 Package Outline Drawing L8.2x3 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 3/10 2.00 A 2X 1.50 PIN 1 INDEX AREA 6X 0.50 B 1 6 PIN #1 INDEX AREA 1.80 +0.10/-0.15 0 0 3. (4X) 0.15 8 8X 0.25 +0.07/-0.05 4 8X 0.40 ±0.10 TOP VIEW 1.65 +0.10/-0.15 0.10M C A B BOTTOM VIEW SEE DETAIL "X" 0.90 ±0.10 0.10 C (1.65) (1.50) C BASE PLANE SEATING PLANE (8X 0.60) 0.08 C 0.05 MAX SIDE VIEW (2.80)(1.80) 0.20 REF C (6X 0.50) (8X 0.25) 0.05 MAX DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compies to JEDEC MO-229 VCED-2. FN7186 Rev 8.00 Page 15 of 21 October 15, 2015

EL5120, EL5220, EL5420 Small Outline Package Family (SO) A D h X 45¬ NN (N/2)+1 A PIN #1 I.D. MARK E E1 c SEE DETAIL ‚Äö 1 (N/2) B L1 0.010M C A B e H C A2 GAUGE SEATING PLANE 0.010 PLANE A1 L 4¬¨¬®Ð 0.004 C 0.010M C A B b DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SO16 SO16 (0.300”) SO20 SO24 SO28 SYMBOL SO-8 SO-14 (0.150”) (SOL-16) (SOL-20) (SOL-24) (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - N 8 14 16 16 20 24 28 Reference - Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 FN7186 Rev 8.00 Page 16 of 21 October 15, 2015

EL5120, EL5220, EL5420 Mini SO Package Family (MSOP) MDP0043 0.25M CAB A MINI SO PACKAGE FAMILY D (N/2)+1 N MILLIMETERS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - E E1 PIN #1 A2 0.86 0.86 ±0.09 - I.D. b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 1 B (N/2) E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - e H C L 0.55 0.55 ±0.15 - SEATING L1 0.95 0.95 Basic - PLANE N 8 10 Reference - 0.10 C b 0.08M CAB Rev. D 2/07 N LEADS NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE 0.25 A1 L 3¬¨¬®Ð DETAIL X FN7186 Rev 8.00 Page 17 of 21 October 15, 2015

EL5120, EL5220, EL5420 Thin Shrink Small Outline Package Family (TSSOP) 0.25M C A B MDP0044 D A THIN SHRINK SMALL OUTLINE PACKAGE FAMILY N (N/2)+1 MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. A 1.20 1.20 1.20 1.20 1.20 Max E E1 A1 0.10 0.10 0.10 0.10 0.10 ±0.05 A2 0.90 0.90 0.90 0.90 0.90 ±0.05 0.20 C B A b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 1 (N/2) 2X N/2 LEAD TIPS B c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 TOP VIEW D 5.00 5.00 6.50 7.80 9.70 ±0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 e 0.05 H e 0.65 0.65 0.65 0.65 0.65 Basic C L 0.60 0.60 0.60 0.60 0.60 ±0.15 SEATING L1 1.00 1.00 1.00 1.00 1.00 Reference PLANE Rev. F 2/07 b 0.10M C A B NOTES: 0.10 C N LEADS SIDE VIEW 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per SEE DETAIL ‚Äö side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A2 A GAUGE PLANE 0.25 L A1 0¬¨¬®Ðê DETAIL X FN7186 Rev 8.00 Page 18 of 21 October 15, 2015

EL5120, EL5220, EL5420 QFN (Quad Flat No-Lead) Package Family MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY A (COMPLIANT TO JEDEC MO-220) D MILLIMETERS 1)2) B SYMBOL QFN44 QFN3 QFN32 TOLERANCE NOTES NN-N- (( A 0.90 0.90 0.90 0.90 ±0.10 - 1 A1 0.02 0.02 0.02 0.02 +0.03/-0.02 - 2 PIN #1 b 0.25 0.25 0.23 0.22 ±0.02 - 3 I.D. MARK c 0.20 0.20 0.20 0.20 Reference - E D 7.00 5.00 8.00 5.00 Basic - D2 5.10 3.80 5.80 3.60/2.48 Reference 8 E 7.00 7.00 8.00 6.00 Basic - 2X E2 5.10 5.80 5.80 4.60/3.40 Reference 8 0.075C 2) N/ e 0.50 0.50 0.80 0.50 Basic - ( 2X 0.075C L 0.55 0.40 0.53 0.50 ±0.05 - TOP VIEW N 44 38 32 32 Reference 4 S ND 11 7 8 7 Reference 6 D EA 0.10 M CAB NE 11 12 8 9 Reference 5 L N b L (N-2)(N-1)N PIN #1 I.D. MILLIMETERS TOLER- 3 SYMBOL QFN28 QFN2 QFN20 QFN16 ANCE NOTES 1 2 A 0.90 0.90 0.90 0.90 0.90 ±0.10 - 3 A1 0.02 0.02 0.02 0.02 0.02 +0.03/ - -0.02 (E2) b 0.25 0.25 0.30 0.25 0.33 ±0.02 - c 0.20 0.20 0.20 0.20 0.20 Reference - NE 5 D 4.00 4.00 5.00 4.00 4.00 Basic - D2 2.65 2.80 3.70 2.70 2.40 Reference - 2) N/ E 5.00 5.00 5.00 4.00 4.00 Basic - ( 7 (D2) E2 3.65 3.80 3.70 2.70 2.40 Reference - BOTTOM VIEW e 0.50 0.50 0.65 0.50 0.65 Basic - L 0.40 0.40 0.40 0.40 0.60 ±0.05 - 0.10 C e N 28 24 20 20 16 Reference 4 C ND 6 5 5 5 4 Reference 6 SEATING NE 8 7 5 5 4 Reference 5 PLANE Rev 11 2/07 0.08 C SEE DETAIL "X" NOTES: N LEADS 1. Dimensioning and tolerancing per ASME Y14.5M-1994. & EXPOSED PAD SIDE VIEW 2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. (c) 2 5. NE is the number of terminals on the “E” side of the package A (orY-direction). C 6. ND is the number of terminals on the “D” side of the package (orX-direction). ND = (N/2)-NE. (L) A1 7. Inward end of terminal may be square or circular in shape with radius N LEADS (b/2) as shown. DETAIL X 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. FN7186 Rev 8.00 Page 19 of 21 October 15, 2015

EL5120, EL5220, EL5420 TSOT Package Family MDP0049 e1 D TSOT PACKAGE FAMILY A MILLIMETERS 6 N 4 SYMBOL TSOT5 TSOT6 TSOT8 TOLERANCE A 1.00 1.00 1.00 Max A1 0.05 0.05 0.05 ±0.05 E1 E A2 0.87 0.87 0.87 ±0.03 2 3 b 0.38 0.38 0.29 ±0.07 0.15 C D c 0.127 0.127 0.127 +0.07/-0.007 2X 1 2 (N/2) 0.25 C D 2.90 2.90 2.90 Basic 5 e 2X N/2 TIPS E 2.80 2.80 2.80 Basic E1 1.60 1.60 1.60 Basic B dddM C A-B D b e 0.95 0.95 0.65 Basic NX e1 1.90 1.90 1.95 Basic L 0.40 0.40 0.40 ±0.10 L1 0.60 0.60 0.60 Reference 0.15 C A-B 1 3 ddd 0.20 0.20 0.13 - 2X D N 5 6 8 Reference Rev. B 2/07 C NOTES: A2 1. Plastic or metal protrusions of 0.15mm maximum per side are SEATING not included. PLANE A1 2. Plastic interlead protrusions of 0.15mm maximum per side are 0.10 C not included. NX 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (TSOT6 AND TSOT8 only). (L1) H 6. TSOT5 version has no center lead (shown as a dashed line). A GAUGE PLANE 0.25 c L 4¬¨¬®Ð FN7186 Rev 8.00 Page 20 of 21 October 15, 2015

EL5120, EL5220, EL5420 Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 3 5.00 ±0.10 14 8 SEE DETAIL "X" 6.40 PIN #1 4.40 ±0.10 I.D. MARK 2 3 0.20 CBA 1 7 0.65 B 0.09-0.20 TOP VIEW END VIEW 1.00 REF H 0.05 C 0.90 +0.15/-0.10 1.20 MAX SEATING GAUGE PLANE PLANE 0.25 0.25 +0.05/-0.06 5 0.10C 0.10 CBA 0.05 MIN 0°-8° 0.15 MAX 0.60 ±0.15 SIDE VIEW DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. TYPICAL RECOMMENDED LAND PATTERN FN7186 Rev 8.00 Page 21 of 21 October 15, 2015

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: R enesas Electronics: EL5220CYZ-T13 EL5420CRZ EL5420CRZ-T13 EL5420CRZ-T7 EL5220CYZ EL5220CYZ-T7 EL5420CRZ-T7A EL5420CSZ EL5420CSZ-T13 EL5420CSZ-T7