LPC2478 Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, LCD, USB 2.0 device/host/OTG, external memory interface Rev. 3.1 — 16 October 2013 Product data sheet 1. General description NXP Semiconductors designed the LPC2478 microcontroller, powered by the ARM7TDMI-S core, to be a highly integrated microcontroller for a wide range of applications that require advanced communications and high quality graphic displays. The LPC2478 microcontroller has 512kB of on-chip high-speed flash memory. This flash memory includes a special 128-bit wide memory interface and accelerator architecture that enables the CPU to execute sequential instructions from flash memory at the maximum 72MHz system clock rate. This feature is available only on the LPC2000 ARM microcontroller family of products. The LPC2478, with real-time debug interfaces that include both JTAG and embedded trace, can execute both 32-bit ARM and 16-bit Thumb instructions. The LPC2478 microcontroller incorporates an LCD controller, a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed Device/Host/OTG Controller with 4kB of endpoint RAM, four UARTs, two Controller Area Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I2C interfaces, and an I2S interface. Supporting this collection of serial communications interfaces are the following feature components; an on-chip 4MHz internal oscillator, 98kB of total RAM consisting of 64kB of local SRAM, 16kB SRAM for Ethernet, 16kB SRAM for general purpose DMA, 2kB of battery powered SRAM, and an External Memory Controller (EMC). These features make this device optimally suited for portable electronics and Point-of-Sale (POS) applications. Complementing the many serial communication controllers, versatile clocking capabilities, and memory features are various 32-bit timers, a 10-bit ADC, 10-bit DAC, two PWM units, and up to 160 fast GPIO lines. The LPC2478 connects 64 of the GPIO pins to the hardware based Vector Interrupt Controller (VIC) allowing the external inputs to generate edge-triggered interrupts. All of these features make the LPC2478 particularly suitable for industrial control and medical systems. 2. Features and benefits  ARM7TDMI-S processor, running at up to 72MHz.  512kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access.  98kB on-chip SRAM includes: 64kB of SRAM on the ARM local bus for high performance CPU access. 16kB SRAM for Ethernet interface. Can also be used as general purpose SRAM. 16kB SRAM for general purpose DMA use also accessible by the USB. 2kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller  LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film Transistors (TFT) displays. Dedicated DMA controller. Selectable display resolution (up to 1024768 pixels). Supports up to 24-bit true-color mode.  Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention.  EMC provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as single data rate SDRAM.  Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.  General Purpose DMA (GPDMA) controller on AHB that can be used with the SSP, I2S-bus, and SD/MMC interface as well as for memory-to-memory transfers.  Serial Interfaces: Ethernet MAC with MII/RMII interface and associated DMA controller. These functions reside on an independent AHB. USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and associated DMA controller. Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO. CAN controller with two channels. SPI controller. Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller. Three I2C-bus interfaces (one with open-drain and two with standard port pins). I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA.  Other peripherals: SD/MMC memory card interface. 160 General purpose I/O pins with configurable pull-up/down resistors. 10-bit ADC with input multiplexing among 8 pins. 10-bit DAC. Four general purpose timers/counters with 8 capture inputs and 10 compare outputs. Each timer block has an external count input. Two PWM/timer blocks with support for three-phase motor control. Each PWM has an external count input. RTC with separate power domain. Clock source can be the RTC oscillator or the APB clock. 2kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off. WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.  Single 3.3V power supply (3.0V to 3.6V).  4MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used as the system clock.  Four reduced power modes: idle, sleep, power-down and deep power-down.  Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0 and port 2 can be used as edge sensitive interrupt sources. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 2 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller  Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, port 0/2 pin interrupt).  Two independent power domains allow fine tuning of power consumption based on needed features.  Each peripheral has its own clock divider for further power saving. These dividers help reduce active power by 20% to 30%.  Brownout detect with separate thresholds for interrupt and forced reset.  On-chip power-on reset.  On-chip crystal oscillator with an operating range of 1MHz to 25MHz.  On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.  Boundary scan for simplified board testing.  Versatile pin function selections allow more possibilities for using on-chip peripheral functions.  Standard ARM test/debug interface for compatibility with existing tools.  Emulation trace module supports real-time trace. 3. Applications  Industrial control  Medical systems  Portable electronics  Point-of-Sale (POS) equipment 4. Ordering information Table 1. Ordering info rmation Type number Package Name Description Version LPC2478FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1 LPC2478FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15  15 SOT950-1 0.7mm LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 3 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 4.1 Ordering options Table 2. Ordering opt ions Type number Flash SRAM (kB) External Ethernet USB SD/ GP Temp range (kB) bus OTG/ MMC DMA r e OHC/ s s s uff device nel nel nel s b n n n bu et B + 4kB ha ha ha Local Ethern GP/US RTC Total FIFO CAN c ADC c DAC c LPC2478FBD208 512 64 16 16 2 98 Full MII/RMII yes 2 yes yes 8 1 40C to +85C 32-bit LPC2478FET208 512 64 16 16 2 98 Full MII/RMII yes 2 yes yes 8 1 40C to +85C 32-bit LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 4 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 5. Block diagram XTAL1 TMS TDI trace signals XTAL2 VDD(3V3) VDDA TRST TCK TDO RESET EXTIN0 DBGEN VREF LPC2478 SYSTEM P0, P1, P2, 64 kB 512 kB TEST/DEBUG E PLL FUNCTIONS VSSA, VSSIO, VSSCORE P3, P4 SRAM FLASH INTERFACE ONDUL VDD(DCDC)(3V3) HIGHG-PSIPOEED INTERNAL ARM7TDMI-S MULATICE MO scylsotcekm IONTSECRILNLAATLO RRC 160 PINS CONTROLLERS ERA TOTAL SRAM FLASH T EXTERNAL D[31:0] 16 kB VIC MEMORY A[23:0] SRAM CONTROLLER control lines AHB2 AHB1 AHB AHB BRIDGE BRIDGE 16 kB MASTER AHB TO SLAVE USB DEVICE/ VBUS MII/RMII EMTAHCE WRNITEHT SRAM PORT AHB BRIDGEPORT 4 HkOB SRTA/OMT AGN WD IDTHM A ppoorrtt21 DMA AHB TO APB BRIDGE GP DMA CONTROLLER EINT3 to EINT0 8 × LCD control EXTERNAL INTERRUPTS LCD INTERFACE P0, P2 LCDVD[23:0] WITH DMA LCDCLKIN 2 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2/MAT3, TIMER2/TIMER3 2 × MAT0, 3 × I2SRX 3 × MAT1 I2S INTERFACE 3 × I2STX 6 × PWM0/PWM1 PWM0, PWM1 SCK0, SCK 1 × PCAP0, MOSI0, MOSI 2 × PCAP1 SSP0/SPI INTERFACE MISO0, MISO SSEL0, SSEL LEGACY GPI/O P0, P1 64 PINS TOTAL SCK1 MOSI1 SSP1 INTERFACE MISO1 8 × AD0 A/D CONVERTER SSEL1 MCICLK, MCIPWR SD/MMC CARD AOUT D/A CONVERTER INTERFACE MCICMD, MCIDAT[3:0] VBAT 2 kB BATTERY RAM TXD0, TXD2, TXD3 UART0, UART2, UART3 RXD0, RXD2, RXD3 power domain 2 RTCX1 RTC REAL- TXD1, DTR1, RTS1 RTCX2 OSCILLATOR CTLIOMCEK UART1 RXD1, DSR1, CTS1, DCD1, RI1 ALARM RD1, RD2 CAN1, CAN2 WATCHDOG TIMER TD1, TD2 SCL0, SCL1, SCL2 I2C0, I2C1, I2C2 SDA0, SDA1, SDA2 SYSTEM CONTROL 002aac805 Fig 1. LPC2478 block diagram LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 5 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 6. Pinning information 6.1 Pinning 8 7 0 5 2 1 1 156 LPC2478FBD208 52 105 3 4 5 10 002aac808 Fig 2. LPC2478 pinning LQFP208 package ball A1 index area 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 17 A B C D E F G H J LPC2478FET208 K L M N P R T U 002aac809 Transparent top view Fig 3. LPC2478 pinning TFBGA208 package Table 3. Pin allocatio n table Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row A 1 P3[27]/D27/ 2 V 3 P1[0]/ENET_TXD0 4 P4[31]/CS1 SSIO CAP1[0]/PWM1[4] 5 P1[4]/ENET_TX_EN 6 P1[9]/ENET_RXD0 7 P1[14]/ENET_RX_ER 8 P1[15]/ ENET_REF_CLK/ ENET_RX_CLK 9 P1[17]/ENET_MDIO 10 P1[3]/ENET_TXD3/ 11 P4[15]/A15 12 V SSIO MCICMD/PWM0[2] LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 6 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol 13 P3[20]/D20/ 14 P1[11]/ENET_RXD2/ 15 P0[8]/I2STX_WS/ 16 P1[12]/ENET_RXD3/ PWM0[5]/DSR1 MCIDAT2/PWM0[6] LCDVD[16]/MISO1/ MCIDAT3/PCAP0[0] MAT2[2] 17 P1[5]/ENET_TX_ER/ - - - MCIPWR/PWM0[3] Row B 1 P3[2]/D2 2 P3[10]/D10 3 P3[1]/D1 4 P3[0]/D0 5 P1[1]/ENET_TXD1 6 V 7 P4[30]/CS0 8 P4[24]/OE SSIO 9 P4[25]/WE 10 P4[29]/BLS3/MAT2[1]/ 11 P1[6]/ENET_TX_CLK/ 12 P0[4]/I2SRX_CLK/ LCDVD[7]/LCDVD[11]/ MCIDAT0/PWM0[4] LCDVD[0]/RD2/CAP2[0] LCDVD[3]/RXD3 13 V 14 P3[19]/D19/ 15 P4[14]/A14 16 P4[13]/A13 DD(3V3) PWM0[4]/DCD1 17 P2[0]/PWM1[1]/TXD1/ - - - TRACECLK/LCDPWR Row C 1 P3[13]/D13 2 TDI 3 RTCK 4 P0[2]/TXD0 5 P3[9]/D9 6 P3[22]/D22/ 7 P1[8]/ENET_CRS_DV/ 8 P1[10]/ENET_RXD1 PCAP0[0]/RI1 ENET_CRS 9 V 10 P3[21]/D21/ 11 P4[28]/BLS2/MAT2[0]/ 12 P0[5]/I2SRX_WS/ DD(3V3) PWM0[6]/DTR1 LCDVD[6]/LCDVD[10]/ LCDVD[1]/TD2/CAP2[1] LCDVD[2]/TXD3 13 P0[7]/I2STX_CLK/ 14 P0[9]/I2STX_SDA/ 15 P3[18]/D18/ 16 P4[12]/A12 LCDVD[9]/SCK1/ LCDVD[17]/MOSI1/ PWM0[3]/CTS1 MAT2[1] MAT2[3] 17 V - - - DD(3V3) Row D 1 TRST 2 P3[28]/D28/ 3 TDO 4 P3[12]/D12 CAP1[1]/PWM1[5] 5 P3[11]/D11 6 P0[3]/RXD0 7 V 8 P3[8]/D8 DD(3V3) 9 P1[2]/ENET_TXD2/ 10 P1[16]/ENET_MDC 11 V 12 V DD(DCDC)(3V3) SSCORE MCICLK/PWM0[1] 13 P0[6]/I2SRX_SDA/ 14 P1[7]/ENET_COL/ 15 P2[2]/PWM1[3]/CTS1/ 16 P1[13]/ENET_RX_DV LCDVD[8]/SSEL1/ MCIDAT1/PWM0[5] PIPESTAT1/LCDDCLK MAT2[0] 17 P2[4]/PWM1[5]/ - - - DSR1/TRACESYNC/ LCDENAB/LCDM Row E 1 P0[26]/AD0[3]/ 2 TCK 3 TMS 4 P3[3]/D3 AOUT/RXD3 14 P2[1]/PWM1[2]/RXD1/ 15 V 16 P2[3]/PWM1[4]/DCD1/ 17 P2[6]/PCAP1[0]/RI1/ SSIO PIPESTAT0/LCDLE PIPESTAT2/LCDFP TRACEPKT1/ LCDVD[0]/LCDVD[4] Row F 1 P0[25]/AD0[2]/ 2 P3[4]/D4 3 P3[29]/D29/ 4 DBGEN I2SRX_SDA/TXD3 MAT1[0]/PWM1[6] LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 7 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol 14 P4[11]/A11 15 P3[17]/D17/ 16 P2[5]/PWM1[6]/ 17 P3[16]/D16/ PWM0[2]/RXD1 DTR1/TRACEPKT0/ PWM0[1]/TXD1 LCDLP Row G 1 P3[5]/D5 2 P0[24]/AD0[1]/ 3 V 4 V DD(3V3) DDA I2SRX_WS/CAP3[1] 14 n.c. 15 P4[27]/BLS1 16 P2[7]/RD2/ 17 P4[10]/A10 RTS1/TRACEPKT2/ LCDVD[1]/LCDVD[5] Row H 1 P0[23]/AD0[0]/ 2 P3[14]/D14 3 P3[30]/D30/ 4 V DD(DCDC)(3V3) I2SRX_CLK/CAP3[0] MAT1[1]/RTS1 14 V 15 P2[8]/TD2/TXD2/ 16 P2[9]/ 17 P4[9]/A9 SSIO TRACEPKT3/ USB_CONNECT1/ LCDVD[2]/LCDVD[6] RXD2/EXTIN0/ LCDVD[3]/LCDVD[7] Row J 1 P3[6]/D6 2 V 3 P3[31]/D31/MAT1[2] 4 n.c. SSA 14 P0[16]/RXD1/ 15 P4[23]/A23/ 16 P0[15]/TXD1/ 17 P4[8]/A8 SSEL0/SSEL RXD2/MOSI1 SCK0/SCK Row K 1 VREF 2 RTCX1 3 RSTOUT 4 V SSCORE 14 P4[22]/A22/ 15 P0[18]/DCD1/ 16 V 17 P0[17]/CTS1/ DD(3V3) TXD2/MISO1 MOSI0/MOSI MISO0/MISO Row L 1 P3[7]/D7 2 RTCX2 3 V 4 P2[30]/DQMOUT2/ SSIO MAT3[2]/SDA2 14 n.c. 15 P4[26]/BLS0 16 P4[7]/A7 17 P0[19]/DSR1/ MCICLK/SDA1 Row M 1 P3[15]/D15 2 RESET 3 VBAT 4 XTAL1 14 P4[6]/A6 15 P4[21]/A21/ 16 P0[21]/RI1/ 17 P0[20]/DTR1/ SCL2/SSEL1 MCIPWR/RD1 MCICMD/SCL1 Row N 1 ALARM 2 P2[31]/DQMOUT3/ 3 P2[29]/DQMOUT1 4 XTAL2 MAT3[3]/SCL2 14 P2[12]/EINT2/ 15 P2[10]/EINT0 16 V 17 P0[22]/RTS1/ SSIO LCDVD[4]/LCDVD[8]/ MCIDAT0/TD1 LCDVD[3]/LCDVD[18]/ MCIDAT2/I2STX_WS Row P 1 P1[31]/USB_OVRCR2/ 2 P1[30]/USB_PWRD2/ 3 P2[27]/CKEOUT3/ 4 P2[28]/DQMOUT0 SCK1/AD0[5] V /AD0[4] MAT3[1]/MOSI0 BUS 5 P2[24]/CKEOUT0 6 V 7 P1[18]/USB_UP_LED1/ 8 V DD(3V3) DD(3V3) PWM1[1]/CAP1[0] LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 8 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol 9 P1[23]/USB_RX_DP1/ 10 V 11 V 12 V SSCORE DD(DCDC)(3V3) SSIO LCDVD[9]/LCDVD[13]/ PWM1[4]/MISO0 13 P2[15]/CS3/ 14 P4[17]/A17 15 P4[18]/A18 16 P4[19]/A19 CAP2[1]/SCL1 17 V - - - DD(3V3) Row R 1 P0[12]/USB_PPWR2/ 2 P0[13]/USB_UP_LED2/ 3 P0[28]/SCL0 4 P2[25]/CKEOUT1 MISO1/AD0[6] MOSI1/AD0[7] 5 P3[24]/D24/ 6 P0[30]/USB_D1 7 P2[19]/CLKOUT1 8 P1[21]/USB_TX_DM1/ CAP0[1]/PWM1[1] LCDVD[7]/LCDVD[11]/ PWM1[3]/SSEL0 9 V 10 P1[26]/USB_SSPND1/ 11 P2[16]/CAS 12 P2[14]/CS2/CAP2[0]/ SSIO LCDVD[12]/LCDVD[20]/ SDA1 PWM1[6]/CAP0[0] 13 P2[17]/RAS 14 P0[11]/RXD2/SCL2/ 15 P4[4]/A4 16 P4[5]/A5 MAT3[1] 17 P4[20]/A20/SDA2/SCK1 - - - Row T 1 P0[27]/SDA0 2 P0[31]/USB_D+2 3 P3[26]/D26/ 4 P2[26]/CKEOUT2/ MAT0[1]/PWM1[3] MAT3[0]/MISO0 5 V 6 P3[23]/D23/ 7 P0[14]/USB_HSTEN2/ 8 P2[20]/DYCS0 SSIO CAP0[0]/PCAP1[0] USB_CONNECT2/ SSEL1 9 P1[24]/USB_RX_DM1/ 10 P1[25]/USB_LS1/ 11 P4[2]/A2 12 P1[27]/USB_INT1/ LCDVD[10]/LCDVD[14]/ LCDVD[11]/LCDVD[15]/ LCDVD[13]/LCDVD[21]/ PWM1[5]/MOSI0 USB_HSTEN1/MAT1[1] USB_OVRCR1/CAP0[1] 13 P1[28]/USB_SCL1/ 14 P0[1]/TD1/RXD3/SCL1 15 P0[10]/TXD2/SDA2/ 16 P2[13]/EINT3/ LCDVD[14]/LCDVD[22]/ MAT3[0] LCDVD[5]/LCDVD[9]/ PCAP1[0]/MAT0[0] LCDVD[19]/MCIDAT3/ I2STX_SDA 17 P2[11]/EINT1/ - - - LCDCLKIN/ MCIDAT1/I2STX_CLK Row U 1 USB_D2 2 P3[25]/D25/ 3 P2[18]/CLKOUT0 4 P0[29]/USB_D+1 MAT0[0]/PWM1[2] 5 P2[23]/DYCS3/ 6 P1[19]/USB_TX_E1/ 7 P1[20]/USB_TX_DP1/ 8 P1[22]/USB_RCV1/ CAP3[1]/SSEL0 USB_PPWR1/CAP1[1] LCDVD[6]/LCDVD[10]/ LCDVD[8]/LCDVD[12]/ PWM1[2]/SCK0 USB_PWRD1/MAT1[0] 9 P4[0]/A0 10 P4[1]/A1 11 P2[21]/DYCS1 12 P2[22]/DYCS2/ CAP3[0]/SCK0 13 V 14 P1[29]/USB_SDA1/ 15 P0[0]/RD1/TXD3/SDA1 16 P4[3]/A3 DD(3V3) LCDVD[15]/LCDVD[23]/ PCAP1[1]/MAT0[1] 17 P4[16]/A16 - - - LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 9 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 6.2 Pin description Table 4. Pin descripti on Symbol Pin Ball Type Description P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. P0[0]/RD1/TXD3/ 94[1] U15[1] I/O P0[0] — General purpose digital input/output pin. SDA1 I RD1 — CAN1 receiver input. O TXD3 — Transmitter output for UART3. I/O SDA1 — I2C1 data input/output (this is not an open-drain pin). P0[1]/TD1/RXD3/ 96[1] T14[1] I/O P0[1] — General purpose digital input/output pin. SCL1 O TD1 — CAN1 transmitter output. I RXD3 — Receiver input for UART3. I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin). P0[2]/TXD0 202[1] C4[1] I/O P0[2] — General purpose digital input/output pin. O TXD0 — Transmitter output for UART0. P0[3]/RXD0 204[1] D6[1] I/O P0[3] — General purpose digital input/output pin. I RXD0 — Receiver input for UART0. P0[4]/I2SRX_CLK/ 168[1] B12[1] I/O P0[4] — General purpose digital input/output pin. LCDVD[0]/RD2/ I/O I2SRX_CLK — I2S Receive clock. It is driven by the master and received CAP2[0] by the slave. Corresponds to the signal SCK in the I2S-bus specification.[17] O LCDVD[0] — LCD data.[17] I RD2 — CAN2 receiver input. I CAP2[0] — Capture input for Timer2, channel 0. P0[5]/I2SRX_WS/ 166[1] C12[1] I/O P0[5] — General purpose digital input/output pin. LCDVD[1]/TD2/ I/O I2SRX_WS — I2S Receive word select. It is driven by the master and CAP2[1] received by the slave. Corresponds to the signal WS in the I2S-bus specification.[17] O LCDVD[1] — LCD data.[17] O TD2 — CAN2 transmitter output. I CAP2[1] — Capture input for Timer2, channel 1. P0[6]/I2SRX_SDA/ 164[1] D13[1] I/O P0[6] — General purpose digital input/output pin. LCDVD[8]/ I/O I2SRX_SDA — I2S Receive data. It is driven by the transmitter and read SSEL1/MAT2[0] by the receiver. Corresponds to the signal SD in the I2S-bus specification.[17] O LCDVD[8] — LCD data.[17] I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer2, channel 0. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 10 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P0[7]/I2STX_CLK/ 162[1] C13[1] I/O P0[7] — General purpose digital input/output pin. LCDVD[9]/SCK1/ I/O I2STX_CLK — I2S transmit clock. It is driven by the master and received MAT2[1] by the slave. Corresponds to the signal SCK in the I2S-bus specification.[17] O LCDVD[9] — LCD data.[17] I/O SCK1 — Serial Clock for SSP1. O MAT2[1] — Match output for Timer2, channel 1. P0[8]/I2STX_WS/ 160[1] A15[1] I/O P0[8] — General purpose digital input/output pin. LCDVD[16]/ I/O I2STX_WS — I2S Transmit word select. It is driven by the master and MISO1/MAT2[2] received by the slave. Corresponds to the signal WS in the I2S-bus specification.[17] O LCDVD[16] — LCD data.[17] I/O MISO1 — Master In Slave Out for SSP1. O MAT2[2] — Match output for Timer2, channel 2. P0[9]/I2STX_SDA/ 158[1] C14[1] I/O P0[9] — General purpose digital input/output pin. LCDVD[17]/ I/O I2STX_SDA — I2S transmit data. It is driven by the transmitter and read MOSI1/MAT2[3] by the receiver. Corresponds to the signal SD in the I2S-bus specification.[17] O LCDVD[17] — LCD data.[17] I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer2, channel 3. P0[10]/TXD2/ 98[1] T15[1] I/O P0[10] — General purpose digital input/output pin. SDA2/MAT3[0] O TXD2 — Transmitter output for UART2. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). O MAT3[0] — Match output for Timer3, channel 0. P0[11]/RXD2/ 100[1] R14[1] I/O P0[11] — General purpose digital input/output pin. SCL2/MAT3[1] I RXD2 — Receiver input for UART2. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer3, channel 1. P0[12]/ 41[2] R1[2] I/O P0[12] — General purpose digital input/output pin. USB_PPWR2/ O USB_PPWR2 — Port Power enable signal for USB port 2. MISO1/AD0[6] I/O MISO1 — Master In Slave Out for SSP1. I AD0[6] — A/D converter 0, input 6. P0[13]/ 45[2] R2[2] I/O P0[13] — General purpose digital input/output pin. USB_UP_LED2/ O USB_UP_LED2 — USB port 2 GoodLink LED indicator. It is LOW when MOSI1/AD0[7] device is configured (non-control endpoints enabled), or when host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when host is enabled and detects activity on the bus. I/O MOSI1 — Master Out Slave In for SSP1. I AD0[7] — A/D converter 0, input 7. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 11 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P0[14]/ 69[1] T7[1] I/O P0[14] — General purpose digital input/output pin. USB_HSTEN2/ O USB_HSTEN2 — Host Enabled status for USB port 2. USB_CONNECT2/ SSEL1 O USB_CONNECT2 — SoftConnect control for USB port 2. Signal used to switch an external 1.5k resistor under software control. Used with the SoftConnect USB feature. I/O SSEL1 — Slave Select for SSP1. P0[15]/TXD1/ 128[1] J16[1] I/O P0[15] — General purpose digital input/output pin. SCK0/SCK O TXD1 — Transmitter output for UART1. I/O SCK0 — Serial clock for SSP0. I/O SCK — Serial clock for SPI. P0[16]/RXD1/ 130[1] J14[1] I/O P0 [16] — General purpose digital input/output pin. SSEL0/SSEL I RXD1 — Receiver input for UART1. I/O SSEL0 — Slave Select for SSP0. I/O SSEL — Slave Select for SPI. P0[17]/CTS1/ 126[1] K17[1] I/O P0[17] — General purpose digital input/output pin. MISO0/MISO I CTS1 — Clear to Send input for UART1. I/O MISO0 — Master In Slave Out for SSP0. I/O MISO — Master In Slave Out for SPI. P0[18]/DCD1/ 124[1] K15[1] I/O P0[18] — General purpose digital input/output pin. MOSI0/MOSI I DCD1 — Data Carrier Detect input for UART1. I/O MOSI0 — Master Out Slave In for SSP0. I/O MOSI — Master Out Slave In for SPI. P0[19]/DSR1/ 122[1] L17[1] I/O P0[19] — General purpose digital input/output pin. MCICLK/SDA1 I DSR1 — Data Set Ready input for UART1. O MCICLK — Clock output line for SD/MMC interface. I/O SDA1 — I2C1 data input/output (this is not an open-drain pin). P0[20]/DTR1/ 120[1] M17[1] I/O P0[20] — General purpose digital input/output pin. MCICMD/SCL1 O DTR1 — Data Terminal Ready output for UART1. I/O MCICMD — Command line for SD/MMC interface. I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin). P0[21]/RI1/ 118[1] M16[1] I/O P0[21] — General purpose digital input/output pin. MCIPWR/RD1 I RI1 — Ring Indicator input for UART1. O MCIPWR — Power Supply Enable for external SD/MMC power supply. I RD1 — CAN1 receiver input. P0[22]/RTS1/ 116[1] N17[1] I/O P0[22] — General purpose digital input/output pin. MCIDAT0/TD1 O RTS1 — Request to Send output for UART1. I/O MCIDAT0 — Data line 0 for SD/MMC interface. O TD1 — CAN1 transmitter output. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 12 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P0[23]/AD0[0]/ 18[2] H1[2] I/O P0[23] — General purpose digital input/output pin. I2SRX_CLK/ I AD0[0] — A/D converter 0, input 0. CAP3[0] I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I CAP3[0] — Capture input for Timer3, channel 0. P0[24]/AD0[1]/ 16[2] G2[2] I/O P0[24] — General purpose digital input/output pin. I2SRX_WS/ I AD0[1] — A/D converter 0, input 1. CAP3[1] I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I CAP3[1] — Capture input for Timer3, channel 1. P0[25]/AD0[2]/ 14[2] F1[2] I/O P0[25] — General purpose digital input/output pin. I2SRX_SDA/ I AD0[2] — A/D converter 0, input 2. TXD3 I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. O TXD3 — Transmitter output for UART3. P0[26]/AD0[3]/ 12[2][3] E1[2][3] I/O P0[26] — General purpose digital input/output pin. AOUT/RXD3 I AD0[3] — A/D converter 0, input 3. O AOUT — D/A converter output. I RXD3 — Receiver input for UART3. P0[27]/SDA0 50[4] T1[4] I/O P0[27] — General purpose digital input/output pin. Output is open-drain. I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance). P0[28]/SCL0 48[4] R3[4] I/O P0[28] — General purpose digital input/output pin. Output is open-drain. I/O SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance). P0[29]/USB_D+1 61[5] U4[5] I/O P0[29] — General purpose digital input/output pin. I/O USB_D+1 — USB port 1 bidirectional D+ line. P0[30]/USB_D1 62[5] R6[5] I/O P0[30] — General purpose digital input/output pin. I/O USB_D1 — USB port 1 bidirectional D line. P0[31]/USB_D+2 51[5] T2[5] I/O P0[31] — General purpose digital input/output pin. I/O USB_D+2 — USB port 2 bidirectional D+ line. P1[0] to P1[31] I/O Port 1: Port 1 is a 32bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. P1[0]/ 196[1] A3[1] I/O P1[0] — General purpose digital input/output pin. ENET_TXD0 O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface). P1[1]/ 194[1] B5[1] I/O P1[1] — General purpose digital input/output pin. ENET_TXD1 O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface). P1[2]/ 185[1] D9[1] I/O P1[2] — General purpose digital input/output pin. ENET_TXD2/ O ENET_TXD2 — Ethernet transmit data 2 (MII interface). MCICLK/ O MCICLK — Clock output line for SD/MMC interface. PWM0[1] O PWM0[1] — Pulse Width Modulator 0, output 1. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 13 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P1[3]/ 177[1] A10[1] I/O P1[3] — General purpose digital input/output pin. ENET_TXD3/ O ENET_TXD3 — Ethernet transmit data 3 (MII interface). MCICMD/ PWM0[2] I/O MCICMD — Command line for SD/MMC interface. O PWM0[2] — Pulse Width Modulator 0, output 2. P1[4]/ 192[1] A5[1] I/O P1[4] — General purpose digital input/output pin. ENET_TX_EN O ENET_TX_EN — Ethernet transmit data enable (RMII/MII interface). P1[5]/ 156[1] A17[1] I/O P1[5] — General purpose digital input/output pin. ENET_TX_ER/ O ENET_TX_ER — Ethernet Transmit Error (MII interface). MCIPWR/ O MCIPWR — Power Supply Enable for external SD/MMC power supply. PWM0[3] O PWM0[3] — Pulse Width Modulator 0, output 3. P1[6]/ 171[1] B11[1] I/O P1[6] — General purpose digital input/output pin. ENET_TX_CLK/ I ENET_TX_CLK — Ethernet Transmit Clock (MII interface). MCIDAT0/ I/O MCIDAT0 — Data line 0 for SD/MMC interface. PWM0[4] O PWM0[4] — Pulse Width Modulator 0, output 4. P1[7]/ 153[1] D14[1] I/O P1[7] — General purpose digital input/output pin. ENET_COL/ I ENET_COL — Ethernet Collision detect (MII interface). MCIDAT1/ I/O MCIDAT1 — Data line 1 for SD/MMC interface. PWM0[5] O PWM0[5] — Pulse Width Modulator 0, output 5. P1[8]/ 190[1] C7[1] I/O P1[8] — General purpose digital input/output pin. ENET_CRS_DV/ I ENET_CRS_DV/ENET_CRS — Ethernet Carrier Sense/Data Valid (RMII ENET_CRS interface)/ Ethernet Carrier Sense (MII interface). P1[9]/ 188[1] A6[1] I/O P1[9] — General purpose digital input/output pin. ENET_RXD0 I ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface). P1[10]/ 186[1] C8[1] I/O P1[10] — General purpose digital input/output pin. ENET_RXD1 I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface). P1[11]/ 163[1] A14[1] I/O P1[11] — General purpose digital input/output pin. ENET_RXD2/ I ENET_RXD2 — Ethernet Receive Data 2 (MII interface). MCIDAT2/ I/O MCIDAT2 — Data line 2 for SD/MMC interface. PWM0[6] O PWM0[6] — Pulse Width Modulator 0, output 6. P1[12]/ 157[1] A16[1] I/O P1[12] — General purpose digital input/output pin. ENET_RXD3/ I ENET_RXD3 — Ethernet Receive Data (MII interface). MCIDAT3/ I/O MCIDAT3 — Data line 3 for SD/MMC interface. PCAP0[0] I PCAP0[0] — Capture input for PWM0, channel 0. P1[13]/ 147[1] D16[1] I/O P1[13] — General purpose digital input/output pin. ENET_RX_DV I ENET_RX_DV — Ethernet Receive Data Valid (MII interface). P1[14]/ 184[1] A7[1] I/O P1[14] — General purpose digital input/output pin. ENET_RX_ER I ENET_RX_ER — Ethernet receive error (RMII/MII interface). P1[15]/ 182[1] A8[1] I/O P1[15] — General purpose digital input/output pin. ENET_REF_CLK/ I ENET_REF_CLK/ENET_RX_CLK — Ethernet Reference Clock (RMII ENET_RX_CLK interface)/ Ethernet Receive Clock (MII interface). LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 14 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P1[16]/ 180[1] D10[1] I/O P1[16] — General purpose digital input/output pin. ENET_MDC O ENET_MDC — Ethernet MIIM clock. P1[17]/ 178[1] A9[1] I/O P1[17] — General purpose digital input/output pin. ENET_MDIO I/O ENET_MDIO — Ethernet MIIM data input and output. P1[18]/ 66[1] P7[1] I/O P1[18] — General purpose digital input/output pin. USB_UP_LED1/ O USB_UP_LED1 — USB port 1 GoodLink LED indicator. It is LOW when PWM1[1]/CAP1[0] device is configured (non-control endpoints enabled), or when host is enabled and has detected a device on the bus. It is HIGH when the device is not configured or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when host is enabled and detects activity on the bus. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I CAP1[0] — Capture input for Timer1, channel 0. P1[19]/ 68[1] U6[1] I/O P1[19] — General purpose digital input/output pin. USB_TX_E1/ O USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG USB_PPWR1/ transceiver). CAP1[1] O USB_PPWR1 — Port Power enable signal for USB port 1. I CAP1[1] — Capture input for Timer1, channel 1. P1[20]/ 70[1] U7[1] I/O P1[20] — General purpose digital input/output pin. USB_TX_DP1/ O USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver).[18] LCDVD[6]/ O LCDVD[6]/LCDVD[10] — LCD data.[18] LCDVD[10]/ PWM1[2]/SCK0 O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I/O SCK0 — Serial clock for SSP0. P1[21]/ 72[1] R8[1] I/O P1[21] — General purpose digital input/output pin. USB_TX_DM1/ O USB_TX_DM1 — D transmit data for USB port 1 (OTG transceiver).[18] LCDVD[7]/ O LCDVD[7]/LCDVD[11] — LCD data.[18] LCDVD[11]/ PWM1[3]/SSEL0 O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I/O SSEL0 — Slave Select for SSP0. P1[22]/USB_RCV1/ 74[1] U8[1] I/O P1[22] — General purpose digital input/output pin. LCDVD[8]/ I USB_RCV1 — Differential receive data for USB port 1 (OTG LCDVD[12]/ transceiver).[18] USB_PWRD1/ O LCDVD[8]/LCDVD[12] — LCD data.[18] MAT1[0] I USB_PWRD1 — Power Status for USB port 1 (host power switch). O MAT1[0] — Match output for Timer1, channel 0. P1[23]/ 76[1] P9[1] I/O P1[23] — General purpose digital input/output pin. USB_RX_DP1/ I USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver).[18] LCDVD[9]/ O LCDVD[9]/LCDVD[13] — LCD data.[18] LCDVD[13]/ PWM1[4]/MISO0 O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 15 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P1[24]/ 78[1] T9[1] I/O P1[24] — General purpose digital input/output pin. USB_RX_DM1/ I USB_RX_DM1 — D receive data for USB port 1 (OTG transceiver).[18] LCDVD[10]/ O LCDVD[10]/LCDVD[14] — LCD data.[18] LCDVD[14]/ PWM1[5]/MOSI0 O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I/O MOSI0 — Master Out Slave in for SSP0. P1[25]/USB_LS1/ 80[1] T10[1] I/O P1[25] — General purpose digital input/output pin. LCDVD[11]/ O USB_LS1 — Low Speed status for USB port 1 (OTG transceiver).[18] LCDVD[15]/ USB_HSTEN1/ O LCDVD[11]/LCDVD[15] — LCD data.[18] MAT1[1] O USB_HSTEN1 — Host Enabled status for USB port 1. O MAT1[1] — Match output for Timer1, channel 1. P1[26]/ 82[1] R10[1] I/O P1[26] — General purpose digital input/output pin. USB_SSPND1/ O USB_SSPND1 — USB port 1 Bus Suspend status (OTG transceiver).[18] LCDVD[12]/ LCDVD[20]/ O LCDVD[12]/LCDVD[20] — LCD data.[18] PWM1[6]/CAP0[0] O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I CAP0[0] — Capture input for Timer0, channel 0. P1[27]/USB_INT1/ 88[1] T12[1] I/O P1[27] — General purpose digital input/output pin. LCDVD[13]/ I USB_INT1 — USB port 1 OTG transceiver interrupt (OTG LCDVD[21]/ transceiver).[18] USB_OVRCR1/ O LCDVD[13]/LCDVD[21] — LCD data.[18] CAP0[1] I USB_OVRCR1 — USB port 1 Over-Current status. I CAP0[1] — Capture input for Timer0, channel 1. P1[28]/USB_SCL1/ 90[1] T13[1] I/O P1[28] — General purpose digital input/output pin. LCDVD[14]/ I/O USB_SCL1 — USB port 1 I2C-bus serial clock (OTG transceiver).[18] LCDVD[22]/ O LCDVD[14]/LCDVD[22] — LCD data.[18] PCAP1[0]/MAT0[0] I PCAP1[0] — Capture input for PWM1, channel 0. O MAT0[0] — Match output for Timer0, channel 0. P1[29]/USB_SDA1/ 92[1] U14[1] I/O P1[29] — General purpose digital input/output pin. LCDVD[15]/ I/O USB_SDA1 — USB port 1 I2C-bus serial data (OTG transceiver).[18] LCDVD[23]/ O LCDVD[15]/LCDVD[23] — LCD data.[18] PCAP1[1]/MAT0[1] I PCAP1[1] — Capture input for PWM1, channel 1. O MAT0[1] — Match output for Timer0, channel 0. P1[30]/ 42[2] P2[2] I/O P1[30] — General purpose digital input/output pin. USB_PWRD2/ I USB_PWRD2 — Power Status for USB port 2. V /AD0[4] BUS I V — Monitors the presence of USB bus power. BUS Note: This signal must be HIGH for USB reset to occur. I AD0[4] — A/D converter 0, input 4. P1[31]/ 40[2] P1[2] I/O P1[31] — General purpose digital input/output pin. USB_OVRCR2/ I USB_OVRCR2 — Over-Current status for USB port 2. SCK1/AD0[5] I/O SCK1 — Serial Clock for SSP1. I AD0[5] — A/D converter 0, input 5. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 16 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 17 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P2[0]/PWM1[1]/ 154[1] B17[1] I/O P2[0] — General purpose digital input/output pin. TXD1/TRACECLK/ O PWM1[1] — Pulse Width Modulator 1, channel 1 output. LCDPWR O TXD1 — Transmitter output for UART1. O TRACECLK — Trace clock.[19] O LCDPWR — LCD panel power enable.[19] P2[1]/PWM1[2]/ 152[1] E14[1] I/O P2[1] — General purpose digital input/output pin. RXD1/PIPESTAT0/ O PWM1[2] — Pulse Width Modulator 1, channel 2 output. LCDLE I RXD1 — Receiver input for UART1. O PIPESTAT0 — Pipeline status, bit 0.[19] O LCDLE — Line end signal.[19] P2[2]/PWM1[3]/ 150[1] D15[1] I/O P2[2] — General purpose digital input/output pin. CTS1/PIPESTAT1/ O PWM1[3] — Pulse Width Modulator 1, channel 3 output. LCDDCLK I CTS1 — Clear to Send input for UART1. O PIPESTAT1 — Pipeline status, bit 1.[19] O LCDDCLK — LCD panel clock.[19] P2[3]/PWM1[4]/ 144[1] E16[1] I/O P2[3] — General purpose digital input/output pin. DCD1/PIPESTAT2/ O PWM1[4] — Pulse Width Modulator 1, channel 4 output. LCDFP I DCD1 — Data Carrier Detect input for UART1. O PIPESTAT2 — Pipeline status, bit 2.[19] O LCDFP — Frame pulse (STN). Vertical synchronization pulse (TFT).[19] P2[4]/PWM1[5]/ 142[1] D17[1] I/O P2[4] — General purpose digital input/output pin. DSR1/ O PWM1[5] — Pulse Width Modulator 1, channel 5 output. TRACESYNC/ LCDENAB/LCDM I DSR1 — Data Set Ready input for UART1. O TRACESYNC — Trace Synchronization.[19] O LCDENAB/LCDM — STN AC bias drive or TFT data enable output.[19] P2[5]/PWM1[6]/ 140[1] F16[1] I/O P2[5] — General purpose digital input/output pin. DTR1/ O PWM1[6] — Pulse Width Modulator 1, channel 6 output. TRACEPKT0/ LCDLP O DTR1 — Data Terminal Ready output for UART1. O TRACEPKT0 — Trace Packet, bit 0.[19] O LCDLP — Line synchronization pulse (STN). Horizontal synchronization pulse (TFT).[19] P2[6]/PCAP1[0]/ 138[1] E17[1] I/O P2[6] — General purpose digital input/output pin. RI1/ I PCAP1[0] — Capture input for PWM1, channel 0. TRACEPKT1/ LCDVD[0]/ I RI1 — Ring Indicator input for UART1. LCDVD[4] O TRACEPKT1 — Trace Packet, bit 1.[19] O LCDVD[0]/LCDVD[4] — LCD data.[19] P2[7]/RD2/ 136[1] G16[1] I/O P2[7] — General purpose digital input/output pin. RTS1/ I RD2 — CAN2 receiver input. TRACEPKT2/ LCDVD[1]/ O RTS1 — Request to Send output for UART1. LCDVD[5] O TRACEPKT2 — Trace Packet, bit 2.[19] O LCDVD[1]/LCDVD[5] — LCD data.[19] LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 18 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P2[8]/TD2/TXD2/ 134[1] H15[1] I/O P2[8] — General purpose digital input/output pin. TRACEPKT3/ O TD2 — CAN2 transmitter output. LCDVD[2]/ LCDVD[6] O TXD2 — Transmitter output for UART2. O TRACEPKT3 — Trace packet, bit 3.[19] O LCDVD[2]/LCDVD[6] — LCD data.[19] P2[9]/ 132[1] H16[1] I/O P2[9] — General purpose digital input/output pin. USB_CONNECT1/ O USB_CONNECT1 — USB1 SoftConnect control. Signal used to switch RXD2/EXTIN0/ an external 1.5k resistor under the software control. Used with the LCDVD[3]/ SoftConnect USB feature. LCDVD[7] I RXD2 — Receiver input for UART2. I EXTIN0 — External Trigger Input.[19] O LCDVD[3]/LCDVD[7] — LCD data.[19] P2[10]/EINT0 110[6] N15[6] I/O P2[10] — General purpose digital input/output pin. Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take over control of the part after a reset. I EINT0 — External interrupt 0 input. P2[11]/EINT1/ 108[6] T17[6] I/O P2[11] — General purpose digital input/output pin. LCDCLKIN/ I EINT1 — External interrupt 1 input.[20] MCIDAT1/ O LCDCLKIN — LCD clock.[20] I2STX_CLK I/O MCIDAT1 — Data line 1 for SD/MMC interface. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. P2[12]/EINT2/ 106[6] N14[6] I/O P2[12] — General purpose digital input/output pin. LCDVD[4]/ I EINT2 — External interrupt 2 input.[20] LCDVD[3]/ O LCDVD[4]/LCDVD[3]/LCDVD[8]/LCDVD[18] — LCD data.[20] LCDVD[8]/ LCDVD[18]/ I/O MCIDAT2 — Data line 2 for SD/MMC interface. MCIDAT2/ I/O I2STX_WS — Transmit Word Select. It is driven by the master and I2STX_WS received by the slave. Corresponds to the signal WS in the I2S-bus specification. P2[13]/EINT3/ 102[6] T16[6] I/O P2[13] — General purpose digital input/output pin. LCDVD[5]/ I EINT3 — External interrupt 3 input.[20] LCDVD[9]/ O LCDVD[5]/LCDVD[9]/LCDVD[19] — LCD data.[20] LCDVD[19]/ MCIDAT3/ I/O MCIDAT3 — Data line 3 for SD/MMC interface. I2STX_SDA I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. P2[14]/CS2/ 91[6] R12[6] I/O P2[14] — General purpose digital input/output pin. CAP2[0]/SDA1 O CS2 — LOW active Chip Select 2 signal. I CAP2[0] — Capture input for Timer2, channel 0. I/O SDA1 — I2C1 data input/output (this is not an open-drain pin). P2[15]/CS3/ 99[6] P13[6] I/O P2[15] — General purpose digital input/output pin. CAP2[1]/SCL1 O CS3 — LOW active Chip Select 3 signal. I CAP2[1] — Capture input for Timer2, channel 1. I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin). LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 19 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P2[16]/CAS 87[1] R11[1] I/O P2[16] — General purpose digital input/output pin. O CAS — LOW active SDRAM Column Address Strobe. P2[17]/RAS 95[1] R13[1] I/O P2[17] — General purpose digital input/output pin. O RAS — LOW active SDRAM Row Address Strobe. P2[18]/ 59[1] U3[1] I/O P2[18] — General purpose digital input/output pin. CLKOUT0 O CLKOUT0 — SDRAM clock 0. P2[19]/ 67[1] R7[1] I/O P2[19] — General purpose digital input/output pin. CLKOUT1 O CLKOUT1 — SDRAM clock 1. P2[20]/DYCS0 73[1] T8[1] I/O P2[20] — General purpose digital input/output pin. O DYCS0 — SDRAM chip select 0. P2[21]/DYCS1 81[1] U11[1] I/O P2[21] — General purpose digital input/output pin. O DYCS1 — SDRAM chip select 1. P2[22]/DYCS2/ 85[1] U12[1] I/O P2[22] — General purpose digital input/output pin. CAP3[0]/SCK0 O DYCS2 — SDRAM chip select 2. I CAP3[0] — Capture input for Timer3, channel 0. I/O SCK0 — Serial clock for SSP0. P2[23]/DYCS3/ 64[1] U5[1] I/O P2[23] — General purpose digital input/output pin. CAP3[1]/SSEL0 O DYCS3 — SDRAM chip select 3. I CAP3[1] — Capture input for Timer3, channel 1. I/O SSEL0 — Slave Select for SSP0. P2[24]/ 53[1] P5[1] I/O P2[24] — General purpose digital input/output pin. CKEOUT0 O CKEOUT0 — SDRAM clock enable 0. P2[25]/ 54[1] R4[1] I/O P2[25] — General purpose digital input/output pin. CKEOUT1 O CKEOUT1 — SDRAM clock enable 1. P2[26]/ 57[1] T4[1] I/O P2[26] — General purpose digital input/output pin. CKEOUT2/ O CKEOUT2 — SDRAM clock enable 2. MAT3[0]/MISO0 O MAT3[0] — Match output for Timer3, channel 0. I/O MISO0 — Master In Slave Out for SSP0. P2[27]/ 47[1] P3[1] I/O P2[27] — General purpose digital input/output pin. CKEOUT3/ O CKEOUT3 — SDRAM clock enable 3. MAT3[1]/MOSI0 O MAT3[1] — Match output for Timer3, channel 1. I/O MOSI0 — Master Out Slave In for SSP0. P2[28]/ 49[1] P4[1] I/O P2[28] — General purpose digital input/output pin. DQMOUT0 O DQMOUT0 — Data mask 0 used with SDRAM and static devices. P2[29]/ 43[1] N3[1] I/O P2[29] — General purpose digital input/output pin. DQMOUT1 O DQMOUT1 — Data mask 1 used with SDRAM and static devices. P2[30]/ 31[1] L4[1] I/O P2[30] — General purpose digital input/output pin. DQMOUT2/ O DQMOUT2 — Data mask 2 used with SDRAM and static devices. MAT3[2]/SDA2 O MAT3[2] — Match output for Timer3, channel 2. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 20 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P2[31]/ 39[1] N2[1] I/O P2[31] — General purpose digital input/output pin. DQMOUT3/ O DQMOUT3 — Data mask 3 used with SDRAM and static devices. MAT3[3]/SCL2 O MAT3[3] — Match output for Timer3, channel 3. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. P3[0]/D0 197[1] B4[1] I/O P3[0] — General purpose digital input/output pin. I/O D0 — External memory data line 0. P3[1]/D1 201[1] B3[1] I/O P3[1] — General purpose digital input/output pin. I/O D1 — External memory data line 1. P3[2]/D2 207[1] B1[1] I/O P3[2] — General purpose digital input/output pin. I/O D2 — External memory data line 2. P3[3]/D3 3[1] E4[1] I/O P3[3] — General purpose digital input/output pin. I/O D3 — External memory data line 3. P3[4]/D4 13[1] F2[1] I/O P3[4] — General purpose digital input/output pin. I/O D4 — External memory data line 4. P3[5]/D5 17[1] G1[1] I/O P3[5] — General purpose digital input/output pin. I/O D5 — External memory data line 5. P3[6]/D6 23[1] J1[1] I/O P3[6] — General purpose digital input/output pin. I/O D6 — External memory data line 6. P3[7]/D7 27[1] L1[1] I/O P3[7] — General purpose digital input/output pin. I/O D7 — External memory data line 7. P3[8]/D8 191[1] D8[1] I/O P3[8] — General purpose digital input/output pin. I/O D8 — External memory data line 8. P3[9]/D9 199[1] C5[1] I/O P3[9] — General purpose digital input/output pin. I/O D9 — External memory data line 9. P3[10]/D10 205[1] B2[1] I/O P3[10] — General purpose digital input/output pin. I/O D10 — External memory data line 10. P3[11]/D11 208[1] D5[1] I/O P3[11] — General purpose digital input/output pin. I/O D11 — External memory data line 11. P3[12]/D12 1[1] D4[1] I/O P3[12] — General purpose digital input/output pin. I/O D12 — External memory data line 12. P3[13]/D13 7[1] C1[1] I/O P3[13] — General purpose digital input/output pin. I/O D13 — External memory data line 13. P3[14]/D14 21[1] H2[1] I/O P3[14] — General purpose digital input/output pin. I/O D14 — External memory data line 14. P3[15]/D15 28[1] M1[1] I/O P3[15] — General purpose digital input/output pin. I/O D15 — External memory data line 15. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 21 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P3[16]/D16/ 137[1] F17[1] I/O P3[16] — General purpose digital input/output pin. PWM0[1]/TXD1 I/O D16 — External memory data line 16. O PWM0[1] — Pulse Width Modulator 0, output 1. O TXD1 — Transmitter output for UART1. P3[17]/D17/ 143[1] F15[1] I/O P3[17] — General purpose digital input/output pin. PWM0[2]/RXD1 I/O D17 — External memory data line 17. O PWM0[2] — Pulse Width Modulator 0, output 2. I RXD1 — Receiver input for UART1. P3[18]/D18/ 151[1] C15[1] I/O P3[18] — General purpose digital input/output pin. PWM0[3]/CTS1 I/O D18 — External memory data line 18. O PWM0[3] — Pulse Width Modulator 0, output 3. I CTS1 — Clear to Send input for UART1. P3[19]/D19/ 161[1] B14[1] I/O P3[19] — General purpose digital input/output pin. PWM0[4]/DCD1 I/O D19 — External memory data line 19. O PWM0[4] — Pulse Width Modulator 0, output 4. I DCD1 — Data Carrier Detect input for UART1. P3[20]/D20/ 167[1] A13[1] I/O P3[20] — General purpose digital input/output pin. PWM0[5]/DSR1 I/O D20 — External memory data line 20. O PWM0[5] — Pulse Width Modulator 0, output 5. I DSR1 — Data Set Ready input for UART1. P3[21]/D21/ 175[1] C10[1] I/O P3[21] — General purpose digital input/output pin. PWM0[6]/DTR1 I/O D21 — External memory data line 21. O PWM0[6] — Pulse Width Modulator 0, output 6. O DTR1 — Data Terminal Ready output for UART1. P3[22]/D22/ 195[1] C6[1] I/O P3[22] — General purpose digital input/output pin. PCAP0[0]/RI1 I/O D22 — External memory data line 22. I PCAP0[0] — Capture input for PWM0, channel 0. I RI1 — Ring Indicator input for UART1. P3[23]/D23/ 65[1] T6[1] I/O P3[23] — General purpose digital input/output pin. CAP0[0]/ I/O D23 — External memory data line 23. PCAP1[0] I CAP0[0] — Capture input for Timer0, channel 0. I PCAP1[0] — Capture input for PWM1, channel 0. P3[24]/D24/ 58[1] R5[1] I/O P3[24] — General purpose digital input/output pin. CAP0[1]/ I/O D24 — External memory data line 24. PWM1[1] I CAP0[1] — Capture input for Timer0, channel 1. O PWM1[1] — Pulse Width Modulator 1, output 1. P3[25]/D25/ 56[1] U2[1] I/O P3[25] — General purpose digital input/output pin. MAT0[0]/ I/O D25 — External memory data line 25. PWM1[2] O MAT0[0] — Match output for Timer0, channel 0. O PWM1[2] — Pulse Width Modulator 1, output 2. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 22 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P3[26]/D26/ 55[1] T3[1] I/O P3[26] — General purpose digital input/output pin. MAT0[1]/ I/O D26 — External memory data line 26. PWM1[3] O MAT0[1] — Match output for Timer0, channel 1. O PWM1[3] — Pulse Width Modulator 1, output 3. P3[27]/D27/ 203[1] A1[1] I/O P3[27] — General purpose digital input/output pin. CAP1[0]/ I/O D27 — External memory data line 27. PWM1[4] I CAP1[0] — Capture input for Timer1, channel 0. O PWM1[4] — Pulse Width Modulator 1, output 4. P3[28]/D28/ 5[1] D2[1] I/O P3[28] — General purpose digital input/output pin. CAP1[1]/ I/O D28 — External memory data line 28. PWM1[5] I CAP1[1] — Capture input for Timer1, channel 1. O PWM1[5] — Pulse Width Modulator 1, output 5. P3[29]/D29/ 11[1] F3[1] I/O P3[29] — General purpose digital input/output pin. MAT1[0]/ I/O D29 — External memory data line 29. PWM1[6] O MAT1[0] — Match output for Timer1, channel 0. O PWM1[6] — Pulse Width Modulator 1, output 6. P3[30]/D30/ 19[1] H3[1] I/O P3[30] — General purpose digital input/output pin. MAT1[1]/ I/O D30 — External memory data line 30. RTS1 O MAT1[1] — Match output for Timer1, channel 1. O RTS1 — Request to Send output for UART1. P3[31]/D31/ 25[1] J3[1] I/O P3[31] — General purpose digital input/output pin. MAT1[2] I/O D31 — External memory data line 31. O MAT1[2] — Match output for Timer1, channel 2. P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. P4[0]/A0 75[1] U9[1] I/O P4[0] — General purpose digital input/output pin. I/O A0 — External memory address line 0. P4[1]/A1 79[1] U10[1] I/O P4[1] — General purpose digital input/output pin. I/O A1 — External memory address line 1. P4[2]/A2 83[1] T11[1] I/O P4[2] — General purpose digital input/output pin. I/O A2 — External memory address line 2. P4[3]/A3 97[1] U16[1] I/O P4[3] — General purpose digital input/output pin. I/O A3 — External memory address line 3. P4[4]/A4 103[1] R15[1] I/O P4[4] — General purpose digital input/output pin. I/O A4 — External memory address line 4. P4[5]/A5 107[1] R16[1] I/O P4[5] — General purpose digital input/output pin. I/O A5 — External memory address line 5. P4[6]/A6 113[1] M14[1] I/O P4[6] — General purpose digital input/output pin. I/O A6 — External memory address line 6. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 23 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P4[7]/A7 121[1] L16[1] I/O P4[7] — General purpose digital input/output pin. I/O A7 — External memory address line 7. P4[8]/A8 127[1] J17[1] I/O P4[8] — General purpose digital input/output pin. I/O A8 — External memory address line 8. P4[9]/A9 131[1] H17[1] I/O P4[9] — General purpose digital input/output pin. I/O A9 — External memory address line 9. P4[10]/A10 135[1] G17[1] I/O P4[10] — General purpose digital input/output pin. I/O A10 — External memory address line 10. P4[11]/A11 145[1] F14[1] I/O P4[11] — General purpose digital input/output pin. I/O A11 — External memory address line 11. P4[12]/A12 149[1] C16[1] I/O P4[12] — General purpose digital input/output pin. I/O A12 — External memory address line 12. P4[13]/A13 155[1] B16[1] I/O P4[13] — General purpose digital input/output pin. I/O A13 — External memory address line 13. P4[14]/A14 159[1] B15[1] I/O P4[14] — General purpose digital input/output pin. I/O A14 — External memory address line 14. P4[15]/A15 173[1] A11[1] I/O P4[15] — General purpose digital input/output pin. I/O A15 — External memory address line 15. P4[16]/A16 101[1] U17[1] I/O P4[16] — General purpose digital input/output pin. I/O A16 — External memory address line 16. P4[17]/A17 104[1] P14[1] I/O P4[17] — General purpose digital input/output pin. I/O A17 — External memory address line 17. P4[18]/A18 105[1] P15[1] I/O P4[18] — General purpose digital input/output pin. I/O A18 — External memory address line 18. P4[19]/A19 111[1] P16[1] I/O P4[19] — General purpose digital input/output pin. I/O A19 — External memory address line 19. P4[20]/A20/ 109[1] R17[1] I/O P4[20] — General purpose digital input/output pin. SDA2/SCK1 I/O A20 — External memory address line 20. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). I/O SCK1 — Serial Clock for SSP1. P4[21]/A21/ 115[1] M15[1] I/O P4[21] — General purpose digital input/output pin. SCL2/SSEL1 I/O A21 — External memory address line 21. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). I/O SSEL1 — Slave Select for SSP1. P4[22]/A22/ 123[1] K14[1] I/O P4[22] — General purpose digital input/output pin. TXD2/MISO1 I/O A22 — External memory address line 22. O TXD2 — Transmitter output for UART2. I/O MISO1 — Master In Slave Out for SSP1. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 24 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description P4[23]/A23/ 129[1] J15[1] I/O P4[23] — General purpose digital input/output pin. RXD2/MOSI1 I/O A23 — External memory address line 23. I RXD2 — Receiver input for UART2. I/O MOSI1 — Master Out Slave In for SSP1. P4[24]/OE 183[1] B8[1] I/O P4[24] — General purpose digital input/output pin. O OE — LOW active Output Enable signal. P4[25]/WE 179[1] B9[1] I/O P4[25] — General purpose digital input/output pin. O WE — LOW active Write Enable signal. P4[26]/BLS0 119[1] L15[1] I/O P4[26] — General purpose digital input/output pin. O BLS0 — LOW active Byte Lane select signal 0. P4[27]/BLS1 139[1] G15[1] I/O P4[27] — General purpose digital input/output pin. O BLS1 — LOW active Byte Lane select signal 1. P4[28]/BLS2/ 170[1] C11[1] I/O P4 [28] — General purpose digital input/output pin. MAT2[0]/LCDVD[6]/ O BLS2 — LOW active Byte Lane select signal 2. LCDVD[10]/ O MAT2[0] — Match output for Timer 2, channel 0.[21] LCDVD[2]/ TXD3 O LCDVD[6]/LCDVD[10]/LCDVD[2] — LCD data.[21] O TXD3 — Transmitter output for UART3. P4[29]/BLS3/ 176[1] B10[1] I/O P4[29] — General purpose digital input/output pin. MAT2[1] O BLS3 — LOW active Byte Lane select signal 3. LCDVD[7]/ O MAT2[1] — Match output for Timer 2, channel 1.[21] LCDVD[11]/ LCDVD[3]/RXD3 O LCDVD[7]/LCDVD[11]/LCDVD[3] — LCD data.[21] I RXD3 — Receiver input for UART3. P4[30]/CS0 187[1] B7[1] I/O P4[30] — General purpose digital input/output pin. O CS0 — LOW active Chip Select 0 signal. P4[31]/CS1 193[1] A4[1] I/O P4[31] — General purpose digital input/output pin. O CS1 — LOW active Chip Select 1 signal. ALARM 37[8] N1[8] O ALARM — RTC controlled output. This is a 1.8V pin. It goes HIGH when a RTC alarm is generated. USB_D2 52 U1 I/O USB_D2 — USB port 2 bidirectional D line. DBGEN 9[1][22] F4[1][22] I DBGEN — JTAG interface control signal. Also used for boundary scanning. TDO 2[1][23] D3[1][23] O TDO — Test Data Out for JTAG interface. TDI 4[1][22] C2[1][22] I TDI — Test Data In for JTAG interface. TMS 6[1][22] E3[1][22] I TMS — Test Mode Select for JTAG interface. TRST 8[1][22] D1[1][22] I TRST — Test Reset for JTAG interface. TCK 10[1][23] E2[1][23] I TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄ 6 of the CPU clock (CCLK) for the JTAG interface to operate. RTCK 206[1][22] C3[1][22] I/O RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset. RSTOUT 29 K3 O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2478 being in Reset state. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 25 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 4. Pin description …continued Symbol Pin Ball Type Description RESET 35[7] M2[7] I external reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5V tolerant. XTAL1 44[8][9] M4[8][9] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 46[8][9] N4[8][9] O Output from the oscillator amplifier. RTCX1 34[8][10] K2[8][10] I Input to the RTC oscillator circuit. RTCX2 36[8][10] L2[8][10] O Output from the RTC oscillator circuit. V 33, 63, L3, T5, I ground: 0V reference for the digital IO pins. SSIO 77, 93, R9, P12, 114, N16, 133, H14, 148, E15, 169, A12, B6, 189, A2[11] 200[11] V 32, 84, K4, P10, I ground: 0V reference for the core. SSCORE 172[11] D12[11] V 22[12] J2[12] I analog ground: 0V reference. This should nominally be the same SSA voltage as V /V , but should be isolated to minimize noise and SSIO SSCORE error. V 15, 60, G3, P6, I 3.3V supply voltage: This is the power supply voltage for the I/O ports. DD(3V3) 71, 89, P8, U13, 112, P17, 125, K16, 146, C17, 165, B13, C9, 181, D7[13] 198[13] n.c. 30, 117, J4, L14, I not connected pins: These pins must be left unconnected (floating). 141[14] G14[14] V 26, 86, H4, P11, I 3.3V DC-to-DC converter supply voltage: This is the power supply for DD(DCDC)(3V3) 174[15] D11[15] the on-chip DC-to-DC converter. V 20[16] G4[16] I analog 3.3V pad supply voltage: This should be nominally the same DDA voltage as V but should be isolated to minimize noise and error. DD(3V3) This voltage is used to power the ADC and DAC. VREF 24[16] K1[16] I ADC reference: This should be nominally the same voltage as V DD(3V3) but should be isolated to minimize noise and error. The level on this pin is used as a reference for ADC and DAC. VBAT 38[16] M3[16] I RTC power supply: 3.3V on this pin supplies the power to the RTC peripheral. [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. [2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled. [3] 5V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. [4] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 26 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller [5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). [6] 5 V tolerant pad with 10ns glitch filter providing digital I/O functions with TTL levels and hysteresis. [7] 5 V tolerant pad with 20ns glitch filter providing digital I/O function with TTL levels and hysteresis. [8] Pad provides special analog functionality. [9] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. [10] If the RTC is not used, these pins can be left floating. [11] Pad provides special analog functionality. [12] Pad provides special analog functionality. [13] Pad provides special analog functionality. [14] Pad provides special analog functionality. [15] Pad provides special analog functionality. [16] Pad provides special analog functionality. [17] Either the I2S function or the LCD function is selectable, see Table20, Table21, and Table22. [18] Either the USB OTG function or the LCD function is selectable, see Table20, Table21, and Table22. [19] Either the trace function or the LCD function is selectable, see Table20, Table21, and Table22. [20] Either one of the external interrupts EINT1 to EINT3 or the LCD function is selectable, see Table20, Table21, and Table22. [21] Either one of the timer outputs MAT2[1] and MAT2[0] or the LCD function is selectable, see Table20, Table21, and Table22. [22] This pin has a built-in pull-up resistor. [23] This pin has no built-in pull-up and no built-in pull-down resistor. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 27 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 7. Functional description 7.1 Architectural overview The LPC2478 microcontroller consists of an ARM7TDMI-S CPU with emulation support, the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external memory, and the AMBA APB for connection to other on-chip peripheral functions. The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order. The LPC2478 implements two AHBs in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC. The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1. In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2 are the ARM7 and the Ethernet block. AHB peripherals are allocated a 2MB range of addresses at the very top of the 4GB ARM memory space. Each AHB peripheral is allocated a 16kB address space within the AHB address space. Lower speed peripheral functions are connected to the APB. The AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated a 2MB range of addresses, beginning at the 3.5GB address point. Each APB peripheral is allocated a 16kB address space within the APB address space. The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: • the standard 32-bit ARM set • a 16-bit Thumb set LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 28 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller The Thumb set’s 16-bit instruction length allows it to approach higher density compared to standard ARM code while retaining most of the ARM’s performance. 7.2 On-chip flash programming memory The LPC2478 incorporates 512kB flash memory system. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port (UART0). The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field and firmware upgrades. The flash memory is 128bits wide and includes pre-fetching and buffering techniques to allow it to operate at speeds of 72MHz. 7.3 On-chip SRAM The LPC2478 includes a SRAM memory of 64kB reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8bits, 16bits, and 32bits. A 16kB SRAM block serving as a buffer for the Ethernet controller and a 16kB SRAM associated with the second AHB can be used for data and code storage. The 2kB RTC SRAM can be used for data storage only. The RTC SRAM is battery powered and retains the content in the absence of the main power supply. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 29 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 7.4 Memory map The LPC2478 memory map incorporates several distinct regions as shown in Table5 and Figure4. In addition, the CPU interrupt vectors may be remapped to allow them to reside in either flash memory (default), boot ROM, or SRAM (see Section7.27.6). Table 5. LPC2478 memory usage and details Address range General use Address range details and description 0x00000000 to on-chip 0x00000000 - 0x0007FFFF flash memory (512kB) 0x3FFFFFFF non-volatile 0x3FFFC000 - 0x3FFFFFFF fast GPIO registers memory and Fast I/O 0x40000000 to on-chip RAM 0x40000000 - 0x4000FFFF RAM (64kB) 0x7FFFFFFF 0x7FE00000 - 0x7FE03FFF Ethernet RAM (16kB) 0x7FD00000 - 0x7FD03FFF USB RAM (16kB) 0x80000000 to off-chip Memory four static memory banks, 16 MB each 0xDFFFFFFF 0x80000000 - 0x80FFFFFF static memory bank 0 0x81000000 - 0x81FFFFFF static memory bank 1 0x82000000 - 0x82FFFFFF static memory bank 2 0x83000000 - 0x83FFFFFF static memory bank 3 four dynamic memory banks, 256 MB each 0xA0000000 - 0xAFFFFFFF dynamic memory bank 0 0xB0000000 - 0xBFFFFFFF dynamic memory bank 1 0xC0000000 - 0xCFFFFFFF dynamic memory bank 2 0xD0000000 - 0xDFFFFFFF dynamic memory bank 3 0xE0000000 to APB peripherals 36 peripheral blocks, 16kB each 0xEFFFFFFF 0xF0000000 to AHB peripherals 0xFFFFFFFF LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 30 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 4.0 GB 0xFFFF FFFF AHB PERIPHERALS 3.75 GB 0xF000 0000 APB PERIPHERALS 3.5 GB 0xE000 0000 0xDFFF FFFF EXTERNAL STATIC AND DYNAMIC MEMORY 2.0 GB 0x8000 0000 BOOT ROM AND BOOT FLASH 0x7FFF FFFF (BOOT FLASH REMAPPED FROM ON-CHIP FLASH) RESERVED ADDRESS SPACE ON-CHIP STATIC RAM 1.0 GB 0x4000 0000 0x3FFF FFFF SPECIAL REGISTERS 0x3FFF 8000 RESERVED ADDRESS SPACE 0x0008 0000 0x0007 FFFF ON-CHIP NON-VOLATILE MEMORY 0.0 GB 0x0000 0000 002aac736 Fig 4. LPC2478 memory map 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 31 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a programmable interrupt priority. When more than one interrupt is assigned the same priority and occur simultaneously, the one connected to the lowest numbered VIC channel will be serviced first. The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping to the address supplied by that register. 7.5.1 Interrupt sources Each peripheral device has one interrupt line connected to the VIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on port 0 and port 2 (total of 64 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. Such interrupt request coming from port 0 and/or port 2 will be combined with the EINT3 interrupt requests. 7.6 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7 External memory controller The LPC2478 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral. 7.7.1 Features • Dynamic memory interface support including single data rate SDRAM. • Asynchronous static memory device support including RAM, ROM, and flash, with or without asynchronous page mode. • Low transaction latency. • Read and write buffers to reduce latency and to improve performance. • 8/16/32data and 24 address lines wide static memory support. • 16 bit and 32 bit wide chip select SDRAM memory support. • Static memory features include: LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 32 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller – Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait • Four chip selects for synchronous memory and four chip selects for static memory devices. • Power-saving modes dynamically control CKE and CLKOUT to SDRAMs. • Dynamic memory self-refresh mode controlled by software. • Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device. • Separate reset domains allow auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.8 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2478 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. 7.8.1 Features • Two DMA channels. Each channel can support a unidirectional transfer. • The GPDMA can transfer data between the 16kB SRAM, external memory, and peripherals such as the SD/MMC, two SSPs, and the I2S interface. • Single DMA and burst DMA request signals. Each peripheral connected to the GPDMA can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the GPDMA. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. Each DMA channel has a specific hardware priority. DMA channel 0 has the highest priority and channel 1 has the lowest priority. If requests from two channels become active at the same time, the channel with the highest priority is serviced first. • AHB slave DMA programming interface. The GPDMA is programmed by writing to the DMA control registers over the AHB slave interface. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 33 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller • One AHB master for transferring data. This interface transfers data when a DMA request goes active. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the peripheral. • Internal four-word FIFO per channel. • Supports 8-bit, 16-bit, and 32-bit wide transactions. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Interrupt masking. The DMA error and DMA terminal count interrupt requests can be masked. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 7.9 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC2478 use accelerated GPIO functions: • GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • All GPIO registers are byte and half-word addressable. • Entire port value can be written in one instruction. Additionally, any pin on port 0 and port 2 (total of 64 pins) that is not configured as an analog input/output can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake the chip up from Power-down mode. 7.9.1 Features • Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset. • Backward compatibility with other earlier devices is maintained with legacy port 0 and port 1 registers appearing at the original addresses on the APB. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 34 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 7.10 LCD controller The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the displayed data) while still supporting a large number of colors. The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time needed to operate the display. 7.10.1 Features • AHB master interface to access frame buffer. • Setup and control via a separate AHB slave interface. • Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. • Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. • Supports single and dual-panel color STN displays. • Supports Thin Film Transistor (TFT) color displays. • Programmable display resolution including, but not limited to: 320200, 320240, 640200, 640240, 640480, 800600, and 1024768. • Hardware cursor support for single-panel displays. • 15 gray-level monochrome, 3375 color STN, and 32K color palettized TFT support. • 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. • 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. • 16 bpp true-color non-palettized, for color STN and TFT. • 24 bpp true-color non-palettized, for color TFT. • Programmable timing for different display panels. • 256 entry, 16-bit palette RAM, arranged as a 12832-bit RAM. • Frame, line, and pixel clock signals. • AC bias signal for STN, data enable signal for TFT panels. • Supports little and big-endian, and Windows CE data formats. • LCD panel clock may be generated from the peripheral clock, or from a clock input pin. 7.11 Ethernet The Ethernet block contains a full featured 10Mbit/s or 100Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 35 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2478 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip memory via the EMC, as well as the SRAM located on another AHB. However, using memory other than the Ethernet SRAM, especially off-chip memory, will slow Ethernet access to memory and increase the loading of its AHB. The Ethernet block interfaces between an off-chip Ethernet PHY using the Media Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 7.11.1 Features • Ethernet standards support: – Supports 10Mbit/s or 100Mbit/s PHY devices including 10Base-T, 100Base-TX, 100Base-FX, and 100Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. • Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 36 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 7.12 USB interface The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The LPC2478 USB interface includes a device, host, and OTG controller. Details on typical USB interfacing solutions can be found in Section 14.2 “Suggested USB interface solutions” on page 77 7.12.1 USB device controller The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the USB RAM. 7.12.1.1 Features • Fully compliant with USB 2.0 Specification (full speed). • Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM. • Supports Control, Bulk, Interrupt and Isochronous endpoints. • Scalable realization of endpoints at run time. • Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the LPC2478 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with the DMA RAM of 16kB on all non-control endpoints. • Allows dynamic switching between CPU-controlled and DMA modes. • Double buffer implementation for Bulk and Isochronous endpoints. 7.12.2 USB host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies with the Open Host Controller Interface (OHCI) specification. 7.12.2.1 Features • OHCI compliant • Two downstream ports • Supports per-port power switching LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 37 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 7.12.3 USB OTG controller USB OTG is a supplement to the USB 2.0 Specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I2C interface to implement OTG dual-role device functionality. The dedicated I2C interface controls an external OTG transceiver. 7.12.3.1 Features • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a. • Hardware support for Host Negotiation Protocol (HNP). • Includes a programmable timer required for HNP and Session Request Protocol (SRP). • Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev. 1.0. 7.13 CAN controller and acceptance filters The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router between two of CAN buses in industrial or automotive applications. Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN Library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the ARM environment. The main operational difference is that the recognition of received Identifiers, known in CAN terminology as Acceptance Filtering, has been removed from the CAN controllers and centralized in a global Acceptance Filter. 7.13.1 Features • Two CAN controllers and buses. • Data rates to 1Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 38 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 7.14 10-bit ADC The LPC2478 contains one ADC. It is a single 10-bit successive approximation ADC with eight channels. 7.14.1 Features • 10-bit successive approximation ADC • Input multiplexing among 8 pins • Power-down mode • Measurement range 0 V to V i(VREF) • 10-bit conversion time  2.44s • Burst conversion mode for single or multiple inputs • Optional conversion on transition of input pin or Timer Match signal • Individual result registers for each ADC channel to reduce interrupt overhead 7.15 10-bit DAC The DAC allows the LPC2478 to generate a variable analog output. The maximum output value of the DAC is V . i(VREF) 7.15.1 Features • 10-bit DAC • Resistor string architecture • Buffered output • Power-down mode • Selectable output drive 7.16 UARTs The LPC2478 contains four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 can be achieved with any crystal frequency above 2MHz. 7.16.1 Features • 16B Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1B, 4B, 8B, and 14B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 39 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller • UART3 includes an IrDA mode to support infrared communication. 7.17 SPI serial I/O controller The LPC2478 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8bits to 16bits of data to the slave, and the slave always sends 8bits to 16bits of data to the master. 7.17.1 Features • Compliant with SPI specification • Synchronous, Serial, Full Duplex Communication • Combined SPI master and slave • Maximum data bit rate of one eighth of the input clock rate • 8bits to 16bits per transfer 7.18 SSP serial I/O controller The LPC2478 contains two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4bits to 16bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.18.1 Features • Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame • Maximum SPI bus data bit rate of one half (Master mode) and one twelfth (Slave mode) of the input clock rate • DMA transfers supported by GPDMA 7.19 SD/MMC card interface The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD memory cards. The SD card interface conforms to the SD Multimedia Card Specification Version 2.11. 7.19.1 Features • The MCI provides all functions specific to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 40 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller • Conforms to Multimedia Card Specification v2.11. • Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96. • Can be used as a multimedia card bus or a secure digital memory card bus host. The SD/MMC can be connected to several multimedia cards or a single secure digital memory card. • DMA supported through the GPDMA controller. 7.20 I2C-bus serial I/O controller The LPC2478 contains three I2C-bus controllers. The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus and can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2478 supports bit rates up to 400kbit/s (Fast I2C-bus). 7.20.1 Features • I2C0 is a standard I2C compliant bus interface with open-drain pins. • I2C1 and I2C2 use standard I/O pins and do not support powering off of individual devices connected to the same bus lines. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. 7.21 I2S-bus serial I/O controllers The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S connection has one master, which is always the master, and one slave. The I2S interface on the LPC2478 provides a separate transmit and receive channel, each of which can operate as either a master or a slave. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 41 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 7.21.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16kHz to 48kHz (16, 22.05, 32, 44.1, 48)kHz. • Configurable word select period in master mode (separately for I2S input and output). • Two 8word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I2S input and I2S output. 7.22 General purpose 32-bit timers/external event counters The LPC2478 includes four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. The Timer/Counter also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.22.1 Features • A 32-bit Timer/Counter with a programmable 32-bit prescaler. • Counter or Timer operation. • Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 42 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 7.23 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2478. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. A dedicated match register controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, a dedicated match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 7.23.1 Features • LPC2478 has two PWMs with the same operational features. These may be operated in a synchronized fashion by setting them both up to run at the same rate, then enabling both simultaneously. PWM0 acts as the master and PWM1 as the slave for this use. • Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). • Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 43 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard timer if the PWM mode is not enabled. • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. 7.24 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. 7.24.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal prescaler. • Selectable time period from (T 2564) to (T 2324) in cy(WDCLK) cy(WDCLK) multiples of T 4. cy(WDCLK) • The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring, for increased reliability. 7.25 RTC and battery RAM The RTC is a set of counters for measuring time when system power is on, and optionally when power is off. It uses little power in Power-down and Deep power-down modes. On the LPC2478, the RTC can be clocked by a separate 32.768kHz oscillator or by a programmable prescale divider based on the APB clock. Also, the RTC is powered by its own power supply pin, VBAT, which can be connected to a battery or to the same 3.3V supply used by the rest of the device. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 44 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions require a minimum of power to operate, which can be supplied by an external battery. When the CPU and the rest of chip functions are stopped and power removed, the RTC can supply an alarm output that can be used by external hardware to restore chip power and resume operation. 7.25.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Dedicated 32kHz oscillator or programmable prescaler from APB clock. • Dedicated power supply pin can be connected to a battery or to the main 3.3V. • An alarm output pin is included to assist in waking up when the chip has had power removed to all functions except the RTC and Battery RAM. • Periodic interrupts can be generated from increments of any field of the time registers, and selected fractional second values. This enhancement enables the RTC to be used as a System Timer. • 2kB data SRAM powered by VBAT. • RTC and Battery RAM power supply is isolated from the rest of the chip. 7.26 Clocking and power control 7.26.1 Crystal oscillators The LPC2478 includes three independent oscillators. These are the Main Oscillator, the Internal RC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the PLL and ultimately the CPU. Following reset, the LPC2478 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. 7.26.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4MHz. The IRC is trimmed to 1% accuracy. Upon power-up or any chip reset, the LPC2478 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.26.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator operates at frequencies of 1MHz to 25MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 45 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section7.26.2 for additional information. 7.26.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the RTC oscillator can be used to drive the PLL and the CPU. 7.26.2 PLL The PLL accepts an input clock frequency in the range of 32kHz to 25MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and the USB block. The PLL input, in the range of 32kHz to 25MHz, may initially be divided down by a value ‘N’, which may be in the range of 1 to 256. This input division provides a wide range of output frequencies from the same input frequency. Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the range of 1 through 32768. The resulting frequency must be in the range of 275MHz to 550MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency. The PLL is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL is enabled by software only. The program must configure and activate the PLL, wait for the PLL to lock, then connect to the PLL as a clock source. 7.26.3 Wake-up timer The LPC2478 begins operation at power-up and when awakened from Power-down and Deep-power down modes by using the 4MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down and Deep power-down modes, any wake-up of the processor from Power-down modes makes use of the Wake-up Timer. The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of V ramp (in the case of power on), the type of crystal and its DD(3V3) electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 46 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 7.26.4 Power control The LPC2478 supports a variety of power control features. There are four special modes of processor power reduction: Idle mode, Sleep mode, Power down-mode and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. The LPC2478 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small SRAM, referred to as the Battery RAM. 7.26.4.1 Idle mode In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.26.4.2 Sleep mode In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The 32kHz RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The CCLK and USB clock dividers automatically get reset to zero. The Sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Sleep mode reduces chip power consumption to a very low value. The flash memory is left on in Sleep mode, allowing a very quick wake-up. On the wake-up from Sleep mode, if the IRC was used before entering Sleep mode, the code execution and peripherals activities will resume after 4 cycles expire. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. The customers need to reconfigure the PLL and clock dividers accordingly. 7.26.4.3 Power-down mode Power-down mode does everything that Sleep mode does, but also turns off the IRC oscillator and the flash memory. This saves more power, but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. On the wake-up from Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60s to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 47 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller the meantime, the flash wake-up timer then counts 4MHz IRC clock cycles to make the 100s flash start-up time. When it times out, access to the flash will be allowed. The customers need to reconfigure the PLL and clock dividers accordingly. 7.26.4.4 Deep power-down mode Deep power-down mode is similar to the Power-down mode, but now the on-chip regulator that supplies power to the internal logic is also shut off. This produces the lowest possible power consumption without removing power from the entire chip. Since the Deep power-down mode shuts down the on-chip logic power supply, there is no register or memory retention, and resumption of operation involves the same activities as a full chip reset. If power is supplied to the LPC2478 during Deep power-down mode, wake-up can be caused by the RTC Alarm interrupt or by external Reset. While in Deep power-down mode, external device power may be removed. In this case, the LPC2478 will start up when external power is restored. Essential data may be retained through Deep power-down mode (or through complete powering off of the chip) by storing data in the Battery RAM, as long as the external power to the VBAT pin is maintained. 7.26.4.5 Power domains The LPC2478 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the Battery RAM. On the LPC2478, I/O pads are powered by the 3.3V (V ) pins, while the DD(3V3) V pins power the on-chip DC-to-DC converter which in turn provides power to DD(DCDC)(3V3) the CPU and most of the peripherals. Although both the I/O pad ring and the core require a 3.3V supply, different powering schemes can be used depending on the actual application requirements. The first option assumes that power consumption is not a concern and the design ties the V and V pins together. This approach requires only one 3.3 V power DD(3V3) DD(DCDC)(3V3) supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.3V supply for the I/O pads (V ) and DD(3V3) a dedicated 3.3V supply for the CPU (V ). Having the on-chip DC-DC DD(DCDC)(3V3) converter powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly”, while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions require a minimum of power to operate, which can be supplied by an external battery. When the CPU and the rest of chip functions are stopped and power removed, the RTC can supply an alarm output that may be used by external hardware to restore chip power and resume operation. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 48 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 7.27 System control 7.27.1 Reset Reset has four sources on the LPC2478: the RESET pin, the Watchdog reset, power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the wake-up timer (see description in Section 7.26.3 “Wake-up timer”), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. 7.27.2 Brownout detection The LPC2478 includes 2-stage monitoring of the voltage on the V pins. If this DD(DCDC)(3V3) voltage falls below 2.95V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts Reset to inactivate the LPC2478 when the voltage on the V pins falls below 2.65V. This Reset prevents alteration of DD(DCDC)(3V3) the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1V, at which point the power-on reset circuitry maintains the overall Reset. Both the 2.95V and 2.65V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.95V detection to reliably interrupt, or a regularly-executed event loop to sense the condition. 7.27.3 Code security (Code Read Protection - CRP) This feature of the LPC2478 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or a call to reinvoke the ISP command to enable flash update via UART0. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 49 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. 7.27.4 AHB The LPC2478 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16kB SRAM. The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1. In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2 are the ARM7 and the Ethernet block. 7.27.5 External interrupt inputs The LPC2478 includes up to 68 edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. 7.27.6 Memory mapping control The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot ROM, the SRAM, or external memory. This allows code running in different memory spaces to have control of the interrupts. 7.28 Emulation and debugging The LPC2478 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself. 7.28.1 EmbeddedICE The EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present on the target system. The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 50 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller DCC is accessed as a coprocessor 14 by the program running on the ARM7TDMI-S core. The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock (TCK) must be slower than 1⁄ of the CPU clock (CCLK) for the JTAG 6 interface to operate. 7.28.2 Embedded trace Since the LPC2478 have significant amounts of on-chip memories, it is not possible to determine how the processor core is operating simply by observing the external pins. The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace port. A software debugger allows configuration of the ETM using a JTAG interface and displays the trace information that has been captured. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external Trace Port Analyzer captures the trace information under software debugger control. The trace port can broadcast the Instruction trace information. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. 7.28.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2478 contain a specific configuration of RealMonitor software programmed into the on-chip ROM memory. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 51 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 8. Limiting values Table 6. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit V supply voltage (3.3 V) core and external 3.0 3.6 V DD(3V3) rail V DC-to-DC converter supply voltage 3.0 3.6 V DD(DCDC)(3V3) (3.3V) V analog 3.3 V pad supply voltage 0.5 +4.6 V DDA V input voltage on pin VBAT for the RTC 0.5 +4.6 V i(VBAT) V input voltage on pin VREF 0.5 +4.6 V i(VREF) V analog input voltage on ADC related 0.5 +5.1 V IA pins V input voltage 5V tolerant I/O [2] 0.5 +6.0 V I pins; only valid when the V DD(3V3) supply voltage is present other I/O pins [2][3] 0.5 V + V DD(3V3) 0.5 I supply current per supply pin [4] - 100 mA DD I ground current per ground pin [4] - 100 mA SS T storage temperature non-operating [5] 65 +150 C stg P total power dissipation (per package) based on package - 1.5 W tot(pack) heat transfer, not device power consumption V electrostatic discharge voltage human body [6] 2500 +2500 V ESD model; all pins [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSSIO/VSSCORE unless otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] Not to exceed 4.6V. [4] The peak current is limited to 25 times the corresponding maximum current. [5] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [6] Human body model: equivalent to discharging a 100pF capacitor through a 1.5k series resistor. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 52 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 9. Thermal characteristics The average chip junction temperature, T (C), can be calculated using the following j equation: Tj = Tamb+PDRthj–a (1) • T = ambient temperature (C), amb • R = the package junction-to-ambient thermal resistance (C/W) th(j-a) • P = sum of internal and I/O power dissipation D The internal power dissipation is the product of I and V . The I/O power dissipation of DD DD the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 7. Thermal cha racteristics V =3.0V to 3.6V; T =40C to +85C unless otherwise specified; DD amb Symbol Parameter Conditions Min Typ Max Unit T maximum junction - - 125 C j(max) temperature Table 8. Thermal resi stance value (C/W): ±15 % V =3.0V to 3.6V; T =40C to +85C unless otherwise specified; DD amb LQFP208 TFBGA208 ja ja JEDEC (4.5 in  4 in) JEDEC (4.5 in  4 in) 0 m/s 27.4 0 m/s 41 1 m/s 25.7 1 m/s 35 2.5 m/s 24.4 2.5 m/s 31 Single-layer (4.5 in  3 in) 8-layer (4.5 in  3 in) 0 m/s 35.4 0 m/s 34.9 1 m/s 31.2 1 m/s 30.9 2.5 m/s 29.2 2.5 m/s 28 jc 8.8 jc 8.3 jb 15.4 jb 13.6 LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 53 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 10. Static characteristics Table 9. Static charac teristics T =40C to +85C for commercial applications, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit V supply voltage (3.3 V) core and external rail 3.0 3.3 3.6 V DD(3V3) V DC-to-DC converter 3.0 3.3 3.6 V DD(DCDC)(3V3) supply voltage (3.3 V) V analog 3.3 V pad 3.0 3.3 3.6 V DDA supply voltage V input voltage on pin [2] 2.0 3.3 3.6 V i(VBAT) VBAT V input voltage on pin 2.5 3.3 V V i(VREF) DDA VREF I active mode V =3.3V; DD(DCDC)act(3V3) DD(DCDC)(3V3) DC-to-DC converter T =25C; code amb supply current (3.3V) while(1){} executed from flash; no peripherals enabled; PCLK=CCLK CCLK=10MHz - 15 - mA CCLK=72MHz - 63 - mA all peripherals enabled; PCLK=CCLK/8 CCLK=10MHz - 21 - mA CCLK=72MHz - 92 - mA all peripherals enabled; PCLK=CCLK CCLK=10MHz - 27 - mA CCLK=72MHz - 125 - mA I Power-down mode V =3.3V; [3] - 113 - A DD(DCDC)pd(3V3) DD(DCDC)(3V3) DC-to-DC converter T =25C amb supply current (3.3V) I Deep power-down [3] DD(DCDC)dpd(3V3 mode DC-to-DC ) converter supply current (3.3V) - 20 - A I active mode battery [4] BATact supply current - 20 - A I battery supply current Deep power-down mode [3] - 20 - A BAT LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 54 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 9. Static characteristics …continued T =40C to +85C for commercial applications, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit Standard port pins, RESET, RTCK I LOW-level input V =0V; no pull-up - - 3 A IL I current I HIGH-level input V =V ; no - - 3 A IH I DD(3V3) current pull-down I OFF-state output V =0V; V =V ; - - 3 A OZ O O DD(3V3) current no pull-up/down I I/O latch-up current (0.5V ) < V < - - 100 mA latch DD(3V3) I (1.5V ); DD(3V3) T < 125C j V input voltage pin configured to provide a [5][6][7] 0 - 5.5 V I digital function [8] V output voltage output active 0 - V V O DD(3V3) V HIGH-level input 2.0 - - V IH voltage V LOW-level input - - 0.8 V IL voltage V hysteresis voltage 0.4 - - V hys V HIGH-level output I =4 mA [9] V  - - V OH OH DD(3V3) voltage 0.4 V LOW-level output I =4 mA [9] - - 0.4 V OL OL voltage I HIGH-level output V =V 0.4V [9] 4 - - mA OH OH DD(3V3) current I LOW-level output V =0.4V [9] 4 - - mA OL OL current I HIGH-level V =0V [10] - - 45 mA OHS OH short-circuit output current I LOW-level V =V [10] - - 50 mA OLS OL DDA short-circuit output current I pull-down current V =5V [11] 10 50 150 A pd I I pull-up current V =0V 15 50 85 A pu I V <V <5V [11] 0 0 0 A DD(3V3) I I2C-bus pins (P0[27] and P0[28]) V HIGH-level input 0.7V - - V IH DD(3V3) voltage V LOW-level input - - 0.3V V IL DD(3V3) voltage V hysteresis voltage - 0.05V - V hys DD(3V3) V LOW-level output I =3 mA [9] - - 0.4 V OL OLS voltage I input leakage current V =V [12] - 2 4 A LI I DD(3V3) V =5V - 10 22 A I LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 55 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 9. Static characteristics …continued T =40C to +85C for commercial applications, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit Oscillator pins V input voltage on pin 0.5 1.8 1.95 V i(XTAL1) XTAL1 V output voltage on pin 0.5 1.8 1.95 V o(XTAL2) XTAL2 V input voltage on pin 0.5 1.8 1.95 V i(RTCX1) RTCX1 V output voltage on pin 0.5 1.8 1.95 V o(RTCX2) RTCX2 USB pins I OFF-state output 0V<V <3.3V - - 10 A OZ I current V bus supply voltage - - 5.25 V BUS V differential input (D+)(D) 0.2 - - V DI sensitivity voltage V differential common includes V range 0.8 - 2.5 V CM DI mode voltage range V single-ended receiver 0.8 - 2.0 V th(rs)se switching threshold voltage V LOW-level output R of 1.5k to 3.6V - - 0.18 V OL L voltage for low-/full-speed V HIGH-level output R of 15k to GND 2.8 - 3.5 V OH L voltage (driven) for low-/full-speed C transceiver pin to GND - - 20 pF trans capacitance Z driver output with 33 series resistor; [13] 36 - 44.1  DRV impedance for driver steady state drive which is not high-speed capable [1] Typical ratings are not guaranteed. The values listed are at room temperature (25C), nominal supply voltages [2] The RTC typically fails when V drops below 1.6V. i(VBAT) [3] VDD(DCDC)(3V3) =3.3V; VDD(3V3) = 3.3 V; Vi(VBAT) = 3.3 V; Tamb=25C. [4] On pin VBAT. [5] Including voltage on outputs in 3-state mode. [6] V supply voltages must be present. DD(3V3) [7] 3-state outputs go into 3-state mode when V is grounded. DD(3V3) [8] Please also see the errata note in errata sheet. [9] Accounts for 100mV voltage drop in all supply lines. [10] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [11] Minimum condition for V =4.5V, maximum condition for V =5.5V. I I [12] To V . SSIO [13] Includes external resistors of 331% on D+ and D. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 56 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 10.1 Power-down mode 002aae049 4 IDD(IO) (μA) 2 VDD(3V3) = 3.3 V VDD(3V3) = 3.0 V 0 −2 −4 −40 −15 10 35 60 85 temperature (°C) Vi(VBAT) = VDD(DCDC)(3V3) = 3.3 V; Tamb=25C. Fig 5. I/O maximum supply current I versus temperature in Power-down mode DD(IO) 002aae050 40 IBAT (μA) 30 Vi(VBAT) = 3.3 V Vi(VBAT) = 3.0 V 20 10 0 −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb=25C. Fig 6. RTC battery maximum supply current I versus temperature in Power-down BAT mode LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 57 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 002aae051 800 IDD(DCDC)pd(3v3) (μA) 600 400 VDD(DCDC)(3V3) = 3.3 V 200 VDD(DCDC)(3V3) = 3.0 V 0 −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = Vi(VBAT) = 3.3 V; Tamb=25C. Fig 7. Total DC-to-DC converter supply current I at different temperatures DD(DCDC)pd(3V3) in Power-down mode 10.2 Deep power-down mode 002aae046 300 IDD(IO) (μA) 200 100 VDD(3V3) = 3.3 V VDD(3V3) = 3.0 V 0 −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb=25C. Fig 8. I/O maximum supply current I versus temperature in Deep power-down DD(IO) mode LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 58 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 002aae047 40 IBAT (μA) 30 Vi(VBAT) = 3.3 V Vi(VBAT) = 3.0 V 20 10 0 −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb=25C Fig 9. RTC battery maximum supply current I versus temperature in Deep BAT power-down mode 002aae048 100 IDD(DCDC)dpd(3v3) (μA) 80 60 VDD(DCDC)(3V3) = 3.3 V 40 VDD(DCDC)(3V3) = 3.0 V 20 0 −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = Vi(VBAT) = 3.3 V; Tamb=25C. Fig 10. Total DC-to-DC converter maximum supply current I versus DD(DCDC)dpd(3V3) temperature in Deep power-down mode LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 59 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 10.3 Electrical pin characteristics 002aaf112 3.6 VOH (V) T = 85 °C 3.2 25 °C −40 °C 2.8 2.4 2.0 0 8 16 24 IOH (mA) Conditions: V = 3.3 V; standard port pins. DD(3V3) Fig 11. Typical HIGH-level output voltage V versus HIGH-level output source current OH I OH 002aaf111 15 IOL T = 85 °C (mA) 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: V = 3.3 V; standard port pins. DD(3V3) Fig 12. Typical LOW-level output current I versus LOW-level output voltage V OL OL LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 60 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 11. Dynamic characteristics Table 10. Dynamic cha racteristics T =40C to +85C for commercial applications; V over specified ranges.[1] amb DD(3V3) Symbol Parameter Conditions Min Typ[2] Max Unit External clock f oscillator frequency 1 - 25 MHz osc T clock cycle time 40 - 1000 ns cy(clk) t clock HIGH time T 0.4 - - ns CHCX cy(clk) t clock LOW time T 0.4 - - ns CLCX cy(clk) t clock rise time - - 5 ns CLCH t clock fall time - - 5 ns CHCL I2C-bus pins (P0[27] and P0[28]) t output fall time V to V 20 + 0.1  C [3] - - ns f(o) IH IL b SSP interface t SPI_MISO set-up time T = 25C; - 11 - ns su(SPI_MISO) amb measured in SPI Master mode; see Figure17 [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25C), nominal supply voltages. [3] Bus capacitance C in pF, from 10 pF to 400 pF. b tCHCX tCHCL tCLCX tCLCH Tcy(clk) 002aaa907 Fig 13. External clock timing (with an amplitude of at least V = 200 mV) i(RMS) LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 61 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 11.1 Internal oscillators Table 11. Dynamic cha racteristic: internal oscillators T =40C to +85C; 3.0 V  V  3.6 V.[1] amb DD(3V3) Symbol Parameter Conditions Min Typ[2] Max Unit f internal RC oscillator frequency - 3.96 4.02 4.04 MHz osc(RC) f RTC input frequency - - 32.768 - kHz i(RTC) [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25C), nominal supply voltages. 11.2 I/O pins Table 12. Dynamic cha racteristic: I/O pins[1] T =40C to +85C; V over specified ranges. amb DD(3V3) Symbol Parameter Conditions Min Typ Max Unit t rise time pin configured as output 3.0 - 5.0 ns r t fall time pin configured as output 2.5 - 5.0 ns f [1] Applies to standard I/O pins and RESET pin. 11.3 USB interface Table 13. Dynamic cha racteristics of USB pins C = 50 pF; R = 1.5k on D+ to V ,unless otherwise specified. L pu DD(3V3) Symbol Parameter Conditions Min Typ Max Unit t rise time 10% to 90% 8.5 - 13.8 ns r t fall time 10% to 90% 7.7 - 13.7 ns f t differential rise and fall time t /t - - 109 % FRFM r f matching V output signal crossover voltage 1.3 - 2.0 V CRS t source SE0 interval of EOP see Figure16 160 - 175 ns FEOPT t source jitter for differential transition see Figure16 2 - +5 ns FDEOP to SE0 transition t receiver jitter to next transition 18.5 - +18.5 ns JR1 t receiver jitter for paired transitions 10% to 90% 9 - +9 ns JR2 t EOP width at receiver must reject as [1] 40 - - ns EOPR1 EOP; see Figure16 t EOP width at receiver must accept as [1] 82 - - ns EOPR2 EOP; see Figure16 [1] Characterized but not implemented as production test. Guaranteed by design. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 62 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 11.4 Flash memory Table 14. Dynamic cha racteristics of flash T =40C to +85C, unless otherwise specified; V = 3.0 V to 3.6 V; all voltages are measured with respect to amb DD(3V3) ground. Symbol Parameter Conditions Min Typ Max Unit N endurance [1] 10000 100000 - cycles endu t retention time powered; < 100 cycles [2] 10 - - years ret unpowered; < 100 cycles 20 - - years t erase time sector or multiple 95 100 105 ms er consecutive sectors t programming time [2] 0.95 1 1.05 ms prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 63 of 93

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Produ LPC2478 11.5 Static external memory interface NXP ct d Table 15. Dynamic cha racteristics: Static external memory interface S ata CL=30pF, Tamb=40C to 85C, VDD(DCDC)(3V3) = VDD(3V3) = 3.0V to 3.6V em sh Symbol Parameter Conditions Min Typ Max Unit ic e e o t Common to read and write cycles[1] n d tCSLAV CS LOW to address valid 0.29 0.20 2.54 ns u time c t o Read cycle parameters[1][2] r s t OE LOW to address valid 0.29 0.20 2.54 ns OELAV time t CS LOW to OE LOW time 0.78 + T  WAITOEN 0 + T  WAITOEN 0.49 + T  WAITOEN ns CSLOEL cy(CCLK) cy(CCLK) cy(CCLK) All inform tam memory access time [3][4] (TWcyA(CICTLRKD) 1 W2.A70IT OEN+ 1) (TWcyA(CICTLRKD) 9 W.5A7ITOEN+ 1) (TWcyA(CICTLRKD) 8 W.1A1ITOEN+ 1) ns Rev. 3.1 — 16 October 2013 ation provided in this document is subject to legal disclaimers. tttttWthCOOBC(LSSEErDSHHiHL)tLOOBAeAELNE VcSHVHHycletdCOtOBCii mmapLSSEEtSaeea HHHLr LaiOIIInGGGOmpWHHHWue t t t ttteohtoooor o Os OBalad[dEL1Ed d]St [d iH6rHm re]HeIIsGeGsIsGsHH i Hn v ttvai imtmaliimdleeid e [5] 0W00000A.....28534IT08999O +E (NWA+ I1T)RD Tc y(CCLK) 000-001.. )2+409 ( TWcAy(ICTCRLKD)  WAITOEN+ 220-0W0.....54612A48400IT +O (EWNA+IT 1R)D T cy(CCLK) nnnnnsssss Sing tCSLWEL CS LOW to WE LOW time 0.88 + Tcy(CCLK)  (1+ 0.10 + Tcy(CCLK)  (1+ 0.20 + Tcy(CCLK)  (1+ ns le- WAITWEN) WAITWEN) WAITWEN) c h t CS LOW to BLS LOW time 0.88 0.49 0.98 ns ip CSLBLSL 1 t WE LOW to data valid time 0.68 2.54 5.86 ns 6 WELDV - b t CS LOW to data valid time 0 2.64 4.79 ns it CSLDV /3 tWELWEH WE LOW to WE HIGH time [3] 0.78 + Tcy(CCLK) 0 + Tcy(CCLK) (WAITWR 0.10 + Tcy(CCLK) ns 2-b 64 of 93 © NXP B.V. 2013. All rights reserved. ttBWLESHLABNLSVH tBWtiimmLESee H LIOGWH ttoo aBdLdSre HssIG inHv alid [[33]] ((0WW0 +.AA8 TII8TTc y+WW(C TRRCcLyK(C )WWCLAAKII)TTWW EENN++ 13)) 00WW. +2AA0 IITTT +cWWy (TCEEcCNNyL(CK++C) L13K ))()WAITWR ((20WW..75AA49II TT++WW TTccRRyy((CCCC WWLLKKAA))IITT WWEENN++ 13)) nnss it microcontroller LPC2478

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Produ LPC2478 TCaLb=le3 105p.F, TDaymnba=mic4 0chCar taoc 8te5risCt,i cVsD: DS(DtaCtDicC )e(3xVt3e) r=n ValD mD(3eVm3)o =r y3 .i0ntVe rtfoa c3e.6 …Vcontinued NXP ct d Symbol Parameter Conditions Min Typ Max Unit S ata tWEHDNV WE HIGH to data invalid [3] 0.78 + Tcy(CCLK) 2.54 + Tcy(CCLK) 5.96 + Tcy(CCLK) ns em sh time ic e e t BLS HIGH to address [3] 0.29 0.20 2.54 ns o t BLSHANV n invalid time d u tBLSHDNV BLS HIGH to data invalid [3] 0 2.54 5.37 ns c t time o r s [1] V = 2.5 V, V = 0.2 V. OH OL [2] V = 2.5 V, V = 0.5 V. IH IL [3] T = 1⁄ . cy(CCLK) CCLK A [4] Latest of address valid, CS LOW, OE LOW to data valid. ll inform [5] Earliest of CS HIGH, OE HIGH, address change to data invalid. Rev. 3.1 — 16 O ation provided in this docum [6] Byte lane state bit (PB) = 1. ctober 2013 ent is subject to legal disclaimers. Sing le - c h ip 1 6 - b it /3 2 - b © NXP it m LP 65 of 93 B.V. 2013. All rights reserved. icrocontroller C2478

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 11.6 Dynamic external memory interface Table 16. Dynamic cha racteristics: Dynamic external memory interface C =30pF, T =40C to 85C, V = V = 3.0V to 3.6V, EMC Dynamic Read Config Register = 0x0 L amb DD(DCDC)(3V3) DD(3V3) (RD = 00) Symbol Parameter Conditions Min Typ Max Unit Common t chip select valid delay time [1] - 1.05 1.76 ns d(SV) t chip select hold time [1] 0.1 1.02 - ns h(S) t row address strobe valid delay time [1] - 1.51 1.95 ns d(RASV) t row address strobe hold time [1] 0.5 1.51 - ns h(RAS) t column address strobe valid delay time [1] - 0.98 1.27 ns d(CASV) t column address strobe hold time [1] 0.1 0.97 - ns h(CAS) t write valid delay time [1] - 0.84 1.95 ns d(WV) t write hold time [1] 0.1 0.84 - ns h(W) t output enable valid delay time [1] - 0.95 1.86 ns d(GV) t output enable hold time [1] 0.1 1 - ns h(G) t address valid delay time [1] - 0.87 1.95 ns d(AV) t address hold time [1] 0.1 0.81 - ns h(A) Read cycle parameters t data input set-up time [1] 0.51 2.24 - ns su(D) t data input hold time [1] 0.57 2.41 - ns h(D) Write cycle parameters t data output valid delay time [1] - 2.65 4.36 ns d(QV) t data output hold time [1] 0.49 2.61 - ns h(Q) [1] See Figure18. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 66 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 17. Dynamic cha racteristics: Dynamic external memory interface C =30pF on all pins, T =40C to 85C, V = V = 3.3V, EMC Dynamic Read Config Register = 0x1 L amb DD(DCDC)(3V3) DD(3V3) (RD = 01), T = 1/CCLK cy(CCLK) Symbol Parameter Conditions Min Typ Max Unit Common t chip select valid delay [1] - 3 + T 1.5 + T ns d(SV) cy(CCLK) cy(CCLK) time t chip select hold time [1] 4 + T 3 + T - ns h(S) cy(CCLK) cy(CCLK) t row address strobe valid [1] - 3 + T 1.5 + T ns d(RASV) cy(CCLK) cy(CCLK) delay time t row address strobe hold [1] 3 + T 2.3 + T - ns h(RAS) cy(CCLK) cy(CCLK) time t column address strobe [1] - 3.4 + T 2.1 + T ns d(CASV) cy(CCLK) cy(CCLK) valid delay time t column address strobe [1] 4 + T 3 + T - ns h(CAS) cy(CCLK) cy(CCLK) hold time t write valid delay time [1] - 3.4 + T 2.1 + T ns d(WV) cy(CCLK) cy(CCLK) t write hold time [1] 4 + T 3 + T - ns h(W) cy(CCLK) cy(CCLK) t output enable valid delay [1] - 3 + T 1.3 + T ns d(GV) cy(CCLK) cy(CCLK) time t output enable hold time [1] 4 + T 2.1 + T - ns h(G) cy(CCLK) cy(CCLK) t address valid delay time [1] - 2.6 + T 1.4 + T ns d(AV) cy(CCLK) cy(CCLK) t address hold time [1] 4 + T 2.3 + T - ns h(A) cy(CCLK) cy(CCLK) Read cycle parameters t data input set-up time [1] 2.6 + T 1.5 + T - ns su(D) cy(CCLK) cy(CCLK) t data input hold time [1] 2.6 + T 1.3 + T - ns h(D) cy(CCLK) cy(CCLK) Write cycle parameters t data output valid delay [1] - 2.6 + T /2 4.8 + T /2 ns d(QV) cy(CCLK) cy(CCLK) time t data output hold time [1] 3.8 + T 3.4 + T - ns h(Q) cy(CCLK) cy(CCLK) [1] See Figure18. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 67 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 11.7 Timing tCSLAV tCSHOEH CS addr tam th(D) data tCSLOEL tOELAV tOEHANV tOELOEH OE tBLSLAV tCSHBLSH BLS 002aad955 Fig 14. External memory read access CS tCSLAV tWELWEH tCSLWEL tBLSLBLSH BLS/WE tWEHANV tCSLBLSL tWELDV tBLSHANV addr tWEHDNV tCSLDV tBLSHDNV data OE 002aad956 Fig 15. External memory write access LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 68 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller TPERIOD crossover point extended crossover point differential data lines source EOP width: tFEOPT differential data to SE0/EOP skew n × TPERIOD + tFDEOP receiver EOP width: tEOPR1, tEOPR2 002aab561 Fig 16. Differential data-to-EOP transition skew and EOP width shifting edges SCK sampling edges MOSI MISO tsu(SPI_MISO) 002aad326 Fig 17. MISO line set-up time in SSP Master mode reference clock td(XXX) th(XXX) output signal (O) tsu(D) th(D) input signal (I) 002aad636 Fig 18. Signal timing LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 69 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 12. ADC electrical characteristics Table 18. ADC static c haracteristics V =2.5V to 3.6V; T =40C to +85C unless otherwise specified; ADC frequency 4.5MHz. DDA amb Symbol Parameter Conditions Min Typ Max Unit V analog input voltage 0 - V V IA DDA C analog input capacitance - - 1 pF ia E differential linearity error [1][2][3] - - 1 LSB D E integral non-linearity [1][4] - - 2 LSB L(adj) E offset error [1][5] - - 3 LSB O E gain error [1][6] - - 0.5 % G E absolute error [1][7] - - 4 LSB T R voltage source interface [8] - - 40 k vsi resistance [1] Conditions: V =0V, V =3.3V. SSA DDA [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error (E ) is the difference between the actual step width and the ideal step width. See Figure19. D [4] The integral non-linearity (E ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after L(adj) appropriate adjustment of gain and offset errors. See Figure19. [5] The offset error (E ) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the O ideal curve. See Figure19. [6] The gain error (E ) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset G error, and the straight line which fits the ideal transfer curve. See Figure19. [7] The absolute error (E ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated T ADC and the ideal transfer curve. See Figure19. [8] See Figure20. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 70 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller offset gain error error EO EG 1023 1022 1021 1020 1019 1018 (2) 7 code (1) out 6 5 (5) 4 (4) 3 (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO Vi(VREF) − VSSA 1 LSB = 1024 002aae604 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 19. ADC characteristics LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 71 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller LPC2XXX 20 kΩ AD0[y] Rvsi AD0[y]SAMPLE 3 pF 5 pF VEXT VSSIO, VSSCORE 002aad586 Fig 20. Suggested ADC interface - LPC2478 AD0[y] pin LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 72 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 13. DAC electrical characteristics Table 19. DAC electric al characteristics V =3.0V to 3.6V; T =40C to +85C unless otherwise specified DDA amb Symbol Parameter Conditions Min Typ Max Unit E differential linearity error - 1 - LSB D E integral non-linearity - 1.5 - LSB L(adj) E offset error - 0.6 - % O E gain error - 0.6 - % G C load capacitance - 200 - pF L R load resistance 1 - - k L LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 73 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 14. Application information 14.1 LCD panel signal usage Table 20. LCD panel co nnections for STN single panel mode External pin 4-bit mono STN single panel 8-bit mono STN single panel Color STN single panel LPC2478 pin LCD function LPC2478 pin LCD function LPC2478 pin LCD function used used used LCDVD[23] - - - - - - LCDVD[22] - - - - - - LCDVD[21] - - - - - - LCDVD[20] - - - - - - LCDVD[19] - - - - - - LCDVD[18] - - - - - - LCDVD[17] - - - - - - LCDVD[16] - - - - - - LCDVD[15] - - - - - - LCDVD[14] - - - - - - LCDVD[13] - - - - - - LCDVD[12] - - - - - - LCDVD[11] - - - - - - LCDVD[10] - - - - - - LCDVD[9] - - - - - - LCDVD[8] - - - - - - LCDVD[7] - - P4[29][3] UD[7] P4[29][3] UD[7] LCDVD[6] - - P4[28][3] UD[6] P4[28][3] UD[6] LCDVD[5] - - P2[13][2] UD[5] P2[13][2] UD[5] LCDVD[4] - - P2[12][2] UD[4] P2[12][2] UD[4] LCDVD[3] P2[9][1] UD[3] P2[9][1] UD[3] P2[9][1] UD[3] LCDVD[2] P2[8][1] UD[2] P2[8][1] UD[2] P2[8][1] UD[2] LCDVD[1] P2[7][1] UD[1] P2[7][1] UD[1] P2[7][1] UD[1] LCDVD[0] P2[6][1] UD[0] P2[6][1] UD[0] P2[6][1] UD[0] LCDLP P2[5][1] LCDLP P2[5][1] LCDLP P2[5][1] LCDLP LCDENAB/ P2[4][1] LCDENAB/ P2[4][1] LCDENAB/ P2[4][1] LCDENAB/ LCDM LCDM LCDM LCDM LCDFP P2[3][1] LCDFP P2[3][1] LCDFP P2[3][1] LCDFP LCDDCLK P2[2][1] LCDDCLK P2[2][1] LCDDCLK P2[2][1] LCDDCLK LCDLE P2[1][1] LCDLE P2[1][1] LCDLE P2[1][1] LCDLE LCDPWR P2[0][1] CDPWR P2[0][1] LCDPWR P2[0][1] LCDPWR LCDCLKIN P2[11][2] LCDCLKIN P2[11][2] LCDCLKIN P2[0][2] LCDPWR [1] ETM replaced with LCD pins. [2] External interrupt pins EINT1, EINT2, EINT3 replaced with LCD pins. [3] Timer pins MAT2[0] and MAT2[1] replaced with LCD pins. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 74 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 21. LCD panel co nnections for STN dual panel mode External pin 4-bit mono STN dual panel 8-bit mono STN dual panel Color STN dual panel LPC2478 pin LCD function LPC2478 pin LCD function LPC2478 pin LCD function used used used LCDVD[23] - - - - - - LCDVD[22] - - - - - - LCDVD[21] - - - - - - LCDVD[20] - - - - - - LCDVD[19] - - - - - - LCDVD[18] - - - - - - LCDVD[17] - - - - - - LCDVD[16] - - - - - - LCDVD[15] - - P1[29][4] LD[7] P1[29][4] LD[7] LCDVD[14] - - P1[28][4] LD[6] P1[28][4] LD[6] LCDVD[13] - - P1[27][4] LD[5] P1[27][4] LD[5] LCDVD[12] - P1[26][4] LD[4] P1[26][4] LD[4] LCDVD[11] P4[29][3] LD[3] P1[25][4] LD[3] P1[25][4] LD[3] LCDVD[10] P4[28][3] LD[2] P1[24][4] LD[2] P1[24][4] LD[2] LCDVD[9] P2[13][2] LD[1] P1[23][4] LD[1] P1[23][4] LD[1] LCDVD[8] P2[12][2] LD[0] P1[22][4] LD[0] P1[22][4] LD[0] LCDVD[7] - - P1[21][4] UD[7] P1[21][4] UD[7] LCDVD[6] - - P1[20][4] UD[6] P1[20][4] UD[6] LCDVD[5] - - P2[13][2] UD[5] P2[13][2] UD[5] LCDVD[4] - - P2[12][2] UD[4] P2[12][2] UD[4] LCDVD[3] P2[9][1] UD[3] P2[9][1] UD[3] P2[9][1] UD[3] LCDVD[2] P2[8][1] UD[2] P2[8][1] UD[2] P2[8][1] UD[2] LCDVD[1] P2[7][1] UD[1] P2[7][1] UD[1] P2[7][1] UD[1] LCDVD[0] P2[6][1] UD[0] P2[6][1] UD[0] P2[6][1] UD[0] LCDLP P2[5][1] LCDLP P2[5][1] LCDLP P2[5][1] LCDLP LCDENAB/ P2[4][1] LCDENAB/ P2[4][1] LCDENAB/ P2[4][1] LCDENAB/ LCDM LCDM LCDM LCDM LCDFP P2[3][1] LCDFP P2[3][1] LCDFP P2[3][1] LCDFP LCDDCLK P2[2][1] LCDDCLK P2[2][1] LCDDCLK P2[2][1] LCDDCLK LCDLE P2[1][1] LCDLE P2[1][1] LCDLE P2[1][1] LCDLE LCDPWR P2[0][1] LCDPWR P2[0][1] LCDPWR P2[0][1] LCDPWR LCDCLKIN P2[11][2] LCDCLKIN P2[11][2] LCDCLKIN P2[11][2] LCDCLKIN [1] ETM replaced by LCD pins. [2] External interrupt pins EINT1, EINT2, EINT3 replaced with LCD pins. [3] Timer pins MAT2[0] and MAT2[1] replaced with LCD pins. [4] USB OTG pins replaced by LCD pins. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 75 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 22. LCD panel co nnections for TFT panels External TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) TFT 16 bit (1:5:5:5 mode) TFT 24 bit pin LPC2478 LCD LPC2478 LCD LPC2478 pin LCD LPC2478 LCD pin used function pin used function used function pin used function LCDVD[23] P1[29][4] BLUE3 P1[29][4] BLUE4 P1[29][4] BLUE4 P1[29][4] BLUE7 LCDVD[22] P1[28][4] BLUE2 P1[28][4] BLUE3 P1[28][4] BLUE3 P1[28][4] BLUE6 LCDVD[21] P1[27][4] BLUE1 P1[27][4] BLUE2 P1[27][4] BLUE2 P1[27][4] BLUE5 LCDVD[20] P1[26][4] BLUE0 P1[26][4] BLUE1 P1[26][4] BLUE1 P1[26][4] BLUE4 LCDVD[19] - - P2[13][2] BLUE0 P2[13][2] BLUE0 P2[13][2] BLUE3 LCDVD[18] - - - - P2[12][2] intensity P2[12][2] BLUE2 LCDVD[17] - - - - - - P0[9][5] BLUE1 LCDVD[16] - - - - - - P0[8][5] BLUE0 LCDVD[15] P1[25][4] GREEN3 P1[25][4] GREEN5 P1[25][4] GREEN4 P1[25][4] GREEN7 LCDVD[14] P1[24][4] GREEN2 P1[24][4] GREEN4 P1[24][4] GREEN3 P1[24][4] GREEN6 LCDVD[13] P1[23][4] GREEN1 P1[23][4] GREEN3 P1[23][4] GREEN2 P1[23][4] GREEN5 LCDVD[12] P1[22][4] GREEN0 P1[22][4] GREEN2 P1[22][4] GREEN1 P1[22][4] GREEN4 LCDVD[11] - - P1[21][4] GREEN1 P1[21][4] GREEN0 P1[21][4] GREEN3 LCDVD[10] - - P1[20][4] GREEN0 P1[20][4] intensity P1[20][4] GREEN2 LCDVD[9] - - - - - - P0[7][5] GREEN1 LCDVD[8] - - - - - - P0[6][5] GREEN0 LCDVD[7] P2[9][1] RED3 P2[9][1] RED4 P2[9][1] RED4 P2[9][1] RED7 LCDVD[6] P2[8][1] RED2 P2[8][1] RED3 P2[8][1] RED3 P2[8][1] RED6 LCDVD[5] P2[7][1] RED1 P2[7][1] RED2 P2[7][1] RED2 P2[7][1] RED5 LCDVD[4] P2[6][1] RED0 P2[6][1] RED1 P2[6][1] RED1 P2[6][1] RED4 LCDVD[3] - - P2[12][2] RED0 P4[29][3] RED0 P4[29][3] RED3 LCDVD[2] - - - - P4[28][3] intensity P4[28][3] RED2 LCDVD[1] - - - - - - P0[5][5] RED1 LCDVD[0] - - - - - - P0[4][5] RED0 LCDLP P2[5][1] LCDLP P2[5][1] LCDLP P2[5][1] LCDLP P2[5][1] LCDLP LCDENAB/ P2[4][1] LCDENAB/ P2[4][1] LCDENAB/ P2[4][1] LCDENAB/ P2[4][1] LCDENAB/L LCDM LCDM LCDM LCDM CDM LCDFP P2[3][1] LCDFP P2[3][1] LCDFP P2[3][1] LCDFP P2[3][1] LCDFP LCDDCLK P2[2][1] LCDDCLK P2[2][1] LCDDCLK P2[2][1] LCDDCLK P2[2][1] LCDDCLK LCDLE P2[1][1] LCDLE P2[1][1] LCDLE P2[1][1] LCDLE P2[1][1] LCDLE LCDPWR P2[0][1] LCDPWR P2[0][1] LCDPWR P2[0][1] LCDPWR P2[0][1] LCDPWR LCDCLKIN P2[11][2] LCDCLKIN P2[11][2] LCDCLKIN P2[11][2] LCDCLKIN P2[11][2] LCDCLKIN [1] ETM replaced by LCD pins. [2] External interrupt pins EINT1, EINT2, EINT3 replaced by LCD pins. [3] Timer pins MAT2[0] and MAT2[1] replaced by LCD pins. [4] USB OTG pins replaced by LCD pins. [5] I2S pins replaced by LCD pins. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 76 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 14.2 Suggested USB interface solutions VDD(3V3) USB_UP_LED USB_CONNECT LPC24XX soft-connect switch R1 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB-B connector USB_D− RS = 33 Ω VSSIO, VSSCORE 002aad587 Fig 21. LPC2478 USB interface on a self-powered device VDD(3V3) R2 LPC24XX R1 USB_UP_LED 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB-B connector USB_D− RS = 33 Ω VSSIO, VSSCORE 002aad588 Fig 22. LPC2478 USB interface on a bus-powered device LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 77 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller VDD R1 R2 R3 R4 RSTOUT RESET_N VBUS ADR/PSW ID VDD OE_N/INT_N DP 33 Ω Mini-AB SPEED DM 33 Ω connector SUSPEND ISP1302 R4 R5 R6 VSSIO, USB_SCL1 SCL VSSCORE USB_SDA1 SDA USB_INT1 INT_N USB_D+1 USB_D−1 VDD USB_UP_LED1 R7 LPC24XX 5 V VDD IN OUTA LM3526-L USB_PPWR2 ENA FLAGA USB_OVRCR2 USB_PWRD2 VBUS USB_D+2 33 Ω D+ USB-A USB_D−2 33 Ω D− connector 15 kΩ 15 kΩ VSSIO, VSSCORE VDD USB_UP_LED2 R8 002aad589 Fig 23. LPC2478 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 78 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller VDD RSTOUT RESET_N USB_TX_E1 OE_N/INT_N USB_TX_DP1 DAT_VP USB_TX_DM1 SE0_VM USB_RCV1 RCV USB_RX_DP1 VP VBUS USB_RX_DM1 VM ID VDD DP 33 Ω USB MINI-AB ISP1302 connector DM 33 Ω LPC24XX ADR/PSW VSSIO, SPEED VSSCORE SUSPEND USB_SCL1 SCL USB_SDA1 SDA USB_INT1 INT_N VDD USB_UP_LED1 002aad590 Fig 24. LPC2478 USB OTG port configuration: VP_VM mode LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 79 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller VDD USB_UP_LED1 VSSIO, VSSCORE USB_D+1 33 Ω D+ USB_D−1 33 Ω D− USB-A 15 kΩ 15 kΩ connector VDD USB_PWRD1 VBUS USB_OVRCR1 USB_PPWR1 ENA FLAGA 5 V OUTA LM3526-L IN LPC24XX VDD USB_UP_LED2 VDD USB_CONNECT2 VSSIO, VSSCORE USB_D+2 33 Ω D+ USB_D−2 33 Ω D− UcoSnBn-eBctor VBUS VBUS 002aad595 Fig 25. LPC2478 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 80 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller VDD USB_UP_LED1 VSSIO, VSSCORE USB_D+1 33 Ω D+ USB_D−1 33 Ω D− USB-A 15 kΩ 15 kΩ connector VDD USB_PWRD1 VBUS USB_OVRCR1 USB_PPWR1 ENA FLAGA 5 V OUTA VDD IN LM3526-L OUTB LPC24XX USB_PPWR2 ENB FLAGB USB_OVRCR2 USB_PWRD2 VBUS USB_D+2 33 Ω D+ USB-A connector USB_D−2 33 Ω D− 15 kΩ 15 kΩ VSSIO, VSSCORE VDD USB_UP_LED2 002aad596 Fig 26. LPC2478 USB OTG port configuration: USB port 1 host, USB port 2 host 14.3 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with C = 100 pF. To limit the input voltage to the specified range, choose an additional i capacitor to ground C which attenuates the input voltage by a factor C / (C + C ). In g i i g slave mode, a minimum of 200 mV (RMS) is needed. LPC2xxx XTAL1 Ci Cg 100 pF 002aae718 Fig 27. Slave mode operation of the on-chip oscillator LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 81 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller In slave mode the input clock signal should be coupled by means of a capacitor of 100pF (Figure27), with an amplitude between 200mV(RMS) and 1000mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTAL2 pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure28 and in Table23 and Table24. Since the feedback resistance is integrated on chip, only a crystal and the capacitances C and C need to be connected externally in case of X1 X2 fundamental mode oscillation (the fundamental frequency is represented by L, C and L R ). Capacitance C in Figure28 represents the parallel package capacitance and should S P not be larger than 7 pF. Parameters F , C , R and C are supplied by the crystal OSC L S P manufacturer. LPC2xxx L XTAL1 XTAL2 = CL CP XTAL RS CX1 CX2 002aag469 Fig 28. Oscillator modes and models: oscillation mode of operation and external crystal model used for C /C evaluation X1 X2 Table 23. Recommended values for C /C in oscillation mode (crystal and external X1 X2 components parameters): low frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency F capacitance C series resistance R capacitors C /C OSC L S X1 X2 1MHz to 5MHz 10 pF < 300 18 pF, 18 pF 20 pF < 300 39 pF, 39 pF 30 pF < 300 57pF, 57pF 5MHz to 10MHz 10 pF < 300 18 pF, 18 pF 20 pF < 200 39 pF, 39 pF 30 pF < 100 57 pF, 57 pF 10MHz to 15MHz 10 pF < 160 18 pF, 18 pF 20 pF < 60 39 pF, 39 pF 15MHz to 20MHz 10 pF < 80 18 pF, 18 pF LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 82 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Table 24. Recommended values for C /C in oscillation mode (crystal and external X1 X2 components parameters): high frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency F capacitance C series resistance R capacitors C , C OSC L S X1 X2 15MHz to 20MHz 10 pF < 180 18 pF, 18 pF 20 pF < 100 39 pF, 39 pF 20MHz to 25MHz 10 pF < 160 18 pF, 18 pF 20 pF < 80 39 pF, 39 pF 14.4 RTC 32 kHz oscillator component selection LPC2xxx L RTCX1 RTCX2 = CL CP 32 kHz XTAL RS CX1 CX2 002aaf495 Fig 29. RTC oscillator modes and models: oscillation mode of operation and external crystal model used for C /C evaluation X1 X2 The RTC external oscillator circuit is shown in Figure29. Since the feedback resistance is integrated on chip, only a crystal, the capacitances C and C need to be connected X1 X2 externally to the microcontroller. Table25 gives the crystal parameters that should be used. C is the typical load L capacitance of the crystal and is usually specified by the crystal manufacturer. The actual C influences oscillation frequency. When using a crystal that is manufactured for a L different load capacitance, the circuit will oscillate at a slightly different frequency (depending on the quality of the crystal) compared to the specified one. Therefore for an accurate time reference it is advised to use the load capacitors as specified in Table25 that belong to a specific C . The value of external capacitances C and C specified in L X1 X2 this table are calculated from the internal parasitic capacitances and the C . Parasitics L from PCB and package are not taken into account. Table 25. Recommended values for the RTC external 32kHz oscillator C /C components X1 X2 Crystal load capacitance Maximum crystal series External load capacitors C /C X1 X2 C resistance R L S 11 pF < 100k 18pF, 18pF 13 pF < 100k 22pF, 22pF 15 pF < 100k 27pF, 27pF LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 83 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 14.5 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C , C , and C in case of x1 x2 x3 third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C and C should be chosen smaller x1 x2 accordingly to the increase in parasitics of the PCB layout. 14.6 Standard I/O pin configuration Figure30 shows the possible pin modes for standard I/O pins with analog input function: • Digital output driver • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Analog input (for ADC input channels) The default configuration for standard I/O pins is input with pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. VDD output enable ESD pin configured as digital output output PIN driver ESD VDD VSS weak pull-up pull-up enable weak pin configured pull-down as digital input pull-down enable data input select analog input pin configured as analog input analog input 002aaf496 Fig 30. Standard I/O pin configuration with analog input LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 84 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 14.7 Reset pin configuration VDD VDD VDD Rpu ESD 20 ns RC reset PIN GLITCH FILTER ESD VSS 002aaf274 Fig 31. Reset pin configuration LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 85 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 15. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1 c y X A 105 156 157 104 ZE e E HE A A2 A1 (A 3 ) wM θ bp Lp L pin 1 index detail X 53 208 1 52 wM ZD v M A e bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HD HE L Lp v w y ZD ZE θ 0.15 1.45 0.27 0.20 28.1 28.1 30.15 30.15 0.75 1.43 1.43 7o mm 1.6 0.05 1.35 0.25 0.17 0.09 27.9 27.9 0.5 29.85 29.85 1 0.45 0.12 0.08 0.08 1.08 1.08 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 00-02-06 SOT459-1 136E30 MS-026 03-02-20 Fig 32. Package outline SOT459-1 (LQFP208) LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 86 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 15 x 15 x 0.7 mm SOT950-1 D B A ball A1 index area E A A2 A1 detail X e1 C ∅ v M C A B e b ∅ wM C y1C y U T R P N M L e K J e2 H G F E D C B A ball A1 1 3 5 7 9 11 13 15 17 index area 2 4 6 8 10 12 14 16 X 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max A1 A2 b D E e e1 e2 v w y y1 0.4 0.8 0.5 15.1 15.1 mm 1.2 0.8 12.8 12.8 0.15 0.08 0.12 0.1 0.3 0.6 0.4 14.9 14.9 OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 06-06-01 SOT950-1 - - - 06-06-14 Fig 33. Package outline SOT950-1 (TFBGA208) LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 87 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 16. Abbreviations Table 26. Acronym list Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BLS Byte Lane Select BOD BrownOut Detection CAN Controller Area Network DAC Digital-to-Analog Converter DCC Debug Communication Channel DMA Direct Memory Access EOP End Of Packet ETM Embedded Trace Macrocell GP General Purpose GPIO General Purpose Input/Output IrDA Infrared Data Association JTAG Joint Test Action Group LCD Liquid Crystal Display MCI Multimedia Card Interface MII Media Independent Interface MIIM Media Independent Interface Management OHC Open Host Controller OHCI Open Host Controller Interface OTG On-The-Go PHY PHYsical layer PLL Phase-Locked Loop PWM Pulse Width Modulator RMII Reduced Media Independent Interface SD Secure Digital SD/MMC Secure Digital/MultiMedia Card SE0 Single Ended Zero SPI Serial Peripheral Interface SSI Synchronous Serial Interface SSP Synchronous Serial Port TTL Transistor-Transistor Logic UART Universal Asynchronous Receiver/Transmitter USB Universal Serial Bus LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 88 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 17. Revision history Table 27. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC2478 v.3.1 20131016 Product data sheet - LPC2478 v.3 Modifications: • Table 4 “Pin description”, Table note6: Changed glitch filter spec from 5 ns to 10 ns. • Table 10 “Dynamic characteristics”: Changed min clock cycle time from 42 to 40. • Table 17 “Dynamic characteristics: Dynamic external memory interface”: Changed t typ d(QV) and max. LPC2478 v.3 20110912 Product data sheet - LPC2478 v.2 Modifications: • Table 4 “Pin description”: Updated description for USB_UP_LED1 and USB_UP_LED2. • Table 6 “Limiting values”: Added “non-operating” to conditions column of T . stg • Table 6 “Limiting values”: Updated Table note [5]. • Table 8 “Thermal resistance value (C/W): ±15 %”: Added new table. • Table 9 “Static characteristics”: Changed V typ value from 0.5V to 0.05V . hys DD(3V3) DD(3V3) • Table 14 “Dynamic characteristics of flash”: Updated table. • Table 15 “Dynamic characteristics: Static external memory interface”: Removed “AHB clock = 1 MHz”. • Table 15 “Dynamic characteristics: Static external memory interface”: Swapped min/max values for t . am • Table 15 “Dynamic characteristics: Static external memory interface”: Updated t WEHDNV spec. • Table 16 “Dynamic characteristics: Dynamic external memory interface”: Removed “AHB clock = 1 MHz”. • Table 17 “Dynamic characteristics: Dynamic external memory interface”: Added new table. • Section 14.6 “Standard I/O pin configuration” Updated bullets. LPC2478 v.2 20100929 Product data sheet - LPC2478 v.1 LPC2478 v.1 20081111 Preliminary data sheet - - LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 89 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 18.2 Definitions Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Draft — The document is a draft version only. The content is still under malfunction of an NXP Semiconductors product can reasonably be expected internal review and subject to formal approval, which may result in to result in personal injury, death or severe property or environmental modifications or additions. NXP Semiconductors does not give any damage. NXP Semiconductors and its suppliers accept no liability for representations or warranties as to the accuracy or completeness of inclusion and/or use of NXP Semiconductors products in such equipment or information included herein and shall have no liability for the consequences of applications and therefore such inclusion and/or use is at the customer’s own use of such information. risk. Short data sheet — A short data sheet is an extract from a full data sheet Applications — Applications that are described herein for any of these with the same product type number(s) and title. A short data sheet is intended products are for illustrative purposes only. NXP Semiconductors makes no for quick reference only and should not be relied upon to contain detailed and representation or warranty that such applications will be suitable for the full information. For detailed and full information see the relevant full data specified use without further testing or modification. sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications full data sheet shall prevail. and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the NXP data sheet shall define the specification of the product as agreed between Semiconductors product is suitable and fit for the customer’s applications and NXP Semiconductors and its customer, unless NXP Semiconductors and products planned, as well as for the planned application and use of customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate shall an agreement be valid in which the NXP Semiconductors product is design and operating safeguards to minimize the risks associated with their deemed to offer functions and qualities beyond those described in the applications and products. Product data sheet. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the 18.3 Disclaimers customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Limited warranty and liability — Information in this document is believed to Semiconductors products in order to avoid a default of the applications and be accurate and reliable. However, NXP Semiconductors does not give any the products or of the application or use by customer’s third party representations or warranties, expressed or implied, as to the accuracy or customer(s). NXP does not accept any liability in this respect. completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no Limiting values — Stress above one or more limiting values (as defined in responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC60134) will cause permanent source outside of NXP Semiconductors. damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in In no event shall NXP Semiconductors be liable for any indirect, incidental, the Recommended operating conditions section (if present) or the punitive, special or consequential damages (including - without limitation - lost Characteristics sections of this document is not warranted. Constant or profits, lost savings, business interruption, costs related to the removal or repeated exposure to limiting values will permanently and irreversibly affect replacement of any products or rework charges) whether or not such the quality and reliability of the device. damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards sale, as published at http://www.nxp.com/profile/terms, unless otherwise customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual with the Terms and conditions of commercial sale of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to Right to make changes — NXP Semiconductors reserves the right to make applying the customer’s general terms and conditions with regard to the changes to information published in this document, including without purchase of NXP Semiconductors products by customer. limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 90 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller Export control — This document as well as the item(s) described herein whenever customer uses the product for automotive applications beyond may be subject to export control regulations. Export might require a prior NXP Semiconductors’ specifications such use shall be solely at customer’s authorization from competent authorities. own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and Non-automotive qualified products — Unless this data sheet expressly use of the product for automotive applications beyond NXP Semiconductors’ states that this specific NXP Semiconductors product is automotive qualified, standard warranty and NXP Semiconductors’ product specifications. the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of 18.4 Trademarks non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in Notice: All referenced brands, product names, service names and trademarks automotive applications to automotive specifications and standards, customer are the property of their respective owners. (a) shall use the product without NXP Semiconductors’ warranty of the I2C-bus — logo is a trademark of NXP B.V. product for such automotive applications, use and specifications, and (b) 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 91 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 20. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 7.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 7.23 Pulse width modulator . . . . . . . . . . . . . . . . . . 43 7.23.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.24 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 44 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 7.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4 7.25 RTC and battery RAM . . . . . . . . . . . . . . . . . . 44 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.25.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6 7.26 Clocking and power control . . . . . . . . . . . . . . 45 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.26.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 45 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7.26.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 45 7 Functional description . . . . . . . . . . . . . . . . . . 28 7.26.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 45 7.26.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 46 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 28 7.26.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2 On-chip flash programming memory . . . . . . . 29 7.26.3 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 46 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 29 7.26.4 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 47 7.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.26.4.1 Idle mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 31 7.26.4.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 32 7.26.4.3 Power-down mode. . . . . . . . . . . . . . . . . . . . . 47 7.6 Pin connect block. . . . . . . . . . . . . . . . . . . . . . 32 7.26.4.4 Deep power-down mode . . . . . . . . . . . . . . . . 48 7.7 External memory controller. . . . . . . . . . . . . . . 32 7.26.4.5 Power domains . . . . . . . . . . . . . . . . . . . . . . . 48 7.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.27 System control. . . . . . . . . . . . . . . . . . . . . . . . 49 7.8 General purpose DMA controller . . . . . . . . . . 33 7.27.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.8.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.27.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 49 7.9 Fast general purpose parallel I/O. . . . . . . . . . 34 7.27.3 Code security 7.9.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 (Code Read Protection - CRP) . . . . . . . . . . . 49 7.10 LCD controller. . . . . . . . . . . . . . . . . . . . . . . . . 35 7.27.4 AHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.10.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.27.5 External interrupt inputs. . . . . . . . . . . . . . . . . 50 7.11 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.27.6 Memory mapping control. . . . . . . . . . . . . . . . 50 7.11.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.28 Emulation and debugging . . . . . . . . . . . . . . . 50 7.12 USB interface. . . . . . . . . . . . . . . . . . . . . . . . . 37 7.28.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 50 7.12.1 USB device controller. . . . . . . . . . . . . . . . . . . 37 7.28.2 Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 51 7.12.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.28.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.12.2 USB host controller. . . . . . . . . . . . . . . . . . . . . 37 7.12.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 52 7.12.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 38 9 Thermal characteristics . . . . . . . . . . . . . . . . . 53 7.12.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10 Static characteristics . . . . . . . . . . . . . . . . . . . 54 7.13 CAN controller and acceptance filters . . . . . . 38 10.1 Power-down mode. . . . . . . . . . . . . . . . . . . . . 57 7.13.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.2 Deep power-down mode . . . . . . . . . . . . . . . . 58 7.14 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.3 Electrical pin characteristics. . . . . . . . . . . . . . 60 7.14.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11 Dynamic characteristics. . . . . . . . . . . . . . . . . 61 7.15 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.1 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 62 7.15.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.2 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.16 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.3 USB interface. . . . . . . . . . . . . . . . . . . . . . . . . 62 7.16.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 63 7.17 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 40 11.5 Static external memory interface . . . . . . . . . . 64 7.17.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.6 Dynamic external memory interface . . . . . . . 66 7.18 SSP serial I/O controller. . . . . . . . . . . . . . . . . 40 11.7 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.18.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.19 SD/MMC card interface . . . . . . . . . . . . . . . . . 40 12 ADC electrical characteristics. . . . . . . . . . . . 70 7.19.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 13 DAC electrical characteristics. . . . . . . . . . . . 73 7.20 I2C-bus serial I/O controller . . . . . . . . . . . . . . 41 14 Application information . . . . . . . . . . . . . . . . . 74 7.20.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 14.1 LCD panel signal usage. . . . . . . . . . . . . . . . . 74 7.21 I2S-bus serial I/O controllers. . . . . . . . . . . . . . 41 14.2 Suggested USB interface solutions. . . . . . . . 77 7.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 14.3 Crystal oscillator XTAL input and 7.22 General purpose 32-bit timers/external event component selection . . . . . . . . . . . . . . . . . . . 81 counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 14.4 RTC 32 kHz oscillator component selection . 83 LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 16 October 2013 92 of 93

LPC2478 NXP Semiconductors Single-chip 16-bit/32-bit microcontroller 14.5 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . 84 14.6 Standard I/O pin configuration . . . . . . . . . . . . 84 14.7 Reset pin configuration. . . . . . . . . . . . . . . . . . 85 15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 86 16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 88 17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 89 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 90 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 90 18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 90 18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 91 19 Contact information. . . . . . . . . . . . . . . . . . . . . 91 20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 October 2013 Document identifier: LPC2478