Product Overview The DW1000 is a fully integrated single chip Ultra Wideband (UWB) low-power low-cost transceiver IC compliant to IEEE802.15.4-2011. It can be used in 2-way ranging or TDOA location systems to locate assets to a precision of 10 cm. It also supports data transfer at rates up to 6.8 Mbps Key Features Key Benefits  IEEE802.15.4-2011 UWB  Supports precision location and compliant data transfer concurrently  Supports 6 RF bands from  Asset location to a precision of 3.5 GHz to 6.5 GHz 10 cm D  Programmable transmitter  Extended communications output power range up to 290 m @ 110 kbps W  Fully coherent receiver for 10% PER minimises required maximum range and accuracy infrastructure in RTLS 1  Complies with FCC & ETSI  High multipath fading immunity 0 UWB spectral masks  Supports high tag densities in 0  Supply voltage 2.8 V to 3.6 V RTLS 0  Low power consumption  Small PCB footprint allows cost-  SLEEP mode current 1 µA effective hardware  DEEP SLEEP mode current 50 implementations IE nA  Long battery life minimises E  Data rates of 110 kbps, 850 system lifetime cost E kbps, 6.8 Mbps 8 Applications  Maximum packet length of 0 1023 bytes for high data 2 throughput applications  Precision real time location .1  Integrated MAC support systems (RTLS) using two-way 5 features ranging or TDOA schemes in a .4 variety of markets: -  Supports 2-way ranging and - o Healthcare 2 TDOA o Consumer 0  SPI interface to host processor 1 o Industrial  6 mm x 6 mm 48-pin QFN 1 o Other package with 0.4 mm lead pitch  Location aware wireless sensor U  Small number of external networks W components B T r a ANALOG RECEIVER POWER MANAGEMENT n R s E V c EI C e S PLL / CLOCK GENERATOR AN HOST INTERFACE / SPI TO HOST i R v T L e A GIT r DI ANALOG TRANSMITTER STATE CONTROLLER DW1000 High Level Block Diagram

DW1000 Datasheet Table of Contents 1 IC DESCRIPTION ........................................... 5 5.11 INTERRUPTS AND DEVICE STATUS ............... 25 5.12 MAC FEATURES ..................................... 25 2 PIN CONNECTIONS ....................................... 6 5.12.1 Timestamping ............................. 25 2.1 PIN NUMBERING .......................................... 6 5.12.2 FCS Generation and Checking ..... 25 2.2 PIN DESCRIPTIONS ........................................ 6 5.12.3 Automatic Frame Filtering .......... 25 5.12.4 Automatic Acknowledge ............. 26 3 ELECTRICAL SPECIFICATIONS ...................... 10 5.12.5 Double Receive Buffer ................. 26 3.1 NOMINAL OPERATING CONDITIONS ............... 10 5.13 EXTERNAL SYNCHRONIZATION ................... 26 3.2 DC CHARACTERISTICS .................................. 10 5.14 CALIBRATION AND SPECTRAL TUNING OF THE 3.3 RECEIVER AC CHARACTERISTICS .................... 10 DW1000 26 3.4 RECEIVER SENSITIVITY CHARACTERISTICS ......... 11 5.14.1 Introduction ................................ 26 3.5 REFERENCE CLOCK AC CHARACTERISTICS ........ 11 5.14.2 Crystal Oscillator Trim ................. 26 3.5.1 Reference Frequency ...................... 11 5.14.3 Transmitter Calibration ............... 27 3.6 TRANSMITTER AC CHARACTERISTICS .............. 12 5.14.4 Antenna Delay Calibration .......... 27 3.7 TEMPERATURE AND VOLTAGE MONITOR 6 OPERATIONAL STATES AND POWER CHARACTERISTICS .................................................. 12 MANAGEMENT .................................................. 28 3.8 ABSOLUTE MAXIMUM RATINGS .................... 12 6.1 OVERVIEW ................................................ 28 4 TYPICAL PERFORMANCE ............................ 13 6.2 OPERATING STATES AND THEIR EFFECT ON POWER 5 FUNCTIONAL DESCRIPTION ........................ 17 CONSUMPTION...................................................... 28 6.3 TRANSMIT AND RECEIVE POWER PROFILES ....... 29 5.1 PHYSICAL LAYER MODES .............................. 17 6.3.1 Typical transmit profile ................... 32 5.1.1 Supported Channels and Bandwidths 6.3.2 Typical receive profiles.................... 32 17 5.1.2 Supported Bit Rates and Pulse 7 POWER SUPPLY .......................................... 33 Repetition Frequencies (PRF) ........................ 17 7.1 POWER SUPPLY CONNECTIONS ...................... 33 5.1.3 Frame Format ................................. 17 7.2 USE OF EXTERNAL DC / DC CONVERTER ......... 33 5.1.4 Symbol Timings .............................. 18 7.3 POWERING DOWN THE DW1000 .................. 34 5.1.5 Proprietary Long Frames ................ 18 5.1.6 Turnaround Times .......................... 18 8 APPLICATION INFORMATION ...................... 35 5.1.7 Frame Filter .................................... 18 8.1 APPLICATION CIRCUIT DIAGRAM .................... 35 5.1.8 Frame Check Sequence (FCS) .......... 19 8.2 RECOMMENDED COMPONENTS ..................... 35 5.2 REFERENCE CRYSTAL OSCILLATOR .................. 19 8.3 APPLICATION CIRCUIT LAYOUT ...................... 36 5.3 SYNTHESIZER ............................................. 19 8.3.1 PCB Stack ........................................ 36 5.4 RECEIVER .................................................. 19 8.3.2 RF Traces ......................................... 36 5.4.1 Bandwidth setting .......................... 19 8.3.3 PLL Loop Filter Layout ..................... 37 5.4.2 Automatic Gain Control (AGC) ....... 19 8.3.4 Decoupling Layout .......................... 37 5.5 TRANSMITTER ............................................ 19 8.3.5 Layout Guidance ............................. 37 5.5.1 Transmit Output Power .................. 19 5.5.2 Transmit Bandwidth Setting ........... 19 9 PACKAGING & ORDERING INFORMATION .. 38 5.6 POWER-UP SEQUENCE ................................. 20 9.1 PACKAGE DIMENSIONS ................................ 38 5.6.1 Typical power-up sequence ............ 20 9.2 DEVICE PACKAGE MARKING .......................... 39 5.6.2 Variation in the power-up sequence 9.3 TRAY INFORMATION .................................... 39 20 9.4 TAPE & REEL INFORMATION ......................... 40 5.6.3 External control of RSTn / use of RSTn 9.4.1 Important note ............................... 40 by external circuitry ...................................... 21 9.4.2 Tape Orientation and Dimensions .. 40 5.7 VOLTAGE/TEMPERATURE MONITORS ............. 21 9.4.3 Reel Information: 330 mm Reel ...... 40 5.8 HOST CONTROLLER INTERFACE ...................... 21 9.4.4 Reel Information: 180 mm reel ....... 41 5.8.1 Configuring the SPI Mode ............... 23 9.5 REFLOW PROFILE ........................................ 42 5.8.2 SPI Signal Timing ............................ 24 9.6 ORDERING INFORMATION ............................ 42 5.9 GENERAL PURPOSE INPUT OUTPUT (GPIO) .... 24 5.10 MEMORY .............................................. 24 10 GLOSSARY ............................................... 43 5.10.1 Receive and Transmit data buffers 11 REFERENCES ............................................ 44 25 5.10.2 Accumulator memory ................. 25 12 DOCUMENT HISTORY .............................. 44 5.10.3 One Time Programmable (OTP) 13 MAJOR CHANGES .................................... 44 Calibration Memory ...................................... 25 © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 2

DW1000 Datasheet 14 ABOUT DECAWAVE ................................ 47 List of Figures FIGURE 1: IC BLOCK DIAGRAM ...................................... 5 RSTN GOING HIGH ............................................. 20 FIGURE 2: DW1000 PIN ASSIGNMENTS ......................... 6 FIGURE 22: DW1000 SPIPHA=0 TRANSFER PROTOCOL 22 FIGURE 3 : RX INTERFERER IMMUNITY ON CHANNEL 2 ..... 13 FIGURE 23: DW1000SPIPHA=1 TRANSFER PROTOCOL . 22 FIGURE 4: TX OUTPUT POWER OVER TEMP & VOLTAGE ... 13 FIGURE 24: SPI BYTE FORMATTING ............................. 22 FIGURE 5: RECEIVER SENSITIVITY CHANNEL 5 110KBPS DATA FIGURE 25: SPI CONNECTIONS .................................... 23 RATE 16 MHZ PRF 2048 PREAMBLE SYMBOLS ...... 13 FIGURE 26: DW1000 SPI TIMING DIAGRAM ............... 24 FIGURE 6: RECEIVER SENSITIVITY CHANNEL 5 110KBPS DATA FIGURE 27: DW1000 SPI DETAILED TIMING DIAGRAM .. 24 RATE 64 MHZ PRF 2048 PREAMBLE SYMBOLS ...... 14 FIGURE 28: SYNC SIGNAL TIMING RELATIVE TO XTAL1 .... 26 FIGURE 7: RECEIVER SENSITIVITY CHANNEL 5 850KBPS DATA FIGURE 29: TYPICAL DEVICE CRYSTAL TRIM PPM RATE 16 MHZ PRF 1024 PREAMBLE SYMBOLS ...... 14 ADJUSTMENT .................................................... 27 FIGURE 8: RECEIVER SENSITIVITY CHANNEL 5 850KBPS DATA FIGURE 30: SLEEP OPTIONS BETWEEN OPERATIONS ......... 29 RATE 64 MHZ PRF 1024 PREAMBLE SYMBOLS ...... 14 FIGURE 31: TYPICAL RANGE VERSUS TX AVERAGE CURRENT FIGURE 9: RECEIVER SENSITIVITY CHANNEL 5 6.81MBPS (CHANNEL 2)..................................................... 31 DATA RATE 16 MHZ PRF 256 PREAMBLE SYMBOLS 15 FIGURE 32: TYPICAL TX POWER PROFILE ....................... 32 FIGURE 10: RECEIVER SENSITIVITY CHANNEL 5 6.81MBPS FIGURE 33: TYPICAL RX POWER PROFILE ...................... 32 DATA RATE 64 MHZ PRF 1256 PREAMBLE SYMBOLS FIGURE 34: TYPICAL RX POWER PROFILE USING SNIFF ...................................................................... 15 MODE .............................................................. 32 FIGURE 11: TYPICAL PROBABILITY DISTRIBUTION OF LINE OF FIGURE 35: POWER SUPPLY CONNECTIONS .................... 33 SIGHT 2-WAY RANGING PERFORMANCE .................. 15 FIGURE 36: SWITCHING REGULATOR CONNECTION.......... 33 FIGURE 12: TX SPECTRUM CHANNEL 1 ......................... 16 FIGURE 37: DW1000 APPLICATION CIRCUIT ................. 35 FIGURE 13: TX SPECTRUM CHANNEL 2 ......................... 16 FIGURE 38: PCB LAYER STACK FOR 4-LAYER BOARD ........ 36 FIGURE 14: TX SPECTRUM CHANNEL 3 ......................... 16 FIGURE 39: DW1000 RF TRACES LAYOUT .................... 37 FIGURE 15: TX SPECTRUM CHANNEL 4 ......................... 16 FIGURE 40: DEVICE PACKAGE MECHANICAL SPECIFICATIONS FIGURE 16: TX SPECTRUM CHANNEL 5 ......................... 16 ...................................................................... 38 FIGURE 17: TX SPECTRUM CHANNEL 7 ......................... 16 FIGURE 41: DEVICE PACKAGE MARKINGS ...................... 39 FIGURE 18: IEEE802.15.4-2011 PPDU STRUCTURE ... 18 FIGURE 42: TRAY ORIENTATION .................................. 39 FIGURE 19: IEEE802.15.4-2011 MAC FRAME FORMAT FIGURE 43: TAPE & REEL ORIENTATION ........................ 40 ...................................................................... 18 FIGURE 44: TAPE DIMENSIONS .................................... 40 FIGURE 20: DW1000 POWER-UP SEQUENCE................ 20 FIGURE 45: 330 MM REEL DIMENSIONS ........................ 41 FIGURE 21: POWER UP EXAMPLE WHERE VDDLDOD FIGURE 46: 180 MM REEL DIMENSIONS ........................ 41 CANNOT BE GUARANTEED TO BE READY IN TIME FOR THE List of Tables TABLE 1: DW1000 PIN FUNCTIONS............................... 6 TABLE 16: EXTERNAL USE OF RSTN .............................. 21 TABLE 2: EXPLANATION OF ABBREVIATIONS ..................... 9 TABLE 17: DW1000 SPI MODE CONFIGURATION .......... 23 TABLE 3: DW1000 OPERATING CONDITIONS ................ 10 TABLE 18: DW1000 SPI TIMING PARAMETERS ............. 24 TABLE 4: DW1000 DC CHARACTERISTICS .................... 10 TABLE 19: TRANSMIT & RECEIVE BUFFER MEMORY SIZE .. 25 TABLE 5: DW1000 RECEIVER AC CHARACTERISTICS ....... 10 TABLE 20: ACCUMULATOR MEMORY SIZE ..................... 25 TABLE 6: TYPICAL RECEIVER SENSITIVITY CHARACTERISTICS 11 TABLE 21: OTP CALIBRATION MEMORY......................... 25 TABLE 7: DW1000 REFERENCE CLOCK AC CHARACTERISTICS TABLE 22: SYNC SIGNAL TIMING RELATIVE TO XTAL ....... 26 ...................................................................... 11 TABLE 23: OPERATING STATES .................................... 28 TABLE 8: DW1000 TRANSMITTER AC CHARACTERISTICS . 12 TABLE 24: OPERATING STATES AND THEIR EFFECT ON POWER TABLE 9: DW1000 TEMPERATURE AND VOLTAGE MONITOR CONSUMPTION .................................................. 28 CHARACTERISTICS .............................................. 12 TABLE 25: OPERATIONAL MODES ................................ 29 TABLE 10: DW1000 ABSOLUTE MAXIMUM RATINGS ..... 12 TABLE 26: TYPICAL TX CURRENT CONSUMPTION ............ 30 TABLE 11: UWB IEEE802.15.4-2011 UWB CHANNELS TABLE 27: TYPICAL RX CURRENT CONSUMPTION ............ 30 SUPPORTED BY THE DW1000 .............................. 17 TABLE 28: LOWEST POWER AND LONGEST RANGE MODES OF TABLE 12: UWB IEEE802.15.4-2011 [1] UWB BIT RATES OPERATION ....................................................... 31 AND PRF MODES SUPPORTED BY THE DW1000 ...... 17 TABLE 29: DEVICE ORDERING INFORMATION .................. 42 TABLE 13: DW1000 SYMBOL DURATIONS ................... 18 TABLE 30: GLOSSARY OF TERMS .................................. 43 TABLE 14: TURN-AROUND TIMES ................................ 18 TABLE 31: DOCUMENT HISTORY .................................. 44 TABLE 15: DW1000 POWER-UP TIMINGS .................... 20 © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 3

DW1000 Datasheet DOCUMENT INFORMATION Disclaimer Decawave reserves the right to change product specifications without notice. As far as possible changes to functionality and specifications will be issued in product specific errata sheets or in new versions of this document. Customers are advised to check with Decawave for the most recent updates on this product. Copyright © 2015 Decawave Ltd LIFE SUPPORT POLICY Decawave products are not authorized for use in safety-critical applications (such as life support) where a failure of the Decawave product would reasonably be expected to cause severe personal injury or death. Decawave customers using or selling Decawave products in such a manner do so entirely at their own risk and agree to fully indemnify Decawave and its representatives against any damages arising out of the use of Decawave products in such safety-critical applications. Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. REGULATORY APPROVALS The DW1000, as supplied from Decawave, has not been certified for use in any particular geographic region by the appropriate regulatory body governing radio emissions in that region although it is capable of such certification depending on the region and the manner in which it is used. All products developed by the user incorporating the DW1000 must be approved by the relevant authority governing radio emissions in any given jurisdiction prior to the marketing or sale of such products in that jurisdiction and user bears all responsibility for obtaining such approval as needed from the appropriate authorities. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 4

DW1000 Datasheet 1 IC DESCRIPTION AN LD D V DIGITAL RX ADC Carrier/ SECDED/ Digital Filter RTeicmoivnegr y sprDeea-der DVeicteordbei r SDRoelecooemddoe-nr Rx Analog Leading Edge SPICLK Baseband and Diagnostics Configuration Host Interface SPICSn RF_P (LDE) Retention H/W SPI SPIMISO MAC RF_N SPIMOSI RF RX OTP Timers IRQ IF Gain Control Register SYNC Digital AON File I/F GPIO[0..6] To all digital Pulse Generator blocks via PMSC VDDPA1 VDDPA2 CBounrtsrot l CoEnvnocloudtieornal SERonlceooemddoe-nr SECDED TCraonnstrmolit RF TX DIGITAL TX To all circuits AON VDDAON DIGITAL Control CAS Loop Power Memory Circuits Tx / Rx Maannda gSetmateen t Array RF PLL / Synth Calibration Control (PMSC) VDDLDOD 13kHz VDDLDOA ROegnu-Clahtoipr s Tciorc aulilt s Bias Tciorc aulilt s Oscillator CLirocoupit s Temperature Osc CLK PLL / Synth /m Boanttietorry POR VDDMSVDDIFVDDCLKVDDVCO VDDSYN VDDDIG VREF VDDBAT VCOTUNE XTAL2 XTAL1 CLKTUNE WAKEUP RSTn FORCEONEXTON Figure 1: IC Block Diagram DW1000 is a fully integrated low-power, single chip initial frequency error adjustment, and range CMOS RF transceiver IC compliant with the accuracy adjustment. These adjustment values can IEEE802.15.4-2011 [1] UWB standard. be automatically retrieved when needed. See section 5.14 for more details. DW1000 consists of an analog front end containing The Always-On (AON) memory can be used to a receiver and a transmitter and a digital back end retain DW1000 configuration data during the lowest that interfaces to an off-chip host processor. A power operational states when the on-chip voltage TX/RX switch is used to connect the receiver or regulators are disabled. This data is uploaded and transmitter to the antenna port. Temperature and downloaded automatically. Use of DW1000 AON voltage monitors are provided on-chip memory is configurable. The receiver consists of an RF front end which The DW1000 clocking scheme is based around 3 amplifies the received signal in a low-noise amplifier main circuits; Crystal Oscillator, Clock PLL and RF before down-converting it directly to baseband. The PLL. The on-chip oscillator is designed to operate receiver is optimized for wide bandwidth, linearity at a frequency of 38.4 MHz using an external and noise figure. This allows each of the supported crystal. An external 38.4 MHz clock signal may be IEEE802.15.4-2011 [1] UWB channels to be down applied in place of the crystal if an appropriately converted with minimum additional noise and stable clock is available elsewhere in the user’s distortion. The baseband signal is demodulated system. This 38.4 MHz clock is used as the and the resulting received data is made available to reference clock input to the two on-chip PLLs. The the host controller via SPI. clock PLL (denoted CLKPLL) generates the clock required by the digital back end for signal The transmit pulse train is generated by applying processing. The RF PLL generates the down- digitally encoded transmit data to the analog pulse conversion local oscillator (LO) for the receive chain generator. The pulse train is up-converted by a and the up-conversion LO for the transmit chain. double balanced mixer to a carrier generated by the An internal 13 kHz oscillator is provided for use in synthesizer and centered on one of the permitted the SLEEP state. IEEE802.15.4-2011 [1] UWB channels. The modulated RF waveform is amplified before The host interface includes a slave-only SPI for transmission from the external antenna. device communications and configuration. A number of MAC features are implemented including The IC has an on-chip One-Time Programmable CRC generation, CRC checking and receive frame (OTP) memory. This memory can be used to store filtering. calibration data such as TX power level, crystal © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 5

DW1000 Datasheet 2 PIN CONNECTIONS 2.1 Pin Numbering QFN-48 package with pin assignments as follows: - Figure 2: DW1000 Pin Assignments 2.2 Pin Descriptions Table 1: DW1000 Pin functions I/O SIGNAL NAME PIN DESCRIPTION (default) Crystal Interface EXTCLK / XTAL1 3 AI Reference crystal input or external reference overdrive pin. XTAL2 4 AI Reference crystal input. Digital Interface SPICLK 41 DI SPI clock DO SPIMISO 40 SPI data output. Refer to section 5.8. (O-L) SPIMOSI 39 DI SPI data input. Refer to section 5.8. SPI chip select. This is an active low enable input. The high-to-low transition on SPICSn signals the start of a new SPI transaction. SPICSn SPICSn 24 DI can also act as a wake-up signal to bring DW1000 out of either SLEEP or DEEPSLEEP states. Refer to section 6. The SYNC input pin is used for external synchronization (see section DIO SYNC / GPIO7 29 5.13). When the SYNC input functionality is not being used this pin may (I) be reconfigured as a general purpose I/O pin, GPIO7. When asserted into its active high state, the WAKEUP pin brings the WAKEUP 23 DI DW1000 out of SLEEP or DEEPSLEEP states into operational mode. When this pin is not being used as WAKEUP it should be tied to VSSIO © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 6

DW1000 Datasheet I/O SIGNAL NAME PIN DESCRIPTION (default) External device enable. Asserted during wake up process and held active until device enters sleep mode. Can be used to control external DC-DC DO EXTON 21 converters or other circuits that are not required when the device is in (O-L) sleep mode so as to minimize power consumption. Refer to sections 5.5.1 & 7. FORCEON 22 DI Not used in normal operation. Must be connected to ground Interrupt Request output from the DW1000 to the host processor. By default IRQ is an active-high output but may be configured to be active low if required. For correct operation in SLEEP and DEEPSLEEP modes it should be configured for active high operation. This pin will float in DIO SLEEP and DEEPSLEEP states and may cause spurious interrupts IRQ / GPIO8 45 (O-L) unless pulled low. When the IRQ functionality is not being used the pin may be reconfigured as a general purpose I/O line, GPIO8. This pin has an internal pulldown to VSSIO and can be left unconnected if not being used. General purpose I/O pin. On power-up it acts as the SPIPHA (SPI phase selection) pin for configuring the SPI operation mode. For details of this please refer to section 5.8. GPIO6 / EXTRXE DIO 30 After power-up, the pin will default to a General Purpose I/O pin. / SPIPHA (I) It may be configured for use as EXTRXE (External Receiver Enable). This pin goes high when the DW1000 is in receive mode. This pin has an internal pulldown to VSSIO and can be left unconnected if not being used. General purpose I/O pin. On power-up it acts as the SPIPOL (SPI polarity selection) pin for configuring the SPI mode of operation. Refer to section 5.8 for further information. GPIO5 / EXTTXE DIO 33 After power-up, the pin will default to a General Purpose I/O pin. / SPIPOL (I) It may be configured for use as EXTTXE (External Transmit Enable). This pin goes high when the DW1000 is in transmit mode. This pin has an internal pulldown to VSSIO and can be left unconnected if not being used. General purpose I/O pin. It may be configured for use as EXTPA (External Power Amplifier). This DIO GPIO4 / EXTPA 34 pin can enable an external Power Amplifier. (I) This pin has an internal pulldown to VSSIO and can be left unconnected if not being used. General purpose I/O pin. It may be configured for use as a TXLED driving pin that can be used to DIO light a LED following a transmission. Refer to the DW1000 User Manual GPIO3 / TXLED 35 (I) [2] for details of LED use. This pin has an internal pulldown to VSSIO and can be left unconnected if not being used. General purpose I/O pin. It may be configured for use as a RXLED driving pin that can be used to DIO light a LED during receive mode. Refer to the DW1000 User Manual [2] GPIO2 / RXLED 36 (I) for details of LED use. This pin has an internal pulldown to VSSIO and can be left unconnected if not being used. General purpose I/O pin. It may be configured for use as a SFDLED driving pin that can be used to DIO light a LED when SFD (Start Frame Delimiter) is found by the receiver. GPIO1 / SFDLED 37 (I) Refer to the DW1000 User Manual [2] for details of LED use. This pin has an internal pulldown to VSSIO and can be left unconnected if not being used. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 7

DW1000 Datasheet I/O SIGNAL NAME PIN DESCRIPTION (default) General purpose I/O pin. It may be configured for use as a RXOKLED driving pin that can be used GPIO0 / DIO to light a LED on reception of a good frame. Refer to the DW1000 User 38 RXOKLED (I) Manual [2] for details of LED use. This pin has an internal pulldown to VSSIO and can be left unconnected if not being used. Reset pin. Active Low Output. DIO RSTn 27 May be pulled low by external open drain driver to reset the DW1000. (O-H) Must not be pulled high by external source. Refer to section 5.6. TESTMODE 46 DI Not used in normal operation. Must be connected to ground. Reference voltages Used for on-chip reference current generation. Must be connected to an VREF 5 AIO 11 kΩ (1% tolerance) resistor to ground. Digital Power Supplies VDDLDOD 26 P External supply for digital circuits. VDDIOA 28 P External supply for digital IO ring. 32 VSSIO G Negative I/O ring supply. Must be connected to ground. 43 Digital Decoupling Output of on-chip regulator. Connect to VDDDIG on PCB if using the VDDREG 20 PD GPIOs to drive high-current outputs such as LEDs. Requires a local 100 nF capacitor to VSSIO. Output of on-chip regulator. Connect to VDDREG on PCB if using the VDDDIG 44 PD GPIOs to drive high-current outputs such as LEDs. Requires a local 100 nF capacitor to VSSIO. 31 VDDIO PD Digital IO Ring Decoupling. 42 RF Interface RF_P 16 AIO Positive pin of the 100 Ω differential RF pair. Should be AC coupled. RF_N 17 AIO Negative pin of the 100 Ω differential RF pair. Should be AC coupled. PLL Interface Clock PLL loop filter connection to off-chip filter components. Referenced CLKTUNE 8 AIO to VDDCLK. RF PLL loop filter connection to off-chip filter components. Referenced to VCOTUNE 12 AIO VDDVCO. Analog Power Supplies VDDAON 25 P External supply for the Always-On (AON) portion of the chip. See 7.3 VDDPA1 18 P External supply to the transmitter power amplifier. VDDPA2 19 P External supply to the transmitter power amplifier. VDDLNA 15 P External supply to the receiver LNA. VDDLDOA 48 P External supply to analog circuits. External supply to all other on-chip circuits. If a TCXO is being used with VDDBATT 47 P the DW1000 this pin should be supplied by the regulated supply used to power the TCXO. See Figure 37. Analog Supply Decoupling VDDCLK 9 PD Output of on-chip regulator to off-chip decoupling capacitor. VDDIF 7 PD Output of on-chip regulator to off-chip decoupling capacitor. VDDMS 6 PD Output of on-chip regulator to off-chip decoupling capacitor. VDDSYN 10 PD Output of on-chip regulator to off-chip decoupling capacitor. VDDVCO 11 PD Output of on-chip regulator to off-chip decoupling capacitor. Ground Paddle © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 8

DW1000 Datasheet I/O SIGNAL NAME PIN DESCRIPTION (default) Ground Paddle on underside of package. Must be soldered to the PCB GND 49 G ground plane for thermal and RF performance. Others 1 2 NC NC Not used in normal operation. Do not connect. 13 14 Table 2: Explanation of Abbreviations ABBREVIATION EXPLANATION AI Analog Input AIO Analog Input / Output AO Analog Output DI Digital Input DIO Digital Input / Output DO Digital Output G Ground P Power Supply PD Power Decoupling NC No Connect O-L Defaults to output, low level after reset O-H Defaults to output, high level after reset I Defaults to input. Note: Any signal with the suffix ‘n’ indicates an active low signal. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 9

DW1000 Datasheet 3 ELECTRICAL SPECIFICATIONS 3.1 Nominal Operating Conditions Table 3: DW1000 Operating Conditions Parameter Min. Typ. Max. Units Condition/Note Operating temperature -40 +85 ˚C Supply voltage VDDIOA 2.8 3.3 3.6 V Supply voltage VDDBATT, VDDAON, 2.8 3.3 3.6 V VDDLNA, VDDPA Supply voltage VDDLDOA, VDDLDOD 1.6 1.8 3.6 V See section 7.2 Only to be used if programming the OTP memory. See the Optional: Supply voltage VDDIO 3.7 3.8 3.9 V DW1000 User Manual [2] for details. Voltage on GPIO0..8, WAKEUP, RSTn, Note that 3.6 V is the max SPICSn, SPIMOSI, SPICLK, TESTMODE, 3.6 V voltage that should be applied to FORCEON these pins Note: Unit operation is guaranteed by design when operating within these ranges 3.2 DC Characteristics T = 25 ˚C, all supplies centered on typical values amb Table 4: DW1000 DC Characteristics Parameter Min. Typ. Max. Units Condition/Note Supply current DEEP SLEEP mode 50 nA Supply current SLEEP mode 1 µA Total current drawn from all Supply current IDLE mode 19 mA 3.3 V and 1.8 V supplies. Supply current INIT mode 5 mA TX : 3.3 V supplies (VDDBAT, VDDPA1, VDDPA2, VDDLNA, 70 mA Channel 5 VDDAON, VDDIOA) TX Power = MAX mean TX : 1.8 V supplies ( -9.3 dBm/500 MHz) 90* mA (VDDLDOA, VDDLDOD) RX : 3.3 V supplies (VDDBAT, VDDPA1, VDDPA2, VDDLNA, 30 mA VDDAON, VDDIOA) Channel 5 RX : 1.8 V supplies 210* mA (VDDLDOA, VDDLDOD) Digital input voltage high 0.7*VDDIO V Digital input voltage low 0.3*VDDIO V Digital output voltage high 0.7*VDDIO V Assumes 500 Ω load. Digital output voltage low 0.3*VDDIO V Assumes 500 Ω load. Digital Output Drive Current GPIOx, IRQ 4 6 mA SPIMISO 8 10 EXTON 3 4 * These currents are on the 1.8 V supplies, not referenced back to the 3.3 V supply 3.3 Receiver AC Characteristics T = 25 ˚C, all supplies centered on nominal values amb Table 5: DW1000 Receiver AC Characteristics Parameter Min. Typ. Max. Units Condition/Note Frequency range 3244 6999 MHz © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 10

DW1000 Datasheet Parameter Min. Typ. Max. Units Condition/Note 500 Channel 1,2,3 and 5 Channel bandwidths MHz 900 Channel 4 and 7 Input P1Db compression point -39 dBm Measured at balun input In-band blocking level 30 dBc Continuous wave interferer Out-of-band blocking level 55 dBc Continuous wave interferer 0 5 m/s 4096 preamble 110kbps, 128 Relative velocity between Receiver & bytes Transmitter 0 500 m/s 64 preamble 6.8 Mbps, 12 bytes 3.4 Receiver Sensitivity Characteristics T = 25 ˚C, all supplies centered on typical values. 20 byte payload amb Table 6: Typical Receiver Sensitivity Characteristics Packet Typical Error Data Rate Receiver Units Condition/Note Rate Sensitivity Carrier frequency 1% 110 kbps -106 dBm/500 MHz Preamble 2048 offset ±1 ppm. Requires use of the “tight” All Rx operating measurements 10% 110 kbps -107 dBm/500 MHz Preamble 2048 parameter set performed on – see [2] Channel 5, PRF 16 MHz. 110 kbps -102 dBm/500 MHz Preamble 2048 Channel 2 is 1% 850 kbps -101 dBm/500 MHz Preamble 1024 approximately 1 6.8 Mbps -93 (*-97) dBm/500 MHz Preamble 256 Carrier dB less sensitive frequency 110 kbps -106 dBm/500 MHz Preamble 2048 offset ±10 ppm 10% 850 kbps -102 dBm/500 MHz Preamble 1024 6.8 Mbps -94 (*-98) dBm/500 MHz Preamble 256 *equivalent sensitivity with Smart TX Power enabled 3.5 Reference Clock AC Characteristics T = 25 ˚C, all supplies centered on typical values amb 3.5.1 Reference Frequency Table 7: DW1000 Reference Clock AC Characteristics Parameter Min. Typ. Max. Units Condition/Note A 38.4 MHz signal can be provided from an Crystal oscillator reference 38.4 MHz external reference in place of a crystal if frequency desired. See Figure 37 Crystal specifications Load capacitance 0 35 pF Depends on crystal used and PCB parasitics Shunt capacitance 0 4 pF Drive level 200 µW Depends on crystal & load capacitance used Equivalent Series 60 Ω Resistance (ESR) DW1000 includes circuitry to trim the crystal Frequency tolerance ±20 ppm oscillator to reduce the initial frequency offset. Trimming range provided by on-chip circuitry. Crystal trimming range ±25 ppm Depends on the crystal used and PCB design. External Reference Must be AC coupled. A coupling capacitor Amplitude 0.8 V pp value of 2200 pF is recommended SSB phase noise power -132 dBc/Hz @1 kHz offset. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 11

DW1000 Datasheet Parameter Min. Typ. Max. Units Condition/Note density SSB phase noise power -145 dBc/Hz @10 kHz offset. density Duty Cycle 40 60 % Low Power RC Oscillator 5 12 15 kHz 3.6 Transmitter AC Characteristics T = 25 ˚C, all supplies centered on typical values amb Table 8: DW1000 Transmitter AC Characteristics Parameter Min. Typ. Max. Units Condition/Note Frequency range 3244 6999 MHz 500 Channel 1, 2, 3 and 5 Channel Bandwidths MHz 900 Channel 4 and 7 Output power spectral density -39 -35 dBm/MHz See Section 5.5 (programmable) Load impedance 100 Ω Differential Power level range 37 dB Coarse Power level step 3 dB Fine Power level step 0.5 dB Output power variation with 0.05 dB/OC temperature 2.73 Channel 2 Output power variation with voltage dB/V 3.34 Channel 5 3.7 Temperature and Voltage Monitor Characteristics Table 9: DW1000 Temperature and Voltage Monitor Characteristics Parameter Min. Typ. Max. Units Condition/Note Voltage Monitor Range 2.4 3.75 V Voltage Monitor Precision 20 mV Voltage Monitor Accuracy 140 mV Temperature Monitor Range -40 +100 °C Temperature Monitor Precision 0.9 °C Temperature Monitor Accuracy 2 °C 3.8 Absolute Maximum Ratings Table 10: DW1000 Absolute Maximum Ratings Parameter Min. Max. Units Voltage VDDPA / VDDLNA / VDDLDOD / VDDLDOA / VDDBATT / -0.3 4.0 V VDDIOA / VDDAON / VDDIO Receiver Power 0 dBm Temperature - Storage temperature -65 +150 ˚C Temperature – Operating temperature -40 +85 ˚C ESD (Human Body Model) 2000 V Stresses beyond those listed in this table may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operating conditions of the specification is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 12

DW1000 Datasheet 4 TYPICAL PERFORMANCE 90 80 Blocker Rejection (dB)567000 40 30 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Blocker Frequency (GHz) Wanted channel 2 (3.9936 GHz) Figure 3 : RX Interferer Immunity on Channel 2 -32 -34 -36 2.5 Volts, +25⁰C -38 Hz) 3.3 Volts, +25⁰C M-40 3.6 Volts, +25⁰C / m B-42 2.5 Volts, -40⁰C d Pwr (-44 3.3 Volts, -40⁰C Tx 3.6 Volts, -40⁰C -46 2.5 Volts, +85⁰C -48 3.3 Volts, +85⁰C -50 3.6 Volts, +85⁰C -52 0 1 2 3 4 5 6 7 Channel Figure 4: TX output Power over Temp & Voltage (note that 2.5 volt data points are shown for information only) Figure 5: Receiver Sensitivity Channel 5 110kbps Data Rate 16 MHz PRF 2048 Preamble Symbols © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 13

DW1000 Datasheet Figure 6: Receiver Sensitivity Channel 5 110kbps Data Rate 64 MHz PRF 2048 Preamble Symbols Figure 7: Receiver Sensitivity Channel 5 850kbps Data Rate 16 MHz PRF 1024 Preamble Symbols Figure 8: Receiver Sensitivity Channel 5 850kbps Data Rate 64 MHz PRF 1024 Preamble Symbols © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 14

DW1000 Datasheet Figure 9: Receiver Sensitivity Channel 5 6.81Mbps Data Rate 16 MHz PRF 256 Preamble Symbols Figure 10: Receiver Sensitivity Channel 5 6.81Mbps Data Rate 64 MHz PRF 1256 Preamble Symbols 0.12 0.1 0.08 y abilit 0.06 b o Pr 0.04 0.02 0 -8 -6 -4 -2 0 2 4 6 8 Error (cm) Figure 11: Typical probability distribution of Line of Sight 2-way ranging performance © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 15

DW1000 Datasheet *RBW 1 MHz *RBW 1 MHz *VBW 1 MHz *VBW 1 MHz Ref -40 dBm Att 5 dB **SWT 4 s Ref -40 dBm Att 5 dB **SWT 4 s -40 -40 -45 A -45 A 1 RM* 1 RM* CLRWR -50 AVG -50 -55 -55 -60 -60 -65 -65 3DB 3DB -70 -70 -75 -75 -80 -80 -85 -85 -90 -90 Center 3.499 GHz 400 MHz/ Span 4 GHz Center 3.9936 GHz 400 MHz/ Span 4 GHz Date: 25.SEP.2013 16:07:44 Date: 25.SEP.2013 15:47:44 Figure 12: TX Spectrum Channel 1 Figure 13: TX Spectrum Channel 2 *RBW 1 MHz *RBW 1 MHz *VBW 1 MHz *VBW 1 MHz Ref -40 dBm Att 5 dB **SWT 4 s Ref -40 dBm Att 5 dB **SWT 4 s -40 -40 -45 A -45 A 1 RM* 1 RM* CLRWR -50 CLRWR -50 -55 -55 -60 -60 -65 -65 3DB 3DB -70 -70 -75 -75 -80 -80 -85 -85 -90 -90 Center 4.493 GHz 400 MHz/ Span 4 GHz Center 3.9936 GHz 400 MHz/ Span 4 GHz Date: 25.SEP.2013 16:09:23 Date: 25.SEP.2013 15:49:33 Figure 14: TX Spectrum Channel 3 Figure 15: TX Spectrum Channel 4 *RBW 1 MHz *RBW 1 MHz *VBW 1 MHz *VBW 1 MHz Ref -40 dBm Att 5 dB **SWT 4 s Ref -40 dBm Att 5 dB **SWT 4 s -40 -40 -45 A -45 A 1 RM* 1 RM* CLRWR -50 CLRWR -50 -55 -55 -60 -60 -65 -65 3DB 3DB -70 -70 -75 -75 -80 -80 -85 -85 -90 -90 Center 6.489 GHz 400 MHz/ Span 4 GHz Center 6.489 GHz 400 MHz/ Span 4 GHz Date: 25.SEP.2013 16:10:30 Date: 25.SEP.2013 16:20:23 Figure 16: TX Spectrum Channel 5 Figure 17: TX Spectrum Channel 7 © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 16

DW1000 Datasheet 5 FUNCTIONAL DESCRIPTION 5.1 Physical Layer Modes Please refer to IEEE802.15.4-2011 [1] for the PHY specification. 5.1.1 Supported Channels and Bandwidths The DW1000 supports the following six IEEE802.15.4-2011 [1] UWB channels: - Table 11: UWB IEEE802.15.4-2011 UWB channels supported by the DW1000 Centre Frequency Band Bandwidth UWB Channel Number (MHz) (MHz) (MHz) 1 3494.4 3244.8 – 3744 499.2 2 3993.6 3774 – 4243.2 499.2 3 4492.8 4243.2 – 4742.4 499.2 4 3993.6 3328 – 4659.2 1331.2* 5 6489.6 6240 – 6739.2 499.2 7 6489.6 5980.3 – 6998.9 1081.6* *DW1000 maximum receiver bandwidth is approximately 900 MHz 5.1.2 Supported Bit Rates and Pulse Repetition Frequencies (PRF) The DW1000 supports IEEE802.15.4-2011 [1] UWB standard bit rates of 110 kbps, 850 kbps and 6.81 Mbps and nominal PRF values of 16 and 64 MHz. Table 12: UWB IEEE802.15.4-2011 [1] UWB bit rates and PRF modes supported by the DW1000 PRF* Data Rate (MHz) (Mbps) 16 0.11 16 0.85 16 6.81 64 0.11 64 0.85 64 6.81 *Actual PRF mean values are slightly higher for SYNC as opposed to the other portions of a frame. Mean PRF values are 16.1/15.6 MHz and 62.89/62.4 MHz, nominally referred to as 16 and 64MHz in this document. Refer to [1] for full details of peak and mean PRFs. Generally speaking, lower data rates give increased receiver sensitivity, increased link margin and longer range but due to longer frame lengths for a given number of data bytes they result in increased air occupancy per frame and a reduction in the number of individual transmissions that can take place per unit time. 16 MHz PRF gives a marginal reduction in transmitter power consumption over 64 MHz PRF. 16 MHz and 64 MHz PRF can coexist on the same physical channel without interfering. 5.1.3 Frame Format IEEE802.15.4-2011 [1] frames are structured as shown in Figure 18. Detailed descriptions of the frame format are given in the standard [1]. The frame consists of a synchronisation header (SHR) which includes the preamble symbols and start frame delimiter (SFD), followed by the PHY header (PHR) and data. The data frame is usually specified in number of bytes and the frame format will include 48 Reed-Solomon parity bits following each block of 330 data bits (or less). The maximum standard frame length is 127 bytes, including the 2-byte FCS. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 17

DW1000 Datasheet 8 or 64 16,64,1024 or 4096 Preambles Symbols 21 bits 8*Frame Length + Reed-Solomon Encoding bits Start Frame Preamble Sequence Delimiter PHR MAC Protocol Data Unit (MPDU) (SFD) Synchronisation Header (SHR) PHY PHY Service Data Unit (PSDU) Header (PHR) PHY Protocol Data Unit (PPDU) Figure 18: IEEE802.15.4-2011 PPDU Structure 5.1.4 Symbol Timings Timing durations in IEEE802.15.4-2011 [1] are expressed in an integer number of symbols. This convention is adopted in DW1000 documentation. Symbol times vary depending on the data rate and PRF configuration of the device and the part of the frame. See Table 13: DW1000 Symbol Durations, for all symbol timings supported by DW1000. Table 13: DW1000 Symbol Durations PRF Data Rate SHR (ns) PHR (ns) Data (ns) (MHz) (Mbps) 16 0.11 993.59 8205.13 8205.13 16 0.85 993.59 1025.64 1025.64 16 6.81 993.59 1025.64 128.21 64 0.11 1017.63 8205.13 8205.13 64 0.85 1017.63 1025.64 1025.64 64 6.81 1017.63 1025.64 128.21 5.1.5 Proprietary Long Frames The DW1000 offers a proprietary long frame mode where frames of up to 1023 bytes may be transferred. This requires a non-standard PHR encoding and so cannot be used in a standard system. Refer to the DW1000 User Manual for full details [2]. 5.1.6 Turnaround Times Turn-around times given in the table below are as defined in [1]. Table 14: Turn-around Times Parameter Min. Typ. Max. Units Condition/Note Achievable turnaround time depends Turn-around time RX to TX*. 10 μs on device configuration and frame parameters and on external host Turn-around time TX to RX*. 6 μs controller. 5.1.7 Frame Filter A standard frame filtering format is defined in IEEE802.15.4-2011 [1]. An overview of the MAC frame format is given in Figure 19 . Note that the Auxiliary Security Header is not processed in DW1000 hardware. Bytes: 2 1 0 to 20 0 to 14 variable 2 Frame Control Sequence Address Auxiliary Frame Check Frame Payload Field (FCF) Number Information Security Header Seq. (FCS) MAC Header (MHR) MAC Payload MAC Footer (MFR) 8*Frame Length + Reed-Solomon Encoding bits MAC Protocol Data Unit (MPDU) PHY Service Data Unit (PSDU) Figure 19: IEEE802.15.4-2011 MAC Frame Format © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 18

DW1000 Datasheet Frame filtering allows the receiver to automatically discard frames that do not match a defined set of criteria. The DW1000 has a number of separately configurable frame filtering criteria to allow selection of the frame types to accept or discard. See IEEE802.15.4-2011 [1] for filtering field definition and acceptance rules. 5.1.8 Frame Check Sequence (FCS) The FCS is also known as the MAC Footer (MFR). It is a 2-byte CRC appended to frames. See IEEE802.15.4- 2011 [1] for information on FCS generation. 5.2 Reference Crystal Oscillator The on-chip crystal oscillator generates the reference frequency for the integrated frequency synthesizers RFPLL and CLKPLL. The oscillator operates at a frequency of 38.4 MHz. DW1000 provides the facility to trim out initial frequency error in the 38.4 MHz reference crystal, see section 5.14. The trimming range depends on the crystal chosen and the loading capacitors used. Typically a trimming range of ±25 ppm is possible. Loading capacitors should be chosen such that minimum frequency error (from the channel center frequency) is achieved when the trim value is approximately mid-range. In applications that require tighter frequency tolerance (maximum range) an external oscillator such as a TCXO can be used to drive the XTAL1 pin directly. 5.3 Synthesizer DW1000 contains 2 frequency synthesizers, RFPLL which is used as a local oscillator (LO) for the TX and RX and CLKPLL which is used as a system clock. Both of these synthesizers are fully integrated apart from external passive 2nd order loop filters. The component values for these loop filters do not change regardless of the RF channel used. The register programming values for these synthesizers is contained in the user manual [2] 5.4 Receiver 5.4.1 Bandwidth setting The receiver can be configured to operate in one of two bandwidth modes; 500 MHz or 900 MHz. The selection of a particular bandwidth mode is made by register settings and is described in the DW1000 User Manual [2]. 5.4.2 Automatic Gain Control (AGC) Automatic Gain Control is provided to ensure optimum receiver performance by adjusting receiver gain for changing signal and environmental conditions. The DW1000 monitors the received signal level and makes appropriate automatic adjustments to ensure optimum receiver performance is maintained. 5.5 Transmitter 5.5.1 Transmit Output Power DW1000 transmit power is fully adjustable as is the transmit spectrum width ensuring that applicable regulatory standards such as FCC [4] and ETSI [3] can be met. For maximum range the transmit power should be set such that the EIRP at the antenna is as close as possible to the maximum allowed, -41.3 dBm/MHz in most regions. See section 5.14.3 for more details. 5.5.2 Transmit Bandwidth Setting The transmitter can be configured to operate over a wide range of bandwidths. The selection of a particular bandwidth mode is made by register settings and is described in the DW1000 User Manual [2]. Transmit spectral shape can also be adjusted to compensate for PCB and external components in order to give an optimal transmit spectral mask. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 19

DW1000 Datasheet 5.6 Power-up sequence 5.6.1 Typical power-up sequence 3.3 V Supplies Von (VDDAON / VDDBAT / VDDIOA / VDDLNA / VDDPA1 / VDDPA2) Tosc_on XTAL1 XTAL1 (38.4MHz) VLDO_OK VDDLDOA & VDDLDOD TRST_OK EXTON Text_on RSTn Tdig_on STATE OFF POWER UP INIT Figure 20: DW1000 Power-up Sequence When power is applied to the DW1000, RSTn is driven low by the DW1000 internal circuitry as part of its power up sequence. See Figure 20 above. RSTn remains low until the XTAL oscillator has powered up and its output is suitable for use by the rest of the device. Once that time is reached the DW1000 de-asserts RSTn. Table 15: DW1000 Power-up Timings Min Nominal Parameter Description Units Value Value V Voltage threshold to enable overall IC power up. 2.0 V ON T Time taken for oscillator to start up and stabilise. 1.0 1.5 ms OSC_ON T EXTON goes high this long before RSTn is released. 1.5 2 ms EXT_ON RSTn held low by internal reset circuit / driven low by external T 1.5 2 ms DIG_ON reset circuit. Voltage threshold on the VDDLDOD supply at which the digital V 1.6 V LDO_OK core powers up. Time for which RSTn must continue to remain low once VDDLDOD exceeds V min. LDO_OK TRST_OK If TRST_OK min cannot be met due to the timing of the VDDLDOD 10 50 ns supply ramp then RSTn should be manually driven low for at least T min time to ensure correct reset operation RST_OK 5.6.2 Variation in the power-up sequence It is possible, that in some circuit arrangements, the start-up sequence may need to be altered. This can happen if, for example, the VDDLDOD supply is controlled via an external controller or if a slow ramp regulator is used to provide the VDDLDOD supply. In these situations the RSTn pin would have to be controlled by the external circuitry to ensure the digital circuits receive proper reset on power up. VLDO_OK VDDLDOA & VDDLDOD TRST_OK EXTON RSTn User asserts RSTn to VDDLDOD not ready ensure reset occurs STATE OFF POWER UP INIT Figure 21: Power up example where VDDLDOD cannot be guaranteed to be ready in time for the RSTn going high © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 20

DW1000 Datasheet Figure 21 shows a situation where the VDDLDOD supply is not high until after the first RSTn low to high transition (start of shaded area of RSTn). In this case the external circuitry must pull RSTn down again after the VDDLDOD supply has exceeded V This will ensure the digital circuits receive proper reset on power up. LDO_OK. The RSTn pin should be either held low during power up until T is met or driven low for a minimum of RST_OK T RST_OK. 5.6.3 External control of RSTn / use of RSTn by external circuitry 5.6.3.1 External control of RSTn An external circuit can reset the DW1000 by asserting RSTn for a minimum of T . RSTn is an RST_OK asynchronous input. DW1000 initialization will proceed when the RSTn pin is released to high impedance. An external source should open-drain the RSTn pin once the DW1000 has been reset. If RSTn is controlled by a GPIO of an external micro-controller care should be taken to ensure that the GPIO is configured as high- impedance as soon as it is released from the LOW state. When in DEEPSLEEP mode, the DW1000 drives RSTn to ground. This can result in current flowing if RSTn is driven high externally and will result in incorrect wake-up operation. RSTn should never be driven high by an external source. 5.6.3.2 Use of RSTn by external circuitry Table 16: External use of RSTn Use of RSTn Description As output to control RSTn may be used as an output to reset external circuitry as part of an orderly bring up of external circuitry a system as power is applied. RSTn may be used as an interrupt input to the external host to indicate that the DW1000 As interrupt input to has entered the INIT state. When RSTn is used in this way care should be taken to ensure external host that the interrupt pin of the external host does not pull-up the RSTn signal which should be left open-drain. Refer to Table 1 and Figure 37. 5.7 Voltage/Temperature Monitors The on-chip voltage and temperature monitors allow the host to read the voltage on the VDDAON pin and the internal die temperature information from the DW1000. See Table 9 for characteristics. 5.8 Host Controller Interface The DW1000 host communications interface is a slave-only SPI. Both clock polarities (SPIPOL=0/1) and phases (SPIPHA=0/1) are supported. The data transfer protocol supports single and multiple byte read/writes accesses. All bytes are transferred MSB first and LSB last. A transfer is initiated by asserting SPICSn low and terminated when SPICSn is deasserted high. The DW1000 transfer protocols for each SPIPOL and SPIPHA setting are given in Figure 22 and Figure 23. Note: Figure 22 and Figure 23 detail the SPI protocol as defined for SPICLK polarities and phases. The sampling and launch edges used by the SPI bus master are shown. DW1000 is a SPI slave device and will comply with the protocol by ensuring that the SPIMISO data is valid on the required SPICLK edge with setup and hold times as given by Table 18. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 21

DW1000 Datasheet CNyucmleb er, # 1 2 3 4 5 6 7 8 9 8*Nbuymtebser of SPIPOL=0, SPIPHA=0 SPICLK SPIPOL=1, SPIPHA=0 SPICLK SPICSn SPIMISO z MSB 6 5 4 3 2 1 LSB MSB LSB X Z SPIMOSI z MSB 6 5 4 3 2 1 LSB MSB LSB X Z Figure 22: DW1000 SPIPHA=0 Transfer Protocol CNyucmleb er, # 1 2 3 4 5 6 7 8 9 8*Nbuymtebser of SPIPOL=0, SPIPHA=1 SPICLK SPIPOL=1, SPIPHA=1 SPICLK SPICSn SPIMISO z X MSB 6 5 4 3 2 1 LSB MSB LSB Z SPIMOSI z X MSB 6 5 4 3 2 1 LSB MSB LSB Z Figure 23: DW1000SPIPHA=1 Transfer Protocol The MSB of the first byte is the read/write indicator, a low bit indicates a read access and a high bit indicates a write access. The second bit, bit 6 of the first byte, indicates whether a sub address byte will be included in the SPI access, a high bit indicates a further address byte to follow the initial byte and a low bit indicating that the bytes to follow the first byte are data. The 6 LSBs of the first byte contain an access address. The second byte of a transfer command, if included, gives the sub address being accessed. If the MSB of this optional second byte is high, it indicates a second sub address byte to follow in the third transfer byte. The 7 LSBs of this second byte give the 7 LSBs of the sub address. The third byte of a transfer command, if included give the 8 MSBs of the sub address. The number of data bytes to follow the 1-3 command bytes is not limited by the DW1000 transfer protocol. Figure 24: SPI Byte Formatting Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Write Sub address Command 0 – Read 0 – no sub address 6-bit access address 1 – Write 1 – sub address present Extended sub address Sub Address 0 0 – 1 byte sub address 7-bits of sub address. These will be the LSBs if more bits are to follow. (Optional) 1 – 2 byte sub address Sub Address 1 8 bits of sub address. These will form the MSBs, bits [14:7] of the 15-bit sub address. (Optional) Data 8-bit read/write bytes (variable number). The SPIMISO line may be connected to multiple slave SPI devices each of which is required to go open-drain when their respective SPICSn lines are de-asserted. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 22

DW1000 Datasheet The DW1000 has internal pull up and pull down circuits to ensure safe operation in the event of the host interface signals being disconnected. These are for internal use only, and should not be used to pull an external signal high or low. Internal pull-down resistance values are in the range 34 kΩ – 90 kΩ, internal pull- up resistance values are in the range 40 kΩ - 90 kΩ. VDDIOA GPIO5 33 (SPIPOL) ~60kΩ 24 ~55kΩ SPICSn S 39 P GPIO6 30 DW1000 SPIMOSI I P Host Controller (SPIPHA) ~55kΩ 40 OR ~55 kΩ SPIMISO T 41 SPICLK ~55kΩ Figure 25: SPI Connections More details of the protocol used for data transfer, the description of the accessible registers and the description of the bit functions of those registers are published in the DW1000 User Manual [2]. 5.8.1 Configuring the SPI Mode The SPI interface supports a number of different clock polarity and clock / data phase modes of operation. These modes are selected using GPIO5 & 6 as follows: - Table 17: DW1000 SPI Mode Configuration GPIO 5 GPIO 6 SPI Description (from the master / host point of view) (SPIPOL) (SPIPHA) Mode Data is sampled on the rising (first) edge of the clock and launched on the 0 0 0 falling (second) edge. Data is sampled on the falling (second) edge of the clock and launched on the 0 1 1 rising (first) edge. Data is sampled on the falling (first) edge of the clock and launched on the 1 0 2 rising (second) edge. Data is sampled on the rising (second) edge of the clock and launched on the 1 1 3 falling (first) edge. Note: The 0 on the GPIO pins can either be open circuit or a pull down to ground. The 1 on the GPIO pins is a pull up to VDDIO. GPIO 5 / 6 are sampled / latched on the rising edge of the RSTn pin to determine the SPI mode. They are internally pulled low to configure a default SPI mode 0 without the use of external components. If a mode other 0 is required then they should be pulled up using an external resistor of value no greater than 10 kΩ to the VDDIO output supply. If GPIO5 / 6 are also being used to control an external transmit / receive switch then external pull-up resistors of no less than 1 kΩ should be used so that the DW1000 can correctly drive these outputs in normal operation after the reset sequence / SPI configuration operation is complete. The recommended range of resistance values to pull-up GPIO 5 / 6 is in the range of 1-10 kΩ. If it is required to pull-down GPIO 5 / 6, such as in the case where the signal is also pulled high at the input to an external IC, the resistor value chosen needs to take account of the DW1000 internal pull-down resistor values as well as those of any connected external pull-up resistors. It is possible to set the SPI mode using the DW1000’s one-time programmable configuration block to avoid the need for external components and to leave the GPIO free for use. This is a one-time activity and cannot be reversed so care must be taken to ensure that the desired SPI mode is set. Please refer to the DW1000 User Manual [2] for details of OTP use and configuration. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 23

DW1000 Datasheet 5.8.2 SPI Signal Timing SPICSn S PIC LK SPIMOSI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 SPIMISO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 t7 t5 t8 t6 t 9 Figure 26: DW1000 SPI Timing Diagram SPICSn S PIC LK SPIMOSI Bit 7 Bit 6 Bit 5 SPIMISO 7 6 5 t 1 t3 t4 t2 Figure 27: DW1000 SPI Detailed Timing Diagram Table 18: DW1000 SPI Timing Parameters Parameter Min Typ Max Unit Description SPICLK The maximum SPI frequency is 20 MHz when the CLKPLL is locked, 50 ns Period otherwise the maximum SPI frequency is 3 MHz. t 38 ns SPICSn select asserted low to valid slave output data 1 t 12 ns SPICLK low to valid slave output data 2 t 10 ns Master data setup time 3 t 10 ns Master data hold time 4 t 32 ns LSB last byte to MSB next byte 5 t 10 ns SPICSn de-asserted high to SPIMISO tri-state 6 t 16 ns Start time; time from select asserted to first SPICLK 7 t 40 ns Idle time between consecutive accesses 8 t 40 ns Last SPICLK to SPICSn de-asserted 9 5.9 General Purpose Input Output (GPIO) The DW1000 provides 8 user-configurable I/O pins. On reset, all GPIO pins default to input. GPIO inputs, when appropriately FROM GPIO configured, are capable of generating interrupts to the host processor via the IRQ signal. Some GPIO lines have multiple functions as described in 470Ω 2.2 above. GPIO0, 1, 2, & 3, as one of their optional functions, can drive LEDs to LED indicate the status of various chip operations. Any GPIO line being used to drive an LED in this way should be connected as shown. GPIO5 & 6 are used to configure the operating mode of the SPI as described in 5.8.1. GPIO4, 5 & 6 may be optionally used to implement a scheme with an external power amplifier to provide a transmit power level in excess of that provided by the DW1000. The DW1000 User Manual [2] provides details of the configuration and use of the GPIO lines. 5.10 Memory The DW1000 includes a number of user accessible memories: - © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 24

DW1000 Datasheet 5.10.1 Receive and Transmit data buffers Buffers used to store received data to be read from the DW1000 by the host controller and data for transmission written into the DW1000 by the host controller. These are sized as follows: - Table 19: Transmit & Receive Buffer Memory Size Memory Size (bits) Description Transmit data buffer. Contains data written by the host processor Tx Buffer 1024 x 8 to be transmitted via the transmitter Receive data buffer. Contains data received via the receiver to be read by the host processor via the SPI interface. Double buffered Rx Buffer 1024 x 8 x 2 so that the receiver can receive a second packet while the first is being read by the host controller 5.10.2 Accumulator memory The accumulator memory is used to store the channel impulse response estimate. Table 20: Accumulator Memory Size Memory Size (bits) Description Accumulator buffer. Used to store channel impulse response Accumulator 1016 x 32 estimate data to be optionally read by the host controller 5.10.3 One Time Programmable (OTP) Calibration Memory The DW1000 contains a small amount of user programmable OTP memory that is used to store per chip calibration information. When programming the OTP, the user should ensure that the VDDIO pins are supplied with 3.7 V minimum. If the VDDIO pin is unavailable, then the VDDIOA pin should be driven instead. Table 21: OTP calibration memory Memory Size (bits) Description One time programmable area of memory used for storing Calibration 56 x 32 calibration data. 5.11 Interrupts and Device Status DW1000 has a number of interrupt events that can be configured to drive the IRQ output pin. The default IRQ pin polarity is active high. A number of status registers are provided in the system to monitor and report data of interest. See DW1000 User Manual [2] for a full description of system interrupts and their configuration and status registers. 5.12 MAC Features 5.12.1 Timestamping DW1000 generates transmit timestamps and captures receive timestamps. These timestamps are 40-bit values at a nominal 64 GHz resolution, for approximately 15 ps event timing precision. These timestamps enable ranging calculations. DW1000 allows antenna delay values to be programmed for automatic adjustment of timestamps. See the DW1000 User Manual [2] for more details of DW1000 implementation and IEEE802.15.4-2011 [1] for details of definitions and required precision of timestamps and antenna delay values. 5.12.2 FCS Generation and Checking DW1000 will automatically append a 2-byte FCS to transmitted frames and check received frames’ FCS. The DW1000 can be used to send frames with a host-generated FCS, if desired. 5.12.3 Automatic Frame Filtering Automatic frame filtering can be carried out using the DW1000. Incoming frames can be rejected automatically if they fail frame type or destination address checks. See the DW1000 User Manual [2] for details. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 25

DW1000 Datasheet 5.12.4 Automatic Acknowledge The DW1000 can be configured to automatically acknowledge received frames requesting acknowledgement. See the DW1000 User Manual [2] for details. Note that RX-TX turnaround is optimised for Automatic Acknowledge and is typically ~6.5 µs, but depends on the configured frame parameters. The delay applied between frames is programmable in preamble symbol durations to allow compliance with IEEE802.15.4-2011 [1] SIFS and LIFS requirements. 5.12.5 Double Receive Buffer The DW1000 has two receive buffers to allow the device to receive another frame whilst the host is accessing a previously received frame. Achievable throughput is increased by this feature. See the DW1000 User Manual [2] for details. 5.13 External Synchronization The DW1000 provides a SYNC input. This allows: -  Synchronization of multiple DW1000 timestamps.  Transmission synchronous to an external reference.  Receive timestamping synchronous to an external counter. As shown in Figure 28 the SYNC input must be source synchronous with the external frequency reference. The SYNC input from the host system provides a common reference point in time to synchronise all the devices with the accuracy necessary to achieve high resolution location estimation. XTAL1 SYNC t t sync_su sync_hd Figure 28: SYNC signal timing relative to XTAL1 Table 22: SYNC signal timing relative to XTAL Parameter Min Typ Max Unit Description t 10 ns SYNC signal setup time before XTAL1 rising edge SYNC_SU t 10 ns SYNC signal hold time after XTAL1 rising edge SYNC_HD Further details on wired and wireless synchronization are available from Decawave. 5.14 Calibration and Spectral Tuning of the DW1000 5.14.1 Introduction Depending on the end use application and the system design, certain internal settings in the DW1000 may need to be tuned. To help with this tuning a number of built in functions such as continuous wave TX and continuous packet transmission can be enabled. See the DW1000 User Manual [2] for further details on the sections described below. 5.14.2 Crystal Oscillator Trim Minimising the carrier frequency offset between different DW1000 devices improves receiver sensitivity. The DW1000 allows trimming to reduce crystal initial frequency error. The simplest way to measure this frequency error is to observe the output of the transmitter at an expected known frequency using a spectrum analyser or frequency counter. To adjust the frequency offset, the device is configured to transmit a CW signal at a particular channel frequency (e.g. 6.5 GHz). By accurately measuring the actual center frequency of the transmission the difference between it and the desired frequency can be determined. The trim value is then adjusted until the smallest frequency offset from the desired center frequency is obtained. Figure 29 gives the relationship between crystal trim code © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 26

DW1000 Datasheet and crystal ppm offset. If required, crystal trimming should be carried out on each DW1000 unit or module. 30.00 20.00 10.00 et offs 0.00 m p p -10.00 -20.00 -30.00 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 Crystal Trim Code Figure 29: Typical Device Crystal Trim PPM Adjustment The type of crystal used and the value of the loading capacitors will affect the crystal trim step size and the total trimming range. The total trim range and frequency step per trim code in ppm can be approximated using the following formula: Total trim range in ppm Trim step size in ppm Where C and C are derived from the crystal model shown below, which is available from the crystal M o manufacturer. C is the external load capacitance including PCB parasitic and C = 7.75 pF, which is the L TRIM maximum internal trimming capacitance in DW1000. 5.14.3 Transmitter Calibration In order to maximise range DW1000 transmit power spectral density (PSD) should be set to the maximum allowable for the geographic region. For most regions this is -41.3 dBm/MHz. The DW1000 provides the facility to adjust the transmit power in coarse and fine steps; 3 dB and 0.5 dB nominally. It also provides the ability to adjust the spectral bandwidth. These adjustments can be used to maximise transmit power whilst meeting regulatory spectral mask. If required, transmit calibration should be carried out on each DW1000 PCB / module. 5.14.4 Antenna Delay Calibration In order to measure range accurately, precise calculation of timestamps is required. To do this the antenna delay must be known. The DW1000 allows this delay to be calibrated and provides the facility to compensate for delays introduced by PCB, external components, antenna and internal DW1000 delays. To calibrate the antenna delay, range is measured at a known distance using 2 DW1000 systems. Antenna delay is adjusted until the known distance and reported range agree. The antenna delay can be stored in OTP memory. Antenna delay calibration must be carried out as a once off measurement for each DW1000 design implementation. If required, for greater accuracy, antenna delay calibration should be carried out on each DW1000 PCB / module. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 27

DW1000 Datasheet 6 OPERATIONAL STATES AND POWER MANAGEMENT 6.1 Overview The DW1000 has a number of basic operating states as follows: - Table 23: Operating States Name Description OFF The chip is powered down This is the lowest power state that allows external micro-controller access. In this state the INIT DW1000 host interface clock is running off the 38.4 MHz reference clock. In this mode the SPICLK frequency can be no greater than 3 MHz. In this state the internal clock generator is running and ready for use. The analog receiver and IDLE transmitter are powered down. Full speed SPI accesses may be used in this state. This is the lowest power state apart from the OFF state. In this state SPI communication is not possible. This state requires an external pin to be driven (can be SPICSn held low or WAKEUP DEEPSLEEP held high) for a minimum of 500 µs to indicate a wake up condition. Once the device has detected the wake up condition, the EXTON pin will be asserted and internal reference oscillator (38.4 MHz) is enabled. In this state it is possible for the DW1000 to wake up after a programmed sleep count. The low power oscillator is running and the internal sleep counter is active. The sleep counter allows for periods from approximately 300 ms to 450 hours before the DW1000 wakes up. SLEEP In this state SPI communication is not possible. In this state it is also possible for an external pin to be driven (can be SPICSn held low or WAKEUP held high) for a minimum of 500 µs to indicate a wake up condition. Once the device has detected the wake up condition, the EXTON pin will be asserted and internal reference oscillator (38.4 MHz) is enabled. RX The DW1000 is actively looking for preamble or receiving a packet In this state the DW1000 periodically enters the RX state, searches for preamble and if no RX PREAMBLE SNIFF preamble is found returns to the IDLE state. If preamble is detected it will stay in the RX state and demodulate the packet. Can be used to lower overall power consumption. TX The DW1000 is actively transmitting a packet For more information on operating states please refer to the user manual [2]. 6.2 Operating States and their effect on power consumption The DW1000 can be configured to return to any one of the states, IDLE, INIT, SLEEP or DEEPSLEEP between active transmit and receive states. This choice has implications for overall system power consumption and timing, see table below. Table 24: Operating States and their effect on power consumption DEVICE STATE IDLE INIT SLEEP DEEPSLEEP OFF Host controller Host controller Host controller command or Host controller command or command or External supplies Entry to State previous operation command previous operation previous operation are off completion completion completion SPICSn held low Host controller Host controller Sleep counter External 3.3 V Exit from State Or WAKEUP held command command timeout supply on high for 500 µs Next state Various IDLE INIT INIT INIT Current 18 mA (No DC/DC) 4 mA 1 µA 50 nA 0 Consumption 12 mA (with DC/DC) Configuration Maintained Maintained Maintained Maintained Not maintained Time before RX Immediate 5 μs 3 ms 3 ms 3 ms State Ready Time before TX Immediate 5 μs 3 ms 3 ms 3 ms State Ready In the SLEEP, DEEPSLEEP and OFF states, it is necessary to wait for the main on-board crystal oscillator to power up and stabilize before the DW1000 can be used. This introduces a delay of up to 3 ms each time the DW1000 exits SLEEP, DEEPSLEEP and OFF states. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 28

DW1000 Datasheet 6.3 Transmit and Receive power profiles 1. POWER OFF BETWEEN OPERATIONS Device ready for Configuration lost operation OSC / PLL OSC / PLL TX / RX OPERATION TX / RX OPERATION STARTUP OFF Idd = 0 STARTUP OFF Idd = 0 5 ms approx / 1mA 2. DEEP SLEEP BETWEEN OPERATIONS Device ready for Configuration retained operation OSC / PLL TX / RX OPERATION DEEPSLEEP Idd = OSC / PLL TX / RX OPERATION STARTUP 100 nA STARTUP DEEPSLEEP Idd = 100 nA 5 ms approx / 1mA 3. SLEEP BETWEEN OPERATIONS Device ready for Configuration retained operation OSC / PLL OSC / PLL TX / RX OPERATION TX / RX OPERATION STARTUP SLEEP Idd = 2 µA STARTUP SLEEP Idd = 2 µA 5 ms approx / 1mA 4. INIT STATE BETWEEN OPERATIONS Device ready for Configuration retained operation OSC / PLL PLL TX / RX OPERATION TX / RX OPERATION STARTUP INIT Idd = 4 mA LOCK INIT Idd = 4 mA 5µs approx / 5mA Figure 30: Sleep options between operations The tables below show typical configurations of the DW1000 and their associated power profiles. Table 25: Operational Modes Data Packet PRF Preamble Typical Use Case Mode Data Rate Length Duration (MHz) (Symbols) (Bytes) (µs) (Refer to DW1000 user manual for further information) RTLS, TDOA Scheme, Long Range, Low Mode 1 110 kbps 16 1024 12 2084 Density RTLS, TDOA Scheme, Short Range, High Mode 2 6.8 Mbps 16 128 12 152 Density RTLS, 2-way ranging scheme, Long Range, Mode 3 110 kbps 16 1024 30 3487 Low Density RTLS, 2-way ranging scheme, Short Range, Mode 4 6.8 Mbps 16 128 30 173 High Density Mode 5 6.8 Mbps 16 1024 1023 1339 Data transfer, Short Range, Long Payload Mode 6 6.8 Mbps 16 128 127 287 Data transfer, Short Range, Short Payload Mode 7 110 kbps 16 1024 1023 78099 Data transfer, Long Range, Long Payload Mode 8 110 kbps 16 1024 127 10730 Data transfer, Long Range, Short Payload Mode 9 110 kbps 64 1024 12 2084 As Mode 1 using 64 MHz PRF Mode 10 6.8 Mbps 64 128 12 152 As Mode 2 using 64 MHz PRF Mode 11 110 kbps 64 1024 30 3487 As Mode 3 using 64 MHz PRF Mode 12 6.8 Mbps 64 128 30 173 As Mode 4 using 64 MHz PRF Mode 13 6.8 Mbps 64 1024 1023 1339 As Mode 5 using 64 MHz PRF Mode 14 6.8 Mbps 64 128 127 287 As Mode 6 using 64 MHz PRF Mode 15 110 kbps 64 1024 1023 78099 As Mode 7 using 64 MHz PRF Mode 16 110 kbps 64 1024 127 10730 As Mode 8 using 64 MHz PRF Note: Other modes are possible © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 29

DW1000 Datasheet Table 26: Typical TX Current Consumption TX I AVG (mA) Mode Channel 2 Channel 5 Units Name Avg Preamble Data Avg Preamble Data Mode 1 48 68 35 56 74 42 mA Mode 2 68 68 50 69 74 57 mA Mode 3 44 68 35 50 74 42 mA Mode 4 60 68 51 67 74 58 mA Mode 5 50 68 51 56 74 58 mA Mode 6 56 68 51 62 74 58 mA Mode 7 35 68 35 42 74 42 mA Mode 8 38 68 35 44 74 42 mA Mode 9 61 83 40 67 89 46 mA Mode 10 79 83 52 85 89 59 mA Mode 11 52 83 40 59 89 46 mA Mode 12 75 83 52 82 89 59 mA Mode 13 53 83 52 60 89 59 mA Mode 14 65 83 52 72 89 59 mA Mode 15 40 83 40 46 89 46 mA Mode 16 43 83 40 50 89 46 mA Table 27: Typical RX Current Consumption RX I AVG (mA) Mode Channel 2 Channel 5 Units Name Data Data Avg Preamble Avg Preamble Demod Demod Mode 1 86 113 59 92 118 62 mA Mode 2 115 113 118 122 118 123 mA Mode 3 76 113 59 81 118 62 mA Mode 4 115 113 115 123 118 123 mA Mode 5 118 113 118 126 118 126 mA Mode 6 113 113 113 125 118 126 mA Mode 7 57 113 59 65 118 62 mA Mode 8 62 113 59 70 118 62 mA Mode 9 90 113 72 94 118 75 mA Mode 10 112 113 118 117 118 123 mA Mode 11 82 113 72 85 118 75 mA Mode 12 112 113 118 118 118 123 mA Mode 13 114 113 118 120 118 123 mA Mode 14 113 113 118 119 118 123 mA Mode 15 72 113 72 76 118 75 mA Mode 16 76 113 72 80 118 75 mA T = 25 ˚C, All supplies centered on typical values. All currents referenced to 3.3 V (VDDLDOA, VDDLDOD amb supplies fed via a 1.6 V 90% efficient DC/DC converter) From Table 25, Table 26 and Table 27 above it is clear that there is a trade-off between communications range and power consumption. Lower data rates allow longer range communication but consume more power. Higher data rates consume less power but have a reduced communications range. For a given payload length, the following table shows two configurations of the DW1000. The first achieves minimum power consumption (not including DEEPSLEEP, SLEEP, INIT & IDLE) and the second achieves © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 30

DW1000 Datasheet longest communication range. Table 28: Lowest power and longest range modes of operation PRF Preamble Data Rx PAC Notes Mode Data Rate Channel Length (MHz) (Symbols) (Symbols) (Refer to DW1000 user manual (Bytes) for further information) Using “tight” gearing 6.8 Mbps with tables and a TCXO as Lowest 16 64 gating gain the source of the 38.4 Power As short MHz clock at each node 2 options as 8 based on possible Using “standard” gearing hardware 6.8 Mbps with 1 tables and an XTAL as configuration gating gain 16 128 the source of the 38.4 MHz clock at each node All 3.5 GHz centre Longest 110 Kbps 16 2048 supported 32 frequency gives best Range lengths propagation The graph below shows typical range and average transmitter current consumption per frame with the transmitter running at -41.3 dBm/MHz output power and using 0 dBi gain antennas for channel 2. 90 250 TX Iavg (mA) 80 Range 200 70 60 150 50 TX I avg Range (mA) (m) 40 100 30 20 50 10 0 0 Modes Figure 31: Typical Range versus TX average current (channel 2) T = 25 ˚C, All supplies centered on typical values. All currents referenced to 3.3 V (VDDLDOA, VDDLDOD amb supplies fed via a 1.6 V 90% efficient DC/DC converter) © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 31

DW1000 Datasheet 6.3.1 Typical transmit profile TX power profile for Mode 2 (Returning to DEEPSLEEP state) mA Date rate 6.8Mb/s; Channel 2; Preamble length 128 symbols; 12 byte frame. 70 60 50 40 65 mA 30 12 Byte Packet 20 15mA 48 mA 10 3mA 12mA 100nA 5 max 0 t TX PHR / OSC STARTUP WR TX DATA TX SHR DEEPSLEEP PSDU PLL STARTUP 7µs ~2ms 10µs 135µs 16µs Power measured over this duration Figure 32: Typical TX Power Profile 6.3.2 Typical receive profiles mA RX power profile for Mode 2 (Returning to DEEPSLEEP) 130 Data rate 6.8Mb/s; Channel 2; Preamble length 128 symbols; 12 byte frame. 120 110 100 125 mA 12 Byte Frame 20 12mA 113 mA 118 mA 100nA 3mA max 10 5 12mA 0 time OSC STARTUP PREAMBLE HUNT RX SHR RX PHR/PSDU HOST RD DATA DEEPSLEEP PLL STARTUP ~2ms 7µs Variable Time 120µs 16µs 56µs Power measured over this duration Figure 33: Typical RX Power Profile mA RX power profile for Mode 2 with Preamble SNIFF mode 130 Data rate 6.8Mb/s; Channel 2; Preamble length 128 symbols; 12 byte frame. 120 110 100 12 Byte 125 mA Frame 113 113 113 113 113 20 12mA mA mA mA mA mA 118 mA 100nA 3mA Max 10 5 12mA 0 time RX PHR/ OSC STARTUP PREAMBLE SNIFF RX SHR HOST RD DATADEEPSLEEP PSDU PLL STARTUP ~2ms 7µs Variable Time 120µs 16µs 56µs Power measured over this duration Figure 34: Typical RX Power Profile using SNIFF mode © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 32

DW1000 Datasheet 7 POWER SUPPLY 7.1 Power Supply Connections There are a number of different power supply connections to the DW1000. The chip operates from a nominal 3.3 V supply. Some circuits in the chip are directly connected to the external 3.3 V supply. Other circuits are fed from a number of on-chip low-dropout regulators. The outputs of these LDO regulators are brought out to pins of the chip for decoupling purposes. Refer to Figure 35 for further details. The majority of the supplies are used in the analog & RF section of the chip where it is important to maintain supply isolation between individual circuits to achieve the required performance. 3.3 V Supply VDDIO VDDLDO VDDLDO VDDBAT VDDAO VDDLN VDDPA VDDPA A D A T N A 1 2 On-chip On-chip “Always D Digital All other W Internal LDO for LDOs for On” Rx Tx IO 3V3 1 Switches digital analog Config LNA PA 0 Ring circuits 0 circuits circuits Store 0 V V V V V V V D D D D D D D VDDIO DDIG DREG DIF DMS DVCO DCLK DSYN To External Decoupling Capacitors Figure 35: Power Supply Connections 7.2 Use of External DC / DC Converter The DW1000 supports the use of external switching regulators to reduce overall power consumption from the power source. Using switching regulators can reduce system power consumption. The EXTON pin can be used to further reduce power by disabling the external regulator when the DW1000 is in the SLEEP or DEEPSLEEP states (provided the EXTON turn on time is sufficient). 3.3 V Supply EXTON VIN EN DC / DC VOUT 1.8 V VDDIOA VDDLDOD VDDLDOA VDDBATT VDDAON VDDLNA VDDPA1 VDDPA2 On-chip On-chip “Always D Internal Digital LDO for LDOs for All other On” Rx Tx W IO 3V3 1 Switches digital analog Config LNA PA 0 Ring circuits 0 circuits circuits Store 0 V V V V V V V D D D D D D D VDDIO DDIG DREG DIF DMS DVCO DCLK DSYN To External Decoupling Capacitors Figure 36: Switching Regulator Connection © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 33

DW1000 Datasheet 7.3 Powering down the DW1000 The DW1000 has a very low DEEPSLEEP current (typ. 50 nA – see Table 3). The recommended practise is to keep the DW1000 powered up and use DEEPSLEEP mode when the device is inactive. In situations where the DW1000 must be power-cycled (the 3.3 V supply in Figure 35 / Figure 36 respectively turned off and then back on), it is important to note that when power is removed the supply voltage will decay towards 0 V at a rate determined by the characteristics of the power source and the amount of decoupling capacitance in the system. In this scenario, power should only be reapplied to the DW1000 when: -  VDDAON is above 2.3 V or:  VDDAON has fallen below 100 mV Reapplying power while VDDAON is between 100 mV and 2.3 V can lead to the DW1000 powering up in an unknown state which can only be recovered by fully powering down the device until the voltage on VDDAON falls below 100 mV. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 34

DW1000 Datasheet 8 APPLICATION INFORMATION 8.1 Application Circuit Diagram Optional Use of TCXO IRQ 0K optional external pull-down if SLEEP VDD_3V3 VCC OUT 10 or DEEPSLEEP modes are used U3 GND GND VDDDIG GND 3V LDO SPICLK GND SPIMISO 0.1uF VDD_XTC2XOVCCGNODUT 2200pF XTAL1 (paddle) VDDLDOA VDDBAT GN0.1uFD SGPPIMIOO0SI 38.4 MHz TCXO GPIO1 GXN1D GND 49 48 47 46 45 44 43 42 41 40 39 38 37 10pFGND 38.4 MHz GND10pF 123 NNCC VDDLDOA VDDBAT TESTMODE IRQ VDDDIG VSSIO VDDIO SPICLK SPIMISO SPIMOSI GPIO0 GPIO1 GGGPPPIIIOOO342 333654 GGGPPPIIIOOO432 mooppdutelilo- uncopansl effigoxture rSranPtaiIo l n XTAL1 33 4 GPIO5 GPIO5 XTAL2 32 %) G 0.1uF 56 VREF VVDSDSIIOO 31 0.1uF GND 10k 11k (1GND GND 0.1uFND 87 VVCDDLKDDTMIFUSNE DW1000 GSPYINOC6 223980 SGYPNIOC6 10k 9 VDDIOA VDDIOA 27p16k0.1uFGND 1p2 70R820p GND8p0.1uF 0.1uFGND 111012 VVVVDDDCDDDO13NCCSVTUYCLKNNO14ENC15VDDLNA16RF_P 17RF_N18VDDPA19VDDPA20VDDDREG 21EXTON22FORCEON23WAKEUP 24SPICSnVVDDDDLRDASOOTNDn 222765U1 VVDDDDLADOOND DRoTSnhT’nits D!o VDD_3V3 2 1 VDDLNA VDDPA VDDPA GND WSAPKICESUnP 0.1uFGND T1 12p EXTON Antenna GND GND RRFF TTrraacceess 110000RR U2 RF Trace 50R 12p VDDDIG En Vout VDDLDOD 0.1 uF 1V8 VDD_3V3 Vin GND VDDLDOA DC-DC Convertor (optional) VDD_3V3 VDDPA VDDPA VDDLNA VDDBAT VDDIOA VDDAON VDDLDOD VDDLDOA 47 uF 0.1 uF 10 pF 330 pF 0.1 uF 10pF 330 pF 10000 pF 0.1 uF 0.1 uF 0.1 uF 0.1 uF 0.1 uF GND Decoupling: Place capacitors close to pins Figure 37: DW1000 Application Circuit 8.2 Recommended Components Function Manufacturer Part No Ref Web Link Taiyo Yuden AH086M555003 www.yuden.co.jp Antenna Abracon ACA-107-T www.abracon.com www.digikey.com SMT UWB Balun TDK Corporation HHM1595A1 T1 http://www.tdk.co.jp/ 3-8 GHz Capacitors Murata GRM155 series www.murata.com © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 35

DW1000 Datasheet Function Manufacturer Part No Ref Web Link (Non polarized) KEMET C0805C476M9PACTU 47 µF capacitoredge.kemet.com ABM10-165-38.400MHz- Abracon www.abracon.com T3 KX-5T (need to request X1 Geyer www.geyer-electronic.de Crystal tight tolerance option) (38.4 MHz Rakon HDD10RSX-10 509344 www.rakon.com +/-10ppm) Note that the crystal loading caps must be selected according to the crystal manufacturer’s recommendation and your PCB design so as to place the nominal crystal oscillation frequency in the centre of the DW1000 crystal trim range. The values given in Figure 37 above are for example purposes only and may not apply to your design. Murata LXDC2HL_18A www.murata.com DC/DC U2 Torex XCL222B181ER-G www.torexsemi.com Resistors ROHM MCR01MZPF www.rohm.com ASTXR-12-38.400MHz- TCXO Abracon www.abracon.com 514054-T (optional use in X2 Anchor nodes. Geyer KXO-84 www.geyer-electronic.de 38.4 MHz) Rakon IT2200K 3.3V 38.4MHz www.rakon.com 8.3 Application Circuit Layout 8.3.1 PCB Stack The following 4-layer PCB stack up is one suggested stack up which can be used to achieve optimum performance. MANUFACTURING STACKUP 4-LAYER IMPEDANCE CONTROLLED PCB WITH TH VIAS File Ext Description Board Stackup GTP Top Paste GTO Top Silkscreen GTS Top Solder GTL Top Layer Copper 38 µm (finished) FR4 Core 510 µm G1 Inner Layer 1 Copper 18 µm 1 x 7628 50% FR4 Pre Preg 207 µm 1 x 106 76% FR4 Pre Preg 58 µm 1 x 7628 50% FR4 Pre Preg 207 µm G2 Inner Layer 2 Copper 18 µm FR4 Core 510 µm GBL Bottom Layer Copper 38 µm (finished) GBS Bottom Solder GBO Bottom Silkscreen GBP Bottom Paste TOTAL THICKNESS 1.600 mm +/- 10% Controlled Impedance Traces are as follows: - a) Tolerance on all lines, unless other wise specified +/- 10% b) 50 Ω Single Ended CPW Traces on Top Layer (50 Ω with reference to Inner Layer 1, no solder resist) = 0.95 mm (1.00 mm GND gap) c) 100 Ω Differential Microstrip Traces on Top Layer (100 Ω with reference to Inner Layer 1, no solder resist) = 0.235 mm Track / 0.127 mm Gap Figure 38: PCB Layer Stack for 4-layer board 8.3.2 RF Traces As with all high frequency designs, particular care should be taken with the routing and matching of the RF sections of the PCB layout. All RF traces should be kept as short as possible and where possible impedance discontinuities should be avoided. Where possible RF traces should cover component land patterns. Poor RF matching of signals to/from the antenna will degrade system performance. A 100 Ω differential impedance should be presented to the RF_P and RF_N pins of DW1000 for optimal performance. This can be realised as either 100 Ω differential RF traces or as 2 single-ended 50 Ω traces depending on the PCB layout. In most cases a single-ended antenna will be used and a wideband balun will be required to convert from 100 Ω © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 36

DW1000 Datasheet differential to 50 Ω single-ended. Figure 39 gives an example of a suggested RF section layout. In this example traces to the 12 pF series capacitors from the RF_P and RF_N pins are realised as 100 Ω differential RF traces referenced to inner layer 1. After the 12 pF capacitors the traces are realized as 50 Ω micro-strip traces again referenced to inner layer 1. Using this method, thin traces can be used to connect to DW1000 and then wider traces can be used to connect to the antenna. P N _ _ F F R R 12p T1 GND D RF Traces 100R N Antenna RF Trace 50R G RF Traces 100R RF trace - 100 Ω differential referenced to inner layer 1. 12p 2 x 50 Ω single-ended RF RF trace – 50 Ω trace can also be used. Need single ended to ensure the traces are referenced to inner referenced to correct ground layer 1 layer Figure 39: DW1000 RF Traces Layout 8.3.3 PLL Loop Filter Layout The components associated with the loop filters of the on-chip PLLs should be placed as close as possible to the chip connection pins to minimize noise pick-up on these lines. 8.3.4 Decoupling Layout All decoupling capacitors should be kept as close to their respective pins of the chip as possible to minimize trace inductance and maximize their effectiveness. 8.3.5 Layout Guidance An application note is available from Decawave together with a set of DXF files to assist customers in reproducing the optimum layout for the DW1000. PCB land-pattern libraries for the DW1000 are available for the most commonly used CAD packages. Contact Decawave for further information. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 37

DW1000 Datasheet 9 PACKAGING & ORDERING INFORMATION 9.1 Package Dimensions Parameter Min Typ Max Units Unit weight 0.105 g Figure 40: Device Package mechanical specifications © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 38

DW1000 Datasheet 9.2 Device Package Marking The diagram below shows the package markings for DW1000. Figure 41: Device Package Markings Legend: W228E-1N 7 digit manufacturing code LLLLLL 6 digit lot ID ZZ 2 digit lot split number PH Assembly location YY 2 digit year number WW 2 digit week number 9.3 Tray Information The general orientation of the 48QFN package in the tray is as shown in Figure 42. Figure 42: Tray Orientation The white dot marking in the chip’s top left hand corner aligns with the chamfered edge of the tray. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 39

DW1000 Datasheet 9.4 Tape & Reel Information 9.4.1 Important note The following diagrams and information relate to reel shipments made from 23rd March 2015 onwards. Information relating to reels shipped prior to that date may be obtained from Decawave. 9.4.2 Tape Orientation and Dimensions The general orientation of the 48QFN package in the tape is as shown in Figure 43. User Direction of Feed Figure 43: Tape & Reel orientation K0 B0 T Expanded Section ‘X - X’ Dimensions Values Notes Ao 6.3 ± 0.1 Bo 6.3 ± 0.1 All dimensions in mm Ko 1.1 ± 0.1 sprocket hole pitch cumulative tolerance ± 0.20 P 12.00 ± 0.1 Material: Conductive Polystyrene T 0.30 ± 0.05 Camber not to exceed 1.0 mm in 250 mm W 16.00 + 0.30 – 0.10 Figure 44: Tape dimensions 9.4.3 Reel Information: 330 mm Reel Base material: High Impact Polystyrene with Integrated Antistatic Additive Surface resistivity: Antistatic with surface resistivity less than 1 x 10e12 Ohms per square © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 40

DW1000 Datasheet Tape A B D N W2 W3 W4 C W1 Width Diameter (min) (min) Hub (max) (min) (max) 13 + 0.5 - 100 / 150 16.4 + 16 330 / 380 1.5 20.2 22.4 15.9 19.4 0.2 +/-1 mm 2.0 – 0.0 Figure 45: 330 mm reel dimensions All dimensions and tolerances are fully compliant with EIA- 481-C and are specified in millimetres. 9.4.4 Reel Information: 180 mm reel Base material: High impact polystyrene with integrated antistatic additive. Surface resistivity: Antistatic with surface resistivity less than 1 x 10e12 Ohms per square. Tape Width A Diameter C D (min) N Hub W1 W2 (max) 16 178 +/- 1.0 13.5 +/- 0.5 20.2 60 + 1.0 – 0.0 17 +/- 0.5 19.5 Figure 46: 180 mm reel dimensions All dimensions and tolerances are fully compliant with EIA- 481-C and are specified in millimetres. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 41

DW1000 Datasheet 9.5 Reflow profile The DW1000 should be soldered using the reflow profile specified in JEDEC J-STD-020 as adapted for the particular PCB onto which the IC is being soldered. 9.6 Ordering Information The standard qualification for the DW1000 is industrial temperature range: -40 ºC to +85 ºC, packaged in a 48- pin QFN package. Table 29: Device ordering information Ordering Codes: High Volume Ordering code Status Package Type Package Qty Note DW1000-I Active Tray 490 Available DW1000-ITR7 Active Tape & Reel 1000 Available DW1000-ITR13 Active Tape & Reel 4000 Available Samples Ordering Code Status Package Type Package Qty Note DW1000-I Active Tray 10-490 Available DW1000-ITR7 Active Tape & Reel 100 – 1000 Available DW1000-ITR13 Active Tape & Reel 100 – 4000 Available All IC’s are packaged in a 48-pin QFN package which is Pb free, RoHS, Green, NiPd lead finish, MSL level 3 IC Operation Temperature -40 ºC to +85 ºC. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 42

DW1000 Datasheet 10 GLOSSARY Table 30: Glossary of Terms Abbreviation Full Title Explanation Equivalent The amount of power that a theoretical isotropic antenna (which evenly distributes EIRP Isotropically power in all directions) would emit to produce the peak power density observed in the Radiated Power direction of maximum gain of the antenna being used. European Regulatory body in the EU charged with the management of the radio spectrum and ETSI Telecommunication the setting of regulations for devices that use it Standards Institute Federal Regulatory body in the USA charged with the management of the radio spectrum and FCC Communications the setting of regulations for devices that use it. Commission FFD Full Function Device Defined in the context of the IEEE802.15.4-2011 [1] standard. General Purpose Pin of an IC that can be configured as an input or output under software control and GPIO Input / Output has no specifically identified function. Institute of Electrical Is the world’s largest technical professional society. It is designed to serve IEEE and Electronic professionals involved in all aspects of the electrical, electronic and computing fields Engineers and related areas of science and technology. Long Inter-Frame Defined in the context of the IEEE802.15.4-2011 [1] standard. LIFS Spacing Circuit normally found at the front-end of a radio receiver designed to amplify very low LNA Low Noise Amplifier level signals while keeping any added noise to as low a level as possible Physical radio channel configuration in which there is a direct line of sight between LOS Line of Sight the transmitter and the receiver. A technique allowing a signal to be driven by more than one device. Generally, each device is permitted to pull the signal to ground but when not doing so it must allow the Open Drain Open Drain signal to float. Devices should not drive the signal high so as to prevent contention with devices attempting to pull it low. Physical radio channel configuration in which there is no direct line of sight between NLOS Non Line of Sight the transmitter and the receiver. Programmable Gain Amplifier whose gain can be set / changed via a control mechanism usually by PGA Amplifier changing register values. Circuit designed to generate a signal at a particular frequency whose phase is related PLL Phase Locked Loop to an incoming “reference” signal. Used to quantify very small relative proportions. Just as 1% is one out of a hundred, PPM Parts Per Million 1 ppm is one part in a million. Generally used to refer to signals in the range of 3 kHz to 300 GHz. In the context of RF Radio Frequency a radio receiver, the term is generally used to refer to circuits in a receiver before down-conversion takes place and in a transmitter after up-conversion takes place. Reduced Function Defined in the context of the IEEE802.15.4-2011 [1] standard. RFD Device Real Time Location System intended to provide information on the location of various items in real-time. RTLS System Start of Frame Defined in the context of the IEEE802.15.4-2011 [1] standard. SFD Delimiter Short Inter-Frame Defined in the context of the IEEE802.15.4-2011 [1] standard. SIFS Spacing Serial Peripheral An industry standard method for interfacing between IC’s using a synchronous serial SPI Interface scheme first introduced by Motorola. Temperature A crystal oscillator whose output frequency is very accurately maintained at its TCXO Controlled Crystal specified value over its specified temperature range of operation. Oscillator Method of measuring the physical distance between two radio units by exchanging TWR Two Way Ranging messages between the units and noting the times of transmission and reception. Refer to Decawave’s website for further information. Method of deriving information on the location of a transmitter. The time of arrival of a transmission at two physically different locations whose clocks are synchronized is Time Difference of noted and the difference in the arrival times provides information on the location of TDOA Arrival the transmitter. A number of such TDOA measurements at different locations can be used to uniquely determine the position of the transmitter. Refer to Decawave’s website for further information. UWB Ultra Wideband A radio scheme employing channel bandwidths of, or in excess of, 500 MHz. © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 43

DW1000 Datasheet Abbreviation Full Title Explanation WSN Wireless Sensor A network of wireless nodes intended to enable the monitoring and control of the Network physical environment. 11 REFERENCES [1] IEEE802.15.4-2011 or “IEEE Std 802.15.4™‐2011” (Revision of IEEE Std 802.15.4-2006). IEEE Standard for Local and metropolitan area networks – Part 15.4: Low-Rate Wireless Personal Area Networks (LR- WPANs). IEEE Computer Society Sponsored by the LAN/MAN Standards Committee. Available from http://standards.ieee.org/ [2] Decawave DW1000 User Manual www.decawave.com [3] www.etsi.org [4] www.fcc.gov [5] EIA-481-C Standard 12 DOCUMENT HISTORY Table 31: Document History Revision Date Description 2.00 7th November 2012 Initial release for production device. 2.01 31st March, 2014 Scheduled update 2.02 8th July 2014 Scheduled update 2.03 30th September 2014 Scheduled update 2.04 31st December 2014 Scheduled update 2.05 31st March 2015 Scheduled update 2.06 30th June 2015 Scheduled update 2.07 30th September 2015 Scheduled update 2.08 31st December 2015 Scheduled update 2.09 31st March 2016 Scheduled update 2.10 30th June 2016 Scheduled update 2.11 30th September 2016 Scheduled update 13 MAJOR CHANGES Revision 2.03 Page Change Description All Update of version number to 2.03 All Various typographical changes 15 Modification to figure 11 caption 21 Addition of text relating to use of RSTn as indicator to external µcontroller 35 Change to application schematic to modify value of TCXO coupling capacitor 36 Correction of Rakon TCXO part number Addition of v2.03 to revision history table 44 Addition of this table and section heading Modification of heading format on this page only Revision 2.04 Page Change Description All Update of version number to 2.04 All Various typographical changes 2 Update of table of contents 23 Modification of SPI timing diagrams figure 25 & 26 to correct timing definitions 33 Addition of section 7.3 re power down © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 44

DW1000 Datasheet Page Change Description 37 Change of page orientation to landscape to expand figure 39 for legibility Corrections to v2.03 change table 43 Addition of v2.04 to revision history table Addition of this table 43 Removal of page breaks in heading numbers 11, 12, 13 and 14 Revision 2.05 Page Change Description All Update of version number to 2.05 2 Update to table of contents 4 Modification of copyright notice to 2015 Modifications to Table 6 re Rx sensitivity conditions and Table 7 re recommended TCXO coupling 11 capacitor value 20 Update to Figure 20 and Table 15 to further clarify power up timings 21 addition of Figure 21 to further clarify power up timings 23 Addition to heading of Table 16 34 Addition of clarification re power supplies that should be removed to power down the chip 38 Addition of device weight to Figure 40 44 Addition of v2.05 to revision history table 45 Addition of this table Revision 2.06 Page Change Description All Update of version number to 2.06 All Various typographical / formatting changes 1 Addition of pin pitch / Update to SLEEP current & DEEPSLEEP current 2 Update to table of contents 10 Addition to table 3 to indicate max digital input voltage 37 Modification to figure 39 to clarify referenced layers for impedance matching purposes 40 – 41 Changes to tape and reel drawings NOTE CHANGE IN QFN ORIENTATION vs. FEED DIRECTION 44 Addition of v2.06 to revision history table 45 Addition of this table Revision 2.07 Page Change Description All Update of version number to 2.07 All Various typographical / formatting changes 35 – 36 Addition of Abracon parts to “Recommended Components” table 44 Addition of v2.07 to revision history table 45 Addition of this table Revision 2.08 Page Change Description All Update of version number to 2.08 All Various typographical / formatting changes 10 Update to typ current values for INIT & IDLE states 35 Figure 37: Addition of decoupling caps on VDDLDOA and VDDLDOD 37 Clarification of reference layers in Figure 38 44 Addition of v2.08 to revision history table 45 Addition of this table © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 45

DW1000 Datasheet Revision 2.09 Page Change Description All Update of version number to 2.09 All Various typographical / formatting changes 20 Modifications to description of power up sequence in section 5.6 to clarify use and control of RSTn including addition of new section 5.6.3 and new Table 16 36 Modification to Figure 38 to correct impedance reference layer from 2 to 1 37 Modification to Figure 37 to include external LDO for TCXO 44 Addition of 2.09 to Table 31 46 Addition of this Table Revision 2.10 Page Change Description All Update of version number to 2.10 All Various typographical / formatting changes 7 Correction of pinout functionality for GPIO5 & 6 in Figure 2 8 Correction of pinout functionality for GPIO5 & 6 in Table 1 8 Addition of explanatory text to GPIO and WAKEUP pins in Table 1 39 Modifications to Figure 41 to reflect actual device markings 39 Modification to Figure 42 to reflect actual device markings 42 Addition of section 9.5 dealing with reflow soldering profile 42 Change of numbering of previous section 9.5 to 9.6 44 Addition of 2.10 to Table 31 46 Addition of this Table Revision 2.11 Page Change Description All Update of version number to 2.11 36 Modification to Figure 37 to remove 4.7 uF capacitor on VDDLDOA 37 Addition of DCDC converter part to recommended components table 46 Addition of 2.11 to Table 31 48 Addition of this Table Revision 2.12 Page Change Description All Update of version number to 2.12 28 Extended description of the SLEEP state and methods of exiting it. 35 Abracon added as current antenna manufacturer © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 46

DW1000 Datasheet 14 ABOUT DECAWAVE Decawave is a pioneering fabless semiconductor company whose flagship product, the DW1000, is a complete, single chip CMOS Ultra-Wideband IC based on the IEEE 802.15.4-2011 [1] UWB standard. This device is the first in a family of parts that will operate at data rates of 110 kbps, 850 kbps, 6.8 Mbps. The resulting silicon has a wide range of standards-based applications for both Real Time Location Systems (RTLS) and Ultra Low Power Wireless Transceivers in areas as diverse as manufacturing, healthcare, lighting, security, transport, inventory & supply chain management. Further Information For further information on this or any other Decawave product contact a sales representative as follows: - Decawave Ltd Adelaide Chambers Peter Street Dublin 8 Ireland e: sales@decawave.com w: www.decawave.com © Decawave Ltd 2016 Subject to change without notice Version 2.12 Page 47