dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 16-Bit Digital Signal Controllers with High-Speed PWM, ADC and Comparators Operating Conditions Timers/Output Compare/Input Capture • 3.0V to 3.6V, -40ºC to +85ºC, DC to 50 MIPS • Six General Purpose Timers: • 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS - Five 16-bit and up to two 32-bit timers/counters • Four Output Compare (OC) modules Configurable as Core: 16-Bit dsPIC33F Timers/Counters • Code-Efficient (C and Assembly) Architecture • Quadrature Encoder Interface (QEI) module • Two 40-Bit Wide Accumulators Configurable as Timer/Counter • Single-Cycle (MAC/MPY) with Dual Data Fetch • Four Input Capture (IC) modules • Single-Cycle Mixed-Sign MUL plus Hardware Divide Communication Interfaces • 32-Bit Multiply Support • Two UART modules (12.5 Mbps): Clock Management - With support for LIN/J2602 2.0 protocols and IrDA® • ±1% Internal Oscillator • Two 4-Wire SPI modules (15 Mbps) • Programmable PLLs and Oscillator Clock Sources • ECAN™ module (1 Mbaud) with ECAN 2.0B Support • Fail-Safe Clock Monitor (FSCM) • Two I2C™ modules (up to 1 Mbaud) with SMBus • Independent Watchdog Timer (WDT) Support • Fast Wake-up and Start-up Direct Memory Access (DMA) Power Management • 4-Channel DMA with User-Selectable Priority • Low-Power Management modes (Sleep, Idle, Doze) Arbitration • Integrated Power-on Reset and Brown-out Reset • UART, SPI, ECAN, IC, OC and Timers • 1.7 mA/MHz Dynamic Current (typical) Input/Output • 50 µA IPD Current (typical) • Sink/Source 18 mA on 18 Pins, 10 mA on 1 Pin or High-Speed PWM 6mA on 66 Pins • Up to 9 PWM Pairs with Independent Timing • 5V Tolerant Pins • Dead Time for Rising and Falling Edges • Selectable Open-Drain and Pull-ups • 1.04 ns PWM Resolution • 29 External Interrupts • PWM Support for: Qualification and Class B Support - DC/DC, AC/DC, Inverters, PFC, Lighting - BLDC, PMSM, ACIM, SRM • AEC-Q100 REVG (Grade 1, -40ºC to +125ºC) • Programmable Fault Inputs • Class B Safety Library, IEC 60730, VDE Certified • Flexible Trigger Configurations for ADC Conversions Debugger Development Support Advanced Analog Features • In-Circuit and In-Application Programming • High-Speed ADC module: • Two Program and Two Complex Data Breakpoints - 10-bit resolution with up to two Successive • IEEE 1149.2 Compatible (JTAG) Boundary Scan Approximation Register (SAR) converters • Trace and Run-Time Watch (up to 4 Msps) - Up to 24 input channels grouped into 12 conversion pairs plus two voltage reference monitoring inputs - Dedicated result buffer for each analog channel • Flexible and Independent ADC Trigger Sources • Up to 4 High-Speed Comparators with Direct Connection to the PWM module: - 10-bit Digital-to-Analog Converter (DAC) for each comparator - DAC reference output - Programmable references with 1024 voltage points  2009-2014 Microchip Technology Inc. DS7000591F-page 1

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed in Table1. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 CONTROLLER FAMILIES ADC s) s Device Pins ogram Flash Memory (Kbyte RAM (Bytes) 16-Bit Timers Input Capture Output Compare UART uadrature Encoder Interface SPI ECAN™ DMA Channels PWM Analog Comparators External Interrupts DAC Output 2IC™ SARs ple-and-Hold (S&H) Circuits Analog-to-Digital Inputs I/O Pins Packages r Q m P a S dsPIC33FJ32GS406 64 32 4K 5 4 4 2 1 2 0 0 6x2 0 5 0 2 1 5 16 58 PT, MR dsPIC33FJ32GS606 64 32 4K 5 4 4 2 2 2 0 0 6x2 4 5 1 2 2 6 16 58 PT, MR dsPIC33FJ32GS608 80 32 4K 5 4 4 2 2 2 0 0 8x2 4 5 1 2 2 6 18 74 PT dsPIC33FJ32GS610 100 32 4K 5 4 4 2 2 2 0 0 9x2 4 5 1 2 2 6 24 85 PT, PF dsPIC33FJ64GS406 64 64 8K 5 4 4 2 1 2 0 0 6x2 0 5 0 2 1 5 16 58 PT, MR dsPIC33FJ64GS606 64 64 9K(1) 5 4 4 2 2 2 1 4 6x2 4 5 1 2 2 6 16 58 PT, MR dsPIC33FJ64GS608 80 64 9K(1) 5 4 4 2 2 2 1 4 8x2 4 5 1 2 2 6 18 74 PT dsPIC33FJ64GS610 100 64 9K(1) 5 4 4 2 2 2 1 4 9x2 4 5 1 2 2 6 24 85 PT, PF Note 1: RAM size is inclusive of 1-Kbyte DMA RAM. DS7000591F-page 2  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams 64-Pin TQFP = Pins are up to 5V tolerant 7 D R 1 L/RE4H/RE3L/RE2H/RE1L/FLT8/RE0 4/RF0 H/UPDN1/CN16/L/CN15/RD6H/CN14/RD5L/CN13/RD4YNCO1/RD3LT7/RD2YNCO2/FLT6/RD WM3WM2WM2WM1WM1F1YNCI DD CAPWM5WM5WM6WM6C4/SC3/FC2/S PPPPPRSVVPPPPOOO 4321098765432109 6666655555555554 PWM3H/RE5 1 48 PGEC2/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 47 PGED2/SOSCI/T4CK/CN1/RC13 PWM4H/RE7 3 46 OC1/QEB1/FLT5/RD0 SCK2/FLT12/CN8/RG6 4 45 IC4/QEA1/FLT4/INT4/RD11 SDI2/FLT11/CN9/RG7 5 44 IC3/INDX1/FLT3/INT3/RD10 SDO2/FLT10/CN10/RG8 6 43 IC2/FLT2/U1CTS/INT2/RD9 MCLR 7 42 IC1/FLT1/SYNCI1/INT1/RD8 SS2/FLT9/SYNCI2/CN11/RG9 8 dsPIC33FJ32GS406 41 VSS VSS 9 dsPIC33FJ64GS406 40 OSC2/REFCLKO/CLKO/RC15 VDD 10 39 OSC1/CLKIN/RC12 AN5/AQEB1/CN7/RB5 11 38 VDD AN4/AQEA1/CN6/RB4 12 37 SCL1/RG2 AN3/AINDX1/CN5/RB3 13 36 SDA1/RG3 AN2/ASS1/CN4/RB2 14 35 U1RTS/SCK1/INT0/RF6 PGEC3/AN1/CN3/RB1 15 34 U1RX/SDI1/RF2 PGED3/AN0/CN2/RB0 16 33 U1TX/SDO1/RF3 7890123456789012 1112222222222333 67 D S8901 S D234545 BB D SBB11 S D1111FF RRVVRRBBVVBBBBRR PGEC1/AN6/OCFA/PGED1/AN7/AAAN8/U2CTS/AN9/TMS/AN10/RTDO/AN11/R TCK/AN12/RTDI/AN13/RAN14/SS1/U2RTS/RAN15/CN12/RX/SDA2/FLT17/CN17/X/SCL2/FLT18/CN18/ RT U2U2  2009-2014 Microchip Technology Inc. DS7000591F-page 3

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 64-Pin QFN = Pins are up to 5V tolerant 7 D R 1 L/RE4H/RE3L/RE2H/RE1L/FLT8/RE0 4/RF0 H/UPDN1/CN16/L/CN15/RD6H/CN14/RD5L/CN13/RD4YNCO1/RD3LT7/RD2YNCO2/FLT6/RD WM3WM2WM2WM1WM1F1YNCI DD CAP WM5WM5WM6WM6C4/SC3/FC2/S PPPPPRSVVPPPPOOO 64636261605958575655545352515049 PWM3H/RE5 1 48 PGEC2/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 47 PGED2/SOSCI/T4CK/CN1/RC13 PWM4H/RE7 3 46 OC1/QEB1/FLT5/RD0 SCK2/FLT12/CN8/RG6 4 45 IC4/QEA1/FLT4/INT4/RD11 SDI2/FLT11/CN9/RG7 5 44 IC3/INDX1/FLT3/INT3/RD10 SDO2/FLT10/CN10/RG8 6 43 IC2/FLT2/U1CTS/INT2/RD9 MCLR 7 42 IC1/FLT1/SYNCI1/INT1/RD8 SS2/FLT9/SYNCI2/CN11/RG9 8 dsPIC33FJ32GS406 41 VSS VSS 9 dsPIC33FJ64GS406 40 OSC2/REFCLKO/CLKO/RC15 VDD 10 39 OSC1/CLKIN/RC12 AN5/AQEB1/CN7/RB5 11 38 VDD AN4/AQEA1/CN6/RB4 12 37 SCL1/RG2 AN3/AINDX1/CN5/RB3 13 36 SDA1/RG3 AN2/ASS1/CN4/RB2 14 35 U1RTS/SCK1/INT0/RF6 PGEC3/AN1/CN3/RB1 15 34 U1RX/SDI1/RF2 PGED3/AN0/CN2/RB0 16 33 U1TX/SDO1/RF3 17181920212223242526272829303132 67 Ds8901 S D234545 RBRBVDVsRBRBB1B1VS VDB1B1B1B1RFRF PGEC1/AN6/OCFA/PGED1/AN7/AAAN8/U2CTS/AN9/TMS/AN10/RTDO/AN11/R TCK/AN12/RTDI/AN13/RAN14/SS1/U2RTS/RAN15/CN12/RX/SDA2/FLT17/CN17/X/SCL2/FLT18/CN18/ U2RU2T Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS7000591F-page 4  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 64-Pin TQFP = Pins are up to 5V tolerant 7 D R 1 L/RE4H/RE3L/RE2H/RE1L/FLT8/RE0 4/RF0 H/UPDN1/CN16/L/CN15/RD6H/CN14/RD5L/CN13/RD4YNCO1/RD3LT7/RD2YNCO2/FLT6/RD WM3WM2WM2WM1WM1F1YNCI DD CAPWM5WM5WM6WM6C4/SC3/FC2/S PPPPPRSVVPPPPOOO 4321098765432109 6666655555555554 PWM3H/RE5 1 48 PGEC2/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 47 PGED2/SOSCI/T4CK/CN1/RC13 PWM4H/RE7 3 46 OC1/QEB1/FLT5/RD0 SCK2/FLT12/CN8/RG6 4 45 IC4/QEA1/FLT4/INT4/RD11 SDI2/FLT11/CN9/RG7 5 44 IC3/INDX1/FLT3/INT3/RD10 SDO2/FLT10/CN10/RG8 6 43 IC2/FLT2/U1CTS/INT2/RD9 MCLR 7 42 IC1/FLT1/SYNCI1/INT1/RD8 SS2/FLT9/SYNCI2/T5CK/CN11/RG9 8 dsPIC33FJ32GS606 41 VSS VSS 9 40 OSC2/REFCLKO/CLKO/RC15 VDD 10 39 OSC1/CLKIN/RC12 AN5/CMP3B/AQEB1/CN7/RB5 11 38 VDD AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 12 37 SCL1/RG2 AN3/CMP2B/AINDX1/CN5/RB3 13 36 SDA1/RG3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 14 35 U1RTS/SCK1/INT0/RF6 PGEC3/AN1/CMP1B/CN3/RB1 15 34 U1RX/SDI1/RF2 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 16 33 U1TX/SDO1/RF3 7890123456789012 1112222222222333 67 D S8901 S D234545 BB D SBB11 S D1111FF RRVVRRBBVVBBBBRR EC1/AN6/CMP3C/CMP4A/OCFA/PGED1/AN7/CMP4B/AAAN8/U2CTS/AN9/DACOUT/TMS/AN10/INDX2/RTDO/AN11/EXTREF/R TCK/AN12/CMP1D/RTDI/AN13/CMP2D/RAN14/CMP3D/SS1/U2RTS/RAN15/CMP4D/CN12/RU2RX/SDA2/QEA2/FLT17/CN17/U2TX/SCL2/QEB2/FLT18/CN18/ G P  2009-2014 Microchip Technology Inc. DS7000591F-page 5

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 64-Pin TQFP = Pins are up to 5V tolerant 7 D R 1 L/RE4H/RE3L/RE2H/RE1L/FLT8/RE0RF1SYNCI4/RF0 H/UPDN1/CN16/L/CN15/RD6H/CN14/RD5L/CN13/RD4YNCO1/RD3LT7/RD2YNCO2/FLT6/RD WM3WM2WM2WM1WM11TX/1RX/ DD CAPWM5WM5WM6WM6C4/SC3/FC2/S PPPPPCCVVPPPPOOO 4321098765432109 6666655555555554 PWM3H/RE5 1 48 PGEC2/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 47 PGED2/SOSCI/T4CK/CN1/RC13 PWM4H/RE7 3 46 OC1/QEB1/FLT5/RD0 SCK2/FLT12/CN8/RG6 4 45 IC4/QEA1/FLT4/INT4/RD11 SDI2/FLT11/CN9/RG7 5 44 IC3/INDX1/FLT3/INT3/RD10 SDO2/FLT10/CN10/RG8 6 43 IC2/FLT2/U1CTS/INT2/RD9 MCLR 7 42 IC1/FLT1/SYNCI1/INT1/RD8 SS2/FLT9/SYNCI2/T5CK/CN11/RG9 8 dsPIC33FJ64GS606 41 VSS VSS 9 40 OSC2/REFCLKO/CLKO/RC15 VDD 10 39 OSC1/CLKIN/RC12 AN5/CMP3B/AQEB1/CN7/RB5 11 38 VDD AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 12 37 SCL1/RG2 AN3/CMP2B/AINDX1/CN5/RB3 13 36 SDA1/RG3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 14 35 U1RTS/SCK1/INT0/RF6 PGEC3/AN1/CMP1B/CN3/RB1 15 34 U1RX/SDI1/RF2 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 16 33 U1TX/SDO1/RF3 7890123456789012 1112222222222333 67 D S8901 S D234545 BB D SBB11 S D1111FF RRVVRRBBVVBBBBRR EC1/AN6/CMP3C/CMP4A/OCFA/PGED1/AN7/CMP4B/AAAN8/U2CTS/AN9/DACOUT/TMS/AN10/INDX2/RTDO/AN11/EXTREF/R TCK/AN12/CMP1D/RTDI/AN13/CMP2D/RAN14/CMP3D/SS1/U2RTS/RAN15/CMP4D/CN12/RU2RX/SDA2/QEA2/FLT17/CN17/U2TX/SCL2/QEB2/FLT18/CN18/ G P DS7000591F-page 6  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 64-Pin QFN = Pins are up to 5V tolerant 7 D R 1 L/RE4H/RE3L/RE2H/RE1L/FLT8/RE0 4/RF0 H/UPDN1/CN16/L/CN15/RD6H/CN14/RD5L/CN13/RD4YNCO1/RD3LT7/RD2YNCO2/FLT6/RD WM3WM2WM2WM1WM1F1YNCI DD CAPWM5WM5WM6WM6C4/SC3/FC2/S PPPPPRSVVPPPPOOO 64636261605958575655545352515049 PWM3H/RE5 1 48 PGEC2/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 47 PGED2/SOSCI/T4CK/CN1/RC13 PWM4H/RE7 3 46 OC1/QEB1/FLT5/RD0 SCK2/FLT12/CN8/RG6 4 45 IC4/QEA1/FLT4/INT4/RD11 SDI2/FLT11/CN9/RG7 5 44 IC3/INDX1/FLT3/INT3/RD10 SDO2/FLT10/CN10/RG8 6 43 IC2/FLT2/U1CTS/INT2/RD9 MCLR 7 42 IC1/FLT1/SYNCI1/INT1/RD8 SS2/FLT9/SYNCI2/T5CK/CN11/RG9 8 41 VSS dsPIC33FJ32GS606 VSS 9 40 OSC2/REFCLKO/CLKO/RC15 VDD 10 39 OSC1/CLKIN/RC12 AN5/CMP3B/AQEB1/CN7/RB5 11 38 VDD AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 12 37 SCL1/RG2 AN3/CMP2B/AINDX1/CN5/RB3 13 36 SDA1/RG3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 14 35 U1RTS/SCK1/INT0/RF6 PGEC3/AN1/CMP1B/CN3/RB1 15 34 U1RX/SDI1/RF2 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 16 33 U1TX/SDO1/RF3 17181920212223242526272829303132 67 D S8901 S D234545 BB D SBB11 S D1111FF RRVVRRBBVVBBBBRR EC1/AN6/CMP3C/CMP4A/OCFA/PGED1/AN7/CMP4B/AAAN8/U2CTS/AN9/DACOUT/TMS/AN10/INDX2/RTDO/AN11/EXTREF/R TCK/AN12/CMP1D/RTDI/AN13/CMP2D/RAN14/CMP3D/SS1/U2RTS/RAN15/CMP4D/CN12/RU2RX/SDA2/QEA2/FLT17/CN17/U2TX/SCL2/QEB2/FLT18/CN18/ G P Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.  2009-2014 Microchip Technology Inc. DS7000591F-page 7

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 64-Pin QFN = Pins are up to 5V tolerant 7 D R 1 L/RE4H/RE3L/RE2H/RE1L/FLT8/RE0RF1SYNCI4/RF0 H/UPDN1/CN16/L/CN15/RD6H/CN14/RD5L/CN13/RD4YNCO1/RD3LT7/RD2YNCO2/FLT6/RD WM3WM2WM2WM1WM11TX/1RX/ DD CAPWM5WM5WM6WM6C4/SC3/FC2/S PPPPPCCVVPPPPOOO 64636261605958575655545352515049 PWM3H/RE5 1 48 PGEC2/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 47 PGED2/SOSCI/T4CK/CN1/RC13 PWM4H/RE7 3 46 OC1/QEB1/FLT5/RD0 SCK2/FLT12/CN8/RG6 4 45 IC4/QEA1/FLT4/INT4/RD11 SDI2/FLT11/CN9/RG7 5 44 IC3/INDX1/FLT3/INT3/RD10 SDO2/FLT10/CN10/RG8 6 43 IC2/FLT2/U1CTS/INT2/RD9 MCLR 7 42 IC1/FLT1/SYNCI1/INT1/RD8 SS2/FLT9/SYNCI2/T5CK/CN11/RG9 8 dsPIC33FJ64GS606 41 VSS VSS 9 40 OSC2/REFCLKO/CLKO/RC15 VDD 10 39 OSC1/CLKIN/RC12 AN5/CMP3B/AQEB1/CN7/RB5 11 38 VDD AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 12 37 SCL1/RG2 AN3/CMP2B/AINDX1/CN5/RB3 13 36 SDA1/RG3 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 14 35 U1RTS/SCK1/INT0/RF6 PGEC3/AN1/CMP1B/CN3/RB1 15 34 U1RX/SDI1/RF2 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 16 33 U1TX/SDO1/RF3 17181920212223242526272829303132 67 D S8901 S D234545 BB D SBB11 S D1111FF RRVVRRBBVVBBBBRR EC1/AN6/CMP3C/CMP4A/OCFA/PGED1/AN7/CMP4B/AAAN8/U2CTS/AN9/DACOUT/TMS/AN10/INDX2/RTDO/AN11/EXTREF/R TCK/AN12/CMP1D/RTDI/AN13/CMP2D/RAN14/CMP3D/SS1/U2RTS/RAN15/CMP4D/CN12/RU2RX/SDA2/QEA2/FLT17/CN17/U2TX/SCL2/QEB2/FLT18/CN18/ G P Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS7000591F-page 8  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 80-Pin TQFP = Pins are up to 5V tolerant D7 D3 R R 1 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2PWM1H/RE1 PWM1L/FLT8/RE0 INDX2/SYNCI4/RG0 QEB2/RG1 C1TX/RF1C1RX/RF0VDD VCAP PWM5H/UPDN1/CN16/ PWM5L/CN15/RD6 PWM6H/CN14/RD5PWM6L/CN13/RD4PWM7L/CN19/RD13 QEA2/RD12PWM7H/OC4/SYNCO1/OC3/FLT7/RD2OC2/SYNCO2/FLT6/RD 8079 78 7776 75 74 7372 71 70 69 6867 6665 64 6362 61 PWM3H/RE5 1 60 PGEC2/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 59 PGED2/SOSCI/T4CK/CN1/RC13 PWM4H/RE7 3 58 OC1/QEB1/FLT5/RD0 AN16/T2CK/RC1 4 57 IC4/QEA1/FLT4/RD11 AN17/T3CK/RC2 5 56 IC3/INDX1/FLT3/RD10 SCK2/FLT12/CN8/RG6 6 55 IC2/FLT2/RD9 SDI2/FLT11/CN9/RG7 7 54 IC1/FLT1/SYNCI1/RD8 SDO2/FLT10/CN10/RG8 8 53 SDA2/INT4/FLT19/RA15 MCLR 9 52 SCL2/INT3/FLT20/RA14 SS2/FLT9/T5CK/CN11/RG9 10 51 VSS VSS 11 dsPIC33FJ32GS608 50 OSC2/REFCLKO/CLKO/RC15 VDD 12 49 OSC1/CLKIN/RC12 TMS/FLT13/INT1/RE8 13 48 VDD TDO/FLT14/INT2/RE9 14 47 SCL1/RG2 AN5/CMP3B/AQEB1/CN7/RB5 15 46 SDA1/RG3 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 16 45 SCK1/INT0/RF6 AN3/CMP2B/AINDX1/CN5/RB3 17 44 SDI1/RF7 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 18 43 SDO1/RF8 PGEC3/AN1/CMP1B/CN3/RB1 19 42 U1RX/RF2 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 20 41 U1TX/RF3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1/AN6CMP3C/CMP4A/OCFA/RB6 PGED1/AN7/CMP4B/RB7 PWM8L/RA9 PWM8H/RA10 AVDD AVSS AN8/U2CTS/RB8 AN9/DACOUT/RB9 AN10/RB10 AN11/EXTREF/RB11 VSS VDD TCK/AN12/CMP1D/RB12 TDI/AN13/CMP2D/RB13 AN14/CMP3D/SS1/U2RTS/RB14 AN15/CMP4D/CN12/RB151CTS/FLT15/SYNCI3/CN20/RD14 /FLT16/SYNCI2/CN21/RD151RTS U2RX/FLT17/CN17/RF4 U2TX/FLT18/CN18/RF5 C U U E G P  2009-2014 Microchip Technology Inc. DS7000591F-page 9

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 80-Pin TQFP = Pins are up to 5V tolerant D7 D3 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2PWM1H/RE1 PWM1L/FLT8/RE0 INDX2/SYNCI4/RG0 QEB2/RG1C1TX/RF1C1RX/RF0VDD VCAP PWM5H/UPDN1/CN16/R PWM5L/CN15/RD6 PWM6H/CN14/RD5PWM6L/CN13/RD4PWM7L/CN19/RD13 QEA2/RD12PWM7H/OC4/SYNCO1/ROC3/FLT7/RD2OC2/SYNCO2/FLT6/RD1 8079 7877 76 75 74 7372 71 70 69 6867 6665 6463 62 61 PWM3H/RE5 1 60 PGEC2/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 59 PGED2/SOSCI/T4CK/CN1/RC13 PWM4H/RE7 3 58 OC1/QEB1/FLT5/RD0 AN16/T2CK/RC1 4 57 IC4/QEA1/FLT4/RD11 AN17/T3CK/RC2 5 56 IC3/INDX1/FLT3/RD10 SCK2/FLT12/CN8/RG6 6 55 IC2/FLT2/RD9 SDI2/FLT11/CN9/RG7 7 54 IC1/FLT1/SYNCI1/RD8 SDO2/FLT10/CN10/RG8 8 53 SDA2/INT4/FLT19/RA15 MCLR 9 52 SCL2/INT3/FLT20/RA14 SS2/FLT9/T5CK/CN11/RG9 10 dsPIC33FJ64GS608 51 VSS VSS 11 50 OSC2/REFCLKO/CLKO/RC15 VDD 12 49 OSC1/CLKIN/RC12 TMS/FLT13/INT1/RE8 13 48 VDD TDO/FLT14/INT2/RE9 14 47 SCL1/RG2 AN5/CMP3B/AQEB1/CN7/RB5 15 46 SDA1/RG3 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 16 45 SCK1/INT0/RF6 AN3/CMP2B/AINDX1/CN5/RB3 17 44 SDI1/RF7 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 18 43 SDO1/RF8 PGEC3/AN1/CMP1B/CN3/RB1 19 42 U1RX/RF2 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 20 41 U1TX/RF3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1/AN6CMP3C/CMP4A/OCFA/RB6 PGED1/AN7/CMP4B/RB7 PWM8L/RA9 PWM8H/RA10 AVDD AVSS AN8/U2CTS/RB8 AN9/DACOUT/RB9 AN10/RB10 AN11/EXTREF/RB11 VSS VDD TCK/AN12/CMP1D/RB12 TDI/AN13/CMP2D/RB13 AN14/CMP3D/SS1/U2RTS/RB14 AN15/CMP4D/CN12/RB151CTS/FLT15/SYNCI3/CN20/RD14 /FLT16/SYNCI2/CN21/RD151RTS U2RX/FLT17/CN17/RF4 U2TX/FLT18/CN18/RF5 C U U E G P DS7000591F-page 10  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 100-Pin TQFP = Pins are up to 5V tolerant 7 D R 1 PWM3L/RE4PWM2H/RE3PWM2L/RE2PWM9H/RG13PWM9L/RG12SYNCO1/FLT23/RG14PWM1H/RE1PWM1L/FLT8/RE0AN23/CN23/RA7AN22/CN22/RA6INDX2/RG0QEB2/RG1C1TX/RF1C1RX/RF0VDDVCAPPWM5H/UPDN1/CN16/PWM5L/CN15/RD6PWM6H/CN14/RD5PWM6L/CN13/RD4PWM7L/CN19/RD13QEA2/RD12PWM7H/OC4/RD3OC3/FLT7/RD2OC2/SYNCO2/FLT6/RD 100999897969594939291908988878685848382818079787776 SYNCI1/RG15 1 75 Vss VDD 2 74 PGEC2/SOSCO/T1CK/CN0/RC14 PWM3H/RE5 3 73 PGED2/SOSCI/CN1/RC13 PWM4L/RE6 4 72 OC1/QEB1/FLT5/RD0 PWM4H/RE7 5 71 IC4/QEA1/FLT4/RD11 AN16/T2CK/RC1 6 70 IC3/INDX1/FLT3/RD10 AN17/T3CK/RC2 7 69 IC2/FLT2/RD9 AN18/T4CK/RC3 8 68 IC1/FLT1/RD8 AN19/T5CK/RC4 9 67 INT4/FLT19/SYNCI4/RA15 SCK2/FLT12/CN8/RG6 10 66 INT3/FLT20/RA14 SDI2/FLT11/CN9/RG7 11 65 VSS SDO2/FLT10/CN10/RG8 12 64 OSC2/REFCLKO/CLKO/RC15 dsPIC33FJ32GS610 MCLR 13 63 OSC1/CLKIN/RC12 SS2/FLT9/CN11/RG9 14 62 VDD VSS 15 61 TDO/RA5 VDD 16 60 TDI/RA4 TMS/RA0 17 59 SDA2/FLT21/RA3 AN20/FLT13/INT1/RE8 18 58 SCL2/FLT22/RA2 AN21/FLT14/INT2/RE9 19 57 SCL1/RG2 AN5/CMP3B/AQEB1/CN7/RB5 20 56 SDA1/RG3 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 21 55 SCK1/INT0/RF6 AN3/CMP2B/AINDX1/CN5/RB3 22 54 SDI1/RF7 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 23 53 SDO1/RF8 PGEC3/AN1/CMP1B/CN3/RB1 24 52 U1RX/RF2 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 25 51 U1TX/RF3 26272829303132333435363738394041424344454647484950 MP3C/CMP4A/OCFA/RB6PGED1/AN7/CMP4B/RB7PWM8L/RA9PWM8H/RA10AVDDAVSSAN8/RB8AN9/DACOUT/RB9AN10/RB10AN11/EXTREF/RB11VSSVDDTCK/RA1U2RTS/RF13U2CTS/RF12AN12/CMP1D/RB12AN13/CMP2D/RB13AN14/CMP3D/SS1/RB14AN15/CMP4D/CN12/RB15VSSVDDLT15/SYNCI3/CN20/RD14LT16/SYNCI2/CN21/RD15U2RX/FLT17/CN17/RF4U2TX/FLT18/CN18/RF5 C FF 6/ S/S/ N TT A CR C1/ U1U1 E G P  2009-2014 Microchip Technology Inc. DS7000591F-page 11

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Pin Diagrams (Continued) 100-Pin TQFP = Pins are up to 5V tolerant 7 D R 1 PWM3L/RE4PWM2H/RE3PWM2L/RE2PWM9H/RG13PWM9L/RG12SYNCO1/FLT23/RG14PWM1H/RE1PWM1L/FLT8/RE0AN23/CN23/RA7AN22/CN22/RA6INDX2/RG0QEB2/RG1C1TX/RF1C1RX/RF0VDDVCAPPWM5H/UPDN1/CN16/PWM5L/CN15/RD6PWM6H/CN14/RD5PWM6L/CN13/RD4PWM7L/CN19/RD13QEA2/RD12PWM7H/OC4/RD3OC3/FLT7/RD2OC2/SYNCO2/FLT6/RD 100999897969594939291908988878685848382818079787776 SYNCI1/RG15 1 75 Vss VDD 2 74 PGEC2/SOSCO/T1CK/CN0/RC14 PWM3H/RE5 3 73 PGED2/SOSCI/CN1/RC13 PWM4L/RE6 4 72 OC1/QEB1/FLT5/RD0 PWM4H/RE7 5 71 IC4/QEA1/FLT4/RD11 AN16/T2CK/RC1 6 70 IC3/INDX1/FLT3/RD10 AN17/T3CK/RC2 7 69 IC2/FLT2/RD9 AN18/T4CK/RC3 8 68 IC1/FLT1/RD8 AN19/T5CK/RC4 9 67 INT4/FLT19/SYNCI4/RA15 SCK2/FLT12/CN8/RG6 10 66 INT3/FLT20/RA14 SDI2/FLT11/CN9/RG7 11 65 VSS SDO2/FLT10/CN10/RG8 12 64 OSC2/REFCLKO/CLKO/RC15 MCLR 13 dsPIC33FJ64GS610 63 OSC1/CLKIN/RC12 SS2/FLT9/CN11/RG9 14 62 VDD VSS 15 61 TDO/RA5 VDD 16 60 TDI/RA4 TMS/RA0 17 59 SDA2/FLT21/RA3 AN20/FLT13/INT1/RE8 18 58 SCL2/FLT22/RA2 AN21/FLT14/INT2/RE9 19 57 SCL1/RG2 AN5/CMP3B/AQEB1/CN7/RB5 20 56 SDA1/RG3 AN4/CMP2C/CMP3A/AQEA1/CN6/RB4 21 55 SCK1/INT0/RF6 AN3/CMP2B/AINDX1/CN5/RB3 22 54 SDI1/RF7 AN2/CMP1C/CMP2A/ASS1/CN4/RB2 23 53 SDO1/RF8 PGEC3/AN1/CMP1B/CN3/RB1 24 52 U1RX/RF2 PGED3/AN0/CMP1A/CMP4C/CN2/RB0 25 51 U1TX/RF3 26272829303132333435363738394041424344454647484950 CMP3C/CMP4A/OCFA/RB6PGED1/AN7/CMP4B/RB7PWM8L/RA9PWM8H/RA10AVDDAVSSAN8/RB8AN9/DACOUT/RB9AN10/RB10AN11/EXTREF/RB11VSSVDDTCK/RA1U2RTS/RF13U2CTS/RF12AN12/CMP1D/RB12AN13/CMP2D/RB13/RB14AN14/CMP3D/SS1AN15/CMP4D/CN12/RB15VSSVDDFLT15/SYNCI3/CN20/RD14FLT16/SYNCI2/CN21/RD15U2RX/FLT17/CN17/RF4U2TX/FLT18/CN18/RF5 6/ S//S N TT A CR C1/ U1U1 E G P DS7000591F-page 12  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Table of Contents dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Product Families...............................................................2 1.0 Device Overview........................................................................................................................................................................17 2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers..........................................................................................23 3.0 CPU............................................................................................................................................................................................33 4.0 Memory Organization.................................................................................................................................................................45 5.0 Flash Program Memory............................................................................................................................................................109 6.0 Resets .....................................................................................................................................................................................115 7.0 Interrupt Controller...................................................................................................................................................................123 8.0 Direct Memory Access (DMA)..................................................................................................................................................179 9.0 Oscillator Configuration............................................................................................................................................................189 10.0 Power-Saving Features............................................................................................................................................................203 11.0 I/O Ports...................................................................................................................................................................................213 12.0 Timer1......................................................................................................................................................................................217 13.0 Timer2/3/4/5 features ..............................................................................................................................................................219 14.0 Input Capture............................................................................................................................................................................225 15.0 Output Compare.......................................................................................................................................................................227 16.0 High-Speed PWM.....................................................................................................................................................................231 17.0 Quadrature Encoder Interface (QEI) Module...........................................................................................................................261 18.0 Serial Peripheral Interface (SPI)...............................................................................................................................................265 19.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................271 20.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................279 21.0 Enhanced CAN (ECAN™) Module...........................................................................................................................................285 22.0 High-Speed, 10-Bit Analog-to-Digital Converter (ADC)............................................................................................................313 23.0 High-Speed Analog Comparator..............................................................................................................................................345 24.0 Special Features......................................................................................................................................................................349 25.0 Instruction Set Summary..........................................................................................................................................................357 26.0 Development Support...............................................................................................................................................................365 27.0 Electrical Characteristics..........................................................................................................................................................369 28.0 50 MIPS Electrical Characteristics...........................................................................................................................................417 29.0 DC and AC Device Characteristics Graphs..............................................................................................................................423 30.0 Packaging Information..............................................................................................................................................................427 Appendix A: Migrating from dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 to dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Devices...................................................................................................................441 Appendix B: Revision History.............................................................................................................................................................442 Index................................................................................................................................................................................................. 449 The Microchip Web Site.....................................................................................................................................................................457 Customer Change Notification Service..............................................................................................................................................457 Customer Support..............................................................................................................................................................................457 Product Identification System............................................................................................................................................................459  2009-2014 Microchip Technology Inc. DS7000591F-page 13

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS7000591F-page 14  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Referenced Sources This device data sheet is based on the following individ- ual chapters of the “dsPIC33/PIC24 Family Reference Manual”. These documents should be considered as the primary reference for the operation of a particular module or device feature. Note1: To access the documents listed below, browse to the documentation section of the dsPIC33FJ64GS610 product page of the Microchip web site (www.microchip.com) to select a family reference manual section from the following list. In addition to parameters, features and other documentation, the resulting page provides links to the related family reference manual sections. • “CPU” (DS70204) • “Data Memory” (DS70202) • “Program Memory” (DS70203) • “Flash Programming” (DS70191) • “Reset” (DS70192) • “Watchdog Timer (WDT) and Power-Saving Modes” (DS70196) • “I/O Ports” (DS70193) • “Timers” (DS70205) • “Input Capture” (DS70198) • “Output Compare” (DS70005157) • “Quadrature Encoder Interface (QEI)” (DS70208) • “Analog-to-Digital Converter (ADC)” (DS70183) • “UART” (DS70188) • “Serial Peripheral Interface (SPI)” (DS70206) • “Inter-Integrated Circuit™ (I2C™)” (DS70000195) • “ECAN™” (DS70185) • “Direct Memory Access (DMA)” (DS70182) • “CodeGuard™ Security” (DS70199) • “Programming and Diagnostics” (DS70207) • “Device Configuration” (DS70194) • “Development Tool Support” (DS70200) • “Oscillator (Part IV)” (DS70307) • “High-Speed PWM” (DS70000323) • “High-Speed 10-Bit ADC” (DS70000321) • “High-Speed Analog Comparator” (DS70296) • “Interrupts (Part V)” (DS70597)  2009-2014 Microchip Technology Inc. DS7000591F-page 15

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS7000591F-page 16  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 1.0 DEVICE OVERVIEW The dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices Note: This data sheet summarizes the features contain extensive Digital Signal Processor (DSP) func- of the dsPIC33FJ32GS406/606/608/610 tionality with a high-performance 16-bit microcontroller and dsPIC33FJ64GS406/606/608/610 (MCU) architecture. families of devices. It is not intended to be Figure1-1 shows a general block diagram of the core a comprehensive reference source. To and peripheral modules in the dsPIC33FJ32GS406/ complement the information in this data 606/608/610 and dsPIC33FJ64GS406/606/608/610 sheet, refer to the latest sections in the devices. Table1-1 lists the functions of the various pins “dsPIC33/PIC24 Family Reference shown in the pinout diagrams. Manual”, which are available from the Microchip web site (www.microchip.com). The information in this data sheet supersedes the information in the FRM. This document contains device-specific information for the following dsPIC33F Digital Signal Controller (DSC) devices: • dsPIC33FJ32GS406 • dsPIC33FJ32GS606 • dsPIC33FJ32GS608 • dsPIC33FJ32GS610 • dsPIC33FJ64GS406 • dsPIC33FJ64GS606 • dsPIC33FJ64GS608 • dsPIC33FJ64GS610  2009-2014 Microchip Technology Inc. DS7000591F-page 17

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 1-1: DEVICE BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus Interrupt X Data Bus PORTA Controller DMA 16 8 16 16 16 RAM Data Latch Data Latch 23 16 23 PCU PCH PCL X RAM Y RAM PORTB Program Counter Stack Loop Address Address DMA Control Control Latch Latch Controller Logic Logic 16 23 16 16 16 PORTC Address Generator Units Address Latch Program Memory EA MUX PORTD Data Latch ROM Latch 24 16 16 a Instruction Dat Decode and al Control Instruction Reg Liter 16 PORTE Control Signals to Various Blocks DSP Engine 16 x 16 Power-up W Register Array Timer Divide Support 16 PORTF OSC2/CLKO Timing Oscillator OSC1/CLKI Generation Start-up Timer Power-on FRC/LPRC Reset Oscillators 16-Bit ALU Watchdog Timer 16 PORTG Brown-out Voltage Reset Regulator VCAP VDD, VSS MCLR Ti1m-e5rs UART1/2 ECAN1 ADC1 OC1-4 P9W x M2 Analog IC1-4 QEI1,2 CNx I2C1/2 SPI1,2 Comparator 1-4 Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. DS7000591F-page 18  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name Description Type Type AN0-AN23 I Analog Analog input channels. CLKI I ST/CMOS External clock source input. Always associated with OSC1 pin function. CLKO O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. OSC1 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. OSC2 I/O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. SOSCI I ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. SOSCO O — 32.768 kHz low-power oscillator crystal output. CN0-CN23 I ST Change Notification inputs. Can be software programmed for internal weak pull-ups on all inputs. C1RX I ST ECAN1 bus receive pin. C1TX O — ECAN1 bus transmit pin. IC1-IC4 I ST Capture Inputs 1 through 4. INDX1, INDX2, AINDX1 I ST Quadrature Encoder Index Pulse input. QEA1, QEA2, AQEA1 I ST Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. QEB1, QEB2, AQEB1 I ST Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. UPDN1 O CMOS Position Up/Down Counter Direction State. OCFA I ST Compare Fault A input. OC1-OC4 O — Compare Outputs 1 through 4. INT0 I ST External Interrupt 0. INT1 I ST External Interrupt 1. INT2 I ST External Interrupt 2. INT3 I ST External Interrupt 3. INT4 I ST External Interrupt 4. RA0-RA15 I/O ST PORTA is a bidirectional I/O port. RB0-RB15 I/O ST PORTB is a bidirectional I/O port. RC0-RC15 I/O ST PORTC is a bidirectional I/O port. RD0-RD15 I/O ST PORTD is a bidirectional I/O port. RE0-RE9 I/O ST PORTE is a bidirectional I/O port. RF0-RF13 I/O ST PORTF is a bidirectional I/O port. RG0-RG15 I/O ST PORTG is a bidirectional I/O port. T1CK I ST Timer1 external clock input. T2CK I ST Timer2 external clock input. T3CK I ST Timer3 external clock input. T4CK I ST Timer4 external clock input. T5CK I ST Timer5 external clock input. Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input ST = Schmitt Trigger input with CMOS levels P = Power O = Output TTL = Transistor-Transistor Logic  2009-2014 Microchip Technology Inc. DS7000591F-page 19

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Description Type Type U1CTS I ST UART1 Clear-to-Send. U1RTS O — UART1 Request-to-Send. U1RX I ST UART1 receive. U1TX O — UART1 transmit. U2CTS I ST UART2 Clear-to-Send. U2RTS O — UART2 Request-to-Send. U2RX I ST UART2 receive. U2TX O — UART2 transmit. SCK1 I/O ST Synchronous serial clock input/output for SPI1. SDI1 I ST SPI1 data in. SDO1 O — SPI1 data out. SS1, ASS1 I/O ST SPI1 slave synchronization or frame pulse I/O. SCK2 I/O ST Synchronous serial clock input/output for SPI2. SDI2 I ST SPI2 data in. SDO2 O — SPI2 data out. SS2 I/O ST SPI2 slave synchronization or frame pulse I/O. SCL1 I/O ST Synchronous serial clock input/output for I2C1. SDA1 I/O ST Synchronous serial data input/output for I2C1. SCL2 I/O ST Synchronous serial clock input/output for I2C2. SDA2 I/O ST Synchronous serial data input/output for I2C2. TMS I TTL JTAG Test mode select pin. TCK I TTL JTAG test clock input pin. TDI I TTL JTAG test data input pin. TDO O — JTAG test data output pin. CMP1A I Analog Comparator 1 Channel A. CMP1B I Analog Comparator 1 Channel B. CMP1C I Analog Comparator 1 Channel C. CMP1D I Analog Comparator 1 Channel D. CMP2A I Analog Comparator 2 Channel A CMP2B I Analog Comparator 2 Channel B. CMP2C I Analog Comparator 2 Channel C. CMP2D I Analog Comparator 2 Channel D. CMP3A I Analog Comparator 3 Channel A. CMP3B I Analog Comparator 3 Channel B. CMP3C I Analog Comparator 3 Channel C. CMP3D I Analog Comparator 3 Channel D. CMP4A I Analog Comparator 4 Channel A. CMP4B I Analog Comparator 4 Channel B. CMP4C I Analog Comparator 4 Channel C. CMP4D I Analog Comparator 4 Channel D. DACOUT O — DAC output voltage. EXTREF I Analog External voltage reference input for the reference DACs. REFCLK O — REFCLK output signal is a postscaled derivative of the system clock. Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input ST = Schmitt Trigger input with CMOS levels P = Power O = Output TTL = Transistor-Transistor Logic DS7000591F-page 20  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Description Type Type FLT1-FLT23 I ST Fault inputs to PWM module. SYNCI1-SYNCI4 I ST External synchronization signal to PWM master time base. SYNCO1-SYNCO2 O — PWM master time base for external device synchronization. PWM1L O — PWM1 low output. PWM1H O — PWM1 high output. PWM2L O — PWM2 low output. PWM2H O — PWM2 high output. PWM3L O — PWM3 low output. PWM3H O — PWM3 high output. PWM4L O — PWM4 low output. PWM4H O — PWM4 high output. PWM5L O — PWM5 low output. PWM5H O — PWM5 high output. PWM6L O — PWM6 low output. PWM6H O — PWM6 high output. PWM7L O — PWM7 low output. PWM7H O — PWM7 high output. PWM8L O — PWM8 low output. PWM8H O — PWM8 high output. PWM9L O — PWM9 low output. PWM9H O — PWM9 high output. PGED1 I/O ST Data I/O pin for Programming/Debugging Communication Channel 1. PGEC1 I ST Clock input pin for Programming/Debugging Communication Channel 1. PGED2 I/O ST Data I/O pin for Programming/Debugging Communication Channel 2. PGEC2 I ST Clock input pin for Programming/Debugging Communication Channel 2. PGED3 I/O ST Data I/O pin for Programming/Debugging Communication Channel 3. PGEC3 I ST Clock input pin for Programming/Debugging Communication Channel 3. MCLR I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device. AVDD P P Positive supply for analog modules. AVSS P P Ground reference for analog modules. VDD P — Positive supply for peripheral logic and I/O pins. VCAP P — CPU logic filter capacitor connection. VSS P — Ground reference for logic and I/O pins. Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input ST = Schmitt Trigger input with CMOS levels P = Power O = Output TTL = Transistor-Transistor Logic  2009-2014 Microchip Technology Inc. DS7000591F-page 21

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS7000591F-page 22  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors STARTED WITH 16-BIT The use of decoupling capacitors on every pair of DIGITAL SIGNAL power supply pins, such as VDD, VSS, AVDD and CONTROLLERS AVSS, is required. Consider the following criteria when using decoupling Note1: This data sheet summarizes the features capacitors: of the dsPIC33FJ32GS406/606/608/610 • Value and type of capacitor: Recommendation of and dsPIC33FJ64GS406/606/608/610 0.1 µF (100 nF), 10-20V. This capacitor should be a family of devices. It is not intended to low-ESR and have resonance frequency in the be a comprehensive reference source. range of 20MHz and higher. It is recommended that To complement the information in ceramic capacitors be used. this data sheet, refer to the “dsPIC33/ PIC24 Family Reference Manual”. • Placement on the printed circuit board: The Please see the Microchip web site decoupling capacitors should be placed as close to (www.microchip.com) for the latest the pins as possible. It is recommended to place the dsPIC33/PIC24 Family Reference Man- capacitors on the same side of the board as the ual sections. The information in this device. If space is constricted, the capacitor can be data sheet supersedes the information placed on another layer on the PCB using a via; in the FRM. however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6mm) in 2: Some registers and associated bits length. described in this section may not be • Handling high-frequency noise: If the board is available on all devices. Refer to experiencing high-frequency noise, upward of tens Section4.0 “Memory Organization” in of MHz, add a second ceramic-type capacitor in par- this data sheet for device-specific register allel to the above described decoupling capacitor. and bit information. The value of the second capacitor can be in the range of 0.01µF to 0.001µF. Place this second 2.1 Basic Connection Requirements capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implement- Getting started with the dsPIC33FJ32GS406/606/ ing a decade pair of capacitances as close to the 608/610 and dsPIC33FJ64GS406/606/608/610 power and ground pins as possible. For example, family of 16-bit Digital Signal Controllers (DSC) 0.1 µF in parallel with 0.001 µF. requires attention to a minimal set of device pin connections before proceeding with development. • Maximizing performance: On the board layout The following is a list of pin names, which must from the power supply circuit, run the power and always be connected: return traces to the decoupling capacitors first, and then to the device pins. This ensures that the • All VDD and VSS pins decoupling capacitors are first in the power chain. (see Section2.2 “Decoupling Capacitors”) Equally important is to keep the trace length • All AVDD and AVSS pins (regardless if ADC module between the capacitor and the power pins to a is not used) minimum, thereby reducing PCB track inductance. (see Section2.2 “Decoupling Capacitors”) • VCAP (see Section2.3 “Capacitor on Internal Voltage Regulator (VCAP)”) • MCLR pin (see Section2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section2.6 “External Oscillator Pins”)  2009-2014 Microchip Technology Inc. DS7000591F-page 23

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 2-1: RECOMMENDED The placement of this capacitor should be close to the MINIMUM CONNECTION VCAP. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section24.2 0.1 µF “On-Chip Voltage Regulator” for details. 22 µF Ceramic VDD Tantalum 2.4 Master Clear (MCLR) Pin R AP DD SS C V V The MCLR pin provides for two specific device R1 V MCLR functions: • Device Reset C • Device programming and debugging dsPIC33F During device programming and debugging, the VSS VDD resistance and capacitance that can be added to the pin must be considered. Device programmers and 0.1 µF VDD D S VSS 0.1 µF debuggers drive the MCLR pin. Consequently, Ceramic VD VS DD SS Ceramic specific voltage levels (VIH and VIL) and fast signal A A V V transitions must not be adversely affected. Therefore, 0.1 µF 0.1 µF specific values of R and C will need to be adjusted Ceramic Ceramic based on the application and PCB requirements. L1(1) For example, as shown in Figure2-2, it is recommended that the capacitor C, be isolated from Note1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and the MCLR pin during programming and debugging AVDD to improve ADC noise rejection. The inductor operations. impedance should be less than 1 and the inductor capacity greater than 10 mA. Place the components shown in Figure2-2 within one-quarter inch (6mm) from the MCLR pin. Where: FCNV f = -------------- (i.e., ADC conversion rate/2) FIGURE 2-2: EXAMPLE OF MCLR PIN 2 CONNECTIONS(1,2) 1 f = ----------------------- 2 LC VDD  1 2 L = ----------------------   2f C R R1 MCLR 2.2.1 TANK CAPACITORS JP dsPIC33F On boards with power traces running longer than six C inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that con- Note 1: R 10k is recommended. A suggested nects the power supply source to the device and the starting value is 10k. Ensure that the maximum current drawn by the device in the applica- MCLR pin VIH and VIL specifications are met. tion. In other words, select the tank capacitor so that it 2: R1 470 will limit any current flowing into meets the acceptable voltage sag at the device. Typical MCLR from the external capacitor C, in the values range from 4.7µF to 47µF. event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin 2.3 Capacitor on Internal Voltage VIH and VIL specifications are met. Regulator (VCAP) A low-ESR (< 0.5 Ohms) capacitor is required on the VCAP pin, which is used to stabilize the voltage regulator output voltage. The VCAP pin must not be connected to VDD, and must have a minimum capacitor of 22 µF, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section27.0 “Electrical Characteristics” for additional information. DS7000591F-page 24  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 2.5 ICSP Pins 2.6 External Oscillator Pins The PGECx and PGEDx pins are used for In-Circuit Many DSCs have options for at least two oscillators: a Serial Programming™ (ICSP™) and debugging pur- high-frequency primary oscillator and a low-frequency poses. It is recommended to keep the trace length secondary oscillator (refer to Section9.0 “Oscillator between the ICSP connector and the ICSP pins on the Configuration” for details). device as short as possible. If the ICSP connector is The oscillator circuit should be placed on the same expected to experience an ESD event, a series resistor side of the board as the device. Also, place the is recommended, with the value in the range of a few oscillator circuit close to the respective oscillator pins, tens of Ohms, not to exceed 100 Ohms. not exceeding one-half inch (12mm) distance Pull-up resistors, series diodes, and capacitors on the between them. The load capacitors should be placed PGECx and PGEDx pins are not recommended as they next to the oscillator itself, on the same side of the will interfere with the programmer/debugger communi- board. Use a grounded copper pour around the cations to the device. If such discrete components are oscillator circuit to isolate them from surrounding an application requirement, they should be removed circuits. The grounded copper pour should be routed from the circuit during programming and debugging. directly to the MCU ground. Do not run any signal Alternatively, refer to the AC/DC characteristics and traces or power traces inside the ground pour. Also, if timing requirements information in the respective using a two-sided board, avoid any traces on the device Flash programming specification for information other side of the board where the crystal is placed. A on capacitive loading limits and pin input voltage high suggested layout is shown in Figure2-3. (VIH) and input low (VIL) requirements. FIGURE 2-3: SUGGESTED PLACEMENT Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device OF THE OSCILLATOR matches the physical connections for the ICSP to CIRCUIT MPLAB® ICD 3 or MPLAB REAL ICE™. For more information on ICD 3 and REAL ICE Main Oscillator connection requirements, refer to the following 13 documents that are available on the Microchip web Guard Ring 14 site. 15 • “Using MPLAB® ICD 3” (poster) (DS51765) Guard Trace • “MPLAB® ICD 3 Design Advisory” (DS51764) 16 • “MPLAB® REAL ICE™ In-Circuit Debugger Secondary 17 Oscillator User’s Guide” (DS51616) 18 • “Using MPLAB® REAL ICE™” (poster) (DS51749) 19 20  2009-2014 Microchip Technology Inc. DS7000591F-page 25

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 2.7 Oscillator Value Conditions on If your application needs to use certain Analog-to- Device Start-up Digital pins as analog input pins during the debug session, the user application must clear the If the PLL of the target device is enabled and corresponding bits in the ADPCFG and ADPCFG2 configured for the device start-up oscillator, the registers during initialization of the ADC module. maximum oscillator source frequency must be limited When MPLAB ICD 3 or REAL ICE is used as a to 4 MHz < FIN < 8 MHz to comply with device PLL programmer, the user application firmware must start-up conditions. This means that if the external correctly configure the ADPCFG and ADPCFG2 oscillator frequency is outside this range, the registers. Automatic initialization of these registers is application must start-up in the FRC mode first. The only done during debugger operation. Failure to default PLL settings after a POR with an oscillator correctly configure the register(s) will result in all frequency outside this range will violate the device Analog-to-Digital pins being recognized as analog input operating speed. pins, resulting in the port value being read as a logic ‘0’, Once the device powers up, the application firmware which may affect user application functionality. can initialize the PLL SFRs, CLKDIV and PLLDBF to a suitable value, and then perform a clock switch to the 2.9 Unused I/Os Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration Word. Unused I/O pins should be configured as outputs and driven to a logic low state. 2.8 Configuration of Analog and Alternatively, connect a 1k to 10k resistor between VSS Digital Pins During ICSP and unused pins and drive the output to logic low. Operations 2.10 Typical Application Connection If MPLAB ICD 3 or REAL ICE is selected as a Examples debugger, it automatically initializes all of the Analog- to-Digital input pins (ANx) as “digital” pins, by setting all Examples of typical application connections are shown bits in the ADPCFG and ADPCFG2 registers. in Figure2-4 through Figure2-11. The bits in the registers that correspond to the Analog-to- Digital pins that are initialized by MPLAB ICD 2, ICD 3, or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. DS7000591F-page 26  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 2-4: DIGITAL PFC IPFC VHV_BUS |VAC| k1 k3 VAC k FET 2 Driver ADC Channel ADC Channel PWM ADC Channel Output dsPIC33FJ32GS406 FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION IPFC VINPUT VOUTPUT k1 k3 k FET 2 Driver ADC Channel ADC PWM ADC Channel Channel Output dsPIC33FJ32GS406  2009-2014 Microchip Technology Inc. DS7000591F-page 27

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input 5V Output I 5V k7 DFrEivTer k1 k2 ADC M M Analog ADC Channel W W Comp. Channel P P dsPIC33FJ32GS606 FIGURE 2-7: MULTIPHASE SYNCHRONOUS BUCK CONVERTER 12V Input 3.3V Output k 6 k FET FET 7 Driver Driver ADC M M M M Channel W W W W PWM FET P P P P PWM Driver Analog Comparator k3 dsPIC33FJ32GS608 Analog Comparator k4 Analog Comparator k5 ADC Channel DS7000591F-page 28  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 2-8: OFF-LINE UPS VDC Push-Pull Converter Full-Bridge Inverter VOUT+ VBAT + VOUT- GND GND FET FET FET FET FET FET Driver Driver k2 k1 Driver Driver Driver Driver k4 k5 PWM PWM ADC ADC PWM PWM PWM PWM or Analog Comp. k3 ADC dsPIC33FJ64GS610 ADC ADC ADC PWM FET k Driver 6 + Battery Charger  2009-2014 Microchip Technology Inc. DS7000591F-page 29

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 2-9: INTERLEAVED PFC VOUT+ |VAC| k4 VAC k 3 k1 k2 VOUT- FET FET Driver Driver ADC Channel PWM ADC PWM ADC ADC Channel Channel Channel dsPIC33FJ32GS608 ADC Channel DS7000591F-page 30  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 2-10: PHASE-SHIFTED FULL-BRIDGE CONVERTER VIN+ Gate 6 Gate 3 Gate 1 VOUT+ S1 S3 VOUT- Gate 2 Gate 4 Gate 5 VIN- Gate 5 6 e at G FET k Driver 2 k 1 Analog Gate 1 Ground FET PWM ADC PWM ADC S1 Driver Channel Channel Gate 3 dsPIC33FJ32GS606 FET Driver S3 PWM Gate 2 Gate 4  2009-2014 Microchip Technology Inc. DS7000591F-page 31

D FIGURE 2-11: AC-TO-DC POWER SUPPLY WITH PFC AND THREE OUTPUTS (12V, 5V AND 3.3V) d S7 s 0 P 0 ZVT with Current Doubler Synchronous Rectifier 0 I 59 VHV_BUS Isolation VOUT C 1F Barrier 3 -pa IZVT 3F g e J 3 3 2 3.3V Multiphase Buck Stage 2 12V Input 3.3V Output G S I3.3V_1 4 0 FET 6 Driver DFrEivTer k4 DFrEivTer 5V Buck Stage 5V Output /606 I5V I3.3V_2 /6 0 M M M M ADC ADC W W W W Channel Channel 8 P P P P FET FET / Driver Driver 6 PWM 1 dPsrPimICa3r3yF CJo6n4GtroSl6le1r0 PWM k5 DFrEivTer k6 k7 I3.3V_3 k11 0 a n ADC ADC PWM ADC UART d Ch. Ch. Output Ch. RX ChAaDnCnel PWM PWM ACnoamlopg. ChAaDnCnel PWMPWM PWMPWM PPWWMM DFrEivTer ds P Analog Comparator k8 I C Secondary Controller dsPIC33FJ64GS610 Analog Comparator k9 33 PFC Stage k2 FET Driver UTAXRT Analog Comparator k10 FJ 6 ADC Channel 4 G  20 VAC S 0 4 9-20 k3 06 1 / 4 6 M 0 ic 6 roc /6 hip k1 0 T 8 ec |VAC| /6 h no VHV_BUS 1 log IPFC 0 y In c .

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 3.0 CPU As a result, three parameter instructions can be sup- ported, allowing A+B=C operations to be executed in a Note1: This data sheet summarizes the features single cycle. of the dsPIC33FJ32GS406/606/608/610 A block diagram of the CPU is shown in and dsPIC33FJ64GS406/606/608/610 Figure 3-1, and the programmer’s model for families of devices. It is not intended to be the dsPIC33FJ32GS406/606/608/610 and a comprehensive reference source. To dsPIC33FJ64GS406/606/608/610 is shown in complement the information in this data Figure 3-2. sheet, refer to “CPU” (DS70204) in the “dsPIC33/PIC24 Family Reference 3.1 Data Addressing Overview Manual”, which is available from the Microchip web site (www.microchip.com). The data space can be addressed as 32K words or The information in this data sheet 64Kbytes and is split into two blocks, referred to as X supersedes the information in the FRM. and Y data memory. Each memory block has its own 2: Some registers and associated bits independent Address Generation Unit (AGU). The described in this section may not be MCU class of instructions operates solely through available on all devices. Refer to theX memory AGU, which accesses the entire Section4.0 “Memory Organization” in memory map as one linear data space. Certain DSP this data sheet for device-specific register instructions operate through the X and Y AGUs to and bit information. support dual operand reads, which splits the data address space into two parts. The X and Y data space The dsPIC33FJ32GS406/606/608/610 and boundary is device-specific. dsPIC33FJ64GS406/606/608/610 CPU module has a Overhead-free circular buffers (Modulo Addressing 16-bit (data) modified Harvard architecture with an mode) are supported in both X and Y address spaces. enhanced instruction set, including significant support The Modulo Addressing removes the software for DSP. The CPU has a 24-bit instruction word with a boundary checking overhead for DSP algorithms. variable length opcode field. The Program Counter Furthermore, the X AGU circular addressing can be (PC) is 23bits wide and addresses up to 4M x 24 bits used with any of the MCU class of instructions. The X of user program memory space. The actual amount of AGU also supports Bit-Reversed Addressing to greatly program memory implemented varies from device to simplify input or output data reordering for radix-2 FFT device. A single-cycle instruction prefetch mechanism is algorithms. used to help maintain throughput and provides predictable execution. All instructions execute in a single The upper 32 Kbytes of the data space memory map cycle, with the exception of instructions that change the can optionally be mapped into program space at any program flow, the double-word move (MOV.D) instruction 16K program word boundary defined by the 8-bit and the table instructions. Overhead-free program loop Program Space Visibility Page (PSVPAG) register. The constructs are supported using the DO and REPEAT program-to-data space mapping feature lets any instructions, both of which are interruptible at any point. instruction access program space as if it were data space. The dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices have six- 3.2 DSP Engine Overview teen, 16-bit Working registers in the programmer’s model. Each of the Working registers can serve as a The DSP engine features a high-speed, 17-bit by 17-bit data, address or address offset register. The sixteenth multiplier, a 40-bit ALU, two 40-bit saturating Working register (W15) operates as a Software Stack accumulators and a 40-bit bidirectional barrel shifter. Pointer (SSP) for interrupts and calls. The barrel shifter is capable of shifting a 40-bit value up There are two classes of instruction in the to 16 bits, right or left, in a single cycle. The DSP dsPIC33FJ32GS406/606/608/610 and instructions operate seamlessly with all other dsPIC33FJ64GS406/606/608/610 devices: MCU and instructions and have been designed for optimal real- DSP. These two instruction classes are seamlessly time performance. The MAC instruction and other integrated into a single CPU. The instruction set includes associated instructions can concurrently fetch two data many addressing modes and is designed for optimum C operands from memory while multiplying two W compiler efficiency. For most instructions, the registers and accumulating and optionally saturating dsPIC33FJ32GS406/606/608/610 and the result in the same cycle. This instruction dsPIC33FJ64GS406/606/608/610 devices are capable functionality requires that the RAM data space be split of executing a data (or program data) memory read, a for these instructions and linear for all others. Data Working register (data) read, a data memory write and a space partitioning is achieved in a transparent and program (instruction) memory read per instruction cycle. flexible manner through dedicating certain Working registers to each address space.  2009-2014 Microchip Technology Inc. DS7000591F-page 33

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 3.3 Special MCU Features The dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 supports 16/16 and The dsPIC33FJ32GS406/606/608/610 and 32/16 divide operations, both fractional and integer. All dsPIC33FJ64GS406/606/608/610 features a 17-bit by divide instructions are iterative operations. They must 17-bit single-cycle multiplier that is shared by both the be executed within a REPEAT loop, resulting in a total MCU ALU and DSP engine. The multiplier can perform execution time of 19 instruction cycles. The divide signed, unsigned and mixed sign multiplication. Using operation can be interrupted during any of those a 17-bit by 17-bit multiplier for 16-bit by 16-bit 19cycles without loss of data. multiplication not only allows you to perform mixed sign A 40-bit barrel shifter is used to perform up to a 16-bit multiplication, it also achieves accurate results for left or right shift in a single cycle. The barrel shifter can special operations, such as (-1.0) x (-1.0). be used by both MCU and DSP instructions. FIGURE 3-1: dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus Interrupt X Data Bus Controller 8 16 16 16 16 Data Latch Data Latch 23 PCU PCH PCL X RAM Y RAM 16 23 Program Counter Stack Loop Address Address Control Control Latch Latch Logic Logic 23 16 16 Address Latch Address Generator Units Program Memory EA MUX Data Latch ROM Latch 24 16 16 a at Instruction D Decode and al Control Instruction Reg er Lit 16 Control Signals to Various Blocks DSP Engine 16 x 16 W Register Array Divide Support 16 16-Bit ALU 16 To Peripheral Modules DS7000591F-page 34  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 3-2: PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.SShadow W1 DOShadow W2 W3 Legend W4 DSP Operand W5 Registers W6 W7 Working Registers W8 DSP Address W9 Registers W10 W11 W12/DSP Offset W13/DSP Write-Back W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register AD39 AD31 AD15 AD0 ACCA DSP Accumulators ACCB PC22 PC0 0 Program Counter 7 0 TBLPAG Data Table Page Address 7 0 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address 22 DOEND DO Loop End Address 15 0 CORCON Core Configuration Register OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRH SRL  2009-2014 Microchip Technology Inc. DS7000591F-page 35

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 3.4 CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0 OA OB SA(1) SB(1) OAB SAB(1,4) DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OA: Accumulator A Overflow Status bit 1 = Accumulator A has overflowed 0 = Accumulator A has not overflowed bit 14 OB: Accumulator B Overflow Status bit 1 = Accumulator B has overflowed 0 = Accumulator B has not overflowed bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit 1 = Accumulator A or B has overflowed 0 = Neither Accumulator A or B has overflowed bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit(1,4) 1 = Accumulator A or B is saturated or has been saturated at some time in the past 0 = Neither Accumulator A or B is saturated bit 9 DA: DO Loop Active bit 1 = DO loop in progress 0 = DO loop not in progress bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred Note 1: This bit can be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). 4: Clearing this bit will clear SA and SB. DS7000591F-page 36  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop is in progress 0 = REPEAT loop is not in progress bit 3 N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 1 Z: MCU ALU Zero bit 1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: This bit can be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). 4: Clearing this bit will clear SA and SB.  2009-2014 Microchip Technology Inc. DS7000591F-page 37

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT(1) DL2 DL1 DL0 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 US: DSP Multiply Unsigned/Signed Control bit 1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed bit 11 EDT: Early DO Loop Termination Control bit(1) 1 = Terminates executing DO loop at the end of the current loop iteration 0 = No effect bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits 111 = 7 DO loops are active • • • 001 = 1 DO loop is active 000 = 0 DO loops are active bit 7 SATA: ACCA Saturation Enable bit 1 = Accumulator A saturation is enabled 0 = Accumulator A saturation is disabled bit 6 SATB: ACCB Saturation Enable bit 1 = Accumulator B saturation is enabled 0 = Accumulator B saturation is disabled bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation is enabled 0 = Data space write saturation is disabled bit 4 ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space is visible in data space 0 = Program space is not visible in data space bit 1 RND: Rounding Mode Select bit 1 = Biased (conventional) rounding is enabled 0 = Unbiased (convergent) rounding is enabled bit 0 IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode is enabled for DSP multiply operations 0 = Fractional mode is enabled for DSP multiply operations Note 1: This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS7000591F-page 38  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 3.5 Arithmetic Logic Unit (ALU) 3.6 DSP Engine The dsPIC33FJ32GS406/606/608/610 and The DSP engine consists of a high-speed, 17-bit x 17-bit dsPIC33FJ64GS406/606/608/610 ALU is 16 bits wide multiplier, a barrel shifter and a 40-bit adder/subtracter and is capable of addition, subtraction, bit shifts and logic (with two target accumulators, round and saturation logic). operations. Unless otherwise mentioned, arithmetic The dsPIC33FJ32GS406/606/608/610 and operations are 2’s complement in nature. Depending on dsPIC33FJ64GS406/606/608/610 is a single-cycle the operation, the ALU can affect the values of the Carry instruction flow architecture; therefore, concurrent (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry operation of the DSP engine with MCU instruction flow (DC) Status bits in the SR register. The C and DC Status is not possible. However, some MCU ALU and DSP bits operate as Borrow and Digit Borrow bits, respectively, engine resources can be used concurrently by the for subtraction operations. same instruction (for example, ED, EDAC). The ALU can perform 8-bit or 16-bit operations, The DSP engine can also perform inherent depending on the mode of the instruction that is used. accumulator-to-accumulator operations that require no Data for the ALU operation can come from the W additional data. These instructions are ADD, SUB and register array or data memory, depending on the NEG. addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array The DSP engine has options selected through bits in or a data memory location. the CPU Core Control register (CORCON), as listed below: Refer to the “16-bit MCU and DSC Programmer’s Ref- erence Manual” (DS70157) for information on the SR • Fractional or integer DSP multiply (IF) bits affected by each instruction. • Signed or unsigned DSP multiply (US) The dsPIC33FJ32GS406/606/608/610 and • Conventional or convergent rounding (RND) dsPIC33FJ64GS406/606/608/610 CPU incorporates • Automatic saturation on/off for ACCA (SATA) hardware support for both multiplication and division. This • Automatic saturation on/off for ACCB (SATB) includes a dedicated hardware multiplier and support • Automatic saturation on/off for writes to data hardware for 16-bit divisor division. memory (SATDW) 3.5.1 MULTIPLIER • Accumulator Saturation mode selection (ACCSAT) Using the high-speed, 17-bit x 17-bit multiplier of the DSP A block diagram of the DSP engine is shown in engine, the ALU supports unsigned, signed or mixed sign Figure3-3. operation in several MCU multiplication modes: • 16-bit x 16-bit signed TABLE 3-1: DSP INSTRUCTIONS • 16-bit x 16-bit unsigned SUMMARY • 16-bit signed x 5-bit (literal) unsigned • 16-bit unsigned x 16-bit unsigned Instruction Algebraic ACC Operation Write-Back • 16-bit unsigned x 5-bit (literal) unsigned • 16-bit unsigned x 16-bit signed CLR A = 0 Yes • 8-bit unsigned x 8-bit unsigned ED A = (x – y)2 No 3.5.2 DIVIDER EDAC A = A + (x – y)2 No MAC A = A + (x * y) Yes The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the MAC A = A + x2 No following data sizes: MOVSAC No change in A Yes • 32-bit signed/16-bit signed divide MPY A = x * y No • 32-bit unsigned/16-bit unsigned divide MPY A = x2 No • 16-bit signed/16-bit signed divide MPY.N A = – x * y No • 16-bit unsigned/16-bit unsigned divide MSC A = A – x * y Yes The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m+1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/ 16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.  2009-2014 Microchip Technology Inc. DS7000591F-page 39

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM S a 40 4400--BBiitt AAccccuummuullaattoorr AB 40 Round ut 16 Logic r a Carry/Borrow Out t Saturate e Carry/Borrow In Adder Negate 40 40 40 Barrel 16 Shifter 40 us B a Sign-Extend at D X s u B a 32 16 at Zero Backfill D Y 32 33 17-Bit Multiplier/Scaler 16 16 To/From W Array DS7000591F-page 40  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 3.6.1 MULTIPLIER 3.6.2.1 Adder/Subtracter, Overflow and Saturation The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a The adder/subtracter is a 40-bit adder with an optional scaler to support either 1.31 fractional (Q31) or 32-bit zero input into one side and either true or complement integer results. Unsigned operands are zero-extended data into the other input. into the 17th bit of the multiplier input value. Signed • In the case of addition, the Carry/Borrow input is operands are sign-extended into the 17th bit of the active-high and the other input is true data (not multiplier input value. The output of the 17-bit x 17-bit complemented). multiplier/scaler is a 33-bit value that is sign-extended • In the case of subtraction, the Carry/Borrow input to 40 bits. Integer data is inherently represented as a is active-low and the other input is complemented. signed 2’s complement value, where the Most Significant bit (MSb) is defined as a sign bit. The range The adder/subtracter generates Overflow Status bits, of an N-bit 2’s complement integer is -2N-1 to 2N-1 – 1. SA/SB and OA/OB, which are latched and reflected in the STATUS Register (SR): • For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including 0. • Overflow from bit 39: this is a catastrophic • For a 32-bit integer, the data range is overflow in which the sign of the accumulator is -2,147,483,648 (0x80000000) to 2,147,483,647 destroyed. (0x7FFF FFFF). • Overflow into guard bits, 32 through 39: this is a recoverable overflow. This bit is set whenever all When the multiplier is configured for fractional the guard bits are not identical to each other. multiplication, the data is represented as a 2’s complement fraction, where the MSb is defined as a The adder has an additional saturation block that sign bit and the radix point is implied to lie just after the controls accumulator data saturation, if selected. It sign bit (QX format). The range of an N-bit 2’s uses the result of the adder, the Overflow Status bits complement fraction with this implied radix point is -1.0 described previously and the SAT<A:B> to (1 – 21-N). For a 16-bit fraction, the Q15 data range (CORCON<7:6>) and ACCSAT (CORCON<4>) mode is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0 control bits to determine when and to what value to and has a precision of 3.01518x10-5. In Fractional saturate. mode, the 16 x 16 multiply operation generates a Six STATUS Register bits support saturation and 1.31product that has a precision of 4.65661 x 10-10. overflow: The same multiplier is used to support the MCU • OA: ACCA overflowed into guard bits multiply instructions, which include integer 16-bit • OB: ACCB overflowed into guard bits signed, unsigned and mixed sign multiply operations. • SA: ACCA saturated (bit 31 overflow and The MUL instruction can be directed to use byte or saturation) word-sized operands. Byte operands will direct a 16-bit or result and word operands will direct a 32-bit result to ACCA overflowed into guard bits and saturated the specified register(s) in the W array. (bit 39 overflow and saturation) 3.6.2 DATA ACCUMULATORS AND • SB: ACCB saturated (bit 31 overflow and saturation) ADDER/SUBTRACTER or The data accumulator consists of a 40-bit adder/ ACCB overflowed into guard bits and saturated subtracter with automatic sign extension logic. It can (bit 39 overflow and saturation) select one of two accumulators (A or B) as its pre- • OAB: Logical OR of OA and OB accumulation source and post-accumulation • SAB: Logical OR of SA and SB destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled The OA and OB bits are modified each time data using the barrel shifter prior to accumulation. passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits(bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the correspond- ing Overflow Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1 register are set (refer to Section7.0 “Interrupt Controller”). This allows the user applica- tion to take immediate action, for example, to correct system gain.  2009-2014 Microchip Technology Inc. DS7000591F-page 41

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 The SA and SB bits are modified each time data 3.6.3 ACCUMULATOR ‘WRITE-BACK’ passes through the adder/subtracter, but can only be The MAC class of instructions (with the exception of cleared by the user application. When set, they indicate MPY, MPY.N, ED and EDAC) can optionally write a that the accumulator has overflowed its maximum rounded version of the high word (bits 31 through 16) range (bit 31 for 32-bit saturation or bit 39 for 40-bit of the accumulator that is not targeted by the instruction saturation) and will be saturated (if saturation is into data space memory. The write is performed across enabled). When saturation is not enabled, SA and SB the X bus into combined X and Y address space. The default to bit 39 overflow and thus, indicate that a cata- following addressing modes are supported: strophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate • W13, Register Direct: an arithmetic warning trap when saturation is disabled. The rounded contents of the non-target accumulator are written into W13 as a 1.15fraction. The Overflow and Saturation Status bits can optionally be • [W13] + = 2, Register Indirect with Post-Increment: viewed in the STATUS Register (SR) as the logical OR of The rounded contents of the non-target OA and OB (in bit OAB) and the logical OR of SA and SB accumulator are written into the address pointed (in bit SAB). Programmers can check one bit in the to by W13 as a 1.15 fraction. W13 is then STATUS Register to determine if either accumulator has overflowed, or one bit to determine if either accumulator incremented by 2 (for a word write). has saturated. This is useful for complex number 3.6.3.1 Round Logic arithmetic, which typically uses both accumulators. The round logic is a combinational block that performs The device supports three Saturation and Overflow a conventional (biased) or convergent (unbiased) modes: round function during an accumulator write (store). The • Bit 39 Overflow and Saturation: Round mode is determined by the state of the RND bit When bit 39 overflow and saturation occurs, the in the CORCON register. It generates a 16-bit, saturation logic loads the maximally positive 1.15data value that is passed to the data space write 9.31 (0x7FFFFFFFFF) or maximally negative saturation logic. If rounding is not indicated by the 9.31 value (0x8000000000) into the target accu- instruction, a truncated 1.15 data value is stored and mulator. The SA or SB bit is set and remains set the least significant word is simply discarded. until cleared by the user application. This condition is referred to as ‘super saturation’ and Conventional rounding zero-extends bit 15 of the accu- provides protection against erroneous data or mulator and adds it to the ACCxH word (bits 16 through unexpected algorithm problems (such as 31 of the accumulator). gain calculations). • If the ACCxL word (bits0 through 15 of the • Bit 31 Overflow and Saturation: accumulator) is between 0x8000 and 0xFFFF When bit 31 overflow and saturation occurs, the (0x8000 included), ACCxH is incremented. saturation logic then loads the maximally positive • If ACCxL is between 0x0000 and 0x7FFF, ACCxH 1.31 value (0x007FFFFFFF) or maximally nega- is left unchanged. tive 1.31 value (0x0080000000) into the target A consequence of this algorithm is that over a accumulator. The SA or SB bit is set and remains succession of random rounding operations, the value set until cleared by the user application. When tends to be biased slightly positive. this Saturation mode is in effect, the guard bits are not used, so the OA, OB or OAB bits are Convergent (or unbiased) rounding operates in the same never set. manner as conventional rounding, except when ACCxL • Bit 39 Catastrophic Overflow: equals 0x8000. In this case, the Least Significant bit The bit 39 Overflow Status bit from the adder is (bit16 of the accumulator) of ACCxH is examined: used to set the SA or SB bit, which remains set • If it is ‘1’, ACCxH is incremented. until cleared by the user application. No saturation • If it is ‘0’, ACCxH is not modified. operation is performed, and the accumulator is allowed to overflow, destroying its sign. If the Assuming that bit 16 is effectively random in nature, this COVTE bit in the INTCON1 register is set, a scheme removes any rounding bias that may accumulate. catastrophic overflow can initiate a trap exception. The SAC and SAC.R instructions store either a truncated (SAC), or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus, subject to data saturation (see Section3.6.3.2 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. DS7000591F-page 42  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 3.6.3.2 Data Space Write Saturation 3.6.4 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data The barrel shifter can perform up to 16-bit arithmetic or space can also be saturated, but without affecting the logic right shifts, or up to 16-bit left shifts in a single contents of the source accumulator. The data space cycle. The source can be either of the two DSP write saturation logic block accepts a 16-bit, 1.15 accumulators or the X bus (to support multi-bit shifts of fractional value from the round logic block as its input, register or memory data). together with overflow status from the original source The shifter requires a signed binary value to determine (accumulator) and the 16-bit round adder. These inputs both the magnitude (number of bits) and direction of the are combined and used to select the appropriate shift operation. A positive value shifts the operand right. 1.15fractional value as output to write to data space A negative value shifts the operand left. A value of ‘0’ memory. does not modify the operand. If the SATDW bit in the CORCON register is set, data The barrel shifter is 40 bits wide, thereby obtaining a (after rounding or truncation) is tested for overflow and 40-bit result for DSP shift operations and a 16-bit result adjusted accordingly: for MCU shift operations. Data from the X bus is • For input data greater than 0x007FFF, data presented to the barrel shifter between bit positions 16 written to memory is forced to the maximum and 31 for right shifts, and between bit positions 0 and positive 1.15 value, 0x7FFF. 16 for left shifts. • For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions.  2009-2014 Microchip Technology Inc. DS7000591F-page 43

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS7000591F-page 44  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.0 MEMORY ORGANIZATION 4.1 Program Address Space The program address memory space is 4M instruc- Note: This data sheet summarizes the features tions. The space is addressable by a 24-bit value of the dsPIC33FJ32GS406/606/608/610 derived either from the 23-bit Program Counter (PC) and dsPIC33FJ64GS406/606/608/610 during program execution, or from table operation or families of devices. It is not intended to be data space remapping as described in Section4.6 a comprehensive reference source. To “Interfacing Program and Data Memory Spaces”. complement the information in this data sheet, refer to the dsPIC33/PIC24 Family User application access to the program memory space Reference Manual, Program Memory” is restricted to the lower half of the address range (DS70203), which is available from the (0x000000 to 0x7FFFFF). The exception is the use of Microchip web site (www.microchip.com). TBLRD/TBLWT operations, which use TBLPAG<7> to The information in this data sheet permit access to the Configuration bits and Device ID supersedes the information in the FRM. sections of the configuration memory space. The memory maps are shown in Figure4-1. The dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 architecture features separate program and data memory spaces and buses. This architecture also allows the direct access to program memory from the data space during code execution. FIGURE 4-1: PROGRAM MEMORY MAPS FOR dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 DEVICES dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 GOTO Instruction 0x000000 GOTO Instruction 0x000000 0x000002 0x000002 Reset Address Reset Address 0x000004 0x000004 Interrupt Vector Table Interrupt Vector Table 0x0000FE 0x0000FE Reserved 0x000100 Reserved 0x000100 0x000104 0x000104 e Alternate Vector Table e Alternate Vector Table c 0x0001FE c 0x0001FE a a p 0x000200 p 0x000200 S S y User Program y User Program or Flash Memory or Flash Memory m (11008 instructions) m (21760 instructions) e 0x0057FE e 0x00ABFE M M er 0x005800 er 0x00AC00 s s U U Unimplemented Unimplemented (Read ‘0’s) (Read ‘0’s) 0x7FFFFE 0x7FFFFE 0x800000 0x800000 Reserved Reserved e e c c a a p p S 0xF7FFFE S 0xF7FFFE ory Device Configuration 0xF80000 ory Device Configuration 0xF80000 m Registers 0xF80017 m Registers 0xF80017 Me 0xF80018 Me 0xF80018 n n o o ati ati gur Reserved gur Reserved nfi nfi o o C C 0xFEFFFE 0xFEFFFE DEVID (2) 0xFF0000 DEVID (2) 0xFF0000 0xFF0002 0xFF0002 Reserved 0xFFFFFE Reserved 0xFFFFFE  2009-2014 Microchip Technology Inc. DS7000591F-page 45

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.1.1 PROGRAM MEMORY 4.1.2 INTERRUPT AND TRAP VECTORS ORGANIZATION All dsPIC33FJ32GS406/606/608/610 and The program memory space is organized in word- dsPIC33FJ64GS406/606/608/610 devices reserve the addressable blocks. Although it is treated as 24bits addresses between 0x00000 and 0x000200 for hard- wide, it is more appropriate to think of each address of coded program execution vectors. A hardware Reset the program memory as a lower and upper word, with vector is provided to redirect code execution from the the upper byte of the upper word being unimplemented. default value of the PC on device Reset to the actual The lower word always has an even address, while the start of code. A GOTO instruction is programmed by the upper word has an odd address (see Figure4-2). user application at 0x000000, with the actual address for the start of code at 0x000002. Program memory addresses are always word-aligned on the lower word and addresses are incremented or The dsPIC33FJ32GS406/606/608/610 and decremented by two during the code execution. This dsPIC33FJ64GS406/606/608/610 devices also have arrangement provides compatibility with data memory two Interrupt Vector Tables (IVT), located from space addressing and makes data in the program 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. memory space accessible. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the Interrupt Vector Tables is provided in Section7.1 “Interrupt Vector Table”. FIGURE 4-2: PROGRAM MEMORY ORGANIZATION msw most significant word least significant word PC Address Address (lsw Address) 23 16 8 0 0x000001 00000000 0x000000 0x000003 00000000 0x000002 0x000005 00000000 0x000004 0x000007 00000000 0x000006 Program Memory Instruction Width ‘Phantom’ Byte (read as ‘0’) DS7000591F-page 46  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.2 Data Address Space All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so The CPU has a separate 16-bit-wide data memory space. care must be taken when mixing byte and word The data space is accessed using separate Address operations, or translating from 8-bit MCU code. If a Generation Units (AGUs) for read and write operations. misaligned read or write is attempted, an address error The data memory maps is shown in Figure4-3. trap is generated. If the error occurred on a read, the All Effective Addresses (EAs) in the data memory space instruction underway is completed. If the error occurred are 16 bits wide and point to bytes within the data space. on a write, the instruction is executed but the write does This arrangement gives a data space address range of not occur. In either case, a trap is then executed, 64Kbytes or 32Kwords. The lower half of the data allowing the system and/or user application to examine memory space (that is, when EA<15> = 0) is used for the machine state prior to execution of the address implemented memory addresses, while the upper half Fault. (EA<15> = 1) is reserved for the Program Space All byte loads into any W register are loaded into the Visibility area (see Section4.6.3 “Reading Data from Least Significant Byte. The Most Significant Byte is not Program Memory Using Program Space Visibility”). modified. The dsPIC33FJ32GS406/606/608/610 and A Sign-Extend (SE) instruction is provided to allow user dsPIC33FJ64GS406/606/608/610 devices implement applications to translate 8-bit signed data to 16-bit up to 9Kbytes of data memory. Should an EA point to signed values. Alternatively, for 16-bit unsigned data, a location outside of this area, an all-zero word or byte user applications can clear the MSB of any W register will be returned. by executing a Zero-Extend (ZE) instruction on the appropriate address. 4.2.1 DATA SPACE WIDTH The data memory space is organized in byte 4.2.3 SFR SPACE addressable, 16-bit wide blocks. Data is aligned in data The first 2 Kbytes of the Near Data Space, from 0x0000 memory and registers as 16-bit words, but all data to 0x07FF, is primarily occupied by Special Function space EAs resolve to bytes. The Least Significant Registers (SFRs). These are used by the core and Bytes (LSBs) of each word have even addresses, while peripheral modules for controlling the operation of the the Most Significant Bytes (MSBs) have odd device. addresses. SFRs are distributed among the modules that they 4.2.2 DATA MEMORY ORGANIZATION control and are generally grouped together by module. AND ALIGNMENT Much of the SFR space contains unused addresses; these are read as ‘0’. To maintain backward compatibility with PIC® MCU devices and improve data space memory usage Note: The actual set of peripheral features and efficiency, the instruction set supports both word and interrupts varies by the device. Refer to the byte operations. As a consequence of byte accessibil- corresponding device tables and pinout ity, all Effective Address calculations are internally diagrams for device-specific information. scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified 4.2.4 NEAR DATA SPACE Register Indirect Addressing mode [Ws++] that results The 8-Kbyte area between 0x0000 and 0x1FFF is in a value of Ws + 1 for byte operations and Ws + 2 for referred to as the Near Data Space. Locations in this word operations. space are directly addressable via a 13-bit absolute Data byte reads will read the complete word that address field within all memory direct instructions. contains the byte, using the LSB of any EA to Additionally, the whole data space is addressable using determine which byte to select. The selected byte is MOV instructions, which support Memory Direct placed onto the LSB of the data path. That is, data Addressing mode with a 16-bit address field, or by memory and registers are organized as two parallel using Indirect Addressing mode using a Working byte-wide entities with shared (word) address decode register as an Address Pointer. but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address.  2009-2014 Microchip Technology Inc. DS7000591F-page 47

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 4-3: DATA MEMORY MAP FOR DEVICES WITH 4-KBYTE RAM MSB LSB Address 16 Bits Address MSb LSb 0x0001 0x0000 2-Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 6-Kbyte X Data RAM (X) Near Data 0x0FFF 0x0FFE Space 0x1001 0x1000 Y Data RAM (Y) 0x17FF 0x17FE 0x1801 0x1800 0x8001 0x8000 X Data Optionally Unimplemented (X) Mapped into Program Memory 0xFFFF 0xFFFE DS7000591F-page 48  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 4-4: DATA MEMORY MAP FOR DEVICES WITH 8-KBYTE RAM MSB LSB Address 16 Bits Address MSb LSb 0x0001 0x0000 2-Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 8-Kbyte X Data RAM (X) Near Data 0x17FF 0x17FE Space 0x1801 0x1800 Y Data RAM (Y) 0x1FFF 0x1FFE 0x2001 0x2000 0x27FF 0x27FE 0x2801 0x2800 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE  2009-2014 Microchip Technology Inc. DS7000591F-page 49

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 4-5: DATA MEMORY MAP FOR DEVICES WITH 9-KBYTE RAM MSB LSB Address 16 Bits Address MSb LSb 0x0001 0x0000 2-Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 8-Kbyte X Data RAM (X) Near Data 0x17FF 0x17FE Space 0x1801 0x1800 Y Data RAM (Y) 0x1FFF 0x1FFE 0x2001 0x2000 0x27FF 0x27FE 0x2801 0x2800 DMA RAM 0x2BFF 0x2BFE 0x2C01 0x2C00 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE DS7000591F-page 50  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.2.5 X AND Y DATA SPACES All data memory writes, including in DSP instructions, view data space as combined X and Y address space. The core has two data spaces, X and Y. These data The boundary between the X and Y data spaces is spaces can beconsidered either separate (for some device-dependent and is not user-programmable. DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are All Effective Addresses (EAs) are 16 bits wide and point accessed using two Address Generation Units (AGUs) to bytes within the data space. Therefore, the data and separate data paths. This feature allows certain space address range is 64 Kbytes, or 32K words, instructions to concurrently fetch two words from RAM, though the implemented memory locations vary by thereby enabling efficient execution of DSP algorithms device. such as Finite Impulse Response (FIR) filtering and 4.2.6 DMA RAM Fast Fourier Transform (FFT). The X data space is used by all instructions and Some devices contain 1Kbyte of dual ported DMA supports all addressing modes. X data space has RAM, which is located at the end of Y data space. separate read and write data buses. The X read data Memory locations that are part of Y data RAM and are in bus is the read data path for all instructions that view the DMA RAM space are accessible simultaneously by data space as combined X and Y address space. It is the CPU and the DMA Controller module. DMA RAM is also the X data prefetch path for the dual operand DSP utilized by the DMA Controller to store data to be instructions (MAC class). transferred to various peripherals using DMA, as well as data transferred from various peripherals using DMA. The Y data space is used in concert with the X data The DMA RAM can be accessed by the DMA Controller space by the MAC class of instructions (CLR, ED, EDAC, without having to steal cycles from the CPU. MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths. When the CPU and the DMA Controller attempt to concurrently write to the same DMA RAM location, the Both the X and Y data spaces support Modulo hardware ensures that the CPU is given precedence in Addressing mode for all instructions, subject to accessing the DMA RAM location. Therefore, the DMA addressing mode restrictions. Bit-Reversed Addressing RAM provides a reliable means of transferring DMA mode is only supported for writes to X data space. data without ever having to stall the CPU.  2009-2014 Microchip Technology Inc. DS7000591F-page 51

D TABLE 4-1: CPU CORE REGISTER MAP d S7 s 0005 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 9 1F WREG0 0000 Working Register 0 0000 3 -p 3 a WREG1 0002 Working Register 1 0000 F g e 5 WREG2 0004 Working Register 2 0000 J3 2 WREG3 0006 Working Register 3 0000 2 G WREG4 0008 Working Register 4 0000 S WREG5 000A Working Register 5 0000 4 WREG6 000C Working Register 6 0000 0 6 WREG7 000E Working Register 7 0000 / 6 WREG8 0010 Working Register 8 0000 0 6 WREG9 0012 Working Register 9 0000 / 6 WREG10 0014 Working Register 10 0000 0 WREG11 0016 Working Register 11 0000 8 / WREG12 0018 Working Register 12 0000 6 1 WREG13 001A Working Register 13 0000 0 WREG14 001C Working Register 14 0000 a n WREG15 001E Working Register 15 0800 d SPLIM 0020 Stack Pointer Limit Register xxxx d ACCAL 0022 ACCAL xxxx s P ACCAH 0024 ACCAH xxxx I ACCAU 0026 ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCAU xxxx C 3 ACCBL 0028 ACCBL xxxx 3 ACCBH 002A ACCBH xxxx F J ACCBU 002C ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCBU xxxx 6 PCL 002E Program Counter Low Byte Register 0000 4 G  2 PCH 0030 — — — — — — — — Program Counter High Byte Register 0000 S 00 TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register 0000 4 9-20 PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register 0000 06 14 RCOUNT 0036 REPEAT Loop Counter Register xxxx /6 M DCOUNT 0038 DCOUNT<15:0> xxxx 0 ic 6 roc DOSTARTL 003A DOSTARTL<15:1> 0 xxxx /6 hip DOSTARTH 003C — — — — — — — — — — DOSTARTH<5:0> 00xx 0 Tec DOENDL 003E DOENDL<15:1> 0 xxxx 8/6 h DOENDH 0040 — — — — — — — — — — DOENDH 00xx n 1 o lo SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0 g y Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. In c .

 TABLE 4-1: CPU CORE REGISTER MAP (CONTINUED) 2 0 0 File SFR All 9-20 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets ds 14 CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 P M I ic MODCON 0046 XMODEN YMODEN — — BWM3 BWM2 BWM1 BWM0 YWM3 YWM2 YWM1 YWM0 XWM3 XWM2 XWM1 XWM0 0000 C roch XMODSRT 0048 XS<15:1> 0 xxxx 33 ip XMODEND 004A XE<15:1> 1 xxxx F T J ec YMODSRT 004C YS<15:1> 0 xxxx 3 hn YMODEND 004E YE<15:1> 1 xxxx 2 o G lo XBREV 0050 BREN XB14 XB13 XB12 XB11 XB10 XB9 XB8 XB7 XB6 XB5 XB4 XB3 XB2 XB1 XB0 xxxx g S y In DISICNT 0052 — — Disable Interrupts Counter Register xxxx 4 c. Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 6 / 6 0 6 / 6 0 8 / 6 1 0 a n d d s P I C 3 3 F J 6 4 G S 4 0 6 D / S 6 7 0 0 0 6 05 /6 9 1 0 F -p 8 ag /6 e 1 5 0 3

D TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES d S7 s 0005 NFailme e ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 9 1F CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 3 -p 3 a CNEN2 0062 — — — — — — — — CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 F g e 5 CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 J3 4 CNPU2 006A — — — — — — — — CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 2 G Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. S 4 0 TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES 6 / 6 File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Name Addr Resets 6 / CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 6 0 CNEN2 0062 — — — — — — — — CN23IE CN22IE — — — CN18IE CN17IE CN16IE 0000 8 CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 /6 CNPU2 006A — — — — — — — — CN23PUE CN22PUE — — — CN18PUE CN17PUE CN16PUE 0000 1 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. a n d d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 2 TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES 0 0 9-20 NFailme e ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 P M INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 I C icro INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 3 ch IFS0 0084 — DMA1IF ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 3 ip F T IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000 J ec IFS2 0088 — — — — — — — — — IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000 3 hn 2 o IFS3 008A — — — — — QEI1IF PSEMIF — — INT4IF INT3IF — — MI2C2IF SI2C2IF — 0000 G lo g IFS4 008C — — — — QEI2IF — PSESMIF — — C1TXIF — — — U2EIF U1EIF — 0000 S y In IFS5 008E PWM2IF PWM1IF ADCP12IF — — — — — — — — ADCP11IF ADCP10IF ADCP9IF ADCP8IF — 0000 4 c 0 . IFS6 0090 ADCP1IF ADCP0IF — — — — AC4IF AC3IF AC2IF PWM9IF PWM8IF PWM7IF PWM6IF PWM5IF PWM4IF PWM3IF 0000 6 / IFS7 0092 — — — — — — — — — — ADCP7IF ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF 0000 6 0 IEC0 0094 — DMA1IE ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 6 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE 0000 /6 IEC2 0098 — — — — — — — — — IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000 0 8 IEC3 009A — — — — — QEI1IE PSEMIE — — INT4IE INT3IE — — MI2C2IE SI2C2IE — 0000 / 6 IEC4 009C — — — — QEI2IE — PSESMIE — — C1TXIE — — — U2EIE U1EIE — 0000 1 0 IEC5 009E PWM2IE PWM1IE ADCP12IE — — — — — — — — ADCP11IE ADCP10IE ADCP9IE ADCP8IE — 0000 a IEC6 00A0 ADCP1IE ADCP0IE — — — — AC4IE AC3IE AC2IE PWM9IE PWM8IE PWM7IE PWM6IE PWM5IE PWM4IE PWM3IE 0000 n IEC7 00A2 — — — — — — — — — — ADCP7IE ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE 0000 d IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444 d s IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — DMA0IP2 DMA0IP1 DMA0IP0 4444 P IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 0444 IC IPC3 00AA — — — — — DMA1IP2 DMA1IP1 DMA1IP0 — ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044 3 3 IPC4 00AC — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444 F IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 J 6 IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — DMA2IP2 DMA2IP1 DMA2IP0 4444 4 IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444 G IPC8 00B4 — C1IP2 C1IP1 C1IP0 — C1RXIP2 C1RXIP1 C1RXIP0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPI2EIP2 SPI2EIP1 SPI2EIP0 4444 S 4 IPC9 00B6 — — — — — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — DMA3IP2 DMA3IP1 DMA3IP0 0444 0 IPC12 00BC — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440 6 D / S IPC13 00BE — — — — — INT4IP2 INT4IP1 INT4IP0 — INT3IP2 INT3IP1 INT3IP0 — — — — 0440 6 7 0 00 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 05 /6 9 1 0 F -p 8 ag /6 e 1 5 0 5

D TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES (CONTINUED) d S7 s 0 File SFR All P 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Name Addr Resets I 5 C 9 1F IPC14 00C0 — — — — — QEI1IP2 QEI1IP1 QEI1IP0 — PSEMIP2 PSEMIP1 PSEMIP0 — — — — 0440 3 -pa IPC16 00C4 — — — — — U2EIP2 U2EIP1 U2EIP0 — U1EIP2 U1EIP1 U1EIP0 — — — — 0440 3F g e IPC17 00C6 — — — — — C1TXIP2 C1TXIP1 C1TXIP0 — — — — — — — — 0400 J 5 3 6 IPC18 00C8 — QEI2IP2 QEI2IP1 QEI2IP0 — — — — — PSESMIP2 PSESMIP1 PSESMIP0 — — — — 4040 2 IPC20 00CC — ADCP10IP2ADCP10IP1ADCP10IP0 — ADCP9IP2 ADCP9IP1 ADCP9IP0 — ADCP8IP2 ADCP8IP1 ADCP8IP0 — — — — 4440 G S IPC21 00CE — — — — — — — — — ADCP12IP2 ADCP12IP1 ADCP12IP0 — ADCP11IP2 ADCP11IP1 ADCP11IP0 0044 4 IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — — 4400 0 6 IPC24 00D4 — PWM6IP2 PWM6IP1 PWM6IP0 — PWM5IP2 PWM5IP1 PWM5IP0 — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0 4444 / 6 IPC25 00D6 — AC2IP2 AC2IP1 AC2IP0 — PWM9IP2 PWM9IP1 PWM9IP0 — PWM8IP2 PWM8IP1 PWM8IP0 — PWM7IP2 PWM7IP1 PWM7IP0 4444 0 IPC26 00D8 — — — — — — — — — AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0 0044 6 / IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — — 4400 6 0 IPC28 00DC — ADCP5IP2 ADCP5IP1 ADCP5IP0 — ADCP4IP2 ADCP4IP1 ADCP4IP0 — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1 ADCP2IP0 4444 8 / IPC29 00DE — — — — — — — — — ADCP7IP2 ADCP7IP1 ADCP7IP0 — ADCP6IP2 ADCP6IP1 ADCP6IP0 0044 6 1 INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. a n d d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES 2 0 09-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 P M I ic INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 C roch IFS0 0084 — DMA1IF ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 33 ip IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000 F T J ec IFS2 0088 — — — — — — — — — IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000 3 hn IFS3 008A — — — — — QEI1IF PSEMIF — — INT4IF INT3IF — — MI2C2IF SI2C2IF — 0000 2 o G lo IFS4 008C — — — — QEI2IF — PSESMIF — — C1TXIF — — — U2EIF U1EIF — 0000 g S y In IFS5 008E PWM2IF PWM1IF ADCP12IF — — — — — — — — — — — ADCP8IF — 0000 4 c. IFS6 0090 ADCP1IF ADCP0IF — — — — AC4IF AC3IF AC2IF — PWM8IF PWM7IF PWM6IF PWM5IF PWM4IF PWM3IF 0000 0 6 IFS7 0092 — — — — — — — — — — ADCP7IF ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF 0000 / 6 IEC0 0094 — DMA1IE ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 0 6 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE 0000 / 6 IEC2 0098 — — — — — — — — — IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000 0 IEC3 009A — — — — — QEI1IE PSEMIE — — INT4IE INT3IE — — MI2C2IE SI2C2IE — 0000 8 / IEC4 009C — — — — QEI2IE — PSESMIE — — C1TXIE — — — U2EIE U1EIE — 0000 6 1 IEC5 009E PWM2IE PWM1IE ADCP12IE — — — — — — — — — — — ADCP8IE — 0000 0 IEC6 00A0 ADCP1IE ADCP0IE — — — — AC4IE AC3IE AC2IE — PWM8IE PWM7IE PWM6IE PWM5IE PWM4IE PWM3IE 0000 a n IEC7 00A2 — — — — — — — — — — ADCP7IE ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE 0000 d IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444 d IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — DMA0IP2 DMA0IP1 DMA0IP0 4444 s P IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 4444 I C IPC3 00AA — — — — — DMA1IP2 DMA1IP1 DMA1IP0 — ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 4444 3 IPC4 00AC — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444 3 IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 F J IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — DMA2IP2 DMA2IP1 DMA2IP0 4444 6 4 IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444 G IPC8 00B4 — C1IP2 C1IP1 C1IP0 — C1RXIP2 C1RXIP1 C1RXIP0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPI2EIP2 SPI2EIP1 SPI2EIP0 4444 S IPC9 00B6 — — — — — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — DMA3IP2 DMA3IP1 DMA3IP0 0444 4 0 IPC12 00BC — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440 6 DS IPC13 00BE — — — — — INT4IP2 INT4IP1 INT4IP0 — INT3IP2 INT3IP1 INT3IP0 — — — — 0440 /6 70 IPC14 00C0 — — — — — QEI1IP2 QEI1IP0 QEI1IP0 — PSEMIP2 PSEMIP1 PSEMIP0 — — — — 0440 0 0 6 05 IPC16 00C4 — — — — — U2EIP2 U2EIP1 U2EIP0 — U1EIP2 U1EIP1 U1EIP0 — — — — 0440 /6 9 1 IPC17 00C6 — — — — — C1TXIP2 C1TXIP1 C1TXIP0 — — — — — — — — 0400 0 F -page ILPeCg1e8nd: 0x0C =8 unkno—wn valueQ oEnI2 RIPe2set, —Q E=I 2uInPim1plemQeEnIt2eIdP,0 read as ‘—0’. Reset val—ues are sho—wn in hexad—ecimal. — PSESMIP2 PSESMIP1 PSESMIP0 — — — — 4040 8/61 5 0 7

D TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES (CONTINUED) d S7 s 0005 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 9 1F IPC20 00CC — — — — — — — — — ADCP8IP2 ADCP8IP1 ADCP8IP0 — — — — 0040 3 -p 3 a IPC21 00CE — — — — — — — — — ADCP12IP2ADCP12IP1ADCP12IP0 — — — — 0040 F g e 5 IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — — 4400 J3 8 IPC24 00D4 — PWM6IP2 PWM6IP2 PWM6IP2 — PWM5IP2 PWM5IP1 PWM5IP0 — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0 4444 2 G IPC25 00D6 — AC2IP2 AC2IP1 AC2IP0 — — — — — PWM8IP2 PWM8IP1 PWM8IP0 — PWM7IP2 PWM7IP1 PWM7IP0 4044 S IPC26 00D8 — — — — — — — — — AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0 0044 4 IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — — 4400 0 6 IPC28 00DC — ADCP5IP2 ADCP5IP1 ADCP5IP0 — ADCP4IP2 ADCP4IP1 ADCP4IP0 — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2ADCP2IP1 ADCP2IP0 4444 / 6 IPC29 00DE — — — — — — — — — ADCP7IP2 ADCP7IP1 ADCP7IP0 — ADCP6IP2ADCP6IP1 ADCP6IP0 0044 0 6 INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2VECNUM1VECNUM0 0000 / 6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 8 / 6 1 0 a n d d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES 2 0 09-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 P M I ic INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 C roch IFS0 0084 — DMA1IF ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 33 ip IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000 F T J ec IFS2 0088 — — — — — — — — — IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000 3 hn IFS3 008A — — — — — QEI1IF PSEMIF — — INT4IF INT3IF — — MI2C2IF SI2C2IF — 0000 2 o G lo IFS4 008C — — — — QEI2IF — PSESMIF — — C1TXIF — — — U2EIF U1EIF — 0000 g S y In IFS5 008E PWM2IF PWM1IF ADCP12IF — — — — — — — — — — — — — 0000 4 c. IFS6 0090 ADCP1IF ADCP0IF — — — — AC4IF AC3IF AC2IF PWM9IF PWM8IF PWM7IF PWM6IF PWM5IF PWM4IF PWM3IF 0000 0 6 IFS7 0092 — — — — — — — — — — ADCP7IF ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF 0000 / 6 IEC0 0094 — DMA1IE ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 0 6 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE 0000 / 6 IEC2 0098 — — — — — — — — — IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000 0 IEC3 009A — — — — — QEI1IE PSEMIE — — INT4IE INT3IE — — MI2C2IE SI2C2IE — 0000 8 / IEC4 009C — — — — QEI2IE — PSESMIE — — C1TXIE — — — U2EIE U1EIE — 0000 6 1 IEC5 009E PWM2IE PWM1IE ADCP12IE — — — — — — — — — — — — — 0000 0 IEC6 00A0 ADCP1IE ADCP0IE — — — — AC4IE AC3IE AC2IE — — — PWM6IE PWM5IE PWM4IE PWM3IE 0000 a n IEC7 00A2 — — — — — — — — — — ADCP7IE ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE 0000 d IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444 d IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — DMA0IP2 DMA0IP1 DMA0IP0 4444 s P IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 4444 I C IPC3 00AA — — — — — DMA1IP2 DMA1IP1 DMA1IP0 — ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 4444 3 IPC4 00AC — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 — MI2C1IP2 MI2C1IP2 MI2C1IP2 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444 3 IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 F J IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — DMA2IP2 DMA2IP1 DMA2IP0 4444 6 4 IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444 G IPC8 00B4 — C1IP2 C1IP1 C1IP0 — C1RXIP2 C1RXIP1 C1RXIP0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPI2EIP2 SPI2EIP1 SPI2EIP0 4444 S IPC9 00B6 — — — — — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — DMA3IP2 DMA3IP1 DMA3IP0 0444 4 0 IPC12 00BC — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440 6 DS IPC13 00BE — — — — — INT4IP2 INT4IP1 INT4IP0 — INT3IP2 INT3IP1 INT3IP0 — — — — 0440 /6 70 IPC14 00C0 — — — — — QEI1IP2 QEI1IP1 QEI1IP0 — PSEMIP2 PSEMIP1 PSEMIP0 — — — — 0440 0 0 6 05 IPC16 00C4 — — — — — U2EIP2 U2EIP1 U2EIP0 — U1EIP2 U1EIP1 U1EIP0 — — — — 0440 /6 9 1 IPC17 00C6 — — — — — C1TXIP2 C1TXIP1 C1TXIP0 — — — — — — — — 0400 0 F -page ILPeCg1e8nd: 0x0 =C 8unknow—n valueQ oEnI 2RIPe2set, —QE =I 2uIPni1mpleQmEenI2tIePd0, read as— ‘0’. Reset v—alues are sh—own in hexa—decimal. — PSESMIP2 PSESMIP1 PSESMIP0 — — — — 4040 8/61 5 0 9

D TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES (CONTINUED) d S7 s 00 File SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All P 0 Name Addr Resets I 5 C 9 1F IPC21 00CE — — — — — — — — — ADCP12IP2 ADCP12IP1 ADCP12IP0 — — — — 0040 3 -pa IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — — 4400 3F g e 6 IPC24 00D4 — PWM6IP2 PWM6IP1 PWM6IP0 — PWM5IP2 PWM5IP1 PWM5IP0 — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0 4444 J3 0 IPC25 00D6 — AC2IP2 AC2IP1 AC2IP0 — PWM9IP2 PWM9IP1 PWM9IP0 — PWM8IP2 PWM8IP1 PWM8IP0 — PWM7IP2 PWM7IP1 PWM7IP0 4000 2 G IPC26 00D8 — — — — — — — — — AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0 0044 S IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — — 4400 4 IPC28 00DC — ADCP5IP2 ADCP5IP1 ADCP5IP0 — ADCP4IP2 ADCP4IP1 ADCP4IP0 — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1 ADCP2IP0 4444 0 6 IPC29 00DE — — — — — — — — — ADCP7IP2 ADCP7IP1 ADCP7IP0 — ADCP6IP2 ADCP6IP1 ADCP6IP0 0004 / 6 INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2VECNUM1VECNUM0 0000 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 / 6 0 8 / 6 1 0 a n d d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES 2 0 09-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — 0000 P M I ic INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 C roch IFS0 0084 — — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 33 ip IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — — — — INT1IF CNIF — MI2C1IF SI2C1IF 0000 F T J ec IFS2 0088 — — — — — — — — — IC4IF IC3IF — — — SPI2IF SPI2EIF 0000 3 hn IFS3 008A — — — — — QEI1IF PSEMIF — — INT4IF INT3IF — — MI2C2IF SI2C2IF — 0000 2 o G lo IFS4 008C — — — — — — PSESMIF — — — — — — U2EIF U1EIF — 0000 g S y In IFS5 008E PWM2IF PWM1IF ADCP12IF — — — — — — — — — — — — — 0000 4 c. IFS6 0090 ADCP1IF ADCP0IF — — — — — — — — — — PWM6IF PWM5IF PWM4IF PWM3IF 0000 0 6 IFS7 0092 — — — — — — — — — — ADCP7IF ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF 0000 / 6 IEC0 0094 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000 0 6 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE — — — — INT1IE CNIE — MI2C1IE SI2C1IE 0000 / 6 IEC2 0098 — — — — — — — — — IC4IE IC3IE — — — SPI2IE SPI2EIE 0000 0 IEC3 009A — — — — — QEI1IE PSEMIE — — INT4IE INT3IE — — MI2C2IE SI2C2IE — 0000 8 / IEC4 009C — — — — — — PSESMIE — — — — — — U2EIE U1EIE — 0000 6 1 IEC5 009E PWM2IE PWM1IE ADCP12IE — — — — — — — — — — — — — 0000 0 IEC6 00A0 — ADCP0IE — — — — — — — — — — PWM6IE PWM5IE PWM4IE PWM3IE 0000 a n IEC7 00A2 — — — — — — — — — ADCP7IE ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE 0000 d IPC0 00A4 T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444 d IPC1 00A6 T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4440 s P IPC2 00A8 U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 4444 I C IPC3 00AA — — — — — — — — ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044 3 IPC4 00AC — CNIP2 CNIP1 CNIP0 — — — — — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444 3 IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 F J IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — — — — 4440 6 4 IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444 G IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPI2EIP2 SPI2EIP1 SPI2EIP0 0044 S IPC9 00B6 — — — — — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — — — — 0440 4 0 IPC12 00BC — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440 6 DS IPC13 00BE — — — — — INT4IP2 INT4IP1 INT4IP0 — INT3IP2 INT3IP1 INT3IP0 — — — — 0440 /6 70 IPC14 00C0 — — — — — QEI1IP2 QEI1IP1 QEI1IP0 — PSEMIP2 PSEMIP1 PSEMIP0 — — — — 0440 0 0 6 05 IPC16 00C4 — — — — — U2EIP2 U2EIP1 U2EIP0 — U1EIP2 U1EIP1 U1EIP0 — — — — 0440 /6 9 1 IPC18 00C8 — — — — — — — — — PSESMIP2 PSESMIP1PSESMIP0 — — — — 0040 0 F -page ILPeCg2e3nd: 0x0D =2 unkno—wn valueP WonM R2eIPs2et, P—W =M u2nIPim1plePmWeMnt2eIPd,0 read as— ‘0’. ResePt WvaMlu1eIsP 2are PshWoMw1nI Pin1 hePxaWdMec1iImPa0l. — — — — — — — — 4400 8/61 6 0 1

DS7 TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES (CONTINUED) ds 0 P 0 File SFR All 05 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 9 1 3 F-p IPC24 00D4 — PWM6IP2 PWM6IP1 PWM6IP0 — PWM5IP2 PWM5IP1 PWM5IP0 — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0 4444 3 ag IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — — 4400 F e J 6 IPC28 00DC — ADCP5IP2 ADCP5IP1 ADCP5IP0 — ADCP4IP2 ADCP4IP1 ADCP4IP0 — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1 ADCP2IP0 4444 3 2 IPC29 00DE — — — — — — — — — ADCP7IP2 ADCP7IP1 ADCP7IP0 — ADCP6IP2 ADCP6IP1 ADCP6IP0 0004 2 G INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 S Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 0 6 / 6 0 6 / 6 0 8 / 6 1 0 a n d d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 TABLE 4-8: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES 2 0 09-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — 0000 P M I ic INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 C roch IFS0 0084 — — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 33 ip IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000 F T J ec IFS2 0088 — — — — — — — — — IC4IF IC3IF — — — SPI2IF SPI2EIF 0000 3 hn IFS3 008A — — — — — QEI1IF PSEMIF — — INT4IF INT3IF — — MI2C2IF SI2C2IF — 0000 2 o G lo IFS4 008C — — — — QEI2IF — PSESMIF — — — — — — U2EIF U1EIF — 0000 g S y In IFS5 008E PWM2IF PWM1IF ADCP12IF — — — — — — — — ADCP11IF ADCP10IF ADCP9IF ADCP8IF — 0000 4 c. IFS6 0090 ADCP1IF ADCP0IF — — — — AC4IF AC3IF AC2IF PWM9IF PWM8IF PWM7IF PWM6IF PWM5IF PWM4IF PWM3IF 0000 0 6 IFS7 0092 — — — — — — — — — — ADCP7IF ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF 0000 / 6 IEC0 0094 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000 0 6 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE — — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE 0000 / 6 IEC2 0098 — — — — — — — — — IC4IE IC3IE — — — SPI2IE SPI2EIE 0000 0 IEC3 009A — — — — — QEI1IE PSEMIE — — INT4IE INT3IE — — MI2C2IE SI2C2IE — 0000 8 / IEC4 009C — — — — QEI2IE — PSESMIE — — — — — — U2EIE U1EIE — 0000 6 1 IEC5 009E PWM2IE PWM1IE ADCP12IE — — — — — — — — ADCP11IE ADCP10IE ADCP9IE ADCP8IE — 0000 0 IEC6 00A0 ADCP1IE ADCP0IE — — — — AC4IE AC3IE AC2IE PWM9IE PWM8IE PWM7IE PWM6IE PWM5IE PWM4IE PWM3IE 0000 a n IEC7 00A2 — — — — — — — — — — ADCP7IE ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE 0000 d IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444 d IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4440 s P IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 4444 I C IPC3 00AA — — — — — — — — — ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044 3 IPC4 00AC — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444 3 IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 F J IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — — — — 4440 6 4 IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444 G IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPI2EIP2 SPI2EIP1 SPI2EIP0 0044 S IPC9 00B6 — — — — — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — — — — 0440 4 0 IPC12 00BC — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440 6 DS IPC13 00BE — — — — — INT4IP2 INT4IP1 INT4IP0 — INT3IP2 INT3IP1 INT3IP0 — — — — 0440 /6 70 IPC14 00C0 — — — — — QEI1IP2 QEI1IP1 QEI1IP0 — PSEMIP2 PSEMIP1 PSEMIP0 — — — — 0440 0 0 6 05 IPC16 00C4 — — — — — U2EIP2 U2EIP1 U2EIP0 — U1EIP2 U1EIP1 U1EIP0 — — — — 0440 /6 9 1 IPC18 00C8 — QEI2IP2 QEI2IP1 QEI2IP0 — — — — — PSESMIP2 PSESMIP1 PSESMIP0 — — — — 4040 0 F -page ILPeCg2e0nd: 0x0 C=C unkno—wn valuAeD oCnP R10eIsPe2t, A—D C=P u1n0imIPp1leAmDeCnPte1d0,I Pre0ad as —‘0’. ReseAtD vCaPlu9eIsP 2areA DshCoPw9nIP in1 hAeDxaCdPe9cIiPm0al. — ADCP8IP2 ADCP8IP1 ADCP8IP0 — — — — 4440 8/61 6 0 3

D TABLE 4-8: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES (CONTINUED) d S7 s 0 P 0 File SFR All 05 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 9 1 3 F IPC21 00CE — — — — — — — — — ADCP12IP2ADCP12IP1 ADCP12IP0 — ADCP11IP2ADCP11IP1ADCP11IP0 0044 -p 3 a IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — — 4400 F g e J 6 IPC24 00D4 — PWM6IP2 PWM6IP1 PWM6IP0 — PWM5IP2 PWM5IP1 PWM5IP0 — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0 4444 3 4 IPC25 00D6 — AC2IP2 AC2IP1 AC2IP0 — PWM9IP2 PWM9IP1 PWM9IP0 — PWM8IP2 PWM8IP1 PWM8IP0 — PWM7IP2 PWM7IP1 PWM7IP0 4444 2 G IPC26 00D8 — — — — — — — — — AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0 0044 S IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — — 4400 4 IPC28 00DC — ADCP5IP2 ADCP5IP1 ADCP5IP0 — ADCP4IP2 ADCP4IP1 ADCP4IP0 — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1 ADCP2IP0 4444 0 6 IPC29 00DE — — — — — — — — — ADCP7IP2 ADCP7IP1 ADCP7IP0 — ADCP6IP2 ADCP6IP1 ADCP6IP0 0044 / 6 INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 0 6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / 6 0 8 / 6 1 0 a n d d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 TABLE 4-9: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS608 2 0 09-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — 0000 P M I ic INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 C roch IFS0 0084 — — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 33 ip IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000 F T J ec IFS2 0088 — — — — — — — — — IC4IF IC3IF — — — SPI2IF SPI2EIF 0000 3 hn IFS3 008A — — — — — QEI1IF PSEMIF — — INT4IF INT3IF — — MI2C2IF SI2C2IF — 0000 2 o G lo IFS4 008C — — — — QEI2IF — PSESMIF — — — — — — U2EIF U1EIF — 0000 g S y In IFS5 008E PWM2IF PWM1IF ADCP12IF — — — — — — — — — — — ADCP8IF — 0000 4 c. IFS6 0090 ADCP1IF ADCP0IF — — — — AC4IF AC3IF AC2IF — PWM8IF PWM7IF PWM6IF PWM5IF PWM4IF PWM3IF 0000 0 6 IFS7 0092 — — — — — — — — — — ADCP7IF ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF 0000 / 6 IEC0 0094 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000 0 6 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE — — — — INT1IE CNIE — MI2C1IE SI2C1IE 0000 / 6 IEC2 0098 — — — — — — — — — IC4IE IC3IE — — — SPI2IE SPI2EIE 0000 0 IEC3 009A — — — — — QEI1IE PSEMIE — — INT4IE INT3IE — — MI2C2IE SI2C2IE — 0000 8 / IEC4 009C — — — — QEI2IE — PSESMIE — — — — — — U2EIE U1EIE — 0000 6 1 IEC5 009E PWM2IE PWM1IE ADCP12IE — — — — — — — — — — — ADCP8IE — 0000 0 IEC6 00A0 ADCP1IE ADCP0IE — — — — AC4IE AC3IE AC2IE — PWM8IE PWM7IE PWM6IE PWM5IE PWM4IE PWM3IE 0000 a n IEC7 00A2 — — — — — — — — — — ADCP7IE ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE 0000 d IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444 d IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4440 s P IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 4444 I C IPC3 00AA — — — — — — — — — ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044 3 IPC4 00AC — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444 3 IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 F J IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — — — — 4440 6 4 IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444 G IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPI2EIP2 SPI2EIP1 SPI2EIP0 0044 S IPC9 00B6 — — — — — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — — — — 0440 4 0 IPC12 00BC — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440 6 DS IPC13 00BE — — — — — INT4IP2 INT4IP1 INT4IP0 — INT3IP2 INT3IP1 INT3IP0 — — — — 0440 /6 70 IPC14 00C0 — — — — — QEI1IP2 QEI1IP1 QEI1IP0 — PSEMIP2 PSEMIP1 PSEMIP0 — — — — 0440 0 0 6 05 IPC16 00C4 — — — — — U2EIP2 U2EIP1 U2EIP0 — U1EIP2 U1EIP1 U1EIP0 — — — — 0440 /6 9 1 IPC18 00C8 — QEI2IP2 QEI2IP1 QEI2IP0 — — — — — PSESMIP2 PSESMIP1 PSESMIP0 — — — — 4040 0 F -page ILPeCg2e0nd: 0x0 C=C unkno—wn value on— Reset, — =— unimpleme—nted, read as— ‘0’. Reset va—lues are sho—wn in hexad—ecimal. — ADCP8IP2 ADCP8IP1 ADCP8IP0 — — — — 0040 8/61 6 0 5

D TABLE 4-9: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS608 (CONTINUED) d S7 s 0 P 0 File SFR All 05 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 9 1 3 F-p IPC21 00CE — — — — — — — — — ADCP12IP2ADCP12IP1 ADCP12IP1 — — — — 0040 3 a IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — — 4400 F g e J 6 IPC24 00D4 — PWM6IP2 PWM6IP1 PWM6IP0 — PWM5IP2 PWM5IP1 PWM5IP0 — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0 4444 3 6 IPC25 00D6 — AC2IP2 AC2IP1 AC2IP0 — — — — — PWM8IP2 PWM8IP1 PWM8IP0 — PWM7IP2 PWM7IP1 PWM7IP0 4044 2 G IPC26 00D8 — — — — — — — — — AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0 0044 S IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — — 4400 4 IPC28 00DC — ADCP5IP2 ADCP5IP1 ADCP5IP0 — ADCP4IP2 ADCP4IP1 ADCP4IP0 — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1ADCP2IP0 4444 0 6 IPC29 00DE — — — — — — — — — ADCP7IP2 ADCP7IP1 ADCP7IP0 — ADCP6IP2 ADCP6IP1ADCP6IP0 0044 / 6 INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2VECNUM1VECNUM0 0000 0 6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / 6 0 8 / 6 1 0 a n d d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 TABLE 4-10: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES 2 0 09-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — 0000 P M I ic INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 C roch IFS0 0084 — — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 33 ip IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000 F T J ec IFS2 0088 — — — — — — — — — IC4IF IC3IF — — — SPI2IF SPI2EIF 0000 3 hn IFS3 008A — — — — — QEI1IF PSEMIF — — INT4IF INT3IF — — MI2C2IF SI2C2IF — 0000 2 o G lo IFS4 008C — — — — QEI2IF — PSESMIF — — — — — — U2EIF U1EIF — 0000 g S y In IFS5 008E PWM2IF PWM1IF ADCP12IF — — — — — — — — — — — — — 0000 4 c. IFS6 0090 ADCP1IF ADCP0IF — — — — AC4IF AC3IF AC2IF — — — PWM6IF PWM5IF PWM4IF PWM3IF 0000 0 6 IFS7 0092 — — — — — — — — — — ADCP7IF ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF 0000 / 6 IEC0 0094 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000 0 6 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE — — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE 0000 / 6 IEC2 0098 — — — — — — — — — IC4IE IC3IE — — — SPI2IE SPI2EIE 0000 0 IEC3 009A — — — — — QEI1IE PSEMIE — — INT4IE INT3IE — — MI2C2IE SI2C2IE — 0000 8 / IEC4 009C — — — — QEI2IE — PSESMIE — — — — — — U2EIE U1EIE — 0000 6 1 IEC5 009E PWM2IE PWM1IE ADCP12IE — — — — — — — — — — — — — 0000 0 IEC6 00A0 ADCP1IE ADCP0IE — — — — AC4IE AC3IE AC2IE — — — PWM6IE PWM5IE PWM4IE PWM3IE 0000 a n IEC7 00A2 — — — — — — — — — — ADCP7IE ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE 0000 d IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444 d IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4440 s P IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 4444 I C IPC3 00AA — — — — — — — — — ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044 3 IPC4 00AC — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444 3 IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 F J IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — — — — 4440 6 4 IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444 G IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPI2EIP2 SPI2EIP1 SPI2EIP0 0044 S IPC9 00B6 — — — — — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — — — — 0440 4 0 IPC12 00BC — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440 6 DS IPC13 00BE — — — — — INT4IP2 INT4IP1 INT4IP0 — INT3IP2 INT3IP1 INT3IP0 — — — — 0440 /6 70 IPC14 00C0 — — — — — QEI1IP2 QEI1IP1 QEI1IP0 — PSEMIP2 PSEMIP1 PSEMIP0 — — — — 0440 0 0 6 05 IPC16 00C4 — — — — — U2EIP2 U2EIP1 U2EIP0 — U1EIP2 U1EIP1 U1EIP0 — — — — 0440 /6 9 1 IPC18 00C8 — QEI2IP2 QEI2IP1 QEI2IP0 — — — — — PSESMIP2 PSESMIP1 PSESMIP0 — — — — 4040 0 F -page ILPeCg2e1nd: 0x0 C=E unkno—wn value on— Reset, — —= unimplem—ented, read a—s ‘0’. Reset v—alues are sh—own in hexa—decimal. — ADCP12IP2ADCP12IP1 ADCP12IP0 — — — — 0040 8/61 6 0 7

D TABLE 4-10: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES (CONTINUED) d S7 s 0 P 0 File SFR All 05 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 9 1 3 F-p IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — — 4400 3 a IPC24 00D4 — PWM6IP2 PWM6IP1 PWM6IP0 — PWM5IP2 PWM5IP1 PWM5IP0 — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0 4444 F g e J 6 IPC25 00D6 — AC2IP2 AC2IP1 AC2IP0 — — — — — — — — — — — — 4000 3 8 IPC26 00D8 — — — — — — — — — AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0 0044 2 G IPC27 00DA — ADCP1IP2ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — — 4400 S IPC28 00DC — ADCP5IP2ADCP5IP1 ADCP5IP0 — ADCP4IP2 ADCP4IP1 ADCP4IP0 — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1 ADCP2IP0 4444 4 IPC29 00DE — — — — — — — — — ADCP7IP2 ADCP7IP1 ADCP7IP0 — ADCP6IP2 ADCP6IP1 ADCP6IP0 0004 0 6 INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2VECNUM1VECNUM0 0000 / 6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 6 / 6 0 8 / 6 1 0 a n d d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 TABLE 4-11: TIMERS REGISTER MAP 2 0 09-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 TMR1 0100 Timer1 Register 0000 P M I ic PR1 0102 Period Register 1 FFFF C roch T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 33 ip TMR2 0106 Timer2 Register 0000 F T J ec TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx 3 hn TMR3 010A Timer3 Register 0000 2 o G log PR2 010C Period Register 2 FFFF S y In PR3 010E Period Register 3 FFFF 4 c 0 . T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 6 T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 / 6 TMR4 0114 Timer4 Register 0000 0 6 TMR5HLD 0116 Timer5 Holding Register (for 32-bit timer operations only) xxxx / 6 TMR5 0118 Timer5 Register 0000 0 PR4 011A Period Register 4 FFFF 8 / 6 PR5 011C Period Register 5 FFFF 1 T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 0 T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 a n Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d d s TABLE 4-12: INPUT CAPTURE REGISTER MAP P I File SFR All C Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets 3 3 IC1BUF 0140 Input 1 Capture Register xxxx F J IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 6 IC2BUF 0144 Input 2 Capture Register xxxx 4 G IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 S IC3BUF 0148 Input 3 Capture Register xxxx 4 IC3CON 014A — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 0 6 D IC4BUF 014C Input 4 Capture Register xxxx / S 6 7 IC4CON 014E — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 0 0 005 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6/6 9 1 0 F -p 8 ag /6 e 1 6 0 9

D TABLE 4-13: OUTPUT COMPARE REGISTER MAP d S7 s 0005 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 9 1F OC1RS 0180 Output Compare 1 Secondary Register xxxx 3 -p 3 a OC1R 0182 Output Compare 1 Register xxxx F g e 7 OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 J3 0 OC2RS 0186 Output Compare 2 Secondary Register xxxx 2 G OC2R 0188 Output Compare 2 Register xxxx S OC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 4 OC3RS 018C Output Compare 3 Secondary Register xxxx 0 6 OC3R 018E Output Compare 3 Register xxxx / 6 OC3CON 0190 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 0 6 OC4RS 0192 Output Compare 4 Secondary Register xxxx / 6 OC4R 0194 Output Compare 4 Register xxxx 0 OC4CON 0196 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 8 / Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 1 0 a TABLE 4-14: QEI1 REGISTER MAP n d NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts d s QEI1CON 01E0 CNTERR — QEISIDL INDX UPDN QEIM2 QEIM1 QEIM0 SWPAB PCDOUT TQGATE TQCKPS1 TQCKPS0 POSRES TQCS UPDN_SRC 0000 P I DFLT1CON 01E2 — — — — — IMV1 IMV0 CEID QEOUT QECK2 QECK1 QECK0 — — — — 0000 C POS1CNT 01E4 Position Counter<15:0> 0000 3 3 MAX1CNT 01E6 Maximum Count<15:0> FFFF F Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. J 6 4 G  2 TABLE 4-15: QEI2 REGISTER MAP S 0 0 4 9-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 06 1 / 4 M QEI2CON 01F0 CNTERR — QEISIDL INDX UPDN QEIM2 QEIM1 QEIM0 SWPAB PCDOUT TQGATE TQCKPS1 TQCKPS0 POSRES TQCS UPDN_SRC 0000 60 ic DFLT2CON 01F2 — — — — — IMV1 IMV0 CEID QEOUT QECK2 QECK1 QECK0 — — — — 0000 6 roch POS2CNT 01F4 Position Counter<15:0> 0000 /6 ip T MAX2CNT 01F6 Maximum Count<15:0> FFFF 08 ec Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /6 h n 1 o lo 0 g y In c .

 2 TABLE 4-16: HIGH-SPEED PWM REGISTER MAP 0 0 9-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 P M PTCON 0400 PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC2 SYNCSRC1 SYNCSRC0 SEVTPS3 SEVTPS2 SEVTPS1 SEVTPS0 0000 I C icro PTCON2 0402 — — — — — — — — — — — — — PCLKDIV<2:0> 0000 3 ch PTPER 0404 PTPER<15:0> FFF8 3 ip F T SEVTCMP 0406 SEVTCMP<12:0> — — — 0000 J echn MDC 040A MDC<15:0> 0000 32 o STCON 040E — — — SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC2 SYNCSRC1 SYNCSRC0 SEVTPS3 SEVTPS2 SEVTPS1 SEVTPS0 0000 G lo gy STCON2 0410 — — — — — — — — — — — — — PCLKDIV<2:0> 0000 S Inc STPER 0412 STPER<15:0> FFF8 40 . SSEVTCMP 0414 SSEVTCMP<15:3> — — — 0000 6 / CHOP 041A CHPCLKEN — — — — — CHOPCLK6 CHOPCLK5 CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0 — — — 0000 6 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 / 6 0 8 TABLE 4-17: HIGH-SPEED PWM GENERATOR 1 REGISTER MAP / 6 1 File SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 0 Name Addr Resets a PWMCON10420 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 DTCP — MTBS CAM XPRES IUE 0000 n d IOCON1 0422 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000 d FCLCON1 0424IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000 s PDC1 0426 PDC1<15:0> 0000 P I PHASE1 0428 PHASE1<15:0> 0000 C 3 DTR1 042A — — DTR1<13:0> 0000 3 ALTDTR1 042C — — ALTDTR1<13:0> 0000 F J SDC1 042E SDC1<15:0> 0000 6 SPHASE1 0430 SPHASE1<15:0> 0000 4 G TRIG1 0432 TRGCMP<12:0> — — — 0000 S TRGCON1 0434TRGDIV3TRGDIV2TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5TRGSTRT4TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000 4 STRIG1 0436 STRGCMP<12:0> — — — 0000 0 6 D PWMCAP1 0438 PWMCAP<12:0> — — — 0000 / S 6 7 LEBCON1 043A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 0 0 005 LEBDLY1 043C — — — — LEB<8:0> — — — 0000 6/6 91 AUXCON1 043E HRPDIS HRDDIS — — BLANKSEL3BLANKSEL2BLANKSEL1BLANKSEL0 — — CHOPSEL3CHOPSEL2CHOPSEL1CHOPSEL0 CHOPHEN CHOPLEN 0000 0 F -p Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 8 ag /6 e 1 7 0 1

D d S7 TABLE 4-18: HIGH-SPEED PWM GENERATOR 2 REGISTER MAP s 0 P 0 0 File SFR All I 5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C 9 Name Addr Resets 1 3 F -p PWMCON2 0440 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 DTCP — MTBS CAM XPRES IUE 0000 3 a F ge IOCON2 0442 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000 J 72 FCLCON2 0444 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000 32 PDC2 0446 PDC2<15:0> 0000 G PHASE2 0448 PHASE2<15:0> 0000 S 4 DTR2 044A — — DTR2<13:0> 0000 0 ALTDTR2 044C — — ALTDTR2<13:0> 0000 6 / SDC2 044E SDC2<15:0> 0000 6 0 SPHASE2 0450 SPHASE2<15:0> 0000 6 TRIG2 0452 TRGCMP<12:0> — — — 0000 /6 0 TRGCON2 0454 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000 8 STRIG2 0456 STRGCMP<12:0> — — — 0000 /6 PWMCAP2 0458 PWMCAP<12:0> — — — 0000 1 0 LEBCON2 045A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 a LEBDLY2 045C — — — — LEB<8:0> — — — 0000 n AUXCON2 045E HRPDIS HRDDIS — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 — — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN 0000 d Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 2 TABLE 4-19: HIGH-SPEED PWM GENERATOR 3 REGISTER MAP 0 0 9-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 P M PWMCON3 0460 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 DTCP — MTBS CAM XPRES IUE 0000 I C icro IOCON3 0462 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000 3 ch FCLCON3 0464 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000 3 ip F T PDC3 0466 PDC3<15:0> 0000 J echn PHASE3 0468 PHASE3<15:0> 0000 32 o DTR3 046C — — DTR3<13:0> 0000 G lo gy ALTDTR3 046C — — ALTDTR3<13:0> 0000 S Inc SDC3 046E SDC3<15:0> 0000 40 . SPHASE3 0470 SPHASE3<15:0> 0000 6 / TRIG3 0472 TRGCMP<12:0> — — — 0000 6 0 TRGCON3 0474 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000 6 / STRIG3 0476 STRGCMP<12:0> — — — 0000 6 0 PWMCAP3 0478 PWMCAP<12:0> — — — 0000 8 LEBCON3 047A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 /6 LEBDLY3 047C — — — — LEB<8:0> — — — 0000 1 0 AUXCON3 047E HRPDIS HRDDIS — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 — — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN 0000 a Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. n d d s P I C 3 3 F J 6 4 G S 4 0 6 D / S 6 7 0 0 0 6 05 /6 9 1 0 F -p 8 ag /6 e 1 7 0 3

D d S7 TABLE 4-20: HIGH-SPEED PWM GENERATOR 4 REGISTER MAP s 0 P 0 0 File SFR All I 5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C 9 Name Addr Resets 1 3 F -p PWMCON4 0480 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 DTCP — MTBS CAM XPRES IUE 0000 3 a F ge IOCON4 0482 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000 J 74 FCLCON4 0484 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000 32 PDC4 0486 PDC4<15:0> 0000 G PHASE4 0488 PHASE4<15:0> 0000 S 4 DTR4 048A — — DTR4<13:0> 0000 0 ALTDTR4 048A — — ALTDTR4<13:0> 0000 6 / SDC4 048E SDC4<15:0> 0000 6 0 SPHASE4 0490 SPHASE4<15:0> 0000 6 TRIG4 0492 TRGCMP<12:0> — — — 0000 /6 0 TRGCON4 0494 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000 8 STRIG4 0496 STRGCMP<12:0> — — — 0000 /6 PWMCAP4 0498 PWMCAP<12:0> — — — 0000 1 0 LEBCON4 049A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 a LEBDLY4 049C — — — — LEB<8:0> — — — 0000 n AUXCON4 049E HRPDIS HRDDIS — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 — — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN 0000 d Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 2 TABLE 4-21: HIGH-SPEED PWM GENERATOR 5 REGISTER MAP 0 0 9-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 P M PWMCON5 04A0 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 DTCP — MTBS CAM XPRES IUE 0000 I C icro IOCON5 04A2 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000 3 ch FCLCON5 04A4 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000 3 ip F T PDC5 04A6 PDC5<15:0> 0000 J echn PHASE5 04A8 PHASE5<15:0> 0000 32 o DTR5 04AA — — DTR5<13:0> 0000 G lo gy ALTDTR5 04AA — — ALTDTR5<13:0> 0000 S Inc SDC5 04AE SDC5<15:0> 0000 40 . SPHASE5 04B0 SPHASE5<15:0> 0000 6 / TRIG5 04B2 TRGCMP<12:0> — — — 0000 6 0 TRGCON5 04B4 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000 6 / STRIG5 04B6 STRGCMP<12:0> — — — 0000 6 0 PWMCAP5 04B8 PWMCAP<12:0> — — — 0000 8 LEBCON5 04BA PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 /6 LEBDLY5 04BC — — — — LEB<8:0> — — — 0000 1 0 AUXCON5 04BE HRPDIS HRDDIS — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 — — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN 0000 a Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. n d d s P I C 3 3 F J 6 4 G S 4 0 6 D / S 6 7 0 0 0 6 05 /6 9 1 0 F -p 8 ag /6 e 1 7 0 5

D d S7 TABLE 4-22: HIGH-SPEED PWM GENERATOR 6 REGISTER MAP s 0 P 0 0 File SFR All I 5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C 9 Name Addr Resets 1 3 F -p PWMCON6 04C0 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 DTCP — MTBS CAM XPRES IUE 0000 3 a F ge IOCON6 04C2 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000 J 76 FCLCON6 04C4 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000 32 PDC6 04C6 PDC6<15:0> 0000 G PHASE6 04C8 PHASE6<15:0> 0000 S 4 DTR6 04CA — — DTR6<13:0> 0000 0 ALTDTR6 04CA — — ALTDTR6<13:0> 0000 6 / SDC6 04CE SDC6<15:0> 0000 6 0 SPHASE6 04D0 SPHASE6<15:0> 0000 6 TRIG6 04D2 TRGCMP<12:0> — — — 0000 /6 0 TRGCON6 04D4 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000 8 STRIG6 04D6 STRGCMP<12:0> — — — 0000 /6 PWMCAP6 04D8 PWMCAP<12:0> — — — 0000 1 0 LEBCON6 04DA PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 a LEBDLY6 04DC — — — — LEB<8:0> — — — 0000 n AUXCON6 04DE HRPDIS HRDDIS — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 — — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN 0000 d Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 2 TABLE 4-23: HIGH-SPEED PWM GENERATOR 7 REGISTER MAP (EXCLUDES dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES) 0 0 9-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 P M PWMCON7 04E0 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 DTCP — MTBS CAM XPRES IUE 0000 I C icro IOCON7 04E2 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000 3 ch FCLCON7 04E4 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000 3 ip F T PDC7 04E6 PDC7<15:0> 0000 J echn PHASE7 04E8 PHASE7<15:0> 0000 32 o DTR7 04EA — — DTR7<13:0> 0000 G lo gy ALTDTR7 04EA — — ALTDTR7<13:0> 0000 S Inc SDC7 04EE SDC7<15:0> 0000 40 . SPHASE7 04F0 SPHASE7<15:0> 0000 6 / TRIG7 04F2 TRGCMP<12:0> — — — 0000 6 0 TRGCON7 04F4 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000 6 / STRIG7 04F6 STRGCMP<12:0> — — — 0000 6 0 PWMCAP7 04F8 PWMCAP<12:0> — — — 0000 8 LEBCON7 04FA PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 /6 LEBDLY7 04FC — — — — LEB<8:0> — — — 0000 1 0 AUXCON7 04FE HRPDIS HRDDIS — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 — — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN 0000 a Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. n d d s P I C 3 3 F J 6 4 G S 4 0 6 D / S 6 7 0 0 0 6 05 /6 9 1 0 F -p 8 ag /6 e 1 7 0 7

D d S7 TABLE 4-24: HIGH-SPEED PWM GENERATOR 8 REGISTER MAP (EXCLUDES dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES) s 0 P 0 0 File SFR All I 5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C 9 Name Addr Resets 1 3 F -p PWMCON8 0500 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 DTCP — MTBS CAM XPRES IUE 0000 3 a F ge IOCON8 0502 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000 J 78 FCLCON8 0504 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000 32 PDC8 0506 PDC8<15:0> 0000 G PHASE8 0508 PHASE8<15:0> 0000 S 4 DTR8 050A — — DTR8<13:0> 0000 0 ALTDTR8 050A — — ALTDTR8<13:0> 0000 6 / SDC8 050E SDC8<15:0> 0000 6 0 SPHASE8 0510 SPHASE8<15:0> 0000 6 TRIG8 0512 TRGCMP<12:0> — — — 0000 /6 0 TRGCON8 0514 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000 8 STRIG8 0516 STRGCMP<12:0> — — — 0000 /6 PWMCAP8 0518 PWMCAP<12:0> — — — 0000 1 0 LEBCON8 051A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 a LEBDLY8 051C — — — — LEB<8:0> — — — 0000 n AUXCON8 051E HRPDIS HRDDIS — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 — — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN 0000 d Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 2 TABLE 4-25: HIGH-SPEED PWM GENERATOR 9 REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES 0 0 9-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 P M PWMCON9 0520 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 DTCP — MTBS CAM XPRES IUE 0000 I C icro IOCON9 0522 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000 3 ch FCLCON9 0524 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000 3 ip F T PDC9 0526 PDC9<15:0> 0000 J echn PHASE9 0528 PHASE9<15:0> 0000 32 o DTR9 052A — — DTR9<13:0> 0000 G lo gy ALTDTR9 052A — — ALTDTR9<13:0> 0000 S Inc SDC9 052E SDC9<15:0> 0000 40 . SPHASE9 0530 SPHASE9<15:0> 0000 6 / TRIG9 0532 TRGCMP<15:0> 0000 6 0 TRGCON9 0534 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000 6 / STRIG9 0536 STRGCMP<15:0> 0000 6 0 PWMCAP9 0538 PWMCAP<12:0> — — — 0000 8 LEBCON9 053A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000 /6 LEBDLY9 053C — — — — LEB<8:0> — — — 0000 1 0 AUXCON9 053E HRPDIS HRDDIS — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 — — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN 0000 a Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. n d d s P I C 3 3 F J 6 4 G S 4 0 6 D / S 6 7 0 0 0 6 05 /6 9 1 0 F -p 8 ag /6 e 1 7 0 9

D d S7 TABLE 4-26: I2C1 REGISTER MAP s 0 P 0 File SFR All 05 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 9 1 3 F-p I2C1RCV 0200 — — — — — — — — I2C1 Receive Register 0000 3 a I2C1TRN 0202 — — — — — — — — I2C1 Transmit Register 00FF F g e J 8 I2C1BRG 0204 — — — — — — — Baud Rate Generator Register 0000 3 0 I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 2 G I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 S I2C1ADD 020A — — — — — — I2C1 Address Register 0000 4 I2C1MSK 020C — — — — — — I2C1 Address Mask Register 0000 0 6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / 6 0 6 TABLE 4-27: I2C2 REGISTER MAP /6 0 File SFR All 8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets / 6 1 I2C2RCV 0210 — — — — — — — — I2C2 Receive Register 0000 0 I2C2TRN 0212 — — — — — — — — I2C2 Transmit Register 00FF a I2C2BRG 0214 — — — — — — — Baud Rate Generator Register 0000 n d I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 d I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 s I2C2ADD 021A — — — — — — I2C2 Address Register 0000 P I I2C2MSK 021C — — — — — — I2C2 Address Mask Register 0000 C Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 TABLE 4-28: UART1 REGISTER MAP 2 0 09-20 File Name ASdFdRr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000 P M I ic U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 C roch U1TXREG 0224 — — — — — — — UART1 Transmit Register xxxx 33 ip U1RXREG 0226 — — — — — — — UART1 Receive Register 0000 F T J ec U1BRG 0228 Baud Rate Generator Prescaler 0000 3 hn Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 o G lo g S y In TABLE 4-29: UART2 REGISTER MAP 4 c 0 . 6 File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 / Name Addr Resets 6 0 U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000 6 / U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 6 0 U2TXREG 0234 — — — — — — — UART2 Transmit Register xxxx 8 U2RXREG 0236 — — — — — — — UART2 Receive Register 0000 /6 1 U2BRG 0238 Baud Rate Generator Prescaler 0000 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. a n d d s P I C 3 3 F J 6 4 G S 4 0 6 D / S 6 7 0 0 0 6 05 /6 9 1 0 F -p 8 ag /6 e 1 8 0 1

D TABLE 4-30: SPI1 REGISTER MAP d S7 s 0 P 0 SFR All 05 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 9 1 3 F-p SPI1STAT 0240 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 3 a SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 F g e J 8 SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY — 0000 3 2 SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000 2 G Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. S 4 0 TABLE 4-31: SPI2 REGISTER MAP 6 / 6 File Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 0 Addr. Resets 6 / SPI2STAT 0260 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 6 0 SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 8 SPI2CON2 0264 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY — 0000 /6 1 SPI2BUF 0268 SPI2 Transmit and Receive Buffer Register 0000 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. a n d d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 TABLE 4-32: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES ONLY 2 0 09-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 M ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0 0003 PI C ic ADPCFG 0302 PCFG<15:0> 0000 ro 3 ch ADPCFG2 0304 — — — — — — — — PCFG<23:16> 0000 3 ip ADSTAT 0306 — — — P12RDY P11RDY P10RDY P9RDY P8RDY P7RDY P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY P0RDY 0000 F T J ec ADBASE 0308 ADBASE<15:1> — 0000 3 hn ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00 0000 2 o G log ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20 0000 S y In ADCPC2 030E IRQEN5 PEND5 SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50 IRQEN4 PEND4 SWTRG4 TRGSRC44 TRGSRC43 TRGSRC42 TRGSRC41 TRGSRC40 0000 4 c 0 . ADCPC3 0310 IRQEN7 PEND7 SWTRG7 TRGSRC74 TRGSRC73 TRGSRC72 TRGSRC71 TRGSRC70 IRQEN6 PEND6 SWTRG6 TRGSRC64 TRGSRC63 TRGSRC62 TRGSRC61 TRGSRC640 0000 6 ADCPC4 0312 IRQEN9 PEND9 SWTRG9 TRGSRC94 TRGSRC93 TRGSRC92 TRGSRC94 TRGSRC90 IRQEN8 PEND8 SWTRG8 TRGSRC84 TRGSRC83 TRGSRC82 TRGSRC81 TRGSRC80 0000 /6 ADCPC5 0314 IRQEN11 PEND11 SWTRG11 TRGSRC114 TRGSRC113 TRGSRC112 TRGSRC111 TRGSRC110 IRQEN10 PEND10 SWTRG10 TRGSRC104 TRGSRC103 TRGSRC102 TRGSRC101 TRGSRC100 0000 0 6 ADCPC6 0316 — — — — — — — — IRQEN12 PEND12 SWTRG12 TRGSRC124 TRGSRC123 TRGSRC122 TRGSRC121 TRGSRC120 0000 / 6 ADCBUF0 0340 ADC Data Buffer 0 xxxx 0 8 ADCBUF1 0342 ADC Data Buffer 1 xxxx / 6 ADCBUF2 0344 ADC Data Buffer 2 xxxx 1 ADCBUF3 0346 ADC Data Buffer 3 xxxx 0 ADCBUF4 0348 ADC Data Buffer 4 xxxx a n ADCBUF5 034A ADC Data Buffer 5 xxxx d ADCBUF6 034C ADC Data Buffer 6 xxxx d ADCBUF7 034E ADC Data Buffer 7 xxxx s P ADCBUF8 0350 ADC Data Buffer 8 xxxx I C ADCBUF9 0352 ADC Data Buffer 9 xxxx 3 ADCBUF10 0354 ADC Data Buffer 10 xxxx 3 F ADCBUF11 0356 ADC Data Buffer 11 xxxx J ADCBUF12 0358 ADC Data Buffer 12 xxxx 6 4 ADCBUF13 035A ADC Data Buffer 13 xxxx G ADCBUF14 035C ADC Data Buffer 14 xxxx S ADCBUF15 035E ADC Data Buffer 15 xxxx 4 0 ADCBUF16 0360 ADC Data Buffer 16 xxxx 6 DS ADCBUF17 0362 ADC Data Buffer 17 xxxx /6 7 0 0 ADCBUF18 0364 ADC Data Buffer 18 xxxx 0 6 05 ADCBUF19 0366 ADC Data Buffer 19 xxxx /6 9 1F ADCBUF20 0368 ADC Data Buffer 20 xxxx 0 -pag ADCBUF21 036A ADC Data Buffer 21 xxxx 8/6 e Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 8 0 3

D TABLE 4-32: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES ONLY (CONTINUED) d S7 s 000 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PI 5 C 9 1F ADCBUF22 036C ADC Data Buffer 22 xxxx 3 -pa ADCBUF23 036E ADC Data Buffer 23 xxxx 3F g e 8 ADCBUF24 0370 ADC Data Buffer 24 xxxx J3 4 ADCBUF25 0372 ADC Data Buffer 25 xxxx 2 G Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. S 4 0 6 / 6 0 6 / 6 0 8 / 6 1 0 a n d d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 TABLE 4-33: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES 2 0 09-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0 0003 P M I ic ADPCFG 0302 PCFG<15:0> 0000 C roch ADPCFG2 0304 — — — — — — — — — — — — — — PCFG<17:16> 0000 33 ip ADSTAT 0306 — — — P12RDY — — — P8RDY P7RDY P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY P0RDY 0000 F T J ec ADBASE 0308 ADBASE<15:1> — 0000 3 hn ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00 0000 2 o G lo ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20 0000 g S y In ADCPC2 030E IRQEN5 PEND5 SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50 IRQEN4 PEND4 SWTRG4 TRGSRC44 TRGSRC43 TRGSRC42 TRGSRC41 TRGSRC40 0000 4 c. ADCPC3 0310 IRQEN7 PEND7 SWTRG7 TRGSRC74 TRGSRC73 TRGSRC72 TRGSRC71 TRGSRC70 IRQEN6 PEND6 SWTRG6 TRGSRC64 TRGSRC63 TRGSRC62 TRGSRC61 TRGSRC640 0000 0 6 ADCPC4 0312 — — — — — — — — IRQEN8 PEND8 SWTRG8 TRGSRC84 TRGSRC83 TRGSRC82 TRGSRC81 TRGSRC80 0000 / 6 ADCPC6 0316 — — — — — — — — IRQEN12 PEND12 SWTRG12 TRGSRC124 TRGSRC123 TRGSRC122 TRGSRC121 TRGSRC120 0000 0 6 ADCBUF0 0340 ADC Data Buffer 0 xxxx / 6 ADCBUF1 0342 ADC Data Buffer 1 xxxx 0 ADCBUF2 0344 ADC Data Buffer 2 xxxx 8 / ADCBUF3 0346 ADC Data Buffer 3 xxxx 6 1 ADCBUF4 0348 ADC Data Buffer 4 xxxx 0 ADCBUF5 034A ADC Data Buffer 5 xxxx a n ADCBUF6 034C ADC Data Buffer 6 xxxx d ADCBUF7 034E ADC Data Buffer 7 xxxx d ADCBUF8 0350 ADC Data Buffer 8 xxxx s P ADCBUF9 0352 ADC Data Buffer 9 xxxx I C ADCBUF10 0354 ADC Data Buffer 10 xxxx 3 ADCBUF11 0356 ADC Data Buffer 11 xxxx 3 ADCBUF12 0358 ADC Data Buffer 12 xxxx F J ADCBUF13 035A ADC Data Buffer 13 xxxx 6 4 ADCBUF14 035C ADC Data Buffer 14 xxxx G ADCBUF15 035E ADC Data Buffer 15 xxxx S ADCBUF16 0360 ADC Data Buffer 16 xxxx 4 0 ADCBUF17 0362 ADC Data Buffer 17 xxxx 6 DS ADCBUF24 0370 ADC Data Buffer 24 xxxx /6 70 ADCBUF25 0372 ADC Data Buffer 25 xxxx 0 0 6 05 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /6 9 1 0 F -p 8 ag /6 e 1 8 0 5

D TABLE 4-34: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS606 AND dsPIC33FJ64GS606 DEVICES d S7 s 0 P 0 File SFR All 05 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 9 1 3 F ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0 0003 -p 3 a ADPCFG 0302 PCFG<15:0> 0000 F g e J 8 ADSTAT 0306 — — — P12RDY — — — — P7RDY P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY P0RDY 0000 3 6 ADBASE 0308 ADBASE<15:1> — 0000 2 G ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00 0000 S ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20 0000 4 ADCPC2 030E IRQEN5 PEND5 SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50 IRQEN4 PEND4 SWTRG4 TRGSRC44 TRGSRC43 TRGSRC42 TRGSRC41 TRGSRC40 0000 0 6 ADCPC3 0310 IRQEN7 PEND7 SWTRG7 TRGSRC74 TRGSRC73 TRGSRC72 TRGSRC71 TRGSRC70 IRQEN6 PEND6 SWTRG6 TRGSRC64 TRGSRC63 TRGSRC62 TRGSRC61 TRGSRC640 0000 / 6 ADCPC6 0316 — — — — — — — — IRQEN12 PEND12 SWTRG12 TRGSRC124 TRGSRC123 TRGSRC122 TRGSRC121 TRGSRC120 0000 0 6 ADCBUF0 0340 ADC Data Buffer 0 xxxx / 6 ADCBUF1 0342 ADC Data Buffer 1 xxxx 0 ADCBUF2 0344 ADC Data Buffer 2 xxxx 8 / ADCBUF3 0346 ADC Data Buffer 3 xxxx 6 1 ADCBUF4 0348 ADC Data Buffer 4 xxxx 0 ADCBUF5 034A ADC Data Buffer 5 xxxx a n ADCBUF6 034C ADC Data Buffer 6 xxxx d ADCBUF7 034E ADC Data Buffer 7 xxxx d ADCBUF8 0350 ADC Data Buffer 8 xxxx s P ADCBUF9 0352 ADC Data Buffer 9 xxxx I C ADCBUF10 0354 ADC Data Buffer 10 xxxx 3 ADCBUF11 0356 ADC Data Buffer 11 xxxx 3 ADCBUF12 0358 ADC Data Buffer 12 xxxx F J ADCBUF13 035A ADC Data Buffer 13 xxxx 6 ADCBUF14 035C ADC Data Buffer 14 xxxx 4 G  2 ADCBUF15 035E ADC Data Buffer 15 xxxx S 0 0 ADCBUF24 0370 ADC Data Buffer 24 xxxx 4 9-20 ADCBUF25 0372 ADC Data Buffer 25 xxxx 06 14 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 TABLE 4-35: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES 2 0 09-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0 0003 P M I ic ADPCFG 0302 PCFG<15:0> 0000 C roch ADSTAT 0306 — — — P12RDY — — — — P7RDY P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY P0RDY 0000 33 ip ADBASE 0308 ADBASE<15:1> — 0000 F T J ec ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00 0000 3 hn ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20 0000 2 o G lo ADCPC2 030E IRQEN5 PEND5 SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50 IRQEN4 PEND4 SWTRG4 TRGSRC44 TRGSRC43 TRGSRC42 TRGSRC41 TRGSRC40 0000 g S y In ADCPC3 0310 IRQEN7 PEND7 SWTRG7 TRGSRC74 TRGSRC73 TRGSRC72 TRGSRC71 TRGSRC70 IRQEN6 PEND6 SWTRG6 TRGSRC64 TRGSRC63 TRGSRC62 TRGSRC61 TRGSRC640 0000 4 c. ADCBUF0 0340 ADC Data Buffer 0 xxxx 0 6 ADCBUF1 0342 ADC Data Buffer 1 xxxx / 6 ADCBUF2 0344 ADC Data Buffer 2 xxxx 0 6 ADCBUF3 0346 ADC Data Buffer 3 xxxx / 6 ADCBUF4 0348 ADC Data Buffer 4 xxxx 0 ADCBUF5 034A ADC Data Buffer 5 xxxx 8 / ADCBUF6 034C ADC Data Buffer 6 xxxx 6 1 ADCBUF7 034E ADC Data Buffer 7 xxxx 0 ADCBUF8 0350 ADC Data Buffer 8 xxxx a n ADCBUF9 0352 ADC Data Buffer 9 xxxx d ADCBUF10 0354 ADC Data Buffer 10 xxxx d ADCBUF11 0356 ADC Data Buffer 11 xxxx s P ADCBUF12 0358 ADC Data Buffer 12 xxxx I C ADCBUF13 035A ADC Data Buffer 13 xxxx 3 ADCBUF14 035C ADC Data Buffer 14 xxxx 3 ADCBUF15 035E ADC Data Buffer 15 xxxx F J Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 4 G S 4 0 6 D / S 6 7 0 0 0 6 05 /6 9 1 0 F -p 8 ag /6 e 1 8 0 7

D TABLE 4-36: DMA REGISTER MAP d S7 s 0 P 0 File SFR All 05 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 9 1F DMA0CON 0380 CHEN SIZE DIR HALF NULLW — — — — — AMODE1 AMODE0 — — MODE1 MODE0 0000 3 -p 3 a DMA0REQ 0382 FORCE — — — — — — — — IRQSEL6 IRQSEL5 IRQSEL4 IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0 007F F g e J 8 DMA0STA 0384 STA<15:0> 0000 3 8 DMA0STB 0386 STB<15:0> 0000 2 G DMA0PAD 0388 PAD<15:0> 0000 S DMA0CNT 038A — — — — — — CNT<9:0> 0000 4 DMA1CON 038C CHEN SIZE DIR HALF NULLW — — — — — AMODE1 AMODE0 — — MODE1 MODE0 0000 0 6 DMA1REQ 038E FORCE — — — — — — — — IRQSEL6 IRQSEL5 IRQSEL4 IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0 007F / 6 DMA1STA 0390 STA<15:0> 0000 0 6 DMA1STB 0392 STB<15:0> 0000 / 6 DMA1PAD 0394 PAD<15:0> 0000 0 DMA1CNT 0396 — — — — — — CNT<9:0> 0000 8 / DMA2CON 0398 CHEN SIZE DIR HALF NULLW — — — — — AMODE1 AMODE0 — — MODE1 MODE0 0000 6 1 DMA2REQ 039A FORCE — — — — — — — — IRQSEL6 IRQSEL5 IRQSEL4 IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0 007F 0 DMA2STA 039C STA<15:0> 0000 a n DMA2STB 039E STB<15:0> 0000 d DMA2PAD 03A0 PAD<15:0> 0000 d DMA2CNT 03A2 — — — — — — CNT<9:0> 0000 s P DMA3CON 03A4 CHEN SIZE DIR HALF NULLW — — — — — AMODE1 AMODE0 — — MODE1 MODE0 0000 I C DMA3REQ 03A6 FORCE — — — — — — — — IRQSEL6 IRQSEL5 IRQSEL4 IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0 007F 3 DMA3STA 03A8 STA<15:0> 0000 3 DMA3STB 03AA STB<15:0> 0000 F J DMA3PAD 03AC PAD<15:0> 0000 6 DMA3CNT 03AE — — — — — — CNT<9:0> 0000 4 G  2 DMACS0 03E0 — — — — PWCOL3 PWCOL2 PWCOL1 PWCOL0 — — — — XWCOL3 XWCOL2 XWCOL1 XWCOL0 0000 S 0 0 DMACS1 03E2 — — — — LSTCH3 LSTCH2 LSTCH1 LSTCH0 — — — — PPST3 PPST2 PPST1 PPST0 0F00 4 9-20 DSADR 03E4 DSADR<15:0> 0000 06 14 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 TABLE 4-37: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 0 OR 1 2 0 09-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 C1CTRL1 0600 — — CSIDL ABAT — REQOP2 REQOP1 REQOP0 OPMODE2 OPMODE1 OPMODE0 — CANCAP — — WIN 0480 P M I ic C1CTRL2 0602 — — — — — — — — — — — DNCNT<4:0> 0000 C ro C1VEC 0604 — — — FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 — ICODE6 ICODE5 ICODE4 ICODE3 ICODE2 ICODE1 ICODE0 0000 3 ch 3 ip C1FCTRL 0606 DMABS2 DMABS1 DMABS0 — — — — — — — — FSA4 FSA3 FSA2 FSA1 FSA0 0000 F Tec C1FIFO 0608 — — FBP5 FBP4 FBP3 FBP2 FBP1 FBP0 — — FNRB5 FNRB4 FNRB3 FNRB2 FNRB1 FNRB0 0000 J3 hn C1INTF 060A — — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000 2 olo C1INTE 060C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000 G gy C1EC 060E TERRCNT7 TERRCNT6 TERRCNT5 TERRCNT4 TERRCNT3 TERRCNT2 TERRCNT1 TERRCNT0 RERRCNT7 RERRCNT6 RERRCNT5 RERRCNT4 RERRCNT3 RERRCNT2 RERRCNT1 RERRCNT0 0000 S Inc C1CFG1 0610 — — — — — — — — SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0000 40 . C1CFG2 0612 — WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 0000 6 / C1FEN1 0614 FLTEN<15:0> FFFF 6 0 C1FMSKSEL1 0618 F7MSK1 F7MSK0 F6MSK1 F6MSK0 F5MSK1 F5MSK0 F4MSK1 F4MSK0 F3MSK1 F3MSK0 F2MSK1 F2MSK0 F1MSK1 F1MSK0 F0MSK1 F0MSK0 0000 6 C1FMSKSEL2 061A F15MSK1 F15MSK0 F14MSK1 F14MSK0 F13MSK1 F13MSK0 F12MSK1 F12MSK1 F11MSK1 F11MSK0 F10MSK1 F10MSK0 F9MSK1 F9MSK0 F8MSK1 F8MSK0 0000 /6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 8 / 6 1 TABLE 4-38: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 0 0 File SFR All a Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n Name Addr Resets d 0600- See definition when WIN = x d 061E s C1RXFUL1 0620 RXFUL<15:0> 0000 P I C1RXFUL2 0622 RXFUL<31:16> 0000 C 3 C1RXOVF1 0628 RXOVF<15:0> 0000 3 C1RXOVF2 062A RXOVF<31:16> 0000 F J C1TR01CON 0630 TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI1 TX1PRI0 TXEN0 TXABT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI1 TX0PRI0 0000 6 C1TR23CON 0632 TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI1 TX3PRI0 TXEN2 TXABT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI1 TX2PRI0 0000 4 G C1TR45CON 0634 TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI1 TX5PRI0 TXEN4 TXABT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI1 TX4PRI0 0000 S C1TR67CON 0636 TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI1 TX7PRI0 TXEN6 TXABT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI1 TX6PRI0 0000 4 C1RXD 0640 ECAN1 Received Data Word Register xxxx 0 6 D C1TXD 0642 ECAN1 Transmit Data Word Register xxxx / S 6 7 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 0 0 6 05 /6 9 1 0 F -p 8 ag /6 e 1 8 0 9

D d S7 TABLE 4-39: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 1 s 0 P 0 File SFR All 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I 5 Name Addr Resets C 9 1 3 F-pa 0066010E- See definition when WIN = x 3F g e C1BUFPNT1 0620 F3BP3 F3BP2 F3BP1 F3BP0 F2BP3 F2BP2 F2BP1 F2BP0 F1BP3 F1BP2 F1BP1 F1BP0 F0BP3 F0BP2 F0BP1 F0BP0 0000 J 9 3 0 C1BUFPNT2 0622 F7BP3 F7BP2 F7BP1 F7BP0 F6BP3 F6BP2 F6BP1 F6BP0 F5BP3 F5BP2 F5BP1 F5BP0 F4BP3 F4BP2 F4BP1 F4BP0 0000 2 C1BUFPNT3 0624 F11BP3 F11BP2 F11BP1 F11BP0 F10BP3 F10BP2 F10BP1 F10BP0 F9BP3 F9BP2 F9BP1 F9BP0 F8BP3 F8BP2 F8BP1 F8BP0 0000 G S C1BUFPNT4 0626 F15BP3 F15BP2 F15BP1 F15BP0 F14BP3 F14BP2 F14BP1 F14BP0 F13BP3 F13BP2 F13BP1 F13BP0 F12BP3 F12BP2 F12BP1 F12BP0 0000 4 C1RXM0SID 0630 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — MIDE — EID17 EID16 xxxx 0 6 C1RXM0EID 0632 EID<15:0> xxxx / 6 C1RXM1SID 0634 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — MIDE — EID17 EID16 xxxx 0 C1RXM1EID 0636 EID<15:0> xxxx 6 / C1RXM2SID 0638 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — MIDE — EID17 EID16 xxxx 6 0 C1RXM2EID 063A EID<15:0> xxxx 8 / C1RXF0SID 0640 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx 6 1 C1RXF0EID 0642 EID<15:0> xxxx 0 C1RXF1SID 0644 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx a C1RXF1EID 0646 EID<15:0> xxxx n d C1RXF2SID 0648 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx d C1RXF2EID 064A EID<15:0> xxxx s C1RXF3SID 064C SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx P I C1RXF3EID 064E EID<15:0> xxxx C C1RXF4SID 0650 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx 3 3 C1RXF4EID 0652 EID<15:0> xxxx F J C1RXF5SID 0654 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx 6 C1RXF5EID 0656 EID<15:0> xxxx 4 G  C1RXF6SID 0658 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx 2 S 00 C1RXF6EID 065A EID<15:0> xxxx 4 9-20 C1RXF7SID 065C SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx 06 1 C1RXF7EID 065E EID<15:0> xxxx / 4 6 M C1RXF8SID 0660 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx 0 ic 6 roc C1RXF8EID 0662 EID<15:0> xxxx /6 hip C1RXF9SID 0664 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx 0 T C1RXF9EID 0666 EID<15:0> xxxx 8 ech C1RXF10SID 0668 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx /6 n 1 olo C1RXF10EID 066A EID<15:0> xxxx 0 g y C1RXF11SID 066C SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx Inc Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. .

 TABLE 4-39: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1<0>) = 1 (CONTINUED) 2 0 0 File SFR All 9-20 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets ds 14 C1RXF11EID 066E EID<15:0> xxxx P M I ic C1RXF12SID 0670 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx C roch C1RXF12EID 0672 EID<15:0> xxxx 33 ip C1RXF13SID 0674 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx F T J ec C1RXF13EID 0676 EID<15:0> xxxx 3 hn C1RXF14SID 0678 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx 2 o G lo C1RXF14EID 067A EID<15:0> xxxx g S y In C1RXF15SID 067C SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE — EID17 EID16 xxxx 4 c. C1RXF15EID 067E EID<15:0> xxxx 0 6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / 6 0 6 TABLE 4-40: ANALOG COMPARATOR CONTROL REGISTER MAP / 6 0 File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 8 Name Addr Resets / 6 CMPCON1 0540 CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000 1 0 CMPDAC1 0542 — — - — — — CMREF<9:0> 0000 a CMPCON2 0544 CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000 n CMPDAC2 0546 — — - — — — CMREF<9:0> 0000 d CMPCON3 0548 CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000 d s CMPDAC3 054A — — - — — — CMREF<9:0> 0000 P CMPCON4 054C CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000 IC CMPDAC4 054E — — — — — — CMREF<9:0> 0000 3 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. F J 6 4 G S 4 0 6 D / S 6 7 0 0 0 6 05 /6 9 1 0 F -p 8 ag /6 e 1 9 0 1

D TABLE 4-41: PORTA REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES d S7 s 0 P 0 File SFR All 05 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 9 1 3 F TRISA 02C0 TRISA<15:14> — — — TRISA<10:9> — TRISA<7:0> C6FF -p 3 a PORTA 02C2 RA<15:14> — — — RA<10:9> — RA<7:0> xxxx F g e J 9 LATA 02C4 LATA<15:14> — — — LATA<10:9> — LATA<7:0> 0000 3 2 ODCA 02C6 ODCA<15:14> — — — ODCA<10:9> — — — ODCA<5:4> — — ODCA<1:0> 0000 2 G Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. S 4 0 TABLE 4-42: PORTA REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES 6 / 6 File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Name Addr Resets 6 / TRISA 02C0 TRISA<15:14> — — — TRISA<10:9> — — — — — — — — — C600 6 0 PORTA 02C2 RA<15:14> — — — RA<10:9> — — — — — — — — — xxxx 8 LATA 02C4 LATA<15:14> — — — LATA<10:9> — — — — — — — — — 0000 /6 ODCA 02C6 ODCA<15:14> — — — ODCA<10:9> — — — — — — — — — 0000 1 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. a n d TABLE 4-43: PORTB REGISTER MAP d s File SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All P Name Addr Resets I C TRISB 02C8 TRISB<15:0> FFFF 3 PORTB 02CA RB<15:0> xxxx 3 F LATB 02CC LATB<15:0> 0000 J Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 4 G  2 S 0 TABLE 4-44: PORTC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES 0 4 9-20 File SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 06 1 Name Addr Resets / 4 6 M TRISC 02D0 TRISC<15:12> — — — — — — — TRISC<4:1> — F01E 0 ic 6 roc PORTC 02D2 RC<15:12> — — — — — — — RC<4:1> — xxxx /6 h ip LATC 02D4 LATC<15:12> — — — — — — — LATC<4:1> — 0000 0 Tec Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 8/6 h n 1 o lo 0 g y In c .

 TABLE 4-45: PORTC REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES 2 0 09-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 TRISC 02D0 TRISC<15:12> — — — — — — — — — TRISC<2:1> — F006 P M I ic PORTC 02D2 RC<15:12> — — — — — — — — — RC<2:1> — xxxx C roch LATC 02D4 LATC<15:12> — — — — — — — — — LATC<2:1> — 0000 33 ip Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. F T J ec 3 hno TABLE 4-46: PORTC REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES 2G lo g S y File SFR All In Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 4 c 0 . 6 TRISC 02D0 TRISC<15:12> — — — — — — — — — — — — F000 / 6 PORTC 02D2 RC<15:12> — — — — — — — — — — — — xxxx 0 LATC 02D4 LATC<15:12> — — — — — — — — — — — — 0000 6 / Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 0 8 / TABLE 4-47: PORTD REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES 6 1 0 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts a n TRISD 02D8 TRISD<15:0> FFFF d PORTD 02DA RD<15:0> xxxx d s LATD 02DC LATD<15:0> 0000 P ODCD 02DE ODCD<15:0> 0000 I C Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 3 F TABLE 4-48: PORTD REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES J 6 4 File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 G Name Addr Resets S TRISD 02D8 — — — — TRISD<11:0> 0FFF 4 0 PORTD 02DA — — — — RD<11:0> xxxx 6 DS LATD 02DC — — — — LATD<11:0> 0000 /6 70 ODCD 02DE — — — — ODCD<11:0> 0000 0 0 6 05 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /6 9 1 0 F -p 8 ag /6 e 1 9 0 3

D TABLE 4-49: PORTE REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES d S7 s 0005 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 9 1F TRISE 02E0 — — — — — — TRISE<9:0> 03FF 3 -p 3 a PORTE 02E2 — — — — — — RE<9:0> xxxx F g e 9 LATE 02E4 — — — — — — LATE<9:0> 0000 J3 4 ODCE 02E6 — — — — — — — — ODCE<7:0> 0000 2 G Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. S 4 0 TABLE 4-50: PORTE REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES 6 / 6 File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Name Addr Resets 6 / TRISE 02E0 — — — — — — — — TRISE<7:0> 00FF 6 0 PORTE 02E2 — — — — — — — — RE<7:0> xxxx 8 LATE 02E4 — — — — — — — — LATE<7:0> 0000 /6 ODCE 02E6 — — — — — — — — ODCE<7:0> 0000 1 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. a n d TABLE 4-51: PORTF REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES d s File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P Name Addr Resets I C TRISF 02E8 — — TRISF<13:12> — — — TRISF<8:0> 30FF 3 PORTF 02EA — — RF<13:12> — — — RF<8:0> xxxx 3 F LATF 02EC — — LATF<13:12> — — — LATF<8:0> 0000 J ODCF 02EE — — ODCF<13:12> — — — ODCF<8:6> — — ODCF<3:1> — 0000 6 4 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G  2 S 0 0 4 9-20 TABLE 4-52: PORTF REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES 06 14 M NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts /60 ic 6 roc TRISF 02E8 — — — — — — — TRISF<8:0> 01FF /6 hip PORTF 02EA — — — — — — — RF<8:0> xxxx 0 Tec LATF 02EC — — — — — — — LATF<8:0> 0000 8/6 h ODCF 02EE — — — — — — — ODCF<8:6> — — ODCF<3:1> — 0000 n 1 o lo Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 g y In c .

 TABLE 4-53: PORTF REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES 2 0 09-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 TRISF 02E8 — — — — — — — — — TRISF<6:0> 007F P M I ic PORTF 02EA — — — — — — — — — RF<6:0> xxxx C roch LATF 02EC — — — — — — — — — LATF<6:0> 0000 33 ip ODCF 02EE — — — — — — — — — ODCF6 — — ODCF<3:1> — 0000 F T J ec Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 hn 2 o G lo g TABLE 4-54: PORTG REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES S y In 4 c File SFR All 0 . Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets 6 / 6 TRISG 02F0 TRISG<15:12 — — TRISG<9:6> — — TRISG<3:0> F3CF 0 PORTG 02F2 RG<15:12> — — RG<9:6> — — RG<3:0> xxxx 6 / LATG 02F4 LATG<15:12> — — LATG<9:6> — — LATG<3:0> 0000 6 0 ODCG 02F6 ODCG<15:12> — — ODCG<9:6> — — ODCG<3:0> 0000 8 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /6 1 0 TABLE 4-55: PORTG REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES a n File SFR All d Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets d s TRISG 02F0 — — — — — — TRISG<9:6> — — TRISG<3:0> 03CF P PORTG 02F2 — — — — — — RG<9:6> — — RG<3:0> xxxx I C LATG 02F4 — — — — — — LATG<9:6> — — LATG<3:0> 0000 3 ODCG 02F6 — — — — — — ODCG<9:6> — — ODCG<3:0> 0000 3 F Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. J 6 4 G TABLE 4-56: PORTG REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES S File SFR All 4 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 6 DS TRISG 02F0 — — — — — — TRISG<9:6> — — TRISG<3:2> — — 03CC /6 70 PORTG 02F2 — — — — — — RG<9:6> — — RG<3:2> — — xxxx 0 0 6 05 LATG 02F4 — — — — — — LATG<9:6> — — LATG<3:2> — — 0000 /6 9 1 ODCG 02F6 — — — — — — ODCG<9:6> — — ODCG<3:2> — — 0000 0 F -pag Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 8/6 e 1 9 0 5

D TABLE 4-57: SYSTEM CONTROL REGISTER MAP d S7 s 0005 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 9 1F RCON 0740 TRAPR IOPUWR — — — — — VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1) 3 -pa OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK — LOCK — CF — — OSWEN 0300(2) 3F g e 9 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN FRCDIV2 FRCDIV1 FRCDIV0 PLLPOST1 PLLPOST0 — PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0 0040 J3 6 PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0030 2 G OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000 S REFOCON 074E ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000 4 ACLKCON 0750 ENAPLL APLLCK SELACLK — — APSTSCLR2 APSTSCLR1 APSTSCLR0 ASRCSEL FRCSEL — — — — — — 2300 0 6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / Note1: The RCON register Reset values are dependent on the type of Reset. 6 0 2: The OSCCON register Reset values are dependent on the FOSCx Configuration bits and on the type of Reset. 6 / 6 0 TABLE 4-58: NVM REGISTER MAP 8 / 6 File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 Name Addr Resets 0 NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) a n NVMKEY 0766 — — — — — — — — NVMKEY<7:0> 0000 d Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d Note1: The Reset value shown is for POR only. The value on other Reset states is dependent on the state of the memory write or erase operations at the time of Reset. s P I C TABLE 4-59: PMD REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES 3 3 File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F Name Addr Resets J 6 PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD ADCMD 0000 4  PMD2 0772 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000 G 2 PMD3 0774 — — — — — CMPMD — — — — QEI2MD — — — I2C2MD — 0000 S 0 0 4 9-20 PPMMDD46 007777A6 PWM—8MD PWM—7MD PWM—6MD PWM—5MD PWM—4MD PWM—3MD PWM—2MD PWM—1MD —— —— —— —— REF—OMD —— —— —— 00000000 06 1 / 4 M PMD7 077C — — — — CMP4MD CMP3MD CMP2MD CMP1MD — — — — — — — PWM9MD 0000 60 ic Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

 TABLE 4-60: PMD REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES 2 0 09-20 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 14 M PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADCMD 0000 PI C ic PMD2 0772 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000 ro 3 ch PMD3 0774 — — — — — CMPMD — — — — QEI2MD — — — I2C2MD — 0000 3 ip PMD4 0776 — — — — — — — — — — — — REFOMD — — — 0000 F T J ec PMD6 077A PWM8MD PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD — — — — — — — — 0000 3 hn PMD7 077C — — — — CMP4MD CMP3MD CMP2MD CMP1MD — — — — — — — PWM9MD 0000 2 o G log Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. S y In 4 c 0 . TABLE 4-61: PMD REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES 6 / 6 File SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 0 Name Addr Resets 6 / PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD ADCMD 0000 6 0 PMD2 0772 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000 8 / PMD3 0774 — — — — — CMPMD — — — — QEI2MD — — — I2C2MD — 0000 6 1 PMD4 0776 — — — — — — — — — — — — REFOMD — — — 0000 0 PMD6 077A PWM8MD PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD — — — — — — — — 0000 a PMD7 077C — — — — CMP4MD CMP3MD CMP2MD CMP1MD — — — — — — — — 0000 n d Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d s P TABLE 4-62: PMD REGISTER MAP FOR dsPIC33FJ32GS608 DEVICES I C File SFR All 3 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets 3 F PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADCMD 0000 J 6 PMD2 0772 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000 4 PMD3 0774 — — — — — CMPMD — — — — QEI2MD — — — I2C2MD — 0000 G PMD4 0776 — — — — — — — — — — — — REFOMD — — — 0000 S 4 PMD6 077A PWM8MD PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD — — — — — — — — 0000 0 PMD7 077C — — — — CMP4MD CMP3MD CMP2MD CMP1MD — — — — — — — — 0000 6 D / S Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 7 0 0 0 6 05 /6 9 1 0 F -p 8 ag /6 e 1 9 0 7

DS7 TABLE 4-63: PMD REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES ds 0 P 0 File SFR All 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I 5 Name Addr Resets C 9 1 3 F-p PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD ADCMD 0000 3 ag PMD2 0772 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000 F e J 9 PMD3 0774 — — — — — CMPMD — — — — QEI2MD — — — I2C2MD — 0000 3 8 PMD4 0776 — — — — — — — — — — — — REFOMD — — — 0000 2 G PMD6 077A — — PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD — — — — — — — — 0000 S PMD7 077C — — — — CMP4MD CMP3MD CMP2MD CMP1MD — — — — — — — — 0000 4 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 / 6 0 TABLE 4-64: PMD REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES 6 / 6 File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Name Addr Resets 8 / PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADCMD 0000 6 1 PMD2 0772 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000 0 PMD3 0774 — — — — — CMPMD — — — — QEI2MD — — — I2C2MD — 0000 a PMD4 0776 — — — — — — — — — — — — REFOMD — — — 0000 n d PMD6 077A — — PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD — — — — — — — — 0000 d PMD7 077C — — — — CMP4MD CMP3MD CMP2MD CMP1MD — — — — — — — — 0000 s Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P I C 3 TABLE 4-65: PMD REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES 3 F File SFR All J Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets 6 4  PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADCMD 0000 G 2 PMD2 0772 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000 S 0 0 4 9-20 PPMMDD34 00777746 —— —— —— —— —— —— —— —— —— —— QE—I2MD —— REF—OMD —— I2C—2MD —— 00000000 06 1 / 4 M PMD6 077A — — PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD — — — — — — — — 0000 60 ic Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.2.7 SOFTWARE STACK 4.3 Instruction Addressing Modes In addition to its use as a Working register, the W15 The addressing modes shown in Table4-66 form the register in the dsPIC33FJ32GS406/606/608/610 and basis of the addressing modes optimized to support the dsPIC33FJ64GS406/606/608/610 devices is also used specific features of individual instructions. The as a Software Stack Pointer. The Stack Pointer always addressing modes provided in the MAC class of points to the first available free word and grows from instructions differ from those in the other instruction lower to higher addresses. It predecrements for stack types. pops and post-increments for stack pushes, as shown in Figure4-6. For a PC push during any CALL instruc- 4.3.1 FILE REGISTER INSTRUCTIONS tion, the MSb of the PC is zero-extended before the Most file register instructions use a 13-bit address field push, ensuring that the MSb is always clear. (f) to directly address data present in the first Note: A PC push during exception processing 8192bytes of data memory (Near Data Space). Most concatenates the SRL register to the MSb file register instructions employ a Working register, W0, of the PC prior to the push. which is denoted as WREG in these instructions. The destination is typically either the same file register or The Stack Pointer Limit register (SPLIM) associated WREG (with the exception of the MUL instruction), with the Stack Pointer sets an upper address boundary which writes the result to a register or register pair. The for the stack. SPLIM is uninitialized at Reset. As is the MOV instruction allows additional flexibility and can case for the Stack Pointer, SPLIM<0> is forced to ‘0’ access the entire data space. because all stack operations must be word-aligned. 4.3.2 MCU INSTRUCTIONS Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is The three-operand MCU instructions are of the form: compared with the value in SPLIM. If the contents of Operand 3 = Operand 1 <function> Operand 2 the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error where Operand 1 is always a Working register (that is, trap will not occur. The stack error trap will occur on a the addressing mode can only be register direct), which subsequent push operation. For example, to cause a is referred to as Wb. Operand 2 can be a W register, stack error trap when the stack grows beyond address fetched from data memory, or a 5-bit literal. The result 0x1800 in RAM, initialize the SPLIM with the value, location can be either a W register or a data memory 0x17FE. location. The following addressing modes are supported by MCU instructions: Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to • Register Direct be less than 0x0800. This prevents the stack from • Register Indirect interfering with the Special Function Register (SFR) • Register Indirect Post-Modified space. • Register Indirect Pre-Modified • 5-Bit or 10-Bit Literal A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. Note: Not all instructions support all the addressing modes given above. Individual FIGURE 4-6: CALL STACK FRAME instructions can support different subsets of these addressing modes. 0x0000 15 0 d waress Todr s Ad ower PC<15:0> W15 (before CALL) Grgh 000000000 PC<22:16> ck Hi <Free Word> W15 (after CALL) a St POP : [--W15] PUSH: [W15++]  2009-2014 Microchip Technology Inc. DS7000591F-page 99

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 4-66: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. 4.3.3 MOVE AND ACCUMULATOR 4.3.4 MAC INSTRUCTIONS INSTRUCTIONS The dual source operand DSP instructions (CLR, ED, Move instructions and the DSP accumulator class of EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred instructions provide a greater degree of addressing to as MAC instructions, use a simplified set of addressing flexibility than other instructions. In addition to the modes to allow the user application to effectively addressing modes supported by most MCU manipulate the Data Pointers through Register Indirect instructions, move and accumulator instructions also tables. support Register Indirect with Register Offset The two-source operand, prefetch registers must be Addressing mode, also referred to as Register Indexed members of the set: {W8, W9, W10, W11}. For data mode. reads, W8 and W9 are always directed to the X RAGU, Note: For the MOV instructions, the addressing and W10 and W11 are always directed to the Y AGU. mode specified in the instruction can differ The Effective Addresses generated (before and after for the source and destination EA. How- modification) must, therefore, be valid addresses within ever, the 4-bit Wb (Register Offset) field is X data space for W8 and W9 and Y data space for W10 shared by both source and destination and W11. (but typically only used by one). Note: Register Indirect with Register Offset In summary, the following addressing modes are Addressing mode is available only for W9 supported by move and accumulator instructions: (in X space) and W11 (in Y space). • Register Direct In summary, the following addressing modes are • Register Indirect supported by the MAC class of instructions: • Register Indirect Post-Modified • Register Indirect • Register Indirect Pre-Modified • Register Indirect Post-Modified by 2 • Register Indirect with Register Offset (Indexed) • Register Indirect Post-Modified by 4 • Register Indirect with Literal Offset • Register Indirect Post-Modified by 6 • 8-Bit Literal • Register Indirect with Register Offset (Indexed) • 16-Bit Literal 4.3.5 OTHER INSTRUCTIONS Note: Not all instructions support all the addressing modes given above. Individual Besides the addressing modes outlined previously, some instructions may support different subsets instructions use literal constants of various sizes. For of these addressing modes. example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. DS7000591F-page 100  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.4 Modulo Addressing 4.4.1 START AND END ADDRESS Modulo Addressing mode is a method used to provide The Modulo Addressing scheme requires that a an automated means to support circular data buffers starting and ending address be specified and loaded using hardware. The objective is to remove the need into the 16-bit Modulo Buffer Address registers: for software to perform data address boundary checks XMODSRT, XMODEND, YMODSRT and YMODEND when executing tightly looped code, as is typical in (see Table4-1). many DSP algorithms. Note: Y Space Modulo Addressing EA Modulo Addressing can operate in either data or program calculations assume word-sized data space (since the Data Pointer mechanism is essentially (LSb of every EA is always clear). the same for both). One circular buffer can be supported The length of a circular buffer is not directly specified. It is in each of the X (which also provides the pointers into determined by the difference between the corresponding program space) and Y data spaces. Modulo Addressing start and end addresses. The maximum possible length can operate on any W Register Pointer. However, it is not of the circular buffer is 32K words (64Kbytes). advisable to use W14 or W15 for Modulo Addressing since these two registers are used as the Stack Frame 4.4.2 W ADDRESS REGISTER Pointer and Stack Pointer, respectively. SELECTION In general, any particular circular buffer can be The Modulo and Bit-Reversed Addressing Control configured to operate in only one direction as there are register, MODCON<15:0>, contains enable flags as certain restrictions on the buffer start address (for incre- well as a W register field to specify the W Address menting buffers), or end address (for decrementing registers. The XWM and YWM fields select the buffers), based upon the direction of the buffer. registers that will operate with Modulo Addressing: The only exception to the usage restrictions is for • If XWM = 15, XRAGU and X WAGU Modulo buffers that have a power-of-two length. As these Addressing is disabled. buffers satisfy the start and end address criteria, they • If YWM = 15, Y AGU Modulo Addressing is disabled. can operate in a bidirectional mode (that is, address boundary checks are performed on both the lower and The X Address Space Pointer W register (XWM), to upper address boundaries). which Modulo Addressing is to be applied, is stored in MODCON<3:0> (see Table4-1). Modulo Addressing is enabled for X data space when XWM is set to any value other than ‘15’ and the XMODEN bit is set at MODCON<15>. The Y Address Space Pointer W register (YWM) to which Modulo Addressing is to be applied is stored in MODCON<7:4>. Modulo Addressing is enabled for Y data space when YWM is set to any value other than ‘15’ and the YMODEN bit is set at MODCON<14>. FIGURE 4-7: MODULO ADDRESSING OPERATION EXAMPLE Byte MOV #0x1100, W0 Address MOV W0, XMODSRT ;set modulo start address MOV #0x1163, W0 MOV W0, MODEND ;set modulo end address 0x1100 MOV #0x8001, W0 MOV W0, MODCON ;enable W1, X AGU for modulo MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer 0x1163 DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 Words  2009-2014 Microchip Technology Inc. DS7000591F-page 101

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.4.3 MODULO ADDRESSING 4.5.1 BIT-REVERSED ADDRESSING APPLICABILITY IMPLEMENTATION Modulo Addressing can be applied to the Effective Bit-Reversed Addressing mode is enabled in any of Address (EA) calculation associated with any W these situations: register. Address boundaries check for addresses • BWMx bits (W register selection) in the MODCON equal to: register are any value other than ‘15’ (the stack • Upper boundary addresses for incrementing buffers cannot be accessed using Bit-Reversed • Lower boundary addresses for decrementing buffers Addressing) • The BREN bit is set in the XBREV register It is important to realize that the address boundaries check for addresses less than or greater than the upper • The addressing mode used is Register Indirect (for incrementing buffers) and lower (for decrementing with Pre-Increment or Post-Increment buffers) boundary addresses (not just equal to). If the length of a bit-reversed buffer is M = 2N bytes, Address changes can, therefore, jump beyond the last ‘N’ bits of the data buffer start address must boundaries and still be adjusted correctly. be zeros. Note: The modulo corrected Effective Address XB<14:0> is the Bit-Reversed Addressing modifier, or is written back to the register only when ‘pivot point,’ which is typically a constant. In the case of Pre-Modify or Post-Modify Addressing an FFT computation, its value is equal to half of the FFT mode is used to compute the Effective data buffer size. Address. When an address offset (such Note: All bit-reversed EA calculations assume as [W7 + W2]) is used, Modulo Addressing word-sized data (LSb of every EA is correction is performed but the contents of always clear). The XB value is scaled the register remain unchanged. accordingly to generate compatible (byte) addresses. 4.5 Bit-Reversed Addressing When enabled, Bit-Reversed Addressing is executed Bit-Reversed Addressing mode is intended to simplify only for Register Indirect with Pre-Increment or Post- data re-ordering for radix-2 FFT algorithms. It is Increment Addressing and word-sized data writes. It supported by the X AGU for data writes only. will not function for any other addressing mode or for The modifier, which can be a constant value or register byte-sized data and normal addresses are generated contents, is regarded as having its bit order reversed. The instead. When Bit-Reversed Addressing is active, the address source and destination are kept in normal order. W Address Pointer is always added to the address Thus, the only operand requiring reversal is the modifier. modifier (XB) and the offset associated with the Regis- ter Indirect Addressing mode is ignored. In addition, as word-sized data is a requirement, the LSb of the EA is ignored (and always clear). Note: Modulo Addressing and Bit-Reversed Addressing should not be enabled together. If an application attempts to do so, Bit-Reversed Addressing will assume priority when active for the X WAGU and X WAGU, and Modulo Addressing will be disabled. However, Modulo Addressing will continue to function in the X RAGU. If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the Bit-Reversed Pointer. DS7000591F-page 102  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE Se que ntial Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-67: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15  2009-2014 Microchip Technology Inc. DS7000591F-page 103

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.6 Interfacing Program and Data 4.6.1 ADDRESSING PROGRAM SPACE Memory Spaces Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is The dsPIC33FJ32GS406/606/608/610 and needed to create a 23-bit or 24-bit program address dsPIC33FJ64GS406/606/608/610 devices’ architecture from 16-bit data registers. The solution depends on the uses a 24-bit-wide program space and a 16-bit-wide interface method to be used. data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the For table operations, the 8-bit Table Page register program space. To use this data successfully, it must (TBLPAG) is used to define a 32Kword region within be accessed in a way that preserves the alignment of the program space. This is concatenated with a 16-bit information in both spaces. EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used Aside from normal execution, the dsPIC33FJ32GS406/ to determine if the operation occurs in the user memory 606/608/610 and dsPIC33FJ64GS406/606/608/610 (TBLPAG<7> = 0) or the configuration memory architecture provides two methods by which program (TBLPAG<7> = 1). space can be accessed during operation: For remapping operations, the 8-bit Program Space • Using table instructions to access individual bytes Visibility register (PSVPAG) is used to define a or words anywhere in the program space 16Kword page in the program space. When the Most • Remapping a portion of the program space into Significant bit of the EA is ‘1’, PSVPAG is concatenated the data space (Program Space Visibility) with the lower 15 bits of the EA to form a 23-bit program Table instructions allow an application to read or write space address. Unlike table operations, this limits to small areas of the program memory. This capability remapping operations strictly to the user memory area. makes the method ideal for accessing data tables that Table4-68 and Figure4-9 show how the program EA is need to be updated periodically. It also allows access created for table operations and remapping accesses to all bytes of the program word. The remapping from the data EA. Here, P<23:0> refers to a program method allows an application to access a large block of space word and D<15:0> refers to a data space word. data on a read-only basis, which is ideal for look-ups from a large table of static data. The application can only access the least significant word of the program word. TABLE 4-68: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 (Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0>(1) (Block Remap/Read) 0 xxxx xxxx xxx xxxx xxxx xxxx Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. DS7000591F-page 104  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 0 23 Bits EA 1/0 Table Operations(2) 1/0 TBLPAG 8 Bits 16 Bits 24 Bits Select 1 EA 0 Program Space Visibility(1) 0 PSVPAG (Remapping) 8 Bits 15 Bits 23 Bits User/Configuration Byte Select Space Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table Read operations are permitted in the configuration memory space.  2009-2014 Microchip Technology Inc. DS7000591F-page 105

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.6.2 DATA ACCESS FROM PROGRAM - In Byte mode, either the upper or lower byte MEMORY USING TABLE of the lower program word is mapped to the INSTRUCTIONS lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower The TBLRDL and TBLWTL instructions offer a direct byte is selected when it is ‘0’. method of reading or writing the lower word of any • TBLRDH (Table Read High): address within the program space without going through data space. The TBLRDH and TBLWTH - In Word mode, this instruction maps the entire instructions are the only method to read or write the upper word of a program address (P<23:16>) upper 8bits of a program space word as data. to a data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’. The PC is incremented by two for each successive - In Byte mode, this instruction maps the upper 24-bit program word. This allows program memory or lower byte of the program word to D<7:0> addresses to directly map to data space addresses. Pro- of the data address, in the TBLRDL gram memory can thus be regarded as two 16-bit-wide instruction. The data is always ‘0’ when word address spaces, residing side by side, each with the upper ‘phantom’ byte is selected the same address range. TBLRDL and TBLWTL access (Byte Select= 1). the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the Similarly, two table instructions, TBLWTH and TBLWTL, upper data byte. are used to write individual bytes or words to a program space address. The details of their operation are Two table instructions are provided to move byte or explained in Section5.0 “Flash Program Memory”. word-sized (16-bit) data to and from program space. Both function as either byte or word operations. For all table operations, the area of program memory space to be accessed is determined by the Table Page • TBLRDL (Table Read Low): register (TBLPAG). TBLPAG covers the entire program - In Word mode, this instruction maps the memory space of the device, including user and lower word of the program space location configuration spaces. When TBLPAG<7> = 0, the table (P<15:0>) to a data address (D<15:0>). page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space. FIGURE 4-10: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG 02 23 15 0 0x000000 23 16 8 0 00000000 00000000 0x020000 00000000 0x030000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 0x800000 Only read operations are shown; write operations are also valid in the user memory area. DS7000591F-page 106  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 4.6.3 READING DATA FROM PROGRAM 24-bit program word are used to contain the data. The MEMORY USING PROGRAM SPACE upper 8 bits of any program space location used as VISIBILITY data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible The upper 32Kbytes of data space may optionally be issues should the area of code ever be accidentally mapped into any 16Kword page of the program space. executed. This option provides transparent access to stored constant data from the data space without the need to Note: PSV access is temporarily disabled during use special instructions (such as TBLRDL/H). Table Reads/Writes. Program space access through the data space occurs For operations that use PSV and are executed outside if the Most Significant bit of the data space EA is ‘1’ and a REPEAT loop, the MOV and MOV.D instructions require program space visibility is enabled by setting the PSV one instruction cycle in addition to the specified bit in the Core Control register (CORCON<2>). The execution time. All other instructions require two location of the program memory space to be mapped instruction cycles in addition to the specified execution into the data space is determined by the Program time. Space Visibility Page register (PSVPAG). This 8-bit For operations that use PSV and are executed inside a register defines any one of 256 possible pages of REPEAT loop, these instances require two instruction 16Kwords in program space. In effect, PSVPAG cycles in addition to the specified execution time of the functions as the upper 8 bits of the program memory instruction: address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each • Execution in the first iteration program memory word, the lower 15 bits of data space • Execution in the last iteration addresses directly map to the lower 15 bits in the • Execution prior to exiting the loop due to an corresponding program space addresses. interrupt Data reads to this area add a cycle to the instruction • Execution upon re-entering the loop after an being executed, since two program memory fetches interrupt is serviced are required. Any other iteration of the REPEAT loop will allow the Although each data space address 8000h and higher instruction using PSV to access data, to execute in a maps directly into a corresponding program memory single cycle. address (see Figure4-11), only the lower 16 bits of the FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space Data Space PSVPAG 23 15 0 02 0x000000 0x0000 Data EA<14:0> 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory 0x8000 space... PSV Area ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 0x800000  2009-2014 Microchip Technology Inc. DS7000591F-page 107

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS7000591F-page 108  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 5.0 FLASH PROGRAM MEMORY pin pairs: PGEC1/PGED1, PGEC2/PGED2 or PGEC3/ PGED3), and three other lines for power (VDD), ground Note1: This data sheet summarizes the features (VSS) and Master Clear (MCLR). This allows customers of the dsPIC33FJ32GS406/606/608/610 to manufacture boards with unprogrammed devices and dsPIC33FJ64GS406/606/608/610 and then program the Digital Signal Controller (DSC) families of devices. It is not intended to just before shipping the product. This also allows the be a comprehensive reference source. most recent firmware or a custom firmware to be To complement the information in this programmed. data sheet, refer to “Flash Program- RTSP is accomplished using TBLRD (Table Read) and ming” (DS70191) in the “dsPIC33/PIC24 TBLWT (Table Write) instructions. With RTSP, the user Family Reference Manual”, which is application can write program memory data, either in available from the Microchip web site blocks or ‘rows’ of 64 instructions (192 bytes) at a time, (www.microchip.com). The information in or a single program memory word, and erase program this data sheet supersedes the memory in blocks or ‘pages’ of 512 instructions information in the FRM. (1536bytes) at a time. 2: Some registers and associated bits described in this section may not be 5.1 Table Instructions and Flash available on all devices. Refer to Programming Section4.0 “Memory Organization” in this data sheet for device-specific register Regardless of the method used, all programming of and bit information. Flash memory is done with the Table Read and Table Write instructions. These allow direct read and write The dsPIC33FJ32GS406/606/608/610 and access to the program memory space from the data dsPIC33FJ64GS406/606/608/610 devices contain memory while the device is in normal operating mode. internal Flash program memory for storing and execut- The 24-bit target address in the program memory is ing application code. The memory is readable, writable formed using bits<7:0> of the TBLPAG register and the and erasable during normal operation over the entire Effective Address (EA) from a W register specified in VDD range. the table instruction, as shown in Figure5-1. Flash memory can be programmed in two ways: The TBLRDL and the TBLWTL instructions are used to • In-Circuit Serial Programming™ (ICSP™) read or write to bits<15:0> of program memory. • Run-Time Self-Programming (RTSP) TBLRDL and TBLWTL can access program memory in both Word and Byte modes. ICSP allows a dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 device to be serially The TBLRDH and TBLWTH instructions are used to read programmed while in the end application circuit. This is or write to bits<23:16> of program memory. TBLRDH done with two lines for programming clock and and TBLWTH can also access program memory in Word programming data (one of the alternate programming or Byte mode. FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 Bits Using 0 Program Counter 0 Program Counter Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 Bits 16 Bits User/Configuration Byte Space Select 24-Bit EA Select  2009-2014 Microchip Technology Inc. DS70000591F-page 109

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 5.2 RTSP Operation For example, if the device is operating at +125°C, the FRC accuracy will be ±2%. If the TUN<5:0> bits (see The dsPIC33FJ32GS406/606/608/610 and Register9-4) are set to ‘b000000, the minimum row dsPIC33FJ64GS406/606/608/610 Flash program write time is equal to Equation5-2. memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a EQUATION 5-2: MINIMUM ROW WRITE page of memory, which consists of eight rows TIME (512instructions) at a time, and to program one row or one word at a time. Table27-12 shows typical erase and 11064 Cycles programming times. The 8-row erase pages and single TRW =7.37 MHz  (1 + 0.02)  (1 – 0.000938) = 1.473 ms row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536bytes and 192bytes, respectively. The maximum row write time is equal to Equation5-3. The program memory implements holding buffers that EQUATION 5-3: MAXIMUM ROW WRITE can contain 64 instructions of programming data. Prior TIME to the actual programming operation, the write data must be loaded into the buffers sequentially. The 11064 Cycles instruction words loaded must always be from a group TRW = = 1.533 ms 7.37 MHz  (1 – 0.02)  (1 – 0.000938) of 64 boundary. The basic sequence for RTSP programming is to set up Setting the WR bit (NVMCON<15>) starts the a Table Pointer, then do a series of TBLWT instructions operation and the WR bit is automatically cleared to load the buffers. Programming is performed by when the operation is finished. setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required 5.4 Control Registers to load the instructions. All of the Table Write operations are single-word writes Two SFRs are used to read and write the program (two instruction cycles) because only the buffers are writ- Flash memory: NVMCON and NVMKEY. ten. A programming cycle is required for programming The NVMCON register (Register5-1) controls which each row. blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. 5.3 Programming Operations NVMKEY is a write-only register that is used for write A complete programming sequence is necessary for protection. To start a programming or erase sequence, programming or erasing the internal Flash in RTSP the user application must consecutively write 0x55 and mode. The processor stalls (waits) until the 0xAA to the NVMKEY register. Refer to Section5.3 programming operation is finished. “Programming Operations” for further details. The programming time depends on the FRC accuracy (see Table27-20) and the value of the FRC Oscillator Tuning register (see Register9-4). Use the following formula to calculate the minimum and maximum values for the Row Write Time, Page Erase Time and Word Write Cycle Time parameters (see Table27-12). EQUATION 5-1: PROGRAMMING TIME T -------------------------------------------------------------------------------------------------------------------------- 7.37 MHzFRC Accuracy%FRC Tuning% DS70000591F-page 110  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — ERASE — — NVMOP3(2) NVMOP2(2) NVMOP1(2) NVMOP0(2) bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit(1) 1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit(1) 1 = Enables Flash program/erase operations 0 = Inhibits Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit(1) 1 = Performs the erase operation specified by the NVMOP<3:0> bits on the next WR command 0 = Performs the program operation specified by the NVMOP<3:0> bits on the next WR command bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,2) If ERASE = 1: 1111 = Memory bulk erase operation 1101 = Erases General Segment (GS) 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erases a single Configuration register byte If ERASE = 0: 1111 = No operation 1101 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Programs a single Configuration register byte Note 1: These bits can only be reset on a Power-on Reset. 2: All other combinations of NVMOP<3:0> are unimplemented.  2009-2014 Microchip Technology Inc. DS70000591F-page 111

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register bits (write-only) DS70000591F-page 112  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 5.4.1 PROGRAMMING ALGORITHM FOR 4. Write the first 64 instructions from data RAM into FLASH PROGRAM MEMORY the program memory buffers (see Example5-2). 5. Write the program block to Flash memory: One row of program Flash memory can be programmed at a time. To achieve this, it is necessary a) Set the NVMOPx bits to ‘0001’ to configure to erase the 8-row erase page that contains the desired for row programming. Clear the ERASE bit row. The general process is: and set the WREN bit. b) Write 0x55 to NVMKEY. 1. Read eight rows of program memory (512instructions) and store in data RAM. c) Write 0xAA to NVMKEY. 2. Update the program data in RAM with the d) Set the WR bit. The programming cycle desired new data. begins and the CPU stalls for the duration of the write cycle. When the write to Flash 3. Erase the block (see Example5-1): memory is done, the WR bit is cleared a) Set the NVMOPx bits (NVMCON<3:0>) to automatically. ‘0010’ to configure for block erase. Set the 6. Repeat Steps 4 and 5, using the next available ERASE (NVMCON<6>) and WREN 64 instructions from the block in data RAM by (NVMCON<14>) bits. incrementing the value in TBLPAG, until all b) Write the starting address of the page to be 512instructions are written back to Flash memory. erased into the TBLPAG and W registers. For protection against accidental operations, the write c) Write 0x55 to NVMKEY. initiate sequence for NVMKEY must be used to allow d) Write 0xAA to NVMKEY. any erase or program operation to proceed. After the e) Set the WR bit (NVMCON<15>). The erase programming command has been executed, the user cycle begins and the CPU stalls for the application must wait for the programming time until duration of the erase cycle. When the erase is programming is complete. The two instructions done, the WR bit is cleared automatically. following the start of the programming sequence should be NOPs, as shown in Example5-3. EXAMPLE 5-1: ERASING A PROGRAM MEMORY PAGE ; Set up NVMCON for block erase operation MOV #0x4042, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted  2009-2014 Microchip Technology Inc. DS70000591F-page 113

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch • • • ; 63rd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch EXAMPLE 5-3: INITIATING A PROGRAMMING SEQUENCE DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the NOP ; erase command is asserted DS70000591F-page 114  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 6.0 RESETS Any active source of Reset will make the SYSRST signal active. On system Reset, some of the registers Note1: This data sheet summarizes the features associated with the CPU and peripherals are forced to of the dsPIC33FJ32GS406/606/608/610 a known Reset state and some are unaffected. and dsPIC33FJ64GS406/606/608/610 Note: Refer to the specific peripheral section or families of devices. It is not intended to be Section3.0 “CPU” of this data sheet for a comprehensive reference source. To register Reset states. complement the information in this data sheet, refer to “Reset” (DS70192) in All types of device Reset sets a corresponding status the “dsPIC33/PIC24 Family Reference bit in the RCON register to indicate the type of Reset Manual”, which is available from the (see Register6-1). Microchip web site (www.microchip.com). A POR clears all the bits, except for the POR bit The information in this data sheet (RCON<0>), that are set. The user application can set supersedes the information in the FRM. or clear any bit at any time during code execution. The 2: Some registers and associated bits RCON bits only serve as status bits. Setting a particular described in this section may not be Reset status bit in software does not cause a device available on all devices. Refer to Reset to occur. Section4.0 “Memory Organization” in The RCON register also has other bits associated with this data sheet for device-specific register the Watchdog Timer and device power-saving states. and bit information. The function of these bits is discussed in other sections The Reset module combines all Reset sources and of this manual. controls the device Master Reset Signal, SYSRST. The Note: The status bits in the RCON register following is a list of device Reset sources: should be cleared after they are read so • POR: Power-on Reset that the next RCON register value after a • BOR: Brown-out Reset device Reset is meaningful. • MCLR: Master Clear Pin Reset • SWR: Software RESET Instruction • WDTO: Watchdog Timer Reset • TRAPR: Trap Conflict Reset • IOPUWR: Illegal Condition Device Reset - Illegal Opcode Reset - Uninitialized W Register Reset - Security Reset A simplified block diagram of the Reset module is shown in Figure6-1.  2009-2014 Microchip Technology Inc. DS70000591F-page 115

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle BOR Internal SYSRST Regulator VDD VDD Rise POR Detect Trap Conflict Illegal Opcode Uninitialized W Register DS70000591F-page 116  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R E GISTER 6-1: RCON: RESET CONTROL REGISTER(1) R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 TRAPR IOPUWR — — — — — VREGS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or Uninitialized W register used as an Address Pointer caused a Reset 0 = An Illegal Opcode or Uninitialized W Reset has not occurred bit 13-9 Unimplemented: Read as ‘0’ bit 8 VREGS: Voltage Regulator Standby During Sleep bit 1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Standby mode during Sleep bit 7 EXTR: External Reset Pin (MCLR) bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset Flag (Instruction) bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.  2009-2014 Microchip Technology Inc. DS70000591F-page 117

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 6.1 System Reset A Warm Reset is the result of all the other Reset sources, including the RESET instruction. On Warm The dsPIC33FJ32GS406/606/608/610 and Reset, the device will continue to operate from the dsPIC33FJ64GS406/606/608/610 families of devices current clock source as indicated by the Current have two types of Reset: Oscillator Selection (COSC<2:0>) bits in the Oscillator • Cold Reset Control (OSCCON<14:12>) register. • Warm Reset The device is kept in a Reset state until the system A Cold Reset is the result of a Power-on Reset (POR) power supplies have stabilized at appropriate levels or a Brown-out Reset (BOR). On a Cold Reset, the and the oscillator clock is ready. The sequence in FNOSCx Configuration bits in the FOSC Configuration which this occurs is described in Figure6-2. register select the device clock source. TABLE 6-1: OSCILLATOR DELAY Oscillator Oscillator Oscillator Mode PLL Lock Time Total Delay Start-up Delay Start-up Timer FRC, FRCDIV16, FRCDIVN TOSCD(1) — — TOSCD(1) FRCPLL TOSCD(1) — TLOCK(3) TOSCD + TLOCK(1,3) XT TOSCD(1) TOST(2) — TOSCD + TOST(1,2) HS TOSCD(1) TOST(2) — TOSCD + TOST(1,2) EC — — — — XTPLL TOSCD(1) TOST(2) TLOCK(3) TOSCD + TOST + TLOCK(1,2,3) HSPLL TOSCD(1) TOST(2) TLOCK(3) TOSCD + TOST + TLOCK(1,2,3) ECPLL — — TLOCK(3) TLOCK(3) LPRC TOSCD(1) — — TOSCD(1) Note 1: TOSCD = Oscillator start-up delay (1.1s max. for FRC, 70s max. for LPRC). Crystal oscillator start-up times vary with the crystal characteristics, load capacitance, etc. 2: TOST = Oscillator Start-up Timer (OST) delay (1024 oscillator clock period). For example, TOST = 102.4s for a 10MHz crystal and TOST=32ms for a 32kHz crystal. 3: TLOCK = PLL lock time (1.5ms nominal) if PLL is enabled. DS70000591F-page 118  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 6-2: SYSTEM RESET TIMING VBOR VPOR VDD TPOR 1 POR TBOR 2 BOR 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 TFSCM FSCM 5 Device Status Reset Run Time Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. 2: BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes stable. 3: PWRT Timer: The programmable Power-up Timer (PWRT) continues to hold the processor in Reset for a specific period of time (TPWRT) after a BOR. The delay, TPWRT, ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay, TPWRT has elapsed and the SYSRST becomes inactive, which in turn, enables the selected oscillator to start generating clock cycles. 4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in Table6-1. Refer to Section9.0 “Oscillator Configuration” for more information. 5: When the oscillator clock is ready, the processor begins execution from location, 0x000000. The user application programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. 6: If the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is ready and the delay, TFSCM, has elapsed. TABLE 6-2: OSCILLATOR DELAY Note: When the device exits the Reset condition (begins normal operation), the Symbol Parameter Value device operating parameters (voltage, VPOR POR Threshold 1.8V nominal frequency, temperature, etc.) must be TPOR POR Extension Time 30s maximum within their operating ranges; otherwise, the device may not function correctly. VBOR BOR Threshold 2.5V nominal The user application must ensure that TBOR BOR Extension Time 100s maximum the delay between the time power is first TPWRT Programmable 0-128ms nominal applied, and the time SYSRST becomes Power-up Time Delay inactive, is long enough to get all TFSCM Fail-Safe Clock Monitor 900s maximum operating parameters within specification. Delay  2009-2014 Microchip Technology Inc. DS70000591F-page 119

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 6.2 Power-on Reset (POR) VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output A Power-on Reset (POR) circuit ensures the device is becomes stable. reset from power-on. The POR circuit is active until The Brown-out Reset (BOR) status bit in the Reset VDD crosses the VPOR threshold and the delay, TPOR, Control (RCON<1>) register is set to indicate the has elapsed. The delay, TPOR, ensures the internal Brown-out Reset. device bias circuits become stable. The device will not run at full speed after a BOR as the The device supply voltage characteristics must meet the specified starting voltage and rise rate VDD should rise to acceptable levels for full-speed operation. The PWRT provides a Power-up Time Delay requirements to generate the POR. Refer to Section27.0 “Electrical Characteristics” for details. (TPWRT) to ensure that the system power supplies have stabilized at the appropriate levels for full-speed The Power-on Reset (POR) status bit in the Reset operation before the SYSRST is released. Control (RCON<0>) register is set to indicate the Power-on Reset. The Power-up Timer delay (TPWRT) is programmed by the Power-on Reset Timer Value Select (FPWRT<2:0>) bits in the FPOR Configuration 6.3 Brown-out Reset (BOR) and (FPOR<2:0>) register, which provides eight settings Power-up Timer (PWRT) (from 0ms to 128ms). Refer to Section24.0 “Special Features” for further details. The on-chip regulator has a Brown-out Reset (BOR) circuit that resets the device when the VDD is too low Figure6-3 shows the typical brown-out scenarios. The (VDD < VBOR) for proper device operation. The BOR Reset delay (TBOR + TPWRT) is initiated each time VDD circuit keeps the device in Reset until VDD crosses the rises above the VBOR trip point FIGURE 6-3: BROWN-OUT SITUATIONS VDD VBOR TBOR + TPWRT SYSRST VDD VBOR TBOR + TPWRT SYSRST VDD Dips Before PWRT Expires VDD VBOR TBOR + TPWRT SYSRST DS70000591F-page 120  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 6.4 External Reset (EXTR) 6.7 Trap Conflict Reset The External Reset is generated by driving the MCLR If a lower priority hard trap occurs while a higher pin low. The MCLR pin is a Schmitt Trigger input with priority trap is being processed, a hard Trap Conflict an additional glitch filter. Reset pulses that are longer Reset occurs. The hard traps include exceptions of than the minimum pulse width will generate a Reset. Priority Level 13 through Level 15, inclusive. The Refer to Section27.0 “Electrical Characteristics” for address error (Level13) and oscillator error (Level 14) minimum pulse width specifications. The External traps fall into this category. Reset (MCLR) pin (EXTR) bit in the Reset Control The Trap Reset (TRAPR) flag in the Reset Control (RCON) register is set to indicate the MCLR Reset. (RCON<15>) register is set to indicate the Trap Conflict Reset. Refer to Section7.0 “Interrupt Controller” for 6.4.1 EXTERNAL SUPERVISORY more information on Trap Conflict Resets. CIRCUIT 6.8 Illegal Condition Device Reset Many systems have external supervisory circuits that generate Reset signals to reset multiple devices in the An illegal condition device Reset occurs due to the system. This external Reset signal can be directly following sources: connected to the MCLR pin to reset the device when the rest of system is reset. • Illegal Opcode Reset • Uninitialized W Register Reset 6.4.2 INTERNAL SUPERVISORY CIRCUIT • Security Reset When using the internal power supervisory circuit to The Illegal Opcode or Uninitialized W Access Reset reset the device, the External Reset pin (MCLR) should (IOPUWR) flag in the Reset Control (RCON<14>) register be tied directly or resistively to VDD. In this case, the is set to indicate the illegal condition device Reset. MCLR pin will not be used to generate a Reset. The 6.8.1 ILLEGAL OPCODE RESET External Reset pin (MCLR) does not have an internal pull-up and must not be left unconnected. A device Reset is generated if the device attempts to execute an illegal opcode value that is fetched from 6.5 Software RESET Instruction (SWR) program memory. Whenever the RESET instruction is executed, the The Illegal Opcode Reset function can prevent the device will assert SYSRST, placing the device in a device from executing program memory sections that special Reset state. This Reset state will not are used to store constant data. To take advantage of re-initialize the clock. The clock source in effect prior to the Illegal Opcode Reset, use only the lower 16 bits of the RESET instruction will remain. SYSRST is released each program memory section to store the data values. at the next instruction cycle and the Reset vector fetch The upper 8 bits should be programmed with 3Fh, will commence. which is an illegal opcode value. The Software Reset (SWR) flag (instruction) in the 6.8.2 UNINITIALIZED W REGISTER RESET Reset Control (RCON<6>) register is set to indicate Any attempt to use the Uninitialized W register as an the Software Reset. Address Pointer will reset the device. The W register array (with the exception of W15) is cleared during all 6.6 Watchdog Timer Time-out Reset Resets and is considered uninitialized until written to. (WDTO) 6.8.3 SECURITY RESET Whenever a Watchdog Timer Time-out Reset occurs, the device will asynchronously assert SYSRST. The If a Program Flow Change (PFC) or Vector Flow clock source will remain unchanged. A WDT time-out Change (VFC) targets a restricted location in a during Sleep or Idle mode will wake-up the processor, protected segment (Boot and Secure Segment), that but will not reset the processor. operation will cause a Security Reset. The Watchdog Timer Time-out (WDTO) flag in the The PFC occurs when the Program Counter is reloaded Reset Control (RCON<4>) register is set to indicate as a result of a call, jump, computed jump, return, return the Watchdog Timer Reset. Refer to Section24.4 from subroutine or other form of branch instruction. “Watchdog Timer (WDT)” for more information on The VFC occurs when the Program Counter is the Watchdog Timer Reset. reloaded with an interrupt or trap vector. Refer to Section24.8 “Code Protection and CodeGuard™ Security” for more information on Security Reset.  2009-2014 Microchip Technology Inc. DS70000591F-page 121

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 6.9 Using the RCON Status Bits Table6-3 provides a summary of the Reset flag bit operation. The user application can read the Reset Control (RCON) register after any device Reset to determine the cause of the Reset. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. TABLE 6-3: RESET FLAG BIT OPERATION Flag Bit Set by: Cleared by: TRAPR (RCON<15>) Trap Conflict Event POR, BOR IOPWR (RCON<14>) Illegal Opcode or Uninitialized W register POR, BOR Access or Security Reset EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET Instruction POR, BOR WDTO (RCON<4>) WDT Time-out PWRSAV Instruction, CLRWDT Instruction, POR, BOR SLEEP (RCON<3>) PWRSAV #SLEEP Instruction POR, BOR IDLE (RCON<2>) PWRSAV #IDLE Instruction POR, BOR BOR (RCON<1>) POR, BOR — POR (RCON<0>) POR — Note: All Reset flag bits can be set or cleared by user software. DS70000591F-page 122  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 7.0 INTERRUPT CONTROLLER Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the Note 1: This data sheet summarizes the features of vector table. Lower addresses generally have a higher the dsPIC33FJ32GS406/606/608/610 natural priority. For example, the interrupt associated and dsPIC33FJ64GS406/606/608/610 with Vector 0 will take priority over interrupts at any families of devices. It is not intended to be other vector address. a comprehensive reference source. To The dsPIC33FJ32GS406/606/608/610 and complement the information in this data dsPIC33FJ64GS406/606/608/610 devices implement sheet, refer to “Interrupts (Part V)” up to 71 unique interrupts and fivenon-maskable traps. (DS70597) in the “dsPIC33/PIC24 Family These are summarized in Table7-1. Reference Manual”, which is available from the Microchip web site 7.1.1 ALTERNATE INTERRUPT VECTOR (www.microchip.com). The information TABLE in this data sheet supersedes the The Alternate Interrupt Vector Table (AIVT) is located information in the FRM. after the IVT, as shown in Figure7-1. Access to the 2: Some registers and associated bits AIVT is provided by the ALTIVT control bit described in this section may not be (INTCON2<15>). If the ALTIVT bit is set, all interrupt available on all devices. Refer to and exception processes use the alternate vectors Section4.0 “Memory Organization” in instead of the default vectors. The alternate vectors are this data sheet for device-specific register organized in the same manner as the default vectors. and bit information. The AIVT supports debugging by providing a means to The dsPIC33FJ32GS406/606/608/610 and switch between an application and a support environ- dsPIC33FJ64GS406/606/608/610 interrupt controller ment without requiring the interrupt vectors to be reduces the numerous peripheral interrupt request reprogrammed. This feature also enables switching signals to a single interrupt request signal to between applications for evaluation of different soft- the dsPIC33FJ32GS406/606/608/610 and ware algorithms at run time. If the AIVT is not needed, dsPIC33FJ64GS406/606/608/610 CPU. It has the the AIVT should be programmed with the same following features: addresses used in the IVT. • Up to Eight Processor Exceptions and Software 7.2 Reset Sequence Traps • Seven User-Selectable Priority Levels A device Reset is not a true exception because the • Interrupt Vector Table (IVT) with up to 118 Vectors interrupt controller is not involved in the Reset • A Unique Vector for each Interrupt or Exception process. The dsPIC33FJ32GS406/606/608/610 and Source dsPIC33FJ64GS406/606/608/610 devices clear their • Fixed Priority within a Specified User Priority Level registers in response to a Reset, which forces the PC to zero. The Digital Signal Controller (DSC) then begins • Alternate Interrupt Vector Table (AIVT) for Debug program execution at location, 0x000000. A GOTO Support instruction at the Reset address can redirect program • Fixed Interrupt Entry and Return Latencies execution to the appropriate start-up routine. 7.1 Interrupt Vector Table Note: Any unimplemented or unused vector locations in the IVT and AIVT should be The Interrupt Vector Table (IVT) is shown in Figure7-1. programmed with the address of a default The IVT resides in program memory, starting at location interrupt handler routine that contains a 000004h. The IVT contains 126 vectors, consisting of RESET instruction. eight nonmaskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit-wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR).  2009-2014 Microchip Technology Inc. DS70000591F-page 123

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 7-1: dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 INTERRUPT VECTOR TABLE Reset – GOTO Instruction 0x000000 Reset – GOTO Address 0x000002 Reserved 0x000004 Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 0x000014 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 0x00007C Interrupt Vector Table (IVT)(1) Interrupt Vector 53 0x00007E ority Interrupt ~Vector 54 0x000080 Pri ~ der ~ Or Interrupt Vector 116 0x0000FC al Interrupt Vector 117 0x0000FE atur Reserved 0x000100 N Reserved 0x000102 g n Reserved si a Oscillator Fail Trap Vector e cr Address Error Trap Vector e D Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 0x000114 Interrupt Vector 1 ~ ~ ~ Alternate Interrupt Vector Table (AIVT)(1) Interrupt Vector 52 0x00017C Interrupt Vector 53 0x00017E Interrupt Vector 54 0x000180 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 0x0001FE Start of Code 0x000200 Note 1: See Table7-1 for the list of implemented interrupt vectors. DS70000591F-page 124  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 7-1: INTERRUPT VECTORS Vector Interrupt IVT Address AIVT Address Interrupt Source Number Request (IQR) Highest Natural Order Priority 8 0 0x000014 0x000114 INT0 – External Interrupt 0 9 1 0x000016 0x000116 IC1 – Input Capture 1 10 2 0x000018 0x000118 OC1 – Output Compare 1 11 3 0x00001A 0x00011A T1 – Timer1 12 4 0x00001C 0x00011C DMA0 – DMA Channel 0 13 5 0x00001E 0x00011E IC2 – Input Capture 2 14 6 0x000020 0x000120 OC2 – Output Compare 2 15 7 0x000022 0x000122 T2 – Timer2 16 8 0x000024 0x000124 T3 – Timer3 17 9 0x000026 0x000126 SPI1E – SPI1 Fault 18 10 0x000028 0x000128 SPI1 – SPI1 Transfer Done 19 11 0x00002A 0x00012A U1RX – UART1 Receiver 20 12 0x00002C 0x00012C U1TX – UART1 Transmitter 21 13 0x00002E 0x00012E ADC–ADC Group Convert Done 22 14 0x000030 0x000130 DMA1 – DMA Channel 1 23 15 0x000032 0x000132 Reserved 24 16 0x000034 0x000134 SI2C1 – I2C1 Slave Event 25 17 0x000036 0x000136 MI2C1 – I2C1 Master Event 26 18 0x000038 0x000138 CMP1 – Analog Comparator 1 Interrupt 27 19 0x00003A 0x00013A CN – Input Change Notification Interrupt 28 20 0x00003C 0x00013C INT1 – External Interrupt 1 29-31 21-23 0x00003E- 0x00013E- Reserved 0x000042 0x000142 32 24 0x000044 0x000144 DMA2 – DMA Channel 2 33 25 0x000046 0x000146 OC3 – Output Compare 3 34 26 0x000048 0x000148 OC4 – Output Compare 4 35 27 0x00004A 0x00014A T4 – Timer4 36 28 0x00004C 0x00014C T5 – Timer5 37 29 0x00004E 0x00014E INT2 – External Interrupt 2 38 30 0x000050 0x000150 U2RX – UART2 Receiver 39 31 0x000052 0x000152 U2TX – UART2 Transmitter 40 32 0x000054 0x000154 SPI2E – SPI2 Error 41 33 0x000056 0x000156 SPI2 – SPI2 Transfer Done 42 34 0x000058 0x000158 C1RX – ECAN1 Receive Data Ready 43 35 0x00005A 0x00015A C1 – ECAN1 Event 44 36 0x00005C 0x00015C DMA3 – DMA Channel 3 45 37 0x00005E 0x00015E IC3 – Input Capture 3 46 38 0x000060 0x000160 IC4 – Input Capture 4 47-56 39-48 0x000062- 0x000162- Reserved 0x000074 0x000174 57 49 0x000076 0x000176 SI2C2 – I2C2 Slave Events 58 50 0x000078 0x000178 MI2C2 – I2C2 Master Events 59-60 51-52 0x00007A- 0x00017A- Reserved 0x00007C 0x00017C 61 53 0x00007E 0x00017E INT3 – External Interrupt 3 62 54 0x000080 0x000180 INT4 – External Interrupt 4  2009-2014 Microchip Technology Inc. DS70000591F-page 125

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Vector Interrupt IVT Address AIVT Address Interrupt Source Number Request (IQR) 63-64 55-56 0x000082- 0x000182- Reserved 0x000084 0x000184 65 57 0x000086 0x000186 PWM PSEM Special Event Match 66 58 0x000088 0x000188 QEI1 – Position Counter Compare 67-72 59-64 0x00008A- 0x00018A- Reserved 0x000094 0x000194 73 65 0x000096 0x000196 U1E – UART1 Error Interrupt 74 66 0x000098 0x000198 U2E – UART2 Error Interrupt 75-77 67-69 0x00009A- 0x00019A- Reserved 0x00009E 0x00019E 78 70 0x0000A0 0x0001A0 C1TX – ECAN1 Transmit Data Request 79 71 0x0000A2 0x0001A2 Reserved 80 72 0x0000A4 0x0001A4 Reserved 81 73 0x0000A6 0x0001A6 PWM Secondary Special Event Match 82 74 0x0000A8 0x0001A8 Reserved 83 75 0x0000AA 0x0001AA QEI2 – Position Counter Compare 84-88 76-80 0x0000AC- 0x0001AC- Reserved 0x0000B4 0x0001B4 89 81 0x0000B6 0x0001B6 ADC Pair 8 Conversion Done 90 82 0x0000B8 0x0001B8 ADC Pair 9 Conversion Done 91 83 0x0000BA 0x0001BA ADC Pair 10 Conversion Done 92 84 0x0000BC 0x0001BC ADC Pair 11 Conversion Done 93 85 0x0000BE 0x0001BE ADC Pair 12 Conversion Done 94-101 86-93 0x0000C0- 0x0001C0- Reserved 0x0000CE 0x0001CE 102 94 0x0000D0 0x0001D0 PWM1 – PWM1 Interrupt 103 95 0x0000D2 0x0001D2 PWM2 – PWM2 Interrupt 104 96 0x0000D4 0x0001D4 PWM3 – PWM3 Interrupt 105 97 0x0000D6 0x0001D6 PWM4 – PWM4 Interrupt 106 98 0x0000D8 0x0001D8 PWM5 – PWM5 Interrupt 107 99 0x0000DA 0x0001DA PWM6 – PWM6 Interrupt 108 100 0x0000DC 0x0001DC PWM7– PWM7 Interrupt 109 101 0x0000DE 0x0001DE PWM8 – PWM8 Interrupt 110 102 0x0000E0 0x0001E0 PWM9 – PWM9 Interrupt 111 103 0x0000E2 0x00001E2 CMP2 – Analog Comparator 2 112 104 0x0000E4 0x0001E4 CMP3 – Analog Comparator 3 113 105 0x0000E6 0x0001E6 CMP4 – Analog Comparator 4 114-117 106-109 0x0000E8- 0x0001E8- Reserved 0x0000EE 0x0001EE 118 110 0x0000F0 0x0001F0 ADC Pair 0 Convert Done 119 111 0x0000F2 0x0001F2 ADC Pair 1 Convert Done 120 112 0x0000F4 0x0001F4 ADC Pair 2 Convert Done 121 113 0x0000F6 0x0001F6 ADC Pair 3 Convert Done 122 114 0x0000F8 0x0001F8 ADC Pair 4 Convert Done 123 115 0x0000FA 0x0001FA ADC Pair 5 Convert Done 124 116 0x0000FC 0x0001FC ADC Pair 6 Convert Done 125 117 0x0000FE 0x0001FE ADC Pair 7 Convert Done Lowest Natural Order Priority DS70000591F-page 126  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 7.3 Interrupt Control and Status 7.3.5 INTTREG Registers The INTTREG register contains the associated interrupt vector number and the new CPU Interrupt The dsPIC33FJ32GS406/606/608/610 and Priority Level, which are latched into the Vector Num- dsPIC33FJ64GS406/606/608/610 devices implement ber (VECNUM<6:0>) and Interrupt Level (ILR<3:0>) bit 44 registers for the interrupt controller: fields in the INTTREG register. The new Interrupt • INTCON1 Priority Level is the priority of the pending interrupt. • INTCON2 The interrupt sources are assigned to the IFSx, IECx • IFSx and IPCx registers in the same sequence that they are • IECx listed in Table7-1. For example, the INT0 (External • IPCx Interrupt 0) is shown as having vector number 8 and a • INTTREG natural order priority of 0. Thus, the INT0IF bit is found 7.3.1 INTCON1 AND INTCON2 in IFS0<0>, the INT0IE bit is found in IEC0<0> and the INT0IP bits are found in the first position of IPC0 Global interrupt control functions are controlled from (IPC0<2:0>). INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the 7.3.6 STATUS/CONTROL REGISTERS control and status flags for the processor trap sources. Although they are not specifically part of the interrupt The INTCON2 register controls the external interrupt control hardware, two of the CPU Control registers request signal behavior and the use of the Alternate contain bits that control interrupt functionality. Interrupt Vector Table. • The CPU STATUS Register, SR, contains the 7.3.2 IFSx IPL<2:0> bits (SR<7:5>). These bits indicate the current CPU Interrupt Priority Level. The user can The IFSx registers maintain all of the interrupt request change the current CPU Priority Level by writing flags. Each source of interrupt has a status bit, which is to the IPLx bits. set by the respective peripherals or external signal and is cleared via software. • The CORCON register contains the IPL3 bit, which together with IPL<2:0>, indicates the 7.3.3 IECx current CPU Priority Level. IPL3 is a read-only bit so that trap events cannot be masked by the user The IECx registers maintain all of the interrupt enable software. bits. These control bits are used to individually enable interrupts from the peripherals or external signals. All Interrupt registers are described in Register7-1 through Register7-46 in the following pages. 7.3.4 IPCx The IPCx registers are used to set the Interrupt Priority Level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels.  2009-2014 Microchip Technology Inc. DS70000591F-page 127

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-1: SR: CPU STATUS REGISTER(1) R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: For complete register details, see Register3-1. 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1. REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT DL2 DL1 DL0 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less Note 1: For complete register details, see Register3-2. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS70000591F-page 128  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14 OVAERR: Accumulator A Overflow Trap Flag bit 1 = Trap was caused by an overflow of Accumulator A 0 = Trap was not caused by an overflow of Accumulator A bit 13 OVBERR: Accumulator B Overflow Trap Flag bit 1 = Trap was caused by an overflow of Accumulator B 0 = Trap was not caused by an overflow of Accumulator B bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit 1 = Trap was caused by a catastrophic overflow of Accumulator A 0 = Trap was not caused by a catastrophic overflow of Accumulator A bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit 1 = Trap was caused by a catastrophic overflow of Accumulator B 0 = Trap was not caused by a catastrophic overflow of Accumulator B bit 10 OVATE: Accumulator A Overflow Trap Enable bit 1 = Trap overflow of Accumulator A 0 = Trap is disabled bit 9 OVBTE: Accumulator B Overflow Trap Enable bit 1 = Trap overflow of Accumulator B 0 = Trap is disabled bit 8 COVTE: Catastrophic Overflow Trap Enable bit 1 = Trap on a catastrophic overflow of Accumulator A or B is enabled 0 = Trap is disabled bit 7 SFTACERR: Shift Accumulator Error Status bit 1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift bit 6 DIV0ERR: Arithmetic Error Status bit 1 = Math error trap was caused by a divide-by-zero 0 = Math error trap was not caused by a divide-by-zero bit 5 DMACERR: DMA Controller Error Status bit 1 = DMA Controller error trap has occurred 0 = DMA Controller error trap has not occurred bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred  2009-2014 Microchip Technology Inc. DS70000591F-page 129

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70000591F-page 130  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Uses Alternate Interrupt Vector Table 0 = Uses standard (default) Interrupt Vector Table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-5 Unimplemented: Read as ‘0’ bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 3 INT3EP: External Interrupt 3 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge  2009-2014 Microchip Technology Inc. DS70000591F-page 131

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 7-5: IFS0: INTERRUPT FLAG STATUS R EGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IF ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 ADIF: ADC Group Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 SPI1EIF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70000591F-page 132  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2009-2014 Microchip Technology Inc. DS70000591F-page 133

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 12 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 DMA2IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7-5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 AC1IF: Analog Comparator 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70000591F-page 134  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2009-2014 Microchip Technology Inc. DS70000591F-page 135

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC4IF IC3IF DMA3IF C1IF(1) C1RXIF(1) SPI2IF SPI2EIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 C1IF: ECAN1 Event Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 C1RXIF: ECAN1 External Event Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: Interrupts are disabled on devices without ECAN™ modules. DS70000591F-page 136  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — QEI1IF PSEMIF — bit 15 bit 8 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 — INT4IF INT3IF — — MI2C2IF SI2C2IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 QEI1IF: QEI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 PSEMIF: PWM Special Event Match Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-7 Unimplemented: Read as ‘0’ bit 6 INT4IF: External Interrupt 4 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 INT3IF: External Interrupt 3 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IF: I2C2 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’  2009-2014 Microchip Technology Inc. DS70000591F-page 137

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 — — — — QEI2IF — PSESMIF — bit 15 bit 8 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — C1TXIF(1) — — — U2EIF U1EIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11 QEI2IF: QEI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 Unimplemented: Read as ‘0’ bit 9 PSESMIF: PWM Special Event Secondary Match Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-7 Unimplemented: Read as ‘0’ bit 6 C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5-3 Unimplemented: Read as ‘0’ bit 2 U2EIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ Note 1: Interrupts are disabled on devices without ECAN™ modules. DS70000591F-page 138  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 PWM2IF PWM1IF ADCP12IF — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — ADCP11IF ADCP10IF ADCP9IF ADCP8IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWM2IF: PWM2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 PWM1IF: PWM1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 ADCP12IF: ADC Pair 12 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-5 Unimplemented: Read as ‘0’ bit 4 ADCP11IF: ADC Pair 11 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 ADCP10IF: ADC Pair 10 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 ADCP9IF: ADC Pair 9 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 ADCP8IF: ADC Pair 8 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’  2009-2014 Microchip Technology Inc. DS70000591F-page 139

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-11: IFS6: INTERRUPT FLAG STATUS REGISTER 6 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 ADCP1IF ADCP0IF — — — — AC4IF AC3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AC2IF PWM9IF PWM8IF PWM7IF PWM6IF PWM5IF PWM4IF PWM3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 ADCP0IF: ADC Pair 0 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-10 Unimplemented: Read as ‘0’ bit 9 AC4IF: Analog Comparator 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 AC3IF: Analog Comparator 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 AC2IF: Analog Comparator 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 PWM9IF: PWM9 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 PWM8IF: PWM8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 PWM7IF: PWM7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 PWM6IF: PWM6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 PWM5IF: PWM5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 PWM4IF: PWM4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 PWM3IF: PWM3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70000591F-page 140  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-12: IFS7: INTERRUPT FLAG STATUS REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ADCP7IF ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 ADCP7IF: ADC Pair 7 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 ADCP6IF: ADC Pair 6 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 ADCP5IF: ADC Pair 5 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 ADCP4IF: ADC Pair 4 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 ADCP3IF: ADC Pair 3 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 ADCP2IF: ADC Pair 2 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2009-2014 Microchip Technology Inc. DS70000591F-page 141

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 7-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IE ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 ADIE: ADC1 Conversion Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 SPI1IE: SPI1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 SPI1EIE: SPI1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4 DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS70000591F-page 142  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2009-2014 Microchip Technology Inc. DS70000591F-page 143

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-14: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 12 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 DMA2IE: DMA Channel 2 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7-5 Unimplemented: Read as ‘0’ bit 4 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 AC1IE: Analog Comparator 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS70000591F-page 144  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-14: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2009-2014 Microchip Technology Inc. DS70000591F-page 145

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 7-15: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IC4IE IC3IE DMA3IE C1IE(1) C1RXIE(1) SPI2IE SPI2EIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6 IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4 DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 C1IE: ECAN1 Event Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: Interrupts are disabled on devices without ECAN™ modules. DS70000591F-page 146  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-16: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — QEI1IE PSEMIE — bit 15 bit 8 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 — INT4IE INT3IE — — MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 QEI1IE: QEI1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 PSEMIE: PWM Special Event Match Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8-7 Unimplemented: Read as ‘0’ bit 6 INT4IE: External Interrupt 4 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 INT3IE: External Interrupt 3 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IE: I2C2 Master Events Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 SI2C2IE: I2C2 Slave Events Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’  2009-2014 Microchip Technology Inc. DS70000591F-page 147

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-17: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 — — — — QEI2IE — PSESMIE — bit 15 bit 8 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — C1TXIE(1) — — — U2EIE U1EIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11 QEI2IE: QEI2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 Unimplemented: Read as ‘0’ bit 9 PSESMIE: PWM Special Event Secondary Match Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8-7 Unimplemented: Read as ‘0’ bit 6 C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5-3 Unimplemented: Read as ‘0’ bit 2 U2EIE: UART2 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: Interrupts are disabled on devices without ECAN™ modules. DS70000591F-page 148  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-18: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 PWM2IE PWM1IE ADCP12IE — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWM2IE: PWM2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 PWM1IE: PWM1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 ADCP12IE: ADC Pair 12 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12-0 Unimplemented: Read as ‘0’  2009-2014 Microchip Technology Inc. DS70000591F-page 149

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-19: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 ADCP1IE ADCP0IE — — — — AC4IE AC3IE bit 15 bit 8 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 AC2IE — — — PWM6IE PWM5IE PWM4IE PWM3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADCP1IE: ADC Pair 1 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 ADCP0IE: ADC Pair 0 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13-10 Unimplemented: Read as ‘0’ bit 9 AC4IE: Analog Comparator 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 AC3IE: Analog Comparator 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 AC2IE: Analog Comparator 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6-4 Unimplemented: Read as ‘0’ bit 3 PWM6IE: PWM6 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 PWM5IE: PWM5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 PWM4IE: PWM4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 PWM3IE: PWM3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS70000591F-page 150  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-20: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ADCP7IE ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 ADCP7IE: ADC Pair 7 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4 ADCP6IE: ADC Pair 6 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 ADCP5IE: ADC Pair 5 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 ADCP4IE: ADC Pair 4 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 ADCP3IE: ADC Pair 3 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 ADCP2IE: ADC Pair 2 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2009-2014 Microchip Technology Inc. DS70000591F-page 151

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-21: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS70000591F-page 152  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-22: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC2IP2 IC2IP1 IC2IP0 — DMA0IP2 DMA0IP1 DMA0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2009-2014 Microchip Technology Inc. DS70000591F-page 153

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-23: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS70000591F-page 154  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-24: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — DMA1IP2 DMA1IP1 DMA1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADIP<2:0>: ADC1 Conversion Complete Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2009-2014 Microchip Technology Inc. DS70000591F-page 155

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-25: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 AC1IP<2:0>: Analog Comparator 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS70000591F-page 156  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-26: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2009-2014 Microchip Technology Inc. DS70000591F-page 157

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 7-27: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC3IP2 OC3IP1 OC3IP0 — DMA2IP2 DMA2IP1 DMA2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS70000591F-page 158  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 7-28: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2009-2014 Microchip Technology Inc. DS70000591F-page 159

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 7-29: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — C1IP2(1) C1IP1(1) C1IP0(1) — C1RXIP2(1) C1RXIP1(1) C1RXIP0(1) bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPI2EIP2 SPI2EIP1 SPI2EIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 C1IP<2:0>: ECAN1 Event Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Note 1: Interrupts are disabled on devices without ECAN™ modules. DS70000591F-page 160  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-30: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — IC4IP2 IC4IP1 IC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC3IP2 IC3IP1 IC3IP0 — DMA3IP2 DMA3IP1 DMA3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2009-2014 Microchip Technology Inc. DS70000591F-page 161

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 7-31: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP<2:0>: I2C2 Master Events Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SI2C2IP<2:0>: I2C2 Slave Events Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70000591F-page 162  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 7-32: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT4IP2 INT4IP1 INT4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT3IP2 INT3IP1 INT3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 INT4IP<2:0>: External Interrupt 4 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT3IP<2:0>: External Interrupt 3 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2009-2014 Microchip Technology Inc. DS70000591F-page 163

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-33: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — QEI1IP2 QEI1IP1 QEI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — PSEMIP2 PSEMIP1 PSEMIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 QEI1IP<2:0>: QEI1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 PSEMIP<2:0>: PWM Special Event Match Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70000591F-page 164  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-34: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — U2EIP2 U2EIP1 U2EIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1EIP2 U1EIP1 U1EIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 U2EIP<2:0>: UART2 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2009-2014 Microchip Technology Inc. DS70000591F-page 165

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-35: IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — C1TXIP2(1) C1TXIP1(1) C1TXIP0(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 C1TXIP<2:0>: ECAN1 Transmit Data Request Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ Note 1: Interrupts are disabled on devices without ECAN™ modules. DS70000591F-page 166  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-36: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — QEI2IP2 QEI2IP1 QEI2IP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — PSESMIP2 PSESMIP1 PSESMIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 QEI2IP<2:0>: QEI2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-7 Unimplemented: Read as ‘0’ bit 6-4 PSESMIP<2:0>: PWM Special Event Secondary Match Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2009-2014 Microchip Technology Inc. DS70000591F-page 167

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-37: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADCP10IP2 ADCP10IP1 ADCP10IP0 — ADCP9IP2 ADCP9IP1 ADCP9IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — ADCP8IP2 ADCP8IP1 ADCP8IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP10IP<2:0>: ADC Pair 10 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 ADCP9IP<2:0>: ADC Pair 9 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCP8IP<2:0>: ADC Pair 8 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70000591F-page 168  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-38: IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — ADCP12IP2 ADCP12IP1 ADCP12IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ADCP12IP<2:0>: ADC Pair 12 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2009-2014 Microchip Technology Inc. DS70000591F-page 169

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-39: IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 PWM2IP<2:0>: PWM2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ DS70000591F-page 170  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-40: IPC24: INTERRUPT PRIORITY CONTROL REGISTER 24 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — PWM6IP2 PWM6IP1 PWM6IP0 — PWM5IP2 PWM5IP1 PWM5IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 PWM6IP<2:0>: PWM6 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 PWM5IP<2:0>: PWM5 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 PWM4IP<2:0>: PWM4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 PWM3IP<2:0>: PWM3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2009-2014 Microchip Technology Inc. DS70000591F-page 171

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-41: IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AC2IP2 AC2IP1 AC2IP0 — PWM9IP2 PWM9IP1 PWM9IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — PWM8IP2 PWM8IP1 PWM8IP0 — PWM7IP2 PWM7IP1 PWM7IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 AC2IP<2:0>: Analog Comparator 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 PWM9IP<2:0>: PWM9 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 PWM8IP<2:0>: PWM8 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 PWM7IP<2:0>: PWM7 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS70000591F-page 172  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-42: IPC26: INTERRUPT PRIORITY CONTROL REGISTER 26 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AC4IP<2:0>: Analog Comparator 4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 AC3IP<2:0>: Analog Comparator 3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2009-2014 Microchip Technology Inc. DS70000591F-page 173

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-43: IPC27: INTERRUPT PRIORITY CONTROL REGISTER 27 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP1IP<2:0>: ADC Pair 1 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 ADCP0IP<2:0>: ADC Pair 0 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ DS70000591F-page 174  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-44: IPC28: INTERRUPT PRIORITY CONTROL REGISTER 28 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADCP5IP2 ADCP5IP1 ADCP5IP0 — ADCP4IP2 ADCP4IP1 ADCP4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1 ADCP2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP5IP<2:0>: ADC Pair 5 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 ADCP4IP<2:0>: ADC Pair 4 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCP3IP<2:0>: ADC Pair 3 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 ADCP2IP<2:0>: ADC Pair 2 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2009-2014 Microchip Technology Inc. DS70000591F-page 175

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-45: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADCP7IP2 ADCP7IP1 ADCP7IP0 — ADCP6IP2 ADCP6IP1 ADCP6IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ADCP7IP<2:0>: ADC Pair 7 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 ADCP6IP<2:0>: ADC Pair 6 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS70000591F-page 176  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 7-46: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt vector pending is Number 135 • • • 0000001 = Interrupt vector pending is Number 9 0000000 = Interrupt vector pending is Number 8  2009-2014 Microchip Technology Inc. DS70000591F-page 177

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 7.4 Interrupt Setup Procedures 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, 7.4.1 INITIALIZATION except that the appropriate trap status flag in the Complete the following steps to configure an interrupt INTCON1 register must be cleared to avoid re-entry source at initialization: into the TSR. 1. Set the NSTDIS bit (INTCON1<15>) if nested 7.4.4 INTERRUPT DISABLE interrupts are not desired. 2. Select the user-assigned priority level for the The following steps outline the procedure to disable all interrupt source by writing the control bits in the user interrupts: appropriate IPCx register. The priority level will 1. Push the current SR value onto the software depend on the specific application and type of stack using the PUSH instruction. interrupt source. If multiple priority levels are not 2. Force the CPU to Priority Level 7 by inclusive desired, the IPCx register control bits for all ORing the value, EOh, with SRL. enabled interrupt sources can be programmed To enable user interrupts, the POP instruction can be to the same non-zero value. used to restore the previous SR value. Note: At a device Reset, the IPCx registers are initialized such that all user interrupt Note: Only user interrupts with a priority level of sources are assigned to Priority Level 4. 7 or lower can be disabled. Trap sources (Level 8-Level 15) cannot be disabled. 3. Clear the interrupt flag status bit associated with The DISI instruction provides a convenient way to the peripheral in the associated IFSx register. disable interrupts of Priority Levels 1-6 for a fixed 4. Enable the interrupt source by setting the period of time. Level 7 interrupt sources are not interrupt enable control bit associated with the disabled by the DISI instruction. source in the appropriate IECx register. 7.4.2 INTERRUPT SERVICE ROUTINE The method used to declare an ISR and initialize the IVT with the correct vector address depends on the programming language (C or assembler) and the language development toolsuite used to develop the application. In general, the user application must clear the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, program will re-enter the ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. DS70000591F-page 178  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 8.0 DIRECT MEMORY ACCESS Direct Memory Access (DMA) is a very efficient (DMA) mechanism of copying data between peripheral SFRs (e.g., the UART Receive register and Input Capture 1 Note 1: This data sheet summarizes the features buffer) and buffers, or variables stored in RAM, with of the dsPIC33FJ32GS406/606/608/610 minimal CPU intervention. The DMA Controller and dsPIC33FJ64GS406/606/608/610 (DMAC) can automatically copy entire blocks of data family of devices. However, it is not without requiring the user software to read or write the intended to be a comprehensive reference peripheral Special Function Registers (SFRs) every source. To complement the information time a peripheral interrupt occurs. The DMA Controller in this data sheet, refer to “Direct uses a dedicated bus for data transfers and, therefore, Memory Access (DMA)” (DS70182) in does not steal cycles from the code execution flow of the “dsPIC33/PIC24 Family Reference the CPU. To exploit the DMA capability, the Manual”, which is available from the corresponding user buffers or variables must be Microchip web site (www.microchip.com). located in DMA RAM. The information in this data sheet Note: The DMA module is not available on supersedes the information in the FRM. dsIPC33FJ32GS406/606/608/610 and 2: Some registers and associated bits dsPIC33FJ64GS406 devices. described in this section may not be The peripherals that can utilize DMA are listed in available on all devices. Refer to Table8-1 along with their associated Interrupt Request Section4.0 “Memory Organization” in (IRQ) numbers. this data sheet for device-specific register and bit information. TABLE 8-1: DMA CONTROLLER CHANNEL TO PERIPHERAL ASSOCIATIONS DMAxPAD Register DMAxPAD Register DMAxREQ Register Peripheral to DMA Association Values to Read from Values to Write to IRQSEL<6:0> Bits Peripheral Peripheral INT0 – External Interrupt 0 0000000 — — IC1 – Input Capture 1 0000001 0x0140 (IC1BUF) — IC2 – Input Capture 2 0000101 0x0144 (IC2BUF) — IC3 – Input Capture 3 0100101 0x0148 (IC3BUF) — IC4 – Input Capture 4 0100110 0x014C (IC4BUF) — OC1 – Output Compare 1 Data 0000010 — 0x0182 (OC1R) OC1 – Output Compare 1 Secondary Data 0000010 — 0x0180 (OC1RS) OC2 – Output Compare 2 Data 0000110 — 0x0188 (OC2R) OC2 – Output Compare 2 Secondary Data 0000110 — 0x0186 (OC2RS) OC3 – Output Compare 3 Data 0011001 — 0x018E (OC3R) OC3 – Output Compare 3 Secondary Data 0011001 — 0x018C (OC3RS) OC4 – Output Compare 4 Data 0011010 — 0x0194 (OC4R) OC4 – Output Compare 4 Secondary Data 0011010 — 0x0192 (OC4RS) TMR2 – Timer2 0000111 — — TMR3 – Timer3 0001000 — — TMR4 – Timer4 0011011 — — TMR5 – Timer5 0011100 — — SPI1 – Transfer Done 0001010 0x0248 (SPI1BUF) 0x0248 (SPI1BUF) SPI2 – Transfer Done 0100001 0x0268 (SPI2BUF) 0x0268 (SPI2BUF) UART1RX – UART1 Receiver 0001011 0x0226 (U1RXREG) — UART1TX – UART1 Transmitter 0001100 — 0x0224 (U1TXREG) UART2RX – UART2 Receiver 0011110 0x0236 (U2RXREG) — UART2TX – UART2 Transmitter 0011111 — 0x0234 (U2TXREG) ECAN1 – RX Data Ready 0100010 0x0640 (C1RXD) — ECAN1 – TX Data Request 1000110 — 0x0642 (C1TXD)  2009-2014 Microchip Technology Inc. DS70000591F-page 179

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 The DMA Controller features four identical data 8.1 DMAC Registers transfer channels. Each channel has its own set of control and status registers. Each DMA channel can be Each DMAC Channel x (x = 0, 1, 2 or 3) contains the configured to copy data either from buffers stored in following registers: dual port DMA RAM to peripheral SFRs or from • A 16-Bit DMA Channel Control Register peripheral SFRs to buffers in DMA RAM. (DMAxCON) The DMA Controller supports the following features: • A 16-Bit DMA Channel IRQ Select Register (DMAxREQ) • Word or byte-sized data transfers. • A 16-Bit DMA RAM Primary Start Address Offset • Transfers from peripheral to DMA RAM or DMA Register (DMAxSTA) RAM to peripheral • A 16-Bit DMA RAM Secondary Start Address • Indirect Addressing of DMA RAM locations with or Offset Register (DMAxSTB) without automatic post-increment • A 16-Bit DMA Peripheral Address Register • Peripheral Indirect Addressing – In some (DMAxPAD) peripherals, the DMA RAM read/write addresses may be partially derived from the peripheral • A 10-Bit DMA Transfer Count Register (DMAxCNT) • One-Shot Block Transfers – Terminating a DMA An additional pair of status registers, DMACS0 and transfer after one block transfer DMACS1, are common to all DMAC channels. • Continuous Block Transfers – Reloading the DMA RAM buffer start address after every block transfer is complete • Ping-Pong Mode – Switching between two DMA RAM start addresses between successive block transfers, thereby filling two buffers alternately • Automatic or manual initiation of block transfers For each DMA channel, a DMA interrupt request is generated when a block transfer is complete. Alternatively, an interrupt can be generated when half of the block has been filled. FIGURE 8-1: TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS Peripheral Indirect Address DMA Controller DMA SRAM DMA RAM MAntrol ChDaMnnAels PerRipehaedryal 3 DCo 0 1 2 3 PORT 1 PORT 2 CPU DMA SRAM X-Bus DMA DS Bus CPU Peripheral DS Bus CPU DMA CPU DMA Non-DMA DMA DMA CPU Ready Ready Ready Peripheral Peripheral 1 Peripheral 2 Note: For clarity, CPU and DMA address buses are not shown. DS70000591F-page 180  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 8-1: DMAxCON: DMA CHANNEL x CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CHEN SIZE DIR HALF NULLW — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — — AMODE1 AMODE0 — — MODE1 MODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHEN: DMA Channel Enable bit 1 = Channel is enabled 0 = Channel is disabled bit 14 SIZE: Data Transfer Size bit 1 = Byte 0 = Word bit 13 DIR: Transfer Direction bit (source/destination bus select) 1 = Reads from DMA RAM address; writes to peripheral address 0 = Reads from peripheral address; writes to DMA RAM address bit 12 HALF: Early Block Transfer Complete Interrupt Select bit 1 = Initiates block transfer complete interrupt when half of the data has been moved 0 = Initiates block transfer complete interrupt when all of the data has been moved bit 11 NULLW: Null Data Peripheral Write Mode Select bit 1 = Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear) 0 = Normal operation bit 10-6 Unimplemented: Read as ‘0’ bit 5-4 AMODE<1:0>: DMA Channel Operating Mode Select bits 11 = Reserved 10 = Peripheral Indirect Addressing mode 01 = Register Indirect without Post-Increment mode 00 = Register Indirect with Post-Increment mode bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 MODE<1:0>: DMA Channel Operating Mode Select bits 11 = One-Shot, Ping-Pong modes are enabled (one block transfer from/to each DMA RAM buffer) 10 = Continuous, Ping-Pong modes are enabled 01 = One-Shot, Ping-Pong modes are disabled 00 = Continuous, Ping-Pong modes are disabled  2009-2014 Microchip Technology Inc. DS70000591F-page 181

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 8-2: DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 FORCE(1) — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — IRQSEL6(2) IRQSEL5(2) IRQSEL4(2) IRQSEL3(2) IRQSEL2(2) IRQSEL1(2) IRQSEL0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FORCE: Force DMA Transfer bit(1) 1 = Forces a single DMA transfer (Manual mode) 0 = Automatic DMA transfer initiation by DMA request bit 14-7 Unimplemented: Read as ‘0’ bit 6-0 IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits(2) 0000000-1111111 = DMAIRQ0-DMAIRQ127 are selected to be Channel DMAREQ Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. 2: See Table8-1 for a complete listing of IRQ numbers for all interrupt sources. REGISTER 8-3: DMAxSTA: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER A R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STA<15:0>: Primary DMA RAM Start Address bits (source or destination) DS70000591F-page 182  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 8-4: DMAxSTB: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER B R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STB<15:0>: Secondary DMA RAM Start Address bits (source or destination) REGISTER 8-5: DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<15:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PAD<15:0>: Peripheral Address Register bits(2) Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: See Table8-1 for a complete list of peripheral addresses.  2009-2014 Microchip Technology Inc. DS70000591F-page 183

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 8-6: DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — CNT<9:8>(2) bit 15 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 CNT<9:0>: DMA Transfer Count Register bits(2) Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: Number of DMA transfers = CNT<9:0> + 1. DS70000591F-page 184  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 U-0 U-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 — — — — PWCOL3 PWCOL2 PWCOL1 PWCOL0 bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 — — — — XWCOL3 XWCOL2 XWCOL1 XWCOL0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11 PWCOL3: Channel 3 Peripheral Write Collision Flag bit 1 = Write collision is detected 0 = No write collision is detected bit 10 PWCOL2: Channel 2 Peripheral Write Collision Flag bit 1 = Write collision is detected 0 = No write collision is detected bit 9 PWCOL1: Channel 1 Peripheral Write Collision Flag bit 1 = Write collision is detected 0 = No write collision is detected bit 8 PWCOL0: Channel 0 Peripheral Write Collision Flag bit 1 = Write collision is detected 0 = No write collision is detected bit 7-4 Unimplemented: Read as ‘0’ bit 3 XWCOL3: Channel 3 DMA RAM Write Collision Flag bit 1 = Write collision is detected 0 = No write collision is detected bit 2 XWCOL2: Channel 2 DMA RAM Write Collision Flag bit 1 = Write collision is detected 0 = No write collision is detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision is detected 0 = No write collision is detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision is detected 0 = No write collision is detected  2009-2014 Microchip Technology Inc. DS70000591F-page 185

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 8-8: DMACS1: DMA CONTROLLER STATUS REGISTER 1 U-0 U-0 U-0 U-0 R-1 R-1 R-1 R-1 — — — — LSTCH3 LSTCH2 LSTCH1 LSTCH0 bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — PPST3 PPST2 PPST1 PPST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 LSTCH<3:0>: Last DMA Channel Active bits 1111 = No DMA transfer has occurred since system Reset 1110 = Reserved • • • 0100 = Reserved 0011 = Last data transfer was by DMA Channel 3 0010 = Last data transfer was by DMA Channel 2 0001 = Last data transfer was by DMA Channel 1 0000 = Last data transfer was by DMA Channel 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 PPST3: Channel 3 Ping-Pong Mode Status Flag bit 1 = DMA3STB register is selected 0 = DMA3STA register is selected bit 2 PPST2: Channel 2 Ping-Pong Mode Status Flag bit 1 = DMA2STB register is selected 0 = DMA2STA register is selected bit 1 PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMA1STB register is selected 0 = DMA1STA register is selected bit 0 PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMA0STB register is selected 0 = DMA0STA register is selected DS70000591F-page 186  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 8-9: DSADR: MOST RECENT DMA RAM ADDRESS REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits  2009-2014 Microchip Technology Inc. DS70000591F-page 187

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70000591F-page 188  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 9.0 OSCILLATOR The oscillator system provides: CONFIGURATION • External and Internal Oscillator Options as Clock Sources Note1: This data sheet summarizes the features • An On-Chip Phase-Locked Loop (PLL) to Scale of the dsPIC33FJ32GS406/606/608/610 the Internal Operating frequency to the Required and dsPIC33FJ64GS406/606/608/610 System Clock Frequency families of devices. It is not intended to • An Internal FRC Oscillator that can also be used be a comprehensive reference source. with the PLL, thereby allowing Full-Speed Operation To complement the information in this without any External Clock Generation Hardware data sheet, refer to “Oscillator (Part IV)” • Clock Switching Between Various Clock Sources (DS70307) in the “dsPIC33/PIC24 Family Reference Manual”, which is • Programmable Clock Postscaler for System available from the Microchip web site Power Savings (www.microchip.com). The information • A Fail-Safe Clock Monitor (FSCM) that Detects in this data sheet supersedes the Clock Failure and takes Fail-Safe Measures information in the FRM. • A Clock Control Register (OSCCON) 2: Some registers and associated bits • Nonvolatile Configuration bits for Main Oscillator described in this section may not be Selection available on all devices. Refer to • Auxiliary PLL for ADC and PWM Section4.0 “Memory Organization” in A simplified diagram of the oscillator system is shown this data sheet for device-specific register in Figure9-1. and bit information.  2009-2014 Microchip Technology Inc. DS70000591F-page 189

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 9-1: OSCILLATOR SYSTEM DIAGRAM Primary Oscillator (POSC) DOZE<2:0> OSC1 POSCCLK XT, HS, EC S2 R(2) SS31 PLL(1) EXCTPPLLLL, ,F HRSCPPLLLL, S1/S3 OZE FCY(4) OSC2 FVCO(1) D POSCMD<1:0> To ADC and Auxiliary Clock FP(4) Generator V ÷ 2 FRC DI FRCDIVN Oscillator FRC S7 FOSC FRCDIV<2:0> FRCDIV16 TUN<5:0> ÷ 16 S6 FRC S0 LPRC LPRC S5 Oscillator Secondary Oscillator (SOSC) SOSC SOSCO S4 LPOSCEN SOSCI Clock Fail Clock Switch Reset Reference Clock Generation S7 NOSC<2:0> FNOSC<2:0> WDT, PWRT, POSCCLK FSCM ÷ N Timer 1 FOSC REFCLKO(3) ROSEL RODIV<3:0> Auxiliary Clock Generation FRCCLK FVCO(1) POSCCLK APLL(1) ACLK To PWM/ADC(1) x16 ÷ N ASRCSEL FRCSEL ENAPLL SELACLK APSTSCLR<2:0> Note 1: See Section9.1.3 “PLL Configuration” and Section9.2 “Auxiliary Clock Generation” for configuration restrictions. 2: If the oscillator is used with XT or HS modes, an external parallel resistor with the value of 1Mmust be connected. 3: REFCLKO functionality is not available if the primary oscillator is used. 4: The term, FP, refers to the clock source for all the peripherals, while FCY refers to the clock source for the CPU. Throughout this document, FP and FCY are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode is used in any ratio other than 1:1, which is the default. DS70000591F-page 190  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 9.1 CPU Clocking System The clock signals generated by the FRC and primary oscillators can be optionally applied to an on-chip Phase- The dsPIC33FJ32GS406/606/608/610 and Locked Loop (PLL) to provide a wide range of output dsPIC33FJ64GS406/606/608/610 devices provide six frequencies for device operation. PLL configuration is system clock options: described in Section9.1.3 “PLL Configuration”. • Fast RC (FRC) Oscillator The FRC frequency depends on the FRC accuracy • FRC Oscillator with PLL (see Table27-20) and the value of the FRC Oscillator • Primary (XT, HS, or EC) Oscillator Tuning register (see Register9-4). • Primary Oscillator with PLL • Low-Power RC (LPRC) Oscillator 9.1.2 SYSTEM CLOCK SELECTION • FRC Oscillator with Postscaler The oscillator source used at a device Power-on Reset • Secondary (LP) Oscillator event is selected using Configuration bit settings. The 9.1.1 SYSTEM CLOCK SOURCES Oscillator Configuration bit settings are located in the Configuration registers in the program memory. (Refer to The Fast RC (FRC) internal oscillator runs at a nominal Section24.1 “Configuration Bits” for further details.) frequency of 7.37 MHz. User software can tune the The Initial Oscillator Selection Configuration bits, FRC frequency. User software can optionally specify a FNOSC<2:0> (FOSCSEL<2:0>), and the Primary Oscil- factor (ranging from 1:2 to 1:256) by which the FRC lator Mode Select Configuration bits, POSCMD<1:0> clock frequency is divided. This factor is selected using (FOSC<1:0>), select the oscillator source that is used at the FRCDIV<2:0> (CLKDIV<10:8>) bits. a Power-on Reset. The FRC primary oscillator is the The primary oscillator can use one of the following as default (unprogrammed) selection. its clock source: The Configuration bits allow users to choose among • XT (Crystal): Crystals and ceramic resonators in 12different clock modes, shown in Table9-1. the range of 3 MHz to 10 MHz. The crystal is The output of the oscillator (or the output of the PLL if connected to the OSC1 and OSC2 pins a PLL mode has been selected), FOSC, is divided by 2 • HS (High-Speed Crystal): Crystals in the range of to generate the device instruction clock (FCY) and the 10 MHz to 50 MHz. The crystal is connected to peripheral clock time base (FP). FCY defines the the OSC1 and OSC2 pins operating speed of the device and speeds up to • EC (External Clock): The external clock signal is 50MIPS are supported by the device architecture. directly applied to the OSC1 pin Instruction execution speed or device operating The secondary (LP) oscillator is designed for low power frequency, FCY, is given by Equation9-1. and uses a 32.768 kHz crystal or ceramic resonator. The LP oscillator uses the SOSCI and SOSCO pins. EQUATION 9-1: DEVICE OPERATING The LPRC internal oscillator runs at a nominal FREQUENCY frequency of 32.768 kHz. It is also used as a reference FCY = FOSC/2 clock by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> See Notes Fast RC Oscillator with Divide-by-N (FRCDIVN) Internal xx 111 1, 2 Fast RC Oscillator with Divide-by-16 (FRCDIV16) Internal xx 110 1 Low-Power RC Oscillator (LPRC) Internal xx 101 1 Secondary Oscillator (SOSC) Secondary xx 100 — Primary Oscillator (HS) with PLL (HSPLL) Primary 10 011 — Primary Oscillator (XT) with PLL (XTPLL) Primary 01 011 — Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1 Primary Oscillator (HS) Primary 10 010 — Primary Oscillator (XT) Primary 01 010 — Primary Oscillator (EC) Primary 00 010 1 Fast RC Oscillator with PLL (FRCPLL) Internal xx 001 1 Fast RC Oscillator (FRC) Internal xx 000 1 Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device.  2009-2014 Microchip Technology Inc. DS70000591F-page 191

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 9.1.3 PLL CONFIGURATION For a primary oscillator or FRC oscillator, output ‘FIN’, the PLL output ‘FOSC’ is given by Equation9-2. The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in EQUATION 9-2: FOSC CALCULATION selecting the device operating speed. A block diagram ( M ) of the PLL is shown in Figure9-2. FOSC = FIN * N1 * N2 The output of the primary oscillator or FRC, denoted as For example, suppose a 10 MHz crystal is being used ‘FIN’, is divided down by a prescale factor (N1) of 2, with the selected oscillator mode of XT with PLL (see 3,... or 33 before being provided to the PLL’s Voltage Equation9-3). Controlled Oscillator (VCO). The input to the VCO must be selected in the range of 0.8 MHz to 8 MHz. The • If PLLPRE<4:0> = 0000, then N1 = 2. This yields a VCO input of 10/2 = 5 MHz, which is within the prescale factor ‘N1’ is selected using the acceptable range of 0.8-8 MHz. PLLPRE<4:0> bits (CLKDIV<4:0>). • If PLLDIV<8:0> = 0x26, then M = 40. This yields a The PLL Feedback Divisor, selected using the VCO output of 5 x 40 = 200 MHz, which is within PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor, ‘M’, the 100-200 MHz ranged needed. by which the input to the VCO is multiplied. This factor must be selected such that the resulting VCO output • If PLLPOST<1:0> = 00, then N2 = 2. This pro- frequency is in the range of 100 MHz to 200 MHz. vides a FOSC of 200/2 = 100 MHz. The resultant device operating speed is 100/2 = 40 MIPS. The VCO output is further divided by a postscale factor, ‘N2’. This factor is selected using the PLLPOST<1:0> EQUATION 9-3: XT WITH PLL MODE bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and EXAMPLE must be selected such that the PLL output frequency (FOSC) is in the range of 12.5 MHz to 100 MHz, which FCY = FOSC = 1 (10000000 * 40) = 50 MIPS generates device operating speeds of 6.25-50 MIPS. 2 2 2 * 2 FIGURE 9-2: PLL BLOCK DIAGRAM FVCO 0.8-8.0 MHz 100-200 MHz 12.5-100 MHz Here(1) Here(1) Here(1,2) Source (Crystal, External Clock PLLPRE X VCO PLLPOST FOSC or Internal RC) PLLDIV N1 N2 Divide by Divide by 2-33 M 2, 4, 8 Divide by 2-513 Note 1: This frequency range must be met at all times. 2: This frequency range is not supported for all devices. DS70000591F-page 192  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 9.2 Auxiliary Clock Generation 9.3 Reference Clock Generation The auxiliary clock generation is used for a peripherals The reference clock output logic provides the user with that need to operate at a frequency unrelated to the the ability to output a clock signal based on the system system clock such as a PWM or ADC. clock or the crystal oscillator on a device pin. The user application can specify a wide range of clock scaling The primary oscillator and internal FRC oscillator prior to outputting the reference clock. sources can be used with an auxiliary PLL to obtain the auxiliary clock. The auxiliary PLL has a fixed 16x multiplication factor. The auxiliary clock has the following configuration restrictions: • For proper PWM operation, auxiliary clock generation must be configured for 120 MHz (see Parameter OS56 in Table27-18 in Section27.0 “Electrical Characteristics”). If a slower frequency is desired, the PWM Input Clock Prescaler (Divider) Select bits (PCLKDIV<2:0>) should be used. • To achieve 1.04 ns PWM resolution, the auxiliary clock must use the 16x auxiliary PLL (APLL). All other clock sources will have a minimum PWM resolution of 8 ns. • If the primary PLL is used as a source for the auxiliary clock, the primary PLL should be config- ured up to a maximum operation of 30 MIPS or less.  2009-2014 Microchip Technology Inc. DS70000591F-page 193

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 9.4 Oscillator Control Registers REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) U-0 R-y R-y R-y U-0 R/W-y R/W-y R/W-y — COSC2 COSC1 COSC0 — NOSC2(2) NOSC1(2) NOSC0(2) bit 15 bit 8 R/W-0 U-0 R-0 U-0 R/C-0 U-0 U-0 R/W-0 CLKLOCK — LOCK — CF — — OSWEN bit 7 bit 0 Legend: C = Clearable bit y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only) 111 = Fast RC Oscillator (FRC) with Divide-by-n 110 = Fast RC Oscillator (FRC) with Divide-by-16 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (XT, HS, EC) with PLL 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator (FRC) with PLL 000 = Fast RC Oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2) 111 = Fast RC Oscillator (FRC) with Divide-by-n 110 = Fast RC Oscillator (FRC) with Divide-by-16 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (XT, HS, EC) with PLL 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator (FRC) with PLL 000 = Fast RC Oscillator (FRC) bit 7 CLKLOCK: Clock Lock Enable bit If Clock Switching is Enabled and FSCM is Disabled (FCKSM<1:0> (FOSC<7:6>) = 0b01): 1 = Clock switching is disabled, system clock source is locked 0 = Clock switching is enabled, system clock source can be modified by clock switching bit 6 Unimplemented: Read as ‘0’ bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled bit 4 Unimplemented: Read as ‘0’ Note 1: Writes to this register require an unlock sequence. Refer to “Oscillator (Part IV)” (DS70307) in the “dsPIC33/PIC24 Family Reference Manual” for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. DS70000591F-page 194  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED) bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2-1 Unimplemented: Read as ‘0’ bit 0 OSWEN: Oscillator Switch Enable bit 1 = Requests oscillator switch to the selection specified by the NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Writes to this register require an unlock sequence. Refer to “Oscillator (Part IV)” (DS70307) in the “dsPIC33/PIC24 Family Reference Manual” for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.  2009-2014 Microchip Technology Inc. DS70000591F-page 195

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 ROI DOZE2 DOZE1 DOZE0 DOZEN(1) FRCDIV2 FRCDIV1 FRCDIV0 bit 15 bit 8 R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PLLPOST1 PLLPOST0 — PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits 111 = FCY/128 110 = FCY/64 101 = FCY/32 100 = FCY/16 011 = FCY/8 (default) 010 = FCY/4 001 = FCY/2 000 = FCY/1 bit 11 DOZEN: Doze Mode Enable bit(1) 1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock/peripheral clock ratio forced to 1:1 bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits 111 = FRC divide-by-256 110 = FRC divide-by-64 101 = FRC divide-by-32 100 = FRC divide-by-16 011 = FRC divide-by-8 010 = FRC divide-by-4 001 = FRC divide-by-2 000 = FRC divide-by-1 (default) bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler) 11 = Output/8 10 = Reserved 01 = Output/4 (default) 00 = Output/2 bit 5 Unimplemented: Read as ‘0’ bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 • • • 11111 = Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. DS70000591F-page 196  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV8 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513  2009-2014 Microchip Technology Inc. DS70000591F-page 197

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 9-4: OSCTUN: OSCILLATOR TUNING REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Center Frequency + 2.91% (7.584 MHz) 011110 = Center Frequency + 2.81% (7.577 MHz) • • • 000001 = Center Frequency + 0.0938% (7.377 MHz) 000000 = Center Frequency (7.37 MHz nominal) 111111 = Center Frequency – 0.0938% (7.363 MHz) • • • 100001 = Center Frequency – 2.91% (7.156 MHz) 100000 = Center Frequency – 3% (7.149 MHz) Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step-size is an approximation and is neither characterized nor tested. DS70000591F-page 198  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 9-5: ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER R/W-0 R-0 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 ENAPLL APLLCK SELACLK — — APSTSCLR2 APSTSCLR1 APSTSCLR0 bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ASRCSEL FRCSEL — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ENAPLL: Auxiliary PLL Enable bit 1 = APLL is enabled 0 = APLL is disabled bit 14 APLLCK: APLL Locked Status bit (read-only) 1 = Indicates that auxiliary PLL is in lock 0 = Indicates that auxiliary PLL is not in lock bit 13 SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit 1 = Auxiliary oscillators provide the source clock for the auxiliary clock divider 0 = Primary PLL (FVCO) provides the source clock for the auxiliary clock divider bit 12-11 Unimplemented: Read as ‘0’ bit 10-8 APSTSCLR<2:0>: Auxiliary Clock Output Divider bits 111 = Divided by 1 110 = Divided by 2 101 = Divided by 4 100 = Divided by 8 011 = Divided by 16 010 = Divided by 32 001 = Divided by 64 000 = Divided by 256 bit 7 ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit 1 = Primary oscillator is the clock source 0 = No clock input is selected bit 6 FRCSEL: Select Reference Clock Source for Auxiliary PLL bit 1 = Selects FRC clock for auxiliary PLL 0 = Input clock source is determined by the ASRCSEL bit setting bit 5-0 Unimplemented: Read as ‘0’  2009-2014 Microchip Technology Inc. DS70000591F-page 199

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 9-6: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROON — ROSSLP ROSEL RODIV3(1) RODIV2(1) RODIV1(1) RODIV0(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator output is enabled on the REFCLK0 pin 0 = Reference oscillator output is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ROSSLP: Reference Oscillator Run in Sleep bit 1 = Reference oscillator output continues to run in Sleep mode 0 = Reference oscillator output is disabled in Sleep mode bit 12 ROSEL: Reference Oscillator Source Select bit 1 = Oscillator crystal is used as the reference clock 0 = System clock is used as the reference clock bit 11-8 RODIV<3:0>: Reference Oscillator Divider bits(1) 1111 = Reference clock divided by 32,768 1110 = Reference clock divided by 16,384 1101 = Reference clock divided by 8,192 1100 = Reference clock divided by 4,096 1011 = Reference clock divided by 2,048 1010 = Reference clock divided by 1,024 1001 = Reference clock divided by 512 1000 = Reference clock divided by 256 0111 = Reference clock divided by 128 0110 = Reference clock divided by 64 0101 = Reference clock divided by 32 0100 = Reference clock divided by 16 0011 = Reference clock divided by 8 0010 = Reference clock divided by 4 0001 = Reference clock divided by 2 0000 = Reference clock bit 7-0 Unimplemented: Read as ‘0’ Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits. DS70000591F-page 200  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 9.5 Clock Switching Operation 2. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and the CF (OSCCON<3>) status Applications are free to switch among any of the four bits are cleared. clock sources (primary, LP, FRC and LPRC) under 3. The new oscillator is turned on by the hardware if software control at any time. To limit the possible side it is not currently running. If a crystal oscillator effects of this flexibility, dsPIC33FJ32GS406/606/608/ must be turned on, the hardware waits until the 610 and dsPIC33FJ64GS406/606/608/610 devices Oscillator Start-up Timer (OST) expires. If the new have a safeguard lock built into the switch process. source is using the PLL, the hardware waits until a Note: Primary oscillator mode has three different PLL lock is detected (LOCK = 1). submodes (XT, HS and EC), which are 4. The hardware waits for 10 clock cycles from the determined by the POSCMD<1:0> Config- new clock source and then performs the clock uration bits. While an application can switch. switch to and from primary oscillator 5. The hardware clears the OSWEN bit to indicate a mode in software, it cannot switch among successful clock transition. In addition, the NOSCx the different primary submodes without bit values are transferred to the COSCx status bits. reprogramming the device. 6. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM are 9.5.1 ENABLING CLOCK SWITCHING enabled) or LP (if LPOSCEN remains set). To enable clock switching, the FCKSM1 Configuration bit Note1: The processor continues to execute code in the FOSC Configuration register must be programmed throughout the clock switching sequence. to ‘0’. (Refer to Section24.1 “Configuration Bits” for Timing-sensitive code should not be further details.) If the FCKSM1 Configuration bit is unpro- executed during this time. grammed (‘1’), the clock switching function and Fail-Safe Clock Monitor function are disabled; this is the default 2: Direct clock switches between any pri- setting. mary oscillator mode with PLL and FRCPLL mode are not permitted. This The NOSC control bits (OSCCON<10:8>) do not applies to clock switches in either direc- control the clock selection when clock switching is tion. In these instances, the application disabled. However, the COSC bits (OSCCON<14:12>) must switch to FRC mode as a transition reflect the clock source selected by the FNOSC<2:0> clock source between the two PLL modes. Configuration bits. 3: Refer to “Oscillator (Part IV)” (DS70307) The OSWEN control bit (OSCCON<0>) has no effect in the “dsPIC33/PIC24 Family Reference when clock switching is disabled; it is held at ‘0’ at all Manual” for details. times. 9.6 Fail-Safe Clock Monitor (FSCM) 9.5.2 OSCILLATOR SWITCHING SEQUENCE To perform a clock switch, the following basic sequence The Fail-Safe Clock Monitor (FSCM) allows the device is required: to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by programming. 1. If desired, read the COSCx bits (OSCCON<14:12>) If the FSCM function is enabled, the LPRC internal to determine the current oscillator source. oscillator runs at all times (except during Sleep mode) 2. Perform the unlock sequence to allow a write to and is not subject to control by the Watchdog Timer. the OSCCON register high byte. In the event of an oscillator failure, the FSCM 3. Write the appropriate value to the NOSCx control generates a clock failure trap event and switches the bits (OSCCON<10:8>) for the new oscillator system clock over to the FRC oscillator. Then, the source. application program can either attempt to restart the 4. Perform the unlock sequence to allow a write to oscillator or execute a controlled shutdown. The trap the OSCCON register low byte. can be treated as a Warm Reset by simply loading the 5. Set the OSWEN bit (OSCCON<0>) to initiate the Reset address into the oscillator fail trap vector. oscillator switch. If the PLL multiplier is used to scale the system clock, Once the basic sequence is completed, the system the internal FRC is also multiplied by the same factor clock hardware responds automatically as follows: on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. 1. The clock switching hardware compares the COSCx status bits with the new value of the NOSCx control bits. If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted.  2009-2014 Microchip Technology Inc. DS70000591F-page 201

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70000591F-page 202  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 10.0 POWER-SAVING FEATURES 10.2 Instruction-Based Power-Saving Modes Note1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 The devices have two special power-saving modes that and dsPIC33FJ64GS406/606/608/610 are entered through the execution of a special PWRSAV families of devices. It is not intended to be instruction. Sleep mode stops clock operation and halts all a comprehensive reference source. To code execution. Idle mode halts the CPU and code complement the information in this data execution, but allows peripheral modules to continue sheet, refer to “Watchdog Timer and operation. The assembler syntax of the PWRSAV Power-Saving Modes” (DS70196) in the instruction is shown in Example10-1. “dsPIC33/PIC24 Family Reference Man- Note: SLEEP_MODE and IDLE_MODE are ual”, which is available from the Microchip constants defined in the assembler web site (www.microchip.com). The infor- include file for the selected device. mation in this data sheet supersedes the information in the FRM. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When 2: Some registers and associated bits the device exits these modes, it is said to wake-up. described in this section may not be available on all devices. Refer to 10.2.1 SLEEP MODE Section4.0 “Memory Organization” in this data sheet for device-specific register The following occurs in Sleep mode: and bit information. • The system clock source is shut down. If an on-chip oscillator is used, it is turned off. The dsPIC33FJ32GS406/606/608/610 and • The device current consumption is reduced to a dsPIC33FJ64GS406/606/608/610 devices provide minimum, provided that no I/O pin is sourcing the ability to manage power consumption by selectively current. managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the • The Fail-Safe Clock Monitor does not operate, number of circuits being clocked constitutes lower since the system clock source is disabled. consumed power. Devices can manage power • The LPRC clock continues to run in Sleep mode if consumption in four different ways: the WDT is enabled. • Clock Frequency • The WDT, if enabled, is automatically cleared prior to entering Sleep mode. • Instruction-Based Sleep and Idle modes • Some device features or peripherals may continue • Software Controlled Doze mode to operate. This includes the items such as the • Selective Peripheral Control in Software Input Change Notification on the I/O ports or Combinations of these methods can be used to peripherals that use an external clock input. selectively tailor an application’s power consumption • Any peripheral that requires the system clock while still maintaining critical application features, such source for its operation is disabled. as timing-sensitive communications. The device will wake-up from Sleep mode on any of these events: 10.1 Clock Frequency and Clock Switching • Any interrupt source that is individually enabled • Any form of device Reset The devices allow a wide range of clock frequencies to • A WDT time-out be selected under application control. If the system On wake-up from Sleep mode, the processor restarts clock configuration is not locked, users can choose with the same clock source that was active when Sleep low-power or high-precision oscillators by simply mode was entered. changing the NOSCx bits (OSCCON<10:8>). The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section9.0 “Oscillator Configuration”. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode  2009-2014 Microchip Technology Inc. DS70000591F-page 203

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 10.2.2 IDLE MODE Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core The following occur in Idle mode: clock speed is determined by the DOZE<2:0> bits • The CPU stops executing instructions. (CLKDIV<14:12>). There are eight possible configura- • The WDT is automatically cleared. tions, from 1:1 to 1:128, with 1:1 being the default • The system clock source remains active. By setting. default, all peripheral modules continue to operate Programs can use Doze mode to selectively reduce normally from the system clock source, but can power consumption in event-driven applications. This also be selectively disabled (see Section10.5 allows clock-sensitive functions, such as synchronous “Peripheral Module Disable”). communications, to continue without interruption while • If the WDT or FSCM is enabled, the LPRC also the CPU idles, waiting for something to invoke an remains active. interrupt routine. An automatic return to full-speed CPU operation on interrupts can be enabled by setting the The device will wake-up from Idle mode on any of these ROI bit (CLKDIV<15>). By default, interrupt events events: have no effect on Doze mode operation. • Any interrupt that is individually enabled For example, suppose the device is operating at • Any device Reset 20MIPS and the ECAN module has been configured • A WDT time-out for 500 kbps based on this device operating speed. If On wake-up from Idle mode, the clock is reapplied to the device is placed in Doze mode with a clock the CPU and instruction execution will begin (2-4 clock frequency ratio of 1:4, the ECAN module continues to cycles later), starting with the instruction following the communicate at the required bit rate of 500 kbps, but PWRSAV instruction, or the first instruction in the ISR. the CPU now starts executing instructions at a frequency of 5 MIPS. 10.2.3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS 10.4 PWM Power-Saving Features Any interrupt that coincides with the execution of a PWRSAV instruction is held off until entry into Sleep or Typically, many applications need either a high- Idle mode has completed. The device then wakes up resolution duty cycle or phase offset (for fixed from Sleep or Idle mode. frequency operation) or a high-resolution PWM period for variable frequency modes of operation (such as Resonant mode). Very few applications require both 10.3 Doze Mode high-resolution modes simultaneously. The preferred strategies for reducing power The HRPDIS and the HRDDIS bits in the AUXCONx consumption are changing clock speed and invoking registers permit the user to disable the circuitry associ- one of the power-saving modes. In some circumstances, ated with the high-resolution duty cycle and PWM this may not be practical. For example, it may be neces- period to reduce the operating current of the device. sary for an application to maintain uninterrupted If the HRDDIS bit is set, the circuitry associated with synchronous communication, even while it is doing noth- the high-resolution duty cycle, phase offset and dead ing else. Reducing system clock speed can introduce time for the respective PWM generator, is disabled. If communication errors, while using a power-saving mode the HRPDIS bit is set, the circuitry associated with the can stop communications completely. high-resolution PWM period for the respective PWM Doze mode is a simple and effective alternative method generator is disabled. to reduce power consumption while the device is still When the HRPDIS bit is set, the smallest unit of executing code. In this mode, the system clock measure for the PWM period is 8.32 ns. continues to operate from the same source and at the same speed. Peripheral modules continue to be If the HRDDIS bit is set, the smallest unit of measure clocked at the same speed, while the CPU clock speed for the PWM duty cycle, phase offset and dead time is is reduced. Synchronization between the two clock 8.32 ns. domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. DS70000591F-page 204  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 10.5 Peripheral Module Disable Note: If a PMD bit is set, the corresponding module is disabled after a delay of one The Peripheral Module Disable (PMD) registers instruction cycle. Similarly, if a PMD bit is provide a method to disable a peripheral module by cleared, the corresponding module is stopping all clock sources supplied to that module. enabled after a delay of one instruction When a peripheral is disabled using the appropriate cycle (assuming the module control regis- PMD control bit, the peripheral is in a minimum power ters are already configured to enable consumption state. The control and status registers module operation). associated with the peripheral are also disabled, so writes to those registers will have no effect and read values will be invalid. A peripheral module is enabled only if both the associated bit in the PMD register is cleared and the peripheral is supported by the specific dsPIC® DSC variant. If the peripheral is present in the device, it is enabled in the PMD register by default.  2009-2014 Microchip Technology Inc. DS70000591F-page 205

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD(1) — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD ADCMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 T5MD: Timer5 Module Disable bit 1 = Timer5 module is disabled 0 = Timer5 module is enabled bit 14 T4MD: Timer4 Module Disable bit 1 = Timer4 module is disabled 0 = Timer4 module is enabled bit 13 T3MD: Timer3 Module Disable bit 1 = Timer3 module is disabled 0 = Timer3 module is enabled bit 12 T2MD: Timer2 Module Disable bit 1 = Timer2 module is disabled 0 = Timer2 module is enabled bit 11 T1MD: Timer1 Module Disable bit 1 = Timer1 module is disabled 0 = Timer1 module is enabled bit 10 QEI1MD: QEI1 Module Disable bit 1 = QEI1 module is disabled 0 = QEI1 module is enabled bit 9 PWMMD: PWM Module Disable bit(1) 1 = PWM module is disabled 0 = PWM module is enabled bit 8 Unimplemented: Read as ‘0’ bit 7 I2C1MD: I2C1 Module Disable bit 1 = I2C1 module is disabled 0 = I2C1 module is enabled bit 6 U2MD: UART2 Module Disable bit 1 = UART2 module is disabled 0 = UART2 module is enabled bit 5 U1MD: UART1 Module Disable bit 1 = UART1 module is disabled 0 = UART1 module is enabled bit 4 SPI2MD: SPI2 Module Disable bit 1 = SPI2 module is disabled 0 = SPI2 module is enabled Note 1: Once the PWM module is re-enabled (PWMMD is set to ‘1’ and then set to ‘0’), all PWM registers must be re-initialized. DS70000591F-page 206  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED) bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2 Unimplemented: Read as ‘0’ bit 1 C1MD: ECAN1 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 ADCMD: ADC Module Disable bit 1 = ADC module is disabled 0 = ADC module is enabled Note 1: Once the PWM module is re-enabled (PWMMD is set to ‘1’ and then set to ‘0’), all PWM registers must be re-initialized.  2009-2014 Microchip Technology Inc. DS70000591F-page 207

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — IC4MD IC3MD IC2MD IC1MD bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — OC4MD OC3MD OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11 IC4MD: Input Capture 4 Module Disable bit 1 = Input Capture 4 module is disabled 0 = Input Capture 4 module is enabled bit 19 IC3MD: Input Capture 3 Module Disable bit 1 = Input Capture 3 module is disabled 0 = Input Capture 3 module is enabled bit 9 IC2MD: Input Capture 2 Module Disable bit 1 = Input Capture 2 module is disabled 0 = Input Capture 2 module is enabled bit 8 IC1MD: Input Capture 1 Module Disable bit 1 = Input Capture 1 module is disabled 0 = Input Capture 1 module is enabled bit 7-4 Unimplemented: Read as ‘0’ bit 3 OC4MD: Output Compare 4 Module Disable bit 1 = Output Compare 4 module is disabled 0 = Output Compare 4 module is enabled bit 2 OC3MD: Output Compare 3 Module Disable bit 1 = Output Compare 3 module is disabled 0 = Output Compare 3 module is enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled DS70000591F-page 208  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 — — — — — CMPMD — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0 — — QEI2MD — — — I2C2MD — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Analog Comparator Module Disable bit 1 = Analog comparator module is disabled 0 = Analog comparator module is enabled bit 9-6 Unimplemented: Read as ‘0’ bit 5 QEI2MD: QEI2 Module Disable bit 1 = QEI2 module is disabled 0 = QEI2 module is enabled bit 4-2 Unimplemented: Read as ‘0’ bit 1 I2C2MD: I2C2 Module Disable bit 1 = I2C2 module is disabled 0 = I2C2 module is enabled bit 0 Unimplemented: Read as ‘0’ REGISTER 10-4: PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 — — — — REFOMD — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 REFOMD: Reference Clock Generator Module Disable bit 1 = Reference clock generator module is disabled 0 = Reference clock generator module is enabled bit 2-0 Unimplemented: Read as ‘0’  2009-2014 Microchip Technology Inc. DS70000591F-page 209

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 10-5: PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWM8MD PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWM8MD: PWM Generator 8 Module Disable bit 1 = PWM Generator 8 module is disabled 0 = PWM Generator 8 module is enabled bit 14 PWM7MD: PWM Generator 7 Module Disable bit 1 = PWM Generator 7 module is disabled 0 = PWM Generator 7 module is enabled bit 13 PWM6MD: PWM Generator 6 Module Disable bit 1 = PWM Generator 6 module is disabled 0 = PWM Generator 6 module is enabled bit 12 PWM5MD: PWM Generator 5 Module Disable bit 1 = PWM Generator 5 module is disabled 0 = PWM Generator 5 module is enabled bit 11 PWM4MD: PWM Generator 4 Module Disable bit 1 = PWM Generator 4 module is disabled 0 = PWM Generator 4 module is enabled bit 10 PWM3MD: PWM Generator 3 Module Disable bit 1 = PWM Generator 3 module is disabled 0 = PWM Generator 3 module is enabled bit 9 PWM2MD: PWM Generator 2 Module Disable bit 1 = PWM Generator 2 module is disabled 0 = PWM Generator 2 module is enabled bit 8 PWM1MD: PWM Generator 1 Module Disable bit 1 = PWM Generator 1 module is disabled 0 = PWM Generator 1 module is enabled bit 7-0 Unimplemented: Read as ‘0’ DS70000591F-page 210  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 10-6: PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CMP4MD CMP3MD CMP2MD CMP1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PWM9MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11 CMP4MD: Analog Comparator 4 Module Disable bit 1 = Analog Comparator 4 module is disabled 0 = Analog Comparator 4 module is enabled bit 10 CMP3MD: Analog Comparator 3 Module Disable bit 1 = Analog Comparator 3 module is disabled 0 = Analog Comparator 3 module is enabled bit 9 CMP2MD: Analog Comparator 2 Module Disable bit 1 = Analog Comparator 2 module is disabled 0 = Analog Comparator 2 module is enabled bit 8 CMP1MD: Analog Comparator 1 Module Disable bit 1 = Analog Comparator 1 module is disabled 0 = Analog Comparator 1 module is enabled bit 7-1 Unimplemented: Read as ‘0’ bit 0 PWM9MD: PWM Generator 9 Module Disable bit 1 = PWM Generator 9 module is disabled 0 = PWM Generator 9 module is enabled  2009-2014 Microchip Technology Inc. DS70000591F-page 211

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70000591F-page 212  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 11.0 I/O PORTS When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as Note1: This data sheet summarizes the features a general purpose output pin is disabled. The I/O pin of the dsPIC33FJ32GS406/606/608/610 can be read, but the output driver for the parallel port bit and dsPIC33FJ64GS406/606/608/610 is disabled. If a peripheral is enabled, but the peripheral families of devices. It is not intended to be is not actively driving a pin, that pin can be driven by a a comprehensive reference source. To port. complement the information in this data All port pins have three registers directly associated sheet, refer to “I/O Ports” (DS70193) in with their operation as digital I/O. The Data Direction the “dsPIC33/PIC24 Family Reference register (TRISx) determines whether the pin is an input Manual”, which is available from the Micro- or an output. If the data direction bit is ‘1’, then the pin chip web site (www.microchip.com). The is an input. All port pins are defined as inputs after a information in this data sheet supersedes Reset. Reads from the latch (LATx) read the latch. the information in the FRM. Writes to the latch write the latch. Reads from the port 2: Some registers and associated bits (PORTx) read the port pins, while writes to the port pins described in this section may not be write the latch. available on all devices. Refer to Any bit and its associated data and control registers Section4.0 “Memory Organization” in that are not valid for a particular device will be this data sheet for device-specific register disabled. That means the corresponding LATx and and bit information. TRISx registers and the port pin will read as zeros. All of the device pins (except VDD, VSS, MCLR and When a pin is shared with another peripheral or OSC1/CLKI) are shared among the peripherals and the function that is defined as an input only, it is parallel I/O ports. All I/O input ports feature Schmitt nevertheless regarded as a dedicated port because Trigger inputs for improved noise immunity. there is no other competing source of outputs. 11.1 Parallel I/O (PIO) Ports Generally a parallel I/O port that shares a pin with a peripheral is subservient to the peripheral. The peripheral’s output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. Figure11-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected.  2009-2014 Microchip Technology Inc. DS70000591F-page 213

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data Read TRIS 0 Data Bus D Q I/O Pin WR TRIS CK TRIS Latch D Q WR LAT + CK WR PORT Data Latch Read LAT Input Data Read PORT DS70000591F-page 214  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 11.2 Open-Drain Configuration 11.4 I/O Port Write/Read Timing In addition to the PORTx, LATx and TRISx registers for One instruction cycle is required between a port direction data control, some digital only port pins can also be change or port write operation and a read operation of individually configured for either digital or open-drain the same port. Typically, this instruction would be a NOP. output. This is controlled by the Open-Drain Control An example is shown in Example11-1. register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an 11.5 Input Change Notification (ICN) open-drain output. The Input Change Notification function of the I/O The open-drain feature allows the generation of ports allows the dsPIC33FJ32GS406/606/608/610 outputs higher than VDD (for example, 5V) on any and dsPIC33FJ64GS406/606/608/610 devices to gen- desired 5V tolerant pins by using external pull-up erate interrupt requests to the processor in response to resistors. The maximum open-drain voltage allowed is a Change-of-State (COS) on selected input pins. This the same as the maximum VIH specification. feature can detect input Change-of-States even in Refer to “Pin Diagrams” for the available pins and Sleep mode, when the clocks are disabled. Depending their functionality. on the device pin count, up to 30 external signals (CNx pin) can be selected (enabled) for generating an 11.3 Configuring Analog Port Pins interrupt request on a Change-of-State. Four control registers are associated with the Change The ADPCFG and TRISx registers control the Notification (CN) module. The CNEN1 and CNEN2 operation of the Analog-to-Digital port pins. The port registers contain the interrupt enable control bits for pins that are to function as analog inputs must have each of the CN input pins. Setting any of these bits their corresponding TRISx bit set (input). If the TRISx enables an CN interrupt for the corresponding pins. bit is cleared (output), the digital output level (VOH or VOL) will be converted. Each CN pin also has a weak pull-up connected to it. The pull-ups act as a current source connected to the The ADPCFG and ADPCFG2 registers have a default pin and eliminate the need for external resistors when value of 0x000; therefore, all pins that share ANx the push button or keypad devices are connected. The functions are analog (not digital) by default. pull-ups are enabled separately using the CNPU1 and When the PORTx register is read, all pins configured as CNPU2 registers, which contain the control bits for analog input channels will read as cleared (a low level). each of the CN pins. Setting any of the control bits Pins configured as digital inputs will not convert an enables the weak pull-ups for the corresponding pins. analog input. Analog levels on any pin defined as a Note: Pull-ups on Change Notification pins digital input (including the ANx pins) can cause the should always be disabled when the port input buffer to consume current that exceeds the pin is configured as a digital output. device specifications. EQUATION 11-1: PORT WRITE/READ EXAMPLE MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs MOV W0, TRISBB ; and PORTB<7:0> as outputs NOP ; Delay 1 cycle BTSS PORTB, #13 ; Next Instruction  2009-2014 Microchip Technology Inc. DS70000591F-page 215

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70000591F-page 216  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 12.0 TIMER1 The unique features of Timer1 allow it to be used for Real-Time Clock (RTC) applications. A block diagram Note1: This data sheet summarizes the features of Timer1 is shown in Figure12-1. of the dsPIC33FJ32GS406/606/608/610 The Timer1 module can operate in one of the following and dsPIC33FJ64GS406/606/608/610 modes: families of devices. It is not intended to be a comprehensive reference source. To • Timer mode complement the information in this data • Gated Timer mode sheet, refer to “Timers” (DS70205) in the • Synchronous Counter mode “dsPIC33/PIC24 Family Reference Man- • Asynchronous Counter mode ual”, which is available from the Microchip In Timer and Gated Timer modes, the input clock is web site (www.microchip.com). The infor- mation in this data sheet supersedes the derived from the internal instruction cycle clock (FCY). In Synchronous and Asynchronous Counter modes, information in the FRM. the input clock is derived from the external clock input 2: Some registers and associated bits at the T1CK pin. described in this section may not be The Timer modes are determined by the following bits: available on all devices. Refer to Section4.0 “Memory Organization” in • Timer Clock Source Control bit: TCS (T1CON<1>) this data sheet for device-specific register • Timer Synchronization Control bit: TSYNC and bit information. (T1CON<2>) • Timer Gate Control bit: TGATE (T1CON<6>) The Timer1 module is a 16-bit timer, which can serve as a time counter for the Real-Time Clock (RTC), or The timer control bit settings for different operating operate as a free-running interval timer/counter. modes are given in the Table12-1. The Timer1 module has the following unique features TABLE 12-1: TIMER MODE SETTINGS over other timers: • Can be operated from the low-power 32.767 kHz Mode TCS TGATE TSYNC crystal oscillator available on the device. Timer 0 0 x • Can be operated in Asynchronous Counter mode Gated Timer 0 1 x from an external clock source. Synchronous 1 x 1 • The external clock input (T1CK) can optionally be Counter synchronized to the internal device clock and the Asynchronous 1 x 0 clock synchronization is performed after the Counter prescaler. FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM Gate Falling Edge 1 Sync Detect Set T1IF Flag 0 FCY Prescaler 10 (/n) Reset TGATE 00 TMR1 TCKPS<1:0> 0 T1CK x1 Equal Prescaler Sync 1 Comparator (/n) TGATE TSYNC TCKPS<1:0> TCS PR1  2009-2014 Microchip Technology Inc. DS70000591F-page 217

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timer1 Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>:Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronizes external clock input 0 = Does not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = External clock from T1CK pin (on the rising edge) 0 = Internal clock (FCY) bit 0 Unimplemented: Read as ‘0’ DS70000591F-page 218  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 13.0 TIMER2/3/4/5 FEATURES Timer2 and Timer4 are Type B timers that offer the following major features: Note 1: This data sheet summarizes the features • A Type B Timer can be Concatenated with a of the dsPIC33FJ32GS406/606/608/610 TypeC Timer to form a 32-Bit Timer and dsPIC33FJ64GS406/606/608/610 • At Least One Type B Timer Has the Ability to families of devices. It is not intended to be Trigger an Analog-to-Digital Conversion a comprehensive reference source. To • External Clock Input (TxCK) is Always Synchronized complement the information in this data to the Internal Device Clock and the Clock sheet, refer to “Timers” (DS70205) in the Synchronization is Performed after the Prescaler “dsPIC33/PIC24 Family Reference Man- ual”, which is available from the Microchip Figure13-1 shows a block diagram of the Type B timer. web site (www.microchip.com). The infor- Timer3 and Timer5 are Type C timers that offer the mation in this data sheet supersedes the following major features: information in the FRM. • A Type C Timer can be Concatenated with a 2: Some registers and associated bits TypeB Timer to form a 32-Bit Timer described in this section may not be • External Clock Input (TxCK) is Always Synchronized available on all devices. Refer to to the Internal Device Clock and the Clock Section4.0 “Memory Organization” in Synchronization is Performed before the Prescaler this data sheet for device-specific register A block diagram of the Type C timer is shown in and bit information. Figure13-2. Note: Timer3 is not available on all devices. FIGURE 13-1: TYPE B TIMER BLOCK DIAGRAM (x = 2, 4) Gate Falling Edge 1 Sync Detect Set TxIF Flag FCY Prescaler 10 0 (/n) Reset 00 TMRx TGATE TCKPS<1:0> Prescaler Sync x1 Equal ADC SOC Trigger (/n) Comparator TxCK TCKPS<1:0> TGATE PRx TCS FIGURE 13-2: TYPE C TIMER BLOCK DIAGRAM (x = 3, 5) Gate Falling Edge 1 Sync Detect Set TxIF Flag Prescaler 10 0 FCY (/n) Reset 00 TMRx TGATE TCKPS<1:0> Prescaler Sync x1 Equal (/n) Comparator TxCK TCKPS<1:0> TGATE PRx TCS  2009-2014 Microchip Technology Inc. DS70000591F-page 219

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 The Timer2/3/4/5 modules can operate in one of the When configured for 32-bit operation, only the Type B following modes: Timerx Control (TxCON) register bits are required for setup and control while the Type C Timer Control • Timer mode register bits are ignored (except the TSIDL bit). • Gated Timer mode For interrupt control, the combined 32-bit timer uses • Synchronous Counter mode the interrupt enable, interrupt flag and interrupt priority In Timer and Gated Timer modes, the input clock is control bits of the Type C timer. The interrupt control derived from the internal instruction cycle clock (FCY). and status bits for the TypeB timer are ignored In Synchronous Counter mode, the input clock is during32-bit timer operation. derived from the external clock input at the TxCK pin. The timers that can be combined to form a 32-bit timer The timer modes are determined by the following bits: are listed in Table13-2. • TCS (TxCON<1>): Timer Clock Source Control bit • TGATE (TxCON<6>): Timer Gate Control bit TABLE 13-2: 32-BIT TIMER Timer control bit settings for different operating modes Type B Timer (lsw) Type C Timer (msw) are given in the Table13-1. Timer2 Timer3 TABLE 13-1: TIMER MODE SETTINGS TImer4 Timer5 A block diagram representation of the 32-bit timer Mode TCS TGATE module is shown in Figure13-3. The 32-timer module Timer 0 0 can operate in one of the following modes: Gated Timer 0 1 • Timer mode Synchronous Counter 1 x • Gated Timer mode • Synchronous Counter mode 13.1 16-Bit Operation To configure the timer features for 32-bit operation: To configure any of the timers for individual 16-bit 1. Set the T32 control bit. operation: 2. Select the prescaler ratio for Timer2 using the 1. Clear the T32 bit corresponding to that timer. TCKPS<1:0> bits. 2. Select the timer prescaler ratio using the 3. Set the Clock and Gating modes using the TCKPS<1:0> bits. corresponding TCS and TGATE bits. 3. Set the Clock and Gating modes using the TCS 4. Load the timer period value. PR3 contains the and TGATE bits. most significant word of the value, while PR2 contains the least significant word. 4. Load the timer period value into the PRx register. 5. If interrupts are required, set the interrupt enable bit, T3IE. Use the priority bits, T3IP<2:0>, to set 5. If interrupts are required, set the interrupt enable the interrupt priority. While Timer2 controls the bit, TxIE. Use the priority bits, TxIP<2:0>, to set timer, the interrupt appears as a Timer3 the interrupt priority. interrupt. 6. Set the TON bit. 6. Set the corresponding TON bit. 13.2 32-Bit Operation A 32-bit timer module can be formed by combining a Type B and a Type C 16-bit timer module. For 32-bit timer operation, the T32 control bit in the Type B Timer Control (TxCON<3>) register must be set. The Type C timer holds the most significant word (msw) and the Type B timer holds the least significant word (lsw) for32-bit operation. DS70000591F-page 220  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 13-3: 32-BIT TIMER BLOCK DIAGRAM Gate Falling Edge Sync Detect 1 Set TyIF Flag PRx PRy 0 Equal Comparator TGATE FCY Prescaler 10 (/n) lsw msw Reset 00 TMRx(1) TMRy(2) TCKPS<1:0> Prescaler Sync x1 (/n) TxCK TMRyHLD TCKPS<1:0> TGATE TCS Data Bus <15:0> Note 1: Timerx is a Type B Timer (x = 2, 4). 2: Timery is a Type C Timer (y = 3, 5).  2009-2014 Microchip Technology Inc. DS70000591F-page 221

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 13-1: TxCON: TIMERx CONTROL REGISTER (x = 2, 4) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timerx On bit When T32 = 1 (in 32-Bit Timer mode): 1 = Starts 32-bit TMRx:TMRy timer pair 0 = Stops 32-bit TMRx:TMRy timer pair When T32 = 0 (in 16-Bit Timer mode): 1 = Starts 16-bit timer 0 = Stops 16-bit timer bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timerx Stop in Idle Mode bit 1 = Discontinues timer operation when device enters Idle mode 0 = Continues timer operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 T32: 32-Bit Timerx Mode Select bit 1 = TMRx and TMRy form a 32-bit timer 0 = TMRx and TMRy form a separate 16-bit timer bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit 1 = External clock from TxCK pin 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ DS70000591F-page 222  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 13-2: TyCON: TIMERy CONTROL REGISTER (y = 3, 5) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(2) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(2) TCKPS1(2) TCKPS0(2) — — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timery On bit(2) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timery Stop in Idle Mode bit(1) 1 = Discontinues timer operation when device enters Idle mode 0 = Continues timer operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timery Gated Time Accumulation Enable bit(2) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timery Input Clock Prescale Select bits(2) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timery Clock Source Select bit(2) 1 = External clock from TxCK pin 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32=1) in the Timerx Control register (TxCON<3>), these bits have no effect.  2009-2014 Microchip Technology Inc. DS70000591F-page 223

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70000591F-page 224  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 14.0 INPUT CAPTURE • Simple Capture Event modes: - Capture timer value on every falling edge of Note1: This data sheet summarizes the features input at ICx pin of the dsPIC33FJ32GS406/606/608/610 - Capture timer value on every rising edge of and dsPIC33FJ64GS406/606/608/610 input at ICx pin families of devices. It is not intended to be • Capture Timer Value on Every Edge (rising and a comprehensive reference source. To falling) complement the information in this data sheet, refer to “Input Capture” (DS70198) • Prescaler Capture Event modes: in the “dsPIC33/PIC24 Family Reference - Capture timer value on every 4th rising edge Manual”, which is available from the Micro- of input at ICx pin chip web site (www.microchip.com). The - Capture timer value on every 16th rising information in this data sheet supersedes edge of input at ICx pin the information in the FRM. Each input capture channel can select one of the 2: Some registers and associated bits two 16-bit timers (Timer2 or Timer3) for the time described in this section may not be base. The selected timer can use either an internal available on all devices. Refer to or external clock. Section4.0 “Memory Organization” in Other operational features include: this data sheet for device-specific register and bit information. • Device Wake-up from Capture Pin during CPU Sleep and Idle modes The input capture module is useful in applications • Interrupt on Input Capture Event requiring frequency (period) and pulse measurement. • 4-Word FIFO Buffer for Capture Values The dsPIC33FJ32GS406/606/608/610 and - Interrupt optionally generated after 1, 2, 3 or dsPIC33FJ64GS406/606/608/610 devices support up 4 buffer locations are filled to two input capture channels. • Use of Input Capture to provide Additional The input capture module captures the 16-bit value of Sources of External Interrupts the selected Time Base register when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: FIGURE 14-1: INPUT CAPTURE x BLOCK DIAGRAM From 16-Bit Timers TMR2 TMR3 16 16 ICTMR 1 0 (ICxCON<7>) Prescaler Edge Detection Logic FIFO Counter and R/W (1, 4, 16) Clock Synchronizer Logic ICx Pin ICM<2:0> (ICxCON<2:0>) 3 Mode Select O F ICOV, ICBNE (ICxCON<4:3>) FI ICxBUF ICI<1:0> Interrupt ICxCON Logic System Bus Set Flag ICxIF (in IFSx Register) Note 1: An ‘x’ in a signal, register or bit name denotes the number of the input capture channel.  2009-2014 Microchip Technology Inc. DS70000591F-page 225

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 14.1 Input Capture Registers REGISTER 14-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER (x = 1 TO 4) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — ICSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0 ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture x Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 ICTMR: Input Capture x Timer Select bit 1 = TMR2 contents are captured on capture event 0 = TMR3 contents are captured on capture event bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture x Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM<2:0>: Input Capture x Mode Select bits 111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode; rising edge detect only, all other control bits are not applicable 110 = Unused (module disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge (rising and falling); ICI<1:0> bits do not control interrupt generation for this mode 000 = Input capture module is turned off DS70000591F-page 226  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 15.0 OUTPUT COMPARE The output compare module can select either Timer2 or Timer3 for its time base. The module compares the Note1: This data sheet summarizes the features value of the timer with the value of one or two Compare of the dsPIC33FJ32GS406/606/608/610 registers depending on the operating mode selected. and dsPIC33FJ64GS406/606/608/610 The state of the output pin changes when the timer families of devices. It is not intended to be value matches the Compare register value. The output a comprehensive reference source. To compare module generates either a single output complement the information in this data pulse, or a sequence of output pulses, by changing the sheet, refer to “Output Compare” state of the output pin on the compare match events. (DS70005157) in the “dsPIC33/PIC24 The output compare module can also generate Family Reference Manual”, which is interrupts on compare match events. available from the Microchip web site The output compare module has multiple operating (www.microchip.com). The information modes: in this data sheet supersedes the information in the FRM. • Active-Low One-Shot mode 2: Some registers and associated bits • Active-High One-Shot mode described in this section may not be • Toggle mode available on all devices. Refer to • Delayed One-Shot mode Section4.0 “Memory Organization” in • Continuous Pulse mode this data sheet for device-specific register • PWM mode without Fault Protection and bit information. • PWM mode with Fault Protection FIGURE 15-1: OUTPUT COMPARE x MODULE BLOCK DIAGRAM Set Flag bit OCxIF OCxRS Output S Q OCx OCxR Logic R Output Enable 3 OCM<2:0> Mode Select OCFA Comparator 0 1 OCTSEL 0 1 16 16 TMR2 TMR3 TMR2 TMR3 Rollover Rollover Note: An ‘x’ in a signal, register or bit name denotes the number of the output compare channels.  2009-2014 Microchip Technology Inc. DS70000591F-page 227

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 15.1 Output Compare Modes application must disable the associated timer when writing to the Output Compare Control registers to Configure the Output Compare modes by setting the avoid malfunctions. appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register. Note: See “Output Compare” (DS70005157) Table15-1 lists the different bit settings for the Output in the “dsPIC33/PIC24 Family Reference Compare modes. Figure15-2 illustrates the output Manual” for OCxR and OCxRS register compare operation for various modes. The user restrictions. TABLE 15-1: OUTPUT COMPARE MODES OCM<2:0> Mode OCx Pin Initial State OCx Interrupt Generation 000 Module Disabled Controlled by GPIO register — 001 Active-Low One-Shot 0 OCx rising edge 010 Active-High One-Shot 1 OCx falling edge 011 Toggle Current output is maintained OCx rising and falling edge 100 Delayed One-Shot 0 OCx falling edge 101 Continuous Pulse 0 OCx falling edge 110 PWM without Fault Protection ‘0’ if OCxR is zero, No interrupt ‘1’ if OCxR is non-zero 111 PWM with Fault Protection ‘0’ if OCxR is zero, OCFA falling edge for OC1 to OC4 ‘1’ if OCxR is non-zero FIGURE 15-2: OUTPUT COMPARE x OPERATION Output Compare Timer is Reset on Mode Enabled Period Match OCxRS TMRy OCxR Active-Low One-Shot (OCM = 001) Active-High One-Shot (OCM = 010) Toggle (OCM = 011) Delayed One-Shot (OCM = 100) Continuous Pulse (OCM = 101) PWM (OCM = 110 or 111) DS70000591F-page 228  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 15-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1 TO 4) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0 — — — OCFLT OCTSEL OCM2 OCM1 OCM0 bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Output Compare x Stop in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode bit 12-5 Unimplemented: Read as ‘0’ bit 4 OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in hardware only) 0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111) bit 3 OCTSEL: Output Compare x Timer Select bit 1 = Timer3 is the clock source for Output Compare x 0 = Timer2 is the clock source for Output Compare x bit 2-0 OCM<2:0>: Output Compare x Mode Select bits 111 = PWM mode on OCx, Fault pin is enabled 110 = PWM mode on OCx, Fault pin is disabled 101 = Initializes OCx pin low, generates continuous output pulses on OCx pin 100 = Initializes OCx pin low, generates single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initializes OCx pin high, compare event forces OCx pin low 001 = Initializes OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled  2009-2014 Microchip Technology Inc. DS70000591F-page 229

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70000591F-page 230  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 16.0 HIGH-SPEED PWM • Dual Trigger from PWM to Analog-to-Digital Converter (ADC) per PWM Period Note1: This data sheet summarizes the features • PWMxL and PWMxH Output Pin Swapping of the dsPIC33FJ32GS406/606/608/610 • Independent PWM Frequency, Duty Cycle and and dsPIC33FJ64GS406/606/608/610 Phase-Shift Changes families of devices. It is not intended to be • Current Compensation a comprehensive reference source. To • Enhanced Leading-Edge Blanking (LEB) Functionality complement the information in this data • PWM Capture Functionality sheet, refer to “High-Speed PWM” Note: Duty cycle, dead-time, phase shift and (DS70000323) in the “dsPIC33/PIC24 frequency resolution is 8.32 ns in Family Reference Manual”, which is Center-Aligned PWM mode. available from the Microchip web site (www.microchip.com). The information Figure16-1 conceptualizes the PWM module in a in this data sheet supersedes the simplified block diagram. Figure16-2 illustrates how information in the FRM. the module hardware is partitioned for each PWM 2: Some registers and associated bits output pair for the Complementary PWM mode. described in this section may not be The PWM module contains nine PWM generators. The available on all devices. Refer to module has up to 18 PWM output pins: PWM1H/ Section4.0 “Memory Organization” in PWM1L through PWM9H/PWM9L. For complementary this data sheet for device-specific register outputs, these 18 I/O pins are grouped into high/low and bit information. pairs. The high-speed PWM module on 16.2 Feature Description the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices supports a The PWM module is designed for applications that wide variety of PWM modes and output formats. This require: PWM module is ideal for power conversion • High-resolution at high PWM frequencies applications, such as: • The ability to drive Standard, Edge-Aligned, • AC/DC Converters Center-Aligned Complementary mode and • DC/DC Converters Push-Pull mode outputs • Power Factor Correction • The ability to create multiphase PWM outputs • Uninterruptible Power Supply (UPS) For Center-Aligned mode, the duty cycle, period phase • Inverters and dead-time resolutions will be 8.32 ns. • Battery Chargers • Digital Lighting Two common, medium power converter topologies are push-pull and half-bridge. These designs require the 16.1 Features Overview PWM output signal to be switched between alternate pins, as provided by the Push-Pull PWM mode. The high-speed PWM module incorporates the Phase-shifted PWM describes the situation where following features: each PWM generator provides outputs, but the phase • Two Master Time Base modules relationship between the generator outputs is • Up to Nine PWM Generators with up to 18 Outputs specifiable and changeable. • Two PWM Outputs per PWM Generator Multiphase PWM is often used to improve DC/DC Con- • Individual Time Base and Duty Cycle for each verter load transient response, and reduce the size of PWM Output output filter capacitors and inductors. Multiple DC/DC • Duty Cycle, Dead Time, Phase Shift and Converters are often operated in parallel, but Frequency Resolution of 1.04 ns phase-shifted in time. A single PWM output, operating at • Independent Fault and Current-Limit Inputs for 250kHz, has a period of 4 s, but an array of four PWM Eight PWM Outputs channels, staggered by 1 s each, yields an effective switching frequency of 1 MHz. Multiphase PWM • Redundant Output applications typically use a fixed-phase relationship. • True Independent Output • Center-Aligned PWM mode Variable phase PWM is useful in Zero Voltage Transition (ZVT) power converters. Here, the PWM • Output Override Control duty cycle is always 50% and the power flow is • Chop mode (also known as Gated mode) controlled by varying the relative phase shift between • Special Event Trigger the two PWM generators. • Prescaler for Input Clock  2009-2014 Microchip Technology Inc. DS70000591F-page 231

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 16-1: HIGH-SPEED PWMx MODULE ARCHITECTURAL DIAGRAM SYNCIx Data Bus Primary and Secondary Master Time Base SYNCOx SynchronizationSignal PWM1Interrupt PWM1H PWM Generator 1 PWM1L Fault, Current-Limit and Dead-Time Compensation SynchronizationSignal PWM2Interrupt PWM2H PWM Generator 2 PWM2L Fault, Current-Limit and Dead-Time Compensation CPU PWM3 through PWM7 SynchronizationSignal PWM8Interrupt PWM8H PWM Generator 8 PWM8L Fault, Current-Limit and Dead-Time Compensation SynchronizationSignal PWM9Interrupt PWM9H PWM Generator 9 PWM9L Primary Trigger Secondary Trigger Fault and ADC Module Current-Limit Special Event Trigger DS70000591F-page 232  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 16-2: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF THE HIGH-SPEED PWMx PTCON, PTCON2 Module Control and Timing SY•N•CI•1 SYNCI4 STCON, STCON2 SYNCO1 PTPER SEVTCMP Special Event Compare Trigger Special Event Comparator Comparator Postscaler Special Event Trigger Master Time Base Counter Clock PMTMR Prescaler Primary Master Time Base SYNCO2 STPER SEVTCMP Special Event Compare Trigger Special Event Comparator Comparator Postscaler Special Event Trigger Master Time Base Counter Clock SMTMR Prescaler Secondary Master Time Base MDC Master Duty Cycle Register n zatio ycle PDCx PWM Generator 1 ni C chro Duty MUX Syn Master Period Comparator PWMCAPx PWCMo nOtruotlp Luot gMicode er us Mast PTMRx ADC Trigger User Override Logic DTeimade- Pin PWM1H Data B PHASEx Comparator OCvuerrrreidnet- LLiomgiitc Logic CLoongtircol PWM1L Bit TRIGx Fault Override Logic 6- SDCx 1 Secondary PWM MUX Comparator Interrupt Fault and Logic Current-Limit FLTn(1) Logic ADC Trigger n STMRx Comparator o ati z oni SPHASEx STRIGx FCLCONx IOCONx ALTDTRx Synchr aster Duty Cycle Master Period PWMCONx TRGCONx LEBCONx DTRx M PWMxH PWMxL PWM Generator 2 – PWM Generator 9 FLTn(1) DTCMPx Note1: n = 1 through 23.  2009-2014 Microchip Technology Inc. DS70000591F-page 233

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 16.3 Control Registers The following registers control the operation of the high-speed PWM module. • PTCON: PWM Time Base Control Register • PTCON2: PWM Clock Divider Select Register 2 • PTPER: PWM Primary Master Time Base Period Register(1,2) • SEVTCMP: PWM Special Event Compare Register(1) • STCON: PWM Secondary Master Time Base Control Register • STCON2: PWM Secondary Clock Divider Select Register2 • STPER: PWM Secondary Master Time Base Period Register • SSEVTCMP: PWM Secondary Special Event Compare Register • CHOP: PWM Chop Clock Generator Register(1) • MDC: PWM Master Duty Cycle Register(1,2) • PWMCONx: PWM Control x Register • PDCx: PWM Generator Duty Cycle x Register(1,2,3) • PHASEx: PWM Primary Phase-Shift x Register(1,2) • DTRx: PWM Dead-Time x Register • ALTDTRx: PWM Alternate Dead-Time x Register • SDCx: PWM Secondary Duty Cycle x Register(1,2,3) • SPHASEx: PWM Secondary Phase-Shift x Register(1,2) • TRGCONx: PWM Trigger Control x Register • IOCONx: PWM I/O Control x Register • FCLCONx: PWM Fault Current-Limit Control x Register • TRIGx: PWM Primary Trigger x Compare Value Register • STRIGx: PWM Secondary Trigger x Compare Value Register(1) • LEBCONx: Leading-Edge Blanking Control x Register • LEBDLYx: Leading-Edge Blanking Delay x Register • AUXCONx: PWM Auxiliary Control x Register • PWMCAPx: Primary PWM Time Base Capture x Register DS70000591F-page 234  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-1: PTCON: PWM TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN — PTSIDL SESTAT SEIEN EIPU(1) SYNCPOL(1) SYNCOEN(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SYNCEN(1) SYNCSRC2(1) SYNCSRC1(1) SYNCSRC0(1) SEVTPS3(1) SEVTPS2(1) SEVTPS1(1) SEVTPS0(1) bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTEN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit 1 = PWM time base halts in CPU Idle mode 0 = PWM time base runs in CPU Idle mode bit 12 SESTAT: Special Event Interrupt Status bit 1 = Special event interrupt is pending 0 = Special event interrupt is not pending bit 11 SEIEN: Special Event Interrupt Enable bit 1 = Special event interrupt is enabled 0 = Special event interrupt is disabled bit 10 EIPU: Enable Immediate Period Updates bit(1) 1 = Active Period register is updated immediately 0 = Active Period register updates occur on PWM cycle boundaries bit 9 SYNCPOL: Synchronize Input and Output Polarity bit(1) 1 = SYNCIx/SYNCO1 polarity is inverted (active-low) 0 = SYNCIx/SYNCO1 is active-high bit 8 SYNCOEN: Primary Time Base Synchronization Enable bit(1) 1 = SYNCO1 output is enabled 0 = SYNCO1 output is disabled bit 7 SYNCEN: External Time Base Synchronization Enable bit(1) 1 = External synchronization of primary time base is enabled 0 = External synchronization of primary time base is disabled bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits(1) 111 = Reserved 101 = Reserved 100 = Reserved 011 = SYNCI4 010 = SYNCI3 001 = SYNCI2 000 = SYNCI1 Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user application must program the Period register with a value that is slightly larger than the expected period of the external synchronization input signal.  2009-2014 Microchip Technology Inc. DS70000591F-page 235

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-1: PTCON: PWM TIME BASE CONTROL REGISTER (CONTINUED) bit 3-0 SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits(1) 1111 = 1:16 Postscaler generates Special Event Trigger on every sixteenth compare match event • • • 0001 = 1:2 Postscaler generates Special Event Trigger on every second compare match event 0000 = 1:1 Postscaler generates Special Event Trigger on every compare match event Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user application must program the Period register with a value that is slightly larger than the expected period of the external synchronization input signal. DS70000591F-page 236  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-2: PTCON2: PWM CLOCK DIVIDER SELECT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCLKDIV<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1) 111 = Reserved 110 = Divide-by-64, maximum PWM timing resolution 101 = Divide-by-32, maximum PWM timing resolution 100 = Divide-by-16, maximum PWM timing resolution 011 = Divide-by-8, maximum PWM timing resolution 010 = Divide-by-4, maximum PWM timing resolution 001 = Divide-by-2, maximum PWM timing resolution 000 = Divide-by-1, maximum PWM timing resolution (power-on default) Note 1: These bits should be changed only when PTEN=0. Changing the clock selection during operation will yield unpredictable results. REGISTER 16-3: PTPER: PWM PRIMARY MASTER TIME BASE PERIOD REGISTER(1,2) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PTPER<15:8> bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 PTPER<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits Note 1: The PWM time base has a minimum value of 0x0010 and a maximum value of 0xFFF8. 2: Any period value that is less than 0x0028 must have the Least Significant 3 bits set to ‘0’, thus yielding a period resolution at 8.32 ns (at fastest auxiliary clock rate).  2009-2014 Microchip Technology Inc. DS70000591F-page 237

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-4: SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<12:5> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 SEVTCMP<4:0> — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 SEVTCMP<12:0>: Special Event Compare Count Value bits bit 2-0 Unimplemented: Read as ‘0’ Note 1: One LSB = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum SEVTCMP resolution is 8.32 ns. DS70000591F-page 238  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-5: STCON: PWM SECONDARY MASTER TIME BASE CONTROL REGISTER U-0 U-0 U-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — SESTAT SEIEN EIPU(1) SYNCPOL SYNCOEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SYNCEN SYNCSRC2 SYNCSRC1 SYNCSRC0 SEVTPS3 SEVTPS2 SEVTPS1 SEVTPS0 bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 SESTAT: Special Event Interrupt Status bit 1 = Secondary special event interrupt is pending 0 = Secondary special event interrupt is not pending bit 11 SEIEN: Special Event Interrupt Enable bit 1 = Secondary special event interrupt is enabled 0 = Secondary special event interrupt is disabled bit 10 EIPU: Enable Immediate Period Updates bit(1) 1 = Active Secondary Period register is updated immediately 0 = Active Secondary Period register updates occur on PWM cycle boundaries bit 9 SYNCPOL: Synchronize Input and Output Polarity bit 1 = SYNCIx/SYNCO2 polarity is inverted (active-low) 0 = SYNCIx/SYNCO2 polarity is active-high bit 8 SYNCOEN: Secondary Master Time Base Synchronization Enable bit 1 = SYNCO2 output is enabled. 0 = SYNCO2 output is disabled bit 7 SYNCEN: External Secondary Master Time Base Synchronization Enable bit 1 = External synchronization of secondary time base is enabled 0 = External synchronization of secondary time base is disabled bit 6-4 SYNCSRC<2:0>: PWM Secondary Time Base Synchronization Source Selection bits 111 = Reserved 101 = Reserved 100 = Reserved 011 = SYNCI4 010 = SYNCI3 001 = SYNCI2 000 = SYNCI1 bit 3-0 SEVTPS<3:0>: PWM Secondary Special Event Trigger Output Postscaler Select bits 1111 = 1:16 Postcale 0001 = 1:2 Postcale • • • 0000 = 1:1 Postscale Note 1: This bit only applies to the secondary master time base period.  2009-2014 Microchip Technology Inc. DS70000591F-page 239

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-6: STCON2: PWM SECONDARY CLOCK DIVIDER SELECT REGISTER2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCLKDIV2(1) PCLKDIV1(1) PCLKDIV0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1) 111 = Reserved 110 = Divide-by-64, maximum PWM timing resolution 101 = Divide-by-32, maximum PWM timing resolution 100 = Divide-by-16, maximum PWM timing resolution 011 = Divide-by-8, maximum PWM timing resolution 010 = Divide-by-4, maximum PWM timing resolution 001 = Divide-by-2, maximum PWM timing resolution 000 = Divide-by-1, maximum PWM timing resolution (power-on default) Note 1: These bits should be changed only when PTEN=0. Changing the clock selection during operation will yield unpredictable results. REGISTER 16-7: STPER: PWM SECONDARY MASTER TIME BASE PERIOD REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 STPER<15:8> bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 STPER<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STPER<15:0>: Secondary Master Time Base (SMTMR) Period Value bits DS70000591F-page 240  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-8: SSEVTCMP: PWM SECONDARY SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEVTCMP<12:5> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 SSEVTCMP<4:0> — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 SSEVTCMP<12:0>: Special Event Compare Count Value bits bit 2-0 Unimplemented: Read as ‘0’ REGISTER 16-9: CHOP: PWM CHOP CLOCK GENERATOR REGISTER(1) R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 CHPCLKEN — — — — — CHOPCLK6 CHOPCLK5 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHPCLKEN: Enable Chop Clock Generator bit 1 = Chop clock generator is enabled 0 = Chop clock generator is disabled bit 14-10 Unimplemented: Read as ‘0’ bit 9-3 CHOPCLK<6:0>: Chop Clock Divider bits Value in 8.32 ns increments. The frequency of the chop clock signal is given by the following expression: Chop Frequency = 1/(16.64 * (CHOPCLK<6:0> + 1) * Primary Master PWM Input Clock Period) bit 2-0 Unimplemented: Read as ‘0’ Note 1: The chop clock generator operates with the primary PWM clock prescaler (PCLKDIV<2:0>) in the PTCON2 register (Register16-2).  2009-2014 Microchip Technology Inc. DS70000591F-page 241

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-10: MDC: PWM MASTER DUTY CYCLE REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MDC<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MDC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 MDC<15:0>: PWM Master Duty Cycle Value bits Note 1: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of Period – 0x0009. 2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 to 40 ns, depending on the mode of operation), the PWM duty cycle resolution will increase from 1 to 3 LSBs. DS70000591F-page 242  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-11: PWMCONx: PWM CONTROL x REGISTER HS/HC-0 HS/HC-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTSTAT(1) CLSTAT(1) TRGSTAT FLTIEN CLIEN TRGIEN ITB(3) MDCS(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 DTC1 DTC0 DTCP(4) — MTBS CAM(2,3,5) XPRES(6) IUE bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTSTAT: Fault Interrupt Status bit(1) 1 = Fault interrupt is pending 0 = No Fault interrupt is pending This bit is cleared by setting FLTIEN = 0. bit 14 CLSTAT: Current-Limit Interrupt Status bit(1) 1 = Current-limit interrupt is pending 0 = No current-limit interrupt is pending This bit is cleared by setting CLIEN = 0. bit 13 TRGSTAT: Trigger Interrupt Status bit 1 = Trigger interrupt is pending 0 = No trigger interrupt is pending This bit is cleared by setting TRGIEN = 0. bit 12 FLTIEN: Fault Interrupt Enable bit 1 = Fault interrupt is enabled 0 = Fault interrupt is disabled and FLTSTAT bit is cleared bit 11 CLIEN: Current-Limit Interrupt Enable bit 1 = Current-limit interrupt is enabled 0 = Current-limit interrupt is disabled and CLSTAT bit is cleared bit 10 TRGIEN: Trigger Interrupt Enable bit 1 = A trigger event generates an interrupt request 0 = Trigger event interrupts are disabled and TRGSTAT bit is cleared bit 9 ITB: Independent Time Base Mode bit(3) 1 = PHASEx/SPHASEx registers provide time base period for this PWM generator 0 = PTPER register provides timing for this PWM generator bit 8 MDCS: Master Duty Cycle Register Select bit(3) 1 = MDC register provides duty cycle information for this PWM generator 0 = PDCx and SDCx registers provide duty cycle information for this PWM generator Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller. 2: The Independent Time Base mode (ITB=1) must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. 3: These bits should not be changed after the PWM is enabled by setting PTEN (PTCON<15>) = 1. 4: For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored. 5: Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase and Dead-Time registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to the fastest clock. 6: Configure CLMOD (FCLCONX<8>) = 0 and ITB (PWMCONx<9>) = 1 to operate in External Period Reset mode.  2009-2014 Microchip Technology Inc. DS70000591F-page 243

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-11: PWMCONx: PWM CONTROL x REGISTER (CONTINUED) bit 7-6 DTC<1:0>: Dead-Time Control bits 11 = Dead-Time Compensation mode 10 = Dead-time function is disabled 01 = Negative dead time is actively applied for Complementary Output mode 00 = Positive dead time is actively applied for all output modes bit 5 DTCP: Dead-Time Compensation Polarity bit(4) 1 = If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened; If DTCMPx = 1, PWMxH is shortened and PWMxL is lengthened 0 = If DTCMPx = 0, PWMxH is shortened and PWMLx is lengthened; If DTCMPx = 1, PWMxL is shortened and PWMxH is lengthened bit 4 Unimplemented: Read as ‘0’ bit 3 MTBS: Master Time Base Select bit 1 = PWM generator uses the secondary master time base for synchronization and the clock source for the PWM generation logic (if secondary time base is available) 0 = PWM generator uses the primary master time base for synchronization and the clock source for the PWM generation logic bit 2 CAM: Center-Aligned Mode Enable bit(2,3,5) 1 = Center-Aligned mode is enabled 0 = Edge-Aligned mode is enabled bit 1 XPRES: External PWM Reset Control bit(6) 1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time Base mode 0 = External pins do not affect PWM time base bit 0 IUE: Immediate Update Enable bit 1 = Updates to the active MDC/PDCx/SDCx registers are immediate 0 = Updates to the active PDCx registers are synchronized to the PWM time base Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller. 2: The Independent Time Base mode (ITB=1) must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. 3: These bits should not be changed after the PWM is enabled by setting PTEN (PTCON<15>) = 1. 4: For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored. 5: Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase and Dead-Time registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to the fastest clock. 6: Configure CLMOD (FCLCONX<8>) = 0 and ITB (PWMCONx<9>) = 1 to operate in External Period Reset mode. DS70000591F-page 244  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-12: PDCx: PWM GENERATOR DUTY CYCLE x REGISTER(1,2,3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PDCx<15:0>: PWM Generator # Duty Cycle Value bits Note 1: In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In the Complementary, Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of both the PWMxH and PWMxL. 2: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of Period – 0x0009. 3: As the duty cycle gets closer to 0% or 100% of the PWM period (0 to 40 ns, depending on the mode of operation), PWM duty cycle resolution will increase from 1 to 3 LSBs. REGISTER 16-13: SDCx: PWM SECONDARY DUTY CYCLE x REGISTER(1,2,3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SDCx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SDCx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 SDCx<15:0>: Secondary Duty Cycle bits for PWMxL Output Pin Note 1: The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the SDCx register controls the PWMxL duty cycle. 2: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of Period – 0x0009. 3: As the duty cycle gets closer to 0% or 100% of the PWM period (0 to 40 ns, depending on the mode of operation), PWM duty cycle resolution will increase from 1 to 3 LSBs.  2009-2014 Microchip Technology Inc. DS70000591F-page 245

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-14: PHASEx: PWM PRIMARY PHASE-SHIFT x REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PHASEx<15:0>: PWM Phase-Shift Value or Independent Time Base Period for the PWM Generator bits Note 1: If PWMCONx<9> = 0, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (IOCONx<10:8> = 00, 01 or 10), PHASEx<15:0> = Phase-Shift Value for PWMxH and PWMxL outputs. • True Independent Output mode (IOCONx<10:8> = 11), PHASEx<15:0> = Phase-Shift Value for PWMxH only. • The PHASEx/SPHASEx registers provide the phase shift with respect to the master time base; therefore, the valid range is 0x0000 through period. 2: If PWMCONx<9> = 1, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (IOCONx<10:8> = 00, 01 or 10), PHASEx<15:0> = Independent Time Base Period Value for PWMxH and PWMxL. • True Independent Output mode (IOCONx<10:8> = 11). PHASEx<15:0> = Independent Time Base Period Value for PWMxH only. • When the PHASEx/SPHASEx registers provide the local period, the valid range is 0x0000 through 0xFFF8. DS70000591F-page 246  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-15: SPHASEx: PWM SECONDARY PHASE-SHIFT x REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 SPHASEx<15:0>: Secondary Phase Offset bits for PWMxL Output Pin bits (used in Independent PWM mode only) Note 1: If PWMCONx<9> = 0, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (IOCONx<10:8> = 00, 01 or 10), SPHASEx<15:0> = Not Used. • True Independent Output mode (IOCONx<10:8> = 11), PHASEx<15:0> = Phase-Shift Value for PWMxL only. • The PHASEx/SPHASEx registers provide the phase shift with respect to the master time base; therefore, the valid range is 0x0000 through period. 2: If PWMCONx<9> = 1, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (IOCONx<10:8> = 00, 01 or 10), SPHASEx<15:0> = Not Used. • True Independent Output mode (IOCONx<10:8> = 11). PHASEx<15:0> = Independent Time Base Period Value for PWMxL only. • When the PHASEx/SPHASEx registers provide the local period, the valid range of values is 0x0010-0xFFF8.  2009-2014 Microchip Technology Inc. DS70000591F-page 247

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-16: DTRx: PWM DEAD-TIME x REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DTRx<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTRx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 DTRx<13:0>: Unsigned 14-Bit Value for PWMx Dead-Time Unit bits REGISTER 16-17: ALTDTRx: PWM ALTERNATE DEAD-TIME x REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ALTDTRx<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALTDTRx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 ALTDTRx<13:0>: Unsigned 14-Bit Value for PWMx Dead-Time Unit bits DS70000591F-page 248  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-18: TRGCONx: PWM TRIGGER CONTROL x REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — bit 15 bit 8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTM(1) — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 TRGDIV<3:0>: Trigger # Output Divider bits 1111 = Trigger output for every 16th trigger event 1110 = Trigger output for every 15th trigger event 1101 = Trigger output for every 14th trigger event 1100 = Trigger output for every 13th trigger event 1011 = Trigger output for every 12th trigger event 1010 = Trigger output for every 11th trigger event 1001 = Trigger output for every 10th trigger event 1000 = Trigger output for every 9th trigger event 0111 = Trigger output for every 8th trigger event 0110 = Trigger output for every 7th trigger event 0101 = Trigger output for every 6th trigger event 0100 = Trigger output for every 5th trigger event 0011 = Trigger output for every 4th trigger event 0010 = Trigger output for every 3rd trigger event 0001 = Trigger output for every 2nd trigger event 0000 = Trigger output for every trigger event bit 11-8 Unimplemented: Read as ‘0’ bit 7 DTM: Dual Trigger Mode bit(1) 1 = Secondary trigger event is combined with the primary trigger event to create the PWM trigger 0 = Secondary trigger event is not combined with the primary trigger event to create the PWM trigger; two separate PWM triggers are generated bit 6 Unimplemented: Read as ‘0’ bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits 111111 = Waits 63 PWM cycles before generating the first trigger event after the module is enabled • • • 000010 = Waits 2 PWM cycles before generating the first trigger event after the module is enabled 000001 = Waits 1 PWM cycle before generating the first trigger event after the module is enabled 000000 = Waits 0 PWM cycles before generating the first trigger event after the module is enabled Note 1: The secondary PWM generator cannot generate PWM trigger interrupts.  2009-2014 Microchip Technology Inc. DS70000591F-page 249

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Raa EGISTER 16-19: IOCONx: PWM I/O CONTROL x REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PENH PENL POLH POLL PMOD1(1) PMOD0(1) OVRENH OVRENL bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OVRDAT1 OVRDAT0 FLTDAT1(2) FLTDAT0(2) CLDAT1(2) CLDAT0(2) SWAP OSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PENH: PWMxH Output Pin Ownership bit 1 = PWM module controls PWMxH pin 0 = GPIO module controls PWMxH pin bit 14 PENL: PWMxL Output Pin Ownership bit 1 = PWM module controls PWMxL pin 0 = GPIO module controls PWMxL pin bit 13 POLH: PWMxH Output Pin Polarity bit 1 = PWMxH pin is active-low 0 = PWMxH pin is active-high bit 12 POLL: PWMxL Output Pin Polarity bit 1 = PWMxL pin is active-low 0 = PWMxL pin is active-high bit 11-10 PMOD<1:0>: PWM # I/O Pin Mode bits(1) 11 = PWM I/O pin pair is in the True Independent Output mode 10 = PWM I/O pin pair is in the Push-Pull Output mode 01 = PWM I/O pin pair is in the Redundant Output mode 00 = PWM I/O pin pair is in the Complementary Output mode bit 9 OVRENH: Override Enable for PWMxH Pin bit 1 = OVRDAT<1> provides data for output on PWMxH pin 0 = PWM generator provides data for output on PWMxH pin bit 8 OVRENL: Override Enable for PWMxL Pin bit 1 = OVRDAT<0> provides data for output on PWMxL pin 0 = PWM generator provides data for output on PWMxL pin bit 7-6 OVRDAT<1:0>: Data for PWMxH, PWMxL Pins if Override is Enabled bits If OVERENH = 1, OVRDAT<1> provides data for PWMxH If OVERENL = 1, OVRDAT<0> provides data for PWMxL bit 5-4 FLTDAT<1:0>: State for PWMxH and PWMxL Pins if FLTMOD is Enabled bits(2) IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode: If Fault is active, then FLTDAT<1> provides the state for PWMxH. If Fault is active, then FLTDAT<0> provides the state for PWMxL. IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode: If current-limit is active, then FLTDAT<1> provides the state for PWMxH. If Fault is active, then FLTDAT<0> provides the state for PWMxL. Note 1: These bits should not be changed after the PWM module is enabled (PTEN = 1). 2: State represents the active/inactive state of the PWM depending on the POLH and POLL bit settings. DS70000591F-page 250  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-19: IOCONx: PWM I/O CONTROL x REGISTER (CONTINUED) bit 3-2 CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMOD is Enabled bits(2) IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode: If current-limit is active, then CLDAT<1> provides the state for PWMxH. If current-limit is active, then CLDAT<0> provides the state for PWMxL. IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode: CLDAT<1:0> is ignored. bit 1 SWAP: SWAP PWMxH and PWMxL Pins bit 1 = PWMxH output signal is connected to the PWMxL pin; PWMxL output signal is connected to the PWMxH pin 0 = PWMxH and PWMxL pins are mapped to their respective pins bit 0 OSYNC: Output Override Synchronization bit 1 = Output overrides, via the OVRDAT<1:0> bits, are synchronized to the PWM time base 0 = Output overrides, via the OVDDAT<1:0> bits, occur on next CPU clock boundary Note 1: These bits should not be changed after the PWM module is enabled (PTEN = 1). 2: State represents the active/inactive state of the PWM depending on the POLH and POLL bit settings. REGISTER 16-20: TRIGx: PWM PRIMARY TRIGGER x COMPARE VALUE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<12:5> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 TRGCMP<4:0> — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 TRGCMP<12:0>: Trigger Compare Value bits When the primary PWM functions in the local time base, this register contains the compare values that can trigger the ADC module. bit 2-0 Unimplemented: Read as ‘0’  2009-2014 Microchip Technology Inc. DS70000591F-page 251

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-21: FCLCONx: PWM FAULT CURRENT-LIMIT CONTROL x REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFLTMOD CLSRC4(2,3) CLSRC3(2,3) CLSRC2(2,3) CLSRC1(2,3) CLSRC0(2,3) CLPOL(1) CLMOD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTSRC4(2,3) FLTSRC3(2,3) FLTSRC2(2,3) FLTSRC1(2,3) FLTSRC0(2,3) FLTPOL(1) FLTMOD1 FLTMOD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IFLTMOD: Independent Fault Mode Enable bit 1 = Independent Fault mode: Current-limit input maps FLTDAT<1> to PWMxH output and Fault input maps FLTDAT<0> to PWMxL output. The CLDAT<1:0> bits are not used for override functions. 0 = Normal Fault mode: Current-Limit mode maps CLDAT<1:0> bits to the PWMxH and PWMxL outputs. The PWM Fault mode maps FLTDAT<1:0> to the PWMxH and PWMxL outputs. bit 14-10 CLSRC<4:0>: Current-Limit Control Signal Source Select for PWM Generator # bits(2,3) These bits also specify the source for the Dead-Time Compensation input signal, DTCMPx. 11111 = Reserved 11110 = Fault 23 11101 = Fault 22 11100 = Fault 21 11011 = Fault 20 11010 = Fault 19 11001 = Fault 18 11000 = Fault 17 10111 = Fault 16 10110 = Fault 15 10101 = Fault 14 10100 = Fault 13 10011 = Fault 12 10010 = Fault 11 10001 = Fault 10 10000 = Fault 9 01111 = Fault 8 01110 = Fault 7 01101 = Fault 6 01100 = Fault 5 01011 = Fault 4 01010 = Fault 3 01001 = Fault 2 01000 = Fault 1 00111 = Reserved 00110 = Reserved 00101 = Reserved 00100 = Reserved 00011 = Analog Comparator 4 00010 = Analog Comparator 3 00001 = Analog Comparator 2 00000 = Analog Comparator 1 Note 1: These bits should be changed only when PTEN (PTCON<15>) = 0. 2: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Current-Limit mode (CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs. 3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode (FLTSRC<4:0>=b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs. DS70000591F-page 252  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-21: FCLCONx: PWM FAULT CURRENT-LIMIT CONTROL x REGISTER (CONTINUED) bit 9 CLPOL: Current-Limit Polarity for PWM Generator # bit(1) 1 = The selected current-limit source is active-low 0 = The selected current-limit source is active-high bit 8 CLMOD: Current-Limit Mode Enable for PWM Generator # bit 1 = Current-Limit mode is enabled 0 = Current-Limit mode is disabled bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select for PWM Generator # bits(2,3) 11111 = Reserved 11110 = Fault 23 11101 = Fault 22 11100 = Fault 21 11011 = Fault 20 11010 = Fault 19 11001 = Fault 18 11000 = Fault 17 10111 = Fault 16 10110 = Fault 15 10101 = Fault 14 10100 = Fault 13 10011 = Fault 12 10010 = Fault 11 10001 = Fault 10 10000 = Fault 9 01111 = Fault 8 01110 = Fault 7 01101 = Fault 6 01100 = Fault 5 01011 = Fault 4 01010 = Fault 3 01001 = Fault 2 01000 = Fault 1 00111 = Reserved 00110 = Reserved 00101 = Reserved 00100 = Reserved 00011 = Analog Comparator 4 00010 = Analog Comparator 3 00001 = Analog Comparator 2 00000 = Analog Comparator 1 bit 2 FLTPOL: Fault Polarity for PWM Generator # bit(1) 1 = The selected Fault source is active-low 0 = The selected Fault source is active-high bit 1-0 FLTMOD<1:0>: Fault Mode for PWM Generator # bits 11 = Fault input is disabled 10 = Reserved 01 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle) 00 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition) Note 1: These bits should be changed only when PTEN (PTCON<15>) = 0. 2: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Current-Limit mode (CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs. 3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode (FLTSRC<4:0>=b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs.  2009-2014 Microchip Technology Inc. DS70000591F-page 253

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-22: STRIGx: PWM SECONDARY TRIGGER x COMPARE VALUE REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STRGCMP<12:5> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 STRGCMP<4:0> — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 STRGCMP<12:0>: PWM Secondary Trigger Compare Value bits When the secondary PWM functions in a local time base, this register contains the compare values that can trigger the ADC module. bit 2-0 Unimplemented: Read as ‘0’ Note 1: STRIGx cannot generate the PWM trigger interrupts. DS70000591F-page 254  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-23: LEBCONx: LEADING-EDGE BLANKING CONTROL x REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 PHR PHF PLR PLF FLTLEBEN CLLEBEN — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — BCH(1) BCL(1) BPHH BPHL BPLH BPLL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PHR: PWMxH Rising Edge Trigger Enable bit 1 = Rising edge of PWMxH will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores rising edge of PWMxH bit 14 PHF: PWMxH Falling Edge Trigger Enable bit 1 = Falling edge of PWMxH will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores falling edge of PWMxH bit 13 PLR: PWMxL Rising Edge Trigger Enable bit 1 = Rising edge of PWMxL will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores rising edge of PWMxL bit 12 PLF: PWMxL Falling Edge Trigger Enable bit 1 = Falling edge of PWMxL will trigger Leading-Edge Blanking counter 0 = Leading-Edge Blanking ignores falling edge of PWMxL bit 11 FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit 1 = Leading-Edge Blanking is applied to selected Fault input 0 = Leading-Edge Blanking is not applied to selected Fault input bit 10 CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit 1 = Leading-Edge Blanking is applied to selected current-limit input 0 = Leading-Edge Blanking is not applied to selected current-limit input bit 9-6 Unimplemented: Read as ‘0’ bit 5 BCH: Blanking in Selected Blanking Signal High Enable bit(1) 1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is high 0 = No blanking when selected blanking signal is high bit 4 BCL: Blanking in Selected Blanking Signal Low Enable bit(1) 1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is low 0 = No blanking when selected blanking signal is low bit 3 BPHH: Blanking in PWMxH High Enable bit 1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is high 0 = No blanking when PWMxH output is high bit 2 BPHL: Blanking in PWMxH Low Enable bit 1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is low 0 = No blanking when PWMxH output is low Note 1: The blanking signal is selected via the BLANKSELx bits in the AUXCONx register.  2009-2014 Microchip Technology Inc. DS70000591F-page 255

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-23: LEBCONx: LEADING-EDGE BLANKING CONTROL x REGISTER (CONTINUED) bit 1 BPLH: Blanking in PWMxL High Enable bit 1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is high 0 = No blanking when PWMxL output is high bit 0 BPLL: Blanking in PWMxL Low Enable bit 1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is low 0 = No blanking when PWMxL output is low Note 1: The blanking signal is selected via the BLANKSELx bits in the AUXCONx register. DS70000591F-page 256  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-24: LEBDLYx: LEADING-EDGE BLANKING DELAY x REGISTER U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — LEB<8:5> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 LEB<4:0> — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-3 LEB<8:0>: Leading-Edge Blanking Delay for Current-Limit and Fault Inputs bits The value is in 8.32 ns increments. bit 2-0 Unimplemented: Read as ‘0’  2009-2014 Microchip Technology Inc. DS70000591F-page 257

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-25: AUXCONx: PWM AUXILIARY CONTROL x REGISTER R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 HRPDIS HRDDIS — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HRPDIS: High-Resolution PWM Period Disable bit 1 = High-resolution PWM period is disabled to reduce power consumption 0 = High-resolution PWM period is enabled bit 14 HRDDIS: High-Resolution PWM Duty Cycle Disable bit 1 = High-resolution PWM duty cycle is disabled to reduce power consumption 0 = High-resolution PWM duty cycle is enabled bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 BLANKSEL<3:0>: PWM State Blank Source Select bits The selected state blank signal will block the current limit and/or Fault input signals (if enabled via the BCH and BCL bits in the LEBCONx register). 1001 = PWM9H is selected as state blank source 1000 = PWM8H is selected as state blank source 0111 = PWM7H is selected as state blank source 0110 = PWM6H is selected as state blank source 0101 = PWM5H is selected as state blank source 0100 = PWM4H is selected as state blank source 0011 = PWM3H is selected as state blank source 0010 = PWM2H is selected as state blank source 0001 = PWM1H is selected as state blank source 0000 = 1’b0 (no state blanking) bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 CHOPSEL<3:0>: PWM Chop Clock Source Select bits The selected signal will enable and disable (CHOPx) the selected PWM outputs. 1001 = PWM9H is selected as chop clock source 1000 = PWM8H is selected as chop clock source 0111 = PWM7H is selected as chop clock source 0110 = PWM6H is selected as chop clock source 0101 = PWM5H is selected as chop clock source 0100 = PWM4H is selected as chop clock source 0011 = PWM3H is selected as chop clock source 0010 = PWM2H is selected as chop clock source 0001 = PWM1H is selected as chop clock source 0000 = Chop clock generator is selected as the chop clock source bit 1 CHOPHEN: PWMxH Output Chopping Enable bit 1 = PWMxH chopping function is enabled 0 = PWMxH chopping function is disabled bit 0 CHOPLEN: PWMxL Output Chopping Enable bit 1 = PWMxL chopping function is enabled 0 = PWMxL chopping function is disabled DS70000591F-page 258  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-26: PWMCAPx: PRIMARY PWM TIME BASE CAPTURE x REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PWMCAP<12:5>(1,2,3,4) bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 U-0 U-0 U-0 PWMCAP<4:0>(1,2,3,4) — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 PWMCAP<12:0>: Captured PWM Time Base Value bits(1,2,3,4) The value in this register represents the captured PWM time base value when a leading edge is detected on the current-limit input. bit 2-0 Unimplemented: Read as ‘0’ Note 1: The capture feature is only available on the primary output (PWMxH). 2: This feature is active only after LEB processing on the current-limit input signal is complete. 3: The minimum capture resolution is 8.32 ns. 4: This feature can be used when the XPRES bit (PWMCONx<1>) is set to ‘0’.  2009-2014 Microchip Technology Inc. DS70000591F-page 259

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70000591F-page 260  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 17.0 QUADRATURE ENCODER This chapter describes the Quadrature Encoder Inter- INTERFACE (QEI) MODULE face (QEI) module and associated operational modes. The QEI module provides the interface to incremental Note 1: This data sheet summarizes the features encoders for obtaining mechanical position data. of the dsPIC33FJ32GS406/606/608/610 The operational features of the QEI include: and dsPIC33FJ64GS406/606/608/610 • Three Input Channels for Two Phase Signals and families of devices. It is not intended to be Index Pulse a comprehensive reference source. To • 16-Bit Up/Down Position Counter complement the information in this data • Count Direction Status sheet, refer to “Quadrature Encoder • Position Measurement (x2 and x4) mode Interface (QEI)” (DS70208) in the “dsPIC33/PIC24 Family Reference Man- • Programmable Digital Noise Filters on Inputs ual”, which is available from the Microchip • Alternate 16-Bit Timer/Counter mode web site (www.microchip.com). The infor- • Quadrature Encoder Interface Interrupts mation in this data sheet supersedes These operating modes are determined by setting the the information in the FRM. appropriate bits, QEIM<2:0> in (QEIxCON<10:8>). 2: Some registers and associated bits Figure17-1 depicts the Quadrature Encoder Interface described in this section may not be block diagram. available on all devices. Refer to Note: An ‘x’ used in the names of pins, control/ Section4.0 “Memory Organization” in status bits and registers denotes a this data sheet for device-specific register particular QEI module number (x = 1 or 2). and bit information. FIGURE 17-1: QUADRATURE ENCODER INTERFACE x BLOCK DIAGRAM (x = 1 OR 2) TQCKPS<1:0> Sleep Input TQCS 2 TCY 0 Synchronize Prescaler Detect 1 1, 8, 64, 256 1 QEIM<2:0> 0 TQGATE D Q QExIF Event Flag CK Q 16-Bit Up/Down Counter Programmable 2 (POSxCNT) QEAx(1) Digital Filter Quadrature Reset Encoder UPDN_SRC Interface Logic Comparator/ Zero-Detect Equal QEIxCON<11> 0 3 QEIM<2:0> 1 Mode Select Max Count Register (MAXxCNT) Programmable QEBx(1) Digital Filter Programmable INDXx(1) Digital Filter Note 1: The QEI1 module can be connected to the QEA1/QEB1/INDX1 PCDOUT 3 or AQEA1/AQEB1/AINDX1 pins, which are controlled by clearing Existing Pin Logic 0 or setting the ALTQIO bit in the FPOR Configuration register. See Section24.0 “Special Features” for more information. UPDNx Up/Down 1  2009-2014 Microchip Technology Inc. DS70000591F-page 261

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 17-1: QEIxCON: QEIx CONTROL REGISTER (x = 1 or 2) R/W-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 CNTERR(1) — QEISIDL INDX UPDN(2) QEIM2 QEIM1 QEIM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SWPAB PCDOUT TQGATE TQCKPS1(3) TQCKPS0(3) POSRES(4) TQCS UPDN_SRC(5) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CNTERR: Count Error Status Flag bit(1) 1 = Position count error has occurred 0 = No position count error has occurred bit 14 Unimplemented: Read as ‘0’ bit 13 QEISIDL: QEIx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 INDX: Index Pin State Status bit (read-only) 1 = Index pin is high 0 = Index pin is low bit 11 UPDN: Position Counter Direction Status bit(2) 1 = Position counter direction is positive (+) 0 = Position counter direction is negative (-) bit 10-8 QEIM<2:0>: Quadrature Encoder Interface Mode Select bits 111 = Quadrature Encoder Interface is enabled (x4 mode) with the position counter reset by the match (MAXxCNT) 110 = Quadrature Encoder Interface is enabled (x4 mode) with the Index Pulse Reset of the position counter 101 = Quadrature Encoder Interface is enabled (x2 mode) with the position counter reset by the match (MAXxCNT) 100 = Quadrature Encoder Interface is enabled (x2 mode) with the Index Pulse Reset of the position counter 011 = Unused (module disabled) 010 = Unused (module disabled) 001 = Starts 16-bit timer 000 = Quadrature Encoder Interface/timer off bit 7 SWPAB: Phase A and Phase B Input Swap Select bit 1 = Phase A and Phase B inputs are swapped 0 = Phase A and Phase B inputs are not swapped bit 6 PCDOUT: Position Counter Direction State Output Enable bit 1 = Position counter direction status output is enabled (QEI logic controls state of I/O pin) 0 = Position counter direction status output is disabled (normal I/O pin operation) Note 1: CNTERR flag only applies when QEIM<2:0> = 110 or 100. 2: Read-only bit when QEIM<2:0> = 1xx; read/write bit when QEIM<2:0> = 001. 3: Prescaler utilized for 16-Bit Timer mode only. 4: This bit applies only when QEIM<2:0> = 100 or 110. 5: When configured for QEI mode, this control bit is a ‘don’t care’. DS70000591F-page 262  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 17-1: QEIxCON: QEIx CONTROL REGISTER (x = 1 or 2) (CONTINUED) bit 5 TQGATE: Timer Gated Time Accumulation Enable bit 1 = Timer gated time accumulation is enabled 0 = Timer gated time accumulation is disabled bit 4-3 TQCKPS<1:0>: Timer Input Clock Prescale Select bits(3) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 2 POSRES: Position Counter Reset Enable bit(4) 1 = Index pulse resets the position counter 0 = Index pulse does not reset the position counter bit 1 TQCS: Timer Clock Source Select bit 1 = External clock from pin, QEAx (on the rising edge) 0 = Internal clock (TCY) bit 0 UPDN_SRC: Position Counter Direction Selection Control bit(5) 1 = QEBx pin state defines the position counter direction 0 = Control/status bit, UPDN (QEIxCON<11>), defines the timer counter (POSxCNT) direction Note 1: CNTERR flag only applies when QEIM<2:0> = 110 or 100. 2: Read-only bit when QEIM<2:0> = 1xx; read/write bit when QEIM<2:0> = 001. 3: Prescaler utilized for 16-Bit Timer mode only. 4: This bit applies only when QEIM<2:0> = 100 or 110. 5: When configured for QEI mode, this control bit is a ‘don’t care’.  2009-2014 Microchip Technology Inc. DS70000591F-page 263

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 17-2: DFLTxCON: DIGITAL FILTER x CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — IMV1 IMV0 CEID bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 QEOUT QECK2 QECK1 QECK0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 IMV<1:0>: Index Match Value bits These bits allow the user application to specify the state of the QEAx and QEBx input pins during an index pulse when the POSxCNT register is to be reset. In x4 Quadrature Count Mode: IMV1 = Required state of Phase B input signal for match on index pulse IMV0 = Required state of Phase A input signal for match on index pulse In x2 Quadrature Count Mode: IMV1 = Selects phase input signal for index state match (0 = Phase A, 1 = Phase B) IMV0 = Required state of the selected phase input signal for match on index pulse bit 8 CEID: Count Error Interrupt Disable bit 1 = Interrupts due to count errors are disabled 0 = Interrupts due to count errors are enabled bit 7 QEOUT: QEAx/QEBx/INDXx Pin Digital Filter Output Enable bit 1 = Digital filter outputs are enabled 0 = Digital filter outputs are disabled (normal pin operation) bit 6-4 QECK<2:0>: QEAx/QEBx/INDXx Digital Filter Clock Divide Select Bits 111 = 1:256 clock divide 110 = 1:128 clock divide 101 = 1:64 clock divide 100 = 1:32 clock divide 011 = 1:16 clock divide 010 = 1:4 clock divide 001 = 1:2 clock divide 000 = 1:1 clock divide bit 3-0 Unimplemented: Read as ‘0’ DS70000591F-page 264  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 18.0 SERIAL PERIPHERAL The Serial Peripheral Interface (SPI) module is a INTERFACE (SPI) synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These Note1: This data sheet summarizes the features peripheral devices can be serial EEPROMs, shift of the dsPIC33FJ32GS406/606/608/610 registers, display drivers, Analog-to-Digital Converters and dsPIC33FJ64GS406/606/608/610 and so on. The SPI module is compatible with the families of devices. It is not intended to be Motorola® SPI and SIOP modules. a comprehensive reference source. To The SPI module consists of a 16-bit shift register, complement the information in this data SPIxSR (where x = 1 or 2), used for shifting data in and sheet, refer to “Serial Peripheral out, and a buffer register, SPIxBUF. A control register, Interface (SPI)” (DS70005185) in the SPIxCON, configures the module. Additionally, a status “dsPIC33/PIC24 Family Reference Man- register, SPIxSTAT, indicates status conditions. ual”, which is available from the Microchip The serial interface consists of these four pins: web site (www.microchip.com). The information in this data sheet supersedes • SDIx (Serial Data Input) the information in the FRM. • SDOx (Serial Data Output) 2: Some registers and associated bits • SCKx (Shift Clock Input Or Output) described in this section may not be • SSx (Active-Low Slave Select) available on all devices. Refer to In Master mode operation, SCK is a clock output; in Section4.0 “Memory Organization” in Slave mode, it is a clock input. this data sheet for device-specific register and bit information. FIGURE 18-1: SPIx MODULE BLOCK DIAGRAM SCKx 1:1 to 1:8 1:1/4/16/64 Secondary Primary FCY Prescaler Prescaler SSx(1) Sync Control Select Control Clock Edge SPIxCON1<1:0> Shift Control SPIxCON1<4:2> SDOx Enable SDIx bit 0 Master Clock SPIxSR Transfer Transfer SPIxRXB SPIxTXB SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus Note 1: The SPI1 module can be connected to the SS1 or ASS1 pins, which are controlled by clearing or setting the ALTSS1 bit in the FPOR Configuration register. See Section24.0 “Special Features” for more information.  2009-2014 Microchip Technology Inc. DS70000591F-page 265

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 SPIEN — SPISIDL — — — — — bit 15 bit 8 U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0 — SPIROV — — — — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: SPIx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 SPIROV: SPIx Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded; the user software has not read the previous data in the SPIxBUF register 0 = No overflow has occurred bit 5-2 Unimplemented: Read as ‘0’ bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit has not yet started, SPIxTXB is full 0 = Transmit has started, SPIxTXB is empty. Automatically set in hardware when CPU writes the SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive is complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty. Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB. DS70000591F-page 266  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 18-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(3) CKP MSTEN SPRE2(2) SPRE1(2) SPRE0(2) PPRE1(2) PPRE0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCKx Pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled; pin functions as I/O 0 = Internal SPI clock is enabled bit 11 DISSDO: Disable SDOx Pin bit 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data is sampled at the end of data output time 0 = Input data is sampled at the middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. bit 8 CKE: SPIx Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) bit 7 SSEN: Slave Select Enable bit (Slave mode)(3) 1 = SSx pin is used for Slave mode 0 = SSx pin is not used by module; pin is controlled by port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: Do not set both primary and secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1.  2009-2014 Microchip Technology Inc. DS70000591F-page 267

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 18-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(2) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(2) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: Do not set both primary and secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. DS70000591F-page 268  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 18-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enabled (SSx pin is used as Frame Sync pulse input/output) 0 = Framed SPIx support is disabled bit 14 SPIFSD: Frame Sync Pulse Direction Control bit 1 = Frame Sync pulse input (slave) 0 = Frame Sync pulse output (master) bit 13 FRMPOL: Frame Sync Pulse Polarity bit 1 = Frame Sync pulse is active-high 0 = Frame Sync pulse is active-low bit 12-2 Unimplemented: Read as ‘0’ bit 1 FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame Sync pulse coincides with first bit clock 0 = Frame Sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application  2009-2014 Microchip Technology Inc. DS70000591F-page 269

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70000591F-page 270  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 19.0 INTER-INTEGRATED CIRCUIT 19.1 Operating Modes (I2C™) The hardware fully implements all the master and slave functions of the I2C Standard and Fast mode Note1: This data sheet summarizes the features specifications, as well as 7-bit and 10-bit addressing. of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 The I2C module can operate either as a slave or a families of devices. It is not intended to be master on an I2C bus. a comprehensive reference source. To The following types of I2C operation are supported: complement the information in this data • I2C slave operation with 7-bit addressing sheet, refer to “Inter-Integrated Cir- cuit™ (I2C™)” (DS70000195) in the • I2C slave operation with 10-bit addressing “dsPIC33/PIC24 Family Reference • I2C master operation with 7-bit or 10-bit addressing Manual”, which is available from the Micro- For details about the communication sequence in each chip web site (www.microchip.com). The of these modes, refer to the “dsPIC33/PIC24 Family information in this data sheet supersedes Reference Manual”. Please see the Microchip web site the information in the FRM. (www.microchip.com) for the latest “dsPIC33/PIC24 2: Some registers and associated bits Family Reference Manual” sections. described in this section may not be available on all devices. Refer to 19.2 I2C Registers Section4.0 “Memory Organization” in I2CxCON and I2CxSTAT are control and status this data sheet for device-specific register registers, respectively. The I2CxCON register is and bit information. readable and writable. The lower six bits of I2CxSTAT The Inter-Integrated Circuit (I2C) module provides are read-only. The remaining bits of the I2CSTAT are complete hardware support for both Slave and read/write: Multi-Master modes of the I2C serial communication • I2CxRSR is the shift register used for shifting data standard with a 16-bit interface. internal to the module and the user application The I2C module has a 2-pin interface: has no access to it. • The SCLx pin is clock. • I2CxRCV is the receive buffer and the register to which data bytes are written or from which data • The SDAx pin is data. bytes are read. The I2C module offers the following key features: • I2CxTRN is the transmit register to which bytes • I2C Interface Supporting Both Master and Slave are written during a transmit operation. modes of Operation • The I2CxADD register holds the slave address. • I2C Slave mode Supports 7-Bit and • A status bit, ADD10, indicates 10-Bit Addressing 10-Bit Addressing mode. • I2C Master mode Supports 7-Bit and • The I2CxBRG acts as the Baud Rate Generator 10-Bit Addressing (BRG) reload value. • I2C Port allows Bidirectional Transfers Between In receive operations, I2CxRSR and I2CxRCV together Master and Slaves form a double-buffered receiver. When I2CxRSR • Serial Clock Synchronization for I2C Port can be receives a complete byte, it is transferred to I2CxRCV used as a Handshake Mechanism to Suspend and an interrupt pulse is generated. and Resume Serial Transfer (SCLREL control) • I2C Supports Multi-Master Operation, Detects Bus Collision and Arbitrates Accordingly  2009-2014 Microchip Technology Inc. DS70000591F-page 271

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 19-1: I2Cx BLOCK DIAGRAM (X = 1 or 2) Internal Data Bus I2CxRCV Read Shift SCLx Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation I2CxSTAT c gi Read o CDoelltiseicotn ntrol L Write o C I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read ShiftClock Reload Control Write BRG Down Counter I2CxBRG Read TCY/2 DS70000591F-page 272  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module; all I2C pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Releases SCLx clock 0 = Holds SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear at beginning of slave transmission. Hardware is clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware is clear at beginning of slave transmission. bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = IPMI mode is enabled; all addresses are Acknowledged 0 = IPMI mode is disabled bit 10 A10M: 10-Bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control is disabled 0 = Slew rate control is enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with SMBus specification 0 = Disables SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C™ slave) 1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address is disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with the SCLREL bit. 1 = Enables software or receives clock stretching 0 = Disables software or receives clock stretching  2009-2014 Microchip Technology Inc. DS70000591F-page 273

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware clears at the end of the master Acknowledge sequence. 0 = Acknowledge sequence is not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clears at the end of the eighth bit of the master receive data byte. 0 = Receive sequence is not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on SDAx and SCLx pins. Hardware clears at the end of the master Stop sequence. 0 = Stop condition is not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware clears at the end of the master Repeated Start sequence. 0 = Repeated Start condition is not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiates Start condition on SDAx and SCLx pins. Hardware clears at the end of the master Start sequence. 0 = Start condition is not in progress DS70000591F-page 274  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HSC R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C™ master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware is set or clear at the end of slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware is set at the beginning of master transmission. Hardware is clear at the end of slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware is set when the address matches the general call address. Hardware is clear at Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware is set at the match of the 2nd byte of matched 10-bit address. Hardware is clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware is set at the occurrence of a write to I2CxTRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was a device address Hardware is clear at a device address match. Hardware is set by reception of a slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected.  2009-2014 Microchip Technology Inc. DS70000591F-page 275

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. bit 2 R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read – indicates data transfer is output from slave 0 = Write – indicates data transfer is input to slave Hardware is set or clear after reception of an I2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive is complete, I2CxRCV is full 0 = Receive is not complete, I2CxRCV is empty Hardware is set when I2CxRCV is written with a received byte. Hardware is clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit is complete, I2CxTRN is empty Hardware is set when software writes to I2CxTRN. Hardware is clear at completion of the data transmission. DS70000591F-page 276  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 19-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK<9:0>: Mask for Address bit x Select bits 1 = Enables masking for bit x of incoming message address; bit match is not required in this position 0 = Disables masking for bit x; bit match is required in this position  2009-2014 Microchip Technology Inc. DS70000591F-page 277

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70000591F-page 278  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 20.0 UNIVERSAL ASYNCHRONOUS The primary features of the UARTx module are: RECEIVER TRANSMITTER • Full-Duplex, 8-Bit or 9-Bit Data Transmission (UART) through the UxTX and UxRX Pins • Even, Odd or No Parity Options (for 8-bit data) Note1: This data sheet summarizes the features • One or Two Stop bits of the dsPIC33FJ32GS406/606/608/610 • Hardware Flow Control Option with UxCTS and and dsPIC33FJ64GS406/606/608/610 UxRTS Pins families of devices. It is not intended to be • Fully Integrated Baud Rate Generator with 16-Bit a comprehensive reference source. To Prescaler complement the information in this data • Baud Rates Ranging from 10Mbps to 38bps at sheet, refer to “UART” (DS70188) in the 40MIPS “dsPIC33/PIC24 Family Reference Man- • Baud Rates Ranging from 12.5Mbps to 47bps at ual”, which is available from the Microchip 50MIPS web site (www.microchip.com). The infor- • 4-Deep, First-In First-Out (FIFO) Transmit Data mation in this data sheet supersedes the Buffer information in the FRM. • 4-Deep FIFO Receive Data Buffer 2: Some registers and associated bits • Parity, Framing and Buffer Overrun Error Detection described in this section may not be • Support for 9-Bit mode with Address Detect available on all devices. Refer to (9thbit =1) Section4.0 “Memory Organization” in • Transmit and Receive Interrupts this data sheet for device-specific register • A Separate Interrupt for all UART Error Conditions and bit information. • Loopback mode for Diagnostic Support The Universal Asynchronous Receiver Transmitter • Support for Sync and Break Characters (UART) module is one of the serial I/O modules • Support for Automatic Baud Rate Detection available in the dsPIC33FJ32GS406/606/608/610 and • IrDA Encoder and Decoder Logic dsPIC33FJ64GS406/606/608/610 device families. The • 16x Baud Clock Output for IrDA® Support UART is a full-duplex, asynchronous system that can • Support for DMA communicate with peripheral devices, such as personal computers, LIN/JS2602, RS-232 and RS-485 A simplified block diagram of the UART module is shown in Figure20-1. The UART module consists of interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and these key hardware elements: also includes an IrDA encoder and decoder. • Baud Rate Generator • Asynchronous Transmitter • Asynchronous Receiver FIGURE 20-1: SIMPLIFIED UARTx BLOCK DIAGRAM Baud Rate Generator IrDA® Hardware Flow Control UxRTS/BCLK UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX  2009-2014 Microchip Technology Inc. DS70000591F-page 279

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 20-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UARTEN(1) — USIDL IREN(2) RTSMD — UEN1 UEN0 bit 15 bit 8 R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches, UARTx power consumption is minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: UARTx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder are enabled 0 = IrDA encoder and decoder are disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Pin Enable bits 11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin is controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins are controlled by port latches bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt is generated on falling edge, bit is cleared in hardware on following rising edge 0 = No wake-up is enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enables Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h) before other data; cleared in hardware upon completion 0 = Baud rate measurement is disabled or completed Note 1: Refer to “UART” (DS70188) in the “dsPIC33/PIC24 Family Reference Manual” for information on enabling the UART module for receive or transmit operation. That section of the manual is available on the Microchip web site: www.microchip.com. 2: This feature is only available for the 16x BRG mode (BRGH=0). DS70000591F-page 280  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: Refer to “UART” (DS70188) in the “dsPIC33/PIC24 Family Reference Manual” for information on enabling the UART module for receive or transmit operation. That section of the manual is available on the Microchip web site: www.microchip.com. 2: This feature is only available for the 16x BRG mode (BRGH=0).  2009-2014 Microchip Technology Inc. DS70000591F-page 281

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware Clearable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: UARTx Transmit Polarity Inversion bit If IREN = 0: 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ If IREN = 1: 1 = IrDA® encoded UxTX Idle state is ‘1’ 0 = IrDA encoded UxTX Idle state is ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: UARTx Transmit Break bit 1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission is disabled or has completed bit 10 UTXEN: UARTx Transmit Enable bit(1) 1 = Transmit is enabled, UxTX pin is controlled by UARTx 0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is controlled by the port bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full; at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits 11 = Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive buffer; receive buffer has one or more characters Note 1: Refer to “UART” (DS70188) in the “dsPIC33/PIC24 Family Reference Manual” for information on enabling the UART module for transmit operation. That section of the manual is available on the Microchip web site: www.microchip.com. DS70000591F-page 282  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data=1) 1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (the character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (the character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed; clearing a previously set OERR bit (10 transition) will reset the receiver buffer and the UxRSR to the empty state bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to “UART” (DS70188) in the “dsPIC33/PIC24 Family Reference Manual” for information on enabling the UART module for transmit operation. That section of the manual is available on the Microchip web site: www.microchip.com.  2009-2014 Microchip Technology Inc. DS70000591F-page 283

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70000591F-page 284  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 21.0 ENHANCED CAN (ECAN™) • Programmable Wake-up Functionality with MODULE Integrated Low-Pass Filter • Programmable Loopback mode Supports Note1: This data sheet summarizes the features Self-Test Operation of the dsPIC33FJ32GS406/606/608/610 • Signaling via Interrupt Capabilities for all CAN and dsPIC33FJ64GS406/606/608/610 Receiver and Transmitter Error States families of devices. It is not intended to be • Programmable Clock Source a comprehensive reference source. To • Programmable Link to Input Capture module complement the information in this data (IC2 for CAN1) for Time-Stamping and Network sheet, refer to “ECAN™” (DS70185) in the Synchronization dsPIC33/PIC24 Family Reference Manual, • Low-Power Sleep and Idle mode which is available from the Microchip web The CAN bus module consists of a protocol engine and site (www.microchip.com). The information message buffering/control. The CAN protocol engine in this data sheet supersedes the handles all functions for receiving and transmitting information in the FRM. messages on the CAN bus. Messages are transmitted 2: Some registers and associated bits by first loading the appropriate data registers. Status described in this section may not be and errors can be checked by reading the appropriate available on all devices. Refer to registers. Any message detected on the CAN bus is Section4.0 “Memory Organization” in checked for errors and then matched against filters to this data sheet for device-specific register see if it should be received and stored in one of the and bit information. receive registers. 21.1 Overview 21.2 Frame Types The Enhanced Controller Area Network (ECAN™) The CAN module transmits various types of frames module is a serial interface, useful for communicating with which include data messages, or remote transmission other ECAN modules or microcontroller devices. This requests initiated by the user, as other frames that are interface/protocol was designed to allow communications automatically generated for control purposes. The within noisy environments. The dsPIC33FJ64GS606/ following frame types are supported: 608/610 devices contain one ECAN module. • Standard Data Frame: A standard data frame is The ECAN module is a communication controller imple- generated by a node when the node wishes to menting the CAN 2.0 A/B protocol, as defined in the transmit data. It includes an 11-bit Standard Identifier BOSCH CAN specification. The module supports (SID), but not an 18-bit Extended Identifier (EID). CAN1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B • Extended Data Frame: An extended data frame is Active versions of the protocol. The module implementa- similar to a standard data frame, but includes an tion is a full CAN system. The CAN specification is not Extended Identifier as well. covered within this data sheet. The reader can refer to • Remote Frame: It is possible for a destination the BOSCH CAN specification for further details. node to request the data from the source. For this The module features are as follows: purpose, the destination node sends a remote frame with an identifier that matches the identifier • Implementation of the CAN Protocol, CAN1.2, of the required data frame. The appropriate data CAN2.0A and CAN2.0B source node sends a data frame as a response to • Standard and Extended Data Frames this remote request. • 0-8 Bytes Data Length • Error Frame: An error frame is generated by any • Programmable Bit Rate, up to 1 Mbit/sec node that detects a bus error. An error frame con- • Automatic Response to Remote Transmission sists of two fields: an error flag field and an error Requests delimiter field. • Up to 8 Transmit Buffers with Application-Specified • Overload Frame: An overload frame can be gen- Prioritization and Abort Capability (each buffer can erated by a node as a result of two conditions. contain up to 8 bytes of data) First, the node detects a dominant bit during inter- • Up to 32 Receive Buffers (each buffer can contain frame space which is an illegal condition. Second, up to 8 bytes of data) due to internal conditions, the node is not yet able • Up to 16 Full (Standard/Extended Identifier) to start reception of the next message. A node Acceptance Filters can generate a maximum of 2 sequential overload • Three Full Acceptance Filter Masks frames to delay the start of the next message. • DeviceNet™ Addressing Support • Interframe Space: Interframe space separates a proceeding frame (of whatever type) from a following data or remote frame.  2009-2014 Microchip Technology Inc. DS70000591F-page 285

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 21-1: ECANx MODULE BLOCK DIAGRAM RxF15 Filter RxF14 Filter RxF13 Filter RxF12 Filter RxF11 Filter DMA Controller RxF10 Filter RxF9 Filter RxF8 Filter TRB7 TX/RX Buffer Control Register RxF7 Filter TRB6 TX/RX Buffer Control Register RxF6 Filter TRB5 TX/RX Buffer Control Register RxF5 Filter TRB4 TX/RX Buffer Control Register RxF4 Filter TRB3 TX/RX Buffer Control Register RxF3 Filter TRB2 TX/RX Buffer Control Register RxF2 Filter RxM2 Mask TRB1 TX/RX Buffer Control Register RxF1 Filter RxM1 Mask TRB0 TX/RX Buffer Control Register RxF0 Filter RxM0 Mask Transmit Byte Message Assembly Sequencer Buffer Control CPU Configuration Bus Logic ECAN Protocol Engine Interrupts C1Tx C1Rx DS70000591F-page 286  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 21.3 Modes of Operation The module can be programmed to apply a low-pass filter function to the CxRX input line while the module or The ECAN™ module can operate in one of several the CPU is in Sleep mode. The WAKFIL bit operation modes selected by the user. These modes (CxCFG2<14>) enables or disables the filter. include: Note: Typically, if the ECAN module is allowed to • Initialization mode transmit in a particular mode of operation, • Disable mode and a transmission is requested immedi- • Normal Operation mode ately after the ECAN module has been • Listen Only mode placed in that mode of operation, the • Listen All Messages mode module waits for 11 consecutive recessive • Loopback mode bits on the bus before starting transmission. If the user switches to Disable mode within Modes are requested by setting the REQOP<2:0> bits this 11-bit period, then this transmission is (CxCTRL1<10:8>). Entry into a mode is Acknowledged aborted and the corresponding TXABTmn by monitoring the OPMODE<2:0> bits (CxCTRL1<7:5>). bit is set and the TXREQmn bit is cleared. The module does not change the mode and the OPMODE bits until a change in mode is acceptable, 21.3.3 NORMAL OPERATION MODE generally during bus Idle time, which is defined as at least 11 consecutive recessive bits. Normal Operation mode is selected when REQOP<2:0> = 000. In this mode, the module is 21.3.1 INITIALIZATION MODE activated and the I/O pins assume the CAN bus In the Initialization mode, the module does not transmit functions. The module transmits and receives CAN bus or receive. The error counters are cleared and the inter- messages via the CxTX and CxRX pins. rupt flags remain unchanged. The user application has 21.3.4 LISTEN ONLY MODE access to Configuration registers that are access restricted in other modes. The module protects the user If the Listen Only mode is activated, the module on the from accidentally violating the CAN protocol through CAN bus is passive. The transmitter buffers revert to programming errors. All registers which control the the port I/O function. The receive pins remain inputs. configuration of the module cannot be modified while For the receiver, no error flags or Acknowledge signals the module is on-line. The ECAN module is not allowed are sent. The error counters are deactivated in this to enter the Configuration mode while a transmission is state. The Listen Only mode can be used for detecting taking place. The Configuration mode serves as a lock the baud rate on the CAN bus. To use this, it is neces- to protect the following registers: sary that there are at least two further nodes that communicate with each other. • All Module Control Registers • Baud Rate and Interrupt Configuration Registers 21.3.5 LISTEN ALL MESSAGES MODE • Bus Timing Registers The module can be set to ignore all errors and receive • Identifier Acceptance Filter Registers any message. The Listen All Messages mode is acti- • Identifier Acceptance Mask Registers vated by setting REQOP<2:0> = 111. In this mode, the 21.3.2 DISABLE MODE data, which is in the message assembly buffer until the time an error occurred, is copied in the receive buffer In Disable mode, the module does not transmit or and can be read via the CPU interface. receive. The module has the ability to set the WAKIF bit due to bus activity, however, any pending interrupts 21.3.6 LOOPBACK MODE remain and the error counters retains their value. If the Loopback mode is activated, the module con- If the REQOP<2:0> bits (CxCTRL1<10:8>) = 001, the nects the internal transmit signal to the internal receive module enters the Module Disable mode. If the module signal at the module boundary. The transmit and is active, the module waits for 11 recessive bits on the receive pins revert to their port I/O function. CAN bus, detects that condition as an Idle bus, then accepts the module disable command. When the OPMODE<2:0> bits (CxCTRL1<7:5>) = 001, that indicates whether the module successfully went into Module Disable mode. The I/O pins revert to normal I/O function when the module is in the Module Disable mode.  2009-2014 Microchip Technology Inc. DS70000591F-page 287

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-1: CxCTRL1: ECANx CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 r-0 R/W-1 R/W-0 R/W-0 — — CSIDL ABAT r REQOP2 REQOP1 REQOP0 bit 15 bit 8 R-1 R-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0 OPMODE2 OPMODE1 OPMODE0 — CANCAP — — WIN bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: ECANx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 ABAT: Abort All Pending Transmissions bit 1 = Signals all transmit buffers to abort transmission 0 = Module will clear this bit when all transmissions are aborted bit 11 Reserved: Do not use bit 10-8 REQOP<2:0>: Request Operation Mode bits 111 = Sets Listen All Messages mode 110 = Reserved 101 = Reserved 100 = Sets Configuration mode 011 = Sets Listen Only Mode 010 = Sets Loopback mode 001 = Sets Disable mode 000 = Sets Normal Operation mode bit 7-5 OPMODE<2:0>: Operation Mode bits 111 = Module is in Listen All Messages mode 110 = Reserved 101 = Reserved 100 = Module is in Configuration mode 011 = Module is in Listen Only mode 010 = Module is in Loopback mode 001 = Module is in Disable mode 000 = Module is in Normal Operation mode bit 4 Unimplemented: Read as ‘0’ bit 3 CANCAP: ECAN Message Receive Timer Capture Event Enable bit 1 = Enables input capture based on ECAN message receive 0 = Disables ECAN capture bit 2-1 Unimplemented: Read as ‘0’ bit 0 WIN: SFR Map Window Select bit 1 = Uses filter window 0 = Uses buffer window DS70000591F-page 288  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-2: CxCTRL2: ECANx CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — DNCNT<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compares up to Data Byte 3, bit 6 with EID<17> • • • 00001 = Compares up to Data Byte 1, bit 7 with EID<0> 00000 = Does not compare data bytes  2009-2014 Microchip Technology Inc. DS70000591F-page 289

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-3: CxVEC: ECANx INTERRUPT CODE REGISTER U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 15 bit 8 U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0 — ICODE6 ICODE5 ICODE4 ICODE3 ICODE2 ICODE1 ICODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit Number bits 10000-11111 = Reserved 01111 = Filter 15 • • • 00001 = Filter 1 00000 = Filter 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 ICODE<6:0>: Interrupt Flag Code bits 1000101-1111111 = Reserved 1000100 = FIFO almost full interrupt 1000011 = Receiver overflow interrupt 1000010 = Wake-up interrupt 1000001 = Error interrupt 1000000 = No interrupt • • • 0010000-0111111 = Reserved 0001111 = RB15 buffer interrupt • • • 0001001 = RB9 buffer interrupt 0001000 = RB8 buffer interrupt 0000111 = TRB7 buffer interrupt 0000110 = TRB6 buffer interrupt 0000101 = TRB5 buffer interrupt 0000100 = TRB4 buffer interrupt 0000011 = TRB3 buffer interrupt 0000010 = TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 Buffer interrupt DS70000591F-page 290  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-4: CxFCTRL: ECANx FIFO CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 DMABS2 DMABS1 DMABS0 — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FSA4(1) FSA3(1) FSA2(1) FSA1(1) FSA0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in DMA RAM 101 = 24 buffers in DMA RAM 100 = 16 buffers in DMA RAM 011 = 12 buffers in DMA RAM 010 = 8 buffers in DMA RAM 001 = 6 buffers in DMA RAM 000 = 4 buffers in DMA RAM bit 12-5 Unimplemented: Read as ‘0’ bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits(1) 11111 = Reads Buffer RB31 11110 = Reads Buffer RB30 • • • 00001 = TX/RX Buffer TRB1 00000 = TX/RX Buffer TRB0 Note 1: FSA<4:0> bits are used to specify the start of the FIFO within the buffer area.  2009-2014 Microchip Technology Inc. DS70000591F-page 291

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-5: CxFIFO: ECANx FIFO STATUS REGISTER U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — FBP5 FBP4 FBP3 FBP2 FBP1 FBP0 bit 15 bit 8 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — FNRB5 FNRB4 FNRB3 FNRB2 FNRB1 FNRB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FBP<5:0>: FIFO Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer • • • 000001 = TRB1 buffer 000000 = TRB0 buffer bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 FNRB<5:0>: FIFO Next Read Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer • • • 000001 = TRB1 buffer 000000 = TRB0 buffer DS70000591F-page 292  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-6: CxINTF: ECANx INTERRUPT FLAG REGISTER U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — TXBO TXBP RXBP TXWAR RXWAR EWARN bit 15 bit 8 R/C-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF bit 7 bit 0 Legend: C = Writable, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 TXBO: Transmitter in Error State Bus Off bit 1 = Transmitter is in Bus Off state 0 = Transmitter is not in Bus Off state bit 12 TXBP: Transmitter in Error State Bus Passive bit 1 = Transmitter is in Bus Passive state 0 = Transmitter is not in Bus Passive state bit 11 RXBP: Receiver in Error State Bus Passive bit 1 = Receiver is in Bus Passive state 0 = Receiver is not in Bus Passive state bit 10 TXWAR: Transmitter in Error State Warning bit 1 = Transmitter is in Error Warning state 0 = Transmitter is not in Error Warning state bit 9 RXWAR: Receiver in Error State Warning bit 1 = Receiver is in Error Warning state 0 = Receiver is not in Error Warning state bit 8 EWARN: Transmitter or Receiver in Error State Warning bit 1 = Transmitter or receiver is in Error Warning state 0 = Transmitter or receiver is not in Error Warning state bit 7 IVRIF: Invalid Message Received Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 WAKIF: Bus Wake-up Activity Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 ERRIF: Error Interrupt Flag bit (multiple sources in CxINTF<13:8> register bits) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 Unimplemented: Read as ‘0’ bit 3 FIFOIF: FIFO Almost Full Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2009-2014 Microchip Technology Inc. DS70000591F-page 293

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-6: CxINTF: ECANx INTERRUPT FLAG REGISTER (CONTINUED) bit 1 RBIF: RX Buffer Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 TBIF: TX Buffer Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70000591F-page 294  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-7: CxINTE: ECANx INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IVRIE: Invalid Message Received Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 WAKIE: Bus Wake-up Activity Interrupt Flag bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 ERRIE: Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4 Unimplemented: Read as ‘0’ bit 3 FIFOIE: FIFO Almost Full Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 RBOVIE: RX Buffer Overflow Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 RBIE: RX Buffer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 TBIE: TX Buffer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2009-2014 Microchip Technology Inc. DS70000591F-page 295

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-8: CxEC: ECANx TRANSMIT/RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TERRCNT7 TERRCNT6 TERRCNT5 TERRCNT4 TERRCNT3 TERRCNT2 TERRCNT1 TERRCNT0 bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RERRCNT7 RERRCNT6 RERRCNT5 RERRCNT4 RERRCNT3 RERRCNT2 RERRCNT1 RERRCNT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 TERRCNT<7:0>: Transmit Error Count bits bit 7-0 RERRCNT<7:0>: Receive Error Count bits REGISTER 21-9: CxCFG1: ECANx BAUD RATE CONFIGURATION REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 SJW<1:0>: Synchronization Jump Width bits 11 = Length is 4 x TQ 10 = Length is 3 x TQ 01 = Length is 2 x TQ 00 = Length is 1 x TQ bit 5-0 BRP<5:0>: Baud Rate Prescaler bits 11 1111 = TQ = 2 x 64 x 1/FCAN • • • 00 0010 = TQ = 2 x 3 x 1/FCAN 00 0001 = TQ = 2 x 2 x 1/FCAN 00 0000 = TQ = 2 x 1 x 1/FCAN DS70000591F-page 296  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-10: CxCFG2: ECANx BAUD RATE CONFIGURATION REGISTER 2 U-0 R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x — WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 WAKFIL: Select ECAN Bus Line Filter for Wake-up bit 1 = Uses ECAN bus line filter for wake-up 0 = ECAN bus line filter is not used for wake-up bit 13-11 Unimplemented: Read as ‘0’ bit 10-8 SEG2PH<2:0>: Phase Segment 2 bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of SEG1PHx bits or Information Processing Time (IPT), whichever is greater bit 6 SAM: Sample of the ECAN Bus Line bit 1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sample point bit 5-3 SEG1PH<2:0>: Phase Segment 1 bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ bit 2-0 PRSEG<2:0>: Propagation Time Segment bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ  2009-2014 Microchip Technology Inc. DS70000591F-page 297

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-11: CxFEN1: ECANx ACCEPTANCE FILTER ENABLE REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 FLTEN<15:0>: Enable Filter n to Accept Messages bits 1 = Enables Filter n 0 = Disables Filter n REGISTER 21-12: CxBUFPNT1: ECANx FILTER 0-3 BUFFER POINTER REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F3BP3 F3BP2 F3BP1 F3BP0 F2BP3 F2BP2 F2BP1 F2BP0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F1BP3 F1BP2 F1BP1 F1BP0 F0BP3 F0BP2 F0BP1 F0BP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F3BP<3:0>: RX Buffer Mask for Filter 3 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F2BP<3:0>: RX Buffer Mask for Filter 2 bits (same values as bits<15:12>) bit 7-4 F1BP<3:0>: RX Buffer Mask for Filter 1 bits (same values as bits<15:12>) bit 3-0 F0BP<3:0>: RX Buffer Mask for Filter 0 bits (same values as bits<15:12>) DS70000591F-page 298  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-13: CxBUFPNT2: ECANx FILTER 4-7 BUFFER POINTER REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7BP3 F7BP2 F7BP1 F7BP0 F6BP3 F6BP2 F6BP1 F6BP0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F5BP3 F5BP2 F5BP1 F5BP0 F4BP3 F4BP2 F4BP1 F4BP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F7BP<3:0>: RX Buffer Mask for Filter 7 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F6BP<3:0>: RX Buffer Mask for Filter 6 bits (same values as bits<15:12>) bit 7-4 F5BP<3:0>: RX Buffer Mask for Filter 5 bits (same values as bits<15:12>) bit 3-0 F4BP<3:0>: RX Buffer Mask for Filter 4 bits (same values as bits<15:12>)  2009-2014 Microchip Technology Inc. DS70000591F-page 299

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-14: CxBUFPNT3: ECANx FILTER 8-11 BUFFER POINTER REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F11BP3 F11BP2 F11BP1 F11BP0 F10BP3 F10BP2 F10BP1 F10BP0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F9BP3 F9BP2 F9BP1 F9BP0 F8BP3 F8BP2 F8BP1 F8BP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F11BP<3:0>: RX Buffer Mask for Filter 11 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F10BP<3:0>: RX Buffer Mask for Filter 10 bits (same values as bits<15:12>) bit 7-4 F9BP<3:0>: RX Buffer Mask for Filter 9 bits (same values as bits<15:12>) bit 3-0 F8BP<3:0>: RX Buffer Mask for Filter 8 bits (same values as bits<15:12>) DS70000591F-page 300  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-15: CxBUFPNT4: ECANx FILTER 12-15 BUFFER POINTER REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15BP3 F15BP2 F15BP1 F15BP0 F14BP3 F14BP2 F14BP1 F14BP0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F13BP3 F13BP2 F13BP1 F13BP0 F12BP3 F12BP2 F12BP1 F12BP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F15BP<3:0>: RX Buffer Mask for Filter 15 bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F14BP<3:0>: RX Buffer Mask for Filter 14 bits (same values as bits<15:12>) bit 7-4 F13BP<3:0>: RX Buffer Mask for Filter 13 bits (same values as bits<15:12>) bit 3-0 F12BP<3:0>: RX Buffer Mask for Filter 12 bits (same values as bits<15:12>)  2009-2014 Microchip Technology Inc. DS70000591F-page 301

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-16: CxRXFnSID: ECANx ACCEPTANCE FILTER n STANDARD IDENTIFIER REGISTER (n = 0-15) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 SID<10:0>: Standard Identifier bits 1 = Message address bit, SIDx, must be ‘1’ to match filter 0 = Message address bit, SIDx, must be ‘0’ to match filter bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDE: Extended Identifier Enable bit If MIDE = 1, then: 1 = Matches only messages with Extended Identifier addresses 0 = Matches only messages with Standard Identifier addresses If MIDE = 0, then: Ignores EXIDE bit. bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits 1 = Message address bit, EIDx, must be ‘1’ to match filter 0 = Message address bit, EIDx, must be ‘0’ to match filter DS70000591F-page 302  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-17: CxRXFnEID: ECANx ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTER (n = 0-15) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID<15:8> bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 EID<15:0>: Extended Identifier bits 1 = Message address bit, EIDx, must be ‘1’ to match filter 0 = Message address bit, EIDx, must be ‘0’ to match filter REGISTER 21-18: CxFMSKSEL1: ECANx FILTER 7-0 MASK SELECTION REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7MSK1 F7MSK0 F6MSK1 F6MSK0 F5MSK1 F5MSK0 F4MSK1 F4MSK0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F3MSK1 F3MSK0 F2MSK1 F2MSK0 F1MSK1 F1MSK0 F0MSK1 F0MSK1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 F7MSK<1:0>: Mask Source for Filter 7 bits 11 = Reserved 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask bit 13-12 F6MSK<1:0>: Mask Source for Filter 6 bits (same values as bits<15:14>) bit 11-10 F5MSK<1:0>: Mask Source for Filter 5 bits (same values as bits<15:14>) bit 9-8 F4MSK<1:0>: Mask Source for Filter 4 bits (same values as bits<15:14>) bit 7-6 F3MSK<1:0>: Mask Source for Filter 3 bits (same values as bits<15:14>) bit 5-4 F2MSK<1:0>: Mask Source for Filter 2 bits (same values as bits<15:14>) bit 3-2 F1MSK<1:0>: Mask Source for Filter 1 bits (same values as bits<15:14>) bit 1-0 F0MSK<1:0>: Mask Source for Filter 0 bits (same values as bits<15:14>)  2009-2014 Microchip Technology Inc. DS70000591F-page 303

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-19: CxFMSKSEL2: ECANx FILTER 15-8 MASK SELECTION REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15MSK1 F15MSK0 F14MSK1 F14MSK0 F13MSK1 F13MSK0 F12MSK1 F12MSK0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F11MSK1 F11MSK0 F10MSK1 F10MSK0 F9MSK1 F9MSK0 F8MSK1 F8MSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 F15MSK<1:0>: Mask Source for Filter 15 bits 11 = Reserved 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask bit 13-12 F14MSK<1:0>: Mask Source for Filter 14 bits (same values as bits<15:14>) bit 11-10 F13MSK<1:0>: Mask Source for Filter 13 bits (same values as bits<15:14>) bit 9-8 F12MSK<1:0>: Mask Source for Filter 12 bits (same values as bits<15:14>) bit 7-6 F11MSK<1:0>: Mask Source for Filter 11 bits (same values as bits<15:14>) bit 5-4 F10MSK<1:0>: Mask Source for Filter 10 bits (same values as bits<15:14>) bit 3-2 F9MSK<1:0>: Mask Source for Filter 9 bits (same values as bits<15:14>) bit 1-0 F8MSK<1:0>: Mask Source for Filter 8 bits (same values as bits<15:14>) DS70000591F-page 304  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-20: CxRXMnSID: ECANx ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER REGISTER (n = 0-2) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — MIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 SID<10:0>: Standard Identifier bits 1 = Includes bit, SIDx, in filter comparison 0 = SIDx bit is don’t care in filter comparison bit 4 Unimplemented: Read as ‘0’ bit 3 MIDE: Identifier Receive Mode bit 1 = Matches only message types (standard or extended address) that correspond to EXIDE bit in filter 0 = Matches either standard or extended address message if filters match (i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID)) bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits 1 = Includes bit, EIDx, in filter comparison 0 = EIDx bit is don’t care in filter comparison REGISTER 21-21: CxRXMnEID: ECANx ACCEPTANCE FILTER MASK n EXTENDED IDENTIFIER REGISTER (n = 0-2) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 EID<15:0>: Extended Identifier bits 1 = Includes bit, EIDx, in filter comparison 0 = EIDx bit is don’t care in filter comparison  2009-2014 Microchip Technology Inc. DS70000591F-page 305

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-22: CxRXFUL1: ECANx RECEIVE BUFFER FULL REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 bit 7 bit 0 Legend: C = Writeable, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXFUL<15:0>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty REGISTER 21-23: CxRXFUL2: ECANx RECEIVE BUFFER FULL REGISTER 2 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 bit 7 bit 0 Legend: C = Writeable, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXFUL<31:16>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty DS70000591F-page 306  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-24: CxRXOVF1: ECANx RECEIVE BUFFER OVERFLOW REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF<15:8> bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF<7:0> bit 7 bit 0 Legend: C = Writeable, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXOVF<15:0>: Receive Buffer n Overflow bits 1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition REGISTER 21-25: CxRXOVF2: ECANx RECEIVE BUFFER OVERFLOW REGISTER 2 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF<31:24> bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF<23:16> bit 7 bit 0 Legend: C = Writeable, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXOVF<31:16>: Receive Buffer n Overflow bits 1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition  2009-2014 Microchip Technology Inc. DS70000591F-page 307

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 21-26: CxTRmnCON: ECANx TX/RX BUFFER mn CONTROL REGISTER (m = 0, 2, 4, 6; n = 1, 3, 5, 7) R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn TXnPRI1 TXnPRI0 bit 15 bit 8 R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXENm TXABTm(1) TXLARBm(1) TXERRm(1) TXREQm RTRENm TXmPRI1 TXmPRI0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 See Definition for bits<7:0>, Controls Buffer n bit 7 TXENm: TX/RX Buffer Selection bit 1 = Buffer TRBn is a transmit buffer 0 = Buffer TRBn is a receive buffer bit 6 TXABTm: Message Aborted bit(1) 1 = Message was aborted 0 = Message completed transmission successfully bit 5 TXLARBm: Message Lost Arbitration bit(1) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERRm: Error Detected During Transmission bit(1) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQm: Message Send request bit 1 = Requests that a message be sent; the bit automatically clears when the message is successfully sent 0 = Clears the bit to ‘0’; while set, requests a message abort bit 2 RTRENm: Auto-Remote Transmit Enable bit 1 = When a remote transmit is received, TXREQm will be set 0 = When a remote transmit is received, TXREQm will be unaffected bit 1-0 TXmPRI<1:0>: Message Transmission Priority bits 11 = Highest message priority 10 = High intermediate message priority 01 = Low intermediate message priority 00 = Lowest message priority Note 1: This bit is cleared when TXREQm is set. Note: The buffers, SID, EID, DLC, Data Field, and Receive Status registers are located in DMA RAM. DS70000591F-page 308  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 21.4 ECANx Message Buffers ECANx message buffers are part of DMA RAM memory. They are not ECAN Special Function Registers. The user application must directly write into the DMA RAM area that is configured for ECANx message buffers. The location and size of the buffer area is defined by the user application. BUFFER 21-1: ECANx MESSAGE BUFFER WORD 0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — SID10 SID9 SID8 SID7 SID6 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID5 SID4 SID3 SID2 SID1 SID0 SRR IDE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-2 SID<10:0>: Standard Identifier bits bit 1 SRR: Substitute Remote Request bit 1 = Message will request remote transmission 0 = Normal message bit 0 IDE: Extended Identifier bit 1 = Message will transmit the Extended Identifier 0 = Message will transmit the Standard Identifier BUFFER 21-2: ECANx MESSAGE BUFFER WORD 1 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x — — — — EID<17:14> bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID<13:6> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 EID<17:6>: Extended Identifier bits  2009-2014 Microchip Technology Inc. DS70000591F-page 309

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 (BUFFER 21-3: ECANx MESSAGE BUFFER WORD 2 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID5 EID4 EID3 EID2 EID1 EID0 RTR RB1 bit 15 bit 8 U-x U-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x — — — RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 EID<5:0>: Extended Identifier bits bit 9 RTR: Remote Transmission Request bit 1 = Message will request remote transmission 0 = Normal message bit 8 RB1: Reserved Bit 1 User must set this bit to ‘0’ per ECAN™ protocol. bit 7-5 Unimplemented: Read as ‘0’ bit 4 RB0: Reserved Bit 0 User must set this bit to ‘0’ per ECAN protocol. bit 3-0 DLC<3:0>: Data Length Code bits BUFFER 21-4: ECANx MESSAGE BUFFER WORD 3 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 1 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 1<15:8>: ECANx Message Byte 1 bit 7-0 Byte 0<7:0>: ECANx Message Byte 0 DS70000591F-page 310  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 BUFFER 21-5: ECANx MESSAGE BUFFER WORD 4 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 3 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 3<15:8>: ECANx Message Byte 3 bit 7-0 Byte 2<7:0>: ECANx Message Byte 2 BUFFER 21-6: ECANx MESSAGE BUFFER WORD 5 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 5 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 4 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 5<15:8>: ECANx Message Byte 5 bit 7-0 Byte 4<7:0>: ECANx Message Byte 4  2009-2014 Microchip Technology Inc. DS70000591F-page 311

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 BUFFER 21-7: ECANx MESSAGE BUFFER WORD 6 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 7 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 6 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 7<15:8>: ECANx Message Byte 7 bit 7-0 Byte 6<7:0>: ECANx Message Byte 6 BUFFER 21-8: ECANx MESSAGE BUFFER WORD 7 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — FILHIT<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit Code bits(1) Encodes number of filter that resulted in writing this buffer. bit 7-0 Unimplemented: Read as ‘0’ Note 1: Only written by module for receive buffers, unused for transmit buffers. DS70000591F-page 312  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 22.0 HIGH-SPEED, 10-BIT 22.2 Module Description ANALOG-TO-DIGITAL This ADC module is designed for applications that CONVERTER (ADC) require low latency between the request for conversion and the resultant output data. Typical applications Note1: This data sheet summarizes the features include: of the dsPIC33FJ32GS406/606/608/610 • AC/DC Power Supplies and dsPIC33FJ64GS406/606/608/610 • DC/DC Converters families of devices. It is not intended to be a comprehensive reference source. • Power Factor Correction (PFC) To complement the information in this This ADC works with the High-Speed PWM module in data sheet, refer to “High-Speed power control applications that require high-frequency 10-Bit ADC” (DS70000321) in the control loops. This module can Sample-and-Convert “dsPIC33/PIC24 Family Reference two analog inputs in a 0.5 microsecond when two SARs Manual”, which is available from the are used. This small conversion delay reduces the Microchip web site (www.microchip.com). “phase lag” between measurement and control system The information in this data sheet response. supersedes the information in the FRM. Up to five inputs may be sampled at a time (four inputs 2: Some registers and associated bits from the dedicated Sample-and-Hold circuits and one described in this section may not be from the shared Sample-and-Hold circuit). If multiple available on all devices. Refer to inputs request conversion, the ADC will convert them in Section4.0 “Memory Organization” in a sequential manner, starting with the lowest order this data sheet for device-specific register input. and bit information. This ADC design provides each pair of analog inputs The dsPIC33FJ32GS406/606/608/610 and (AN1, AN0), (AN3, AN2),..., the ability to specify its own dsPIC33FJ64GS406/606/608/610 devices provide trigger source out of a maximum of sixteen different high-speed successive approximation Analog-to-Digital trigger sources. This capability allows this ADC to conversions to support applications, such as AC/DC and Sample-and-Convert analog inputs that are associated DC/DC power converters. with PWM generators operating on independent time bases. 22.1 Features Overview The user application typically requires synchronization between analog data sampling and PWM output to the The ADC module incorporates the following features: application circuit. The very high-speed operation of • 10-Bit Resolution this ADC module allows “data on demand”. • Unipolar Inputs In addition, several hardware features have been • Up to Two Successive Approximation Registers added to the peripheral interface to improve real-time (SARs) performance in a typical DSP-based application. • Up to 24 External Input Channels • Result Alignment Options • Two Internal Analog Inputs • Automated Sampling • Dedicated Result Register for each Analog Input • External Conversion Start Control • ±1 LSB Accuracy at 3.3V • Two Internal Inputs to Monitor the INTREF and • Single Supply Operation EXTREF Input Signals • 4 Msps Conversion Rate at 3.3V (devices with Block diagrams of the ADC module for the family two SARs) devices are shown in Figure22-1 through Figure22-4. • 2 Msps Conversion Rate at 3.3V (devices with one SAR) • Low-Power CMOS Technology  2009-2014 Microchip Technology Inc. DS70000591F-page 313

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 22.3 Module Functionality The ADC module uses the following control and status registers: The High-Speed, 10-Bit ADC is designed to support • ADCON: ADC Control Register power conversion applications when used with the High-Speed PWM module. The ADC may have one or • ADSTAT: ADC Status Register two SAR modules, depending on the device variant. If • ADBASE: ADC Base Register(1,2) two SARs are present on a device, two conversions • ADPCFG: ADC Port Configuration Register can be processed at a time, yielding 4 Msps conversion • ADPCFG2: ADC Port Configuration Register2 rate. If only one SAR is present on a device, only one • ADCPC0: ADC Convert Pair Control Register 0 conversion can be processed at a time, yielding 2 Msps • ADCPC1: ADC Convert Pair Control Register 1 conversion rate. The High-Speed, 10-Bit ADC produces two 10-bit conversion results in a 0.5 microsecond. • ADCPC2: ADC Convert Pair Control Register 2 • ADCPC3: ADC Convert Pair Control Register 3 The ADC module supports up to 24 external analog inputs and two internal analog inputs. To monitor • ADCPC4: ADC Convert Pair Control Register 4 reference voltage, two internal inputs, AN24 and AN25, • ADCPC5: ADC Convert Pair Control Register 5 are connected to EXTREF and INTREF, respectively. • ADCPC6: ADC Convert Pair Control Register 6(2) The analog reference voltage is defined as the device The ADCON register controls the operation of the supply voltage (AVDD/AVSS). ADC module. The ADSTAT register displays the status of the conversion processes. The ADPCFG registers configure the port pins as analog inputs or as digital I/O. The ADCPCx registers control the triggering of the ADC conversions. See Register22-1 through Register22-12 for detailed bit configurations. Note: A unique feature of the ADC module is its ability to sample inputs in an asynchronous manner. Individual Sample-and-Hold circuits can be triggered independently of each other. DS70000591F-page 314  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 22-1: ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 AN2 e c AN4 CSoArRe DataFormat RSe1igx6ti-seBteeitnrs s Interfa u B AN6 AN1 Shared Sample-and-Hold AN3 AN5 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15  2009-2014 Microchip Technology Inc. DS70000591F-page 315

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 22-2: ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS606 AND dsPIC33FJ64GS606 DEVICES WITH TWO SARs Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 AN2 CSoArRe Dataormat Re1Ng6ii-nsBteeitrs F AN4 AN6 Even Numbered Inputs AN8 with Shared S&H e c a erf AN10 s Int u B AN12 AN14 AN24(1) (EXTREF) Odd Numbered Inputs AN1 with Shared S&H AANN53 CSoArRe DataFormat Re1Ng6ii-nsBteeitrs AN7 AN9 AN11 AN13 AN15 AN25(2) (INTREF) Note1: AN24 (EXTREF) is an internal analog input. To measure the voltage at AN24 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. 2: AN25 (INTREF) is an internal analog input and is not available on a pin. DS70000591F-page 316  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 22-3: ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES WITH TWO SARs Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 AN2 CSoArRe Dataormat Re1gT6ei-sBnteitrs F AN4 AN6 Even Numbered Inputs AN8 with Shared S&H e c AN10 a erf nt AN12 s I u B AN14 AN16 AN24(1) (EXTREF) AN1 Odd Numbered Inputs with Shared S&H AN3 CSoArRe Dataormat Re1gT6ei-sBnteitrs AN5 F AN7 AN9 AN11 AN13 AN15 AN17 AN25(2) (INTREF) Note1: AN24 (EXTREF) is an internal analog input. To measure the voltage at AN24 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. 2: AN25 (INTREF) is an internal analog input and is not available on a pin.  2009-2014 Microchip Technology Inc. DS70000591F-page 317

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 22-4: ADC BLOCK DIAGRAM FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES WITH TWO SARs Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 AN2 CSoArRe Dataormat RTe1hg6iri-tsBeteeitrns F AN4 AN6 Even Numbered Inputs AN8 with Shared S&H e c a AN10 erf nt AN12 s I u AN14 B AN16 AN18 AN20 AN22 AN24(1) (EXTREF) AN1 Odd Numbered Inputs with Shared S&H AN3 CSoArRe Dataormat RTe1hg6iri-tsBeteeitrns F AN5 AN7 AN9 AN11 AN13 AN15 AN17 AN19 AN21 AN23 AN25(2) (INTREF) Note1: AN24 (EXTREF) is an internal analog input. To measure the voltage at AN24 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. 2: AN25 (INTREF) is an internal analog input and is not available on a pin. DS70000591F-page 318  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-1: ADCON: ADC CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 ADON — ADSIDL SLOWCLK(1) — GSWTRG — FORM(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-1 R/W-1 EIE(1) ORDER(1,2) SEQSAMP(1,2) ASYNCSAMP(1) — ADCS2(1) ADCS1(1) ADCS0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: ADC Module Operating Mode bit 1 = ADC module is operating 0 = ADC module is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: ADC Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 SLOWCLK: Enable the Slow Clock Divider bit(1) 1 = ADC is clocked by the auxiliary PLL (ACLK) 0 = ADC is clock by the primary PLL (FVCO) bit 11 Unimplemented: Read as ‘0’ bit 10 GSWTRG: Global Software Trigger bit When this bit is set by the user, it will trigger conversions if selected by the TRGSRCx<4:0> bits in the ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e., this bit is not auto-clearing). bit 9 Unimplemented: Read as ‘0’ bit 8 FORM: Data Output Format bit(1) 1 = Fractional (DOUT = dddd dddd dd00 0000) 0 = Integer (DOUT=0000 00dd dddd dddd) bit 7 EIE: Early Interrupt Enable bit(1) 1 = Interrupt is generated after first conversion is completed 0 = Interrupt is generated after second conversion is completed bit 6 ORDER: Conversion Order bit(1,2) 1 = Odd numbered analog input is converted first, followed by conversion of even numbered input 0 = Even numbered analog input is converted first, followed by conversion of odd numbered input bit 5 SEQSAMP: Sequential S&H Sampling Enable bit(1,2) 1 = Shared Sample-and-Hold (S&H) circuit is sampled at the start of the second conversion if ORDER=0. If ORDER = 1, then the shared S&H is sampled at the start of the first conversion. 0 = Shared S&H is sampled at the same time the dedicated S&H is sampled if the shared S&H is not cur- rently busy with an existing conversion process. If the shared S&H is busy at the time the dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion cycle. Note 1: This control bit can only be changed while the ADC is disabled (ADON = 0). 2: This control bit is only active on devices that have one SAR.  2009-2014 Microchip Technology Inc. DS70000591F-page 319

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-1: ADCON: ADC CONTROL REGISTER (CONTINUED) bit 4 ASYNCSAMP: Asynchronous Dedicated S&H Sampling Enable bit(1) 1 = The dedicated S&H is constantly sampling and then terminates sampling as soon as the trigger pulse is detected 0 = The dedicated S&H starts sampling when the trigger event is detected and completes the sampling process in two ADC clock cycles bit 3 Unimplemented: Read as ‘0’ bit 2-0 ADCS<2:0>: Analog-to-Digital Conversion Clock Divider Select bits(1) 111 = FADC/8 110 = FADC/7 101 = FADC/6 100 = FADC/5 011 = FADC/4 (default) 010 = FADC/3 001 = FADC/2 000 = FADC/1 Note 1: This control bit can only be changed while the ADC is disabled (ADON = 0). 2: This control bit is only active on devices that have one SAR. DS70000591F-page 320  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R E GISTER 22-2: ADSTAT: ADC STATUS REGISTER U-0 U-0 U-0 R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS — — — P12RDY(1) P11RDY(1) P10RDY(1) P9RDY(1) P8RDY(1) bit 15 bit 8 R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS P7RDY(1) P6RDY(1) P5RDY(1) P4RDY(1) P3RDY(1) P2RDY(1) P1RDY(1) P0RDY(1) bit 7 bit 0 Legend: C = Clearable bit HS - Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 6 P12RDY: Conversion Data for Pair 12 Ready bit(1) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 5 P11RDY: Conversion Data for Pair 11 Ready bit(1) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 4 P10RDY: Conversion Data for Pair 10 Ready bit(1) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 3 P9RDY: Conversion Data for Pair 9 Ready bit(1) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 2 P8RDY: Conversion Data for Pair 8 Ready bit(1) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 1 P7RDY: Conversion Data for Pair 7 Ready bit(1) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 6 P6RDY: Conversion Data for Pair 6 Ready bit(1) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 5 P5RDY: Conversion Data for Pair 5 Ready bit(1) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 4 P4RDY: Conversion Data for Pair 4 Ready bit(1) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 3 P3RDY: Conversion Data for Pair 3 Ready bit(1) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 2 P2RDY: Conversion Data for Pair 2 Ready bit(1) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 1 P1RDY: Conversion Data for Pair 1 Ready bit(1) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 0 P0RDY: Conversion Data for Pair 0 Ready bit(1) Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. Note 1: Not all PxRDY bits are available on all devices. See Figure22-1, Figure22-2, Figure22-3 and Figure22-4 for the available analog inputs.  2009-2014 Microchip Technology Inc. DS70000591F-page 321

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-3: ADBASE: ADC BASE REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADBASE<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 ADBASE<7:1> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 ADBASE<15:1>: ADC Base Address bits This register contains the base address of the user’s ADC Interrupt Service Routine jump table. This register, when read, contains the sum of the ADBASE register contents and the encoded value of the PxRDY status bits. The encoder logic provides the bit number of the highest priority PxRDY bits where P0RDY is the highest priority and P6RDY is the lowest priority. bit 0 Unimplemented: Read as ‘0’ Note 1: The encoding results are shifted left two bits so bits 1-0 of the result are always zero. 2: As an alternative to using the ADBASE register, the ADCP0-ADCP12 ADC pair conversion complete interrupts can be used to invoke Analog-to-Digital conversion completion routines for individual ADC input pairs. DS70000591F-page 322  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-4: ADPCFG: ADC PORT CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG<15:8>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG<7:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PCFG<15:0>: ADC Port Configuration Control bits(1) 1 = Port pin in Digital mode, port read input is enabled; Analog-to-Digital input multiplexer is connected to AVSS 0 = Port pin in Analog mode, port read input is disabled; Analog-to-Digital samples the pin voltage Note 1: Not all PCFGx bits are available on all devices. See Figure22-1, Figure22-2, Figure22-3 and Figure22-4 for the available analog inputs (PCFGx = ANx, where x = 0-15). REGISTER 22-5: ADPCFG2: ADC PORT CONFIGURATION REGISTER2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG<23:16>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 PCFG<23:16>: ADC Port Configuration Control bits(1) 1 = Port pin in Digital mode, port read input is enabled; Analog-to-Digital input multiplexer is connected to AVSS 0 = Port pin in Analog mode, port read input is disabled; Analog-to-Digital samples the pin voltage Note 1: Not all PCFGx bits are available on all devices. See Figure22-1, Figure22-2, Figure22-3 and Figure22-4 for the available analog inputs (PCFGx = ANx, where x can be 0 through 15).  2009-2014 Microchip Technology Inc. DS70000591F-page 323

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-6: ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN1: Interrupt Request Enable 1 bit 1 = Enables IRQ generation when requested conversion of Channels AN3 and AN2 is completed 0 = IRQ is not generated bit 14 PEND1: Pending Conversion Status 1 bit 1 = Conversion of Channels AN3 and AN2 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 13 SWTRG1: Software Trigger 1 bit 1 = Starts conversion of AN3 and AN2 (if selected by the TRGSRCx<4:0> bits)(1) This bit is automatically cleared by hardware when the PEND1 bit is set. 0 = Conversion has not started Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available. DS70000591F-page 324  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-6: ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0 (CONTINUED) bit 12-8 TRGSRC1<4:0>: Trigger 1 Source Selection bits Selects trigger source for conversion of Analog Channels AN3 and AN2. 11111 = Timer2 period match 11110 = PWM Generator 8 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = PWM Generator 9 secondary trigger is selected 10101 = PWM Generator 8 secondary trigger is selected 10100 = PWM Generator 7 secondary trigger is selected 10011 = PWM Generator 6 secondary trigger is selected 10010 = PWM Generator 5 secondary trigger is selected 10001 = PWM Generator 4 secondary trigger is selected 10000 = PWM Generator 3 secondary trigger is selected 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = PWM secondary Special Event Trigger is selected 01100 = Timer1 period match 01011 = PWM Generator 8 primary trigger is selected 01010 = PWM Generator 7 primary trigger is selected 01001 = PWM Generator 6 primary trigger is selected 01000 = PWM Generator 5 primary trigger is selected 00111 = PWM Generator 4 primary trigger selected 00110 = PWM Generator 3 primary trigger is selected 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled bit 7 IRQEN0: Interrupt Request Enable 0 bit 1 = Enables IRQ generation when requested conversion of Channels AN1 and AN0 is completed 0 = IRQ is not generated bit 6 PEND0: Pending Conversion Status 0 bit 1 = Conversion of Channels AN1 and AN0 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 5 SWTRG0: Software Trigger 0 bit 1 = Starts conversion of AN1 and AN0 (if selected by the TRGSRCx<4:0> bits)(1) This bit is automatically cleared by hardware when the PEND0 bit is set. 0 = Conversion has not started. Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available.  2009-2014 Microchip Technology Inc. DS70000591F-page 325

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-6: ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0 (CONTINUED) bit 4-0 TRGSRC0<4:0>: Trigger 0 Source Selection bits Selects trigger source for conversion of Analog Channels AN1 and AN0. 11111 = Timer2 period match 11110 = PWM Generator 8 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = PWM Generator 9 secondary trigger is selected 10101 = PWM Generator 8 secondary trigger is selected 10100 = PWM Generator 7 secondary trigger is selected 10011 = PWM Generator 6 secondary trigger is selected 10010 = PWM Generator 5 secondary trigger is selected 10001 = PWM Generator 4 secondary trigger is selected 10000 = PWM Generator 3 secondary trigger is selected 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = PWM secondary Special Event Trigger is selected 01100 = Timer1 period match 01011 = PWM Generator 8 primary trigger is selected 01010 = PWM Generator 7 primary trigger is selected 01001 = PWM Generator 6 primary trigger is selected 01000 = PWM Generator 5 primary trigger is selected 00111 = PWM Generator 4 primary trigger is selected 00110 = PWM Generator 3 primary trigger is selected 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available. DS70000591F-page 326  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-7: ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN3: Interrupt Request Enable 3 bit 1 = Enables IRQ generation when requested conversion of Channels AN7 and AN6 is completed 0 = IRQ is not generated bit 14 PEND3: Pending Conversion Status 3 bit 1 = Conversion of Channels AN7 and AN6 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 13 SWTRG3: Software Trigger 3 bit 1 = Starts conversion of AN7 and AN6 (if selected by the TRGSRCx<4:0> bits)(1) This bit is automatically cleared by hardware when the PEND3 bit is set. 0 = Conversion has not started Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available.  2009-2014 Microchip Technology Inc. DS70000591F-page 327

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-7: ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) bit 12-8 TRGSRC3<4:0>: Trigger 3 Source Selection bits Selects trigger source for conversion of analog channels AN7 and AN6. 11111 = Timer2 period match 11110 = PWM Generator 8 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = PWM Generator 9 secondary trigger is selected 10101 = PWM Generator 8 secondary trigger is selected 10100 = PWM Generator 7 secondary trigger is selected 10011 = PWM Generator 6 secondary trigger is selected 10010 = PWM Generator 5 secondary trigger is selected 10001 = PWM Generator 4 secondary trigger is selected 10000 = PWM Generator 3 secondary trigger is selected 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = PWM secondary Special Event Trigger is selected 01100 = Timer1 period match 01011 = PWM Generator 8 primary trigger is selected 01010 = PWM Generator 7 primary trigger is selected 01001 = PWM Generator 6 primary trigger is selected 01000 = PWM Generator 5 primary trigger is selected 00111 = PWM Generator 4 primary trigger is selected 00110 = PWM Generator 3 primary trigger is selected 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled bit 7 IRQEN2: Interrupt Request Enable 2 bit 1 = Enables IRQ generation when requested conversion of Channels AN5 and AN4 is completed 0 = IRQ is not generated bit 6 PEND2: Pending Conversion Status 2 bit 1 = Conversion of Channels AN5 and AN4 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 5 SWTRG2: Software Trigger 2 bit 1 = Starts conversion of AN5 and AN4 (if selected by the TRGSRCx<4:0> bits)(1) This bit is automatically cleared by hardware when the PEND2 bit is set. 0 = Conversion has not started Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available. DS70000591F-page 328  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-7: ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) bit 4-0 TRGSRC2<4:0>: Trigger 2 Source Selection bits Selects trigger source for conversion of Analog Channels AN5 and AN4. 11111 = Timer2 period match 11110 = PWM Generator 8 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = PWM Generator 9 secondary trigger is selected 10101 = PWM Generator 8 secondary trigger is selected 10100 = PWM Generator 7 secondary trigger is selected 10011 = PWM Generator 6 secondary trigger is selected 10010 = PWM Generator 5 secondary trigger is selected 10001 = PWM Generator 4 secondary trigger selected 10000 = PWM Generator 3 secondary trigger is selected 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = PWM secondary Special Event Trigger is selected 01100 = Timer1 period match 01011 = PWM Generator 8 primary trigger is selected 01010 = PWM Generator 7 primary trigger is selected 01001 = PWM Generator 6 primary trigger is selected 01000 = PWM Generator 5 primary trigger is selected 00111 = PWM Generator 4 primary trigger is selected 00110 = PWM Generator 3 primary trigger is selected 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available.  2009-2014 Microchip Technology Inc. DS70000591F-page 329

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-8: ADCPC2: ADC CONVERT PAIR CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN5 PEND5 SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN4 PEND4 SWTRG4 TRGSRC44 TRGSRC43 TRGSRC42 TRGSRC41 TRGSRC40 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN5: Interrupt Request Enable 5 bit 1 = Enables IRQ generation when requested conversion of Channels AN11 and AN10 is completed 0 = IRQ is not generated bit 14 PEND5: Pending Conversion Status 5 bit 1 = Conversion of Channels AN11 and AN10 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 13 SWTRG5: Software Trigger 5 bit 1 = Starts conversion of AN11 and AN10 (if selected by the TRGSRCx<4:0> bits)(1) This bit is automatically cleared by hardware when the PEND5 bit is set. 0 = Conversion has not started Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available. DS70000591F-page 330  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-8: ADCPC2: ADC CONVERT PAIR CONTROL REGISTER 2 (CONTINUED) bit 12-8 TRGSRC5<4:0>: Trigger 5 Source Selection bits Selects trigger source for conversion of Analog Channels AN11 and AN10. 11111 = Timer2 period match 11110 = PWM Generator 8 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = PWM Generator 9 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 01110 = PWM Generator 1 secondary trigger selected 01101 = PWM secondary Special Event Trigger selected 01100 = Timer1 period match 01011 = PWM Generator 8 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00100 = PWM Generator 1 primary trigger selected 00011 = PWM Special Event Trigger selected 00010 = Global software trigger selected 00001 = Individual software trigger selected 00000 = No conversion is enabled bit 7 IRQEN4: Interrupt Request Enable 4 bit 1 = Enables IRQ generation when requested conversion of Channels AN9 and AN8 is completed 0 = IRQ is not generated bit 6 PEND4: Pending Conversion Status 4 bit 1 = Conversion of Channels AN9 and AN8 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 5 SWTRG4: Software Trigger 4 bit 1 = Starts conversion of AN9 and AN8 (if selected by the TRGSRCx<4:0> bits)(1) This bit is automatically cleared by hardware when the PEND4 bit is set. 0 = Conversion has not started Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available.  2009-2014 Microchip Technology Inc. DS70000591F-page 331

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-8: ADCPC2: ADC CONVERT PAIR CONTROL REGISTER 2 (CONTINUED) bit 4-0 TRGSRC4<4:0>: Trigger 4 Source Selection bits Selects trigger source for conversion of Analog Channels AN9 and AN8. 11111 = Timer2 period match 11110 = PWM Generator 8 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = PWM Generator 9 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 01110 = PWM Generator 1 secondary trigger selected 01101 = PWM secondary Special Event Trigger selected 01100 = Timer1 period match 01011 = PWM Generator 8 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00100 = PWM Generator 1 primary trigger selected 00011 = PWM Special Event Trigger selected 00010 = Global software trigger selected 00001 = Individual software trigger selected 00000 = No conversion is enabled Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available. DS70000591F-page 332  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-9: ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN7 PEND7 SWTRG7 TRGSRC74 TRGSRC73 TRGSRC72 TRGSRC71 TRGSRC70 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN6 PEND6 SWTRG6 TRGSRC64 TRGSRC63 TRGSRC62 TRGSRC61 TRGSRC60 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN7: Interrupt Request Enable 7 bit 1 = Enables IRQ generation when requested conversion of Channels AN15 and AN14 is completed 0 = IRQ is not generated bit 14 PEND7: Pending Conversion Status 7 bit 1 = Conversion of Channels AN15 and AN14 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 13 SWTRG7: Software Trigger 7 bit 1 = Starts conversion of AN15 and AN14 (if selected by the TRGSRCx<4:0> bits)(1) This bit is automatically cleared by hardware when the PEND7 bit is set. 0 = Conversion has not started Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available.  2009-2014 Microchip Technology Inc. DS70000591F-page 333

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-9: ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3 (CONTINUED) bit 12-8 TRGSRC7<4:0>: Trigger 7 Source Selection bits Selects trigger source for conversion of Analog Channels AN15 and 14. 11111 = Timer2 period match 11110 = PWM Generator 8 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = PWM Generator 9 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 01110 = PWM Generator 1 secondary trigger selected 01101 = PWM secondary Special Event Trigger selected 01100 = Timer1 period match 01011 = PWM Generator 8 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00100 = PWM Generator 1 primary trigger selected 00011 = PWM Special Event Trigger selected 00010 = Global software trigger selected 00001 = Individual software trigger selected 00000 = No conversion is enabled bit 7 IRQEN6: Interrupt Request Enable 6 bit 1 = Enables IRQ generation when requested conversion of Channels AN13 and AN12 is completed 0 = IRQ is not generated bit 6 PEND6: Pending Conversion Status 6 bit 1 = Conversion of Channels AN13 and AN12 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 5 SWTRG6: Software Trigger 6 bit 1 = Starts conversion of AN13 and AN12 (if selected by the TRGSRCx<4:0> bits)(1) This bit is automatically cleared by hardware when the PEND6 bit is set. 0 = Conversion has not started Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available. DS70000591F-page 334  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-9: ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3 (CONTINUED) bit 4-0 TRGSRC6<4:0>: Trigger 6 Source Selection bits Selects trigger source for conversion of Analog Channels AN13 and AN12. 11111 = Timer2 period match 11110 = PWM Generator 8 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = PWM Generator 9 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 01110 = PWM Generator 1 secondary trigger selected 01101 = PWM secondary Special Event Trigger selected 01100 = Timer1 period match 01011 = PWM Generator 8 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00100 = PWM Generator 1 primary trigger selected 00011 = PWM Special Event Trigger selected 00010 = Global software trigger selected 00001 = Individual software trigger selected 00000 = No conversion is enabled Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available.  2009-2014 Microchip Technology Inc. DS70000591F-page 335

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-10: ADCPC4: ADC CONVERT PAIR CONTROL REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN9 PEND9 SWTRG9 TRGSRC94 TRGSRC93 TRGSRC92 TRGSRC91 TRGSRC90 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN8 PEND8 SWTRG8 TRGSRC84 TRGSRC83 TRGSRC82 TRGSRC81 TRGSRC80 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN9: Interrupt Request Enable 9 bit 1 = Enable IRQ generation when requested conversion of channels AN19 and AN18 is completed 0 = IRQ is not generated bit 14 PEND9: Pending Conversion Status 9 bit 1 = Conversion of channels AN19 and AN18 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 13 SWTRG9: Software Trigger 9 bit 1 = Starts conversion of AN19 and AN18 (if selected by the TRGSRCx<4:0> bits)(1) This bit is automatically cleared by hardware when the PEND9 bit is set. 0 = Conversion is not started Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available. DS70000591F-page 336  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-10: ADCPC4: ADC CONVERT PAIR CONTROL REGISTER 4 (CONTINUED) bit 12-8 TRGSRC9<4:0>: Trigger 9 Source Selection bits Selects trigger source for conversion of analog channels AN19 and AN18. 11111 = Timer2 period match 11110 = PWM Generator 8 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = PWM Generator 9 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 01110 = PWM Generator 1 secondary trigger selected 01101 = PWM secondary Special Event Trigger selected 01100 = Timer1 period match 01011 = PWM Generator 8 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00100 = PWM Generator 1 primary trigger selected 00011 = PWM Special Event Trigger selected 00010 = Global software trigger selected 00001 = Individual software trigger selected 00000 = No conversion is enabled bit 7 IRQEN8: Interrupt Request Enable 8 bit 1 = Enables IRQ generation when requested conversion of Channels AN17 and AN16 is completed 0 = IRQ is not generated bit 6 PEND8: Pending Conversion Status 8 bit 1 = Conversion of Channels AN17 and AN16 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 5 SWTRG8: Software Trigger 8 bit 1 = Starts conversion of AN17 and AN16 (if selected by TRGSRC bits)(1) This bit is automatically cleared by hardware when the PEND8 bit is set. 0 = Conversion has not started Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available.  2009-2014 Microchip Technology Inc. DS70000591F-page 337

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-10: ADCPC4: ADC CONVERT PAIR CONTROL REGISTER 4 (CONTINUED) bit 4-0 TRGSRC8<4:0>: Trigger 8 Source Selection bits Selects trigger source for conversion of Analog Channels AN17 and AN16. 11111 = Timer2 period match 11110 = PWM Generator 8 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = PWM Generator 9 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 01110 = PWM Generator 1 secondary trigger selected 01101 = PWM secondary Special Event Trigger selected 01100 = Timer1 period match 01011 = PWM Generator 8 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00100 = PWM Generator 1 primary trigger selected 00011 = PWM Special Event Trigger selected 00010 = Global software trigger selected 00001 = Individual software trigger selected 00000 = No conversion is enabled Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available. DS70000591F-page 338  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-11: ADCPC5: ADC CONVERT PAIR CONTROL REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN11 PEND11 SWTRG11 TRGSRC114 TRGSRC113 TRGSRC112 TRGSRC111 TRGSRC110 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN10 PEND10 SWTRG10 TRGSRC104 TRGSRC103 TRGSRC102 TRGSRC101 TRGSRC100 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN11: Interrupt Request Enable 11 bit 1 = Enables IRQ generation when requested conversion of Channels AN23 and AN22 is completed 0 = IRQ is not generated bit 14 PEND11: Pending Conversion Status 11 bit 1 = Conversion of Channels AN23 and AN22 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 13 SWTRG11: Software Trigger 11 bit 1 = Starts conversion of AN23 and AN22 (if selected by the TRGSRCx<4:0> bits)(1) This bit is automatically cleared by hardware when the PEND11 bit is set. 0 = Conversion is not started Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available.  2009-2014 Microchip Technology Inc. DS70000591F-page 339

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-11: ADCPC5: ADC CONVERT PAIR CONTROL REGISTER 5 (CONTINUED) bit 12-8 TRGSRC11<4:0>: Trigger 11 Source Selection bits Selects trigger source for conversion of analog channels AN23 and AN22. 11111 = Timer2 period match 11110 = PWM Generator 8 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = PWM Generator 9 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 01110 = PWM Generator 1 secondary trigger selected 01101 = PWM secondary Special Event Trigger selected 01100 = Timer1 period match 01011 = PWM Generator 8 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00100 = PWM Generator 1 primary trigger selected 00011 = PWM Special Event Trigger selected 00010 = Global software trigger selected 00001 = Individual software trigger selected 00000 = No conversion is enabled bit 7 IRQEN10: Interrupt Request Enable 10 bit 1 = Enables IRQ generation when requested conversion of Channels AN21 and AN20 is completed 0 = IRQ is not generated bit 6 PEND10: Pending Conversion Status 10 bit 1 = Conversion of Channels AN21 and AN20 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 5 SWTRG10: Software Trigger 10 bit 1 = Starts conversion of AN21 and AN20 (if selected by the TRGSRCx<4:0> bits)(1) This bit is automatically cleared by hardware when the PEND10 bit is set. 0 = Conversion has not started Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available. DS70000591F-page 340  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-11: ADCPC5: ADC CONVERT PAIR CONTROL REGISTER 5 (CONTINUED) bit 4-0 TRGSRC10<4:0>: Trigger 10 Source Selection bits Selects trigger source for conversion of analog channels AN21 and AN20. 11111 = Timer2 period match 11110 = PWM Generator 8 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = PWM Generator 9 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 01110 = PWM Generator 1 secondary trigger selected 01101 = PWM secondary Special Event Trigger selected 01100 = Timer1 period match 01011 = PWM Generator 8 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00100 = PWM Generator 1 primary trigger selected 00011 = PWM Special Event Trigger selected 00010 = Global software trigger selected 00001 = Individual software trigger selected 00000 = No conversion enabled Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available.  2009-2014 Microchip Technology Inc. DS70000591F-page 341

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-12: ADCPC6: ADC CONVERT PAIR CONTROL REGISTER 6(2) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN12 PEND12 SWTRG12 TRGSRC124 TRGSRC123 TRGSRC122 TRGSRC121 TRGSRC120 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IRQEN12: Interrupt Request Enable 12 bit 1 = Enables IRQ generation when requested conversion of Channels AN25 and AN24 is completed 0 = IRQ is not generated bit 6 PEND12: Pending Conversion Status 12 bit 1 = Conversion of Channels AN25 and AN24 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 5 SWTRG12: Software Trigger 12 bit 1 = Starts conversion of AN25 (INTREF) and AN24 (EXTREF) if selected by the TRGSRCx<4:0> bits(1) This bit is automatically cleared by hardware when the PEND12 bit is set. 0 = Conversion has not started Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available. 2: This register is not available on dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices. DS70000591F-page 342  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 22-12: ADCPC6: ADC CONVERT PAIR CONTROL REGISTER 6(2) (CONTINUED) bit 4-0 TRGSRC12<4:0>: Trigger 12 Source Selection bits Selects trigger source for conversion of analog channels AN25 and AN24. 11111 = Timer2 period match 11110 = PWM Generator 8 current-limit ADC trigger 11101 = PWM Generator 7 current-limit ADC trigger 11100 = PWM Generator 6 current-limit ADC trigger 11011 = PWM Generator 5 current-limit ADC trigger 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = PWM Generator 9 secondary trigger selected 10101 = PWM Generator 8 secondary trigger selected 10100 = PWM Generator 7 secondary trigger selected 10011 = PWM Generator 6 secondary trigger selected 10010 = PWM Generator 5 secondary trigger selected 10001 = PWM Generator 4 secondary trigger selected 10000 = PWM Generator 3 secondary trigger selected 01111 = PWM Generator 2 secondary trigger selected 01110 = PWM Generator 1 secondary trigger selected 01101 = PWM secondary Special Event Trigger selected 01100 = Timer1 period match 01011 = PWM Generator 8 primary trigger selected 01010 = PWM Generator 7 primary trigger selected 01001 = PWM Generator 6 primary trigger selected 01000 = PWM Generator 5 primary trigger selected 00111 = PWM Generator 4 primary trigger selected 00110 = PWM Generator 3 primary trigger selected 00101 = PWM Generator 2 primary trigger selected 00100 = PWM Generator 1 primary trigger selected 00011 = PWM Special Event Trigger selected 00010 = Global software trigger selected 00001 = Individual software trigger selected 00000 = No conversion is enabled Note 1: The trigger source must be set as an individual software trigger prior to setting this bit to ‘1’. If other conversions are in progress, the conversion is performed when the conversion resources are available. 2: This register is not available on dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices.  2009-2014 Microchip Technology Inc. DS70000591F-page 343

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70000591F-page 344  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 23.0 HIGH-SPEED ANALOG • 10-Bit DAC for each Analog Comparator COMPARATOR • Programmable Output Polarity • Interrupt Generation Capability Note 1: This data sheet summarizes the features of • DACOUT Pin to provide DAC Output the dsPIC33FJ32GS406/606/608/610 • DAC has Three Ranges of Operation: and dsPIC33FJ64GS406/606/608/610 - AVDD/2 families of devices. It is not intended to be - Internal Reference (INTREF) a comprehensive reference source. To - External Reference (EXTREF) complement the information in this data • ADC Sample-and-Convert Trigger Capability sheet, refer to “High-Speed Analog • Disable Capability reduces Power Consumption Comparator” (DS70296) in the • Functional Support for PWM module: “dsPIC33/PIC24 Family Reference Man- - PWM duty cycle control ual”, which is available from the Microchip web site (www.microchip.com). The infor- - PWM period control mation in this data sheet supersedes the - PWM Fault detect information in the FRM. 23.2 Module Description 2: Some registers and associated bits described in this section may not be Figure23-1 shows a functional block diagram of one available on all devices. Refer to analog comparator from the SMPS comparator Section4.0 “Memory Organization” in module. The analog comparator provides high-speed this data sheet for device-specific register operation with a typical delay of 20 ns. The comparator and bit information. has a typical offset voltage of ±5 mV. The negative input of the comparator is always connected to the The dsPIC33F Switch Mode Power Supply (SMPS) DAC circuit. The positive input of the comparator is comparator module monitors current and/or voltage connected to an analog multiplexer that selects the transients that may be too fast for the CPU and ADC to desired source pin. capture. The analog comparator input pins are typically shared 23.1 Features Overview with pins used by the Analog-to-Digital Converter (ADC) module. Both the comparator and the ADC can The SMPS comparator module offers the following use the same pins at the same time. This capability major features: enables a user to measure an input voltage with the • 16 Selectable Comparator Inputs ADC and detect voltage transients with the • Up to Four Analog Comparators comparator. FIGURE 23-1: HIGH-SPEED ANALOG COMPARATOR x MODULE BLOCK DIAGRAM INSEL<1:0> CMPxA* Trigger to PWM Status CMPxB* M U CMPxC* X CMPxD* CMPx* 0 Pulse Glitch Filter Generator 1 RANGE CMPPOL AVDD/2 M INTREF(1) Interrupt U DAC DACOUT Request X AVSS 10 CMREF DACOE EXTREF(1) * x = 1, 2, 3 and 4 Note 1: Refer to Parameters DA01 and DA08 in the DAC Module Specifications (Table27-43) for details.  2009-2014 Microchip Technology Inc. DS70000591F-page 345

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 23.3 Module Applications 23.5 Interaction with I/O Buffers This module provides a means for the SMPS dsPIC® If the comparator module is enabled and a pin has DSC devices to monitor voltage and currents in a been selected as the source for the comparator, then power conversion application. The ability to detect the chosen I/O pad must disable the digital input buffer transient conditions and stimulate the dsPIC DSC associated with the pad to prevent excessive currents processor and/or peripherals, without requiring the in the digital buffer due to analog input voltages. processor and ADC to constantly monitor voltages or 23.6 Digital Logic currents, frees the dsPIC DSC to perform other tasks. The comparator module has a high-speed comparator The CMPCONx register (see Register23-1) provides and an associated 10-bit DAC that provides a pro- the control logic that configures the comparator grammable reference voltage to the inverting input of module. The digital logic provides a glitch filter for the the comparator. The polarity of the comparator output comparator output to mask transient signals in less is user-programmable. The output of the module can than two instruction cycles. In Sleep or Idle mode, the be used in the following modes: glitch filter is bypassed to enable an asynchronous path from the comparator to the interrupt controller. • Generate an Interrupt This asynchronous path can be used to wake-up the • Trigger an ADC Sample-and-Convert Process processor from Sleep or Idle mode. • Truncate the PWM Signal (current limit) The comparator can be disabled while in Idle mode if • Truncate the PWM Period (current minimum) the CMPSIDL bit is set. If a device has multiple • Disable the PWM Outputs (Fault latch) comparators, if any CMPSIDL bit is set, then the entire The output of the comparator module may be used in group of comparators will be disabled while in Idle multiple modes at the same time, such as: 1) generate mode. This behavior reduces complexity in the design an interrupt, 2) have the ADC take a sample and con- of the clock control logic for this module. vert it, and 3) truncate the PWM output in response to The digital logic also provides a one TCY width pulse a voltage being detected beyond its expected value. generator for triggering the ADC and generating The comparator module can also be used to wake-up interrupt requests. the system from Sleep or Idle mode when the analog The CMPDACx (see Register23-2) register provides input voltage exceeds the programmed threshold the digital input value to the reference DAC. voltage. If the module is disabled, the DAC and comparator are 23.4 DAC disabled to reduce power consumption. 23.7 Comparator Input Range The range of the DAC is controlled via an analog multiplexer that selects either AVDD/2, an internal ref- The comparator has a limitation for the input erence source, INTREF, or an external reference Common-Mode Range (CMR) of (AVDD – 1.5V), source, EXTREF. The full range of the DAC (AVDD/2) typical. This means that both inputs should not exceed will typically be used when the chosen input source pin this range. As long as one of the inputs is within the is shared with the ADC. The reduced range option Common-Mode Range, the comparator output will be (INTREF) will likely be used when monitoring current correct. However, any input exceeding the CMR levels using a current sense resistor. Usually, the limitation will cause the comparator input to be measured voltages in such applications are small saturated. (<1.25V); therefore the option of using a reduced reference range for the comparator extends the If both inputs exceed the CMR, the comparator output available DAC resolution in these applications. The will be indeterminate. use of an external reference enables the user to 23.8 DAC Output Range connect to a reference that better suits their application. The DAC has a limitation for the maximum reference DACOUT, shown in Figure23-1, can only be voltage input of (AVDD – 1.6) volts. An external associated with a single comparator at a given time. reference voltage input should not exceed this value or the reference DAC output will become indeterminate. Note: It should be ensured in software that multiple DACOE bits are not set. The 23.9 Comparator Registers output on the DACOUT pin will be indeter- The comparator module is controlled by the following minate if multiple comparators enable the registers: DAC output. • CMPCONx: Comparator Control x Register • CMPDACx: Comparator DAC Control x Register DS70000591F-page 346  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R E GISTER 23-1: CMPCONx: COMPARATOR CONTROL x REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 CMPON — CMPSIDL — — — — DACOE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMPON: Comparator Operating Mode bit 1 = Comparator module is enabled 0 = Comparator module is disabled (reduces power consumption) bit 14 Unimplemented: Read as ‘0’ bit 13 CMPSIDL: Comparator Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode. 0 = Continues module operation in Idle mode If a device has multiple comparators, any CMPSIDL bit set to ‘1’ disables ALL comparators while in Idle mode. bit 12-9 Unimplemented: Read as ‘0’ bit 8 DACOE: DAC Output Enable 1 = DAC analog voltage is output to the DACOUT pin(1) 0 = DAC analog voltage is not connected to the DACOUT pin bit 7-6 INSEL<1:0>: Input Source Select for Comparator bits 11 = Selects CMPxD input pin 10 = Selects CMPxC input pin 01 = Selects CMPxB input pin 00 = Selects CMPxA input pin bit 5 EXTREF: Enable External Reference bit 1 = External source provides reference to DAC (maximum DAC voltage determined by external voltage source) 0 = Internal reference sources provide reference to DAC (maximum DAC voltage determined by RANGE bit setting) bit 4 Unimplemented: Read as ‘0’ bit 3 CMPSTAT: Current State of Comparator Output Including CMPPOL Selection bit bit 2 Unimplemented: Read as ‘0’ bit 1 CMPPOL: Comparator Output Polarity Control bit 1 = Output is inverted 0 = Output is non-inverted bit 0 RANGE: Selects DAC Output Voltage Range bit 1 = High Range: Max DAC Value = AVDD/2, 1.65V at 3.3V AVDD 0 = Low Range: Max DAC Value = INTREF Note 1: DACOUT can be associated only with a single comparator at any given time. The software must ensure that multiple comparators do not enable the DAC output by setting their respective DACOE bit.  2009-2014 Microchip Technology Inc. DS70000591F-page 347

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 R EGISTER 23-2: CMPDACx: COMPARATOR DAC CONTROL x REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — CMREF<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMREF<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 CMREF<9:0>: Comparator Reference Voltage Select bits 1111111111 = (CMREF * INTREF/1024) or (CMREF * (AVDD/2)/1024) volts depending on the RANGE bit or (CMREF * EXTREF/1024) if EXTREF is set • • • 0000000000 = 0.0 volts DS70000591F-page 348  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 24.0 SPECIAL FEATURES 24.1 Configuration Bits Note 1: This data sheet summarizes the features The dsPIC33FJ32GS406/606/608/610 and of the dsPIC33FJ32GS406/606/608/610 dsPIC33FJ64GS406/606/608/610 devices provide and dsPIC33FJ64GS406/606/608/610 non-volatile memory implementations for device devices. It is not intended to be a compre- Configuration bits. Refer to “Device Configuration” hensive reference source. To complement (DS70194) in the “dsPIC33/PIC24 Family Reference the information in this data sheet, refer to Manual” for more information on this implementation. the “dsPIC33/PIC24 Family Reference The Configuration bits can be programmed (read Manual”. Please see the Microchip web as‘0’), or left unprogrammed (read as ‘1’), to select site (www.microchip.com) for the latest various device configurations. These bits are mapped “dsPIC33/PIC24 Family Reference Man- starting at program memory location 0xF80000. ual” sections. The information in this The individual Configuration bit descriptions for the data sheet supersedes the information Configuration registers are shown in Table24-2. in the FRM. Note that address, 0xF80000, is beyond the user pro- 2: Some registers and associated bits gram memory space. It belongs to the configuration described in this section may not be memory space (0x800000-0xFFFFFF), which can only available on all devices. Refer to be accessed using Table Reads and Table Writes. Section4.0 “Memory Organization” in this data sheet for device-specific register To prevent inadvertent configuration changes during and bit information. code execution, all programmable Configuration bits are write-once. After a bit is initially programmed during The dsPIC33FJ32GS406/606/608/610 and a power cycle, it cannot be written again. Changing a dsPIC33FJ64GS406/606/608/610 devices include device configuration requires that power to the device several features intended to maximize application be cycled. flexibility and reliability, and minimize cost through The device Configuration register map is shown in elimination of external components. These are: Table24-1. • Flexible Configuration • Watchdog Timer (WDT) • Code Protection and CodeGuard™ Security • JTAG Boundary Scan Interface • In-Circuit Serial Programming™ (ICSP™) • In-Circuit Emulation • Brown-out Reset (BOR) TABLE 24-1: DEVICE CONFIGURATION REGISTER MAP Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0xF80000 FBS — — — — BSS<2:0> BWRP 0xF80002 RESERVED — — — — — — — — 0xF80004 FGS — — — — — GSS<1:0> GWRP 0xF80006 FOSCSEL IESO — — — FNOSC<2:0> 0xF80008 FOSC FCKSM<1:0> — — — OSCIOFNC POSCMD<1:0> 0xF8000A FWDT FWDTEN WINDIS — WDTPRE WDTPOST<3:0> 0xF8000C FPOR — ALTQIO ALTSS1 — — FPWRT<2:0> 0xF8000E FICD Reserved(1) Reserved(1) JTAGEN — — — ICS<1:0> 0xF80010 FCMP — — CMPPOL1(2) HYST1<1:0>(2) CMPPOL0(2) HYST0<1:0>(2) Legend: — = unimplemented bit, read as ‘0’. Note 1: These bits are reserved for use by development tools and must be programmed as ‘1’. 2: These bits are reserved on dsPIC33FJXXXGS406 devices and always read as ‘1’.  2009-2014 Microchip Technology Inc. DS70000591F-page 349

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 24-2: dsPIC33F CONFIGURATION BITS DESCRIPTION Bit Field Register RTSP Effect Description BWRP FBS Immediate Boot Segment Program Flash Write Protection bit 1 = Boot segment can be written 0 = Boot segment is write-protected BSS<2:0> FBS Immediate Boot Segment Program Flash Code Protection Size bits X11 = No boot program Flash segment Boot Space is 256 Instruction Words (except interrupt vectors): 110 = Standard security; boot program Flash segment ends at 0x0003FE 010 = High security; boot program Flash segment ends at 0x0003FE Boot Space is 768 Instruction Words (except interrupt vectors): 101 = Standard security; boot program Flash segment ends at 0x0007FE 001 = High security; boot program Flash segment ends at 0x0007FE Boot Space is 1792 Instruction Words (except interrupt vectors): 100 = Standard security; boot program Flash segment ends at 0x000FFE 000 = High security; boot program Flash segment ends at 0x000FFE GSS<1:0> FGS Immediate General Segment Code-Protect bits 11 = User program memory is not code-protected 10 = Standard security 0x = High security GWRP FGS Immediate General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected IESO FOSCSEL Immediate Two-Speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user selected oscillator source when ready 0 = Start-up device with user selected oscillator source FNOSC<2:0> FOSCSEL If clock switch Initial Oscillator Source Selection bits is enabled, 111 = Internal Fast RC (FRC) Oscillator with Postscaler RTSP effect 110 = Internal Fast RC (FRC) Oscillator with Divide-by-16 is on any 101 = LPRC Oscillator device Reset; 100 = Secondary (LP) Oscillator otherwise, 011 = Primary (XT, HS, EC) Oscillator with PLL immediate 010 = Primary (XT, HS, EC) Oscillator 001 = Internal Fast RC (FRC) Oscillator with PLL 000 = FRC Oscillator FCKSM<1:0> FOSC Immediate Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSCIOFNC FOSC Immediate OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is the clock output 0 = OSC2 is the general purpose digital I/O pin POSCMD<1:0> FOSC Immediate Primary Oscillator Mode Select bits 11 = Primary Oscillator is disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode DS70000591F-page 350  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 24-2: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register RTSP Effect Description FWDTEN FWDT Immediate Watchdog Timer Enable bit 1 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the SWDTEN bit in the RCON register will have no effect) 0 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) WINDIS FWDT Immediate Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode WDTPRE FWDT Immediate Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 WDTPOST<3:0> FWDT Immediate Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 FPWRT<2:0> FPOR Immediate Power-on Reset Timer Value Select bits 111 = PWRT = 128 ms 110 = PWRT = 64 ms 101 = PWRT = 32 ms 100 = PWRT = 16 ms 011 = PWRT = 8 ms 010 = PWRT = 4 ms 001 = PWRT = 2 ms 000 = PWRT = Disabled JTAGEN FICD Immediate JTAG Enable bit 1 = JTAG is enabled 0 = JTAG is disabled ICS<1:0> FICD Immediate ICD Communication Channel Select Enable bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use ALTQIO FPOR Immediate Enable Alternate QEI1 Pin bit 1 = QEA1, QEB1 and INDX1 are selected as inputs to QEI1 0 = AQEA1, AQEB1 and AINDX1 are selected as inputs to QEI1 ALTSS1 FPOR Immediate Enable Alternate SS1 pin bit 1 = ASS1 is selected as the I/O pin for SPI1 0 = SS1 is selected as the I/O pin for SPI1 CMPPOL0 FCMP Immediate Comparator Hysteresis Polarity bit (for even numbered comparators) 1 = Hysteresis is applied to falling edge 0 = Hysteresis is applied to rising edge HYST0<1:0> FCMP Immediate Comparator Hysteresis Select bits 11 = 45 mV hysteresis 10 = 30 mV hysteresis 01 = 15 mV hysteresis 00 = No hysteresis  2009-2014 Microchip Technology Inc. DS70000591F-page 351

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 24-2: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register RTSP Effect Description CMPPOL1 FCMP Immediate Comparator Hysteresis Polarity bit (for odd numbered comparators) 1 = Hysteresis is applied to falling edge 0 = Hysteresis is applied to rising edge HYST1<1:0> FCMP Immediate Comparator Hysteresis Select bits 11 = 45 mV hysteresis 10 = 30 mV hysteresis 01 = 15 mV hysteresis 00 = No hysteresis DS70000591F-page 352  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 24.2 On-Chip Voltage Regulator 24.3 Brown-out Reset (BOR) The dsPIC33FJ32GS406/606/608/610 and The Brown-out Reset (BOR) module is based on an dsPIC33FJ64GS406/606/608/610 devices power internal voltage reference circuit. The main purpose of their core digital logic at a nominal2.5V. This can create the BOR module is to generate a device Reset when a a conflict for designs that are required to operate at a brown-out condition occurs. Brown-out conditions are higher typical voltage, such as 3.3V. To simplify system generally caused by glitches on the AC mains (for design, all devices in the dsPIC33FJ32GS406/606/608/ example, missing portions of the AC cycle waveform 610 and dsPIC33FJ64GS406/606/608/610 families due to bad power transmission lines, or voltage sags incorporate an on-chip regulator that allows the device to due to excessive current draw when a large inductive run its core logic from VDD. load is turned on). The regulator provides power to the core from the other A BOR generates a Reset pulse, which resets the VDD pins. When the regulator is enabled, a low-ESR device. The BOR selects the clock source based on the (less than 5 ohms) capacitor (such as tantalum or device Configuration bit values (FNOSC<2:0> and ceramic) must be connected to the VCAP pin POSCMD<1:0>). (Figure24-1). This helps to maintain the stability of the If an oscillator mode is selected, the BOR activates the regulator. The recommended value for the filter Oscillator Start-up Timer (OST). The system clock is capacitor is provided in Table27-13, located in held until OST expires. If the PLL is used, the clock is Section27.1 “DC Characteristics”. held until the LOCK bit (OSCCON<5>) is ‘1’. Note: It is important for the low-ESR capacitor to Concurrently, the Power-up Timer (PWRT) Time-out be placed as close as possible to the VCAP (TPWRT) is applied before the internal Reset is pin. released. If TPWRT = 0 and a crystal oscillator is being used, then a nominal delay of TFSCM = 100 is applied. On a POR, it takes approximately 20s for the on-chip The total delay in this case is TFSCM. voltage regulator to generate an output voltage. During this time, designated as TSTARTUP, code execution is The BOR status bit (RCON<1>) is set to indicate that a disabled. TSTARTUP is applied every time the device BOR has occurred. The BOR circuit continues to resumes operation after any power-down. operate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold FIGURE 24-1: CONNECTIONS FOR THE voltage. ON-CHIP VOLTAGE REGULATOR(1,2,3) 24.4 Watchdog Timer (WDT) For dsPIC33FJ32GS406/606/608/610 and 3.3V dsPIC33FJ64GS406/606/608/610 devices, the WDT dsPIC33F is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. VDD 24.4.1 PRESCALER/POSTSCALER VCAP The nominal WDT clock source from LPRC is CEFC VSS 32.767kHz. This feeds a prescaler that can be config- ured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Config- uration bit. With a 32.767kHz input, the prescaler yields Note 1: These are typical operating voltages. Refer to Table27-13 located in Section27.1 “DC a nominal WDT Time-out (TWDT) period of 1 ms in 5-bit mode or 4 ms in 7-bit mode. Characteristics” for the full operating ranges of VDD. A variable postscaler divides down the WDT prescaler 2: It is important for the low-ESR capacitor to output and allows for a wide range of time-out periods. be placed as close as possible to the VCAP The postscaler is controlled by the WDTPOST<3:0> pin. Configuration bits (FWDT<3:0>), which allow the 3: Typical VCAP pin voltage = 2.5V when selection of 16 settings, from 1:1 to 1:32,768. Using the VDDVDDMIN. prescaler and postscaler, time-out periods, ranging from 1ms to 131 seconds, can be achieved.  2009-2014 Microchip Technology Inc. DS70000591F-page 353

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 The WDT, prescaler and postscaler are reset: 24.4.3 ENABLING WDT • On any device Reset The WDT is enabled or disabled by the FWDTEN • On the completion of a clock switch, whether Configuration bit in the FWDT Configuration register. invoked by software (i.e., setting the OSWEN bit When the FWDTEN Configuration bit is set, the WDT is after changing the NOSCx bits) or by hardware always enabled. (i.e., Fail-Safe Clock Monitor) The WDT can be optionally controlled in software when • When a PWRSAV instruction is executed the FWDTEN Configuration bit has been programmed (i.e., Sleep or Idle mode is entered) to ‘0’. The WDT is enabled in software by setting the • When the device exits Sleep or Idle mode to SWDTEN control bit (RCON<5>). The SWDTEN resume normal operation control bit is cleared on any device Reset. The software • By a CLRWDT instruction during normal execution WDT option allows the user application to enable the WDT for critical code segments and disable the WDT Note: The CLRWDT and PWRSAV instructions during non-critical segments for maximum power clear the prescaler and postscaler counts savings. when executed. Note: If the WINDIS bit (FWDT<6>) is cleared, 24.4.2 SLEEP AND IDLE MODES the CLRWDT instruction should be executed by the application software only during the If the WDT is enabled, it will continue to run during last 1/4 of the WDT period. This CLRWDT Sleep or Idle modes. When the WDT time-out occurs, window can be determined by using a timer. the WDT will wake the device and code execution will If a CLRWDT instruction is executed before continue from where the PWRSAV instruction was this window, a WDT Reset occurs. executed. The corresponding SLEEP or IDLE bits (RCON<3:2>) will need to be cleared in software after The WDT flag bit, WDTO (RCON<4>), is not automatically the device wakes up. cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. FIGURE 24-2: WDT BLOCK DIAGRAM All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle WDTPRE WDTPOST<3:0> SWDTEN WDT FWDTEN Wake-up RS RS 1 Prescaler Postscaler LPRC Clock (Divide-by-N1) (Divide-by-N2) WDT 0 Reset WINDIS WDT Window Select CLRWDT Instruction DS70000591F-page 354  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 24.5 JTAG Interface 24.7 In-Circuit Debugger The dsPIC33FJ32GS406/606/608/610 and When MPLAB® ICD 3 is selected as a debugger, the in- dsPIC33FJ64GS406/606/608/610 devices implement circuit debugging functionality is enabled. This function a JTAG interface, which supports boundary scan allows simple debugging functions when used with device testing. Detailed information on this interface MPLAB X IDE. Debugging functionality is controlled will be provided in future revisions of the document. through the EMUCx (Emulation/Debug Clock) and EMUDx (Emulation/Debug Data) pin functions. 24.6 In-Circuit Serial Programming Any of the three pairs of debugging clock/data pins can be used: The dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 family Digital • PGEC1 and PGED1 Signal Controllers (DSCs) can be serially programmed • PGEC2 and PGED2 while in the end application circuit. This is done with • PGEC3 and PGED3 two lines for clock and data and three other lines for To use the in-circuit debugger function of the device, power, ground and the programming sequence. Serial the design must implement ICSP connections to programming allows customers to manufacture boards with unprogrammed devices and then program the MCLR, VDD, VSS, PGECx, PGEDx and the EMUDx/ EMUCx pin pair. In addition, when the feature is Digital Signal Controller just before shipping the enabled, some of the resources are not available for product. Serial programming also allows the most general use. These resources include the first 80 bytes recent firmware or a custom firmware to be of data RAM and two I/O pins. programmed. Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for details about In-Circuit Serial Programming™ (ICSP™). Any of the three pairs of programming clock/data pins can be used: • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3  2009-2014 Microchip Technology Inc. DS70000591F-page 355

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 24.8 Code Protection and The code protection features are controlled by the CodeGuard™ Security Configuration registers: FBS and FGS. Secure segment and RAM protection is not imple- The dsPIC33FJ32GS406/606/608/610 and mented in dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices offer the dsPIC33FJ64GS406/606/608/610 devices. intermediate implementation of CodeGuard™ Security. CodeGuard Security enables multiple parties to securely Note: Refer to “CodeGuard™ Security” share resources (memory, interrupts and peripherals) on (DS70199) in the “dsPIC33/PIC24 Family a single chip. This feature helps protect individual Reference Manual” for further information Intellectual Property in collaborative system designs. on usage, configuration and operation of CodeGuard Security. When coupled with software encryption libraries, CodeGuard Security can be used to securely update Flash even when multiple IPs reside on a single chip. TABLE 24-3: CODE FLASH SECURITY SEGMENT SIZES FOR 64-KBYTE DEVICES BSS<2:0> = x11, 0K BSS<2:0> = x10, 1K BSS<2:0> = x01, 4K BSS<2:0> = x00, 8K 000000h 000000h 000000h 000000h VS = 256 IW VS = 256 IW VS = 256 IW VS = 256 IW 0001FEh 0001FEh 0001FEh 0001FEh 000200h BS = 768 IW 000200h BS = 3840 IW 000200h BS = 7936 IW 000200h 0007FEh 000800h 001FFEh 002000h 003FFEh 004000h GS = 21760 IW GS = 20992 IW GS = 17920 IW GS = 13824 IW 00ABFEh 00ABFEh 00ABFEh 00ABFEh TABLE 24-4: CODE FLASH SECURITY SEGMENT SIZES FOR 32-KBYTE DEVICES BSS<2:0> = x11, 0K BSS<2:0> = x10, 1K BSS<2:0> = x01, 4K BSS<2:0> = x00, 8K 000000h 000000h 000000h 000000h VS = 256 IW 0001FEh VS = 256 IW 0001FEh VS = 256 IW 0001FEh VS = 256 IW 0001FEh 000200h BS = 768 IW 000200h BS = 3840 IW 000200h BS = 7936 IW 000200h 0007FEh 000800h 001FFEh 002000h 003FFEh 004000h GS = 11008 IW GS = 10240 IW GS = 7168 IW GS = 3072 IW 0057FEh 0057FEh 0057FEh 0057FEh 00ABFEh 00ABFEh 00ABFEh 00ABFEh DS70000591F-page 356  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 25.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/shift instructions) have two operands: Note: This data sheet summarizes the features • The W register (with or without an address of the dsPIC33FJ32GS406/606/608/610 modifier) or file register (specified by the value of and dsPIC33FJ64GS406/606/608/610 ‘Ws’ or ‘f’) devices. It is not intended to be a • The bit in the W register or file register comprehensive reference source. To (specified by a literal value or indirectly by the complement the information in this data contents of register ‘Wb’) sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”. Please see the The literal instructions that involve data movement can Microchip web site (www.microchip.com) for use some of the following operands: the latest “dsPIC33F/PIC24H Family • A literal value to be loaded into a W register or file Reference Manual” sections. The register (specified by ‘k’) information in this data sheet supersedes • The W register or file register where the literal the information in the FRM. value is to be loaded (specified by ‘Wb’ or ‘f’) The dsPIC33F instruction set is identical to that of the However, literal instructions that involve arithmetic or dsPIC30F. logical operations use some of the following operands: Most instructions are a single program memory word • The first source operand, which is a register ‘Wb’ (24 bits). Only three instructions require two program without any address modifier memory locations. • The second source operand, which is a literal Each single-word instruction is a 24-bit word, divided value into an 8-bit opcode, which specifies the instruction • The destination of the result (only if not the same type and one or more operands, which further specify as the first source operand), which is typically a the operation of the instruction. register ‘Wd’ with or without an address modifier The instruction set is highly orthogonal and is grouped The MAC class of DSP instructions can use some of the into five basic categories: following operands: • Word or byte-oriented operations • The accumulator (A or B) to be used (required • Bit-oriented operations operand) • Literal operations • The W registers to be used as the two operands • DSP operations • The X and Y address space prefetch operations • Control operations • The X and Y address space prefetch destinations Table25-1 shows the general symbols used in • The accumulator write-back destination describing the instructions. The other DSP instructions do not involve any The dsPIC33F instruction set summary in Table25-2 multiplication and can include: lists all the instructions, along with the status flags • The accumulator to be used (required) affected by each instruction. • The source or destination operand (designated as Most word or byte-oriented W register instructions Wso or Wdo, respectively) with or without an (including barrel shift instructions) have three address modifier operands: • The amount of shift specified by a W register, • The first source operand, which is typically a ‘Wn’, or a literal value register ‘Wb’ without any address modifier The control instructions can use some of the following • The second source operand, which is typically a operands: register ‘Ws’ with or without an address modifier • A program memory address • The destination of the result, which is typically a • The mode of the Table Read and Table Write register ‘Wd’ with or without an address modifier instructions However, word or byte-oriented file register instructions have two operands: • The file register specified by the value, ‘f’ • The destination, which could be either the file register, ‘f’, or the W0 register, which is denoted as ‘WREG’  2009-2014 Microchip Technology Inc. DS70000591F-page 357

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Most instructions are a single word. Certain (unconditional/computed branch), indirect CALL/GOTO, double-word instructions are designed to provide all the all Table Reads and Writes, and RETURN/RETFIE required information in these 48 bits. In the second instructions, which are single-word instructions but take word, the 8MSbs are ‘0’s. If this second word is two or three cycles. Certain instructions that involve executed as an instruction (by itself), it will execute as skipping over the subsequent instruction require either a NOP. two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word The double-word instructions execute in two instruction or two-word instruction. Moreover, double-word moves cycles. require two cycles. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the Note: For more details on the instruction set, Program Counter is changed as a result of the refer to the “16-bit MCU and DSC instruction. In these cases, the execution takes two Programmer’s Reference Manual” instruction cycles with the additional instruction cycle(s) (DS70157). executed as a NOP. Notable exceptions are the BRA TABLE 25-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means “literal defined by text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator Write-Back Destination Address register {W13, [W13]+ = 2} bit4 4-bit bit selection field (used in word-addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0x0000...0x1FFF} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; LSb must be ‘0’ None Field does not require an entry, can be blank OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor Working register pair (Direct Addressing) DS70000591F-page 358  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 25-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier Working register pair for Square instructions  {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier Working register pair for DSP instructions  {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 Working registers {W0..W15} Wnd One of 16 Destination Working registers {W0...W15} Wns One of 16 Source Working registers {W0...W15} WREG W0 (Working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register  { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wx X Data Space Prefetch Address register for DSP instructions  {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none} Wxd X Data Space Prefetch Destination register for DSP instructions {W4...W7} Wy Y Data Space Prefetch Address register for DSP instructions  {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Wyd Y Data Space Prefetch Destination register for DSP instructions {W4...W7}  2009-2014 Microchip Technology Inc. DS70000591F-page 359

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 25-2: INSTRUCTION SET OVERVIEW Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z ADD Wso,#Slit4,Acc 16-Bit Signed Add to Accumulator 1 1 OA,OB,SA,SB 2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z 3 AND AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z 4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z 5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None 6 BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater Than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater Than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater Than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater Than 1 1 (2) None BRA LE,Expr Branch if Less Than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less Than or Equal 1 1 (2) None BRA LT,Expr Branch if Less Than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less Than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OA,Expr Branch if Accumulator A Overflow 1 1 (2) None BRA OB,Expr Branch if Accumulator B Overflow 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA SA,Expr Branch if Accumulator A Saturated 1 1 (2) None BRA SB,Expr Branch if Accumulator B Saturated 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None 7 BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None 8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None DS70000591F-page 360  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 9 BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None 10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3) 11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) 12 BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z 13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z 14 CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB 16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep 17 COM COM f f = f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z 18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z 19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z 20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z (Wb – Ws – C) 21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, Skip if = 1 1 None (2 or 3) 22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, Skip if > 1 1 None (2 or 3) 23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, Skip if < 1 1 None (2 or 3) 24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, Skip if  1 1 None (2 or 3) 25 DAW DAW Wn Wn = Decimal Adjust Wn 1 1 C 26 DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z 27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z 28 DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None  2009-2014 Microchip Technology Inc. DS70000591F-page 361

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 29 DIV DIV.S Wm,Wn Signed 16/16-Bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-Bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-Bit Integer Divide 1 18 N,Z,C,OV DIV.UD Wm,Wn Unsigned 32/16-Bit Integer Divide 1 18 N,Z,C,OV 30 DIVF DIVF Wm,Wn Signed 16/16-Bit Fractional Divide 1 18 N,Z,C,OV 31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 None DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None 39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z 41 IOR IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 43 LNK LNK #lit14 Link Frame Pointer 1 1 None 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z 45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply and Accumulate 1 1 OA,OB,OAB, , SA,SB,SAB AWB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB 46 MOV MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 N,Z MOV f,WREG Move f to WREG 1 1 None MOV #lit16,Wn Move 16-Bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-Bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 None MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None 47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and Store Accumulator 1 1 None DS70000591F-page 362  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 48 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd, Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, AWB SA,SB,SAB 51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(Ws) MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(lit5) MUL f W3:W2 = f * WREG 1 1 None 52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f = f + 1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 53 NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None 54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None W(nd):W(nd + 1) POP.S Pop Shadow Registers 1 1 All 55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None 56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep 57 RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None 58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None 59 RESET RESET Software Device Reset 1 1 None 60 RETFIE RETFIE Return from interrupt 1 3 (2) None 61 RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None 62 RETURN RETURN Return from Subroutine 1 3 (2) None 63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z 64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z 65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z  2009-2014 Microchip Technology Inc. DS70000591F-page 363

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None 68 SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C,N,Z 69 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None 70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB 71 SL SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z 72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f – WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z 73 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z 74 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z 75 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z 76 SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None 77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None 78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None 79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 81 ULNK ULNK Unlink Frame Pointer 1 1 None 82 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z 83 ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C,Z,N DS70000591F-page 364  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 26.0 DEVELOPMENT SUPPORT 26.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2009-2014 Microchip Technology Inc. DS7000591F-page 365

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 26.2 MPLAB XC Compilers 26.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16 and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other related modules together relocatable object files and archives to create an exe- • Flexible creation of libraries with easy module cutable file. MPLAB XC Compiler uses the assembler listing, replacement, deletion and extraction to produce its object file. Notable features of the assembler include: 26.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 26.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS7000591F-page 366  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 26.6 MPLAB X SIM Software Simulator 26.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 26.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 26.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the programs all 8, 16 and 32-bit MCU, and DSC devices target via a Microchip debug (RJ-11) connector (com- with the easy-to-use, powerful graphical user interface of patible with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 26.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2009-2014 Microchip Technology Inc. DS7000591F-page 367

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 26.11 Demonstration/Development 26.12 Third-Party Development Tools Boards, Evaluation Kits and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS7000591F-page 368  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 27.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(3) ....................................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD  3.0V(3) .................................................. -0.3V to +5.6V Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(3).........................................-0.3V to (VDD + 0.3V) Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin(2)...........................................................................................................................250 mA Maximum current sourced/sunk by any 4x I/O pin..................................................................................................15 mA Maximum current sourced/sunk by any 8x I/O pin..................................................................................................25 mA Maximum current sourced/sunk by any 16x I/O pin................................................................................................45 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports(2)...............................................................................................................200 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of the device maximum power dissipation (see Table27-2). 3: See the “Pin Diagrams” section for 5V tolerant pins.  2009-2014 Microchip Technology Inc. DS70000591F-page 369

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 27.1 DC Characteristics TABLE 27-1: OPERATING MIPS vs. VOLTAGE Max MIPS VDD Range Temp Range Characteristic (in Volts) (in °C) dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 — 3.0-3.6V(1) -40°C to +85°C 40 — 3.0-3.6V(1) -40°C to +125°C 40 Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. See Parameter BO10 in Table27-11 for the BOR values. TABLE 27-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Industrial Temperature Devices Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Extended Temperature Devices Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W I/O Pin Power Dissipation: I/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W TABLE 27-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm) JA 28 — °C/W 1 Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm) JA 39 — °C/W 1 Package Thermal Resistance, 80-Pin TQFP (12x12x1 mm) JA 53.1 — °C/W 1 Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm) JA 43 — °C/W 1 Package Thermal Resistance, 100-Pin TQFP (14x14x1 mm) JA 43 — °C/W 1 Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS70000591F-page 370  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Operating Voltage DC10 VDD Supply Voltage(4) 3.0 — 3.6 V Industrial and extended DC12 VDR RAM Data Retention Voltage(2) 1.8 — — V DC16 VPOR VDD Start Voltage — — VSS V to Ensure Internal Power-on Reset Signal DC17 SVDD VDD Rise Rate(3) 0.03 — — V/ms 0-3.0V in 0.1s to Ensure Internal Power-on Reset Signal Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: This is the limit to which VDD may be lowered without losing RAM data. 3: These parameters are characterized but not tested in manufacturing. 4: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN. See Parameter BO10 in Table27-11 for the BOR values.  2009-2014 Microchip Technology Inc. DS70000591F-page 371

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Typical(1) Max Units Conditions No. Operating Current (IDD)(2) DC20d 21 30 mA -40°C DC20a 21 30 mA +25°C 10 MIPS 3.3V DC20b 21 30 mA +85°C (See Note 2) DC20c 22 30 mA +125°C DC21d 28 40 mA -40°C DC21a 28 40 mA +25°C 16 MIPS 3.3V DC21b 28 40 mA +85°C (See Notes 2 and 3) DC21c 29 40 mA +125°C DC22d 35 45 mA -40°C DC22a 35 45 mA +25°C 20 MIPS 3.3V DC22b 35 45 mA +85°C (See Notes 2 and 3) DC22c 36 45 mA +125°C DC23d 49 60 mA -40°C DC23a 49 60 mA +25°C 30 MIPS 3.3V DC23b 49 60 mA +85°C (See Notes 2 and 3) DC23c 50 60 mA +125°C DC24d 66 75 mA -40°C DC24a 66 75 mA +25°C 40 MIPS 3.3V DC24b 66 75 mA +85°C (See Note 2) DC24c 67 75 mA +125°C DC25d 153 170 mA -40°C 40 MIPS DC25a 154 170 mA +25°C (See Notes 2 and 3), except PWM is 3.3V DC25b 155 170 mA +85°C operating at maximum speed (PTCON2 = 0x0000) DC25c 156 170 mA +125°C Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 2: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are all ‘0’s) • CPU executing while(1) statement • JTAG disabled 3: These parameters are characterized but not tested in manufacturing. DS70000591F-page 372  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Typical(1) Max Units Conditions No. Operating Current (IDD)(2) DC26d 122 135 mA -40°C 40 MIPS DC26a 123 135 mA +25°C (See Notes 2 and 3), except PWM is 3.3V DC26b 124 135 mA +85°C operating at 1/2 speed (PTCON2 = 0x0001)) DC26c 125 135 mA +125°C DC27d 107 120 mA -40°C 40 MIPS DC27a 108 120 mA +25°C (See Notes 2 and 3), except PWM is 3.3V DC27b 109 120 mA +85°C operating at 1/4 speed (PTCON2 = 0x0002)) DC27c 110 120 mA +125°C DC28d 88 100 mA -40°C 40 MIPS DC28a 89 100 mA +25°C (See Notes 2 and 3), except PWM is 3.3V DC28b 89 100 mA +85°C operating at 1/8 speed (PTCON2 = 0x0003) DC28c 89 100 mA +125°C Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 2: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are all ‘0’s) • CPU executing while(1) statement • JTAG disabled 3: These parameters are characterized but not tested in manufacturing.  2009-2014 Microchip Technology Inc. DS70000591F-page 373

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Typical(1) Max Units Conditions No. Idle Current (IIDLE): Core Off, Clock On Base Current(2) DC40d 8 15 mA -40°C DC40a 9 15 mA +25°C 3.3V 10 MIPS DC40b 9 15 mA +85°C DC40c 10 15 mA +125°C DC41d 11 20 mA -40°C DC41a 11 20 mA +25°C 3.3V 16 MIPS(3) DC41b 11 20 mA +85°C DC41c 12 20 mA +125°C DC42d 14 25 mA -40°C DC42a 14 25 mA +25°C 3.3V 20 MIPS(3) DC42b 14 25 mA +85°C DC42c 15 25 mA +125°C DC43d 20 30 mA -40°C DC43a 20 30 mA +25°C 3.3V 30 MIPS(3) DC43b 21 30 mA +85°C DC43c 22 30 mA +125°C DC44d 29 40 mA -40°C DC44a 29 40 mA +25°C 3.3V 40 MIPS DC44b 30 40 mA +85°C DC44c 31 40 mA +125°C Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 2: Base Idle current (IIDLE) is measured as follows: • CPU core is off, oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are all ‘0’s) • JTAG is disabled 3: These parameters are characterized but not tested in manufacturing. DS70000591F-page 374  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Typical(1) Max Units Conditions No. Power-Down Current (IPD)(2,4) DC60d 50 500 A -40°C DC60a 50 500 A +25°C 3.3V Base Power-Down Current DC60b 200 500 A +85°C DC60c 600 1000 A +125°C DC61d 8 13 A -40°C DC61a 10 15 A +25°C 3.3V Watchdog Timer Current: IWDT(3) DC61b 12 20 A +85°C DC61c 13 25 A +125°C Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. 2: IPD (Sleep) current is measured as follows: • CPU core is off, oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • All peripheral modules are disabled (all PMDx bits are all ‘1’s) • The VREGS bit (RCON<8>) = 0 (i.e., core regulator is set to standby while the device is in Sleep mode) • JTAG disabled 3: The  current is the additional current consumed when the WDT module is enabled. This current should be added to the base IPD current. 4: These currents are measured on the device containing the most memory in this family.  2009-2014 Microchip Technology Inc. DS70000591F-page 375

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Doze Parameter No. Typical(1) Max Units Conditions Ratio Doze Current (IDOZE)(2) DC73a 45 60 1:2 mA DC73f 40 60 1:64 mA -40°C 3.3V 40 MIPS DC73g 40 60 1:128 mA DC70a 43 60 1:2 mA DC70f 38 60 1:64 mA +25°C 3.3V 40 MIPS DC70g 38 60 1:128 mA DC71a 42 60 1:2 mA DC71f 37 60 1:64 mA +85°C 3.3V 40 MIPS DC71g 37 60 1:128 mA DC72a 41 60 1:2 mA DC72f 36 60 1:64 mA +125°C 3.3V 40 MIPS DC72g 36 60 1:128 mA Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. 2: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDOZE measurements are as follows: • Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are all ‘0’s) • CPU executing while(1) statement • JTAG disabled DS70000591F-page 376  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VIL Input Low Voltage DI10 I/O Pins VSS — 0.2VDD V DI15 MCLR VSS — 0.2VDD V DI16 I/O Pins with OSC1 or SOSCI VSS — 0.2VDD V DI18 I/O Pins with SDAx, SCLx VSS — 0.3 VDD V SMBus disabled DI19 I/O Pins with SDAx, SCLx VSS — 0.8 V SMBus enabled VIH Input High Voltage DI20 I/O Pins Non 5V Tolerant(4) 0.7VDD — VDD V DI21 I/O Pins 5V Tolerant(4) 0.7VDD — 5.5 V DI28 SDAx, SCLx 0.7VDD — 5.5 V SMBus disabled DI29 SDAx, SCLx 2.1 — 5.5 V SMBus enabled ICNPU CNx Pull-up Current DI30 — 250 — A VDD = 3.3V, VPIN = VSS IIL Input Leakage Current(2,3,4) DI50 I/O Pins with: 4x Driver Pins: RA0-RA7, RA14, — — ±2 A VSS  VPIN  VDD, RA15, RB0-RB15(10), RC1-RC4, Pin at high-impedance RC12-RC14, RD0-RD2, RD8-RD12, RD14, RD15, RE8, RE9, RF0-RF8, RF12, RF13, RG0-RG3, RG6-RG9, RG14, RG15 8x Driver Pins: RC15 — — ±4 A VSS  VPIN  VDD, Pin at high-impedance 16x Driver Pins: RA9, RA10, — — ±8 A VSS  VPIN  VDD, RD3-RD7, RD13, RE0-RE7, Pin at high-impedance RG12, RG13 DI55 MCLR — — ±2 A VSS VPIN VDD DI56 OSC1 — — ±2 A VSS VPIN VDD, XT and HS modes Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See the “Pin Diagrams” section for the list of 5V tolerant I/O pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: VIH source > (VDD + 0.3) for non-5V tolerant pins only. 7: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any “positive” input injection current. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted, provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. 10: RB11 has also been tested up to ±8 µA test limits.  2009-2014 Microchip Technology Inc. DS70000591F-page 377

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. IICL Input Low Injection Current DI60a 0 — -5(3,5,8) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO and RB11 IICH Input High Injection Current DI60b 0 — +5(6,7,8) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO, RB11 and digital 5V tolerant designated pins(3) IICT Total Input Injection Current DI60c (sum of all I/O and control pins) -20(9) — +20(9) mA Absolute instantaneous sum of all ± input injection currents from all I/O pins (| IICL + | IICH |)  IICT Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See the “Pin Diagrams” section for the list of 5V tolerant I/O pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: VIH source > (VDD + 0.3) for non-5V tolerant pins only. 7: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any “positive” input injection current. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted, provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. 10: RB11 has also been tested up to ±8 µA test limits. DS70000591F-page 378  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min. Typ. Max. Units Conditions VOL Output Low Voltage DO10 I/O Pins: — — 0.4 V IOL  6 mA, VDD = 3.3V 4x Sink Driver Pins – RA0-RA7, (See Note 1) RA14, RA15, RB0-RB15, RC1-RC4, RC12-RC14, RD0-RD2, RD8-RD12, RD14, RD15, RE8, RE9, RF0-RF8, RF12, RF13, RG0-RG3, RG6-RG9, RG14, RG15 Output Low Voltage I/O Pins: — — 0.4 V IOL  10 mA, VDD = 3.3V 8x Sink Driver Pin – RC15 (See Note 1) Output Low Voltage I/O Pins: — — 0.4 V IOL  18 mA, VDD = 3.3V 16x Sink Driver Pins – RA9, RA10, (See Note 1) RD3-RD7, RD13, RE0-RE7, RG12, RG13 VOH Output High Voltage DO20 I/O Pins: 2.4 — — V IOH-6 mA, VDD = 3.3V 4x Sink Driver Pins – RA0-RA7, (See Note 1) RA14, RA15, RB0-RB15, RC1-RC4, RC12-RC14, RD0-RD2, RD8-RD12, RD14, RD15, RE8, RE9, RF0-RF8, RF12, RF13, RG0-RG3, RG6-RG9, RG14, RG15 Output High Voltage I/O Pins: 2.4 — — V IOH-10 mA, VDD = 3.3V 8x Sink Driver Pin – RC15 (See Note 1) Output High Voltage I/O Pins: 2.4 — — V IOH-18 mA, VDD = 3.3V 16x Sink Driver Pins – RA9, RA10, (See Note 1) RD3-RD7, RD13, RE0-RE7, RG12, RG13 Note 1: Parameters are characterized, but not tested.  2009-2014 Microchip Technology Inc. DS70000591F-page 379

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min. Typ. Max. Units Conditions VOH1 Output High Voltage DO20A I/O Pins: 1.5 — — V IOH-12 mA, VDD = 3.3V 4x Sink Driver Pins – RA0-RA7, (See Note 1) RA14, RA15, RB0-RB15, 2.0 — — V IOH-11 mA, VDD = 3.3V RC1-RC4, RC12-RC14, RD0-RD2, (See Note 1) RD8-RD12, RD14, RD15, RE8, 3.0 — — V IOH-3 mA, VDD = 3.3V RE9, RF0-RF8, RF12, RF13, (See Note 1) RG0-RG3, RG6-RG9, RG14, RG15 Output High Voltage I/O Pins: 1.5 — — V IOH-16 mA, VDD = 3.3V 8x Sink Driver Pin – RC15 (See Note 1) 2.0 — — V IOH-12 mA, VDD = 3.3V (See Note 1) 3.0 — — V IOH-4 mA, VDD = 3.3V (See Note 1) Output High Voltage I/O Pins: 1.5 — — V IOH-30 mA, VDD = 3.3V 16x Sink Driver Pins – RA9, RA10, (See Note 1) RD3-RD7, RD13, RE0-RE7, 2.0 — — V IOH-25 mA, VDD = 3.3V RG12, RG13 (See Note 1) 3.0 — — V IOH-8 mA, VDD = 3.3V (See Note 1) Note 1: Parameters are characterized, but not tested. TABLE 27-11: ELECTRICAL CHARACTERISTICS: BROWN-OUT RESET (BOR) Standard Operating Conditions: 3.0V to 3.6V(3) (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min(1) Typ Max Units Conditions No. BO10 VBOR BOR Event on VDD Transition 2.6 — 2.95 V See Note 2 High-to-Low Note 1: Parameters are for design guidance only and are not tested in manufacturing. 2: The device will operate as normal until the VDDMIN threshold is reached. 3: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. DS70000591F-page 380  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Program Flash Memory D130 EP Cell Endurance 10,000 — — E/W -40C to +125C D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132B VPEW VDD for Self-Timed Write VMIN — 3.6 V VMIN = Minimum operating voltage D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated, -40C to +125C D135 IDDP Supply Current during — 10 — mA Programming D136a TRW Row Write Time 1.488 — 1.518 ms TRW = 11064 FRC cycles, TA = +85°C (See Note 2) D136b TRW Row Write Time 1.473 — 1.533 ms TRW = 11064 FRC cycles, TA = +125°C (See Note 2) D137a TPE Page Erase Time 22.7 — 23.1 ms TPE = 168517 FRC cycles, TA = +85°C (See Note 2) D137b TPE Page Erase Time 22.4 — 23.3 ms TPE = 168517 FRC cycles, TA = +125°C (See Note 2) D138a TWW Word Write Cycle Time 47.7 — 48.7 µs TWW = 355 FRC cycles, TA = +85°C (See Note 2) D138b TWW Word Write Cycle Time 47.3 — 49.2 µs TWW = 355 FRC cycles, TA = +125°C (See Note 2) Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min.), TUN<5:0> = b'100000 (for Max.). This parameter depends on the FRC accuracy (see Table27-20) and the value of the FRC Oscillator Tuning register (see Register9-4). For complete details on calculating the minimum and maximum time, see Section5.3 “Programming Operations”. TABLE 27-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristics Min Typ Max Units Comments No. — CEFC External Filter Capacitor 22 — — µF Capacitor must be low Value(1) series resistance (< 0.5 Ohms) Note 1: Typical VCAP voltage = 2.5 volts when VDD  VDDMIN.  2009-2014 Microchip Technology Inc. DS70000591F-page 381

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 27.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 AC characteristics and timing parameters. TABLE 27-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial AC CHARACTERISTICS -40°C  TA  +125°C for Extended Operating voltage VDD range as described in Section27.0 “Electrical Characteristics”. FIGURE 27-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSC2 VSS 15 pF for OSC2 output TABLE 27-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol Characteristic Min Typ Max Units Conditions No. DO50 COSCO OSC2 Pin — — 15 pF In XT and HS modes, when external clock is used to drive OSC1 DO56 CIO All I/O Pins and OSC2 — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode DS70000591F-page 382  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 27-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symb Characteristic Min Typ(1) Max Units Conditions No. OS10 FIN External CLKI Frequency DC — 40 MHz EC (external clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency 3.5 — 10 MHz XT — — 33 kHz SOSC 10 — 40 MHz HS OS20 TOSC TOSC = 1/FOSC 12.5 — DC ns OS25 TCY Instruction Cycle Time(2) 25 — DC ns OS30 TosL, External Clock in (OSC1) 0.375 x TOSC — 0.625 x TOSC ns EC TosH High or Low Time OS31 TosR, External Clock in (OSC1) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(3) — 5.2 — ns OS41 TckF CLKO Fall Time(3) — 5.2 — ns OS41 GM External Oscillator 14 16 18 mA/V VDD = 3.3V, Transconductance TA = +25ºC Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.  2009-2014 Microchip Technology Inc. DS70000591F-page 383

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS50 FPLLI PLL Voltage Controlled 0.8 — 8 MHz ECPLL, XTPLL modes Oscillator (VCO) Input Frequency Range OS51 FSYS On-Chip VCO System 100 — 200 MHz Frequency OS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 mS OS53 DCLK CLKO Stability (Jitter)(2) -3 0.5 3 % Measured over a 100 ms period Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested in manufacturing. 2: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases or communication clocks, use this formula: DCLK Peripheral Clock Jitter = ------------------------------------------------------------------------  FOSC  -------------------------------------------------------------- Peripheral Bit Rate Clock For example: FOSC = 32 MHz, DCLK = 3%, SPI bit rate clock (i.e., SCK) is 2 MHz. DCLK 3% 3% SPI SCK Jitter = ------------------------------ = ---------- = -------- = 0.75% 32 MHz 16 4 --------------------  2 MHz TABLE 27-18: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS56 FHPOUT On-Chip, 16x PLL CCO 112 118 120 MHz Frequency OS57 FHPIN On-Chip, 16x PLL Phase 7.0 7.37 7.5 MHz Detector Input Frequency OS58 TSU Frequency Generator Lock — — 10 µs Time Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested in manufacturing. DS70000591F-page 384  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-19: AC CHARACTERISTICS: INTERNAL FRC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA +85°C for industrial -40°C  TA  +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1) F20a FRC -1 — +1 % -40°C  TA +85°C VDD = 3.0-3.6V F20b FRC -2 — +2 % -40°C  TA +125°C VDD = 3.0-3.6V Note 1: Frequency calibrated at +25°C and 3.3V. The TUN<5:0> bits can be used to compensate for temperature drift. TABLE 27-20: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. LPRC @ 32.768 kHz(1) F21a LPRC -40 — +40 % -40°C  TA +85°C F21b LPRC -50 — +50 % -40°C  TA +125°C Note 1: Change of LPRC frequency as VDD changes.  2009-2014 Microchip Technology Inc. DS70000591F-page 385

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure27-1 for load conditions. TABLE 27-21: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. DO31 TIOR Port Output Rise Time 4x Source Driver Pins – RA0-RA7, — 10 25 ns Refer to Figure27-1 RA14, RA15, RB0-RB15, RC1-RC4, for test conditions RC12-RC14, RD0-RD2, RD8-RD12, RD14, RD15, RE8, RE9, RF0-RF8, RF12, RF13, RG0-RG3, RG6-RG9, RG14, RG15 8x Source Driver Pins – RC15 — 8 20 ns 16x Source Driver Pins – RE0-RE7, — 6 15 ns RG12, RG13 DO32 TIOF Port Output Fall Time 4x Source Driver Pins – RA0-RA7, — 10 25 ns Refer to Figure27-1 RA14, RA15, RB0-RB15, RC1-RC4, for test conditions RC12-RC14, RD0-RD2, RD8-RD12, RD14, RD15, RE8, RE9, RF0-RF8, RF12, RF13, RG0-RG3, RG6-RG9, RG14, RG15 8x Source Driver Pins – RC15 — 8 20 ns 16x Source Driver Pins – RE0-RE7, — 6 15 ns RG12, RG13 DI35 TINP INTx Pin High or Low Time (input) 20 — — ns DI40 TRBP CNx High or Low Time (input) 2 — — TCY Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. DS70000591F-page 386  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD SY12 MCLR Internal SY10 POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure27-1 for load conditions.  2009-2014 Microchip Technology Inc. DS70000591F-page 387

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SY10 TMCL MCLR Pulse Width (low) 2 — — s -40°C to +85°C SY11 TPWRT Power-up Timer Period — 2 — ms -40°C to +85°C, 4 User programmable 8 16 32 64 128 SY12 TPOR Power-on Reset Delay 3 10 30 s -40°C to +85°C SY13 TIOZ I/O High-Impedance from 0.68 0.72 1.2 s MCLR Low or Watchdog Timer Reset SY20 TWDT1 Watchdog Timer Time-out — — — ms See Section24.4 “Watchdog Period Timer (WDT)” and LPRC Parameter F21a (Table27-20) SY30 TOST Oscillator Start-up Time — 1024TOSC — — TOSC = OSC1 period Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. DS70000591F-page 388  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-5: TIMER1/2/3 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRx Note: Refer to Figure27-1 for load conditions. TABLE 27-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature-40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TA10 TTXH T1CK High Time Synchronous, TCY + 20 — — ns Must also meet no Prescaler Parameter TA15, Synchronous, (TCY + 20)/N — — ns N = Prescale value (1, 8, 64, 256) with Prescaler Asynchronous 20 — — ns TA11 TTXL T1CK Low Time Synchronous, (TCY + 20) — — ns Must also meet no Prescaler Parameter TA15, Synchronous, (TCY + 20)/N — — ns N = Prescale value (1, 8, 64, 256) with Prescaler Asynchronous 20 — — ns TA15 TTXP T1CK Input Synchronous, 2 TCY + 40 — — ns Period no Prescaler Synchronous, Greater of: — — — N = Prescale value with Prescaler 40 ns or (1, 8, 64, 256) (2 TCY + 40)/N Asynchronous 40 — — ns OS60 Ft1 SOSCI/T1CK Oscillator Input DC — 50 kHz Frequency Range (oscillator enabled by setting bit, TCS (T1CON<1>)) TA20 TCKEXTMRL Delay from External T1CK Clock 0.75 TCY + 40 — 1.75 TCY + 40 — Edge to Timer Increment Note 1: Timer1 is a Type A.  2009-2014 Microchip Technology Inc. DS70000591F-page 389

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 T ABLE 27-24: TIMER2/4 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. TB10 TtxH TxCK High Synchronous Greater of: — — ns Must also meet Time mode 20 or Parameter TB15, (TCY + 20)/N N = Prescale value (1, 8, 64, 256) TB11 TtxL TxCK Low Synchronous Greater of: — — ns Must also meet Time mode 20 or Parameter TB15, (TCY + 20)/N N = Prescale value (1, 8, 64, 256) TB15 TtxP TxCK Input Synchronous Greater of: — — ns N = Prescale value Period mode 40 or (1, 8, 64, 256) (2 TCY + 40)/N TB20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns Clock Edge to Timer Increment Note 1: These parameters are characterized, but are not tested in manufacturing. TABLE 27-25: TIMER3/5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. TC10 TtxH TxCK High Synchronous TCY + 20 — — ns Must also meet Time Parameter TC15 TC11 TtxL TxCK Low Synchronous TCY + 20 — — ns Must also meet Time Parameter TC15 TC15 TtxP TxCK Input Synchronous, 2 TCY + 40 — — ns Period with Prescaler TC20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns Clock Edge to Timer Increment Note 1: These parameters are characterized, but are not tested in manufacturing. DS70000591F-page 390  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-6: INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure27-1 for load conditions. TABLE 27-26: INPUT CAPTURE x TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Max Units Conditions No. IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns With Prescaler 10 — ns IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns With Prescaler 10 — ns IC15 TccP ICx Input Period (TCY + 40)/N — ns N = Prescale value (1, 4, 16) Note 1: These parameters are characterized but not tested in manufacturing. FIGURE 27-7: OUTPUT COMPARE x (OCx) MODULE TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure27-1 for load conditions. TABLE 27-27: OUTPUT COMPARE x MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. OC10 TccF OCx Output Fall Time — — — ns See Parameter DO32 OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31 Note 1: These parameters are characterized but not tested in manufacturing.  2009-2014 Microchip Technology Inc. DS70000591F-page 391

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-8: OUTPUT COMPARE x/PWMx MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 OCx Active Tri-State TABLE 27-28: SIMPLE OCx/PWMx MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. OC15 TFD Fault Input to PWM I/O — — TCY + 20 ns Change OC20 TFLT Fault Input Pulse Width TCY + 20 — — ns Note 1: These parameters are characterized but not tested in manufacturing. DS70000591F-page 392  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-9: HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS MP30 FLTx MP20 PWMx FIGURE 27-10: HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure27-1 for load conditions. TABLE 27-29: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. MP10 TFPWM PWMx Output Fall Time — 2.5 — ns MP11 TRPWM PWMx Output Rise Time — 2.5 — ns MP20 TFD Fault Input  to PWMx — — 15 ns DTC<1:0> = 10 I/O Change MP30 TFH Minimum PWMx Fault Pulse 8 — — ns Width MP31 TPDLY Tap Delay 1.04 — — ns ACLK = 120 MHz MP32 ACLK PWMx Input Clock — — 120 MHz See Note 2 Note 1: These parameters are characterized but not tested in manufacturing. 2: This parameter is a maximum allowed input clock for the PWM module.  2009-2014 Microchip Technology Inc. DS70000591F-page 393

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-30: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Master Master Slave Maximum Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP Data Rate (Half-Duplex) (Full-Duplex) (Full-Duplex) 15 MHz Table27-31 — — 0,1 0,1 0,1 10 MHz — Table27-32 — 1 0,1 1 10 MHz — Table27-33 — 0 0,1 1 15 MHz — — Table27-34 1 0 0 11 MHz — — Table27-35 1 1 0 15 MHz — — Table27-36 0 1 0 11 MHz — — Table27-37 0 0 0 FIGURE 27-11: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 Note: Refer to Figure27-1 for load conditions. FIGURE 27-12: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 Note: Refer to Figure27-1 for load conditions. DS70000591F-page 394  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-31: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCKx Frequency — — 15 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdiV2scH, SDOx Data Output Setup to 30 — — ns TdiV2scL First SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2014 Microchip Technology Inc. DS70000591F-page 395

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-13: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP40 SDIx MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure27-1 for load conditions. TABLE 27-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCKx Frequency — — 10 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2sc, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70000591F-page 396  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-14: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure27-1 for load conditions. TABLE 27-33: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCKx Frequency — — 10 MHz -40ºC to +125ºC and see Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2014 Microchip Technology Inc. DS70000591F-page 397

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-15: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP50 SP52 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure27-1 for load conditions. DS70000591F-page 398  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input Frequency — — 15 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock, generated by the master, must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2014 Microchip Technology Inc. DS70000591F-page 399

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-16: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SP52 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure27-1 for load conditions. DS70000591F-page 400  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input Frequency — — 11 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock, generated by the master, must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2014 Microchip Technology Inc. DS70000591F-page 401

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-17: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOX MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure27-1 for load conditions. DS70000591F-page 402  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input Frequency — — 15 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock, generated by the master, must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2014 Microchip Technology Inc. DS70000591F-page 403

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-18: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOX MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure27-1 for load conditions. DS70000591F-page 404  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-37: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input Frequency — — 11 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock, generated by the master, must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009-2014 Microchip Technology Inc. DS70000591F-page 405

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-19: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Start Stop Condition Condition Note: Refer to Figure27-1 for load conditions. FIGURE 27-20: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM21 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure27-1 for load conditions. DS70000591F-page 406  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 T ABLE 27-38: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min(1) Max Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 100 ns IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) 40 — ns IM26 THD:DAT Data Input 100 kHz mode 0 — s Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(2) 0.2 — s IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — s Only relevant for Setup Time 400 kHz mode TCY/2 (BRG + 1) — s Repeated Start 1 MHz mode(2) TCY/2 (BRG + 1) — s condition IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — s After this period, the Hold Time 400 kHz mode TCY/2 (BRG + 1) — s first clock pulse is 1 MHz mode(2) TCY/2 (BRG + 1) — s generated IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — s Setup Time 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns 1 MHz mode(2) TCY/2 (BRG + 1) — ns IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(2) — 400 ns IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be 400 kHz mode 1.3 — s free before a new 1 MHz mode(2) 0.5 — s transmission can start IM50 CB Bus Capacitive Loading — 400 pF IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 3 Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to “Inter-Integrated Circuit™ (I2C™)” (DS70000195) in the “dsPIC33/PIC24 Family Reference Manual”. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: Typical value for this parameter is 130 ns.  2009-2014 Microchip Technology Inc. DS70000591F-page 407

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-21: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS34 IS30 IS33 SDAx Start Stop Condition Condition FIGURE 27-22: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS70000591F-page 408  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-39: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min Max Units Conditions IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — s Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(1) 0 0.3 s IS30 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated Setup Time 400 kHz mode 0.6 — s Start condition 1 MHz mode(1) 0.25 — s IS31 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first Hold Time 400 kHz mode 0.6 — s clock pulse is generated 1 MHz mode(1) 0.25 — s IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — s Setup Time 400 kHz mode 0.6 — s 1 MHz mode(1) 0.6 — s IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — ns 1 MHz mode(1) 250 ns IS40 TAA:SCL Output Valid 100 kHz mode 0 3500 ns From Clock 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start 1 MHz mode(1) 0.5 — s IS50 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).  2009-2014 Microchip Technology Inc. DS70000591F-page 409

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-40: 10-BIT, HIGH-SPEED ADC MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V and 3.6V(2) (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of: — Lesser of V VDD – 0.3 VDD + 0.3 or 3.0 or 3.6 AD02 AVSS Module VSS Supply Vss – 0.3 — VSS + 0.3 V Analog Input AD10 VINH-VINL Full-Scale Input Span VSS — VDD V AD11 VIN Absolute Input Voltage AVSS — AVDD V AD12 IAD Operating Current — 8 — mA AD13 — Leakage Current — ±0.6 — A VINL = AVSS = 0V, AVDD = 3.3V, Source Impedance = 100 AD17 RIN Recommended Impedance — — 100  of Analog Voltage Source DC Accuracy AD20 Nr Resolution 10 data bits bits AD21A INL Integral Nonlinearity > -2 ±0.5 < 2 LSb VINL = AVSS = 0V, AVDD = 3.3V AD22A DNL Differential Nonlinearity > -1 ±0.5 < 1 LSb VINL = AVSS = 0V, AVDD = 3.3V AD23A GERR Gain Error > -5 ±2.0 < 5 LSb VINL = AVSS = 0V, AVDD = 3.3V AD24A EOFF Offset Error > -3 ±0.75 < 3 LSb VINL = AVSS = VSS = 0V, AVDD = VDD = 3.3V AD25 — Monotonicity(1) — — — — Guaranteed Dynamic Performance AD30 THD Total Harmonic Distortion — -73 — dB AD31 SINAD Signal to Noise and — 58 — dB Distortion AD32 SFDR Spurious Free Dynamic — -73 — dB Range AD33 FNYQ Input Signal Bandwidth — — 1 MHz AD34 ENOB Effective Number of Bits — 9.4 — bits Note 1: The Analog-to-Digital conversion result never decreases with an increase in the input voltage and has no missing codes. 2: Overall functional device operation at VBOR < VDD < VDDMIN is ensured but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. DS70000591F-page 410  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-41: 10-BIT, HIGH-SPEED ADC MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V(2) (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Clock Parameters AD50b TAD ADC Clock Period 35.8 — — ns Conversion Rate AD55b tCONV Conversion Time — 14 TAD — — AD56b FCNV Throughput Rate Devices with Single SAR — — 2.0 Msps Devices with Dual SARs — — 4.0 Msps Timing Parameters AD63b tDPU Time to Stabilize Analog Stage 1.0 — 10 s from ADC Off to ADC On(1) Note 1: These parameters are characterized but not tested in manufacturing. 2: Overall functional device operation at VBOR < VDD < VDDMIN is guaranteed but not characterized. All device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN. FIGURE 27-23: ANALOG-TO-DIGITAL CONVERSION TIMING PER INPUT TCONV Trigger Pulse TAD ADC Clock ADC Data 9 8 2 1 0 ADBUFx Old Data New Data CONV  2009-2014 Microchip Technology Inc. DS70000591F-page 411

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-42: COMPARATOR MODULE SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) AC and DC CHARACTERISTICS Operating temperature:-40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min Typ Max Units Comments No. CM10 VIOFF Input Offset Voltage ±5 ±15 mV CM11 VICM Input Common-Mode 0 — AVDD – 1.5 V Voltage Range(1) CM12 VGAIN Open-Loop Gain(1) 90 — — db CM13 CMRR Common-Mode 70 — — db Rejection Ratio(1) CM14 TRESP Large Signal Response 20 30 ns V+ input step of 100mv while V- input held at AVDD/2. Delay measured from analog input pin to PWM output pin. Note 1: Parameters are for design guidance only and are not tested in manufacturing. TABLE 27-43: DAC MODULE SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) AC and DC CHARACTERISTICS Operating temperature:-40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Comments . No. DA01 EXTREF External Reference Voltage(1) 0 — AVDD – 1.6 V DA08 INTREF Internal Reference Voltage(1) 1.25 1.32 1.41 V DA02 CVRES Resolution 10 data bits bits DA03 INL Integral Nonlinearity Error — ±1.0 — — AVDD = 3.3V, DACREF = (AVDD/2)V DA04 DNL Differential Nonlinearity Error — ±0.8 — LSB DA05 EOFF Offset Error — ±2.0 — LSB DA06 EG Gain Error — ±2.0 — LSB DA07 TSET Settling Time(1) — — 650 nsec Measured when range=1 (high range) and CMREF<9:0> transitions from 0x1FF to 0x300. Note 1: Parameters are for design guidance only and are not tested in manufacturing. DS70000591F-page 412  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-44: DAC OUTPUT BUFFER SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min Typ Max Units Comments No. DA10 RLOAD Resistive Output Load 3K — —  Impedance DA11 CLOAD Output Load — 20 35 pF Capacitance DA12 IOUT Output Current Drive 200 300 400 A Sink and source Strength DA13 VRANGE Full Output Drive AVSS + 250 mV — AVDD – 900 mV V Strength Voltage Range DA14 VLRANGE Output Drive Voltage AVSS + 50 mV — AVDD – 500 mV V Range at Reduced Current Drive of 50 A DA15 IDD Current Consumed when — — 1.3 x IOUT A Module will always Module is Enabled, consume this current High-Power Mode even if no load is connected to the output DA16 ROUTON Output Impedance when — 500 —  Module is Enabled FIGURE 27-24: QEA/QEB INPUT CHARACTERISTICS TQ36 QEA (input) TQ31 TQ30 TQ35 QEB (input) TQ41 TQ40 TQ31 TQ30 TQ35 QEB Internal  2009-2014 Microchip Technology Inc. DS70000591F-page 413

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-45: QUADRATURE DECODER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Typ(2) Max Units Conditions No. TQ30 TQUL Quadrature Input Low Time 6 TCY — ns TQ31 TQUH Quadrature Input High Time 6 TCY — ns TQ35 TQUIN Quadrature Input Period 12 TCY — ns TQ36 TQUP Quadrature Phase Period 3 TCY — ns TQ40 TQUFL Filter Time to Recognize Low, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 3) TQ41 TQUFH Filter Time to Recognize High, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 3) Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: N = Index Channel Digital Filter Clock Divide Select bits. Refer to “Quadrature Encoder Interface (QEI)” (DS70208) in the “dsPIC33/PIC24 Family Reference Manual”. FIGURE 27-25: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ50 TQ51 Index Internal TQ55 Position Counter Reset DS70000591F-page 414  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 27-46: QEI INDEX PULSE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Max Units Conditions No. TQ50 TqIL Filter Time to Recognize Low, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) TQ51 TqiH Filter Time to Recognize High, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) TQ55 Tqidxr Index Pulse Recognized to Position 3 TCY — ns Counter Reset (ungated index) Note 1: These parameters are characterized but not tested in manufacturing. 2: Alignment of index pulses to QEA and QEB is shown for Position Counter Reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but index pulse recognition occurs on the falling edge. FIGURE 27-26: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEB TQ10 TQ11 TQ15 TQ20 POSCNT TABLE 27-47: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature-40°C TA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. TQ10 TtQH TQCK High Time Synchronous, TCY + 20 — — ns Must also meet with Prescaler Parameter TQ15 TQ11 TtQL TQCK Low Time Synchronous, TCY + 20 — — ns Must also meet with Prescaler Parameter TQ15 TQ15 TtQP TQCP Input Synchronous, 2 * TCY + 40 — — ns Period with Prescaler TQ20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing.  2009-2014 Microchip Technology Inc. DS70000591F-page 415

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 FIGURE 27-27: ECAN™ MODULE I/O TIMING CHARACTERISTICS CxTx Pin Old Value New Value (output) CA10 CA11 CxRx Pin (input) CA20 TABLE 27-48: ECAN™ MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. CA10 TioF Port Output Fall Time — — — ns See Parameter DO32 CA11 TioR Port Output Rise Time — — — ns See Parameter DO31 CA20 Tcwf Pulse Width to Trigger 120 — — ns CAN Wake-up Filter Note 1: These parameters are characterized but not tested in manufacturing. TABLE 27-49: DMA READ/WRITE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Characteristic Min. Typ Max. Units Conditions No. DM1 DMA Read/Write Cycle Time — — 1 TCY ns DS70000591F-page 416  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 28.0 50 MIPS ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 electrical characteristics for devices operating at 50 MIPS. Specifications are identical to those shown in Section27.0 “Electrical Characteristics”, with the exception of the parameters listed in this section. Absolute maximum ratings for the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 50 MIPS devices are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias...............................................................................................................-40°C to +85°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(2) ....................................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD  3.0V(2) .................................................. -0.3V to +5.6V Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(2).........................................-0.3V to (VDD + 0.3V) Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin(2)...........................................................................................................................250 mA Maximum current sourced/sunk by any 4x I/O pin..................................................................................................15 mA Maximum current sourced/sunk by any 8x I/O pin..................................................................................................25 mA Maximum current sourced/sunk by any 16x I/O pin................................................................................................45 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports(2)...............................................................................................................200 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: See the “Pin Diagrams” section for 5V tolerant pins.  2009-2014 Microchip Technology Inc. DS70000591F-page 417

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 28.1 DC Characteristics TABLE 28-1: OPERATING MIPS vs. VOLTAGE Max MIPS VDD Range Temp Range Characteristic (in Volts) (in °C) dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 — 3.0-3.6V(1) -40°C to +85°C 50 Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. See Parameter BO10 in Table27-11 for the BOR values. TABLE 28-2: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial Parameter Typical Max Units Conditions No. Operating Current (IDD)(1) MDC29d 85 100 mA -40°C MDC29a 85 100 mA +25°C 3.3V 50 MIPS MDC29b 85 100 mA +85°C Note 1: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are zeroed) • CPU executing while(1) statement • JTAG is disabled DS70000591F-page 418  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 28-3: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Parameter Typical Max Units Conditions No. Idle Current (IIDLE): Core Off Clock On Base Current(1) MDC45d 40 50 mA -40°C MDC45a 40 50 mA +25°C 3.3V 50 MIPS MDC45b 40 50 mA +85°C Note 1: Base Idle current (IIDLE) is measured as follows: • CPU core is off, oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are ‘0’s) • JTAG is disabled  2009-2014 Microchip Technology Inc. DS70000591F-page 419

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE 28-4: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Doze Parameter No. Typical Max Units Conditions Ratio Doze Current (IDOZE)(1) MDC74a 49 70 1:2 mA MDC74f 43 70 1:64 mA -40°C 3.3V 50 MIPS MDC74g 43 70 1:128 mA MDC75a 47 70 1:2 mA MDC75f 41 70 1:64 mA +25°C 3.3V 50 MIPS MDC75g 41 70 1:128 mA MDC76a 46 70 1:2 mA MDC76f 40 70 1:64 mA +85°C 3.3V 50 MIPS MDC76g 40 70 1:128 mA Note 1: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDOZE measurements are as follows: • Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are ‘0’s) • CPU executing while(1) statement • JTAG is disabled DS70000591F-page 420  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 28.2 AC Characteristics and Timing Parameters This section defines the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 AC characteristics and timing parameters for 50 MIPS devices. TABLE 28-5: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Param Symb Characteristic Min Typ(1) Max Units Conditions No. MOS10 FIN External CLKI Frequency DC — 50 MHz EC (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency 3.5 — 10 MHz XT — — 33 kHz SOSC 10 — 50 MHz HS MOS20 TOSC TOSC = 1/FOSC 10 — DC ns MOS25 TCY Instruction Cycle Time(2) 20 — DC ns MOS30 TosL, External Clock in (OSC1) 0.375 x TOSC — 0.625 x TOSC ns EC TosH High or Low Time MOS31 TosR, External Clock in (OSC1) — — 20 ns EC TosF Rise or Fall Time MOS40 TckR CLKO Rise Time(3) — 5.2 — ns MOS41 TckF CLKO Fall Time(3) — 5.2 — ns MOS41 GM External Oscillator 14 16 18 mA/V VDD = 3.3V, Transconductance TA = +25ºC Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.  2009-2014 Microchip Technology Inc. DS70000591F-page 421

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70000591F-page 422  2009-2014 Microchip Technology Inc.

 29.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS 2 0 0 9-20 Note: Tonhley . gTrhaep hpse rpforormvidaendc efo clhloawraincgte trhisisti cnso lties taerde h ae rsetiant iastriec anlo st utemsmteadr yo rb gausaerda notne ead l.i mIni tseodm neu gmrbaeprh so,f tshaem dpalteas p arensde anrtee dp mroavyid beed ofourt sdidees itghne gsupiedcainfieced oppuerpraotsinegs ds 14 range (e.g., outside specified power supply range) and therefore, outside the warranted range. P M I C ic ro 3 ch FIGURE 29-1: VOH – 4x DRIVER PINS FIGURE 29-3: VOH – 16x DRIVER PINS 3 ip F T --00..003300 --00..008800 J ec 3 hn 3.6V --00..007700 3.6V 2 o --00..002255 G lo gy 3.3V --00..006600 3.3V S Inc --00..002200 --00..005500 40 . A)A) 3V A)A) 3V Absolute Maximum 6 H (H ( --00..001155 Absolute Maximum H (H ( --00..004400 /6 OO OO 0 II II --00..003300 6 --00..001100 / --00..002200 6 0 -0.005 8 -0.010 / 6 0.000 0.000 1 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 1.00 2.00 3.00 4.00 a VOH (V) VOH (V) n d d s FIGURE 29-2: VOH – 8x DRIVER PINS P I --00..004400 C 3 --00..003355 3.6V 3 F --00..003300 3.3V J 6 4 --00..002255 3V Absolute Maximum G A)A) S H (H ( --00..002200 4 OO 0 D II --00..001155 6 S 70 -0.010 /6 0 0 0 0 6 59 -0.005 /6 1 F 0 -p 0.000 8 age 0.00 1.00 2.00 3.00 4.00 /6 4 VOH (V) 1 2 0 3

D FIGURE 29-4: VOL – 4x DRIVER PINS FIGURE 29-6: VOL – 16x DRIVER PINS d S7 s 0 P 0 0 00..004400 00..112200 I 0 C 5 9 3 1 00..003355 F-p 3.6V 00..110000 3.6V 3F ag 00..003300 3.3V 3.3V J e 424 00..002255 3V 00..008800 3V 32G A)A) A)A) OL (OL ( 00..002200 OL (OL ( 00..006600 S4 II 00..001155 Absolute Maximum II 00..004400 Absolute Maximum 06 / 00..001100 6 0 0.020 6 0.005 / 6 0 0.000 0.000 8 0.00 1.00 2.00 3.00 4.00 0.00 1.00 2.00 3.00 4.00 /6 1 VOL (V) VOL (V) 0 a n d FIGURE 29-5: VOL – 8x DRIVER PINS d s P 00..006600 IC 3 00..005500 3.6V 3F J 3.3V 6 00..004400 4 3V G  200 L (A)L (A) 00..003300 S4 9-201 IOIO 00..002200 Absolute Maximum 06/ 4 6 M 0 icroc 0.010 6/6 h ip 0 T 0.000 8 ec 0.00 1.00 2.00 3.00 4.00 /6 h n 1 olo VOL (V) 0 g y In c .

 FIGURE 29-7: TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 29-9: TYPICAL IIDLE CURRENT @ VDD = 3.3V 2 0 0 9-20 40 ds 14 P M 35 I C ic rochip A) mA) 30 33F Techn ent ( rent ( 2205 J32 ology In CurrD ge Cur 15 GS4 c P a 0 . I er 10 6 v / A 6 5 0 6 0 / 6 10 20 30 40 50 0 8 / Temperature (Celsius) MIPS 6 1 0 a FIGURE 29-8: TYPICAL IDD CURRENT @ VDD = 3.3V FIGURE 29-10: TYPICAL FRC FREQUENCY @ VDD = 3.3V n d d 90 s P 80 I C ) 3 A)70 Hz 3 m M F nt (60 cy ( J6 e n 4 rr50 ue G u q e C40 Fre S4 ag C 0 DS70 Aver30 FR 6/6 0 20 0 0 0 6 59 10 /6 1 F-pa 10 20 30 40 50 08 ge MIPS Temperature (Celsius) /6 4 1 2 0 5

D FIGURE 29-11: TYPICAL LPRC FREQUENCY @ VDD = 3.3V FIGURE 29-12: TYPICAL INTREF @ VDD = 3.3V d S7 s 0 P 0 0 I 0 C 5 9 3 1 F 3 -p F age 426 cy (kHz) V) J32G en F ( S u E 4 eq R 0 Fr NT 6 C I /6 R 0 P 6 L / 6 0 8 / 6 1 0 Temperature (Celsius) Temperature (Celsius) a n d d s P I C 3 3 F J 6 4 G  2 S 0 0 4 9-20 06 1 / 4 6 M 0 ic 6 roc /6 h ip 0 T 8 ec /6 h n 1 o lo 0 g y In c .

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 64-Lead QFN (9x9x0.9mm) Example XXXXXXXXXX 33FJ32GS XXXXXXXXXX 406-I/MR e3 YYWWNNN 1210017 64-Lead TQFP (10x10x1mm) Example XXXXXXXXXX dsPIC33FJ XXXXXXXXXX 32GS406 XXXXXXXXXX -I/PTe3 YYWWNNN 1210017 80-Lead TQFP (12x12x1mm) Example XXXXXXXXXXXX 33FJ32GS608 XXXXXXXXXXXX -I/PTe3 YYWWNNN 1210017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information.  2009-2014 Microchip Technology Inc. DS70000591F-page 427

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 30.1 Package Marking Information (Continued) 100-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX dsPIC33FJ64 XXXXXXXXXXXX GS608-I/PTe3 YYWWNNN 1210017 100-Lead TQFP (14x14x1mm) Example XXXXXXXXXXXX 33FJ32GS610 XXXXXXXXXXXX -I/PFe3 YYWWNNN 1210017 DS70000591F-page 428  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 30.2 Package Details Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2014 Microchip Technology Inc. DS70000591F-page 429

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000591F-page 430  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2014 Microchip Technology Inc. DS70000591F-page 431

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 D1/2 D NOTE 2 E1/2 A B E1 E A A SEE DETAIL 1 N 4X N/4 TIPS 0.20 C A-B D 1 3 2 4X NOTE 1 0.20 H A-B D TOP VIEW A2 A C 0.05 SEATING PLANE A1 64 X b 0.08 C 0.08 C A-B D e SIDE VIEW Microchip Technology Drawing C04-085C Sheet 1 of 2 DS70000591F-page 432  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging H c (cid:69) L (cid:84) (L1) X=A—B OR D SECTION A-A X e/2 DETAIL 1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 64 Lead Pitch e 0.50 BSC Overall Height A - - 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 - 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle (cid:73) 0° 3.5° 7° Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC Lead Thickness c 0.09 - 0.20 Lead Width b 0.17 0.22 0.27 Mold Draft Angle Top (cid:68) 11° 12° 13° Notes: Mold Draft Angle Bottom (cid:69) 11° 12° 13° 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-085C Sheet 2 of 2  2009-2014 Microchip Technology Inc. DS70000591F-page 433

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000591F-page 434  2009-2014 Microchip Technology Inc.

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(cid:16)(cid:31)0? (cid:19)? :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)@(cid:21)$’(cid:25) / (cid:15)(cid:5)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2) (cid:15)(cid:5)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)@(cid:21)$’(cid:25) /(cid:15) (cid:15)(cid:18)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2)(cid:15) (cid:15)(cid:18)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), 8(cid:13)(cid:11)$(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:22) (cid:4)(cid:31)(cid:4)(cid:6) = (cid:4)(cid:31)(cid:18)(cid:4) 8(cid:13)(cid:11)$(cid:14)@(cid:21)$’(cid:25) * (cid:4)(cid:31)(cid:15)(cid:19) (cid:4)(cid:31)(cid:18)(cid:18) (cid:4)(cid:31)(cid:18)(cid:19) (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)(cid:26)(cid:24)(cid:10) (cid:4) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)2(cid:24)’’(cid:24)( (cid:5) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? & (cid:13)(cid:6)(cid:12)’ (cid:15)(cid:31) (cid:21)(cid:27)(cid:14)(cid:15)(cid:14)!(cid:21)"#(cid:11)(cid:28)(cid:14)(cid:21)(cid:27)$(cid:13)%(cid:14)&(cid:13)(cid:11)’#(cid:23)(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29))(cid:14)*#’(cid:14)(#"’(cid:14)*(cid:13)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)+(cid:21)’(cid:25)(cid:21)(cid:27)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:25)(cid:11)’(cid:22)(cid:25)(cid:13)$(cid:14)(cid:11)(cid:23)(cid:13)(cid:11)(cid:31) (cid:18)(cid:31) ,(cid:25)(cid:11)(&(cid:13)(cid:23)"(cid:14)(cid:11)’(cid:14)(cid:22)(cid:24)(cid:23)(cid:27)(cid:13)(cid:23)"(cid:14)(cid:11)(cid:23)(cid:13)(cid:14)(cid:24)(cid:10)’(cid:21)(cid:24)(cid:27)(cid:11)(cid:28)-(cid:14)"(cid:21).(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29)(cid:31) (cid:16)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)"(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:27)$(cid:14)/(cid:15)(cid:14)$(cid:24)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:21)(cid:27)(cid:22)(cid:28)#$(cid:13)(cid:14)((cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:31)(cid:14)(cid:20)(cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:14)"(cid:25)(cid:11)(cid:28)(cid:28)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:13)%(cid:22)(cid:13)(cid:13)$(cid:14)(cid:4)(cid:31)(cid:18)0(cid:14)(((cid:14)(cid:10)(cid:13)(cid:23)(cid:14)"(cid:21)$(cid:13)(cid:31) (cid:5)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:21)(cid:27)(cid:12)(cid:14)(cid:11)(cid:27)$(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:21)(cid:27)(cid:12)(cid:14)(cid:10)(cid:13)(cid:23)(cid:14)(cid:7)(cid:3)(cid:20)/(cid:14)1(cid:15)(cid:5)(cid:31)0(cid:20)(cid:31) 2(cid:3),3 2(cid:11)"(cid:21)(cid:22)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:31)(cid:14)(cid:26)(cid:25)(cid:13)(cid:24)(cid:23)(cid:13)’(cid:21)(cid:22)(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)(cid:13)%(cid:11)(cid:22)’(cid:14)!(cid:11)(cid:28)#(cid:13)(cid:14)"(cid:25)(cid:24)+(cid:27)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13)"(cid:31) (cid:8)/43 (cid:8)(cid:13)&(cid:13)(cid:23)(cid:13)(cid:27)(cid:22)(cid:13)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27))(cid:14)#"#(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13))(cid:14)&(cid:24)(cid:23)(cid:14)(cid:21)(cid:27)&(cid:24)(cid:23)((cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:10)#(cid:23)(cid:10)(cid:24)"(cid:13)"(cid:14)(cid:24)(cid:27)(cid:28)(cid:29)(cid:31) (cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:26)(cid:13)(cid:22)(cid:25)(cid:27)(cid:24)(cid:28)(cid:24)(cid:12)(cid:29)(cid:2)(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12),(cid:4)(cid:5)(cid:9)(cid:4)(cid:6)(cid:18)2  2009-2014 Microchip Technology Inc. DS70000591F-page 435

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000591F-page 436  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 (cid:27)(cid:3)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:28)(cid:29)(cid:27)(cid:28)(cid:29)(cid:27)(cid:9)(cid:30)(cid:30)(cid:9)(cid:31) (cid:8)!"(cid:9)(cid:28)#(cid:3)(cid:3)(cid:9)(cid:30)(cid:30)(cid:9)$(cid:16)(cid:19)(cid:21)(cid:10)% & (cid:13)(cid:6)’ 4(cid:24)(cid:23)(cid:14)’(cid:25)(cid:13)(cid:14)((cid:24)"’(cid:14)(cid:22)#(cid:23)(cid:23)(cid:13)(cid:27)’(cid:14)(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)$(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12)")(cid:14)(cid:10)(cid:28)(cid:13)(cid:11)"(cid:13)(cid:14)"(cid:13)(cid:13)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:22)(cid:21)&(cid:21)(cid:22)(cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)(cid:11)’(cid:14) (cid:25)’’(cid:10)366+++(cid:31)((cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:31)(cid:22)(cid:24)(6(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12) D D1 e E E1 N b NOTE1 123 NOTE2 α c A φ β L A1 L1 A2 7(cid:27)(cid:21)’" (cid:20)(cid:30)88(cid:30)(cid:20)/(cid:26)/(cid:8)(cid:3) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:14)8(cid:21)((cid:21)’" (cid:20)(cid:30)9 9:(cid:20) (cid:20)(cid:7); 9#(*(cid:13)(cid:23)(cid:14)(cid:24)&(cid:14)8(cid:13)(cid:11)$" 9 (cid:15)(cid:4)(cid:4) 8(cid:13)(cid:11)$(cid:14) (cid:21)’(cid:22)(cid:25) (cid:13) (cid:4)(cid:31)(cid:5)(cid:4)(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)<(cid:13)(cid:21)(cid:12)(cid:25)’ (cid:7) = = (cid:15)(cid:31)(cid:18)(cid:4) (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:7)(cid:18) (cid:4)(cid:31)(cid:6)0 (cid:15)(cid:31)(cid:4)(cid:4) (cid:15)(cid:31)(cid:4)0 (cid:3)’(cid:11)(cid:27)$(cid:24)&&(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:31)(cid:4)0 = (cid:4)(cid:31)(cid:15)0 4(cid:24)(cid:24)’(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) 8 (cid:4)(cid:31)(cid:5)0 (cid:4)(cid:31)>(cid:4) (cid:4)(cid:31)(cid:19)0 4(cid:24)(cid:24)’(cid:10)(cid:23)(cid:21)(cid:27)’ 8(cid:15) (cid:15)(cid:31)(cid:4)(cid:4)(cid:14)(cid:8)/4 4(cid:24)(cid:24)’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13) (cid:3) (cid:4)? (cid:16)(cid:31)0? (cid:19)? :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)@(cid:21)$’(cid:25) / (cid:15)(cid:5)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2) (cid:15)(cid:5)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)@(cid:21)$’(cid:25) /(cid:15) (cid:15)(cid:18)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2)(cid:15) (cid:15)(cid:18)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), 8(cid:13)(cid:11)$(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:22) (cid:4)(cid:31)(cid:4)(cid:6) = (cid:4)(cid:31)(cid:18)(cid:4) 8(cid:13)(cid:11)$(cid:14)@(cid:21)$’(cid:25) * (cid:4)(cid:31)(cid:15)(cid:16) (cid:4)(cid:31)(cid:15)(cid:17) (cid:4)(cid:31)(cid:18)(cid:16) (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)(cid:26)(cid:24)(cid:10) (cid:4) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)2(cid:24)’’(cid:24)( (cid:5) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? & (cid:13)(cid:6)(cid:12)’ (cid:15)(cid:31) (cid:21)(cid:27)(cid:14)(cid:15)(cid:14)!(cid:21)"#(cid:11)(cid:28)(cid:14)(cid:21)(cid:27)$(cid:13)%(cid:14)&(cid:13)(cid:11)’#(cid:23)(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29))(cid:14)*#’(cid:14)(#"’(cid:14)*(cid:13)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)+(cid:21)’(cid:25)(cid:21)(cid:27)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:25)(cid:11)’(cid:22)(cid:25)(cid:13)$(cid:14)(cid:11)(cid:23)(cid:13)(cid:11)(cid:31) (cid:18)(cid:31) ,(cid:25)(cid:11)(&(cid:13)(cid:23)"(cid:14)(cid:11)’(cid:14)(cid:22)(cid:24)(cid:23)(cid:27)(cid:13)(cid:23)"(cid:14)(cid:11)(cid:23)(cid:13)(cid:14)(cid:24)(cid:10)’(cid:21)(cid:24)(cid:27)(cid:11)(cid:28)-(cid:14)"(cid:21).(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29)(cid:31) (cid:16)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)"(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:27)$(cid:14)/(cid:15)(cid:14)$(cid:24)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:21)(cid:27)(cid:22)(cid:28)#$(cid:13)(cid:14)((cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:31)(cid:14)(cid:20)(cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:14)"(cid:25)(cid:11)(cid:28)(cid:28)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:13)%(cid:22)(cid:13)(cid:13)$(cid:14)(cid:4)(cid:31)(cid:18)0(cid:14)(((cid:14)(cid:10)(cid:13)(cid:23)(cid:14)"(cid:21)$(cid:13)(cid:31) (cid:5)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:21)(cid:27)(cid:12)(cid:14)(cid:11)(cid:27)$(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:21)(cid:27)(cid:12)(cid:14)(cid:10)(cid:13)(cid:23)(cid:14)(cid:7)(cid:3)(cid:20)/(cid:14)1(cid:15)(cid:5)(cid:31)0(cid:20)(cid:31) 2(cid:3),3 2(cid:11)"(cid:21)(cid:22)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:31)(cid:14)(cid:26)(cid:25)(cid:13)(cid:24)(cid:23)(cid:13)’(cid:21)(cid:22)(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)(cid:13)%(cid:11)(cid:22)’(cid:14)!(cid:11)(cid:28)#(cid:13)(cid:14)"(cid:25)(cid:24)+(cid:27)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13)"(cid:31) (cid:8)/43 (cid:8)(cid:13)&(cid:13)(cid:23)(cid:13)(cid:27)(cid:22)(cid:13)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27))(cid:14)#"#(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13))(cid:14)&(cid:24)(cid:23)(cid:14)(cid:21)(cid:27)&(cid:24)(cid:23)((cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:10)#(cid:23)(cid:10)(cid:24)"(cid:13)"(cid:14)(cid:24)(cid:27)(cid:28)(cid:29)(cid:31) (cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:26)(cid:13)(cid:22)(cid:25)(cid:27)(cid:24)(cid:28)(cid:24)(cid:12)(cid:29)(cid:2)(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12),(cid:4)(cid:5)(cid:9)(cid:15)(cid:4)(cid:4)2  2009-2014 Microchip Technology Inc. DS70000591F-page 437

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000591F-page 438  2009-2014 Microchip Technology Inc.

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(cid:16)(cid:31)0? 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DS70000591F-page 439

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000591F-page 440  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 APPENDIX A: MIGRATING FROM dsPIC33FJ06GS101/X02 AND dsPIC33FJ16GSX02/X04 TO dsPIC33FJ32GS406/606/608/610 AND dsPIC33FJ64GS406/606/608/610 DEVICES This appendix provides an overview of considerations On dsPIC33FJ32GS406/606/608/610 and for migrating from the dsPIC33FJ06GS101/X02 and dsPIC33FJ64GS406/606/608/610 devices, Fault1 dsPIC33FJ16GSX02/X04 family of devices to the through Fault8 were assigned to Fault and Current- dsPIC33FJ32GS406/606/608/610 and Limit Controls with the following values: dsPIC33FJ64GS406/606/608/610 family of devices. • 01000 = Fault 1 The code developed for the dsPIC33FJ06GS101/X02 • 01001 = Fault 2 and dsPIC33FJ16GSX02/X04 devices can be ported to the dsPIC33FJ32GS406/606/608/610 and • 01010 = Fault 3 dsPIC33FJ64GS406/606/608/610 devices after • 01011 = Fault 4 making the appropriate changes outlined below. • 01100 = Fault 5 • 01101 = Fault 6 A.1 Device Pins and Peripheral Pin • 01110 = Fault 7 Select (PPS) • 01111 = Fault 8 On dsPIC33FJ06GS101/X02 and A.2.2 ANALOG COMPARATORS dsPIC33FJ16GSX02/X04 devices, some peripherals CONNECTION such as the Timer, Input Capture, Output Compare, UART, SPI, External Interrupts, Analog Comparator Connection of analog comparators to the PWM Fault Output, as well as the PWM4 pin pair, were mapped to and Current-Limit Control Signal Sources on physical pins via Peripheral Pin Select (PPS) dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ functionality. On dsPIC33FJ32GS406/606/608/610 X04 devices is performed by assigning a comparator to and dsPIC33FJ64GS406/606/608/610 devices, these one of the Fault sources via the virtual PPS pins, and peripherals are hard-coded to dedicated pins. Because then selecting the desired Fault as the source for Fault of this, as well as pinout differences between the two and Current-Limit Control. On dsPIC33FJ32GS406/ devices families, software must be updated to utilize 606/608/610 and dsPIC33FJ64GS406/606/608/610 peripherals on the desired pin locations. devices, analog comparators have a direct connection to Fault and Current-Limit Control, and can be selected A.2 High-Speed PWM with the following values for the CLSRC or FLTSRC bits: A.2.1 FAULT AND CURRENT-LIMIT • 00000 = Analog Comparator 1 CONTROL SIGNAL SOURCE • 00001 = Analog Comparator 2 SELECTION • 00010 = Analog Comparator 3 Fault and Current-Limit Control Signal Source selec- • 00011 = Analog Comparator 4 tion has changed between the two families of devices. On dsPIC33FJ06GS101/X02 and A.2.3 LEADING-EDGE BLANKING (LEB) dsPIC33FJ16GSX02/X04 devices, Fault1 through The Leading-Edge Blanking Delay (LEB) bits have Fault8 were assigned to Fault and Current-Limit been moved from the LEBCOx register on Controls with the following values: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ • 00000 = Fault 1 X04 devices to the LEBDLYx register on • 00001 = Fault 2 dsPIC33FJ32GS406/606/608/610 and • 00010 = Fault 3 dsPIC33FJ64GS406/606/608/610 devices. • 00011 = Fault 4 • 00100 = Fault 5 • 00101 = Fault 6 • 00110 = Fault 7 • 00111 = Fault 8  2009-2014 Microchip Technology Inc. DS70000591F-page 441

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 APPENDIX B: REVISION HISTORY Revision B (November 2009) The revision includes the following global update: Revision A (March 2009) • Added Note 2 to the shaded table that appears at This is the initial release of this document. the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in TableB-1. TABLE B-1: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Added “DMA Channels” column and updated the RAM size to 9K for the Signal Controllers” dsPIC33FJ64GS406 devices in the controller families table (see Table1). Updated the pin diagrams as follows: • 64-pin TQFP and QFN - Removed FLT8 from pin 51 - Added FLT8 to pin 60 - Added FLT17 to pin 31 - Added FLT18 to pin32 • 80-pin TQFP - Removed FLT8 from pin 63 - Added FLT8 to pin 76 - Added FLT19 to pin 53 - Added FLT20 to pin 52 • 100-pin TQFP - Removed FLT8 from pin 78 - Added FLT8 to pin 93 - Added SYNCO1 to pin 95 Section4.0 “Memory Organization” Added Data Memory Map for Devices with 8 KB RAM (see Figure4-4). Removed SFRs IPC25 and IPC26 from the Interrupt Controller Register Map for dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices (see Table4-7). The following bits in the Interrupt Controller Register Map for dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices were changed to unimplemented (see Table4-7): • Bit 2 of IFS1 • Bits 9-7 of IFS6 • Bit 2 of IEC1 • Bits 9-7 of IEC6 • Bits 10-8 of IPC4 Removed OSCTUN2 and LFSR, updated OSCCON and OSCTUN, renamed bit 13 of the REFOCON SFR in the System Control Register Map from ROSIDL to ROSSLP and changed the All Resets value from ‘0000’ to ‘2300’ for the ACLKCON SFR (see Table4-56). Updated bit 1 of the PMD Register Map for dsPIC33FJ64GS608 devices from unimplemented to C1MD (see Table4-60). DS70000591F-page 442  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE B-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section9.0 “Oscillator Configuration” Removed Section 9.2 “FRC Tuning”. Removed the PRCDEN, TSEQEN, and LPOSCEN bits from the Oscillator Control Register (see Register9-1). Updated the Oscillator Tuning Register (see Register9-4). Removed the Oscillator Tuning Register 2 and the Linear Feedback Shift Register. Updated the default Reset values from R/W-0 to R/W-1 for the SELACLK and APSTSCLR<2:0> bits in the ACLKCON register (see Register9-5). Renamed the ROSIDL bit to ROSSLP in the REFOCON register (see Register9-6). Section10.0 “Power-Saving Features” Updated the last paragraph of Section10.2.2 “Idle Mode” to clarify when instruction execution begins. Added Note 1 to the PMD1 register (see Register10-1). Section11.0 “I/O Ports” Changed the reference to digital-only pins to 5V tolerant pins in the second paragraph of Section11.2 “Open-Drain Configuration”. Section16.0 “High-Speed PWM” Updated the High-Speed PWM Module Register Interconnect Diagram (see Figure16-2). Updated the SYNCSRC<2:0> = 111, 101, and 100 definitions to Reserved in the PTCON and STCON registers (see Register16-1 and Register16-5). Updated the PWM time base maximum value from 0xFFFB to 0xFFF8 in the PTPER register (Register16-3). Updated the smallest pulse width value from 0x0008 to 0x0009 in Note 1 of the shaded note that follows the MDC register (see Register16-10). Updated the smallest pulse width value from 0x0008 to 0x0009 in Note 2 of the shaded note that follows the PDCx and SDCx registers (see Register16-12 and Register16-13). Added Note 2 and updated the FLTDAT<1:0> and CLDAT<1:0> bits, changing the word ‘data’ to ‘state’ in the IOCONx register (see Register16-19). Section20.0 “Universal Updated the two baud rate range features to: 10 Mbps to 38 bps at 40 Asynchronous Receiver Transmitter MIPS. (UART)” Section22.0 “High-Speed 10-bit Updated the TRGSRCx<4:0> = 01101 definition from Reserved to PWM Analog-to-Digital Converter (ADC)” secondary special event trigger selected, and updated Note 1 in the ADCP0-ADCP6 registers (see Register22-6 through Register22-12). Section24.0 “Special Features” Updated the second paragraph and removed the fourth paragraph in Section24.1 “Configuration Bits”. Updated the Device Configuration Register Map (see Table24-1).  2009-2014 Microchip Technology Inc. DS70000591F-page 443

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE B-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section27.0 “Electrical Updated the Absolute Maximum Ratings for high temperature and added Characteristics” Note 4. Updated all Operating Current (IDD) Typical and Max values in Table27-5. Updated all Idle Current (IIDLE) Typical and Max values in Table27-6. Updated all Power-Down Current (IPD) Typical and Max values in Table27-7. Updated all Doze Current (IDOZE) Typical and Max values in Table27-8. Updated the Typ and Max values for parameter D150 and removed parameters DI26, DI28, and DI29 from the I/O Pin Input Specifications (see Table27-9). Updated the Typ and Max values for parameter DO10 and DO27 and the Min and Typ values for parameter DO20 in the I/O Pin Output Specifications (see Table27-10). Added parameter numbers to the Auxiliary PLL Clock Timing Specifications (see Table27-18). Added parameters numbers and updated the Internal RC Accuracy Min, Typ, and Max values (see Table27-19 and Table27-20). Added parameter numbers, Note 2, updated the Min and Typ parameter values for MP31 and MP32, and removed the conditions for MP10 and MP11 in the High-Speed PWM Module Timing Requirements (see Table27-29). Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics (see Figure27-14). Added parameter IM51 to the I2Cx Bus Data Timing Requirements (Master Mode) (see Table27-34). Updated the Max value for parameter AD33 in the 10-bit High-Speed ADC Module Specifications (see Table27-36). Updated the titles and added parameter numbers to the Comparator and DAC Module Specifications (see Table27-38 and Table27-39) and the DAC Output Buffer Specifications (see Table27-40). DS70000591F-page 444  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Revision C (February 2010) This revision includes minor typographical and formatting changes throughout the data sheet text. All other changes are referenced by their respective section in TableB-2. TABLE B-2: MAJOR SECTION UPDATES Section Name Update Description Section16.0 “High-Speed PWM” Added Note 2 to PTPER (Register16-3). Added Note 1 to SEVTCMP (Register16-4). Updated Note 1 in MDC (Register16-10). Updated Note 5 and added Note 6 to PWMCONx (Register16-11). Updated Note 1 in PDCx (Register16-12). Updated Note 1 in SDCx (Register16-13). Updated Note 1 and Note 2 in PHASEx (Register16-14). Updated Note 2 in SPHASEx (Register16-15). Updated Note 1 in FCLCONx (Register16-21). Added Note 1 to STRIGx (Register16-22). Updated Leading-Edge Blanking Delay increment value from 8.4 ns to 8.32 ns and added a shaded note in LEBDLYx (Register16-24). Added Note 3 and Note 4 to PWMCAPx (Register16-26). Section27.0 “Electrical Updated the Min and Typ values for the Internal Voltage Regulator Characteristics” specifications in Table27-13. Updated the Min and Max values for the Internal RC Accuracy specifications in Table27-20.  2009-2014 Microchip Technology Inc. DS70000591F-page 445

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Revision D (January 2012) All other changes are referenced by their respective section in TableB-3. This revision includes minor typographical and formatting changes throughout the data sheet text. All occurrences of PGCn and PGDn (where n = 1, 2, or3) were updated to: PGECn and PGEDn throughout the document. TABLE B-3: MAJOR SECTION UPDATES Section Name Update Description “16-Bit Digital Signal Controllers with Added 50 MIPS to Operating Range. High-Speed PWM, ADC and Comparators” Changed the Oscillator frequency range in System Management. Added the “Referenced Sources” section. Section1.0 “Device Overview” Updated the block diagram of the core and peripheral modules (see Figure1-1). Section2.0 “Guidelines for Getting Updated the Recommended Minimum Connection diagram (see Started with 16-Bit Digital Signal Figure2-1). Controllers” Updated the VCAP pin capacitor specification in Section2.3 “Capacitor on Internal Voltage Regulator (VCAP)”. Section4.0 “Memory Organization” Removed IPC20 and updated IFS5, IFS7, IEC5, IEC7, and IPC29 in the Interrupt Controller Register Map for dsPIC33FJ64GS606 devices (see Table4-6). Removed IPC20 and IPC21 and updated IFS5, IFS7, IEC5, IEC7, and IPC29 in the Interrupt Controller Register Map for dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices (see Table4-7). Removed IPC20 and updated IFS5, IFS7, IEC5, IEC7, and IPC29 in the Interrupt Controller Register Map for dsPIC33FJ32GS606 devices (see Table4-10). Added High-Speed 10-bit ADC Register Map for dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices (see Table4-35). Updated ODCG in PORTG Register Map for dsPIC33FJ32GS610 and dsPIC33FJ64GS610 devices (see Table4-54). Updated ODCG in PORTG Register Map for dsPIC33FJ32GS608 and dsPIC33FJ64GS608 devices (see Table4-55). Updated ODCG in PORTG Register Map for dsPIC33FJ32GS406/606 and dsPIC33FJ64GS406/606 devices (see Table4-56). Section9.0 “Oscillator Configuration” Changed the High-Speed Crystal (HS) frequency range in Section9.1.1 “System Clock sources”. Updated the device operating speed to up to 50 MHz in Section9.1.2 “System Clock Selection”. Updated Section9.1.3 “PLL Configuration” to reflect the new operating range/speed of 50 MIPS/50 MHz. Updated Section9.2 “Auxiliary Clock Generation”. DS70000591F-page 446  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE B-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section22.0 “High-Speed, 10-Bit Analog- Updated the ADC Block Diagram for dsPIC33FJ32GS406 and to-Digital Converter (ADC)” dsPIC33FJ64GS406 Devices with one SAR (see Table22-1). Added Note 2 to ADCPC6: ADC Convert Pair Control Register 6 (see Register22-12). Section23.0 “High-Speed Analog Added Note 1 to the High-Speed Analog Comparator Module block Comparator” diagram (see Figure23-1). Section24.0 “Special Features” Updated Section24.1 “Configuration Bits”. Added the RTSP Effect column to the dsPIC33F Configuration Bits Description (see Table24-2). Added Note 3 to the Connections for the On-chip Voltage Regulator (see Figure24-1). Section27.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings. Updated the Operating MIPS vs. Voltage and added Note 1 (see Table27-1). Updated Note 4 and removed parameter DC18 from the DC Temperature and Voltage Specifications (see Table27-4). Updated Note 2, Typical and Maximum values for parameters DC20- DC24, and the Conditions for parameters DC25-DC28 in the Operating Current DC Characteristics (see Table27-5). Updated Note 2 in the Idle Current DC Characteristics (see Table27-6). Updated Note 2 in the Power-down Current DC Characteristics (see Table27-7). Added Note 2 to the Doze Current DC Characteristics (see Table27-8). Added parameters DI60a, DI60b, and DI60c to the I/O Pin Input Specifications (see Table27-9). Updated all I/O Pin Output Specifications (see Table27-10). Updated parameter BO10 and added Note 2 and Note 3 to the BOR Electrical Characteristics (see Table27-11). Added Note 1 to the Internal Voltage Regulator Specifications (see Table27-13). Updated the OS25 parameter in the External Clock Timing diagram (see Figure27-2). Added the Secondary Oscillator (SOSC) to parameter OS10, added parameter OS42 (GM), and added Note 2 to the External Clock Timing Requirements (see Table27-16). Updated Note 2 in the Internal FRC Accuracy AC Characteristics (see Table27-19). Updated parameters DO31 and DO32 in the I/O Timing Requirements (see Table27-21).  2009-2014 Microchip Technology Inc. DS70000591F-page 447

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TABLE B-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section27.0 “Electrical Characteristics” Updated the Timer1, Timer2, and Timer3 External Clock Timing (Continued) Requirements (see Table27-23, Table27-24, and Table27-25). Updated the Simple OC/PWM Mode Timing Requirements (see Table27-28). Updated all SPI Timing specifications (see Figure27-11-Figure27-18 and Table27-30-Table27-37). Added Note 2 to the 10-bit High-Speed ADC Module Specifications (see Table27-40). Added Note 2 to the 10-bit High-Speed ADC Module Timing Requirements (see Table27-41). Added parameter DA08 to the DAC Module Specifications (see Table27-43). Updated parameter DA16 in the DAC Output Buffer Specifications (see Table27-44). Added DMA Read/Write Timing Requirements (see Table27-49). Section28.0 “50 MIPS Electrical Added new chapter with electrical specifications for 50 MIPS devices. Characteristics” Section29.0 “DC and AC Device Added new chapter. Characteristics Graphs” Revision E (October 2012) This revision removes the Preliminary watermark and includes minor typographical and formatting changes throughout the data sheet. Revision F (July 2014) Changes CHOP bit to CHOPCLK in the High Speed Adds Register29-7 through Register29-12 to PWM Register Map and CHOPCLK PWMCHOP Clock Section29.0 “DC and AC Device Characteristics Generator Register (see Register4-16 and Graphs” Register16-9). Also includes minor typographical and formatting Changes values in the Minimum Row Write Time and changes throughout the data sheet. Maximum Row Write time equation examples (see Equation5-2 and Equation5-3). Adds the Oscillator Delay table (see Table6-2). Updates TUN bit ranges in the OSCTUN: Oscillator Tuning Register (see Register9-4). Updates the Type C Timer Block Diagram (see Figure13-2). Adds Note 1 to the CxFCTRL: ECANx FIFO Control Register (see Register21-4). Adds Note 10 to the DC Characteristics: I/O Pin Input Specifications (see Table27-9). Updates values in the DC Characteristics: Program Memory Table (see Table27-12). DS70000591F-page 448  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 INDEX A Type B Timer............................................................219 Type C Timer............................................................219 AC Characteristics............................................................382 Watchdog Timer (WDT)............................................354 10-Bit, High-Speed ADC...........................................410 Brown-out Reset (BOR)....................................120, 349, 353 Internal FRC Accuracy..............................................385 Internal LPRC Accuracy............................................385 C Load Conditions........................................................382 C Compilers Temperature and Voltage Specifications..................382 MPLAB XC Compilers..............................................366 Arithmetic Logic Unit (ALU).................................................39 Clock Generation Assembler Auxiliary....................................................................193 MPASM Assembler...................................................366 Reference.................................................................193 B Clock Switching................................................................201 Enabling....................................................................201 Barrel Shifter.......................................................................43 Sequence.................................................................201 Bit-Reversed Addressing..................................................102 Code Examples Example....................................................................103 Erasing a Program Memory Page............................113 Implementation.........................................................102 Initiating a Programming Sequence.........................114 Sequence Table (16-Entry).......................................103 Loading Write Buffers...............................................114 Block Diagrams Port Write/Read........................................................215 16-Bit Timer1 Module................................................217 PWRSAV Instruction Syntax....................................203 AC-to-DC Power Supply with PFC and 3 Outputs..........32 Code Protection........................................................349, 356 ADC Module with 1 SAR for dsPIC33FJ32GS406, CodeGuard Security.................................................349, 356 dsPIC33FJ64GS406 Devices...............................315 Configuration Bits.............................................................349 ADC Module with 2 SARs for dsPIC33FJ32GS606, Description................................................................350 dsPIC33FJ64GS606 Devices...............................316 Configuration Register Map..............................................349 ADC Module with 2 SARs for dsPIC33FJ32GS608, Configuring Analog Port Pins............................................215 dsPIC33FJ64GS608 Devices...............................317 CPU ADC Module with 2 SARs for dsPIC33FJ32GS610, Control Registers........................................................36 dsPIC33FJ64GS610 Devices...............................318 Data Addressing Overview.........................................33 Boost Converter Implementation................................27 DSP Engine Overview................................................33 Conceptual High-Speed PWMx................................233 Special MCU Features...............................................34 Connections for On-Chip Voltage Regulator.............353 CPU Clocking System......................................................191 Digital PFC..................................................................27 PLL Configuration.....................................................192 DMA Top Level Architecture Using Dedicated Selection...................................................................191 Transaction Bus................................................180 Sources....................................................................191 DSP Engine................................................................40 Customer Change Notification Service.............................455 dsPIC33FJ32GS406/606/608/610 and Customer Notification Service..........................................455 dsPIC33FJ64GS406/606/608/610.........................18 Customer Support.............................................................455 dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 CPU Core........34 D ECANx Module.........................................................286 Data Accumulators and Adder/Subtracter..........................41 High-Speed Analog Comparator x Module...............345 Data Space Write Saturation......................................43 High-Speed PWMx Architecture...............................232 Overflow and Saturation.............................................41 I2Cx Module..............................................................272 Round Logic...............................................................42 Input Capture x.........................................................225 Write-Back..................................................................42 Interleaved PFC..........................................................30 Data Address Space...........................................................47 MCLR Pin Connections...............................................24 Alignment....................................................................47 Minimum Connections................................................24 Memory Map for 4-Kbyte RAM Devices.....................48 Multi-Phase Synchronous Buck Converter.................28 Memory Map for 8-Kbyte RAM Devices.....................49 Off-Line Ups................................................................29 Memory Map for 9-Kbyte RAM Devices.....................50 Oscillator Circuit Placement........................................25 Near Data Space........................................................47 Oscillator System......................................................190 SFR Space.................................................................47 Output Compare x Module........................................227 Software Stack...........................................................99 Phase-Shifted Full-Bridge Converter..........................31 Width..........................................................................47 PLL............................................................................192 DC and AC Characteristics Quadrature Encoder Interface x................................261 Graphs and Tables...................................................423 Reset System............................................................116 DC Characteristics Shared Port Structure...............................................214 Brown-out Reset (BOR)............................................380 Simplified UARTx Module.........................................279 Doze Current (IDOZE)................................................376 Single-Phase Synchronous Buck Converter...............28 I/O Pin Input Specifications......................................377 SPIx Module..............................................................265 I/O Pin Output Specifications....................................379 Timer2/3/4/5 (32-Bit).................................................221  2009-2014 Microchip Technology Inc. DS70000591F-page 449

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Idle Current (IIDLE)....................................................374 G Internal Voltage Regulator Specifications.................381 Getting Started with 16-Bit DSCs.......................................23 Operating Current (IDD).............................................372 Application Connection Examples..............................26 Operating MIPS vs. Voltage......................................370 Capacitor on Internal Voltage Regulator (VCAP).........24 Power-Down Current (IPD)........................................375 Configuring Analog and Digital Pins During Program Memory......................................................381 ICSP Operations.................................................26 Temperature and Voltage Specifications..................371 Connection Requirements..........................................23 DC Characteristics (50 MIPS) Decoupling Capacitors................................................23 Doze Current (IDOZE)................................................420 External Oscillator Pins...............................................25 Idle Current (IIDLE)....................................................419 ICSP Pins...................................................................25 Operating Current (IDD).............................................418 Master Clear (MCLR) Pin...........................................24 Operating MIPS vs. Voltage......................................418 Oscillator Value Conditions on Start-up......................26 Demo/Development Boards, Evaluation and Unused I/Os................................................................26 Starter Kits................................................................368 Development Support.......................................................365 H Third-Party Tools......................................................368 High-Speed Analog Comparator.......................................345 DMA Controller Applications..............................................................346 Channel to Peripheral Associations..........................179 Comparator Input Range..........................................346 Control Registers......................................................180 Control Registers......................................................346 Doze Mode........................................................................204 DAC..........................................................................346 DSP Engine.........................................................................39 Output Range...................................................346 Multiplier......................................................................41 Digital Logic..............................................................346 E Features Overview....................................................345 Interaction with I/O Buffers.......................................346 ECAN Module Module Description...................................................345 Frame Types.............................................................285 High-Speed PWM.............................................................231 Modes of Operation..................................................287 Control Registers......................................................234 Overview...................................................................285 High-Speed, 10-Bit ADC ECANx Message Buffers Control Registers......................................................314 ECANx Word 0..........................................................309 Description................................................................313 ECANx Word 1..........................................................309 Module Functionality.................................................314 ECANx Word 2..........................................................310 ECANx Word 3..........................................................310 I ECANx Word 4..........................................................311 I/O Ports............................................................................213 ECANx Word 5..........................................................311 Parallel I/O (PIO)......................................................213 ECANx Word 6..........................................................312 Write/Read Timing....................................................215 ECANx Word 7..........................................................312 I2C Electrical Characteristics...................................................369 Control Registers......................................................271 Absolute Maximum Ratings......................................369 Operating Modes......................................................271 AC Characteristics and Timing Parameters..............382 Illegal Opcode Reset (IOPUWR)......................................121 Electrical Characteristics (50 MIPS)..................................417 In-Circuit Debugger...........................................................355 AC Characteristics and Timing Parameters..............421 In-Circuit Emulation..........................................................349 Enhanced CAN (ECAN) Module.......................................285 In-Circuit Serial Programming (ICSP).......................349, 355 Equations Input Capture....................................................................225 Device Operating Frequency....................................191 Control Registers......................................................226 FOSC Calculation.......................................................192 Input Change Notification.................................................215 Maximum Row Write Time........................................110 Instruction Addressing Modes............................................99 Minimum Row Write Time.........................................110 File Register Instructions............................................99 Programming Time...................................................110 Fundamental Modes Supported...............................100 XT with PLL Mode Example......................................192 MAC Instructions......................................................100 Errata..................................................................................14 MCU Instructions........................................................99 External Reset (EXTR)......................................................121 Move and Accumulator Instructions..........................100 F Other Instructions.....................................................100 Instruction Set Fail-Safe Clock Monitor (FSCM).......................................201 Overview...................................................................360 Flash Program Memory.....................................................109 Summary..................................................................357 Control Registers......................................................110 Symbols Used in Opcode Descriptions....................358 Operations................................................................110 Instruction-Based Power-Saving Modes...........................203 Programming Algorithm............................................113 Idle............................................................................204 RTSP Operation........................................................110 Sleep........................................................................203 Table Instructions......................................................109 Interfacing Program and Data Memory Spaces................104 Flexible Configuration.......................................................349 Inter-Integrated Circuit. See I2C. DS70000591F-page 450  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Internet Address................................................................455 O Interrupts Open-Drain Configuration.................................................215 Alternate Interrupt Vector Table (AIVT)....................123 Oscillator Configuration....................................................189 Control and Status Registers....................................127 Control Registers......................................................194 Interrupt Control and Status Registers Output Compare...............................................................227 IECx..................................................................127 Modes.......................................................................228 IFSx..................................................................127 INTCON1..........................................................127 P INTCON2..........................................................127 Packaging.........................................................................427 INTTREG..........................................................127 Details.......................................................................429 IPCx..................................................................127 Marking.....................................................................427 Interrupt Vector Table (IVT)......................................123 Peripheral Module Disable (PMD)....................................205 Reset Sequence.......................................................123 PICkit 3 In-Circuit Debugger/Programmer........................367 Setup Procedures.....................................................178 Pinout I/O Descriptions (table)............................................19 Initialization.......................................................178 Power Save Instructions Interrupt Disable...............................................178 Coincident Interrupts................................................204 Interrupt Service Routine..................................178 Power-on Reset (POR).....................................................120 Trap Service Routine........................................178 Power-Saving Features....................................................203 J Clock Frequency.......................................................203 Clock Switching........................................................203 JTAG Boundary Scan Interface........................................349 Power-up Timer (PWRT)..................................................120 JTAG Interface..................................................................355 Program Address Space.....................................................45 L Construction.............................................................104 Data Access from Program Memory Leading-Edge Blanking (LEB)...........................................231 Using PSV........................................................107 LPRC Oscillator Data Access from Program Memory Using Use with WDT...........................................................353 Table Instructions.............................................106 M Data Access from, Address Generation...................105 Memory Maps.............................................................45 Memory Organization..........................................................45 Table Read High Instructions Microchip Internet Web Site..............................................455 TBLRDH...........................................................106 Migrating from dsPIC33FJ06GS101/X02 and Table Read Low Instructions dsPIC33FJ16GSX02/X04 to dsPIC33FJ32GS406/606/ TBLRDL............................................................106 608/610 and dsPIC33FJ64GS406/606/608/610 Visibility Operation....................................................107 Devices.....................................................................441 Program Memory Migration Interrupt Vector...........................................................46 Analog Comparators Connection..............................441 Organization...............................................................46 Device Pins and Peripheral Pin Select (PPS)...........441 Reset Vector...............................................................46 Fault and Current-Limit Control Signal Programmer’s Model..........................................................35 Source Selection...............................................441 PWM Leading-Edge Blanking (LEB)...................................441 Power-Saving Features............................................204 Modes of Operation Disable......................................................................287 Q Initialization...............................................................287 Quadrature Encoder Interface (QEI).................................261 Listen All Messages..................................................287 Listen Only................................................................287 R Loopback..................................................................287 RCON Register Normal......................................................................287 Use of Status Bits.....................................................122 Modulo Addressing...........................................................101 Register Maps Applicability...............................................................102 Analog Comparator Control........................................91 Operation Example...................................................101 Change Notification (dsPIC33FJ32GS406/606 and Start and End Address..............................................101 dsPIC33FJ64GS406/606 Devices)........................54 W Address Register Selection..................................101 Change Notification (dsPIC33FJ32GS608/610 and MPLAB Assembler, Linker, Librarian................................366 dsPIC33FJ64GS608/610 Devices)........................54 MPLAB ICD 3 In-Circuit Debugger...................................367 CPU Core...................................................................52 MPLAB PM3 Device Programmer....................................367 DMA............................................................................88 MPLAB REAL ICE In-Circuit Emulator System.................367 ECAN1 (WIN (C1CTRL1) = 0 or 1).............................89 MPLAB X Integrated Development ECAN1 (WIN (C1CTRL1) = 0)....................................89 Environment Software...............................................365 ECAN1 (WIN (C1CTRL1) = 1)....................................90 MPLAB X SIM Software Simulator....................................367 High-Speed 10-Bit ADC Module (dsPIC33FJ32GS608 MPLIB Object Librarian.....................................................366 and dsPIC33FJ64GS608 Devices)........................85 MPLINK Object Linker......................................................366  2009-2014 Microchip Technology Inc. DS70000591F-page 451

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 High-Speed 10-Bit ADC Module (dsPIC33FJ32GS610 PORTE (dsPIC33FJ32GS406/606 and and dsPIC33FJ64GS610 Devices)........................83 dsPIC33FJ64GS406/606 Devices).....................94 High-Speed 10-Bit ADC Module (for PORTE (dsPIC33FJ32GS608/610 and dsPIC33FJ32GS406 and dsPIC33FJ64GS406 dsPIC33FJ64GS608/610 Devices).....................94 Devices)..............................................................87 PORTF (dsPIC33FJ32GS406/606 and High-Speed 10-Bit ADC Module (for dsPIC33FJ64GS406/606 Devices).....................95 dsPIC33FJ32GS606 and dsPIC33FJ64GS606 PORTF (dsPIC33FJ32GS608 and Devices)..............................................................86 dsPIC33FJ64GS608 Devices)............................94 High-Speed PWM.......................................................71 PORTF (dsPIC33FJ32GS610 and High-Speed PWM Generator 1...................................71 dsPIC33FJ64GS610 Devices)............................94 High-Speed PWM Generator 2...................................72 PORTG (dsPIC33FJ32GS406/606 and High-Speed PWM Generator 3...................................73 dsPIC33FJ64GS406/606 Devices).....................95 High-Speed PWM Generator 4...................................74 PORTG (dsPIC33FJ32GS608 and High-Speed PWM Generator 5...................................75 dsPIC33FJ64GS608 Devices)............................95 High-Speed PWM Generator 6...................................76 PORTG (dsPIC33FJ32GS610 and High-Speed PWM Generator 7 (All Devices dsPIC33FJ64GS610 Devices)............................95 except dsPIC33FJ32GS406 and Quadrature Encoder Interface 1 (QEI1)......................70 dsPIC33FJ64GS406).............................................77 Quadrature Encoder Interface 2 (QEI2)......................70 High-Speed PWM Generator 8 (All Devices SPI1............................................................................82 except dsPIC33FJ32GS406 and SPI2............................................................................82 dsPIC33FJ64GS406).............................................78 System Control...........................................................96 High-Speed PWM Generator 9 (dsPIC33FJ32GS610 Timers.........................................................................69 and dsPIC33FJ64GS610 Devices)........................79 UART1........................................................................81 I2C1............................................................................80 UART2........................................................................81 I2C2............................................................................80 Registers Input Capture..............................................................69 ACLKCON (Auxiliary Clock Divisor Control).............199 Interrupt Controller (dsPIC33FJ32GS406 and ADBASE (ADC Base)...............................................322 dsPIC33FJ64GS406 Devices)............................61 ADC Base Register (ADBASE).................................322 Interrupt Controller (dsPIC33FJ32GS606 ADCON (ADC Control).............................................319 Devices)..............................................................67 ADCPC0 (ADC Convert Pair Control 0)....................324 Interrupt Controller (dsPIC33FJ32GS608 ADCPC1 (ADC Convert Pair Control 1)....................327 Devices)..............................................................65 ADCPC2 (ADC Convert Pair Control 2)....................330 Interrupt Controller (dsPIC33FJ32GS610 ADCPC3 (ADC Convert Pair Control 3)....................333 Devices)..............................................................63 ADCPC4 (ADC Convert Pair Control 4)....................336 Interrupt Controller (dsPIC33FJ64GS606 ADCPC5 (ADC Convert Pair Control 5)....................339 Devices)..............................................................59 ADCPC6 (ADC Convert Pair Control 6)....................342 Interrupt Controller (dsPIC33FJ64GS608 ADPCFG (ADC Port Configuration)..........................323 Devices)..............................................................57 ADPCFG2 (ADC Port Configuration 2).....................323 Interrupt Controller (dsPIC33FJ64GS610 ADSTAT (ADC Status).............................................321 Devices)..............................................................55 ALTDTRx (PWM Alternate Dead-Time x).................248 NVM............................................................................96 AUXCONx (PWM Auxiliary Control x)......................258 Output Compare.........................................................70 CHOP (PWM Chop Clock Generator)......................241 PMD (dsIPC33FJ64GS606 Devices)..........................98 CLKDIV (Clock Divisor)............................................196 PMD (dsPIC33FJ32GS406 and CMPCONx (Comparator Control x)..........................347 dsPIC33FJ64GS406 Devices)............................98 CMPDACx (Comparator DAC Control x)..................348 PMD (dsPIC33FJ32GS606 Devices)..........................98 CORCON (Core Control)....................................38, 128 PMD (dsPIC33FJ32GS608 Devices)..........................97 CxBUFPNT1 (ECANx Filter 0-3 PMD (dsPIC33FJ32GS610 Devices)..........................97 Buffer Pointer 1)...............................................298 PMD (dsPIC33FJ64GS608 Devices)..........................97 CxBUFPNT2 (ECANx Filter 4-7 PMD (dsPIC33FJ64GS610 Devices)..........................96 Buffer Pointer 2)...............................................299 PORTA (dsPIC33FJ32GS608 and CxBUFPNT3 (ECANx Filter 8-11 dsPIC33FJ64GS608 Devices)............................92 Buffer Pointer 3)...............................................300 PORTA (dsPIC33FJ32GS610 and CxBUFPNT4 (ECANx Filter 12-15 dsPIC33FJ64GS610 Devices)............................92 Buffer Pointer 4)...............................................301 PORTB........................................................................92 CxCFG1 (ECANx Baud Rate Configuration 1).........296 PORTC (dsPIC33FJ32GS406/606 and CxCFG2 (ECANx Baud Rate Configuration 2).........297 dsPIC33FJ64GS406/606 Devices).....................93 CxCTRL1 (ECANx Control 1)...................................288 PORTC (dsPIC33FJ32GS608 and CxCTRL2 (ECANx Control 2)...................................289 dsPIC33FJ64GS608 Devices)............................93 CxEC (ECANx Transmit/Receive Error Count).........296 PORTC (dsPIC33FJ32GS610 and CxFCTRL (ECANx FIFO Control).............................291 dsPIC33FJ64GS610 Devices)............................92 CxFEN1 (ECANx Acceptance Filter Enable 1).........298 PORTD (dsPIC33FJ32GS406/606 and CxFIFO (ECANx FIFO Status)..................................292 dsPIC33FJ64GS406/606 Devices).....................93 CxFMSKSEL1 (ECANx Filter 7-0 Mask PORTD (dsPIC33FJ32GS608/610 and Selection 1).......................................................303 dsPIC33FJ64GS608/610 Devices).....................93 DS70000591F-page 452  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 CxFMSKSEL2 (ECANx Filter 15-8 Mask IPC16 (Interrupt Priority Control 16).........................165 Selection 2).......................................................304 IPC17 (Interrupt Priority Control 17).........................166 CxINTE (ECANx Interrupt Enable)............................295 IPC18 (Interrupt Priority Control 18).........................167 CxINTF (ECANx Interrupt Flag)................................293 IPC2 (Interrupt Priority Control 2).............................154 CxRXFnEID (ECANx Acceptance Filter n IPC20 (Interrupt Priority Control 20).........................168 Extended Identifier)...........................................303 IPC21 (Interrupt Priority Control 21).........................169 CxRXFnSID (ECANx Acceptance Filter n IPC23 (Interrupt Priority Control 23).........................170 Standard Identifier)...........................................302 IPC24 (Interrupt Priority Control 24).........................171 CxRXFUL1 (ECANx Receive Buffer Full 1)..............306 IPC25 (Interrupt Priority Control 25).........................172 CxRXFUL2 (ECANx Receive Buffer Full 2)..............306 IPC26 (Interrupt Priority Control 26).........................173 CxRXMnEID (ECANx Acceptance Filter Mask n IPC27 (Interrupt Priority Control 27).........................174 Extended Identifier)...........................................305 IPC28 (Interrupt Priority Control 28).........................175 CxRXMnSID (ECANx Acceptance Filter Mask n IPC29 (Interrupt Priority Control 29).........................176 Standard Identifier)...........................................305 IPC3 (Interrupt Priority Control 3).............................155 CxRXOVF1 (ECANx Receive Buffer IPC4 (Interrupt Priority Control 4).............................156 Overflow 1).......................................................307 IPC5 (Interrupt Priority Control 5).............................157 CxRXOVF2 (ECANx Receive Buffer IPC6 (Interrupt Priority Control 6).............................158 Overflow 2).......................................................307 IPC7 (Interrupt Priority Control 7).............................159 CxTRmnCON (ECANx TX/RX IPC8 (Interrupt Priority Control 8).............................160 Buffer mn Control)............................................308 IPC9 (Interrupt Priority Control 9).............................161 CxVEC (ECANx Interrupt Code)...............................290 LEBCONx (Leading-Edge Blanking Control x).........255 DFLTxCON (Digital Filter x Control).........................264 LEBDLYx (Leading-Edge Blanking Delay x)............257 DMACS0 (DMA Controller Status 0).........................185 MDC (PWM Master Duty Cycle)...............................242 DMACS1 (DMA Controller Status 1).........................186 NVMCON (Flash Memory Control)...........................111 DMAxCNT (DMA Channel x Transfer Count)...........184 NVMKEY (Nonvolatile Memory Key)........................112 DMAxCON (DMA Channel x Control).......................181 OCxCON (Output Compare x Control, x = 1-4)........229 DMAxPAD (DMA Channel x OSCCON (Oscillator Control)...................................194 Peripheral Address)..........................................183 OSCTUN (Oscillator Tuning)....................................198 DMAxREQ (DMA Channel x IRQ Select).................182 PDCx (PWM Generator Duty Cycle x)......................245 DMAxSTA (DMA Channel x RAM Start Address PHASEx (PWM Primary Phase-Shift x)....................246 Offset A)............................................................182 PLLFBD (PLL Feedback Divisor).............................197 DMAxSTB (DMA Channel x RAM Start Address PMD1 (Peripheral Module Disable Control 1)..........206 Offset B)............................................................183 PMD2 (Peripheral Module Disable Control 2)..........208 DSADR (Most Recent DMA RAM Address)..............187 PMD3 (Peripheral Module Disable Control 3)..........209 DTRx (PWM Dead-Time x).......................................248 PMD4 (Peripheral Module Disable Control 4)..........209 FCLCONx (PWM Fault Current-Limit Control x).......252 PMD6 (Peripheral Module Disable Control 6)..........210 I2CxCON (I2Cx Control)...........................................273 PMD7 (Peripheral Module Disable Control 7)..........211 I2CxMSK (I2Cx Slave Mode Address Mask)............277 PTCON (PWM Time Base Control)..........................235 I2CxSTAT (I2Cx Status)...........................................275 PTCON2 (PWM Clock Divider Select 2)...................237 ICxCON (Input Capture x Control)............................226 PTPER (PWM Primary Master IEC0 (Interrupt Enable Control 0).............................142 Time Base Period)............................................237 IEC1 (Interrupt Enable Control 1).............................144 PWMCAPx (Primary PWM Time Base IEC2 (Interrupt Enable Control 2).............................146 Capture x).........................................................259 IEC3 (Interrupt Enable Control 3).............................147 PWMCONx (PWM Control x)...................................243 IEC4 (Interrupt Enable Control 4).............................148 QEIxCON (QEIx Control, x = 1 or 2).........................262 IEC5 (Interrupt Enable Control 5).............................149 RCON (Reset Control)..............................................117 IEC6 (Interrupt Enable Control 6).............................150 REFOCON (Reference Oscillator Control)...............200 IEC7 (Interrupt Enable Control 7).............................151 SDCx (PWM Secondary Duty Cycle x).....................245 IFS0 (Interrupt Flag Status 0)...................................132 SEVTCMP (PWM Special Event Compare).............238 IFS1 (Interrupt Flag Status 1)...................................134 SPHASEx (PWM Secondary Phase-Shift x)............247 IFS2 (Interrupt Flag Status 2)...................................136 SPIxCON1 (SPIx Control 1).....................................267 IFS3 (Interrupt Flag Status 3)...................................137 SPIxCON2 (SPIx Control 2).....................................269 IFS4 (Interrupt Flag Status 4)...................................138 SPIxSTAT (SPIx Status and Control).......................266 IFS5 (Interrupt Flag Status 5)...................................139 SR (CPU STATUS)............................................36, 128 IFS6 (Interrupt Flag Status 6)...................................140 SSEVTCMP (PWM Secondary Special Event IFS7 (Interrupt Flag Status 7)...................................141 Compare)..........................................................241 INTCON1 (Interrupt Control 1)..................................129 STCON (PWM Secondary Master Time Base INTCON2 (Interrupt Control 2)..................................131 Control).............................................................239 INTTREG (Interrupt Control and Status)...................177 STCON2 (PWM Secondary Clock Divider IOCONx (PWM I/O Control x)...................................250 Select 2)...........................................................240 IPC0 (Interrupt Priority Control 0).............................152 STPER (PWM Secondary Master Time Base IPC1 (Interrupt Priority Control 1).............................153 Period)..............................................................240 IPC12 (Interrupt Priority Control 12).........................162 STRIGx (PWM Secondary Trigger x IPC13 (Interrupt Priority Control 13).........................163 Compare Value)...............................................254 IPC14 (Interrupt Priority Control 14).........................164 T1CON (Timer1 Control)..........................................218  2009-2014 Microchip Technology Inc. DS70000591F-page 453

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 TRGCONx (PWM Trigger Control x).........................249 SPIx Slave Mode (Full-Duplex, CKE = 0, TRIGx (PWM Primary Trigger x CKP = 0, SMP = 0)...........................................404 Compare Value)................................................251 SPIx Slave Mode (Full-Duplex, CKE = 0, TxCON (Timerx Control, x = 2, 4).............................222 CKP = 1, SMP = 0)...........................................402 TyCON (Timery Control, y = 3, 5).............................223 SPIx Slave Mode (Full-Duplex, CKE = 1, UxMODE (UARTx Mode)..........................................280 CKP = 0, SMP = 0)...........................................398 UxSTA (UARTx Status and Control).........................282 SPIx Slave Mode (Full-Duplex, CKE = 1, Resets...............................................................................115 CKP = 1, SMP = 0)...........................................400 Brown-out Reset (BOR)............................................115 System Reset...........................................................119 Illegal Condition Reset (IOPUWR)............................115 Timer1/2/3 External Clock........................................389 Illegal Opcode...................................................115, 121 TimerQ (QEI Module) External Clock Master Clear Pin Reset (MCLR)...............................115 Characteristics..................................................415 Power-on Reset (POR).............................................115 Timing Requirements Security.....................................................................121 10-Bit, High-Speed ADC...........................................411 Security Reset...........................................................115 Auxiliary PLL Clock Specifications............................384 Software RESET Instruction (SWR).........................115 Capacitive Loading on Output Pins..........................382 Trap Conflict Reset (TRAPR)....................................115 DMA Read/Write.......................................................416 Uninitialized W Register....................................115, 121 ECAN I/O..................................................................416 Watchdog Timer Reset (WDTO)...............................115 External Clock...........................................................383 Revision History................................................................442 High-Speed PWMx...................................................393 I/O.............................................................................386 S I2Cx Bus Data (Master Mode)..................................407 Serial Peripheral Interface (SPI).......................................265 I2Cx Bus Data (Slave Mode)....................................409 Software RESET Instruction (SWR)..................................121 Input Capture x (ICx)................................................391 Software Stack Pointer, Frame Pointer Output Compare x (OCx)..........................................391 CALL Stack Frame......................................................99 PLL Clock Specifications..........................................384 Special Features of the CPU.............................................349 QEI External Clock...................................................415 QEI Index Pulse........................................................415 T Quadrature Decoder.................................................414 Thermal Operating Conditions..........................................370 Reset, Watchdog Timer, Oscillator Start-up Timer, Thermal Packaging Characteristics..................................370 Power-up Timer and Brown-out Reset.............388 Timer1...............................................................................217 Simple OCx/PWMx Mode.........................................392 Mode Settings...........................................................217 SPIx Master Mode (Full-Duplex, CKE = 0, Timer2/3/4/5......................................................................219 CKP = x, SMP = 1)...........................................397 16-Bit Operation........................................................220 SPIx Master Mode (Full-Duplex, CKE = 1, 32-Bit Operation........................................................220 CKP = x, SMP = 1)...........................................396 32-Bit Timer..............................................................220 SPIx Master Mode (Half-Duplex, Mode Settings...........................................................220 Transmit Only)..................................................395 Timing Diagrams SPIx Slave Mode (Full-Duplex, CKE = 0, Analog-to-Digital Conversion per Input.....................411 CKP = 0, SMP = 0)...........................................405 Brown-out Situations.................................................120 SPIx Slave Mode (Full-Duplex, CKE = 0, ECAN I/O..................................................................416 CKP = 1, SMP = 0)...........................................403 External Clock...........................................................383 SPIx Slave Mode (Full-Duplex, CKE = 1, High-Speed PWMx Characteristics...........................393 CKP = 0, SMP = 0)...........................................399 High-Speed PWMx Fault Characteristics..................393 SPIx Slave Mode (Full-Duplex, CKE = 1, I/O Characteristics....................................................386 CKP = 1, SMP = 0)...........................................401 I2Cx Bus Data (Master Mode)..................................406 Timer1 External Clock..............................................389 I2Cx Bus Data (Slave Mode)....................................408 Timer2/4 External Clock...........................................390 I2Cx Bus Start/Stop Bits (Master Mode)...................406 Timer3/5 External Clock...........................................390 I2Cx Bus Start/Stop Bits (Slave Mode).....................408 Timing Requirements (50 MIPS) Input Capture x (ICx) Characteristics........................391 External Clock...........................................................421 OCx/PWMx Characteristics......................................392 Timing Specifications Output Compare x (OCx) Characteristics.................391 Comparator Module..................................................412 Output Compare x Operation....................................228 DAC Module.............................................................412 QEA/QEB Input Characteristics................................413 DAC Output Buffer....................................................413 QEI Module Index Pulse...........................................414 Trap Conflict Reset (TRAPR)...........................................121 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer.........................................387 SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1)............................................397 SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1)............................................396 SPIx Master Mode (Half-Duplex, Transmit Only, CKE = 0)...................................394 SPIx Master Mode (Half-Duplex, Transmit Only, CKE = 1)...................................394 DS70000591F-page 454  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 U W Universal Asynchronous Receiver Watchdog Timer (WDT)............................................349, 353 Transmitter (UART)...................................................279 Programming Considerations...................................354 Watchdog Timer Time-out Reset (WDTO).......................121 V WWW Address.................................................................455 Voltage Regulator (On-Chip)............................................353 WWW, On-Line Support.....................................................14  2009-2014 Microchip Technology Inc. DS70000591F-page 455

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70000591F-page 456  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2009-2014 Microchip Technology Inc. DS7000591F-page 457

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS7000591F-page 458  2009-2014 Microchip Technology Inc.

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 32 GS4 06 T -50I / PT - XXX Examples: a) dsPIC33FJ32GS406-50-I/PT: Microchip Trademark SMPS dsPIC33, 32-Kbyte program memory, 64-pin, Architecture 50 MIPS, Industrial temp., TQFP Flash Memory Family package. Program Memory Size (Kbytes) Product Group Pin Count Tape and Reel Flag (if applicable) Speed Temperature Range Package Pattern Architecture: 33 = 16-Bit Digital Signal Controller Flash Memory FJ = Flash program memory, 3.3V Family: Product Group: GS4 = Switch Mode Power Supply (SMPS) family GS6 = Switch Mode Power Supply (SMPS) family Pin Count: 06 = 64-pin 08 = 80-pin 10 = 100-pin Speed: 50 = 50 MIPS = 40 MIPS (marking intentionally absent) Temperature Range: I = -40C to +85C (Industrial) E = -40C to +125C (Extended) Package: PT = Plastic Thin Quad Flatpack – 10x10x1 mm body (TQFP) PT = Plastic Thin Quad Flatpack – 12x12x1 mm body (TQFP) PF = Plastic Thin Quad Flatpack – 14x14x1 mm body (TQFP) MR = Plastic Quad Flat, No Lead Package – 9x9x0.9 mm body (QFN)  2009-2014 Microchip Technology Inc. DS70000591F-page 459

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 NOTES: DS70000591F-page 460  2009-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2009-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63276-374-7 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2009-2014 Microchip Technology Inc. DS7000591F-page 461

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: DSPIC33FJ64GS406-E/MR DSPIC33FJ64GS406-E/PT DSPIC33FJ64GS406-I/MR DSPIC33FJ64GS406-I/PT DSPIC33FJ64GS406T-I/MR DSPIC33FJ64GS406T-I/PT DSPIC33FJ64GS606-E/MR DSPIC33FJ64GS606-E/PT DSPIC33FJ64GS606-I/MR DSPIC33FJ64GS606-I/PT DSPIC33FJ64GS606T-I/MR DSPIC33FJ64GS606T-I/PT DSPIC33FJ64GS608-E/PT DSPIC33FJ64GS608-I/PT DSPIC33FJ64GS608T-I/PT DSPIC33FJ64GS610-E/PF DSPIC33FJ64GS610-E/PT DSPIC33FJ64GS610-I/PF DSPIC33FJ64GS610-I/PT DSPIC33FJ64GS610T-I/PF DSPIC33FJ64GS610T-I/PT DSPIC33FJ32GS406-50I/MR DSPIC33FJ32GS406-50I/PT DSPIC33FJ32GS406T-50I/MR DSPIC33FJ32GS406T-50I/PT DSPIC33FJ32GS606-50I/MR DSPIC33FJ32GS606-50I/PT DSPIC33FJ32GS606T- 50I/MR DSPIC33FJ32GS606T-50I/PT DSPIC33FJ32GS608-50I/PT DSPIC33FJ32GS608T-50I/PT DSPIC33FJ32GS610-50I/PF DSPIC33FJ32GS610-50I/PT DSPIC33FJ32GS610T-50I/PF DSPIC33FJ32GS610T- 50I/PT DSPIC33FJ64GS406-50I/MR DSPIC33FJ64GS406-50I/PT DSPIC33FJ64GS406T-50I/MR DSPIC33FJ64GS406T-50I/PT DSPIC33FJ64GS606-50I/MR DSPIC33FJ64GS606-50I/PT DSPIC33FJ64GS606T- 50I/MR DSPIC33FJ64GS606T-50I/PT DSPIC33FJ64GS608-50I/PT DSPIC33FJ64GS608T-50I/PT DSPIC33FJ64GS610-50I/PF DSPIC33FJ64GS610-50I/PT DSPIC33FJ64GS610T-50I/PF DSPIC33FJ64GS610T- 50I/PT DSPIC33FJ32GS606-I/PT DSPIC33FJ32GS406-I/MR DSPIC33FJ32GS406T-I/PT DSPIC33FJ32GS606T- I/MR DSPIC33FJ32GS606-E/PT DSPIC33FJ32GS610-E/PF DSPIC33FJ32GS610-I/PT DSPIC33FJ32GS606T-I/PT DSPIC33FJ32GS610-E/PT DSPIC33FJ32GS608T-I/PT DSPIC33FJ32GS606-I/MR DSPIC33FJ32GS606-E/MR DSPIC33FJ32GS610T-I/PF DSPIC33FJ32GS406-E/MR DSPIC33FJ32GS406-I/PT DSPIC33FJ32GS406-E/PT DSPIC33FJ32GS406T-I/MR DSPIC33FJ32GS608-I/PT DSPIC33FJ32GS608-E/PT DSPIC33FJ32GS610-I/PF DSPIC33FJ32GS610T-I/PT