dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Advanced Analog Operating Conditions System Peripherals • 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS • 16-bit dual channel 100 ksps Audio DAC • 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS • Cyclic Redundancy Check (CRC) module • Up to five 16-bit and up to two 32-bit Timers/ Clock Management Counters • 2% internal oscillator • Up to four Input Capture (IC) modules • Programmable PLL and oscillator clock sources • Up to four Output Compare (OC) modules • Fail-Safe Clock Monitor (FSCM) • Real-Time Clock and Calendar (RTCC) module • Independent Watchdog Timer Communication Interfaces • Low-power management modes • Fast wake-up and start-up • Parallel Master Port (PMP) • Two UART modules (10 Mbps) Core Performance - Supports LIN 2.0 protocols • Up to 40 MIPS 16-bit dsPIC33F CPU - RS-232, RS-485, and IrDA® support • Single-cycle MUL plus hardware divide • Two 4-wire SPI modules (15 Mbps) • Enhanced CAN (ECAN) module (1 Mbaud) with Advanced Analog Features 2.0B support • 10/12-bit ADC with 1.1Msps/500 ksps rate: • I2C module (100K, 400K and 1Mbaud) with SMbus support - Up to 13 ADC input channels and four S&H • Data Converter Interface (DCI) module with I2S - Flexible/Independent trigger sources codec support • 150 ns Comparators: - Up to two Analog Comparator modules Direct Memory Access (DMA) - 4-bit DAC with two ranges for Analog Comparators • 8-channel DMA with no CPU stalls or overhead Input/Output • UART, SPI, ADC, ECAN, IC, OC, INT0 • Software remappable pin functions Qualification and Class B Support • 5V-tolerant pins • AEC-Q100 REVG (Grade 0 -40ºC to +150ºC) • Selectable open drain and internal pull-ups • Class B Safety Library, IEC 60730, VDE certified • Up to 5 mA overvoltage clamp current/pin • Multiple external interrupts Debugger Development Support • In-circuit and in-application programming • Two program breakpoints • Trace and run-time watch Packages Type SPDIP SOIC QFN-S QFN TQFP Pin Count 28 28 28 44 44 I/O Pins 21 21 21 35 35 Contact Lead/Pitch .100” 1.27 0.65 0.65 0.80 Dimensions .285x.135x1.365” 7.50x2.05x17.9 6x6x0.9 8x8x0.9 10x10x1 Note: All dimensions are in millimeters (mm) unless specified. © 2007-2012 Microchip Technology Inc. DS70292G-page 1

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 PRODUCT FAMILIES The device names, pin counts, memory sizes, and peripheral availability of each device are listed below. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 CONTROLLER FAMILIES Remappable Peripheral or) Device Pins Program Flash Memory (Kbyte) (1)RAM (Kbyte) Remappable Pins (2)16-bit Timer Input Capture Output CompareStandard PWM Data Converter Interface UART SPI ECAN™ (3)External Interrupts RTCC 2IC™ CRC Generator 10-bit/12-bit ADC(Channels) 16-bit Audio DAC (Pins) Analog Comparator2 Channels/Voltage Regulat 8-bit Parallel Master Port (Address Lines) I/O Pins Packages ( dsPIC33FJ128GP804 44 128 16 26 5 4 4 1 2 2 1 3 1 1 1 13 6 1/1 11 35 QFN TQFP dsPIC33FJ128GP802 28 128 16 16 5 4 4 1 2 2 1 3 1 1 1 10 4 1/0 2 21 SPDIP SOIC QFN-S dsPIC33FJ128GP204 44 128 8 26 5 4 4 1 2 2 0 3 1 1 1 13 0 1/1 11 35 QFN TQFP dsPIC33FJ128GP202 28 128 8 16 5 4 4 1 2 2 0 3 1 1 1 10 0 1/0 2 21 SPDIP SOIC QFN-S dsPIC33FJ64GP804 44 64 16 26 5 4 4 1 2 2 1 3 1 1 1 13 6 1/1 11 35 QFN TQFP dsPIC33FJ64GP802 28 64 16 16 5 4 4 1 2 2 1 3 1 1 1 10 4 1/0 2 21 SPDIP SOIC QFN-S dsPIC33FJ64GP204 44 64 8 26 5 4 4 1 2 2 0 3 1 1 1 13 0 1/1 11 35 QFN TQFP dsPIC33FJ64GP202 28 64 8 16 5 4 4 1 2 2 0 3 1 1 1 10 0 1/0 2 21 SPDIP SOIC QFN-S dsPIC33FJ32GP304 44 32 4 26 5 4 4 1 2 2 0 3 1 1 1 13 0 1/1 11 35 QFN TQFP dsPIC33FJ32GP302 28 32 4 16 5 4 4 1 2 2 0 3 1 1 1 10 0 1/0 2 21 SPDIP SOIC QFN-S Note 1: RAM size is inclusive of 2Kbytes of DMA RAM for all devices except dsPIC33FJ32GP302/304, which include 1Kbyte of DMA RAM. 2: Only four out of five timers are remappable. 3: Only two out of three interrupts are remappable. DS70292G-page 2 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams 28-Pin SPDIP, SOIC = Pins are up to 5V tolerant MCLR 1 28 AVDD AN0/VREF+/CN2/RA0 2 27 AVSS AN1/VREF-/CN3/RA1 3 26 AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 4 25 AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14 PGEC1/ AN3/C2IN+/RP1(1)/CN5/RB1 5 dsds 24 AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13 PP AN4/C1IN-/RP2(1)/CN6/RB2 6 ICIC 23 AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12 AN5/C1IN+/RP3(1)/CN7/RVBS3S 78 33FJ33FJ 2221 PPGGEECD22//TTMDIS/R/RPP1101(1(1)/)C/CNN1165/P/PMMDD21/R/RBB1101 16 OSC1/CLKI/CN30/RA2 9 284G 20 VCAP OSC2/CLKO/CN29/PMA0/RA3 10 GP 19 VSS SOSCI/RP4(1)/CN1/PMBE/RB4 11 P880 18 TDO/SDA1/RP9(1)/CN21/PMD3/RB9 02 SOSCO/T1CK/CN0/PMA1/RA4 12 2 17 TCK/SCL1/RP8(1)/CN22/PMD4/RB8 VDD 13 16 INT0/RP7(1)/CN23/PMD5/RB7 PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 14 15 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 28-Pin SPDIP, SOIC = Pins are up to 5V tolerant MCLR 1 28 AVDD AN0/VREF+/CN2/RA0 2 27 AVSS AN1/VREF-/CN3/RA1 3 26 AN9/RP15(1)/CN11/PMCS1/RB15 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 4 ddd 25 AN10/RTCC/RP14(1)/CN12/PMWR/RB14 PGEC1/ AN3/C2IN+/RP1(1)/CN5/RB1 5 sPsPsP 24 AN11/RP13(1)/CN13/PMRD/RB13 AANN54//CCO11SIINCN+1-///RRCPPL32K((I11/C))//CCNNN3076///RRRVABBS232S 6789 IC33FJ128GIC33FJ64GIC33FJ32G 22223210 VAPPNGGCA1EEP2CD/R22//PTT1MD2IS(/1R/)R/PCP1N1011(1(41)//)CP/CMNN1D1605//P/RPMBMD1D221/R/RBB1101 OSOSCS2C/IC/RLPK4O(1/C)/CNN291//PPMMAB0E//RRAB34 1110 P202P202P302 1198 VTDSSO/SDA1/RP9(1)/CN21/PMD3/RB9 SOSCO/T1CK/CN0/PMA1/RA4 12 17 TCK/SCL1/RP8(1)/CN22/PMD4/RB8 VDD 13 16 INT0/RP7(1)/CN23/PMD5/RB7 PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 14 15 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 Note 1: The RPx pins can be used by any remappable peripheral. See Table1 in this section for the list of available peripherals. © 2007-2012 Microchip Technology Inc. DS70292G-page 3

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 28-Pin QFN-S(2) = Pins are up to 5V tolerant 4 1 B R R/ 15 W B M R P 1/ 2/ S 1 C N M C N11/P(1)P14/ C R -/CN3/RA1REF +/CN2/RA0REF (1)AC1LN/RP15/ DAC1LP/RTCC/ AN1/V AN0/VMCLR AVDD AVSSAN9/D AN10/ 8 7 65 4 3 2 2 2 22 2 2 2 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 1 21 AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 2 20 AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12 AN4/C1IN-/RP2(1)/CN6/RB2 3 dsPIC33FJ64GP802 19 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11 AN5/C1IN+/RP3(1)/CN7/RB3 4 dsPIC33FJ128GP802 18 PGED2/TDI/RP10(1)/CN16/PMD2/RB10 VSS 5 17 VCAP OSC1/CLKI/CN30/RA2 6 16 VSS OSC2/CLKO/CN29/PMA0/RA3 7 15 TDO/SDA1/RP9(1)/CN21/PMD3/RB9 8 9 1011 12 13 14 4 4 D 5 6 7 8 B A D B B B B R R V R R R R E/ 1/ 7/ 6/ 5/ 4/ B A D D D D M M M M M M P P P P P P 1/ 0/ 7/ 4/ 3/ 2/ N N 2 2 2 2 C C N N N N (1)CI/RP4/ CO/T1CK/ (1)1/RP5/C(1)1/RP6/C(1)0/RP7/C(1)1/RP8/C S S A L T L O O D C N C S S S S I S 3/A 3/A CK/ D C T E E G G P P Note 1: The RPx pins can be used by any remappable peripheral. See Table1 in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70292G-page 4 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 28-Pin QFN-S(2) = Pins are up to 5V tolerant 4 1 B R R/ 15 W B M CS1/R N12/P M C 11/P(1)4/ N 1 CN3/RA1 CN2/RA0 (1)N/RP15/C LP/RTCC/RP -/REF +/REF AC1L DAC1 AN1/V AN0/VMCLR AVDD AVSSAN9/D AN10/ 8 7 65 4 3 2 2 2 22 2 2 2 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 1 21 AN11/RP13(1)/CN13/PMRD/RB13 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 2 20 AN12/RP12(1)/CN14/PMD0/RB12 AN4/C1IN-/RP2(1)/CN6/RB2 3 dsPIC33FJ32GP302 19 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11 AN5/C1IN+/RP3(1)/CN7/RB3 4 dsPIC33FJ64GP202 18 PGED2/TDI/RP10(1)/CN16/PMD2/RB10 VSS 5 dsPIC33FJ128GP202 17 VCAP OSC1/CLKI/CN30/RA2 6 16 VSS OSC2/CLKO/CN29/PMA0/RA3 7 15 TDO/SDA1/RP9(1)/CN21/PMD3/RB9 8 9 1011 12 13 14 MBE/RB4 MA1/RA4 VDD MD7/RB5 MD6/RB6 MD5/RB7 MD4/RB8 (1)SOSCI/RP4/CN1/P SOSCO/T1CK/CN0/P (1)ASDA1/RP5/CN27/P(1)ASCL1/RP6/CN24/P(1)INT0/RP7/CN23/P(1)K/SCL1/RP8/CN22/P D3/ C3/ TC E E G G P P Note 1: The RPx pins can be used by any remappable peripheral. See Table1 in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. © 2007-2012 Microchip Technology Inc. DS70292G-page 5

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) = Pins are up to 5V tolerant 4 1 B R R/ 15W BM RP RB1RB0 CS1/N12/ (1)PGEC1/AN3/C2IN+/RP1/CN5/(1)PGED1/AN2/C2IN-/RP0/CN4/AN1/V-/CN3/RA1REFAN0/V+/CN2/RA0REFMCLRAVDDAVSS(1)AN9/DAC1LN/RP15/CN11/PM(1)AN10/DAC1LP/RTCC/RP14/CTCK/PMA7/RA7TMS/PMA10/RA10 AN4/C1IN-/RP2(1)/CN6/RB2 23 2221201918171615141312 11 AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13 AN5/C1IN+/RP3(1)/CN7/RB3 24 10 AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12 AN6/DAC1RM/RP16(1)/CN8/RC0 25 9 PGEC2/RP11(1)/CN15/PMD1/RB11 AN7/DAC1LM/RP17(1)/CN9/RC1 26 8 PGED2/RP10(1)/CN16/PMD2/RB10 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 27 7 VCAP dsPIC33FJ64GP804 VDD 28 6 VSS VSS 29 dsPIC33FJ128GP804 5 RP25(1)/CN19/PMA6/RC9 OSC1/CLKI/CN30/RA2 30 4 RP24(1)/CN20/PMA5/RC8 OSC2/CLKO/CN29/RA3 31 3 RP23(1)/CN17/PMA0/RC7 TDO/PMA8/RA8 32 2 RP22(1)/CN18/PMA1/RC6 SOSCI/RP4(1)/CN1/RB4 33 45678901234 1 SDA1/RP9(1)/CN21/PMD3/RB9 33333344444 49345SD5678 AACCCSDBBBB RRRRRVVRRRR 0/9/E/4/3/ 7/6/5/4/ NABAA DDDD CMMMM MMMM K/PPPP PPPP T1CTDI/N28/N25/N26/ N27/N24/N23/N22/ O/ CCC CCCC OSC (1)19/(1)20/(1)21/ (1)P5/(1)P6/(1)P7/(1)P8/ S PPP RRRR RRR 1/1/0/1/ ALTL DCNC SSIS AA 3/3/ DC EE GG PP Note 1: The RPx pins can be used by any remappable peripheral. See Table1 in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70292G-page 6 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) = Pins are up to 5V tolerant 4 1 B (1)C2IN+/RP1/CN5/RB1(1)C2IN-/RP0/CN4/RB0N3/RA1N2/RA0 CN11/PMCS1/RB15(1)RP14/CN12/PMWR/RA7RA10 PGEC1/AN3/PGED1/AN2/AN1/V-/CREFAN0/V+/CREFMCLRAVDDAVSS(1)AN9/RP15/AN10/RTCC/TCK/PMA7/RTMS/PMA10/ AN4/C1IN-/RP2(1)/CN6/RB2 23 2221201918171615141312 11 AN11/RP13(1)/CN13/PMRD/RB13 AN5/C1IN+/RP3(1)/CN7/RB3 24 10 AN12/RP12(1)/CN14/PMD0/RB12 AN6/RP16(1)/CN8/RC0 25 9 PGEC2/RP11(1)/CN15/PMD1/RB11 AN7/RP17(1)/CN9/RC1 26 8 PGED2/RP10(1)/CN16/PMD2/RB10 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 27 dsPIC33FJ32GP304 7 VCAP VDD 28 dsPIC33FJ64GP204 6 VSS VSS 29 dsPIC33FJ128GP204 5 RP25(1)/CN19/PMA6/RC9 OSC1/CLKI/CN30/RA2 30 4 RP24(1)/CN20/PMA5/RC8 OSC2/CLKO/CN29/RA3 31 3 RP23(1)/CN17/PMA0/RC7 TDO/PMA8/RA8 32 2 RP22(1)/CN18/PMA1/RC6 SOSCI/RP4(1)/CN1/RB4 33 45678901234 1 SDA1/RP9(1)/CN21/PMD3/RB9 33333344444 49345SD5678 AACCCSDBBBB RRRRRVVRRRR 0/9/E/4/3/ 7/6/5/4/ NABAA DDDD CMMMM MMMM K/PPPP PPPP T1CTDI/N28/N25/N26/ N27/N24/N23/N22/ O/ CCC CCCC OSC (1)19/(1)20/(1)21/ (1)P5/(1)P6/(1)P7/(1)P8/ S PPP RRRR RRR 1/1/0/1/ ALTL DCNC SSIS AA 3/3/ DC EE GG PP Note 1: The RPx pins can be used by any remappable peripheral. See Table1 in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. © 2007-2012 Microchip Technology Inc. DS70292G-page 7

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 44-Pin TQFP = Pins are up to 5V tolerant 4 1 B R R/ 15W BM RP RB1RB0 CS1/N12/ (1)PGEC1/AN3/C2IN+/RP1/CN5/(1)PGED1/AN2/C2IN-/RP0/CN4/AN1/V-/CN3/RA1REFAN0/V+/CN2/RA0REFMCLRAVDDAVSS(1)AN9/DAC1LN/RP15/CN11/PM(1)AN10/DAC1LP/RTCC/RP14/CTCK/PMA7/RA7TMS/PMA10/RA10 21098765432 AN4/C1IN-/RP2(1)/CN6/RB2 232221111111111 AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13 AN5/C1IN+/RP3(1)/CN7/RB3 24 10 AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12 AN6/DAC1RM/RP16(1)/CN8/RC0 25 9 PGEC2/RP11(1)/CN15/PMD1/RB11 AN7/DAC1LM/RP17/(1)/CN9/RC1 26 8 PGED2/EMCD2/RP10(1)/CN16/PMD2/RB10 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 27 dsPIC33FJ64GP804 7 VCAP VDD 28 6 VSS VSS 29 dsPIC33FJ128GP8045 RP25(1)/CN19/PMA6/RC9 OSC1/CLKI/CN30/RA2 30 4 RP24(1)/CN20/PMA5/RC8 OSC2/CLKO/CN29/RA3 31 3 RP23(1)/CN17/PMA0/RC7 TDO/PMA8/RA8 32 2 RP22(1)/CN18/PMA1/RC6 SOSCI/RP4(1)/CN1/RB4 33 1 SDA1/RP9(1)/CN21/PMD3/RB9 45678901234 33333344444 49345S D5678 AACCCS DBBBB RRRRRVVRRRR 0/9/E/4/3/ 7/6/5/4/ NABAA DDDD CMMMM MMMM K/PPPP PPPP T1CTDI/N28/N25/N26/ N27/N24/N23/N22/ O/ CCC CCCC OSC (1)19/(1)20/(1)21/ (1)P5/(1)P6/(1)P7/(1)P8/ S PPP RRRR RRR 1/1/0/1/ ALTL DCNC SSIS AA 3/3/ DC EE GG PP Note 1: The RPx pins can be used by any remappable peripheral. See Table1 in this section for the list of available peripherals. DS70292G-page 8 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 44-Pin TQFP = Pins are up to 5V tolerant 4 1 B (1)C2IN+/RP1/CN5/RB1(1)C2IN-/RP0/CN4/RB0N3/RA1N2/RA0 CN11/PMCS1/RB15(1)RP14/CN12/PMWR/RA7RA10 PGEC1/AN3/PGED1/AN2/AN1/V-/CREFAN0/V+/CREFMCLRAVDDAVSS(1)AN9/RP15/AN10/RTCC/TCK/PMA7/RTMS/PMA10/ 21098765432 AN4/C1IN-/RP2(1)/CN6/RB2 232221111111111 AN11/RP13(1)/CN13/PMRD/RB13 AN5/C1IN+/RP3(1)/CN7/RB3 24 10 AN12/RP12(1)/CN14/PMD0/RB12 AN6/RP16(1)/CN8/RC0 25 9 PGEC2/RP11(1)/CN15/PMD1/RB11 AN7/RP17(1)/CN9/RC1 26 8 PGED2/EMCD2/RP10(1)/CN16/PMD2/RB10 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 27 dsPIC33FJ32GP304 7 VCAP VDD 28 dsPIC33FJ64GP204 6 VSS VSS 29dsPIC33FJ128GP204 5 RP25(1)/CN19/PMA6/RC9 OSC1/CLKI/CN30/RA2 30 4 RP24(1)/CN20/PMA5/RC8 OSC2/CLKO/CN29/RA3 31 3 RP23(1)/CN17/PMA0/RC7 TDO/PMA8/RA8 32 2 RP22(1)/CN18/PMA1/RC6 SOSCI/RP4(1)/CN1/RB4 33 1 SDA1/RP9(1)/CN21/PMD3/RB9 45678901234 33333344444 49345S D5678 AACCCS DBBBB RRRRRVVRRRR 0/9/E/4/3/ 7/6/5/4/ NABAA DDDD CMMMM MMMM K/PPPP PPPP T1CTDI/N28/N25/N26/ N27/N24/N23/N22/ O/ CCC CCCC OSC (1)19/(1)20/(1)21/ (1)P5/(1)P6/(1)P7/(1)P8/ S PPP RRRR RRR 1/1/0/1/ ALTL DCNC SSIS AA 3/3/ DC EE GG PP Note 1: The RPx pins can be used by any remappable peripheral. See Table1 in this section for the list of available peripherals. © 2007-2012 Microchip Technology Inc. DS70292G-page 9

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Table of Contents dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Product Families.............................................2 1.0 Device Overview........................................................................................................................................................................13 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers..........................................................................................19 3.0 CPU............................................................................................................................................................................................23 4.0 Memory Organization.................................................................................................................................................................35 5.0 Flash Program Memory..............................................................................................................................................................71 6.0 Resets .......................................................................................................................................................................................77 7.0 Interrupt Controller.....................................................................................................................................................................87 8.0 Direct Memory Access (DMA)..................................................................................................................................................129 9.0 Oscillator Configuration............................................................................................................................................................141 10.0 Power-Saving Features............................................................................................................................................................153 11.0 I/O Ports...................................................................................................................................................................................159 12.0 Timer1......................................................................................................................................................................................189 13.0 Timer2/3 and Timer4/5 Feature ...............................................................................................................................................193 14.0 Input Capture............................................................................................................................................................................199 15.0 Output Compare.......................................................................................................................................................................203 16.0 Serial Peripheral Interface (SPI)...............................................................................................................................................207 17.0 Inter-Integrated Circuit™ (I2C™)..............................................................................................................................................213 18.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................221 19.0 Enhanced CAN (ECAN™) Module...........................................................................................................................................227 20.0 Data Converter Interface (DCI) Module....................................................................................................................................255 21.0 10-bit/12-bit Analog-to-Digital Converter (ADC).......................................................................................................................263 22.0 Audio Digital-to-Analog Converter (DAC).................................................................................................................................277 23.0 Comparator Module..................................................................................................................................................................283 24.0 Real-Time Clock and Calendar (RTCC) ..................................................................................................................................289 25.0 Programmable Cyclic Redundancy Check (CRC) Generator..................................................................................................301 26.0 Parallel Master Port (PMP).......................................................................................................................................................307 27.0 Special Features......................................................................................................................................................................315 28.0 Instruction Set Summary..........................................................................................................................................................325 29.0 Development Support...............................................................................................................................................................333 30.0 Electrical Characteristics..........................................................................................................................................................337 31.0 High Temperature Electrical Characteristics............................................................................................................................391 32.0 DC and AC Device Characteristics Graphs..............................................................................................................................403 33.0 Packaging Information..............................................................................................................................................................407 Appendix A: Revision History.............................................................................................................................................................417 Index..................................................................................................................................................................................................427 The Microchip Web Site.....................................................................................................................................................................431 Customer Change Notification Service..............................................................................................................................................431 Customer Support..............................................................................................................................................................................431 Reader Response..............................................................................................................................................................................432 Product Identification System.............................................................................................................................................................433 DS70292G-page 10 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007-2012 Microchip Technology Inc. DS70292G-page 11

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33F/PIC24H Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note1: To access the documents listed below, browse to the documentation section of the dsPIC33FJ64GP804 product page of the Microchip web site (www.microchip.com) or select a family reference manual section from the following list. In addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections. • Section 1. “Introduction” (DS70197) • Section 2. “CPU” (DS70204) • Section 3. “Data Memory” (DS70202) • Section 4. “Program Memory” (DS70203) • Section 5. “Flash Programming” (DS70191) • Section 8. “Reset” (DS70192) • Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196) • Section 11. “Timers” (DS70205) • Section 12. “Input Capture” (DS70198) • Section 13. “Output Compare” (DS70209) • Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) • Section 17. “UART” (DS70188) • Section 18. “Serial Peripheral Interface (SPI)” (DS70206) • Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195) • Section 23. “CodeGuard™ Security” (DS70199) • Section 24. “Programming and Diagnostics” (DS70207) • Section 25. “Device Configuration” (DS70194) • Section 30. “I/O Ports with Peripheral Pin Select (PPS)” (DS70190) • Section 32. “Interrupts (Part III)” (DS70214) • Section 33. “Audio Digital-to-Analog Converter (DAC)” (DS70211) • Section 34. “Comparator” (DS70212) • Section 35. “Parallel Master Port (PMP)” (DS70299) • Section 36. “Programmable Cyclic Redundancy Check (CRC)” (DS70298) • Section 37. “Real-Time Clock and Calendar (RTCC)” (DS70301) • Section 38. “Direct Memory Access (DMA) (Part III)” (DS70215) • Section 39. “Oscillator (Part III)” (DS70216) DS70292G-page 12 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 1.0 DEVICE OVERVIEW This document contains device specific information for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ Note1: This data sheet summarizes the features X04, and dsPIC33FJ128GPX02/X04 Digital Signal of the dsPIC33FJ32GP302/304, Controller (DSC) Devices. The dsPIC33F devices dsPIC33FJ64GPX02/X04, and contain extensive Digital Signal Processor (DSP) dsPIC33FJ128GPX02/X04 families of functionality with a high performance 16-bit devices. It is not intended to be a compre- microcontroller (MCU) architecture. hensive reference source. To comple- Figure1-1 shows a general block diagram of the ment the information in this data sheet, core and peripheral modules in the refer to the “dsPIC33F/PIC24H Family dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, Reference Manual”. Please see the and dsPIC33FJ128GPX02/X04 families of devices. Microchip web site (www.microchip.com) Table1-1 lists the functions of the various pins for the latest dsPIC33F/PIC24H Family shown in the pinout diagrams. Reference Manual sections. 2: Some registers and associated bits described in this section may not be avail- able on all devices. Refer to Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. © 2007-2012 Microchip Technology Inc. DS70292G-page 13

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 1-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus Interrupt X Data Bus PORTA Controller 16 8 16 16 16 DMA RAM Data Latch Data Latch 23 PORT B PCU PCH PCL X RAM Y RAM 23 Program Counter Stack Loop Address Address Control Control Latch Latch 16 Logic Logic DMA 23 Controller 16 16 PORTC Address Generator Units Address Latch Remappable Program Memory Pins EA MUX Data Latch ROM Latch 24 16 16 a at Instruction D Decode and al Control Instruction Reg er Lit 16 Control Signals to Various Blocks DSP Engine 16 x 16 OSC2/CLKO Timing Power-up W Register Array OSC1/CLKI Generation Timer Divide Support 16 Oscillator FRC/LPRC Start-up Timer Oscillators Power-on Reset 16-bit ALU Precision Band Gap Watchdog Reference Timer 16 Brown-out Voltage Reset Regulator VCAP VDD, VSS MCLR PMP/ Comparator ECAN1 Timers UART1, 2 ADC1 OC/ EPSP 2 Ch. 1-5 PWM1-4 RTCC DAC1 SPI1, 2 IC1, 2, 7, 8 CNx I2C1 DCI Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. DS70292G-page 14 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name PPS Description Type Type AN0-AN12 I Analog Analog input channels. CLKI I ST/CMOS No External clock source input. Always associated with OSC1 pin function. CLKO O — No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. OSC1 I ST/CMOS No Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. OSC2 I/O — No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. SOSCI I ST/CMOS No 32.768 kHz low-power oscillator crystal input; CMOS otherwise. SOSCO O — No 32.768 kHz low-power oscillator crystal output. CN0-CN30 I ST No Change notification inputs. No Can be software programmed for internal weak pull-ups on all inputs. IC1-IC2 I ST Yes Capture inputs 1/2. IC7-IC8 I ST Yes Capture inputs 7/8. OCFA I ST Yes Compare Fault A input (for Compare Channels 1, 2, 3 and 4). OC1-OC4 O — Yes Compare outputs 1 through 4. INT0 I ST No External interrupt 0. INT1 I ST Yes External interrupt 1. INT2 I ST Yes External interrupt 2. RA0-RA4 I/O ST No PORTA is a bidirectional I/O port. RA7-RA10 I/O ST No PORTA is a bidirectional I/O port. RB0-RB15 I/O ST No PORTB is a bidirectional I/O port. RC0-RC9 I/O ST No PORTC is a bidirectional I/O port. T1CK I ST No Timer1 external clock input. T2CK I ST Yes Timer2 external clock input. T3CK I ST Yes Timer3 external clock input. T4CK I ST Yes Timer4 external clock input. T5CK I ST Yes Timer5 external clock input. U1CTS I ST Yes UART1 clear to send. O — Yes UART1 ready to send. U1RTS I ST Yes UART1 receive. U1RX O — Yes UART1 transmit. U1TX U2CTS I ST Yes UART2 clear to send. O — Yes UART2 ready to send. U2RTS I ST Yes UART2 receive. U2RX O — Yes UART2 transmit. U2TX SCK1 I/O ST Yes Synchronous serial clock input/output for SPI1. SDI1 I ST Yes SPI1 data in. SDO1 O — Yes SPI1 data out. SS1 I/O ST Yes SPI1 slave synchronization or frame pulse I/O. SCK2 I/O ST Yes Synchronous serial clock input/output for SPI2. SDI2 I ST Yes SPI2 data in. SDO2 O — Yes SPI2 data out. SS2 I/O ST Yes SPI2 slave synchronization or frame pulse I/O. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select © 2007-2012 Microchip Technology Inc. DS70292G-page 15

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name PPS Description Type Type SCL1 I/O ST No Synchronous serial clock input/output for I2C1. SDA1 I/O ST No Synchronous serial data input/output for I2C1. ASCL1 I/O ST No Alternate synchronous serial clock input/output for I2C1. ASDA1 I/O ST No Alternate synchronous serial data input/output for I2C1. TMS I ST No JTAG Test mode select pin. TCK I ST No JTAG test clock input pin. TDI I ST No JTAG test data input pin. TDO O — No JTAG test data output pin. C1RX I ST Yes ECAN1 bus receive pin. C1TX O — Yes ECAN1 bus transmit pin. RTCC O — No Real-Time Clock Alarm Output. CVREF O ANA No Comparator Voltage Reference Output. C1IN- I ANA No Comparator 1 Negative Input. C1IN+ I ANA No Comparator 1 Positive Input. C1OUT O — Yes Comparator 1 Output. C2IN- I ANA No Comparator 2 Negative Input. C2IN+ I ANA No Comparator 2 Positive Input. C2OUT O — Yes Comparator 2 Output. PMA0 I/O TTL/ST No Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). PMA1 I/O TTL/ST No Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). PMA2 -PMPA10 O — No Parallel Master Port Address (Demultiplexed Master Modes). PMBE O — No Parallel Master Port Byte Enable Strobe. PMCS1 O — No Parallel Master Port Chip Select 1 Strobe. PMD0-PMPD7 I/O TTL/ST No Parallel Master Port Data (Demultiplexed Master mode) or Address/ Data (Multiplexed Master modes). PMRD O — No Parallel Master Port Read Strobe. PMWR O — No Parallel Master Port Write Strobe. DAC1RN O — No DAC1 Right Channel Negative Output. DAC1RP O — No DAC1 Right Channel Positive Output. DAC1RM O — No DAC1 Right Channel Middle Point Value (typically 1.65V). DAC1LN O — No DAC1 Left Channel Negative Output. DAC1LP O — No DAC1 Left Channel Positive Output. DAC1LM O — No DAC1 Left Channel Middle Point Value (typically 1.65V). COFS I/O ST Yes Data Converter Interface frame synchronization pin. CSCK I/O ST Yes Data Converter Interface serial clock input/output pin. CSDI I ST Yes Data Converter Interface serial data input pin CSDO O — Yes Data Converter Interface serial data output pin. PGED1 I/O ST No Data I/O pin for programming/debugging communication channel 1. PGEC1 I ST No Clock input pin for programming/debugging communication channel 1. PGED2 I/O ST No Data I/O pin for programming/debugging communication channel 2. PGEC2 I ST No Clock input pin for programming/debugging communication channel 2. PGED3 I/O ST No Data I/O pin for programming/debugging communication channel 3. PGEC3 I ST No Clock input pin for programming/debugging communication channel 3. MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device. AVDD P P No Positive supply for analog modules. This pin must be connected at all times. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select DS70292G-page 16 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name PPS Description Type Type AVSS P P No Ground reference for analog modules. VDD P — No Positive supply for peripheral logic and I/O pins. VCAP P — No CPU logic filter capacitor connection. Vss P — No Ground reference for logic and I/O pins. VREF+ I Analog No Analog voltage reference (high) input. VREF- I Analog No Analog voltage reference (low) input. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select © 2007-2012 Microchip Technology Inc. DS70292G-page 17

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 18 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors STARTED WITH 16-BIT The use of decoupling capacitors on every pair of DIGITAL SIGNAL power supply pins, such as VDD, VSS, AVDD and CONTROLLERS AVSS is required. Consider the following criteria when using decoupling Note1: This data sheet summarizes the features capacitors: of the dsPIC33FJ32GP302/304, • Value and type of capacitor: Recommendation dsPIC33FJ64GPX02/X04, and of 0.1 µF (100 nF), 10-20V. This capacitor should dsPIC33FJ128GPX02/X04 family of be a low-ESR and have resonance frequency in devices. It is not intended to be a the range of 20MHz and higher. It is comprehensive reference source. To recommended that ceramic capacitors be used. complement the information in this data sheet, refer to the “dsPIC33F/PIC24H • Placement on the printed circuit board: The Family Reference Manual”, which is decoupling capacitors should be placed as close available from the Microchip website to the pins as possible. It is recommended to (www.microchip.com). place the capacitors on the same side of the board as the device. If space is constricted, the 2: Some registers and associated bits capacitor can be placed on another layer on the described in this section may not be avail- PCB using a via; however, ensure that the trace able on all devices. Refer to Section4.0 length from the pin to the capacitor is within “Memory Organization” in this data one-quarter inch (6mm) in length. sheet for device-specific register and bit • Handling high frequency noise: If the board is information. experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor 2.1 Basic Connection Requirements in parallel to the above described decoupling capacitor. The value of the second capacitor can Getting started with the dsPIC33FJ32GP302/304, be in the range of 0.01µF to 0.001µF. Place this dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ second capacitor next to the primary decoupling X04 family of 16-bit Digital Signal Controllers (DSCs) capacitor. In high-speed circuit designs, consider requires attention to a minimal set of device pin implementing a decade pair of capacitances as connections before proceeding with development. The close to the power and ground pins as possible. following is a list of pin names, which must always be For example, 0.1 µF in parallel with 0.001 µF. connected: • Maximizing performance: On the board layout • All VDD and VSS pins from the power supply circuit, run the power and (see Section2.2 “Decoupling Capacitors”) return traces to the decoupling capacitors first, • All AVDD and AVSS pins (regardless if ADC module and then to the device pins. This ensures that the is not used) decoupling capacitors are first in the power chain. (see Section2.2 “Decoupling Capacitors”) Equally important is to keep the trace length • VCAP between the capacitor and the power pins to a (see Section2.3 “CPU Logic Filter Capacitor minimum thereby reducing PCB track inductance. Connection (VCAP)”) • MCLR pin (see Section2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section2.6 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of the ADC voltage reference source. © 2007-2012 Microchip Technology Inc. DS70292G-page 19

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 2-1: RECOMMENDED The placement of this capacitor should be close to the MINIMUM CONNECTION VCAP. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section27.2 0.1 µF “On-Chip Voltage Regulator” for details. VDD 10 µF Ceramic Tantalum 2.4 Master Clear (MCLR) Pin R CAP VDD VSS The MCLR pin provides for two specific device R1 V functions: MCLR • Device Reset C • Device programming and debugging dsPIC33F During device programming and debugging, the VSS VDD resistance and capacitance that can be added to the pin must be considered. Device programmers and 0.1 µF VDD D S VSS 0.1 µF debuggers drive the MCLR pin. Consequently, Ceramic VD VS DD SS Ceramic specific voltage levels (VIH and VIL) and fast signal A A V V transitions must not be adversely affected. Therefore, 0.1 µF 0.1 µF specific values of R and C will need to be adjusted Ceramic Ceramic based on the application and PCB requirements. L1(1) For example, as shown in Figure2-2, it is recommended that the capacitor C, be isolated from Note 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and the MCLR pin during programming and debugging AVDD to improve ADC noise rejection. The inductor operations. impedance should be less than 1Ω and the inductor capacity greater than 10 mA. Place the components shown in Figure2-2 within one-quarter inch (6mm) from the MCLR pin. Where: FCNV f = -------------- (i.e., ADC conversion rate/2) FIGURE 2-2: EXAMPLE OF MCLR PIN 2 CONNECTIONS 1 f = ----------------------- (2π LC) VDD ⎛ 1 ⎞2 L = ⎝---------------------⎠ (2πf C) R(1) R1(2) MCLR 2.2.1 TANK CAPACITORS JP dsPIC33F On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor C for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that con- Note 1: R≤ 10kΩ is recommended. A suggested nects the power supply source to the device, and the starting value is 10kΩ. Ensure that the MCLR maximum current drawn by the device in the applica- pin VIH and VIL specifications are met. tion. In other words, select the tank capacitor so that it 2: R1≤ 470Ω will limit any current flowing into meets the acceptable voltage sag at the device. Typical MCLR from the external capacitor C, in the values range from 4.7µF to 47µF. event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical 2.3 CPU Logic Filter Capacitor Overstress (EOS). Ensure that the MCLR pin Connection (VCAP) VIH and VIL specifications are met. A low-ESR (< 5 Ohms) capacitor is required on the VCAP pin, which is used to stabilize the voltage regulator output voltage. The VCAP pin must not be connected to VDD, and must have a capacitor between 4.7µF and 10 µF, preferably surface mount connected within one-eights inch of the VCAP pin connected to ground. The type can be ceramic or tantalum. Refer to Section30.0 “Electrical Characteristics” for additional information. DS70292G-page 20 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2.5 ICSP Pins 2.6 External Oscillator Pins The PGECx and PGEDx pins are used for In-Circuit Many DSCs have options for at least two oscillators: a Serial Programming™ (ICSP™) and debugging pur- high-frequency primary oscillator and a low-frequency poses. It is recommended to keep the trace length secondary oscillator (refer to Section9.0 “Oscillator between the ICSP connector and the ICSP pins on the Configuration” for details). device as short as possible. If the ICSP connector is The oscillator circuit should be placed on the same expected to experience an ESD event, a series resistor side of the board as the device. Also, place the is recommended, with the value in the range of a few oscillator circuit close to the respective oscillator pins, tens of Ohms, not to exceed 100 Ohms. not exceeding one-half inch (12mm) distance Pull-up resistors, series diodes, and capacitors on the between them. The load capacitors should be placed PGECx and PGEDx pins are not recommended as they next to the oscillator itself, on the same side of the will interfere with the programmer/debugger communi- board. Use a grounded copper pour around the cations to the device. If such discrete components are oscillator circuit to isolate them from surrounding an application requirement, they should be removed circuits. The grounded copper pour should be routed from the circuit during programming and debugging. directly to the MCU ground. Do not run any signal Alternatively, refer to the AC/DC characteristics and traces or power traces inside the ground pour. Also, if timing requirements information in the respective using a two-sided board, avoid any traces on the device Flash programming specification for information other side of the board where the crystal is placed. A on capacitive loading limits and pin input voltage high suggested layout is shown in Figure2-3. (VIH) and input low (VIL) requirements. Recommendations for crystals and ceramic resonators are provided in Table2-1 and Table2-2, Ensure that the “Communication Channel Select” (i.e., respectively. PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 3 or MPLAB REAL ICE™. FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR For more information on ICD 3 and REAL ICE CIRCUIT connection requirements, refer to the following documents that are available on the Microchip website. • “Using MPLAB® ICD 3 In-Circuit Debugger” Main Oscillator (poster) DS51765 13 • “MPLAB® ICD 3 Design Advisory” DS51764 Guard Ring 14 • “MPLAB® REAL ICE™ In-Circuit Emulator User’s 15 Guide” DS51616 Guard Trace 16 • “Using MPLAB® REAL ICE™” (poster) DS51749 Secondary 17 Oscillator 18 19 20 TABLE 2-1: CRYSTAL RECOMMENDATIONS Part Load Package Frequency Mounting Operating Vendor Freq. Number Cap. Case Tolerance Type Temperature ECS-40-20-4DN ECS Inc. 4 MHz 20 pF HC49/US ±30 ppm TH -40°C to +85°C ECS-80-18-4DN ECS Inc. 8 MHz 18 pF HC49/US ±30 ppm TH -40°C to +85°C ECS-100-18-4-DN ECS Inc. 10 MHz 18 pF HC49/US ±30 ppm TH -40°C to +85°C ECS-200-20-4DN ECS Inc. 20 MHz 20 pF HC49/US ±30 ppm TH -40°C to +85°C ECS-40-20-5G3XDS-TR ECS Inc. 4 MHz 20 pF HC49/US ±30 ppm SM -40°C to +125°C ECS-80-20-5G3XDS-TR ECS Inc. 8 MHz 20 pF HC49/US ±30 ppm SM -40°C to +125°C ECS-100-20-5G3XDS-TR ECS Inc. 10 MHz 20 pF HC49/US ±30 ppm SM -40°C to +125°C ECS-200-20-5G3XDS-TR ECS Inc. 20 MHz 20 pF HC49/US ±30 ppm SM -40°C to 125°C NX3225SA 20MHZ AT-W NDK 20 MHz 8 pF 3.2 mm x 2.5 mm ±50 ppm SM -40°C to 125°C Legend: TH = Through Hole SM = Surface Mount © 2007-2012 Microchip Technology Inc. DS70292G-page 21

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 2-2: RESONATOR RECOMMENDATIONS Part Load Package Frequency Mounting Operating Vendor Freq. Number Cap. Case Tolerance Type Temperature FCR4.0M5T TDK Corp. 4 MHz N/A Radial ±0.5% TH -40°C to +85°C FCR8.0M5 TDK Corp. 8 MHz N/A Radial ±0.5% TH -40°C to +85°C HWZT-10.00MD TDK Corp. 10 MHz N/A Radial ±0.5% TH -40°C to +85°C HWZT-20.00MD TDK Corp. 20 MHz N/A Radial ±0.5% TH -40°C to +85°C Legend: TH = Through Hole 2.7 Oscillator Value Conditions on 2.9 Unused I/Os Device Start-up Unused I/O pins should be configured as outputs and If the PLL of the target device is enabled and driven to a logic-low state. configured for the device start-up oscillator, the Alternatively, connect a 1k to 10k resistor between VSS maximum oscillator source frequency must be limited and the unused pin. to ≤8 MHz for start-up with the PLL enabled to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed. Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration word. 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 3 or REAL ICE is selected as a debug- ger, it automatically initializes all of the analog-to-digital input pins (ANx) as “digital” pins, by setting all bits in the AD1PCFGL register. The bits in this register that correspond to the analog-to-digital pins that are initialized by MPLAB ICD 3 or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain analog-to-digital pins as analog input pins during the debug session, the user application must clear the corresponding bits in the AD1PCFGL register during initialization of the ADC module. When MPLAB ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the AD1PCFGL register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all analog-to-digital pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. DS70292G-page 22 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.0 CPU a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be Note1: This data sheet summarizes the features supported, allowing A + B = C operations to be of the dsPIC33FJ32GP302/304, executed in a single cycle. dsPIC33FJ64GPX02/X04, and A block diagram of the CPU is shown in Figure3-1, and dsPIC33FJ128GPX02/X04 families of the programmer’s model for the dsPIC33FJ32GP302/ devices. It is not intended to be a compre- 304, dsPIC33FJ64GPX02/X04, and hensive reference source. To comple- dsPIC33FJ128GPX02/X04 is shown in Figure3-2. ment the information in this data sheet, refer to Section 2. “CPU” (DS70204) of 3.2 Data Addressing Overview the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the The data space can be addressed as 32K words or Microchip website (www.microchip.com). 64Kbytes and is split into two blocks, referred to as X 2: Some registers and associated bits and Y data memory. Each memory block has its own described in this section may not be avail- independent Address Generation Unit (AGU). The able on all devices. Refer to Section4.0 MCU class of instructions operates solely through the “Memory Organization” in this data X memory AGU, which accesses the entire memory sheet for device-specific register and bit map as one linear data space. Certain DSP instructions information. operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is 3.1 Overview device-specific. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ Overhead-free circular buffers (Modulo Addressing X04, and dsPIC33FJ128GPX02/X04 CPU module has mode) are supported in both X and Y address spaces. a 16-bit (data) modified Harvard architecture with an The Modulo Addressing removes the software enhanced instruction set, including significant support boundary checking overhead for DSP algorithms. for DSP. The CPU has a 24-bit instruction word with a Furthermore, the X AGU circular addressing can be variable length opcode field. The Program Counter used with any of the MCU class of instructions. The X (PC) is 23bits wide and addresses up to 4M x 24 bits AGU also supports Bit-Reversed Addressing to greatly of user program memory space. The actual amount of simplify input or output data reordering for radix-2 FFT program memory implemented varies by device. A algorithms. single-cycle instruction prefetch mechanism is used to The upper 32 Kbytes of the data space memory map help maintain throughput and provides predictable can optionally be mapped into program space at any execution. All instructions execute in a single cycle, 16K program word boundary defined by the 8-bit with the exception of instructions that change the Program Space Visibility Page (PSVPAG) register. The program flow, the double-word move (MOV.D) program-to-data-space mapping feature lets any instruction and the table instructions. Overhead-free instruction access program space as if it were data program loop constructs are supported using the DO space. and REPEAT instructions, both of which are interruptible at any time. 3.3 DSP Engine Overview The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices have The DSP engine features a high-speed 17-bit by 17-bit sixteen, 16-bit working registers in the programmer’s multiplier, a 40-bit ALU, two 40-bit saturating model. Each of the working registers can serve as a accumulators and a 40-bit bidirectional barrel shifter. data, address or address offset register. The 16th The barrel shifter is capable of shifting a 40-bit value up working register (W15) operates as a software Stack to 16 bits right or left, in a single cycle. The DSP Pointer (SP) for interrupts and calls. instructions operate seamlessly with all other instructions and have been designed for optimal real- There are two classes of instruction in the time performance. The MAC instruction and other dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, associated instructions can concurrently fetch two data and dsPIC33FJ128GPX02/X04 devices: MCU and operands from memory while multiplying two W DSP. These two instruction classes are seamlessly registers and accumulating and optionally saturating integrated into a single CPU. The instruction set the result in the same cycle. This instruction includes many addressing modes and is designed for functionality requires that the RAM data space be split optimum C compiler efficiency. For most instructions, for these instructions and linear for all others. Data the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ space partitioning is achieved in a transparent and X04, and dsPIC33FJ128GPX02/X04 is capable of flexible manner through dedicating certain working executing a data (or program data) memory read, a registers to each address space. working register (data) read, a data memory write and © 2007-2012 Microchip Technology Inc. DS70292G-page 23

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.4 Special MCU Features The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 supports 16/16 The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ and 32/16 divide operations, both fractional and inte- X04, and dsPIC33FJ128GPX02/X04 features a 17-bit ger. All divide instructions are iterative operations. They by 17-bit single-cycle multiplier that is shared by both must be executed within a REPEAT loop, resulting in a the MCU ALU and DSP engine. The multiplier can per- total execution time of 19 instruction cycles. The divide form signed, unsigned and mixed-sign multiplication. operation can be interrupted during any of those Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit 19cycles without loss of data. multiplication not only allows you to perform mixed-sign A 40-bit barrel shifter is used to perform up to a 16-bit multiplication, it also achieves accurate results for left or right shift in a single cycle. The barrel shifter can special operations, such as (-1.0) x (-1.0). be used by both MCU and DSP instructions. FIGURE 3-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus Interrupt X Data Bus Controller 8 16 16 16 16 Data Latch Data Latch 23 DMA 23 PCU PCH PCL X RAM Y RAM RAM 16 Program Counter Stack Loop Address Address Control Control Latch Latch Logic Logic 23 16 16 DMA Address Latch Address Generator Units Controller Program Memory EA MUX Data Latch ROM Latch 24 16 16 a at D Instruction al Decode and er Control Instruction Reg Lit 16 Control Signals to Various Blocks DSP Engine 16 x 16 W Register Array Divide Support 16 16-bit ALU 16 To Peripheral Modules DS70292G-page 24 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 3-2: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 DSP Operand W5 Registers W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register AD39 AD31 AD15 AD0 DSP ACCA Accumulators ACCB PC22 PC0 0 Program Counter 7 0 TBLPAG Data Table Page Address 7 0 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address 22 DOEND DO Loop End Address 15 0 CORCON Core Configuration Register OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRH SRL © 2007-2012 Microchip Technology Inc. DS70292G-page 25

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.5 CPU Resources Many useful resources are provided on the main prod- uct page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 3.5.1 KEY RESOURCES • Section 2. “CPU” (DS70204) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70292G-page 26 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.6 CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA(1) SB(1) OAB SAB(4) DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL<2:0>(2) RA N OV Z C bit 7 bit 0 Legend: C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OA: Accumulator A Overflow Status bit 1 = Accumulator A overflowed 0 = Accumulator A has not overflowed bit 14 OB: Accumulator B Overflow Status bit 1 = Accumulator B overflowed 0 = Accumulator B has not overflowed bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed bit 10 SAB: SA || SB Combined Accumulator (Sticky) Status bit(4) 1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated bit 9 DA: DO Loop Active bit 1 = DO loop in progress 0 = DO loop not in progress bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred Note 1: This bit can be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read only when the NSTDIS bit (INTCON1<15>) = 1. 4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB. © 2007-2012 Microchip Technology Inc. DS70292G-page 27

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: MCU ALU Overflow bit This bit is used for signed arithmetic (two’s complement). It indicates an overflow of a magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 1 Z: MCU ALU Zero bit 1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: This bit can be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read only when the NSTDIS bit (INTCON1<15>) = 1. 4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB. DS70292G-page 28 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT(1) DL<2:0> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 15-13 Unimplemented: Read as ‘0’ bit 12 US: DSP Multiply Unsigned/Signed Control bit 1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed bit 11 EDT: Early DO Loop Termination Control bit(1) 1 = Terminate executing DO loop at end of current loop iteration 0 = No effect bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits 111 = 7 DO loops active • • • 001 = 1 DO loop active 000 = 0 DO loops active bit 7 SATA: ACCA Saturation Enable bit 1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled bit 6 SATB: ACCB Saturation Enable bit 1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation enabled 0 = Data space write saturation disabled bit 4 ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space bit 1 RND: Rounding Mode Select bit 1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled bit 0 IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Note 1: This bit is always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2007-2012 Microchip Technology Inc. DS70292G-page 29

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.7 Arithmetic Logic Unit (ALU) 3.8 DSP Engine The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ The DSP engine consists of a high-speed 17-bit x X04, and dsPIC33FJ128GPX02/X04 ALU is 16 bits 17-bit multiplier, a barrel shifter and a 40-bit adder/ wide and is capable of addition, subtraction, bit shifts subtracter (with two target accumulators, round and and logic operations. Unless otherwise mentioned, saturation logic). arithmetic operations are two’s complement in nature. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ Depending on the operation, the ALU can affect the X04, and dsPIC33FJ128GPX02/X04 is a single-cycle values of the Carry (C), Zero (Z), Negative (N), instruction flow architecture; therefore, concurrent Overflow (OV) and Digit Carry (DC) Status bits in the operation of the DSP engine with MCU instruction flow SR register. The C and DC Status bits operate as is not possible. However, some MCU ALU and DSP Borrow and Digit Borrow bits, respectively, for engine resources can be used concurrently by the subtraction operations. same instruction (e.g., ED, EDAC). The ALU can perform 8-bit or 16-bit operations, The DSP engine can also perform inherent accumula- depending on the mode of the instruction that is used. tor-to-accumulator operations that require no additional Data for the ALU operation can come from the W data. These instructions are ADD, SUB and NEG. register array or data memory, depending on the addressing mode of the instruction. Likewise, output The DSP engine has options selected through bits in data from the ALU can be written to the W register array the CPU Core Control register (CORCON), as listed or a data memory location. below: Refer to the “16-bit MCU and DSC Programmer’s Ref- • Fractional or integer DSP multiply (IF) erence Manual” (DS70157) for information on the SR • Signed or unsigned DSP multiply (US) bits affected by each instruction. • Conventional or convergent rounding (RND) • Automatic saturation on/off for ACCA (SATA) The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ • Automatic saturation on/off for ACCB (SATB) X04, and dsPIC33FJ128GPX02/X04 CPU incorpo- • Automatic saturation on/off for writes to data rates hardware support for both multiplication and divi- memory (SATDW) sion. This includes a dedicated hardware multiplier and • Accumulator Saturation mode selection (ACC- support hardware for 16-bit-divisor division. SAT) 3.7.1 MULTIPLIER A block diagram of the DSP engine is shown in Figure3-3. Using the high-speed 17-bit x 17-bit multiplier of the DSP engine, the ALU supports unsigned, signed or TABLE 3-1: DSP INSTRUCTIONS mixed-sign operation in several MCU multiplication SUMMARY modes: • 16-bit x 16-bit signed Algebraic ACC Write Instruction • 16-bit x 16-bit unsigned Operation Back • 16-bit signed x 5-bit (literal) unsigned CLR A = 0 Yes • 16-bit unsigned x 16-bit unsigned ED A = (x – y)2 No • 16-bit unsigned x 5-bit (literal) unsigned • 16-bit unsigned x 16-bit signed EDAC A = A + (x – y)2 No • 8-bit unsigned x 8-bit unsigned MAC A = A + (x•y) Yes MAC A = A + x2 No 3.7.2 DIVIDER MOVSAC No change in A Yes The divide block supports 32-bit/16-bit and 16-bit/16-bit MPY A = x•y No signed and unsigned integer divide operations with the MPY A = x 2 No following data sizes: MPY.N A = – x•y No 1. 32-bit signed/16-bit signed divide MSC A = A – x•y Yes 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. DS70292G-page 30 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM S 40 40-bit Accumulator A a 40 Round t 16 40-bit Accumulator B u Logic r Carry/Borrow Out a Saturate t e Adder Carry/Borrow In Negate 40 40 40 Barrel 16 Shifter 40 us B a at D Sign-Extend X s u B a 32 16 at Zero Backfill D Y 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array © 2007-2012 Microchip Technology Inc. DS70292G-page 31

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.8.1 MULTIPLIER The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in The 17-bit x 17-bit multiplier is capable of signed or the STATUS register: unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit • Overflow from bit 39: this is a catastrophic integer results. Unsigned operands are zero-extended overflow in which the sign of the accumulator is into the 17th bit of the multiplier input value. Signed destroyed. operands are sign-extended into the 17th bit of the • Overflow into guard bits 32 through 39: this is a multiplier input value. The output of the 17-bit x 17-bit recoverable overflow. This bit is set whenever all multiplier/scaler is a 33-bit value that is sign-extended the guard bits are not identical to each other. to 40 bits. Integer data is inherently represented as a The adder has an additional saturation block that signed two’s complement value, where the Most controls accumulator data saturation, if selected. It Significant bit (MSb) is defined as a sign bit. The range uses the result of the adder, the Overflow Status bits of an N-bit two’s complement integer is -2N-1 to 2N-1 – 1. described previously and the SAT<A:B> • For a 16-bit integer, the data range is -32768 (CORCON<7:6>) and ACCSAT (CORCON<4>) mode (0x8000) to 32767 (0x7FFF) including 0. control bits to determine when and to what value to • For a 32-bit integer, the data range is - saturate. 2,147,483,648 (0x80000000) to 2,147,483,647 Six STATUS register bits support saturation and (0x7FFF FFFF). overflow: When the multiplier is configured for fractional • OA: ACCA overflowed into guard bits multiplication, the data is represented as a two’s • OB: ACCB overflowed into guard bits complement fraction, where the MSb is defined as a • SA: ACCA saturated (bit 31 overflow and sign bit and the radix point is implied to lie just after the saturation) sign bit (QX format). The range of an N-bit two’s or complement fraction with this implied radix point is -1.0 to (1 – 21-N). For a 16-bit fraction, the Q15 data range ACCA overflowed into guard bits and saturated (bit 39 overflow and saturation) is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0 and has a precision of 3.01518x10-5. In Fractional • SB: ACCB saturated (bit 31 overflow and mode, the 16 x 16 multiply operation generates a 1.31 saturation) product that has a precision of 4.65661 x 10-10. or ACCB overflowed into guard bits and saturated The same multiplier is used to support the MCU (bit 39 overflow and saturation) multiply instructions, which include integer 16-bit • OAB: Logical OR of OA and OB signed, unsigned and mixed sign multiply operations. • SAB: Logical OR of SA and SB The MUL instruction can be directed to use byte or word-sized operands. Byte operands direct a 16-bit The OA and OB bits are modified each time data result, and word operands direct a 32-bit result to the passes through the adder/subtracter. When set, they specified registers in the W array. indicate that the most recent operation has overflowed into the accumulator guard bits(bits 32 through 39). 3.8.2 DATA ACCUMULATORS AND The OA and OB bits can also optionally generate an ADDER/SUBTRACTER arithmetic warning trap when set and the corresponding Overflow Trap Flag Enable bits (OVATE, The data accumulator consists of a 40-bit adder/ OVBTE) in the INTCON1 register are set (refer to subtracter with automatic sign extension logic. It can Section7.0 “Interrupt Controller”). This allows the select one of two accumulators (A or B) as its pre- user application to take immediate action, for example, accumulation source and post-accumulation to correct the system gain. destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled The SA and SB bits are modified each time data using the barrel shifter prior to accumulation. passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate 3.8.2.1 Adder/Subtracter, Overflow and that the accumulator has overflowed its maximum Saturation range (bit 31 for 32-bit saturation or bit 39 for 40-bit sat- uration) and is saturated (if saturation is enabled). The adder/subtracter is a 40-bit adder with an optional When saturation is not enabled, SA and SB default to zero input into one side, and either true or complement bit 39 overflow and thus indicate that a catastrophic data into the other input. overflow has occurred. If the COVTE bit in the • In the case of addition, the Carry/Borrow input is INTCON1 register is set, the SA and SB bits generate active-high and the other input is true data (not an arithmetic warning trap when saturation is disabled. complemented). • In the case of subtraction, the Carry/Borrow input is active-low and the other input is complemented. DS70292G-page 32 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 The Overflow and Saturation Status bits can 3.8.3.1 Round Logic optionally be viewed in the STATUS Register (SR) as The round logic is a combinational block that performs the logical OR of OA and OB (in bit OAB) and the a conventional (biased) or convergent (unbiased) logical OR of SA and SB (in bit SAB). Programmers round function during an accumulator write (store). The can check one bit in the STATUS register to Round mode is determined by the state of the RND bit determine if either accumulator has overflowed, or in the CORCON register. It generates a 16-bit, 1.15 one bit to determine if either accumulator has data value that is passed to the data space write saturated. This is useful for complex number saturation logic. If rounding is not indicated by the arithmetic, which typically uses both accumulators. instruction, a truncated 1.15 data value is stored and The device supports three Saturation and Overflow the least significant word is simply discarded. modes: Conventional rounding zero-extends bit 15 of the accu- • Bit 39 Overflow and Saturation: mulator and adds it to the ACCxH word (bits 16 through When bit 39 overflow and saturation occurs, the 31 of the accumulator). saturation logic loads the maximally positive 9.31 • If the ACCxL word (bits0 through 15 of the accu- (0x7FFFFFFFFF) or maximally negative 9.31 value mulator) is between 0x8000 and 0xFFFF (0x8000 (0x8000000000) into the target accumulator. The included), ACCxH is incremented. SA or SB bit is set and remains set until cleared by • If ACCxL is between 0x0000 and 0x7FFF, ACCxH the user application. This condition is referred to as is left unchanged. ‘super saturation’ and provides protection against erroneous data or unexpected algorithm problems A consequence of this algorithm is that over a succes- (such as gain calculations). sion of random rounding operations, the value tends to • Bit 31 Overflow and Saturation: be biased slightly positive. When bit 31 overflow and saturation occurs, the Convergent (or unbiased) rounding operates in the saturation logic then loads the maximally positive same manner as conventional rounding, except when 1.31 value (0x007FFFFFFF) or maximally nega- ACCxL equals 0x8000. In this case, the Least tive 1.31 value (0x0080000000) into the target Significant bit (bit16 of the accumulator) of ACCxH is accumulator. The SA or SB bit is set and remains examined: set until cleared by the user application. When • If it is ‘1’, ACCxH is incremented. this Saturation mode is in effect, the guard bits are • If it is ‘0’, ACCxH is not modified. not used, so the OA, OB or OAB bits are never set. Assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may • Bit 39 Catastrophic Overflow: accumulate. The bit 39 Overflow Status bit from the adder is used to set the SA or SB bit, which remains set The SAC and SAC.R instructions store either a until cleared by the user application. No saturation truncated (SAC), or rounded (SAC.R) version of the operation is performed, and the accumulator is contents of the target accumulator to data memory via allowed to overflow, destroying its sign. If the the X bus, subject to data saturation (see COVTE bit in the INTCON1 register is set, a Section3.8.3.2 “Data Space Write Saturation”). For catastrophic overflow can initiate a trap exception. the MAC class of instructions, the accumulator write- back operation functions in the same manner, 3.8.3 ACCUMULATOR ‘WRITE BACK’ addressing combined MCU (X and Y) data space The MAC class of instructions (with the exception of though the X bus. For this class of instructions, the data MPY, MPY.N, ED and EDAC) can optionally write a is always subject to rounding. rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported: • W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15fraction. • [W13] + = 2, Register Indirect with Post-Increment: The rounded contents of the non-target accumu- lator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write). © 2007-2012 Microchip Technology Inc. DS70292G-page 33

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.8.3.2 Data Space Write Saturation 3.8.4 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data The barrel shifter can perform up to 16-bit arithmetic or space can also be saturated, but without affecting the logic right shifts, or up to 16-bit left shifts in a single contents of the source accumulator. The data space cycle. The source can be either of the two DSP write saturation logic block accepts a 16-bit, 1.15 accumulators or the X bus (to support multi-bit shifts of fractional value from the round logic block as its input, register or memory data). together with overflow status from the original source The shifter requires a signed binary value to determine (accumulator) and the 16-bit round adder. These inputs both the magnitude (number of bits) and direction of the are combined and used to select the appropriate 1.15 shift operation. A positive value shifts the operand right. fractional value as output to write to data space A negative value shifts the operand left. A value of ‘0’ memory. does not modify the operand. If the SATDW bit in the CORCON register is set, data The barrel shifter is 40 bits wide, thereby obtaining a (after rounding or truncation) is tested for overflow and 40-bit result for DSP shift operations and a 16-bit result adjusted accordingly: for MCU shift operations. Data from the X bus is • For input data greater than 0x007FFF, data presented to the barrel shifter between bit positions 16 written to memory is forced to the maximum and 31 for right shifts, and between bit positions 0 and positive 1.15 value, 0x7FFF. 16 for left shifts. • For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. DS70292G-page 34 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.0 MEMORY ORGANIZATION 4.1 Program Address Space Note: This data sheet summarizes the features The program address memory space of the of the dsPIC33FJ32GP302/304, dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, dsPIC33FJ64GPX02/X04, and and dsPIC33FJ128GPX02/X04 devices is 4M dsPIC33FJ128GPX02/X04 families of instructions. The space is addressable by a 24-bit devices. It is not intended to be a value derived either from the 23-bit Program Counter comprehensive reference source. To (PC) during program execution, or from table operation complement the information in this data or data space remapping as described in Section4.8 sheet, refer to Section 4. “Program “Interfacing Program and Data Memory Spaces”. Memory” (DS70203) of the “dsPIC33F/ User application access to the program memory space PIC24H Family Reference Manual”, which is restricted to the lower half of the address range is available from the Microchip website (0x000000 to 0x7FFFFF). The exception is the use of (www.microchip.com). TBLRD/TBLWT operations, which use TBLPAG<7> to The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ permit access to the Configuration bits and Device ID X04, and dsPIC33FJ128GPX02/X04 architecture sections of the configuration memory space. features separate program and data memory spaces The memory map for the dsPIC33FJ32GP302/304, and buses. This architecture also allows the direct dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ access of program memory from the data space during X04 devices is shown in Figure4-1. code execution. FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, AND dsPIC33FJ128GPX02/X04 DEVICES dsPIC33FJ32GP302/304 dsPIC33FJ64GPX02/X04 dsPIC33FJ128GPX02/X04 GOTO Instruction GOTO Instruction GOTO Instruction 0x000000 Reset Address Reset Address Reset Address 0x000002 0x000004 Interrupt Vector Table Interrupt Vector Table Interrupt Vector Table 0x0000FE Reserved Reserved Reserved 0x000100 Alternate Vector Table Alternate Vector Table Alternate Vector Table 0x000104 0x0001FE 0x000200 User Program Flash Memory ce (11264 instructions) User Program pa Flash Memory 0x0057FE S (22016 instructions) 0x005800 y User Program or Flash Memory m e (44032 instructions) M er 00xx0000AACBF00E s U Unimplemented (Read ‘0’s) Unimplemented 0x0157FE (Read ‘0’s) 0x015800 Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved Reserved Reserved e c pa 0xF7FFFE S Device Configuration Device Configuration Device Configuration 0xF80000 ory Registers Registers Registers 0xF80017 m 0xF80018 e M n Reserved Reserved Reserved o ati ur onfig DEVID (2) DEVID (2) DEVID (2) 00xxFFEF0F0F0F0E C 0xFF0002 Reserved Reserved Reserved 0xFFFFFE Note: Memory areas are not shown to scale. © 2007-2012 Microchip Technology Inc. DS70292G-page 35

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.1.1 PROGRAM MEMORY 4.1.2 INTERRUPT AND TRAP VECTORS ORGANIZATION All dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ The program memory space is organized in word- X04, and dsPIC33FJ128GPX02/X04 devices reserve addressable blocks. Although it is treated as 24bits the addresses between 0x00000 and 0x000200 for wide, it is more appropriate to think of each address of hard-coded program execution vectors. A hardware the program memory as a lower and upper word, with Reset vector is provided to redirect code execution the upper byte of the upper word being unimplemented. from the default value of the PC on device Reset to the The lower word always has an even address, while the actual start of code. A GOTO instruction is programmed upper word has an odd address (Figure4-2). by the user application at 0x000000, with the actual address for the start of code at 0x000002. Program memory addresses are always word-aligned on the lower word, and addresses are incremented or dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, decremented by two during code execution. This and dsPIC33FJ128GPX02/X04 devices also have two arrangement provides compatibility with data memory interrupt vector tables, located from 0x000004 to space addressing and makes data in the program 0x0000FF and 0x000100 to 0x0001FF. These vector memory space accessible. tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section7.1 “Interrupt Vector Table”. FIGURE 4-2: PROGRAM MEMORY ORGANIZATION msw most significant word least significant word PC Address Address (lsw Address) 23 16 8 0 0x000001 00000000 0x000000 0x000003 00000000 0x000002 0x000005 00000000 0x000004 0x000007 00000000 0x000006 Program Memory Instruction Width ‘Phantom’ Byte (read as ‘0’) DS70292G-page 36 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.2 Data Address Space All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ care must be taken when mixing byte and word X04, and dsPIC33FJ128GPX02/X04 CPU has a operations, or translating from 8-bit MCU code. If a separate 16-bit-wide data memory space. The data misaligned read or write is attempted, an address error space is accessed using separate Address Generation trap is generated. If the error occurred on a read, the Units (AGUs) for read and write operations. The data instruction underway is completed. If the error occurred memory maps is shown in Figure4-4. on a write, the instruction is executed but the write does All Effective Addresses (EAs) in the data memory space not occur. In either case, a trap is then executed, are 16 bits wide and point to bytes within the data space. allowing the system and/or user application to examine This arrangement gives a data space address range of the machine state prior to execution of the address 64Kbytes or 32K words. The lower half of the data Fault. memory space (that is, when EA<15> = 0) is used for All byte loads into any W register are loaded into the implemented memory addresses, while the upper half Least Significant Byte. The Most Significant Byte is not (EA<15> = 1) is reserved for the Program Space modified. Visibility area (see Section4.8.3 “Reading Data from A sign-extend instruction (SE) is provided to allow user Program Memory Using Program Space Visibility”). applications to translate 8-bit signed data to 16-bit dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, signed values. Alternatively, for 16-bit unsigned data, and dsPIC33FJ128GPX02/X04 devices implement up user applications can clear the MSB of any W register to 16Kbytes of data memory. Should an EA point to a by executing a zero-extend (ZE) instruction on the location outside of this area, an all-zero word or byte is appropriate address. returned. 4.2.3 SFR SPACE 4.2.1 DATA SPACE WIDTH The first 2Kbytes of the Near Data Space, from 0x0000 The data memory space is organized in byte to 0x07FF, is primarily occupied by Special Function addressable, 16-bit wide blocks. Data is aligned in data Registers (SFRs). These are used by the memory and registers as 16-bit words, but all data dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, space EAs resolve to bytes. The Least Significant and dsPIC33FJ128GPX02/X04 core and peripheral Bytes (LSBs) of each word have even addresses, while modules for controlling the operation of the device. the Most Significant Bytes (MSBs) have odd SFRs are distributed among the modules that they addresses. control, and are generally grouped together by module. 4.2.2 DATA MEMORY ORGANIZATION Much of the SFR space contains unused addresses; AND ALIGNMENT these are read as ‘0’. To maintain backward compatibility with PIC® MCU Note: The actual set of peripheral features and devices and improve data space memory usage interrupts varies by the device. Refer to efficiency, the dsPIC33FJ32GP302/304, the corresponding device tables and dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ pinout diagrams for device-specific X04 instruction set supports both word and byte information. operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to 4.2.4 NEAR DATA SPACE step through word-aligned memory. For example, the The 8 Kbyte area between 0x0000 and 0x1FFF is core recognizes that Post-Modified Register Indirect referred to as the near data space. Locations in this Addressing mode [Ws++] results in a value of Ws + 1 space are directly addressable via a 13-bit absolute for byte operations and Ws + 2 for word operations. address field within all memory direct instructions. A data byte read, reads the complete word that Additionally, the whole data space is addressable using contains the byte, using the LSB of any EA to MOV instructions, which support Memory Direct determine which byte to select. The selected byte is Addressing mode with a 16-bit address field, or by placed onto the LSB of the data path. That is, data using Indirect Addressing mode using a working memory and registers are organized as two parallel register as an address pointer. byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2007-2012 Microchip Technology Inc. DS70292G-page 37

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ32GP302/304 DEVICES WITH 4 KB RAM MSB LSB Address 16 bits Address MSB LSB 0x0000 0x0000 2 Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 X Data RAM (X) 6 Kbyte 0x0FFF 0x0FFE Near 0x1001 0x1000 Data 4 Kbyte Space Y Data RAM (Y) SRAM Space 0x13FF 0x13FE 0x1401 0x1400 DMA RAM 0x17FE 0x17FF 0x1800 0x1801 0x8001 0x8000 Optionally X Data Mapped Unimplemented (X) into Program Memory 0xFFFF 0xFFFE DS70292G-page 38 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJ128GP202/204 AND dsPIC33FJ64GP202/ 204 DEVICES WITH 8 KB RAM MSB LSB Address 16 bits Address MSB LSB 0x0001 0x0000 2 Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 8 Kbyte X Data RAM (X) Near Data Space 8 Kbyte 0x17FF 0x17FE SRAM Space 0x1801 0x1800 Y Data RAM (Y) 0x1FFF 0x1FFE 0x2001 0x2000 DMA RAM 0x27FF 0x27FE 0x2801 0x2800 0x8001 0x8000 X Data Optionally Unimplemented (X) Mapped into Program Memory 0xFFFF 0xFFFE © 2007-2012 Microchip Technology Inc. DS70292G-page 39

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/ 804 DEVICES WITH 16 KB RAM LSB MSB Address Address 16 bits MSB LSB 0x0001 0x0000 2 Kbyte SFR Space SFR Space 0x07FF 0x07FE 8 Kbyte 0x0801 0x0800 Near Data X Data RAM (X) Space 0x1FFF 0x1FFE 16 Kbyte 0x27FF 0x27FE SRAM Space 0x2801 0x2800 Y Data RAM (Y) 0x3FFF 0x3FFE 0x4001 0x4000 DMA RAM 0x47FF 0x47FE 0x4801 0x4800 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE DS70292G-page 40 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.2.5 X AND Y DATA SPACES 4.2.6 DMA RAM The core has two data spaces, X and Y. These data Every dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ spaces can beconsidered either separate (for some X04, and dsPIC33FJ128GPX02/X04 device contains DSP instructions), or as one unified linear address up to 2 Kbytes of dual ported DMA RAM located at range (for MCU instructions). The data spaces are the end of Y data space, and is part of Y data space. accessed using two Address Generation Units (AGUs) Memory locations in the DMA RAM space are and separate data paths. This feature allows certain accessible simultaneously by the CPU and the DMA instructions to concurrently fetch two words from RAM, controller module. DMA RAM is utilized by the DMA thereby enabling efficient execution of DSP algorithms controller to store data to be transferred to various such as Finite Impulse Response (FIR) filtering and peripherals using DMA, as well as data transferred Fast Fourier Transform (FFT). from various peripherals using DMA. The DMA RAM can be accessed by the DMA controller without The X data space is used by all instructions and having to steal cycles from the CPU. supports all addressing modes. X data space has separate read and write data buses. The X read data When the CPU and the DMA controller attempt to bus is the read data path for all instructions that view concurrently write to the same DMA RAM location, the data space as combined X and Y address space. It is hardware ensures that the CPU is given precedence in also the X data prefetch path for the dual operand DSP accessing the DMA RAM location. Therefore, the DMA instructions (MAC class). RAM provides a reliable means of transferring DMA data without ever having to stall the CPU. The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, Note: DMA RAM can be used for general EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to purpose data storage if the DMA function provide two concurrent data read paths. is not required in an application. Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to 4.3 Memory Resources addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X data space. Many useful resources related to Memory Organization are provided on the main product page of the Microchip All data memory writes, including in DSP instructions, web site for the devices listed in this data sheet. This view data space as combined X and Y address space. product page, which can be accessed using this link, The boundary between the X and Y data spaces is contains the latest updates and additional information. device-dependent and is not user-programmable. Note: In the event you are not able to access the All effective addresses are 16 bits wide and point to product page using the link above, enter bytes within the data space. Therefore, the data space this URL in your browser: address range is 64 Kbytes, or 32K words, though the http://www.microchip.com/wwwproducts/ implemented memory locations vary by device. Devices.aspx?dDocName=en532311 4.3.1 KEY RESOURCES • Section 2. “Program Memory” (DS70203) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools © 2007-2012 Microchip Technology Inc. DS70292G-page 41

D 4.4 Special Function Register Maps d S s 7029 TABLE 4-1: CPU CORE REGISTERS MAP PIC 2 G SFR All 3 -p SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 3 a F g e WREG0 0000 Working Register 0 0000 J 4 3 2 WREG1 0002 Working Register 1 0000 2 G WREG2 0004 Working Register 2 0000 P WREG3 0006 Working Register 3 0000 3 0 WREG4 0008 Working Register 4 0000 2 WREG5 000A Working Register 5 0000 /3 WREG6 000C Working Register 6 0000 0 4 WREG7 000E Working Register 7 0000 , d WREG8 0010 Working Register 8 0000 s WREG9 0012 Working Register 9 0000 P I WREG10 0014 Working Register 10 0000 C 3 WREG11 0016 Working Register 11 0000 3 F WREG12 0018 Working Register 12 0000 J WREG13 001A Working Register 13 0000 6 4 WREG14 001C Working Register 14 0000 G WREG15 001E Working Register 15 0800 P X SPLIM 0020 Stack Pointer Limit Register xxxx 0 ACCAL 0022 ACCAL xxxx 2 / ACCAH 0024 ACCAH xxxx X 0 ACCAU 0026 ACCA<39> ACCAU xxxx 4 , ACCBL 0028 ACCBL xxxx A ACCBH 002A ACCBH xxxx N D ACCBU 002C ACCB<39> ACCBU xxxx PCL 002E Program Counter Low Word Register xxxx d © s 2 PCH 0030 — — — — — — — — Program Counter High Byte Register 0000 P 00 TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register 0000 IC 7-20 PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register 0000 33 1 RCOUNT 0036 Repeat Loop Counter Register xxxx F 2 M DCOUNT 0038 DCOUNT<15:0> xxxx J1 icro DOSTARTL 003A DOSTARTL<15:1> 0 xxxx 28 ch DOSTARTH 003C — — — — — — — — — — DOSTARTH<5:0> 00xx G ip T DOENDL 003E DOENDL<15:1> 0 xxxx P e X ch DOENDH 0040 — — — — — — — — — — DOENDH 00xx 0 n 2 olo SR 0042 OA OB SA SB OAB SAB DA DC IPL<2:0> RA N OV Z C 0000 /X gy CORCON 0044 — — — US EDT DL<2:0> SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0020 0 In Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 c .

© TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED) 2 d 007 SFR Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts sP -2 I 01 MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 C 2 3 M XMODSRT 0048 XS<15:1> 0 xxxx 3 icro XMODEND 004A XE<15:1> 1 xxxx FJ chip YMODSRT 004C YS<15:1> 0 xxxx 32 T YMODEND 004E YE<15:1> 1 xxxx G ec XBREV 0050 BREN XB<14:0> xxxx P h 3 no DISICNT 0052 — — Disable Interrupts Counter Register xxxx 0 lo 2 g Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / y 3 In 0 c 4 . , d s P I C 3 3 F J 6 4 G P X 0 2 / X 0 4 , A N D d s P I C 3 3 F J 1 2 D 8 S7 G 02 P 9 X 2 G 0 -p 2 a / g X e 43 04

D TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302 d S s 70292 NSaFmRe ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC G 3 -p CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE — — — CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 3 a F g e CNEN2 0062 — CN30IE CN29IE — CN27IE — — CN24IE CN23IE CN22IE CN21IE — — — — CN16IE 0000 J 4 3 4 CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE — — — CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 2 G CNPU2 006A — CN30PUE CN29PUE — CN27PUE — — CN24PUE CN23PUE CN22PUE CN21PUE — — — — CN16PUE 0000 P 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 2 / 3 TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304 0 4 , SFR SFR All d Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets s P CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 IC CNEN2 0062 — CN30IE CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 33 CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 FJ CNPU2 006A — CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 64 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G P X 0 2 / X 0 4 , A N D d © s 2 P 00 IC 7-20 33 1 F 2 M J1 ic 2 ro 8 ch G ip T P e X ch 0 n 2 olo /X gy 0 In 4 c .

© TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP 2 d 00 SFR SFR All s 7 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P -2 Name Addr Resets I 0 C 1 2 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 3 M 3 ic INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 F roc IFS0 0084 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 J3 hip IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 2 Te IFS2 0088 — DMA4IF PMPIF — — — — — — — — DMA3IF C1IF(1) C1RXIF(1) SPI2IF SPI2EIF 0000 GP c hno IFS3 008A — RTCIF DMA5IF DCIIF DCIEIF — — — — — — — — — — — 0000 30 lo IFS4 008C DAC1LIF(2) DAC1RIF(2) — — — — — — — C1TXIF(1) DMA7IF DMA6IF CRCIF U2EIF U1EIF — 0000 2 g / y In IEC0 0094 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 30 c. IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 4 , IEC2 0098 — DMA4IE PMPIE — — — — — — — — DMA3IE C1IE(1) C1RXIE(1) SPI2IE SPI2EIE 0000 d s IEC3 009A — RTCIE DMA5IE DCIIE DCIEIE — — — — — — — — — — — 0000 P IEC4 009C DAC1LIE(2) DAC1RIE(2) — — — — — — — C1TXIE(1) DMA7IE DMA6IE CRCIE U2EIE U1EIE — 0000 IC IPC0 00A4 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444 3 3 IPC1 00A6 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444 F J IPC2 00A8 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 6 4 IPC3 00AA — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444 G IPC4 00AC — CNIP<2:0> — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444 P X IPC5 00AE — IC8IP<2:0> — IC7IP<2:0> — — — — — INT1IP<2:0> 4404 0 IPC6 00B0 — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444 2 / X IPC7 00B2 — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444 0 IPC8 00B4 — C1IP<2:0>(1) — C1RXIP<2:0>(1) — SPI2IP<2:0> — SPI2EIP<2:0> 4444 4 , IPC9 00B6 — — — — — — — — — — — — — DMA3IP<2:0> 0004 A IPC11 00BA — — — — — DMA4IP<2:0> — PMPIP<2:0> — — — — 0440 N D IPC14 00C0 — DCIEIP<2:0> — — — — — — — — — — — — 4000 d IPC15 00C2 — — — — — RTCIP<2:0> — DMA5IP<2:0> — DCIIP<2:0> 0444 s P IPC16 00C4 — CRCIP<2:0> — U2EIP<2:0> — U1EIP<2:0> — — — — 4440 I IPC17 00C6 — — — — — C1TXIP<2:0>(1) — DMA7IP<2:0> — DMA6IP<2:0> 0444 C 3 IPC19 00CA — DAC1LIP<2:0>(2) — DAC1RIP<2:0>(2) — — — — — — — — 4400 3 F INTTREG 00E0 — — — — ILR<3:0>> — VECNUM<6:0> 4444 J 1 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 D 8 S702 Note 21:: IInntteerrrruuppttss ddiissaabblleedd oonn ddeevviicceess wwiitthhoouutt AEuCdAioN ™DA mCo mduoldeusl.es. GP 9 X 2 G 0 -p 2 a / g X e 45 04

D TABLE 4-5: TIMER REGISTER MAP d S s 70292 NSaFmRe ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC G 3 -p TMR1 0100 Timer1 Register 0000 3 a F ge PR1 0102 Period Register 1 FFFF J 46 T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — TSYNC TCS — 0000 32 TMR2 0106 Timer2 Register 0000 G P TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx 3 TMR3 010A Timer3 Register 0000 0 2 PR2 010C Period Register 2 FFFF /3 0 PR3 010E Period Register 3 FFFF 4 T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS<1:0> T32 — TCS — 0000 , d T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 s P TMR4 0114 Timer4 Register 0000 I C TMR5HLD 0116 Timer5 Holding Register (for 32-bit timer operations only) xxxx 3 TMR5 0118 Timer5 Register 0000 3 F PR4 011A Period Register 4 FFFF J 6 PR5 011C Period Register 5 FFFF 4 G T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS<1:0> T32 — TCS — 0000 P T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 X 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 / X TABLE 4-6: INPUT CAPTURE REGISTER MAP 0 4 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All , A Name Addr Resets N IC1BUF 0140 Input 1 Capture Register xxxx D IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 d © s 2 IC2BUF 0144 Input 2 Capture Register xxxx P 00 IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 IC 7-20 IC7BUF 0158 Input 7 Capture Register xxxx 33 12 M IICC78CBUOFN 001155CA — — ICSIDL — — — — Inp—ut 8CaptuIrCe TRMeRgister ICI<1:0> ICOV ICBNE ICM<2:0> 0x0x0x0x FJ1 ic 2 ro IC8CON 015E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 8 chip T Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. GP e X ch 0 n 2 olo /X gy 0 In 4 c .

© TABLE 4-7: OUTPUT COMPARE REGISTER MAP 2 d 00 SFR All s 7 SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P -2 Addr Resets I 0 C 1 2 OC1RS 0180 Output Compare 1 Secondary Register xxxx 3 M 3 ic OC1R 0182 Output Compare 1 Register xxxx F roc OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 J3 hip OC2RS 0186 Output Compare 2 Secondary Register xxxx 2 T G e OC2R 0188 Output Compare 2 Register xxxx P c hno OC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 30 lo OC3RS 018C Output Compare 3 Secondary Register xxxx 2 g / y In OC3R 018E Output Compare 3 Register xxxx 30 c. OC3CON 0190 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 4 , OC4RS 0192 Output Compare 4 Secondary Register xxxx d s OC4R 0194 Output Compare 4 Register xxxx P OC4CON 0196 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 IC Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 3 F TABLE 4-8: I2C1 REGISTER MAP J 6 4 SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All G Addr Resets P X I2C1RCV 0200 — — — — — — — — Receive Register 0000 0 I2C1TRN 0202 — — — — — — — — Transmit Register 00FF 2 / X I2C1BRG 0204 — — — — — — — Baud Rate Generator Register 0000 0 I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 4 , I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 A I2C1ADD 020A — — — — — — Address Register 0000 N D I2C1MSK 020C — — — — — — Address Mask Register 0000 d Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. s P I TABLE 4-9: UART1 REGISTER MAP C 3 3 SFR All SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F Addr Resets J 1 U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000 2 D 8 S7 U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 G 02 U1TXREG 0224 — — — — — — — UTX8 UART Transmit Register xxxx P 9 X 2 U1RXREG 0226 — — — — — — — URX8 UART Received Register 0000 G 0 -p U1BRG 0228 Baud Rate Generator Prescaler 0000 2 a / ge 47 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X04

D d S TABLE 4-10: UART2 REGISTER MAP s 70 P 29 SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All IC 2 Addr Resets G 3 -p U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000 3 a F g e U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 J 4 3 8 U2TXREG 0234 — — — — — — — UTX8 UART Transmit Register xxxx 2 G U2RXREG 0236 — — — — — — — URX8 UART Receive Register 0000 P U2BRG 0238 Baud Rate Generator Prescaler 0000 3 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 / 3 TABLE 4-11: SPI1 REGISTER MAP 0 4 , SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All d Addr Resets s P SPI1STAT 0240 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 I C SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000 3 SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY — 0000 3 F SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000 J 6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 G P TABLE 4-12: SPI2 REGISTER MAP X 0 SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 2 Addr Resets / X SPI2STAT 0260 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 0 4 SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000 , A SPI2CON2 0264 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY — 0000 N SPI2BUF 0268 SPI2 Transmit and Receive Buffer Register 0000 D Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d © s 2 P 00 IC 7-20 33 1 F 2 M J1 ic 2 ro 8 ch G ip T P e X ch 0 n 2 olo /X gy 0 In 4 c .

TABLE 4-13: ADC1 REGISTER MAP FOR dsPIC33FJ64GP202/802, dsPIC33FJ128GP202/802 AND dsPIC33FJ32GP302 © 2 d 00 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All s 7 Resets P -2 I 01 ADC1BUF0 0300 ADC Data Buffer 0 xxxx C 2 3 M AD1CON1 0320 ADON — ADSIDL ADDMABM — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000 3 icro AD1CON2 0322 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000 FJ chip AD1CON3 0324 ADRC — — SAMC<4:0> ADCS<7:0> 0000 32 T AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000 G e P ch AD1CHS0 0328 CH0NB — — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000 3 no AD1PCFGL 032C — — — PCFG12 PCFG11 PCFG10 PCFG9 — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0 lo 2 gy AD1CSSL 0330 — — — CSS12 CSS11 CSS10 CSS9 — — — CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000 /3 Inc AD1CON4 0332 — — — — — — — — — — — — — DMABL<2:0> 0000 04 . Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. , d s TABLE 4-14: ADC1 REGISTER MAP FOR dsPIC33FJ64GP204/804, dsPIC33FJ128GP204/804 AND dsPIC33FJ32GP304 P I C All 3 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 3 F ADC1BUF0 0300 ADC Data Buffer 0 xxxx J 6 AD1CON1 0320 ADON — ADSIDL ADDMABM — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000 4 G AD1CON2 0322 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000 P AD1CON3 0324 ADRC — — SAMC<4:0> ADCS<7:0> 0000 X 0 AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000 2 AD1CHS0 0328 CH0NB — — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000 /X 0 AD1PCFGL 032C — — — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 4 AD1CSSL 0330 — — — CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000 , A AD1CON4 0332 — — — — — — — — — — — — — DMABL<2:0> 0000 N Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. D d s TABLE 4-15: DAC1 REGISTER MAP FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804 P I C SFR All SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 3 3 F DAC1CON 03F0 DACEN — DACSIDL AMPON — — — FORM — DACFDIV<6:0> 0000 J DAC1STAT 03F2 LOEN — LMVOEN — — LITYPE LFULL LEMPTY ROEN — RMVOEN — — RITYPE RFULL REMPTY 0000 12 DS7 DAC1DFLT 03F4 DAC1DFLT<15:0> 0000 8G 02 DAC1RDAT 03F6 DAC1RDAT<15:0> 0000 P 9 X 2G DAC1LDAT 03F8 DAC1LDAT<15:0> 0000 0 -p Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 a / g X e 49 04

DS TABLE 4-16: DMA REGISTER MAP ds 70 P 292 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC G 3 -p DMA0CON 0380 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 3 a F g e DMA0REQ 0382 FORCE — — — — — — — — IRQSEL<6:0> 0000 J 5 3 0 DMA0STA 0384 STA<15:0> 0000 2 G DMA0STB 0386 STB<15:0> 0000 P DMA0PAD 0388 PAD<15:0> 0000 3 0 DMA0CNT 038A — — — — — — CNT<9:0> 0000 2 DMA1CON 038C CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 /3 0 DMA1REQ 038E FORCE — — — — — — — — IRQSEL<6:0> 0000 4 , DMA1STA 0390 STA<15:0> 0000 d DMA1STB 0392 STB<15:0> 0000 s P DMA1PAD 0394 PAD<15:0> 0000 I C DMA1CNT 0396 — — — — — — CNT<9:0> 0000 3 3 DMA2CON 0398 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 F DMA2REQ 039A FORCE — — — — — — — — IRQSEL<6:0> 0000 J 6 DMA2STA 039C STA<15:0> 0000 4 G DMA2STB 039E STB<15:0> 0000 P DMA2PAD 03A0 PAD<15:0> 0000 X 0 DMA2CNT 03A2 — — — — — — CNT<9:0> 0000 2 / DMA3CON 03A4 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 X 0 DMA3REQ 03A6 FORCE — — — — — — — — IRQSEL<6:0> 0000 4 DMA3STA 03A8 STA<15:0> 0000 , A DMA3STB 03AA STB<15:0> 0000 N DMA3PAD 03AC PAD<15:0> 0000 D DMA3CNT 03AE — — — — — — CNT<9:0> 0000 d © s 2 DMA4CON 03B0 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 P 00 DMA4REQ 03B2 FORCE — — — — — — — — IRQSEL<6:0> 0000 IC 7-20 DMA4STA 03B4 STA<15:0> 0000 33 12 Mic DDMMAA44SPATDB 0033BB86 PSATDB<<1155::00>> 00000000 FJ12 ro DMA4CNT 03BA — — — — — — CNT<9:0> 0000 8 ch G ip T DMA5CON 03BC CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 P e DMA5REQ 03BE FORCE — — — — — — — — IRQSEL<6:0> 0000 X chn DMA5STA 03C0 STA<15:0> 0000 02 olo DMA5STB 03C2 STB<15:0> 0000 /X gy In Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 04 c .

© TABLE 4-16: DMA REGISTER MAP (CONTINUED) 2 d 007 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts sP -2 I 0 C 12 DMA5PAD 03C4 PAD<15:0> 0000 3 M DMA5CNT 03C6 — — — — — — CNT<9:0> 0000 3 ic F ro DMA6CON 03C8 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 J c 3 hip DMA6REQ 03CA FORCE — — — — — — — — IRQSEL<6:0> 0000 2 T DMA6STA 03CC STA<15:0> 0000 G e P c h DMA6STB 03CE STB<15:0> 0000 3 nolo DMA6PAD 03D0 PAD<15:0> 0000 02 gy DMA6CNT 03D2 — — — — — — CNT<9:0> 0000 /3 In 0 c DMA7CON 03D4 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 4 . , DMA7REQ 03D6 FORCE — — — — — — — — IRQSEL<6:0> 0000 d DMA7STA 03D8 STA<15:0> 0000 s P DMA7STB 03DA STB<15:0> 0000 I C DMA7PAD 03DC PAD<15:0> 0000 3 3 DMA7CNT 03DE — — — — — — CNT<9:0> 0000 F DMACS0 03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 0000 J 6 DMACS1 03E2 — — — — LSTCH<3:0> PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0000 4 G DSADR 03E4 DSADR<15:0> 0000 P Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X 0 2 / X 0 4 , A N D d s P I C 3 3 F J 1 2 D 8 S7 G 02 P 9 X 2 G 0 -p 2 a / g X e 51 04

D TABLE 4-17: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1 (FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) d S s 70 P 292 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC G 3 -p C1CTRL1 0400 — — CSIDL ABAT — REQOP<2:0> OPMODE<2:0> — CANCAP — — WIN 0480 3 a F g e C1CTRL2 0402 — — — — — — — — — — — DNCNT<4:0> 0000 J 5 3 2 C1VEC 0404 — — — FILHIT<4:0> — ICODE<6:0> 0000 2 G C1FCTRL 0406 DMABS<2:0> — — — — — — — — FSA<4:0> 0000 P C1FIFO 0408 — — FBP<5:0> — — FNRB<5:0> 0000 3 0 C1INTF 040A — — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000 2 / C1INTE 040C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000 3 0 C1EC 040E TERRCNT<7:0> RERRCNT<7:0> 0000 4 , C1CFG1 0410 — — — — — — — — SJW<1:0> BRP<5:0> 0000 d C1CFG2 0412 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0000 s P C1FEN1 0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 FFFF I C C1FMSKSEL1 0418 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000 3 3 C1FMSKSEL2 041A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000 F Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. J 6 4 TABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 (FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) G P All X File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 2 / 0400- See definition when WIN = x X 041E 0 4 C1RXFUL1 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000 , A C1RXFUL2 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000 N C1RXOVF1 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000 D C1RXOVF2 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000 d 2© C1TR01CON 0430 TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI<1:0> TXEN0 TXABT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI<1:0> 0000 sP 00 C1TR23CON 0432 TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI<1:0> TXEN2 TXABT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI<1:0> 0000 IC 7-20 C1TR45CON 0434 TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI<1:0> TXEN4 TXABT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI<1:0> 0000 33 1 C1TR67CON 0436 TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI<1:0> TXEN6 TXABT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI<1:0> 0000 F 2 M C1RXD 0440 Received Data Word xxxx J1 ic 2 ro C1TXD 0442 Transmit Data Word xxxx 8 ch Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G ip T P e X ch 0 n 2 olo /X gy 0 In 4 c .

© TABLE 4-19: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1(FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) 2 d 00 All s 7 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P -2 Resets I 0 C 1 2 0400- See definition when WIN = x 3 M 041E 3 ic F ro C1BUFPNT1 0420 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000 J c 3 hip C1BUFPNT2 0422 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> 0000 2 T C1BUFPNT3 0424 F11BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> 0000 G e P ch C1BUFPNT4 0426 F15BP<3:0> F14BP<3:0> F13BP<3:0> F12BP<3:0> 0000 3 nolo C1RXM0SID 0430 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx 02 gy C1RXM0EID 0432 EID<15:8> EID<7:0> xxxx /3 Inc C1RXM1SID 0434 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx 04 . C1RXM1EID 0436 EID<15:8> EID<7:0> xxxx , d C1RXM2SID 0438 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx s P C1RXM2EID 043A EID<15:8> EID<7:0> xxxx I C C1RXF0SID 0440 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 3 3 C1RXF0EID 0442 EID<15:8> EID<7:0> xxxx F C1RXF1SID 0444 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx J 6 C1RXF1EID 0446 EID<15:8> EID<7:0> xxxx 4 G C1RXF2SID 0448 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx P C1RXF2EID 044A EID<15:8> EID<7:0> xxxx X 0 C1RXF3SID 044C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 2 C1RXF3EID 044E EID<15:8> EID<7:0> xxxx /X 0 C1RXF4SID 0450 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 4 C1RXF4EID 0452 EID<15:8> EID<7:0> xxxx , A C1RXF5SID 0454 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx N C1RXF5EID 0456 EID<15:8> EID<7:0> xxxx D C1RXF6SID 0458 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx d s C1RXF6EID 045A EID<15:8> EID<7:0> xxxx P I C1RXF7SID 045C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx C 3 C1RXF7EID 045E EID<15:8> EID<7:0> xxxx 3 C1RXF8SID 0460 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx F J C1RXF8EID 0462 EID<15:8> EID<7:0> xxxx 1 2 D C1RXF9SID 0464 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 8 S702 C1RXF9EID 0466 EID<15:8> EID<7:0> xxxx GP 9 C1RXF10SID 0468 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X 2 G 0 -p C1RXF10EID 046A EID<15:8> EID<7:0> xxxx 2 ag C1RXF11SID 046C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx /X e 53 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 04

D TABLE 4-19: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1(FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) (CONTINUED) d S s 70 All P 29 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 2 G 3 -p C1RXF11EID 046E EID<15:8> EID<7:0> xxxx 3 ag C1RXF12SID 0470 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx F e J 5 C1RXF12EID 0472 EID<15:8> EID<7:0> xxxx 3 4 2 C1RXF13SID 0474 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx G C1RXF13EID 0476 EID<15:8> EID<7:0> xxxx P 3 C1RXF14SID 0478 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 0 2 C1RXF14EID 047A EID<15:8> EID<7:0> xxxx / 3 C1RXF15SID 047C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 0 4 C1RXF15EID 047E EID<15:8> EID<7:0> xxxx , d Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. s P I C TABLE 4-20: DCI REGISTER MAP 3 3 F SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State J 6 DCICON1 0280 DCIEN — DCISIDL — DLOOP CSCKD CSCKE COFSD UNFM CSDOM DJST — — — COFSM1 COFSM0 0000 0000 0000 0000 4 G DCICON2 0282 — — — — BLEN1 BLEN0 — COFSG<3:0> — WS<3:0> 0000 0000 0000 0000 P DCICON3 0284 — — — — BCG<11:0> 0000 0000 0000 0000 X 0 DCISTAT 0286 — — — — SLOT3 SLOT2 SLOT1 SLOT0 — — — — ROV RFUL TUNF TMPTY 0000 0000 0000 0000 2 TSCON 0288 TSE15 TSE14 TSE13 TSE12 TSE11 TSE10 TSE9 TSE8 TSE7 TSE6 TSE5 TSE4 TSE3 TSE2 TSE1 TSE0 0000 0000 0000 0000 /X RSCON 028C RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 0000 0000 0000 0000 0 4 RXBUF0 0290 Receive Buffer 0 Data Register 0000 0000 0000 0000 , A RXBUF1 0292 Receive Buffer 1 Data Register 0000 0000 0000 0000 N RXBUF2 0294 Receive Buffer 2 Data Register 0000 0000 0000 0000 D RXBUF3 0296 Receive Buffer 3 Data Register 0000 0000 0000 0000 d © s 2 TXBUF0 0298 Transmit Buffer 0 Data Register 0000 0000 0000 0000 P 00 TXBUF1 029A Transmit Buffer 1 Data Register 0000 0000 0000 0000 IC 7-20 TXBUF2 029C Transmit Buffer 2 Data Register 0000 0000 0000 0000 33 12 M TLeXgBeUnFd3: — =0 2u9nEimplemented, read as ‘0’. Transmit Buffer 3 Data Register 0000 0000 0000 0000 FJ1 ic 2 ro 8 ch G ip T P e X ch 0 n 2 olo /X gy 0 In 4 c .

© TABLE 4-21: PERIPHERAL PIN SELECT INPUT REGISTER MAP 2 d 007 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All sP -2 Resets I 0 C 1 2 RPINR0 0680 — — — INT1R<4:0> — — — — — — — — 1F00 3 M 3 ic RPINR1 0682 — — — — — — — — — — — INT2R<4:0> 001F F roc RPINR3 0686 — — — T3CKR<4:0> — — — T2CKR<4:0> 1F1F J3 hip T RPINR4 0688 — — — T5CKR<4:0> — — — T4CKR<4:0> 1F1F 2G ec RPINR7 068E — — — IC2R<4:0> — — — IC1R<4:0> 1F1F P h 3 no RPINR10 0694 — — — IC8R<4:0> — — — IC7R<4:0> 1F1F 0 lo 2 gy RPINR11 0696 — — — — — — — — — — — OCFAR<4:0> 001F /3 Inc RPINR18 06A4 — — — U1CTSR<4:0> — — — U1RXR<4:0> 1F1F 04 . RPINR19 06A6 — — — U2CTSR<4:0> — — — U2RXR<4:0> 1F1F , d RPINR20 06A8 — — — SCK1R<4:0> — — — SDI1R<4:0> 1F1F s P RPINR21 06AA — — — — — — — — — — — SS1R<4:0> 001F IC RPINR22 06AC — — — SCK2R<4:0> — — — SDI2R<4:0> 1F1F 3 3 RPINR23 06AE — — — — — — — — — — — SS2R<4:0> 001F F J RPINR24 06B0 — — — CSCKR<4:0> — — — CSDIR<4:0> 1F1F 6 4 RPINR25 06B2 — — — — — — — — — — — COFSR<4:0> 001F G RPINR26(1) 06B4 — — — — — — — — — — — C1RXR<4:0> 001F P X Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 Note 1: This register is present only for dsPIC33FJ128GP802/804 and dsPIC33FJ64GP802/804 2 / X 0 4 , A N D d s P I C 3 3 F J 1 2 D 8 S7 G 02 P 9 X 2 G 0 -p 2 a / g X e 55 04

D TABLE 4-22: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND d S s 70 dsPIC33FJ32GP302 P 29 IC 2 All G File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3 -p Resets 3 age RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> 0000 FJ 5 RPOR1 06C2 — — — RP3R<4:0> — — — RP2R<4:0> 0000 3 6 2 RPOR2 06C4 — — — RP5R<4:0> — — — RP4R<4:0> 0000 G RPOR3 06C6 — — — RP7R<4:0> — — — RP6R<4:0> 0000 P 3 RPOR4 06C8 — — — RP9R<4:0> — — — RP8R<4:0> 0000 0 2 RPOR5 06CA — — — RP11R<4:0> — — — RP10R<4:0> 0000 / 3 RPOR6 06CC — — — RP13R<4:0> — — — RP12R<4:0> 0000 0 4 RPOR7 06CE — — — RP15R<4:0> — — — RP14R<4:0> 0000 , d Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. s P I C 3 TABLE 4-23: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND 3 dsPIC33FJ32GP304 F J 6 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 4 Resets G RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> 0000 P X RPOR1 06C2 — — — RP3R<4:0> — — — RP2R<4:0> 0000 0 2 RPOR2 06C4 — — — RP5R<4:0> — — — RP4R<4:0> 0000 / X RPOR3 06C6 — — — RP7R<4:0> — — — RP6R<4:0> 0000 0 RPOR4 06C8 — — — RP9R<4:0> — — — RP8R<4:0> 0000 4, RPOR5 06CA — — — RP11R<4:0> — — — RP10R<4:0> 0000 A N RPOR6 06CC — — — RP13R<4:0> — — — RP12R<4:0> 0000 D RPOR7 06CE — — — RP15R<4:0> — — — RP14R<4:0> 0000 d © RPOR8 06D0 — — — RP17R<4:0> — — — RP16R<4:0> 0000 s 200 RPOR9 06D2 — — — RP19R<4:0> — — — RP18R<4:0> 0000 PIC 7-201 RRPPOORR1110 0066DD46 —— —— —— RRPP2213RR<<44::00>> —— —— —— RRPP2202RR<<44::00>> 00000000 33F 2 M RPOR12 06D8 — — — RP25R<4:0> — — — RP24R<4:0> 0000 J1 ic Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 ro 8 ch G ip T P e X ch 0 n 2 olo /X gy 0 In 4 c .

© TABLE 4-24: PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND 2 d 00 dsPIC33FJ32GP302 s 7 P -20 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All IC 1 Resets 2 3 M 3 ic PMCON 0600 PMPEN — PSIDL ADRMUX<1:0> PTBEEN PTWREN PTRDEN CSF1 CSF0 ALP — CS1P BEP WRSP RDSP 0000 F roc PMMODE 0602 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0> 0000 J3 hip PMADDR ADDR15 CS1 ADDR<13:0> 0000 2 T 0604 G e PMDOUT1 Parallel Port Data Out Register 1 (Buffers 0 and 1) 0000 P c hno PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3) 0000 30 lo PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1) 0000 2 g / y In PMPDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3) 0000 30 c. PMAEN 060C — PTEN14 — — — — — — — — — — — — PTEN<1:0> 0000 4 , PMSTAT 060E IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 008F d s Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P I C 3 TABLE 4-25: PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND 3 F dsPIC33FJ32GP304 J 6 All 4 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets G P PMCON 0600 PMPEN — PSIDL ADRMUX<1:0> PTBEEN PTWREN PTRDEN CSF1 CSF0 ALP — CS1P BEP WRSP RDSP 0000 X 0 PMMODE 0602 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0> 0000 2 PMADDR ADDR15 CS1 ADDR<13:0> 0000 /X 0604 0 PMDOUT1 Parallel Port Data Out Register 1 (Buffers 0 and 1) 0000 4 PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3) 0000 , A PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1) 0000 N PMPDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3) 0000 D PMAEN 060C — PTEN14 — — — PTEN<10:0> 0000 d s PMSTAT 060E IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 008F P I Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. C 3 3 F J 1 2 D 8 S7 G 02 P 9 X 2 G 0 -p 2 a / g X e 57 04

D TABLE 4-26: REAL-TIME CLOCK AND CALENDAR REGISTER MAP d S s 70292 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC G 3 -p ALRMVAL 0620 Alarm Value Register Window based on APTR<1:0> xxxx 3 a F ge ALCFGRPT 0622 ALRMEN CHIME AMASK<3:0> ALRMPTR<1:0> ARPT<7:-0> 0000 J 58 RTCVAL 0624 RTCC Value Register Window based on RTCPTR<1:0> xxxx 32 RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR<1:0> CAL<7:0> 0000 G P PADCFG1 02FC — — — — — — — — — — — — — — RTSECSEL PMPTTL 0000 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 2 / 3 0 TABLE 4-27: CRC REGISTER MAP 4 , d All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 s Resets P I CRCCON 0640 — — CSIDL VWORD<4:0> CRCFUL CRCMPT — CRCGO PLEN<3:0> 0000 C 3 CRCXOR 0642 X<15:0> 0000 3 F CRCDAT 0644 CRC Data Input Register 0000 J CRCWDAT 0646 CRC Result Register 0000 6 4 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G P X 0 TABLE 4-28: DUAL COMPARATOR REGISTER MAP 2 / X All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Resets 4 , CMCON 0630 CMIDL — C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTEN C2OUT C1OUT C2INV C1INV C2NEG C2POS C1NEG C1POS 0000 A CVRCON 0632 — — — — — — — — CVREN CVROE CVRR CVRSS CVR<3:0> 0000 N D Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d © s 2 P 00 TABLE 4-29: PORTA REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302 IC 7-201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 33F 2 M TRISA 02C0 — — — — — — — — — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001F J1 ic 2 ro PORTA 02C2 — — — — — — — — — — — RA4 RA3 RA2 RA1 RA0 xxxx 8 ch G ip Te LOADTCAA 0022CC64 —— —— —— —— —— —— —— —— —— —— —— LA—TA4 LA—TA3 LA—TA2 LA—TA1 LA—TA0 x0x0x0x0 PX chn Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 02 olo /X gy 0 In 4 c .

© TABLE 4-30: PORTA REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304 2 d 00 All s 7 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P -2 Resets I 0 C 1 2 TRISA 02C0 — — — — — TRISA10 TRISA9 TRISA8 TRISA7 — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 079F 3 M 3 ic PORTA 02C2 — — — — — RA10 RA9 RA8 RA7 — — RA4 RA3 RA2 RA1 RA0 xxxx F roc LATA 02C4 — — — — — LATA10 LATA9 LATA8 LATA7 — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx J3 hip ODCA 02C6 — — — — — ODCA10 ODCA9 ODCA8 ODCA7 — — — — — — — 0000 2 T G e Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P c h 3 no 0 lo 2 g TABLE 4-31: PORTB REGISTER MAP / y 3 In 0 c. File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 4, d TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF s P PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx I C LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx 3 3 ODCB 02CE — — — — ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 — — — — — 0000 F Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. J 6 4 G TABLE 4-32: PORTC REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304 P X All 0 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 2 / X TRISC 02D0 — — — — — — TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 03FF 0 4 PORTC 02D2 — — — — — — RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx , A LATC 02D4 — — — — — — LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx N ODCC 02D6 — — — — — — ODCC9 ODCC8 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 — — — 0000 D Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d s P I C 3 3 F J 1 2 D 8 S7 G 02 P 9 X 2 G 0 -p 2 a / g X e 59 04

D TABLE 4-33: SYSTEM CONTROL REGISTER MAP d S s 70292 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC G 3 -p RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1) 3 a F ge OSCCON 0742 — COSC<2:0> — NOSC<2:0> CLKLOCK IOLOCK LOCK — CF — LPOSCEN OSWEN 0300(2) J 6 3 0 CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> PLLPOST<1:0> — PLLPRE<4:0> 3040 2 G PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0030 P OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000 3 0 ACLKCON 074A — — SELACLK AOSCMD<1:0> APSTSCLR<2:0> ASRCSEL — — — — — — — 0000 2 / Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 0 Note 1: RCON register Reset values dependent on type of Reset. 4 2: OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset. , d s P TABLE 4-34: SECURITY REGISTER MAP(1) IC 3 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 3 Resets F J BSRAM 0750 — — — — — — — — — — — — — IW_BSR IR_BSR RL_BSR 0000 6 4 SSRAM 0752 — — — — — — — — — — — — — IW_ SSR IR_SSR RL_SSR 0000 G P Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X Note 1: This register is not present in devices with 4K RAM and 32K Flash memory. 0 2 / X TABLE 4-35: NVM REGISTER MAP 0 4 , All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A Resets N NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP<3:0> 0000 D NVMKEY 0766 — — — — — — — — NVMKEY<7:0> 0000 d © s 2 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P 00 IC 7-20 TABLE 4-36: PMD REGISTER MAP 33 1 F 2 Mic File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts J12 ro 8 ch PMD1 0770 T5MD T4MD T3MD T2MD T1MD — — DCIMD I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD AD1MD 0000 G ip T PMD2 0772 IC8MD IC7MD — — — — IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000 P e X ch PMD3 0774 — — — — — CMPMD RTCCMD PMPMD CRCMD DAC1MD — — — — — — 0000 0 n 2 olo Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /X gy 0 In 4 c .

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.4.1 SOFTWARE STACK 4.4.2 DATA RAM PROTECTION FEATURE In addition to its use as a working register, the W15 The dsPIC33F product family supports Data RAM register in the dsPIC33FJ32GP302/304, protection features that enable segments of RAM to be dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ protected when used in conjunction with Boot and X04 devices is also used as a software Stack Pointer. Secure Code Segment Security. BSRAM (Secure RAM The Stack Pointer always points to the first available segment for BS) is accessible only from the Boot free word and grows from lower to higher addresses. It Segment Flash code when enabled. SSRAM (Secure pre-decrements for stack pops and post-increments for RAM segment for RAM) is accessible only from the stack pushes, as shown in Figure4-6. For a PC push Secure Segment Flash code when enabled. See during any CALL instruction, the MSb of the PC is zero- Table4-1 for an overview of the BSRAM and SSRAM extended before the push, ensuring that the MSb is SFRs. always clear. 4.5 Instruction Addressing Modes Note: A PC push during exception processing concatenates the SRL register to the MSb The addressing modes shown in Table4-37 form the of the PC prior to the push. basis of the addressing modes optimized to support the specific features of individual instructions. The The Stack Pointer Limit register (SPLIM) associated addressing modes provided in the MAC class of with the Stack Pointer sets an upper address boundary instructions differ from those in the other instruction for the stack. SPLIM is uninitialized at Reset. As is the types. case for the Stack Pointer, SPLIM<0> is forced to ‘0’ because all stack operations must be word aligned. 4.5.1 FILE REGISTER INSTRUCTIONS Whenever an EA is generated using W15 as a source Most file register instructions use a 13-bit address field or destination pointer, the resulting address is (f) to directly address data present in the first 8192 compared with the value in SPLIM. If the contents of bytes of data memory (near data space). Most file the Stack Pointer (W15) and the SPLIM register are register instructions employ a working register, W0, equal and a push operation is performed, a stack error which is denoted as WREG in these instructions. The trap does not occur. The stack error trap occurs on a destination is typically either the same file register or subsequent push operation. For example, to cause a WREG (with the exception of the MUL instruction), stack error trap when the stack grows beyond address which writes the result to a register or register pair. The 0x2000 in RAM, initialize the SPLIM with the value MOV instruction allows additional flexibility and can 0x1FFE. access the entire data space. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to 4.5.2 MCU INSTRUCTIONS be less than 0x0800. This prevents the stack from The three-operand MCU instructions are of the form: interfering with the Special Function Register (SFR) space. Operand 3 = Operand 1 <function> Operand 2 where: A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. Operand 1 is always a working register (that is, the addressing mode can only be register direct), which is FIGURE 4-6: CALL STACK FRAME referred to as Wb. Operand 2 can be a W register, fetched from data 0x0000 15 0 memory, or a 5-bit literal. The result location can be either a W register or a data memory location. The fol- lowing addressing modes are supported by MCU d waress instructions: Todr • Register Direct s Ad ower PC<15:0> W15 (before CALL) • Register Indirect Grgh 000000000 PC<22:16> • Register Indirect Post-Modified ck Hi <Free Word> W15 (after CALL) a • Register Indirect Pre-Modified St • 5-bit or 10-bit Literal POP : [--W15] PUSH: [W15++] Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. © 2007-2012 Microchip Technology Inc. DS70292G-page 61

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 4-37: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. 4.5.3 MOVE AND ACCUMULATOR 4.5.4 MAC INSTRUCTIONS INSTRUCTIONS The dual source operand DSP instructions (CLR, ED, Move instructions and the DSP accumulator class of EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred instructions provide a greater degree of addressing to as MAC instructions, use a simplified set of addressing flexibility than other instructions. In addition to the modes to allow the user application to effectively addressing modes supported by most MCU manipulate the data pointers through register indirect instructions, move and accumulator instructions also tables. support Register Indirect with Register Offset The two-source operand prefetch registers must be Addressing mode, also referred to as Register Indexed members of the set {W8, W9, W10, W11}. For data mode. reads, W8 and W9 are always directed to the X RAGU, Note: For the MOV instructions, the addressing and W10 and W11 are always directed to the Y AGU. mode specified in the instruction can differ The effective addresses generated (before and after for the source and destination EA. modification) must, therefore, be valid addresses within However, the 4-bit Wb (Register Offset) X data space for W8 and W9 and Y data space for W10 field is shared by both source and and W11. destination (but typically only used by Note: Register Indirect with Register Offset one). Addressing mode is available only for W9 (in X space) and W11 (in Y space). In summary, the following addressing modes are supported by move and accumulator instructions: In summary, the following addressing modes are • Register Direct supported by the MAC class of instructions: • Register Indirect • Register Indirect • Register Indirect Post-modified • Register Indirect Post-Modified by 2 • Register Indirect Pre-modified • Register Indirect Post-Modified by 4 • Register Indirect with Register Offset (Indexed) • Register Indirect Post-Modified by 6 • Register Indirect with Literal Offset • Register Indirect with Register Offset (Indexed) • 8-bit Literal 4.5.5 OTHER INSTRUCTIONS • 16-bit Literal Besides the addressing modes outlined previously, some Note: Not all instructions support all the address- instructions use literal constants of various sizes. For ing modes given above. Individual instruc- example, BRA (branch) instructions use 16-bit signed lit- tions may support different subsets of erals to specify the branch destination directly, whereas these addressing modes. the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. DS70292G-page 62 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.6 Modulo Addressing The length of a circular buffer is not directly specified. It is determined by the difference between the Modulo Addressing mode is a method of providing an corresponding start and end addresses. The maximum automated means to support circular data buffers using possible length of the circular buffer is 32K words hardware. The objective is to remove the need for (64Kbytes). software to perform data address boundary checks when executing tightly looped code, as is typical in 4.6.2 W ADDRESS REGISTER many DSP algorithms. SELECTION Modulo Addressing can operate in either data or program The Modulo and Bit-Reversed Addressing Control space (since the data pointer mechanism is essentially register, MODCON<15:0>, contains enable flags as well the same for both). One circular buffer can be supported as a W register field to specify the W Address registers. in each of the X (which also provides the pointers into The XWM and YWM fields select the registers that program space) and Y data spaces. Modulo Addressing operate with Modulo Addressing: can operate on any W register pointer. However, it is not • If XWM = 15, XRAGU and X WAGU Modulo advisable to use W14 or W15 for Modulo Addressing Addressing is disabled. since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively. • If YWM = 15, Y AGU Modulo Addressing is disabled. In general, any particular circular buffer can be config- ured to operate in only one direction as there are The X Address Space Pointer W register (XWM), to certain restrictions on the buffer start address (for incre- which Modulo Addressing is to be applied, is stored in menting buffers), or end address (for decrementing MODCON<3:0> (see Table4-1). Modulo Addressing is buffers), based upon the direction of the buffer. enabled for X data space when XWM is set to any value other than ‘15’ and the XMODEN bit is set at The only exception to the usage restrictions is for MODCON<15>. buffers that have a power-of-two length. As these buffers satisfy the start and end address criteria, they The Y Address Space Pointer W register (YWM) to can operate in a bidirectional mode (that is, address which Modulo Addressing is to be applied is stored in boundary checks are performed on both the lower and MODCON<7:4>. Modulo Addressing is enabled for Y upper address boundaries). data space when YWM is set to any value other than ‘15’ and the YMODEN bit is set at MODCON<14>. 4.6.1 START AND END ADDRESS The Modulo Addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table4-1). Note: Y space Modulo Addressing EA calculations assume word-sized data (LSb of every EA is always clear). FIGURE 4-7: MODULO ADDRESSING OPERATION EXAMPLE Byte MOV #0x1100, W0 Address MOV W0, XMODSRT ;set modulo start address MOV #0x1163, W0 MOV W0, MODEND ;set modulo end address 0x1100 MOV #0x8001, W0 MOV W0, MODCON ;enable W1, X AGU for modulo MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer 0x1163 DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2007-2012 Microchip Technology Inc. DS70292G-page 63

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.6.3 MODULO ADDRESSING XB<14:0> is the Bit-Reversed Address modifier, or APPLICABILITY ‘pivot point,’ which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT Modulo Addressing can be applied to the Effective data buffer size. Address (EA) calculation associated with any W register. Address boundaries check for addresses Note: All bit-reversed EA calculations assume equal to: word-sized data (LSb of every EA is always clear). The XB value is scaled • The upper boundary addresses for incrementing accordingly to generate compatible (byte) buffers addresses. • The lower boundary addresses for decrementing buffers When enabled, Bit-Reversed Addressing is executed only for Register Indirect with Pre-Increment or Post- It is important to realize that the address boundaries Increment Addressing and word-sized data writes. It check for addresses less than or greater than the upper does not function for any other addressing mode or for (for incrementing buffers) and lower (for decrementing byte-sized data, and normal addresses are generated buffers) boundary addresses (not just equal to). instead. When Bit-Reversed Addressing is active, the Address changes can, therefore, jump beyond W Address Pointer is always added to the address boundaries and still be adjusted correctly. modifier (XB), and the offset associated with the Note: The modulo corrected effective address is Register Indirect Addressing mode is ignored. In written back to the register only when Pre- addition, as word-sized data is a requirement, the LSb Modify or Post-Modify Addressing mode is of the EA is ignored (and always clear). used to compute the effective address. Note: Modulo Addressing and Bit-Reversed When an address offset (such as [W7 + Addressing should not be enabled W2]) is used, Modulo Address correction together. If an application attempts to do so, is performed but the contents of the Bit-Reversed Addressing assumes priority register remain unchanged. when active for the X WAGU and X WAGU, Modulo Addressing is disabled. However, 4.7 Bit-Reversed Addressing Modulo Addressing continues to function in the X RAGU. Bit-Reversed Addressing mode is intended to simplify data reordering for radix-2 FFT algorithms. It is If Bit-Reversed Addressing has already been enabled supported by the X AGU for data writes only. by setting the BREN bit (XBREV<15>), a write to the The modifier, which can be a constant value or register XBREV register should not be immediately followed by contents, is regarded as having its bit order reversed. an indirect read operation using the W register that has The address source and destination are kept in normal been designated as the bit-reversed pointer. order. Thus, the only operand requiring reversal is the modifier. 4.7.1 BIT-REVERSED ADDRESSING IMPLEMENTATION Bit-Reversed Addressing mode is enabled in any of these situations: • BWM bits (W register selection) in the MODCON register are any value other than ‘15’ (the stack cannot be accessed using Bit-Reversed Addressing) • The BREN bit is set in the XBREV register • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment If the length of a bit-reversed buffer is M = 2N bytes, the last ‘N’ bits of the data buffer start address must be zeros. DS70292G-page 64 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-38: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 © 2007-2012 Microchip Technology Inc. DS70292G-page 65

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.8 Interfacing Program and Data 4.8.1 ADDRESSING PROGRAM SPACE Memory Spaces Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ needed to create a 23-bit or 24-bit program address X04, and dsPIC33FJ128GPX02/X04 architecture uses from 16-bit data registers. The solution depends on the a 24 bit wide program space and a 16 bit wide data interface method to be used. space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the For table operations, the 8-bit Table Page register program space. To use this data successfully, it must (TBLPAG) is used to define a 32Kword region within be accessed in a way that preserves the alignment of the program space. This is concatenated with a 16-bit information in both spaces. EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used Aside from normal execution, the to determine if the operation occurs in the user memory dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, (TBLPAG<7> = 0) or the configuration memory and dsPIC33FJ128GPX02/X04 architecture provides (TBLPAG<7> = 1). two methods by which program space can be accessed during operation: For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a • Using table instructions to access individual bytes 16Kword page in the program space. When the Most or words anywhere in the program space Significant bit of the EA is ‘1’, PSVPAG is concatenated • Remapping a portion of the program space into with the lower 15 bits of the EA to form a 23-bit program the data space (Program Space Visibility) space address. Unlike table operations, this limits Table instructions allow an application to read or write remapping operations strictly to the user memory area. to small areas of the program memory. This capability Table4-39 and Figure4-9 show how the program EA is makes the method ideal for accessing data tables that created for table operations and remapping accesses need to be updated periodically. It also allows access from the data EA. Here, P<23:0> refers to a program to all bytes of the program word. The remapping space word, and D<15:0> refers to a data space word. method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. The application can only access the least significant word of the program word. TABLE 4-39: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 (Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0>(1) (Block Remap/Read) 0 xxxx xxxx xxx xxxx xxxx xxxx Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. DS70292G-page 66 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 0 23 bits EA 1/0 Table Operations(2) 1/0 TBLPAG 8 bits 16 bits 24 bits Select 1 EA 0 Program Space Visibility(1) 0 PSVPAG (Remapping) 8 bits 15 bits 23 bits User/Configuration Byte Select Space Select Note1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. © 2007-2012 Microchip Technology Inc. DS70292G-page 67

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.8.2 DATA ACCESS FROM PROGRAM - In Byte mode, either the upper or lower byte MEMORY USING TABLE of the lower program word is mapped to the INSTRUCTIONS lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower The TBLRDL and TBLWTL instructions offer a direct byte is selected when it is ‘0’. method of reading or writing the lower word of any • TBLRDH (Table Read High): address within the program space without going through data space. The TBLRDH and TBLWTH - In Word mode, this instruction maps the entire instructions are the only method to read or write the upper word of a program address (P<23:16>) upper 8bits of a program space word as data. to a data address. The ‘phantom’ byte (D<15:8>), is always ‘0’. The PC is incremented by two for each successive - In Byte mode, this instruction maps the upper 24-bit program word. This allows program memory or lower byte of the program word to D<7:0> addresses to directly map to data space addresses. of the data address, in the TBLRDL instruc- Program memory can thus be regarded as two 16-bit- tion. The data is always ‘0’ when the upper wide word address spaces, residing side by side, each ‘phantom’ byte is selected (Byte Select = 1). with the same address range. TBLRDL and TBLWTL access the space that contains the least significant In a similar fashion, two table instructions, TBLWTH data word. TBLRDH and TBLWTH access the space that and TBLWTL, are used to write individual bytes or contains the upper data byte. words to a program space address. The details of their operation are explained in Section5.0 “Flash Two table instructions are provided to move byte or Program Memory”. word-sized (16-bit) data to and from program space. Both function as either byte or word operations. For all table operations, the area of program memory space to be accessed is determined by the Table Page • TBLRDL (Table Read Low): register (TBLPAG). TBLPAG covers the entire program - In Word mode, this instruction maps the memory space of the device, including user application lower word of the program space and configuration spaces. When TBLPAG<7> = 0, the location (P<15:0>) to a data address table page is located in the user memory space. When (D<15:0>). TBLPAG<7> = 1, the page is located in configuration space. FIGURE 4-10: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG 02 23 15 0 0x000000 23 16 8 0 00000000 00000000 0x020000 00000000 0x030000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 0x800000 Only read operations are shown; write operations are also valid in the user memory area. DS70292G-page 68 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.8.3 READING DATA FROM PROGRAM 24-bit program word are used to contain the data. The MEMORY USING PROGRAM SPACE upper 8 bits of any program space location used as VISIBILITY data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible The upper 32Kbytes of data space may optionally be issues should the area of code ever be accidentally mapped into any 16Kword page of the program space. executed. This option provides transparent access to stored constant data from the data space without the need to Note: PSV access is temporarily disabled during use special instructions (such as TBLRDL/H). table reads/writes. Program space access through the data space occurs For operations that use PSV and are executed outside if the Most Significant bit of the data space EA is ‘1’ and a REPEAT loop, the MOV and MOV.D instructions program space visibility is enabled by setting the PSV require one instruction cycle in addition to the specified bit in the Core Control register (CORCON<2>). The execution time. All other instructions require two location of the program memory space to be mapped instruction cycles in addition to the specified execution into the data space is determined by the Program time. Space Visibility Page register (PSVPAG). This 8-bit For operations that use PSV, and are executed inside register defines any one of 256 possible pages of a REPEAT loop, these instances require two instruction 16Kwords in program space. In effect, PSVPAG cycles in addition to the specified execution time of the functions as the upper 8 bits of the program memory instruction: address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each • Execution in the first iteration program memory word, the lower 15 bits of data space • Execution in the last iteration addresses directly map to the lower 15 bits in the • Execution prior to exiting the loop due to an corresponding program space addresses. interrupt Data reads to this area add a cycle to the instruction • Execution upon re-entering the loop after an being executed, since two program memory fetches interrupt is serviced are required. Any other iteration of the REPEAT loop allows the Although each data space address 0x8000 and higher instruction using PSV to access data, to execute in a maps directly into a corresponding program memory single cycle. address (see Figure4-11), only the lower 16bits of the FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space Data Space PSVPAG 23 15 0 02 0x000000 0x0000 Data EA<14:0> 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory 0x8000 space... PSV Area ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 0x800000 © 2007-2012 Microchip Technology Inc. DS70292G-page 69

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 70 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 5.0 FLASH PROGRAM MEMORY programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for Note1: This data sheet summarizes the features power (VDD), ground (VSS) and Master Clear (MCLR). of the dsPIC33FJ32GP302/304, This allows customers to manufacture boards with dsPIC33FJ64GPX02/X04, and unprogrammed devices and then program the digital dsPIC33FJ128GPX02/X04 families of signal controller just before shipping the product. This devices. It is not intended to be a also allows the most recent firmware or a custom comprehensive reference source. To firmware to be programmed. complement the information in this data RTSP is accomplished using TBLRD (table read) and sheet, refer to Section 5. “Flash TBLWT (table write) instructions. With RTSP, the user Programming” (DS70191) of the application can write program memory data either in “dsPIC33F/PIC24H Family Reference blocks or ‘rows’ of 64 instructions (192 bytes) at a time Manual”, which is available from the or a single program memory word, and erase program Microchip website (www.microchip.com). memory in blocks or ‘pages’ of 512 instructions (1536 2: Some registers and associated bits bytes) at a time. described in this section may not be avail- able on all devices. Refer to Section4.0 5.1 Table Instructions and Flash “Memory Organization” in this data Programming sheet for device-specific register and bit information. Regardless of the method used, all programming of Flash memory is done with the table read and table The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ write instructions. These allow direct read and write X04, and dsPIC33FJ128GPX02/X04 devices contain access to the program memory space from the data internal Flash program memory for storing and memory while the device is in normal operating mode. executing application code. The memory is readable, The 24-bit target address in the program memory is writable and erasable during normal operation over the formed using bits <7:0> of the TBLPAG register and the entire VDD range. Effective Address (EA) from a W register specified in Flash memory can be programmed in two ways: the table instruction, as shown in Figure5-1. • In-Circuit Serial Programming™ (ICSP™) The TBLRDL and the TBLWTL instructions are used to programming capability read or write to bits <15:0> of program memory. • Run-Time Self-Programming (RTSP) TBLRDL and TBLWTL can access program memory in both Word and Byte modes. ICSP allows any of the following devices, dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, The TBLRDH and TBLWTH instructions are used to read and dsPIC33FJ128GPX02/X04, to be serially or write to bits <23:16> of program memory. TBLRDH programmed while in the end application circuit. This is and TBLWTH can also access program memory in Word done with two lines for programming clock and or Byte mode. FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 bits Using 0 Program Counter 0 Program Counter Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 bits 16 bits User/Configuration Byte Space Select 24-bit EA Select © 2007-2012 Microchip Technology Inc. DS70292G-page 71

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 5.2 RTSP Operation EQUATION 5-2: MINIMUM ROW WRITE TIME The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 Flash program 11064 Cycles memory array is organized into rows of 64 instructions T =------------------------------------------------------------------------------------------------=1.435ms RW 7.37 MHz× (1+0.05)× (1–0.00375) or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one The maximum row write time is equal to Equation5-3. word at a time. Table30-12 shows typical erase and programming times. The 8-row erase pages and single EQUATION 5-3: MAXIMUM ROW WRITE row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and TIME 192 bytes, respectively. 11064 Cycles The program memory implements holding buffers that T =------------------------------------------------------------------------------------------------=1.586ms RW 7.37 MHz× (1–0.05)× (1–0.00375) can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers sequentially. The Setting the WR bit (NVMCON<15>) starts the instruction words loaded must always be from a group operation, and the WR bit is automatically cleared of 64 boundary. when the operation is finished. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions 5.4 Control Registers to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total Two SFRs are used to read and write the program of 64 TBLWTL and TBLWTH instructions are required Flash memory: NVMCON and NVMKEY. to load the instructions. The NVMCON register (Register5-1) controls which All of the table write operations are single-word writes blocks are to be erased, which memory type is to be (two instruction cycles) because only the buffers are programmed and the start of the programming cycle. written. A programming cycle is required for NVMKEY (Register5-2) is a write-only register that is programming each row. used for write protection. To start a programming or erase sequence, the user application must consecu- 5.3 Programming Operations tively write 0x55 and 0xAA to the NVMKEY register. Refer to Section5.3 “Programming Operations” for A complete programming sequence is necessary for further details. programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the 5.5 Flash Resources programming operation is finished. The programming time depends on the FRC accuracy Many useful resources related to Flash memory are (see Table30-19) and the value of the FRC Oscillator provided on the main product page of the Microchip Tuning register (see Register9-4). Use the formula in web site for the devices listed in this data sheet. This Equation5-1 to calculate the minimum and maximum product page, which can be accessed using this link, values for the Row Write Time, Page Erase Time and contains the latest updates and additional information. Word Write Cycle Time parameters (see Table30-12). Note: In the event you are not able to access the product page using the link above, enter EQUATION 5-1: PROGRAMMING TIME this URL in your browser: http://www.microchip.com/wwwproducts/ T ---------------------------------------------------------------------------------------------------------------------------- Devices.aspx?dDocName=en532311 7.37 MHz× (FRC Accuracy)%× (FRC Tuning)% 5.5.1 KEY RESOURCES For example, if the device is operating at +125°C, • Section 5. “Flash Programming” (DS70191) the FRC accuracy will be ±5%. If the TUN<5:0> bits • Code Samples (see Register9-4) are set to ‘b111111, the • Application Notes minimum row write time is equal to Equation5-2. • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70292G-page 72 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 5.6 Flash Control Registers REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — ERASE — — NVMOP<3:0>(2) bit 7 bit 0 Legend: SO = Settable only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command 0 = Perform the program operation specified by NVMOP<3:0> on the next WR command bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation Select bits(2) If ERASE = 1: 1111 = Memory bulk erase operation 1110 = Reserved 1101 = Erase General Segment 1100 = Erase Secure Segment 1011 = Reserved 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte If ERASE = 0: 1111 = No operation 1110 = Reserved 1101 = No operation 1100 = No operation 1011 = Reserved 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2007-2012 Microchip Technology Inc. DS70292G-page 73

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits DS70292G-page 74 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 5.6.1 PROGRAMMING ALGORITHM FOR 4. Write the first 64 instructions from data RAM into FLASH PROGRAM MEMORY the program memory buffers (see Example5-2). 5. Write the program block to Flash memory: Programmers can program one row of program Flash memory at a time. To do this, it is necessary to erase a) Set the NVMOP bits to ‘0001’ to configure the 8-row erase page that contains the desired row. for row programming. Clear the ERASE bit The general process is: and set the WREN bit. b) Write 0x55 to NVMKEY. 1. Read eight rows of program memory (512instructions) and store in data RAM. c) Write 0xAA to NVMKEY. 2. Update the program data in RAM with the d) Set the WR bit. The programming cycle desired new data. begins and the CPU stalls for the duration of the write cycle. When the write to Flash mem- 3. Erase the block (see Example5-1): ory is done, the WR bit is cleared a) Set the NVMOP bits (NVMCON<3:0>) to automatically. ‘0010’ to configure for block erase. Set the 6. Repeat steps 4 and 5, using the next available ERASE (NVMCON<6>) and WREN 64 instructions from the block in data RAM by (NVMCON<14>) bits. incrementing the value in TBLPAG, until all b) Write the starting address of the page to be 512instructions are written back to Flash memory. erased into the TBLPAG and W registers. For protection against accidental operations, the write c) Write 0x55 to NVMKEY. initiate sequence for NVMKEY must be used to allow d) Write 0xAA to NVMKEY. any erase or program operation to proceed. After the e) Set the WR bit (NVMCON<15>). The erase programming command has been executed, the user cycle begins and the CPU stalls for the dura- application must wait for the programming time until tion of the erase cycle. When the erase is programming is complete. The two instructions done, the WR bit is cleared automatically. following the start of the programming sequence should be NOPs, as shown in Example5-3. EXAMPLE 5-1: ERASING A PROGRAM MEMORY PAGE ; Set up NVMCON for block erase operation MOV #0x4042, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted © 2007-2012 Microchip Technology Inc. DS70292G-page 75

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch • • • ; 63rd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch EXAMPLE 5-3: INITIATING A PROGRAMMING SEQUENCE DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the NOP ; erase command is asserted DS70292G-page 76 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 6.0 RESETS A simplified block diagram of the Reset module is shown in Figure6-1. Note1: This data sheet summarizes the features Any active source of reset will make the SYSRST sig- of the dsPIC33FJ32GP302/304, nal active. On system Reset, some of the registers dsPIC33FJ64GPX02/X04, and associated with the CPU and peripherals are forced to dsPIC33FJ128GPX02/X04 families of a known Reset state and some are unaffected. devices. It is not intended to be a compre- hensive reference source. To comple- Note: Refer to the specific peripheral section or ment the information in this data sheet, Section3.0 “CPU” of this manual for refer to Section 8. “Reset” (DS70192) of register Reset states. the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the All types of device Reset sets a corresponding status Microchip website (www.microchip.com). bit in the RCON register to indicate the type of Reset (see Register6-1). 2: Some registers and associated bits described in this section may not be avail- A POR clears all the bits, except for the POR bit able on all devices. Refer to Section4.0 (RCON<0>), that are set. The user application can set “Memory Organization” in this data or clear any bit at any time during code execution. The sheet for device-specific register and bit RCON bits only serve as status bits. Setting a particular information. Reset status bit in software does not cause a device Reset to occur. The Reset module combines all reset sources and The RCON register also has other bits associated with controls the device Master Reset Signal, SYSRST. The the Watchdog Timer and device power-saving states. following is a list of device Reset sources: The function of these bits is discussed in other sections • POR: Power-on Reset of this manual. • BOR: Brown-out Reset Note: The status bits in the RCON register • MCLR: Master Clear Pin Reset should be cleared after they are read so • SWR: RESET Instruction that the next RCON register value after a • WDTO: Watchdog Timer Reset device Reset is meaningful. • CM: Configuration Mismatch Reset • TRAPR: Trap Conflict Reset • IOPUWR: Illegal Condition Device Reset - Illegal Opcode Reset - Uninitialized W Register Reset - Security Reset FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle BOR Internal Regulator SYSRST VDD VDD Rise POR Detect Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2007-2012 Microchip Technology Inc. DS70292G-page 77

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 6.1 Reset Resources Many useful resources related to Resets are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 6.1.1 KEY RESOURCES • Section 8. “Resets” (DS70192) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70292G-page 78 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 6.2 Reset Control Registers REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 TRAPR IOPUWR — — — — CM VREGS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred bit 13-10 Unimplemented: Read as ‘0’ bit 9 CM: Configuration Mismatch Flag bit 1 = A configuration mismatch Reset has occurred 0 = A configuration mismatch Reset has not occurred bit 8 VREGS: Voltage Regulator Standby During Sleep bit 1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Standby mode during Sleep bit 7 EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2007-2012 Microchip Technology Inc. DS70292G-page 79

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70292G-page 80 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 6.3 System Reset A warm Reset is the result of all other reset sources, including the RESET instruction. On warm Reset, the The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ device will continue to operate from the current clock X04, and dsPIC33FJ128GPX02/X04 family of devices source as indicated by the Current Oscillator Selection have two types of Reset: bits (COSC<2:0>) in the Oscillator Control register • Cold Reset (OSCCON<14:12>). • Warm Reset The device is kept in a Reset state until the system A cold Reset is the result of a Power-on Reset (POR) power supplies have stabilized at appropriate levels or a Brown-out Reset (BOR). On a cold Reset, the and the oscillator clock is ready. The sequence in FNOSC configuration bits in the FOSC device which this occurs is shown in Figure6-2. configuration register selects the device clock source. TABLE 6-1: OSCILLATOR DELAY Oscillator Oscillator Startup Oscillator Mode PLL Lock Time Total Delay Startup Delay Timer FRC, FRCDIV16, TOSCD — — TOSCD FRCDIVN FRCPLL TOSCD — TLOCK TOSCD + TLOCK XT TOSCD TOST — TOSCD + TOST HS TOSCD TOST — TOSCD + TOST EC — — — — XTPLL TOSCD TOST TLOCK TOSCD + TOST + TLOCK HSPLL TOSCD TOST TLOCK TOSCD + TOST + TLOCK ECPLL — — TLOCK TLOCK SOSC TOSCD TOST — TOSCD + TOST LPRC TOSCD — — TOSCD Note 1: TOSCD = Oscillator Start-up Delay (1.1μs max for FRC, 70μs max for LPRC). Crystal Oscillator start-up times vary with crystal characteristics, load capacitance, etc. 2: TOST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4μs for a 10MHz crystal and TOST=32ms for a 32kHz crystal. 3: TLOCK = PLL lock time (1.5ms nominal), if PLL is enabled. © 2007-2012 Microchip Technology Inc. DS70292G-page 81

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 6-2: SYSTEM RESET TIMING Vbor VBOR VPOR VDD TPOR 1 POR TBOR 2 BOR 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 TFSCM FSCM 5 Device Status Reset Run Time Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay TPOR has elapsed. 2: BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output becomes stable. 3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (TPWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay TPWRT has elapsed, the SYSRST becomes inactive, which in turn enables the selected oscillator to start generating clock cycles. 4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in Table6-1. Refer to Section9.0 “Oscillator Configuration” for more information. 5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay TFSCM elapsed. DS70292G-page 82 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 6-2: OSCILLATOR DELAY Symbol Parameter Value VPOR POR threshold 1.8V nominal TPOR POR extension time 30μs maximum VBOR BOR threshold 2.5V nominal TBOR BOR extension time 100μs maximum TPWRT Programmable power-up time delay 0-128ms nominal TFSCM Fail-Safe Clock Monitor Delay 900μs maximum 6.4.1 Brown-out Reset (BOR) and Note: When the device exits the Reset condi- Power-up timer (PWRT) tion (begins normal operation), the device operating parameters (voltage, The on-chip regulator has a Brown-out Reset (BOR) frequency, temperature, etc.) must be circuit that resets the device when the VDD is too low within their operating ranges, otherwise (VDD < VBOR) for proper device operation. The BOR cir- the device may not function correctly. cuit keeps the device in Reset until VDD crosses VBOR The user application must ensure that threshold and the delay TBOR has elapsed. The delay the delay between the time power is TBOR ensures the voltage regulator output becomes first applied, and the time SYSRST stable. becomes inactive, is long enough to get all operating parameters within The BOR status bit (BOR) in the Reset Control register specification. (RCON<1>) is set to indicate the Brown-out Reset. The device will not run at full speed after a BOR as the 6.4 Power-on Reset (POR) VDD should rise to acceptable levels for full-speed operation. The PWRT provides power-up time delay A Power-on Reset (POR) circuit ensures the device is (TPWRT) to ensure that the system power supplies have reset from power-on. The POR circuit is active until stabilized at the appropriate levels for full-speed VDD crosses the VPOR threshold and the delay TPOR operation before the SYSRST is released. has elapsed. The delay TPOR ensures the internal The power-up timer delay (TPWRT) is programmed by device bias circuits become stable. the Power-on Reset Timer Value Select bits The device supply voltage characteristics must meet (FPWRT<2:0>) in the POR Configuration register the specified starting voltage and rise rate (FPOR<2:0>), which provides eight settings (from 0ms requirements to generate the POR. Refer to to 128ms). Refer to Section27.0 “Special Features” Section30.0 “Electrical Characteristics” for details. for further details. The POR status bit (POR) in the Reset Control register Figure6-3 shows the typical brown-out scenarios. The (RCON<0>) is set to indicate the Power-on Reset. reset delay (TBOR + TPWRT) is initiated each time VDD rises above the VBOR trip point © 2007-2012 Microchip Technology Inc. DS70292G-page 83

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 6-3: BROWN-OUT SITUATIONS VDD VBOR TBOR + TPWRT SYSRST VDD VBOR TBOR + TPWRT SYSRST VDD dips before PWRT expires VDD VBOR TBOR + TPWRT SYSRST 6.5 External Reset (EXTR) The Software Reset (Instruction) Flag (SWR) bit in the Reset Control (RCON<6>) register is set to indicate The external Reset is generated by driving the MCLR the software Reset. pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than 6.7 Watchdog Time-out Reset (WDTO) the minimum pulse-width will generate a Reset. Refer to Section30.0 “Electrical Characteristics” for Whenever a Watchdog time-out occurs, the device will minimum pulse-width specifications. The External asynchronously assert SYSRST. The clock source will Reset (MCLR) Pin (EXTR) bit in the Reset Control remain unchanged. A WDT time-out during Sleep or register (RCON) is set to indicate the MCLR Reset. Idle mode will wake-up the processor, but will not reset the processor. 6.5.0.1 EXTERNAL SUPERVISORY CIRCUIT The Watchdog Timer Time-out Flag (WDTO) bit in the Many systems have external supervisory circuits that Reset Control register (RCON<4>) is set to indicate generate reset signals to Reset multiple devices in the the Watchdog Reset. Refer to Section27.4 system. This external Reset signal can be directly con- “Watchdog Timer (WDT)” for more information on nected to the MCLR pin to Reset the device when the Watchdog Reset. rest of system is Reset. 6.8 Trap Conflict Reset 6.5.0.2 INTERNAL SUPERVISORY CIRCUIT If a lower-priority hard trap occurs while a higher-prior- When using the internal power supervisory circuit to ity trap is being processed, a hard trap conflict Reset Reset the device, the external reset pin (MCLR) should occurs. The hard traps include exceptions of priority be tied directly or resistively to VDD. In this case, the level 13 through level 15, inclusive. The address error MCLR pin will not be used to generate a Reset. The (level13) and oscillator error (level 14) traps fall into external reset pin (MCLR) does not have an internal this category. pull-up and must not be left unconnected. The Trap Reset Flag (TRAPR) bit in the Reset Control register (RCON<15>) is set to indicate the Trap Conflict 6.6 Software RESET Instruction (SWR) Reset. Refer to Section7.0 “Interrupt Controller” for Whenever the RESET instruction is executed, the more information on trap conflict Resets. device will assert SYSRST, placing the device in a special Reset state. This Reset state will not re- initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST is released at the next instruction cycle, and the reset vector fetch will commence. DS70292G-page 84 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 6.9 Configuration Mismatch Reset each program memory section to store the data values. The upper 8 bits should be programmed with 0x3F, To maintain the integrity of the peripheral pin select which is an illegal opcode value. control registers, they are constantly monitored with shadow registers in hardware. If an unexpected 6.10.2 UNINITIALIZED W REGISTER change in any of the registers occur (such as cell dis- RESET turbances caused by ESD or other external events), a configuration mismatch Reset occurs. Any attempts to use the uninitialized W register as an address pointer will Reset the device. The W register The Configuration Mismatch Flag (CM) bit in the Reset array (with the exception of W15) is cleared during all Control register (RCON<9>) is set to indicate the resets and is considered uninitialized until written to. configuration mismatch Reset. Refer to Section11.0 “I/O Ports” for more information on the configuration 6.10.3 SECURITY RESET mismatch Reset. If a Program Flow Change (PFC) or Vector Flow Note: The configuration mismatch feature and Change (VFC) targets a restricted location in a associated reset flag is not available on all protected segment (Boot and Secure Segment), that devices. operation will cause a security Reset. The PFC occurs when the Program Counter is 6.10 Illegal Condition Device Reset reloaded as a result of a Call, Jump, Computed Jump, An illegal condition device Reset occurs due to the Return, Return from Subroutine, or other form of following sources: branch instruction. • Illegal Opcode Reset The VFC occurs when the Program Counter is reloaded with an Interrupt or Trap vector. • Uninitialized W Register Reset • Security Reset Refer to Section27.8 “Code Protection and CodeGuard™ Security” for more information on The Illegal Opcode or Uninitialized W Access Reset Security Reset. Flag (IOPUWR) bit in the Reset Control register (RCON<14>) is set to indicate the illegal condition 6.11 Using the RCON Status Bits device Reset. The user application can read the Reset Control 6.10.1 ILLEGAL OPCODE RESET register (RCON) after any device Reset to determine A device Reset is generated if the device attempts to the cause of the reset. execute an illegal opcode value that is fetched from Note: The status bits in the RCON register program memory. should be cleared after they are read so The illegal opcode Reset function can prevent the that the next RCON register value after a device from executing program memory sections that device Reset will be meaningful. are used to store constant data. To take advantage of the illegal opcode Reset, use only the lower 16 bits of Table6-3 provides a summary of the reset flag bit operation. TABLE 6-3: RESET FLAG BIT OPERATION Flag Bit Set by: Cleared by: TRAPR (RCON<15>) Trap conflict event POR, BOR IOPWR (RCON<14>) Illegal opcode or uninitialized POR, BOR W register access or Security Reset CM (RCON<9>) Configuration Mismatch POR, BOR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET instruction POR, BOR WDTO (RCON<4>) WDT time-out PWRSAV instruction, CLRWDT instruction, POR, BOR SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR, BOR IDLE (RCON<2>) PWRSAV #IDLE instruction POR, BOR BOR (RCON<1>) POR, BOR — POR (RCON<0>) POR — Note: All Reset flag bits can be set or cleared by user software. © 2007-2012 Microchip Technology Inc. DS70292G-page 85

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 86 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 7.0 INTERRUPT CONTROLLER 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE Note1: This data sheet summarizes the features The Alternate Interrupt Vector Table (AIVT) is located of the dsPIC33FJ32GP302/304, after the IVT, as shown in Figure7-1. Access to the dsPIC33FJ64GPX02/X04, and AIVT is provided by the ALTIVT control bit dsPIC33FJ128GPX02/X04 families of (INTCON2<15>). If the ALTIVT bit is set, all interrupt devices. It is not intended to be a compre- and exception processes use the alternate vectors hensive reference source. To comple- instead of the default vectors. The alternate vectors are ment the information in this data sheet, organized in the same manner as the default vectors. refer to Section 32. “Interrupts (Part III)” (DS70214) of the “dsPIC33F/PIC24H The AIVT supports debugging by providing a means to Family Reference Manual”, which is avail- switch between an application and a support able from the Microchip website environment without requiring the interrupt vectors to (www.microchip.com). be reprogrammed. This feature also enables switching between applications for evaluation of different 2: Some registers and associated bits software algorithms at run time. If the AIVT is not described in this section may not be avail- needed, the AIVT should be programmed with the able on all devices. Refer to Section4.0 same addresses used in the IVT. “Memory Organization” in this data sheet for device-specific register and bit 7.2 Reset Sequence information. A device Reset is not a true exception because the The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ interrupt controller is not involved in the Reset process. X04, and dsPIC33FJ128GPX02/X04 interrupt The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ controller reduces the numerous peripheral interrupt X04, and dsPIC33FJ128GPX02/X04 device clears its request signals to a single interrupt request signal to registers in response to a Reset, which forces the PC the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ to zero. The digital signal controller then begins X04, and dsPIC33FJ128GPX02/X04 CPU. program execution at location 0x000000. A GOTO The interrupt controller has the following features: instruction at the Reset address can redirect program • Up to eight processor exceptions and software traps execution to the appropriate start-up routine. • Eight user-selectable priority levels Note: Any unimplemented or unused vector • Interrupt Vector Table (IVT) with up to 118 vectors locations in the IVT and AIVT should be • A unique vector for each interrupt or exception programmed with the address of a default source interrupt handler routine that contains a • Fixed priority within a specified user priority level RESET instruction. • Alternate Interrupt Vector Table (AIVT) for debug support • Fixed interrupt entry and return latencies 7.1 Interrupt Vector Table The Interrupt Vector Table (IVT), shown in Figure7-1, resides in program memory, starting at location 000004h. The IVT contains 126 vectors consisting of eightnonmaskable trap vectors plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority. For example, the interrupt associated with vector 0 takes priority over interrupts at any other vector address. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices implement up to 53 unique interrupts and five nonmaskable traps. These are summarized in Table7-1. © 2007-2012 Microchip Technology Inc. DS70292G-page 87

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 7-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 INTERRUPT VECTOR TABLE Reset – GOTO Instruction 0x000000 Reset – GOTO Address 0x000002 Reserved 0x000004 Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 0x000014 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 0x00007C Interrupt Vector Table (IVT)(1) Interrupt Vector 53 0x00007E ority Interrupt ~Vector 54 0x000080 Pri ~ der ~ Or Interrupt Vector 116 0x0000FC al Interrupt Vector 117 0x0000FE atur Reserved 0x000100 N Reserved 0x000102 g n Reserved si a Oscillator Fail Trap Vector e cr Address Error Trap Vector e D Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 0x000114 Interrupt Vector 1 ~ ~ ~ Alternate Interrupt Vector Table (AIVT)(1) Interrupt Vector 52 0x00017C Interrupt Vector 53 0x00017E Interrupt Vector 54 0x000180 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 0x0001FE Start of Code 0x000200 Note 1: See Table7-1 for the list of implemented interrupt vectors. DS70292G-page 88 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 7-1: INTERRUPT VECTORS Vector IVT Address AIVT Address Interrupt Source Number 0 0x000004 0x000104 Reserved 1 0x000006 0x000106 Oscillator Failure 2 0x000008 0x000108 Address Error 3 0x00000A 0x00010A Stack Error 4 0x00000C 0x00010C Math Error 5 0x00000E 0x00010E DMA Error 6-7 0x000010-0x000012 0x000110-0x000112 Reserved 8 0x000014 0x000114 INT0 – External Interrupt 0 9 0x000016 0x000116 IC1 – Input Capture 1 10 0x000018 0x000118 OC1 – Output Compare 1 11 0x00001A 0x00011A T1 – Timer1 12 0x00001C 0x00011C DMA0 – DMA Channel 0 13 0x00001E 0x00011E IC2 – Input Capture 2 14 0x000020 0x000120 OC2 – Output Compare 2 15 0x000022 0x000122 T2 – Timer2 16 0x000024 0x000124 T3 – Timer3 17 0x000026 0x000126 SPI1E – SPI1 Error 18 0x000028 0x000128 SPI1 – SPI1 Transfer Done 19 0x00002A 0x00012A U1RX – UART1 Receiver 20 0x00002C 0x00012C U1TX – UART1 Transmitter 21 0x00002E 0x00012E ADC1 – ADC 1 22 0x000030 0x000130 DMA1 – DMA Channel 1 23 0x000032 0x000132 Reserved 24 0x000034 0x000134 SI2C1 – I2C1 Slave Events 25 0x000036 0x000136 MI2C1 – I2C1 Master Events 26 0x000038 0x000138 CM – Comparator Interrupt 27 0x00003A 0x00013A CN – Change Notification Interrupt 28 0x00003C 0x00013C INT1 – External Interrupt 1 29 0x00003E 0x00013E Reserved 30 0x000040 0x000140 IC7 – Input Capture 7 31 0x000042 0x000142 IC8 – Input Capture 8 32 0x000044 0x000144 DMA2 – DMA Channel 2 33 0x000046 0x000146 OC3 – Output Compare 3 34 0x000048 0x000148 OC4 – Output Compare 4 35 0x00004A 0x00014A T4 – Timer4 36 0x00004C 0x00014C T5 – Timer5 37 0x00004E 0x00014E INT2 – External Interrupt 2 38 0x000050 0x000150 U2RX – UART2 Receiver 39 0x000052 0x000152 U2TX – UART2 Transmitter 40 0x000054 0x000154 SPI2E – SPI2 Error 41 0x000056 0x000156 SPI2 – SPI2 Transfer Done 42 0x000058 0x000158 C1RX – ECAN1 RX Data Ready 43 0x00005A 0x00015A C1 – ECAN1 Event 44 0x00005C 0x00015C DMA3 – DMA Channel 3 45-52 0x00005E-0x00006C 0x00015E-0x00016C Reserved 53 0x00006E 0x00016E PMP – Parallel Master Port 54 0x000070 0x000170 DMA–DMA Channel 4 © 2007-2012 Microchip Technology Inc. DS70292G-page 89

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Vector IVT Address AIVT Address Interrupt Source Number 55-66 0x000072-0x000088 0x000172-0x000188 Reserved 67 0x00008A 0x00018A DCIE – DCI Error 68 0x00008C 0x00018C DCI–DCI Transfer Done 69 0x00008E 0x00018E DMA5 – DMA Channel 5 70 0x000090 0x000190 RTCC – Real Time Clock 71-72 0x000092-0x000094 0x000192-0x000194 Reserved 73 0x000096 0x000196 U1E – UART1 Error 74 0x000098 0x000198 U2E – UART2 Error 75 0x00009A 0x00019A CRC–CRC Generator Interrupt 76 0x00009C 0x00019C DMA6 – DMA Channel 6 77 0x00009E 0x00019E DMA7 – DMA Channel 7 78 0x0000A0 0x0001A0 C1TX – ECAN1 TX Data Request 79-85 0x0000A2-0x0000AE 0x0001A2-0x0001AE Reserved 86 0x0000B0 0x0001B0 DAC1R – DAC1 Right Data Request 87 0x0000B2 0x0001B2 DAC1L – DAC1 Left Data Request 88-126 0x0000B4-0x0000FE 0x0001B4-0x0001FE Reserved DS70292G-page 90 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 7.3 Interrupt Control and Status 7.3.6 STATUS/CONTROL REGISTERS Registers Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, contain bits that control interrupt functionality. and dsPIC33FJ128GPX02/X04 devices implement a total of 30 registers for the interrupt controller: • The CPU STATUS register, SR, contains the IPL<2:0> bits (SR<7:5>). These bits indicate the • INTCON1 current CPU interrupt priority level. The user • INTCON2 software can change the current CPU priority • IFSx level by writing to the IPL bits. • IECx • The CORCON register contains the IPL3 bit • IPCx which, together with IPL<2:0>, also indicates the • INTTREG current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user 7.3.1 INTCON1 AND INTCON2 software. Global interrupt control functions are controlled from All Interrupt registers are described in Register7-1 INTCON1 and INTCON2. INTCON1 contains the through Register7-31. Interrupt Nesting Disable bit (NSTDIS) as well as the control and status flags for the processor trap sources. 7.4 Interrupts Resources The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Many useful resources related to Interrupts are provided on the main product page of the Microchip Interrupt Vector Table. web site for the devices listed in this data sheet. This 7.3.2 IFSX product page, which can be accessed using this link, contains the latest updates and additional information. The IFS registers maintain all of the interrupt request flags. Each source of interrupt has a status bit, which is Note: In the event you are not able to access the set by the respective peripherals or external signal and product page using the link above, enter is cleared via software. this URL in your browser: http://www.microchip.com/wwwproducts/ 7.3.3 IECX Devices.aspx?dDocName=en532311 The IEC registers maintain all of the interrupt enable 7.4.1 KEY RESOURCES bits. These control bits are used to individually enable interrupts from the peripherals or external signals. • Section 32. “Interrupts (Part III)” (DS70214) • Code Samples 7.3.4 IPCX • Application Notes The IPC registers are used to set the interrupt priority • Software Libraries level for each source of interrupt. Each user interrupt • Webinars source can be assigned to one of eight priority levels. • All related dsPIC33F/PIC24H Family Reference 7.3.5 INTTREG Manuals Sections The INTTREG register contains the associated • Development Tools interrupt vector number and the new CPU interrupt priority level, which are latched into vector number (VECNUM<6:0>) and Interrupt level bits (ILR<3:0>) in the INTTREG register. The new interrupt priority level is the priority of the pending interrupt. The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are listed in Table7-1. For example, the INT0 (External Interrupt 0) is shown as having vector number 8 and a natural order priority of 0. Thus, the INT0IF bit is found in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP bits in the first position of IPC0 (IPC0<2:0>). © 2007-2012 Microchip Technology Inc. DS70292G-page 91

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 7.5 CPU Registers REGISTER 7-1: SR: CPU STATUS REGISTER(1) R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL<2:0>(2,3) RA N OV Z C bit 7 bit 0 Legend: C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: For complete register details, see Register3-1. 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1. REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT DL<2:0> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less Note 1: For complete register details, see Register3-2. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS70292G-page 92 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14 OVAERR: Accumulator A Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A bit 13 OVBERR: Accumulator B Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B bit 10 OVATE: Accumulator A Overflow Trap Enable bit 1 = Trap overflow of Accumulator A 0 = Trap disabled bit 9 OVBTE: Accumulator B Overflow Trap Enable bit 1 = Trap overflow of Accumulator B 0 = Trap disabled bit 8 COVTE: Catastrophic Overflow Trap Enable bit 1 = Trap on catastrophic overflow of Accumulator A or B enabled 0 = Trap disabled bit 7 SFTACERR: Shift Accumulator Error Status bit 1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift bit 6 DIV0ERR: Arithmetic Error Status bit 1 = Math error trap was caused by a divide by zero 0 = Math error trap was not caused by a divide by zero bit 5 DMACERR: DMA Controller Error Status bit 1 = DMA controller error trap has occurred 0 = DMA controller error trap has not occurred bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred © 2007-2012 Microchip Technology Inc. DS70292G-page 93

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70292G-page 94 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table 0 = Use standard (default) vector table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-3 Unimplemented: Read as ‘0’ bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2007-2012 Microchip Technology Inc. DS70292G-page 95

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 SPI1EIF: SPI1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70292G-page 96 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007-2012 Microchip Technology Inc. DS70292G-page 97

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC8IF IC7IF — INT1IF CNIF CMIF MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 DMA2IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 IC8IF: Input Capture Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 IC7IF: Input Capture Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70292G-page 98 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) bit 2 CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007-2012 Microchip Technology Inc. DS70292G-page 99

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — DMA4IF PMPIF — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DMA3IF C1IF(1) C1RXIF(1) SPI2IF SPI2EIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA4IF: DMA Channel 4 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-5 Unimplemented: Read as ‘0’ bit 4 DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 C1IF: ECAN1 Event Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: Interrupts are disabled on devices without ECAN™ modules. DS70292G-page 100 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — RTCIF DMA5IF DCIIF DCIEIF — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock and Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 DMA5IF: DMA Channel 5 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 DCIIF: DCI Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 DCIEIF: DCI Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10-0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. DS70292G-page 101

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 DAC1LIF(2) DAC1RIF(2) — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — C1TXIF(1) DMA7IF DMA6IF CRCIF U2EIF U1EIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DAC1LIF: DAC Left Channel Interrupt Flag Status bit(2) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 DAC1RIF: DAC Right Channel Interrupt Flag Status bit(2) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-7 Unimplemented: Read as ‘0’ bit 6 C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 DMA7IF: DMA Channel 7 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 DMA6IF: DMA Channel 6 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U2EIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ Note 1: Interrupts are disabled on devices without ECAN™ modules. 2: Interrupts are disabled on devices without Audio DAC modules. DS70292G-page 102 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 SPI1IE: SPI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 SPI1EIE: SPI1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007-2012 Microchip Technology Inc. DS70292G-page 103

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Flag Status bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70292G-page 104 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC8IE IC7IE — INT1IE CNIE CMIE MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 DMA2IE: DMA Channel 2 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 IC8IE: Input Capture Channel 8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 IC7IE: Input Capture Channel 7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 Unimplemented: Read as ‘0’ bit 4 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007-2012 Microchip Technology Inc. DS70292G-page 105

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 2 CMIE: Comparator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70292G-page 106 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — DMA4IE PMPIE — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DMA3IE C1IE(1) C1RXIE(1) SPI2IE SPI2EIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA4IE: DMA Channel 4 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 PMPIE: Parallel Master Port Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12-5 Unimplemented: Read as ‘0’ bit 4 DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request has enabled bit 3 C1IE: ECAN1 Event Interrupt Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note 1: Interrupts are disabled on devices without ECAN™ modules. © 2007-2012 Microchip Technology Inc. DS70292G-page 107

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — RTCIE DMA5IE DCIIE DCIEIE — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock and Calendar Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 DCIIE: DCI Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 DCIEIE: DCI Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10-0 Unimplemented: Read as ‘0’ DS70292G-page 108 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 DAC1LIE(2) DAC1RIE(2) — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — C1TXIE(1) DMA7IE DMA6IE CRCIE U2EIE U1EIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DAC1LIE: DAC Left Channel Interrupt Enable bit(2) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 14 DAC1RIE: DAC Right Channel Interrupt Enable bit(2) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13-7 Unimplemented: Read as ‘0’ bit 6 C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit(1) 1 = Interrupt request occurred 0 = Interrupt request not occurred bit 5 DMA7IE: DMA Channel 7 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 DMA6IE: DMA Channel 6 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 U2EIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: Interrupts are disabled on devices without ECAN™ modules. 2: Interrupts are disabled on devices without Audio DAC modules. © 2007-2012 Microchip Technology Inc. DS70292G-page 109

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP<2:0> — OC1IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP<2:0> — INT0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70292G-page 110 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP<2:0> — OC2IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC2IP<2:0> — DMA0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007-2012 Microchip Technology Inc. DS70292G-page 111

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP<2:0> — SPI1IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI1EIP<2:0> — T3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70292G-page 112 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — DMA1IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP<2:0> — U1TXIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007-2012 Microchip Technology Inc. DS70292G-page 113

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP<2:0> — CMIP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP<2:0> — SI2C1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 CMIP<2:0>: Comparator Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70292G-page 114 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC8IP<2:0> — IC7IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007-2012 Microchip Technology Inc. DS70292G-page 115

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T4IP<2:0> — OC4IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC3IP<2:0> — DMA2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70292G-page 116 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP<2:0> — U2RXIP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP<2:0> — T5IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007-2012 Microchip Technology Inc. DS70292G-page 117

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — C1IP<2:0>(1) — C1RXIP<2:0>(1) bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP<2:0> — SPI2EIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 C1IP<2:0>: ECAN1 Event Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: Interrupts are disabled on devices without ECAN™ modules. DS70292G-page 118 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — DMA3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007-2012 Microchip Technology Inc. DS70292G-page 119

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-25: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — DMA4IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — PMPIP<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA4IP<2:0>: DMA Channel 4 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 PMPIP<2:0>: Parallel Master Port Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70292G-page 120 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-26: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — DCIEIP<2:0> — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 DCIEIP<2:0>: DCI Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. DS70292G-page 121

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-27: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — DMA5IP<2:0> — DCIIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Flag Status bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 DMA5IP<2:0>: DMA Channel 5 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 DCIIP<2:0>: DCI Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70292G-page 122 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 7-28: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP<2:0> — U2EIP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1EIP<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP<2:0>: CRC Generator Error Interrupt Flag Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2EIP<2:0>: UART2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. DS70292G-page 123

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-29: IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — C1TXIP<2:0>(1) bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — DMA7IP<2:0> — DMA6IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 C1TXIP<2:0>: ECAN1 Transmit Data Request Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 DMA7IP<2:0>: DMA Channel 7 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: Interrupts are disabled on devices without ECAN™ modules. DS70292G-page 124 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-30: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — DAC1LIP<2:0>(1) — DAC1RIP<2:0>(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 DAC1LIP<2:0>: DAC Left Channel Interrupt Flag Status bit(1) 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 DAC1RIP<2:0>: DAC Right Channel Interrupt Flag Status bit(1) 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ Note 1: Interrupts are disabled on devices without Audio DAC modules. © 2007-2012 Microchip Technology Inc. DS70292G-page 125

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-31: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ILR<3:0> bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70292G-page 126 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 7.6 Interrupt Setup Procedures 7.6.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, 7.6.1 INITIALIZATION except that the appropriate trap status flag in the To configure an interrupt source at initialization: INTCON1 register must be cleared to avoid re-entry into the TSR. 1. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. 7.6.4 INTERRUPT DISABLE 2. Select the user-assigned priority level for the All user interrupts can be disabled using this interrupt source by writing the control bits in the procedure: appropriate IPCx register. The priority level depends on the specific application and type of 1. Push the current SR value onto the software interrupt source. If multiple priority levels are not stack using the PUSH instruction. desired, the IPCx register control bits for all 2. Force the CPU to priority level 7 by inclusive enabled interrupt sources can be programmed ORing the value OEh with SRL. to the same non-zero value. To enable user interrupts, the POP instruction can be Note: At a device Reset, the IPCx registers are used to restore the previous SR value. initialized such that all user interrupt sources are assigned to priority level 4. Note: Only user interrupts with a priority level of 7 or lower can be disabled. Trap sources 3. Clear the interrupt flag status bit associated with (level 8-level 15) cannot be disabled. the peripheral in the associated IFSx register. The DISI instruction provides a convenient way to 4. Enable the interrupt source by setting the inter- disable interrupts of priority levels 1-6 for a fixed period rupt enable control bit associated with the of time. Level 7 interrupt sources are not disabled by source in the appropriate IECx register. the DISI instruction. 7.6.2 INTERRUPT SERVICE ROUTINE The method used to declare an ISR and initialize the IVT with the correct vector address depends on the programming language (C or assembler) and the language development tool suite used to develop the application. In general, the user application must clear the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, the program re-enters the ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2007-2012 Microchip Technology Inc. DS70292G-page 127

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 128 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 8.0 DIRECT MEMORY ACCESS Direct Memory Access (DMA) is a very efficient (DMA) mechanism of copying data between peripheral SFRs (e.g., UART Receive register, Input Capture 1 buffer), and buffers or variables stored in RAM, with minimal Note1: This data sheet summarizes the features CPU intervention. The DMA controller can of the dsPIC33FJ32GP302/304, automatically copy entire blocks of data without dsPIC33FJ64GPX02/X04, and requiring the user software to read or write the dsPIC33FJ128GPX02/X04 families of peripheral Special Function Registers (SFRs) every devices. It is not intended to be a compre- time a peripheral interrupt occurs. The DMA controller hensive reference source. To comple- uses a dedicated bus for data transfers and therefore, ment the information in this data sheet, does not steal cycles from the code execution flow of refer to Section 38. “Direct Memory the CPU. To exploit the DMA capability, the Access (DMA) (Part III)” (DS70215) of corresponding user buffers or variables must be the “dsPIC33F/PIC24H Family Reference located in DMA RAM. Manual”, which is available from the Microchip website (www.microchip.com). The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 peripherals that 2: Some registers and associated bits can utilize DMA are listed in Table8-1. described in this section may not be avail- able on all devices. Refer to Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. TABLE 8-1: DMA CHANNEL TO PERIPHERAL ASSOCIATIONS DMAxPAD Register DMAxPAD Register DMAxREQ Register Peripheral to DMA Association Values to Read from Values to Write to IRQSEL<6:0> Bits Peripheral Peripheral INT0 – External Interrupt 0 0000000 — — IC1 – Input Capture 1 0000001 0x0140 (IC1BUF) — OC1 – Output Compare 1 Data 0000010 — 0x0182 (OC1R) OC1 – Output Compare 1 Secondary Data 0000010 — 0x0180 (OC1RS) IC2 – Input Capture 2 0000101 0x0144 (IC2BUF) — OC2 – Output Compare 2 Data 0000110 — 0x0188 (OC2R) OC2 – Output Compare 2 Secondary Data 0000110 — 0x0186 (OC2RS) TMR2 – Timer2 0000111 — — TMR3 – Timer3 0001000 — — SPI1 – Transfer Done 0001010 0x0248 (SPI1BUF) 0x0248 (SPI1BUF) UART1RX – UART1 Receiver 0001011 0x0226 (U1RXREG) — UART1TX – UART1 Transmitter 0001100 — 0x0224 (U1TXREG) ADC1 – ADC1 convert done 0001101 0x0300 (ADC1BUF0) — UART2RX – UART2 Receiver 0011110 0x0236 (U2RXREG) — UART2TX – UART2 Transmitter 0011111 — 0x0234 (U2TXREG) SPI2 – Transfer Done 0100001 0x0268 (SPI2BUF) 0x0268 (SPI2BUF) ECAN1 – RX Data Ready 0100010 0x0440 (C1RXD) — PMP – Master Data Transfer 0101101 0x0608 (PMDIN1) 0x0608 (PMDIN1) ECAN1 – TX Data Request 1000110 — 0x0442 (C1TXD) DCI – Codec Transfer Done 0111100 0x0290 (RXBUF0) 0x0298 (TXBUF0) DAC1 – Right Data Output 1001110 — 0x03F6 (DAC1RDAT) DAC2 – Left Data Output 1001111 — 0x03F8 (DAC1LDAT) © 2007-2012 Microchip Technology Inc. DS70292G-page 129

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 The DMA controller features eight identical data • Byte or word transfers transfer channels. • Fixed priority channel arbitration • Manual (software) or Automatic (peripheral DMA Each channel has its own set of control and status requests) transfer initiation registers. Each DMA channel can be configured to copy data either from buffers stored in dual port DMA • One-Shot or Auto-Repeat block transfer modes RAM to peripheral SFRs, or from peripheral SFRs to • Ping-Pong mode (automatic switch between two buffers in DMA RAM. DPSRAM start addresses after each block trans- fer complete) The DMA controller supports the following features: • DMA request for each channel can be selected • Eight DMA channels from any supported interrupt source • Register Indirect With Post-increment Addressing • Debug support features mode For each DMA channel, a DMA interrupt request is • Register Indirect Without Post-increment generated when a block transfer is complete. Addressing mode Alternatively, an interrupt can be generated when half of • Peripheral Indirect Addressing mode (peripheral the block has been filled. generates destination address) • CPU interrupt after half or full block transfer complete FIGURE 8-1: TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS Peripheral Indirect Address DMA Controller DMA Ready SRAM DMA RAM DMAontrol ChDaMnnAels Peripheral 3 C PORT 1 PORT 2 CPU DMA SRAM X-Bus DMA DS Bus CPU Peripheral DS Bus CPU DMA CPU DMA Non-DMA DMA DMA CPU Ready Ready Ready Peripheral Peripheral 1 Peripheral 2 Note: CPU and DMA address buses are not shown for clarity. DS70292G-page 130 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 8.1 DMA Resources 8.2 DMAC Registers Many useful resources related to the CPU are provided Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7) on the main product page of the Microchip web site for contains the following registers: the devices listed in this data sheet. This product page, • A 16-bit DMA Channel Control register which can be accessed using this link, contains the (DMAxCON) latest updates and additional information. • A 16-bit DMA Channel IRQ Select register Note: In the event you are not able to access the (DMAxREQ) product page using the link above, enter • A 16-bit DMA RAM Primary Start Address register this URL in your browser: (DMAxSTA) http://www.microchip.com/wwwproducts/ • A 16-bit DMA RAM Secondary Start Address Devices.aspx?dDocName=en532311 register (DMAxSTB) • A 16-bit DMA Peripheral Address register 8.1.1 KEY RESOURCES (DMAxPAD) • Section 38. “Direct Memory Access (DMA) • A 10-bit DMA Transfer Count register (DMAxCNT) (Part III)” (DS70215) An additional pair of status registers, DMACS0 and • Code Samples DMACS1, are common to all DMAC channels. • Application Notes DMACS0 contains the DMA RAM and SFR write colli- • Software Libraries sion flags, XWCOLx and PWCOLx, respectively. • Webinars DMACS1 indicates DMA channel and Ping-Pong mode • All related dsPIC33F/PIC24H Family Reference status. Manuals Sections The DMAxCON, DMAxREQ, DMAxPAD and • Development Tools DMAxCNT are all conventional read/write registers. Reads of DMAxSTA or DMAxSTB reads the contents of the DMA RAM Address register. Writes to DMAx- STA or DMAxSTB write to the registers. This allows the user to determine the DMA buffer pointer value (address) at any time. The interrupt flags (DMAxIF) are located in an IFSx register in the interrupt controller. The corresponding interrupt enable control bits (DMAxIE) are located in an IECx register in the interrupt controller, and the cor- responding interrupt priority control bits (DMAxIP) are located in an IPCx register in the interrupt controller. © 2007-2012 Microchip Technology Inc. DS70292G-page 131

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 8.3 DMA Control Registers REGISTER 8-1: DMAxCON: DMA CHANNEL x CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CHEN SIZE DIR HALF NULLW — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — — AMODE<1:0> — — MODE<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHEN: Channel Enable bit 1 = Channel enabled 0 = Channel disabled bit 14 SIZE: Data Transfer Size bit 1 = Byte 0 = Word bit 13 DIR: Transfer Direction bit (source/destination bus select) 1 = Read from DMA RAM address, write to peripheral address 0 = Read from peripheral address, write to DMA RAM address bit 12 HALF: Early Block Transfer Complete Interrupt Select bit 1 = Initiate block transfer complete interrupt when half of the data has been moved 0 = Initiate block transfer complete interrupt when all of the data has been moved bit 11 NULLW: Null Data Peripheral Write Mode Select bit 1 = Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear) 0 = Normal operation bit 10-6 Unimplemented: Read as ‘0’ bit 5-4 AMODE<1:0>: DMA Channel Operating Mode Select bits 11 = Reserved (acts as Peripheral Indirect Addressing mode) 10 = Peripheral Indirect Addressing mode 01 = Register Indirect without Post-Increment mode 00 = Register Indirect with Post-Increment mode bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 MODE<1:0>: DMA Channel Operating Mode Select bits 11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer) 10 = Continuous, Ping-Pong modes enabled 01 = One-Shot, Ping-Pong modes disabled 00 = Continuous, Ping-Pong modes disabled DS70292G-page 132 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 8-2: DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 FORCE(1) — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IRQSEL6<6:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FORCE: Force DMA Transfer bit(1) 1 = Force a single DMA transfer (Manual mode) 0 = Automatic DMA transfer initiation by DMA request bit 14-7 Unimplemented: Read as ‘0’ bit 6-0 IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits(2) 1111111 = DMAIRQ127 selected to be Channel DMAREQ . . . 0000000 = DMAIRQ0 selected to be Channel DMAREQ Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. 2: Refer to Table7-1 for a complete listing of IRQ numbers for all interrupt sources. © 2007-2012 Microchip Technology Inc. DS70292G-page 133

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 8-3: DMAxSTA: DMA CHANNEL x RAM START ADDRESS REGISTER A(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STA<15:0>: Primary DMA RAM Start Address bits (source or destination) Note 1: A read of this address register returns the current contents of the DMA RAM Address register, not the con- tents written to STA<15:0>. If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. REGISTER 8-4: DMAxSTB: DMA CHANNEL x RAM START ADDRESS REGISTER B(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STB<15:0>: Secondary DMA RAM Start Address bits (source or destination) Note 1: A read of this address register returns the current contents of the DMA RAM Address register, not the con- tents written to STB<15:0>. If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. DS70292G-page 134 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 8-5: DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PAD<15:0>: Peripheral Address Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. REGISTER 8-6: DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — CNT<9:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 CNT<9:0>: DMA Transfer Count Register bits(2) Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: Number of DMA transfers = CNT<9:0> + 1. © 2007-2012 Microchip Technology Inc. DS70292G-page 135

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWCOL7: Channel 7 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 14 PWCOL6: Channel 6 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 13 PWCOL5: Channel 5 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 12 PWCOL4: Channel 4 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 11 PWCOL3: Channel 3 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 10 PWCOL2: Channel 2 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 9 PWCOL1: Channel 1 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 8 PWCOL0: Channel 0 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 7 XWCOL7: Channel 7 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 6 XWCOL6: Channel 6 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 5 XWCOL5: Channel 5 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 4 XWCOL4: Channel 4 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected DS70292G-page 136 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 (CONTINUED) bit 3 XWCOL3: Channel 3 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 2 XWCOL2: Channel 2 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected © 2007-2012 Microchip Technology Inc. DS70292G-page 137

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 8-8: DMACS1: DMA CONTROLLER STATUS REGISTER 1 U-0 U-0 U-0 U-0 R-1 R-1 R-1 R-1 — — — — LSTCH<3:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 LSTCH<3:0>: Last DMA Channel Active bits 1111 = No DMA transfer has occurred since system Reset 1110-1000 = Reserved 0111 = Last data transfer was by DMA Channel 7 0110 = Last data transfer was by DMA Channel 6 0101 = Last data transfer was by DMA Channel 5 0100 = Last data transfer was by DMA Channel 4 0011 = Last data transfer was by DMA Channel 3 0010 = Last data transfer was by DMA Channel 2 0001 = Last data transfer was by DMA Channel 1 0000 = Last data transfer was by DMA Channel 0 bit 7 PPST7: Channel 7 Ping-Pong Mode Status Flag bit 1 = DMA7STB register selected 0 = DMA7STA register selected bit 6 PPST6: Channel 6 Ping-Pong Mode Status Flag bit 1 = DMA6STB register selected 0 = DMA6STA register selected bit 5 PPST5: Channel 5 Ping-Pong Mode Status Flag bit 1 = DMA5STB register selected 0 = DMA5STA register selected bit 4 PPST4: Channel 4 Ping-Pong Mode Status Flag bit 1 = DMA4STB register selected 0 = DMA4STA register selected bit 3 PPST3: Channel 3 Ping-Pong Mode Status Flag bit 1 = DMA3STB register selected 0 = DMA3STA register selected bit 2 PPST2: Channel 2 Ping-Pong Mode Status Flag bit 1 = DMA2STB register selected 0 = DMA2STA register selected bit 1 PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMA1STB register selected 0 = DMA1STA register selected bit 0 PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMA0STB register selected 0 = DMA0STA register selected DS70292G-page 138 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 8-9: DSADR: MOST RECENT DMA RAM ADDRESS R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits © 2007-2012 Microchip Technology Inc. DS70292G-page 139

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 140 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 9.0 OSCILLATOR CONFIGURATION • External and internal oscillator options as clock sources Note 1: This data sheet summarizes the • An on-chip Phase-Locked Loop (PLL) to scale the features of the dsPIC33FJ32GP302/304, internal operating frequency to the required dsPIC33FJ64GPX02/X04, and system clock frequency dsPIC33FJ128GPX02/X04 families of • An internal FRC oscillator that can also be used devices. It is not intended to be a with the PLL, thereby allowing full-speed operation comprehensive reference source. To without any external clock generation hardware complement the information in this data • Clock switching between various clock sources sheet, refer to Section 39. “Oscillator • Programmable clock postscaler for system power (Part III)” (DS70216) of the “dsPIC33F/ savings PIC24H Family Reference Manual”, • A Fail-Safe Clock Monitor (FSCM) that detects which is available from the Microchip clock failure and takes fail-safe measures website (www.microchip.com). • An Oscillator Control register (OSCCON) 2: Some registers and associated bits • Non-volatile Configuration bits for main oscillator described in this section may not be avail- selection able on all devices. Refer to Section4.0 • An auxiliary crystal oscillator for Audio DAC “Memory Organization” in this data sheet for device-specific register and bit A simplified diagram of the oscillator system is shown information. in Figure9-1. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 oscillator system provides: FIGURE 9-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator OSC1 POSCCLK XT, HS, EC DOZE<2:0> S2 R(2) S3 XTPLL, HSPLL, S1 PLL ECPLL, FRCPLL S1/S3 ZE FCY(3) OSC2 FOSC(1) O POSCMD<1:0> D OsFcRillCator CDIV FRCDIVN S7 ÷2 FP(3) R F FOSC TUN<5:0> FRCDIV<2:0> FRCDIV16 S6 ÷16 FRC S0 LPRC LPRC Oscillator S5 Secondary Oscillator SOSC SOSCO S4 LPOSCEN SOSCI Clock Fail Clock Switch Reset S7 NOSC<2:0>FNOSC<2:0> WDT, PWRT, FSCM Timer1 3.5 MHz ≤ AUX_OSC_FIN ≤ 10 MHz Auxiliary Oscillator POSCCLK FOSC(1) 1 0 AOSCCLK ACLK DAC ÷N 0 1 AOSCMD<1:0> ASRCSEL SELACK APSTSCLR<2:0> Note 1: See Figure9-2 for PLL details. 2: If the Oscillator is used with XT or HS modes, an extended parallel resistor with the value of 1 MΩ must be connected. 3: The term FP refers to the clock source for all the peripherals, while FCY refers to the clock source for the CPU. Throughout this document FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode is used in any ratio other than 1:1, which is the default. © 2007-2012 Microchip Technology Inc. DS70292G-page 141

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 9.1 CPU Clocking System 9.1.2 SYSTEM CLOCK SELECTION The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ The oscillator source used at a device Power-on X04, and dsPIC33FJ128GPX02/X04 devices provide Reset event is selected using Configuration bit seven system clock options: settings. The oscillator Configuration bit settings are located in the Configuration registers in the program • Fast RC (FRC) Oscillator memory. (Refer to Section27.1 “Configuration • FRC Oscillator with Phase-Locked Loop (PLL) Bits” for further details.) The Initial Oscillator • Primary (XT, HS or EC) Oscillator Selection Configuration bits, FNOSC<2:0> • Primary Oscillator with PLL (FOSCSEL<2:0>), and the Primary Oscillator Mode Select Configuration bits, POSCMD<1:0> • Secondary (LP) Oscillator (FOSC<1:0>), select the oscillator source that is used • Low-Power RC (LPRC) Oscillator at a Power-on Reset. The FRC primary oscillator is • FRC Oscillator with postscaler the default (unprogrammed) selection. 9.1.1 SYSTEM CLOCK SOURCES The Configuration bits allow users to choose among 12 different clock modes, shown in Table9-1. The Fast RC (FRC) internal oscillator runs at a nominal frequency of 7.37 MHz. User software can tune the The output of the oscillator (or the output of the PLL if FRC frequency. User software can optionally specify a a PLL mode has been selected) FOSC is divided by 2 to factor (ranging from 1:2 to 1:256) by which the FRC generate the device instruction clock (FCY) and clock frequency is divided. This factor is selected using peripheral clock time base (FP). FCY defines the operating speed of the device, and speeds up to 40 the FRCDIV<2:0> bits (CLKDIV<10:8>). MHz are supported by the dsPIC33FJ32GP302/304, The primary oscillator can use one of the following as dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ its clock source: X04 architecture. • Crystal (XT): Crystals and ceramic resonators in Instruction execution speed or device operating the range of 3 MHz to 10 MHz. The crystal is connected to the OSC1 and OSC2 pins. frequency, FCY, is given by: • High-Speed Crystal (HS): Crystals in the range of EQUATION 9-1: DEVICE OPERATING 10 MHz to 40 MHz. The crystal is connected to FREQUENCY the OSC1 and OSC2 pins. • External Clock (EC): External clock signal is directly applied to the OSC1 pin. FCY = F----O----S---C-- 2 The secondary (LP) oscillator is designed for low power and uses a 32.768 kHz crystal or ceramic resonator. The LP oscillator uses the SOSCI and SOSCO pins. 9.1.3 AUXILIARY OSCILLATOR The Low-Power RC (LPRC) internal oscIllator runs at a The Auxiliary Oscillator (AOSC) can be used for periph- nominal frequency of 32.768 kHz. It is also used as a erals that need to operate at a frequency unrelated to reference clock by the Watchdog Timer (WDT) and the system clock such as a Digital-to-Analog Converter Fail-Safe Clock Monitor (FSCM). (DAC). The clock signals generated by the FRC and primary The Auxiliary Oscillator can use one of the following as oscillators can be optionally applied to an on-chip PLL its clock source: to provide a wide range of output frequencies for device • Crystal (XT): Crystal and ceramic resonators in operation. PLL configuration is described in the range of 3MHz to 10MHz. The crystal is Section9.1.4 “PLL Configuration”. connected to the SOCI and SOSCO pins. The FRC frequency depends on the FRC accuracy • High-Speed Crystal (HS): Crystals in the range of (see Table30-19) and the value of the FRC Oscillator 10 to 40MHz. The crystal is connected to the Tuning register (see Register9-4). SOSCI and SOSCO pins. • External Clock (EC): External clock signal up to 64MHz. The external clock signal is directly applied to SOSCI pin. DS70292G-page 142 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 9.1.4 PLL CONFIGURATION For a primary oscillator or FRC oscillator, output ‘FIN’, the PLL output ‘FOSC’ is given by: The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in EQUATION 9-2: FOSC CALCULATION selecting the device operating speed. A block diagram of the PLL is shown in Figure9-2. FOSC = FIN• ⎝⎛N-----1----M•-----N-----2--⎠⎞ The output of the primary oscillator or FRC, denoted as ‘FIN’, is divided down by a prescale factor (N1) of 2, 3, ... or 33 before being provided to the PLL’s Voltage For example, suppose a 10 MHz crystal is being used Controlled Oscillator (VCO). The input to the VCO must with the selected oscillator mode of XT with PLL. be selected in the range of 0.8 MHz to 8 MHz. The • If PLLPRE<4:0> = 0, then N1 = 2. This yields a prescale factor ‘N1’ is selected using the VCO input of 10/2 = 5 MHz, which is within the PLLPRE<4:0> bits (CLKDIV<4:0>). acceptable range of 0.8-8 MHz. The PLL Feedback Divisor, selected using the • If PLLDIV<8:0> = 0x1E, then M = 32. This yields a PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M,’ VCO output of 5 x 32 = 160 MHz, which is within by which the input to the VCO is multiplied. This factor the 100-200 MHz ranged needed. must be selected such that the resulting VCO output • If PLLPOST<1:0> = 0, then N2 = 2. This provides frequency is in the range of 100 MHz to 200 MHz. a Fosc of 160/2 = 80 MHz. The resultant device The VCO output is further divided by a postscale factor operating speed is 80/2 = 40 MIPS. ‘N2.’ This factor is selected using the PLLPOST<1:0> bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and EQUATION 9-3: XT WITH PLL MODE must be selected such that the PLL output frequency EXAMPLE (FOSC) is in the range of 12.5 MHz to 80 MHz, which generates device operating speeds of 6.25-40 MIPS. FCY = F----O--2--S---C-- = 12---⎝⎛-1--0---0---0---20---0--•--0---02----•-----3---2--⎠⎞ =40MIPS FIGURE 9-2: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 PLL BLOCK DIAGRAM FVCO (1) (1) 0.8-8.0 MHz(1) 100-200 MHz 12.5-80 MHz Source (Crystal, External Clock or Internal RC) PLLPRE X VCO PLLPOST FOSC PLLDIV N1 N2 Divide by Divide by 2-33 M 2, 4, 8 Divide by 2-513 Note1: This frequency range must be satisfied at all times. © 2007-2012 Microchip Technology Inc. DS70292G-page 143

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION See Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> Note Fast RC Oscillator with Divide-by-N Internal xx 111 1, 2 (FRCDIVN) Fast RC Oscillator with Divide-by-16 Internal xx 110 1 (FRCDIV16) Low-Power RC Oscillator (LPRC) Internal xx 101 1 Secondary (Timer1) Oscillator (SOSC) Secondary xx 100 1 Primary Oscillator (HS) with PLL Primary 10 011 — (HSPLL) Primary Oscillator (XT) with PLL Primary 01 011 — (XTPLL) Primary Oscillator (EC) with PLL Primary 00 011 1 (ECPLL) Primary Oscillator (HS) Primary 10 010 — Primary Oscillator (XT) Primary 01 010 — Primary Oscillator (EC) Primary 00 010 1 Fast RC Oscillator with PLL (FRCPLL) Internal xx 001 1 Fast RC Oscillator (FRC) Internal xx 000 1 Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. 9.2 Oscillator Resources Many useful resources related to the Oscillator are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 9.2.1 KEY RESOURCES • Section 39. “Oscillator (Part III)” (DS70216) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70292G-page 144 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 9.3 Oscillator Control Registers REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,3) U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y — COSC<2:0> — NOSC<2:0>(2) bit 15 bit 8 R/W-0 R/W-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0 CLKLOCK IOLOCK LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 Legend: y = Value set from Configuration bits on POR C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only) 111 = Fast RC oscillator (FRC) with Divide-by-n 110 = Fast RC oscillator (FRC) with Divide-by-16 101 = Low-Power RC oscillator (LPRC) 100 = Secondary oscillator (SOSC) 011 = Primary oscillator (XT, HS, EC) with PLL 010 = Primary oscillator (XT, HS, EC) 001 = Fast RC Oscillator (FRC) with divide-by-N and PLL (FRCDIVN + PLL) 000 = Fast RC oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2) 111 = Fast RC oscillator (FRC) with Divide-by-n 110 = Fast RC oscillator (FRC) with Divide-by-16 101 = Low-Power RC oscillator (LPRC) 100 = Secondary oscillator (SOSC) 011 = Primary oscillator (XT, HS, EC) with PLL 010 = Primary oscillator (XT, HS, EC) 001 = Fast RC Oscillator (FRC) with divide-by-N and PLL (FRCDIVN + PLL) 000 = Fast RC oscillator (FRC) bit 7 CLKLOCK: Clock Lock Enable bit If clock switching is enabled and FSCM is disabled, FCKSM<1:0>(FOSC<7:6>) = 0b01 1 = Clock switching is disabled, system clock source is locked 0 = Clock switching is enabled, system clock source can be modified by clock switching bit 6 IOLOCK: Peripheral Pin Select Lock bit 1 = Peripherial pin select is locked, write to peripheral pin select registers not allowed 0 = Peripherial pin select is not locked, write to peripheral pin select registers allowed bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled bit 4 Unimplemented: Read as ‘0’ Note 1: Writes to this register require an unlock sequence. Refer to Section 39. “Oscillator (Part III)” (DS70216) in the “dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip website) for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). © 2007-2012 Microchip Technology Inc. DS70292G-page 145

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,3) (CONTINUED) bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Writes to this register require an unlock sequence. Refer to Section 39. “Oscillator (Part III)” (DS70216) in the “dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip website) for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). DS70292G-page 146 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER(2) R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 ROI DOZE<2:0> DOZEN(1) FRCDIV<2:0> bit 15 bit 8 R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PLLPOST<1:0> — PLLPRE<4:0> bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clears the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits 111 = FCY/128 110 = FCY/64 101 = FCY/32 100 = FCY/16 011 = FCY/8 (default) 010 = FCY/4 001 = FCY/2 000 = FCY/1 bit 11 DOZEN: Doze Mode Enable bit(1) 1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock/peripheral clock ratio forced to 1:1 bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits 111 = FRC divide by 256 110 = FRC divide by 64 101 = FRC divide by 32 100 = FRC divide by 16 011 = FRC divide by 8 010 = FRC divide by 4 001 = FRC divide by 2 000 = FRC divide by 1 (default) bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler) 11 = Output/8 10 = Reserved 01 = Output/4 (default) 00 = Output/2 bit 5 Unimplemented: Read as ‘0’ bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 11111 = Input/33 • • • 00000 = Input/2 (default) 00001 = Input/3 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. 2: This register is reset only on a Power-on Reset (POR). © 2007-2012 Microchip Technology Inc. DS70292G-page 147

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV<8> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 111111111 = 513 • • • 000110000 = 50 (default) • • • 000000010 = 4 000000001 = 3 000000000 = 2 Note 1: This register is reset only on a Power-on Reset (POR). DS70292G-page 148 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 9-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER(2) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 111111 = Center frequency -0.375% (7.345 MHz) • • • 100001 = Center frequency -11.625% (6.52 MHz) 100000 = Center frequency -12% (6.49 MHz) 011111 = Center frequency +11.625% (8.23 MHz) 011110 = Center frequency +11.25% (8.20 MHz) • • • 000001 = Center frequency +0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal) Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. 2: This register is reset only on a Power-on Reset (POR). © 2007-2012 Microchip Technology Inc. DS70292G-page 149

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 9-5: ACLKCON: AUXILIARY CONTROL REGISTER(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — SELACLK AOSCMD<1:0> APSTSCLR<2:0> bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 ASRCSEL — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider 1 = Auxiliary Oscillators provides the source clock for Auxiliary Clock Divider 0 = PLL output (Fosc) provides the source clock for the Auxiliary Clock Divider bit 12-11 AOSCMD<1:0>: Auxiliary Oscillator Mode 11 = EC External Clock Mode Select 10 = XT Oscillator Mode Select 01 = HS Oscillator Mode Select 00 = Auxiliary Oscillator Disabled bit 10-8 APSTSCLR<2:0>: Auxiliary Clock Output Divider 111 = divided by 1 110 = divided by 2 101 = divided by 4 100 = divided by 8 011 = divided by 16 010 = divided by 32 001 = divided by 64 000 = divided by 256 (default) bit 7 ASRCSEL: Select Reference Clock Source for Auxiliary Clock 1 = Primary Oscillator is the Clock Source 0 = Auxiliary Oscillator is the Clock Source bit 6-0 Unimplemented: Read as ‘0’ Note 1: This register is reset only on a Power-on Reset (POR). DS70292G-page 150 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 9.4 Clock Switching Operation 2. If a valid clock switch has been initiated, the status bits, LOCK (OSCCON<5>) and the CF Applications are free to switch among any of the four (OSCCON<3>) are cleared. clock sources (Primary, LP, FRC and LPRC) under 3. The new oscillator is turned on by the hardware software control at any time. To limit the possible side if it is not currently running. If a crystal oscillator effects of this flexibility, dsPIC33FJ32GP302/304, must be turned on, the hardware waits until the dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ Oscillator Start-up Timer (OST) expires. If the X04 devices have a safeguard lock built into the switch new source is using the PLL, the hardware waits process. until a PLL lock is detected (LOCK = 1). Note: Primary Oscillator mode has three different 4. The hardware waits for 10 clock cycles from the submodes (XT, HS and EC), which are new clock source and then performs the clock determined by the POSCMD<1:0> Config- switch. uration bits. While an application can 5. The hardware clears the OSWEN bit to indicate a switch to and from Primary Oscillator successful clock transition. In addition, the NOSC mode in software, it cannot switch among bit values are transferred to the COSC status bits. the different primary submodes without 6. The old clock source is turned off at this time, reprogramming the device. with the exception of LPRC (if WDT or FSCM are enabled) or LP (if LPOSCEN remains set). 9.4.1 ENABLING CLOCK SWITCHING Note1: The processor continues to execute code To enable clock switching, the FCKSM1 Configuration bit in the Configuration register must be programmed to throughout the clock switching sequence. ‘0’. (Refer to Section27.1 “Configuration Bits” for Timing-sensitive code should not be further details.) If the FCKSM1 Configuration bit is executed during this time. unprogrammed (‘1’), the clock switching function and 2: Direct clock switches between any primary Fail-Safe Clock Monitor function are disabled. This is oscillator mode with PLL and FRCPLL the default setting. mode are not permitted. This applies to The NOSC control bits (OSCCON<10:8>) do not clock switches in either direction. In these control the clock selection when clock switching is instances, the application must switch to disabled. However, the COSC bits (OSCCON<14:12>) FRC mode as a transition clock source reflect the clock source selected by the FNOSC between the two PLL modes. Configuration bits. 3: Refer to Section 39. “Oscillator (PartIII)” (DS70216) in the The OSWEN control bit (OSCCON<0>) has no effect “dsPIC33F/PIC24H Family Reference when clock switching is disabled. It is held at ‘0’ at all Manual” for details. times. 9.4.2 OSCILLATOR SWITCHING SEQUENCE 9.5 Fail-Safe Clock Monitor (FSCM) Performing a clock switch requires this basic The Fail-Safe Clock Monitor (FSCM) allows the device sequence: to continue to operate even in the event of an oscillator 1. If desired, read the COSC bits failure. The FSCM function is enabled by programming. (OSCCON<14:12>) to determine the current If the FSCM function is enabled, the LPRC internal oscillator source. oscillator runs at all times (except during Sleep mode) 2. Perform the unlock sequence to allow a write to and is not subject to control by the Watchdog Timer. the OSCCON register high byte. In the event of an oscillator failure, the FSCM 3. Write the appropriate value to the NOSC control generates a clock failure trap event and switches the bits (OSCCON<10:8>) for the new oscillator system clock over to the FRC oscillator. Then the source. application program can either attempt to restart the 4. Perform the unlock sequence to allow a write to oscillator or execute a controlled shutdown. The trap the OSCCON register low byte. can be treated as a warm Reset by simply loading the Reset address into the oscillator fail trap vector. 5. Set the OSWEN bit (OSCCON<0>) to initiate the oscillator switch. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor Once the basic sequence is completed, the system on clock failure. Essentially, the device switches to clock hardware responds automatically as follows: FRC with PLL on a clock failure. 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits. If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. © 2007-2012 Microchip Technology Inc. DS70292G-page 151

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 152 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 10.0 POWER-SAVING FEATURES 10.2 Instruction-Based Power-Saving Modes Note1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, dsPIC33FJ64GPX02/X04, and and dsPIC33FJ128GPX02/X04 devices have two dsPIC33FJ128GPX02/X04 families of special power-saving modes that are entered through devices. It is not intended to be a compre- the execution of a special PWRSAV instruction. Sleep hensive reference source. To comple- mode stops clock operation and halts all code ment the information in this data sheet, execution. Idle mode halts the CPU and code refer to Section 9. “Watchdog Timer execution, but allows peripheral modules to continue and Power-Saving Modes” (DS70196) operation. The assembler syntax of the PWRSAV of the “dsPIC33F/PIC24H Family Refer- instruction is shown in Example10-1. ence Manual”, which is available from the Microchip website (www.microchip.com). Note: SLEEP_MODE and IDLE_MODE are con- stants defined in the assembler include 2: Some registers and associated bits file for the selected device. described in this section may not be avail- able on all devices. Refer to Section4.0 Sleep and Idle modes can be exited as a result of an “Memory Organization” in this data enabled interrupt, WDT time-out or a device Reset. When sheet for device-specific register and bit the device exits these modes, it is said to wake up. information. 10.2.1 SLEEP MODE The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ The following occur in Sleep mode: X04, and dsPIC33FJ128GPX02/X04 devices provide the ability to manage power consumption by selectively • The system clock source is shut down. If an managing clocking to the CPU and the peripherals. In on-chip oscillator is used, it is turned off. general, a lower clock frequency and a reduction in the • The device current consumption is reduced to a number of circuits being clocked constitutes lower minimum, provided that no I/O pin is sourcing consumed power. dsPIC33FJ32GP302/304, current. dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ • The Fail-Safe Clock Monitor does not operate, X04 devices can manage power consumption in four since the system clock source is disabled. ways: • The LPRC clock continues to run in Sleep mode if • Clock frequency the WDT is enabled. • Instruction-based Sleep and Idle modes • The WDT, if enabled, is automatically cleared • Software-controlled Doze mode prior to entering Sleep mode. • Selective peripheral control in software • Some device features or peripherals can continue to operate. This includes items such as the input Combinations of these methods can be used to selec- change notification on the I/O ports, or peripherals tively tailor an application’s power consumption while that use an external clock input. still maintaining critical application features, such as • Any peripheral that requires the system clock timing-sensitive communications. source for its operation is disabled. 10.1 Clock Frequency and Clock The device wakes up from Sleep mode on any of these Switching events: • Any interrupt source that is individually enabled dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, • Any form of device Reset and dsPIC33FJ128GPX02/X04 devices allow a wide range of clock frequencies to be selected under • A WDT time-out application control. If the system clock configuration is On wake-up from Sleep mode, the processor restarts not locked, users can choose low-power or high- with the same clock source that was active when Sleep precision oscillators by simply changing the NOSC bits mode was entered. (OSCCON<10:8>). The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section9.0 “Oscillator Configuration”. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2007-2012 Microchip Technology Inc. DS70292G-page 153

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 10.2.2 IDLE MODE Programs can use Doze mode to selectively reduce power consumption in event-driven applications. This The following occur in Idle mode: allows clock-sensitive functions, such as synchronous • The CPU stops executing instructions. communications, to continue without interruption while • The WDT is automatically cleared. the CPU idles, waiting for something to invoke an • The system clock source remains active. By interrupt routine. An automatic return to full-speed CPU default, all peripheral modules continue to operate operation on interrupts can be enabled by setting the normally from the system clock source, but can ROI bit (CLKDIV<15>). By default, interrupt events also be selectively disabled (see Section10.4 have no effect on Doze mode operation. “Peripheral Module Disable”). For example, suppose the device is operating at • If the WDT or FSCM is enabled, the LPRC also 20MIPS and the ECAN module has been configured remains active. for 500 kbps based on this device operating speed. If the device is placed in Doze mode with a clock The device wakes from Idle mode on any of these frequency ratio of 1:4, the ECAN module continues to events: communicate at the required bit rate of 500 kbps, but • Any interrupt that is individually enabled the CPU now starts executing instructions at a • Any form of device Reset frequency of 5 MIPS. • A WDT time-out 10.4 Peripheral Module Disable On wake-up from Idle mode, the clock is reapplied to the CPU and instruction execution will begin (2-4 clock The Peripheral Module Disable (PMD) registers cycles later), starting with the instruction following the provide a method to disable a peripheral module by PWRSAV instruction, or the first instruction in the ISR. stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate 10.2.3 INTERRUPTS COINCIDENT WITH PMD control bit, the peripheral is in a minimum power POWER SAVE INSTRUCTIONS consumption state. The control and status registers Any interrupt that coincides with the execution of a associated with the peripheral are also disabled, so PWRSAV instruction is held off until entry into Sleep or writes to those registers do not have effect and read Idle mode has completed. The device then wakes up values are invalid. from Sleep or Idle mode. A peripheral module is enabled only if both the associated bit in the PMD register is cleared and the 10.3 Doze Mode peripheral is supported by the specific dsPIC® DSC variant. If the peripheral is present in the device, it is The preferred strategies for reducing power enabled in the PMD register by default. consumption are changing clock speed and invoking one of the power-saving modes. In some Note: If a PMD bit is set, the corresponding mod- circumstances, this cannot be practical. For example, it ule is disabled after a delay of one instruc- may be necessary for an application to maintain tion cycle. Similarly, if a PMD bit is cleared, uninterrupted synchronous communication, even while the corresponding module is enabled after it is doing nothing else. Reducing system clock speed a delay of one instruction cycle (assuming can introduce communication errors, while using a the module control registers are already power-saving mode can stop communications configured to enable module operation). completely. Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed, while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core clock speed is determined by the DOZE<2:0> bits (CLKDIV<14:12>). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default setting. DS70292G-page 154 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 10.5 Power-Saving Resources Many useful resources related to Power-Saving are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 10.5.1 KEY RESOURCES • Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools © 2007-2012 Microchip Technology Inc. DS70292G-page 155

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 10.6 Power-Saving Control Registers REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 T5MD T4MD T3MD T2MD T1MD — — DCIMD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD AD1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 T5MD: Timer5 Module Disable bit 1 = Timer5 module is disabled 0 = Timer5 module is enabled bit 14 T4MD: Timer4 Module Disable bit 1 = Timer4 module is disabled 0 = Timer4 module is enabled bit 13 T3MD: Timer3 Module Disable bit 1 = Timer3 module is disabled 0 = Timer3 module is enabled bit 12 T2MD: Timer2 Module Disable bit 1 = Timer2 module is disabled 0 = Timer2 module is enabled bit 11 T1MD: Timer1 Module Disable bit 1 = Timer1 module is disabled 0 = Timer1 module is enabled bit 10-9 Unimplemented: Read as ‘0’ bit 8 DCIMD: DCI Module Disable bit 1 = DCI module is disabled 0 = DCI module is enabled bit 7 I2C1MD: I2C1 Module Disable bit 1 = I2C1 module is disabled 0 = I2C1 module is enabled bit 6 U2MD: UART2 Module Disable bit 1 = UART2 module is disabled 0 = UART2 module is enabled bit 5 U1MD: UART1 Module Disable bit 1 = UART1 module is disabled 0 = UART1 module is enabled bit 4 SPI2MD: SPI2 Module Disable bit 1 = SPI2 module is disabled 0 = SPI2 module is enabled bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2 Unimplemented: Read as ‘0’ bit 1 C1MD: ECAN1 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled DS70292G-page 156 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 IC8MD IC7MD — — — — IC2MD IC1MD bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — OC4MD OC3MD OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IC8MD: Input Capture 8 Module Disable bit 1 = Input Capture 8 module is disabled 0 = Input Capture 8 module is enabled bit 14 IC7MD: Input Capture 2 Module Disable bit 1 = Input Capture 7 module is disabled 0 = Input Capture 7 module is enabled bit 13-10 Unimplemented: Read as ‘0’ bit 9 IC2MD: Input Capture 2 Module Disable bit 1 = Input Capture 2 module is disabled 0 = Input Capture 2 module is enabled bit 8 IC1MD: Input Capture 1 Module Disable bit 1 = Input Capture 1 module is disabled 0 = Input Capture 1 module is enabled bit 7-4 Unimplemented: Read as ‘0’ bit 3 OC4MD: Output Compare 4 Module Disable bit 1 = Output Compare 4 module is disabled 0 = Output Compare 4 module is enabled bit 2 OC3MD: Output Compare 3 Module Disable bit 1 = Output Compare 3 module is disabled 0 = Output Compare 3 module is enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled © 2007-2012 Microchip Technology Inc. DS70292G-page 157

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CMPMD RTCCMD PMPMD bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 CRCMD DAC1MD — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Comparator Module Disable bit 1 = Comparator module is disabled 0 = Comparator module is enabled bit 9 RTCCMD: RTCC Module Disable bit 1 = RTCC module is disabled 0 = RTCC module is enabled bit 8 PMPMD: PMP Module Disable bit 1 = PMP module is disabled 0 = PMP module is enabled bit 7 CRCMD: CRC Module Disable bit 1 = CRC module is disabled 0 = CRC module is enabled bit 6 DAC1MD: DAC1 Module Disable bit 1 = DAC1 module is disabled 0 = DAC1 module is enabled bit 5-0 Unimplemented: Read as ‘0’ DS70292G-page 158 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 11.0 I/O PORTS has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through,” in Note1: This data sheet summarizes the features which a port’s digital output can drive the input of a of the dsPIC33FJ32GP302/304, peripheral that shares the same pin. Figure11-1 shows dsPIC33FJ64GPX02/X04, and how ports are shared with other peripherals and the dsPIC33FJ128GPX02/X04 families of associated I/O pin to which they are connected. devices. It is not intended to be a compre- When a peripheral is enabled and the peripheral is hensive reference source. To comple- actively driving an associated pin, the use of the pin as ment the information in this data sheet, a general purpose output pin is disabled. The I/O pin refer to Section “30. I/O Ports with can be read, but the output driver for the parallel port bit Peripheral Pin Select” (DS70190) of the is disabled. If a peripheral is enabled, but the peripheral “dsPIC33F/PIC24H Family Reference is not actively driving a pin, that pin can be driven by a Manual”, which is available from the port. Microchip website (www.microchip.com). All port pins have three registers directly associated 2: Some registers and associated bits with their operation as digital I/O. The data direction described in this section may not be avail- register (TRISx) determines whether the pin is an input able on all devices. Refer to Section4.0 or an output. If the data direction bit is a ‘1’, then the pin “Memory Organization” in this data is an input. All port pins are defined as inputs after a sheet for device-specific register and bit Reset. Reads from the latch (LATx) read the latch. information. Writes to the latch write the latch. Reads from the port (PORTx) read the port pins, while writes to the port pins All of the device pins (except VDD, VSS, MCLR and write the latch. OSC1/CLKI) are shared among the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Any bit and its associated data and control registers Trigger inputs for improved noise immunity. that are not valid for a particular device is disabled. This means the corresponding LATx and TRISx 11.1 Parallel I/O (PIO) Ports registers and the port pin are read as zeros. When a pin is shared with another peripheral or Generally a parallel I/O port that shares a pin with a function that is defined as an input only, it is peripheral is subservient to the peripheral. The nevertheless regarded as a dedicated port because peripheral’s output buffer data and control signals are there is no other competing source of outputs. provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data Read TRIS 0 Data Bus D Q I/O Pin WR TRIS CK TRIS Latch D Q WR LAT + WR Port CK Data Latch Read LAT Input Data Read Port © 2007-2012 Microchip Technology Inc. DS70292G-page 159

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 11.2 Open-Drain Configuration 11.4 I/O Port Write/Read Timing In addition to the PORT, LAT and TRIS registers for One instruction cycle is required between a port data control, some port pins can also be individually direction change or port write operation and a read configured for either digital or open-drain output. This operation of the same port. Typically this instruction is controlled by the Open-Drain Control register, would be an NOP, as shown in Example11-1. ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an 11.5 Input Change Notification open-drain output. The input change notification function of the I/O ports The open-drain feature allows the generation of allows the dsPIC33FJ32GP302/304, outputs higher than VDD (e.g., 5V) on any desired 5V dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ tolerant pins by using external pull-up resistors. The X04 devices to generate interrupt requests to the maximum open-drain voltage allowed is the same as processor in response to a change-of-state on selected the maximum VIH specification. input pins. This feature can detect input change-of- Refer to “Pin Diagrams” for the available pins and states even in Sleep mode, when the clocks are their functionality. disabled. Depending on the device pin count, up to 21 external signals (CNx pin) can be selected (enabled) 11.3 Configuring Analog Port Pins for generating an interrupt request on a change-of- state. The AD1PCFGL and TRIS registers control the opera- Four control registers are associated with the CN mod- tion of the Analog-to-Digital (ADC) port pins. The port ule. The CNEN1 and CNEN2 registers contain the pins that are to function as analog inputs must have interrupt enable control bits for each of the CN input their corresponding TRIS bit set (input). If the TRIS bit pins. Setting any of these bits enables a CN interrupt is cleared (output), the digital output level (VOH or VOL) for the corresponding pins. is converted. Each CN pin also has a weak pull-up connected to it. The AD1PCFGL register has a default value of 0x0000; The pull-ups act as a current source connected to the therefore, all pins that share ANx functions are analog pin, and eliminate the need for external resistors when (not digital) by default. push-button or keypad devices are connected. The When the PORT register is read, all pins configured as pull-ups are enabled separately using the CNPU1 and analog input channels are read as cleared (a low level). CNPU2 registers, which contain the control bits for Pins configured as digital inputs do not convert an each of the CN pins. Setting any of the control bits analog input. Analog levels on any pin defined as a enables the weak pull-ups for the corresponding pins. digital input (including the ANx pins) can cause the Note: Pull-ups on change notification pins input buffer to consume current that exceeds the should always be disabled when the port device specifications. pin is configured as a digital output. EXAMPLE 11-1: PORT WRITE/READ EXAMPLE MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs MOV W0, TRISBB ; and PORTB<7:0> as outputs NOP ; Delay 1 cycle btss PORTB, #13 ; Next Instruction DS70292G-page 160 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 11.6 Peripheral Pin Select 11.6.2.1 Input Mapping Peripheral pin select configuration enables peripheral The inputs of the peripheral pin select options are set selection and placement on a wide range of I/O mapped on the basis of the peripheral. A control pins. By increasing the pinout options available on a register associated with a peripheral dictates the pin it particular device, programmers can better tailor the is mapped to. The RPINRx registers are used to microcontroller to their entire application, rather than configure peripheral input mapping (see Register11-1 trimming the application to fit the device. through Register11-16). Each register contains sets of 5-bit fields, with each set associated with one of the The peripheral pin select configuration feature remappable peripherals. Programming a given operates over a fixed subset of digital I/O pins. peripheral’s bit field with an appropriate 5-bit value Programmers can independently map the input and/or maps the RPn pin with that value to that peripheral. output of most digital peripherals to any one of these For any given device, the valid range of values for any I/O pins. Peripheral pin select is performed in bit field corresponds to the maximum number of software, and generally does not require the device to peripheral pin selections supported by the device. be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the Figure11-2 illustrates remappable pin selection for peripheral mapping, once it has been established. U1RX input. Note: For input mapping only, the Peripheral Pin 11.6.1 AVAILABLE PINS Select (PPS) functionality does not have The peripheral pin select feature is used with a range priority over the TRISx settings. Therefore, of up to 26 pins. The number of available pins depends when configuring the RPx pin for input, the on the particular device and its pin count. Pins that corresponding bit in the TRISx register support the peripheral pin select feature include the must also be configured for input (i.e., set designation “RPn” in their full pin designation, where to ‘1’). “RP” designates a remappable peripheral and “n” is the remappable pin number. FIGURE 11-2: REMAPPABLE MUX INPUT FOR U1RX 11.6.2 CONTROLLING PERIPHERAL PIN SELECT U1RXR<4:0> Peripheral pin select features are controlled through two sets of special function registers: one to map 0 peripheral inputs, and one to map outputs. Because RP0 they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be 1 placed on any selectable function pin without RP1 U1RX input constraint. to peripheral 2 The association of a peripheral to a peripheral select- RP2 able pin is handled in two different ways, depending on whether an input or output is being mapped. 25 RP 25 © 2007-2012 Microchip Technology Inc. DS70292G-page 161

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 11-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Configuration Input Name Function Name Register Bits External Interrupt 1 INT1 RPINR0 INT1R<4:0> External Interrupt 2 INT2 RPINR1 INT2R<4:0> Timer2 External Clock T2CK RPINR3 T2CKR<4:0> Timer3 External Clock T3CK RPINR3 T3CKR<4:0> Timer4 External Clock T4CK RPINR4 T4CKR<4:0> Timer5 External Clock T5CK RPINR4 T5CKR<4:0> Input Capture 1 IC1 RPINR7 IC1R<4:0> Input Capture 2 IC2 RPINR7 IC2R<4:0> Input Capture 7 IC7 RPINR10 IC7R<4:0> Input Capture 8 IC8 RPINR10 IC8R<4:0> Output Compare Fault A OCFA RPINR11 OCFAR<4:0> UART1 Receive U1RX RPINR18 U1RXR<4:0> UART1 Clear To Send U1CTS RPINR18 U1CTSR<4:0> UART2 Receive U2RX RPINR19 U2RXR<4:0> UART2 Clear To Send U2CTS RPINR19 U2CTSR<4:0> SPI1 Data Input SDI1 RPINR20 SDI1R<4:0> SPI1 Clock Input SCK1 RPINR20 SCK1R<4:0> SPI1 Slave Select Input SS1 RPINR21 SS1R<4:0> SPI2 Data Input SDI2 RPINR22 SDI2R<4:0> SPI2 Clock Input SCK2 RPINR22 SCK2R<4:0> SPI2 Slave Select Input SS2 RPINR23 SS2R<4:0> DCI Serial Data Input CSDI RPINR24 CSDIR<4:0> DCI Serial Clock Input CSCK RPINR24 CSCKR<4:0> DCI Frame Sync Input COFS RPINR25 COFSR<4:0> ECAN1 Receive CIRX RPINR26 CIRXR<4:0> Note 1: Unless otherwise noted, all inputs use Schmitt input buffers. DS70292G-page 162 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 11.6.2.2 Output Mapping FIGURE 11-3: MULTIPLEXING OF REMAPPABLE OUTPUT In contrast to inputs, the outputs of the peripheral pin FOR RPn select options are mapped on the basis of the pin. In this case, a control register associated with a particular RPnR<4:0> pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. default 0 Like the RPINRx registers, each register contains sets U1TX Output enable 3 of 5-bit fields, with each set associated with one RPn pin (see Register11-17 through Register11-29). The U1RTS Output enable 4 value of the bit field corresponds to one of the Output Enable peripherals, and that peripheral’s output is mapped to the pin (see Table11-2 and Figure11-3). The list of peripherals for output mapping also includes OC4 Output a null value of ‘00000’ because of the mapping 21 technique. This permits any given pin to remain unconnected from the output of any of the pin default selectable peripherals. 0 U1TX Output 3 U1RTS Output 4 RPn Output Data OC4 Output 21 TABLE 11-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn) Function RPnR<4:0> Output Name NULL 00000 RPn tied to default port pin C1OUT 00001 RPn tied to Comparator1 Output C2OUT 00010 RPn tied to Comparator2 Output U1TX 00011 RPn tied to UART1 Transmit U1RTS 00100 RPn tied to UART1 Ready To Send U2TX 00101 RPn tied to UART2 Transmit U2RTS 00110 RPn tied to UART2 Ready To Send SDO1 00111 RPn tied to SPI1 Data Output SCK1 01000 RPn tied to SPI1 Clock Output SS1 01001 RPn tied to SPI1 Slave Select Output SDO2 01010 RPn tied to SPI2 Data Output SCK2 01011 RPn tied to SPI2 Clock Output SS2 01100 RPn tied to SPI2 Slave Select Output CSDO 01101 RPn tied to DCI Serial Data Output CSCK 01110 RPn tied to DCI Serial Clock Output COFS 01111 RPn tied to DCI Frame Sync Output C1TX 10000 RPn tied to ECAN1 Transmit OC1 10010 RPn tied to Output Compare 1 OC2 10011 RPn tied to Output Compare 2 OC3 10100 RPn tied to Output Compare 3 OC4 10101 RPn tied to Output Compare 4 © 2007-2012 Microchip Technology Inc. DS70292G-page 163

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 11.6.3 CONTROLLING CONFIGURATION 11.6.3.2 Continuous State Monitoring CHANGES In addition to being protected from direct writes, the Because peripheral remapping can be changed during contents of the RPINRx and RPORx registers are run time, some restrictions on peripheral remapping constantly monitored in hardware by shadow registers. are needed to prevent accidental configuration If an unexpected change in any of the registers occurs changes. dsPIC33F devices include three features to (such as cell disturbances caused by ESD or other prevent alterations to the peripheral map: external events), a configuration mismatch Reset is triggered. • Control register lock sequence • Continuous state monitoring 11.6.3.3 Configuration Bit Pin Select Lock • Configuration bit pin select lock As an additional level of safety, the device can be configured to prevent more than one write session to 11.6.3.1 Control Register Lock the RPINRx and RPORx registers. The IOL1WAY con- Under normal operation, writes to the RPINRx and figuration bit (FOSC<5>) blocks the IOLOCK bit from RPORx registers are not allowed. Attempted writes being cleared after it has been set once. If IOLOCK appear to execute normally, but the contents of the reg- remains set, the register unlock procedure does not isters remain unchanged. To change these registers, execute, and the peripheral pin select control registers they must be unlocked in hardware. The register lock is cannot be written to. The only way to clear the bit and controlled by the IOLOCK bit (OSCCON<6>). Setting re-enable peripheral remapping is to perform a device IOLOCK prevents writes to the control registers; Reset. clearing IOLOCK allows writes. In the default (unprogrammed) state, IOL1WAY is set, To set or clear IOLOCK, a specific command sequence restricting users to one write session. Programming must be executed: IOL1WAY allows user applications unlimited access 1. Write 0x46 to OSCCON<7:0>. (with the proper use of the unlock sequence) to the peripheral pin select registers. 2. Write 0x57 to OSCCON<7:0>. 3. Clear (or set) IOLOCK as a single operation. Note: MPLAB® C30 provides built-in C language functions for unlocking the OSCCON register: __builtin_write_OSCCONL(value) __builtin_write_OSCCONH(value) See MPLAB Help for more information. Unlike the similar sequence with the oscillator’s LOCK bit, IOLOCK remains in one state until changed. This allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. DS70292G-page 164 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 11.7 I/O Helpful Tips 4. Each CN pin has a configurable internal weak pull-up resistor. The pull-ups act as a current 1. In some cases, certain pins as defined in TABLE source connected to the pin, and eliminates the 30-9: “DC Characteristics: I/O Pin Input Speci- need for external resistors in certain applica- fications” under “Injection Current”, have internal tions. The internal pull-up is to ~(VDD-0.8) not protection diodes to VDD and VSS. The term VDD. This is still above the minimum VIH of “Injection Current” is also referred to as “Clamp CMOS and TTL devices. Current”. On designated pins, with sufficient exter- 5. When driving LEDs directly, the I/O pin can source nal current limiting precautions by the user, I/O pin or sink more current than what is specified in the input voltages are allowed to be greater or less VOH/IOH and VOL/IOL DC characteristic specifica- than the data sheet absolute maximum ratings tion. The respective IOH and IOL current rating only with nominal VDD with respect to the VSS and VDD applies to maintaining the corresponding output at supplies. Note that when the user application for- or above the VOH and at or below the VOL levels. ward biases either of the high or low side internal However, for LEDs unlike digital inputs of an exter- input clamp diodes, that the resulting current being nally connected device, they are not governed by injected into the device that is clamped internally the same minimum VIH/VIL levels. An I/O pin out- by the VDD and VSS power rails, may affect the put can safely sink or source any current less than ADC accuracy by four to six counts. that listed in the absolute maximum rating section 2. I/O pins that are shared with any analog input pin, of the data sheet. For example: (i.e., ANx), are always analog pins by default after any reset. Consequently, any pin(s) configured as VOH = 2.4v @ IOH = -8 mA and VDD = 3.3V an analog input pin, automatically disables the dig- The maximum output current sourced by any 8mA ital input pin buffer. As such, any attempt to read a I/O pin = 12 mA. digital input pin will always return a ‘0’ regardless LED source current < 12 mA is technically of the digital logic level on the pin if the analog pin permitted. Refer to the VOH/IOH graphs in is configured. To use a pin as a digital I/O pin on a Section30.0 “Electrical Characteristics” for shared ANx pin, the user application needs to con- additional information. figure the analog pin configuration registers in the ADC module, (i.e., ADxPCFGL, AD1PCFGH), by 11.8 I/O Resources setting the appropriate bit that corresponds to that I/O port pin to a ‘1’. On devices with more than one Many useful resources related to I/O are provided on ADC, both analog pin configurations for both ADC the main product page of the Microchip web site for the modules must be configured as a digital I/O pin for devices listed in this data sheet. This product page, that pin to function as a digital I/O pin. which can be accessed using this link, contains the latest updates and additional information. Note: Although it is not possible to use a digital input pin when its analog function is Note: In the event you are not able to access the enabled, it is possible to use the digital I/O product page using the link above, enter output function, TRISx = 0x0, while the this URL in your browser: analog function is also enabled. However, http://www.microchip.com/wwwproducts/ this is not recommended, particularly if the Devices.aspx?dDocName=en532311 analog input is connected to an external analog voltage source, which would cre- 11.8.1 KEY RESOURCES ate signal contention between the analog • Section 10. “I/O Ports” (DS70193) signal and the output pin driver. • Code Samples 3. Most I/O pins have multiple functions. Referring to • Application Notes the device pin diagrams in the data sheet, the pri- • Software Libraries orities of the functions allocated to any pins are • Webinars indicated by reading the pin name from left-to- right. The left most function name takes prece- • All related dsPIC33F/PIC24H Family Reference dence over any function to its right in the naming Manuals Sections convention. For example: AN16/T2CK/T7CK/RC1. • Development Tools This indicates that AN16 is the highest priority in this example and will supersede all other functions to its right in the list. Those other functions to its right, even if enabled, would not work as long as any other function to its left was enabled. This rule applies to all of the functions listed for a given pin. © 2007-2012 Microchip Technology Inc. DS70292G-page 165

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 11.9 Peripheral Pin Select Registers The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 family of devices implement 33 registers for remappable peripheral configuration: • 16 Input Remappable Peripheral Registers: - RPINR0-RPINR1, RPINR3-RPINR4, RPINR7, RPINR10-RPINR11 and PRINR18-RPINR26 • 13 Output Remappable Peripheral Registers: - RPOR0-RPOR12 Note: Input and Output Register values can only be changed if the IOLOCK bit (OSCCON<6>) is set to ‘0’. See Section11.6.3.1 “Control Register Lock” for a specific command sequence. REGISTER 11-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — INT1R<4:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ DS70292G-page 166 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — INT2R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007-2012 Microchip Technology Inc. DS70292G-page 167

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T3CKR<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T2CKR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70292G-page 168 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-4: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T5CKR<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T4CKR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T5CKR<4:0>: Assign Timer5 External Clock (T5CK) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T4CKR<4:0>: Assign Timer4 External Clock (T4CK) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007-2012 Microchip Technology Inc. DS70292G-page 169

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC2R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC2R<4:0>: Assign Input Capture 2 (IC2) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25. • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70292G-page 170 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-6: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC8R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC7R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC8R<4:0>: Assign Input Capture 8 (IC8) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC7R<4:0>: Assign Input Capture 7 (IC7) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007-2012 Microchip Technology Inc. DS70292G-page 171

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-7: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — OCFAR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign Output Compare A (OCFA) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70292G-page 172 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-8: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — U1CTSR<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — U1RXR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 U1CTSR<4:0>: Assign UART1 Clear to Send (U1CTS) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007-2012 Microchip Technology Inc. DS70292G-page 173

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-9: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — U2CTSR<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — U2RXR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 U2CTSR<4:0>: Assign UART2 Clear to Send (U2CTS) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 U2RXR<4:0>: Assign UART2 Receive (U2RX) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70292G-page 174 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-10: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SCK1R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SDI1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 SCK1R<4:0>: Assign SPI1 Clock Input (SCK1) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007-2012 Microchip Technology Inc. DS70292G-page 175

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-11: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SS1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS1R<4:0>: Assign SPI1 Slave Select Input (SS1) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70292G-page 176 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-12: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SCK2R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SDI2R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 SCK2R<4:0>: Assign SPI2 Clock Input (SCK2) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007-2012 Microchip Technology Inc. DS70292G-page 177

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-13: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SS2R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS2R<4:0>: Assign SPI2 Slave Select Input (SS2) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70292G-page 178 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-14: RPINR24: PERIPHERAL PIN SELECT INPUT REGISTER 24 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — CSCKR<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — CSDIR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 CSCKR<4:0>: Assign DCI Serial Clock Input (CSCK) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 4-0 CSDIR<4:0>: Assign DCI Serial Data Input (CSDI) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007-2012 Microchip Technology Inc. DS70292G-page 179

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-15: RPINR25: PERIPHERAL PIN SELECT INPUT REGISTER 25 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — COFSR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 COFSR<4:0>: Assign DCI Frame Sync Input (COFS) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 REGISTER 11-16: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — C1RXR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 C1RXR<4:0>: Assign ECAN1Receive (C1RX) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 Note 1: This register is disabled on devices without an ECAN™ module. DS70292G-page 180 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-17: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP1R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP0R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table11-2 for peripheral function numbers) REGISTER 11-18: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP3R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP2R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table11-2 for peripheral function numbers) © 2007-2012 Microchip Technology Inc. DS70292G-page 181

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-19: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP5R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP4R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table11-2 for peripheral function numbers) REGISTER 11-20: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP7R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP6R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table11-2 for peripheral function numbers) DS70292G-page 182 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-21: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP9R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP8R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table11-2 for peripheral function numbers) REGISTER 11-22: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP11R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP10R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table11-2 for peripheral function numbers) © 2007-2012 Microchip Technology Inc. DS70292G-page 183

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-23: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP13R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP12R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits (see Table11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table11-2 for peripheral function numbers) REGISTER 11-24: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP15R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP14R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table11-2 for peripheral function numbers) DS70292G-page 184 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-25: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP17R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP16R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits (see Table11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP16R<4:0>: Peripheral Output Function is Assigned to RP16 Output Pin bits (see Table11-2 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. REGISTER 11-26: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP19R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP18R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits (see Table11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits (see Table11-2 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. © 2007-2012 Microchip Technology Inc. DS70292G-page 185

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-27: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP21R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP20R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP21R<4:0>: Peripheral Output Function is Assigned to RP21 Output Pin bits (see Table11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table11-2 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. REGISTER 11-28: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP23R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP22R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table11-2 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. DS70292G-page 186 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-29: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP25R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP24R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP25R<4:0>: Peripheral Output Function is Assigned to RP25 Output Pin bits (see Table11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table11-2 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. © 2007-2012 Microchip Technology Inc. DS70292G-page 187

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 188 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 12.0 TIMER1 The unique features of Timer1 allow it to be used for Real-Time Clock (RTC) applications. A block diagram Note1: This data sheet summarizes the features of Timer1 is shown in Figure12-1. of the dsPIC33FJ32GP302/304, The Timer1 module can operate in one of the following dsPIC33FJ64GPX02/X04, and modes: dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a compre- • Timer mode hensive reference source. To comple- • Gated Timer mode ment the information in this data sheet, • Synchronous Counter mode refer to Section 11. “Timers” (DS70205) • Asynchronous Counter mode of the “dsPIC33F/PIC24H Family Refer- In Timer and Gated Timer modes, the input clock is ence Manual”, which is available from the Microchip website (www.microchip.com). derived from the internal instruction cycle clock (FCY). In Synchronous and Asynchronous Counter modes, 2: Some registers and associated bits the input clock is derived from the external clock input described in this section may not be avail- at the T1CK pin. able on all devices. Refer to Section4.0 The Timer modes are determined by the following bits: “Memory Organization” in this data sheet for device-specific register and bit • Timer Clock Source Control bit (TCS): T1CON<1> information. • Timer Synchronization Control bit (TSYNC): T1CON<2> The Timer1 module is a 16-bit timer, which can serve • Timer Gate Control bit (TGATE): T1CON<6> as the time counter for the real-time clock, or operate as a free-running interval timer/counter. Timer control bit setting for different operating modes are given in the Table12-1. The Timer1 module has the following unique features over other timers: TABLE 12-1: TIMER MODE SETTINGS • Can be operated from the low power 32 kHz crystal oscillator available on the device Mode TCS TGATE TSYNC • Can be operated in Asynchronous Counter mode Timer 0 0 x from an external clock source. Gated timer 0 1 x • The external clock input (T1CK) can optionally be Synchronous 1 x 1 synchronized to the internal device clock and the counter clock synchronization is performed after the prescaler. Asynchronous 1 x 0 counter FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM Gate Falling Edge Sync Detect 1 Set T1IF flag 0 FCY Prescaler 10 (/n) Reset TGATE TMR1 00 TCKPS<1:0> 0 SOSCO/ T1CK x1 Equal Prescaler Sync 1 Comparator (/n) TGATE TSYNC TCKPS<1:0> TCS SOSCI PR1 LPOSCEN(1) Note 1: Refer to Section9.0 “Oscillator Configuration” for information on enabling the secondary oscillator. © 2007-2012 Microchip Technology Inc. DS70292G-page 189

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 12.1 Timer Resources Many useful resources related to Timers are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 12.1.1 KEY RESOURCES • Section 11. “Timers” (DS70205) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70292G-page 190 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 12.2 Timer1 Control Register REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS<1:0> — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = External clock from pin T1CK (on the rising edge) 0 = Internal clock (FCY) bit 0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. DS70292G-page 191

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 192 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 13.0 TIMER2/3 AND TIMER4/5 • A Type B timer can be concatenated with a Type FEATURE C timer to form a 32-bit timer • The external clock input (TxCK) is always Note1: This data sheet summarizes the features synchronized to the internal device clock and the of the dsPIC33FJ32GP302/304, clock synchronization is performed after the dsPIC33FJ64GPX02/X04, and prescaler. dsPIC33FJ128GPX02/X04 families of A block diagram of the Type B timer is shown in devices. It is not intended to be a compre- Figure13-1. hensive reference source. To comple- ment the information in this data sheet, Timer3 and Timer5 are Type C timers with the following refer to Section 11. “Timers” (DS70205) specific features: of the “dsPIC33F/PIC24H Family Refer- • A Type C timer can be concatenated with a Type ence Manual”, which is available from the B timer to form a 32-bit timer Microchip website (www.microchip.com). • At least one Type C timer has the ability to trigger 2: Some registers and associated bits an analog-to-digital conversion. described in this section may not be avail- • The external clock input (TxCK) is always syn- able on all devices. Refer to Section4.0 chronized to the internal device clock and the “Memory Organization” in this data clock synchronization is performed before the sheet for device-specific register and bit prescaler information. A block diagram of the Type C timer is shown in Figure13-2. Timer2 and Timer4 are Type B timers with the following specific features: FIGURE 13-1: TYPE B TIMER BLOCK DIAGRAM (x = 2 or 4) Gate Falling Edge Sync Detect 1 Set TxIF flag FCY Prescaler 10 0 (/n) Reset 00 TMRx TCKPS<1:0> TGATE Prescaler Sync x1 (/n) Equal TxCK Comparator TCKPS<1:0> TGATE TCS PRx FIGURE 13-2: TYPE C TIMER BLOCK DIAGRAM (x = 3 or 5) Gate Falling Edge Sync Detect 1 Set TxIF flag FCY Prescaler 10 0 (/n) Reset TMRx 00 TGATE TCKPS<1:0> Prescaler Sync x1 (/n) Equal ADC SOC Trigger Comparator TxCK TCKPS<1:0> TGATE TCS PRx © 2007-2012 Microchip Technology Inc. DS70292G-page 193

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 The Timer2/3 and Timer4/5 modules can operate in For interrupt control, the combined 32-bit timer uses one of the following modes: the interrupt enable, interrupt flag and interrupt priority control bits of the Type C timer. The interrupt control • Timer mode and status bits for the TypeB timer are ignored during • Gated Timer mode 32-bit timer operation. • Synchronous Counter mode The Type B and Type C timers that can be combined to In Timer and Gated Timer modes, the input clock is form a 32-bit timer are listed in Table13-2. derived from the internal instruction cycle clock (FCY). In Synchronous Counter mode, the input clock is TABLE 13-2: 32-BIT TIMER derived from the external clock input at TxCK pin. TYPE B Timer (lsw) TYPE C Timer (msw) The timer modes are determined by the following bits: • TCS (TxCON<1>): Timer Clock Source Control bit Timer2 Timer3 • TGATE (TxCON<6>): Timer Gate Control bit Timer4 Timer5 Timer control bit settings for different operating modes A block diagram representation of the 32-bit timer mod- are given in the Table13-1. ule is shown in Figure13-3. The 32-bit timer module can operate in one of the following modes: TABLE 13-1: TIMER MODE SETTINGS • Timer mode Mode TCS TGATE • Gated Timer mode • Synchronous Counter mode Timer 0 0 To configure the features of Timer2/3 or Timer4/5 for Gated timer 0 1 32-bit operation: Synchronous 1 x counter 1. Set the T32 control bit. 2. Select the prescaler ratio for Timer2 or Timer4 13.1 16-bit Operation using the TCKPS<1:0> bits. 3. Set the Clock and Gating modes using the To configure any of the timers for individual 16-bit corresponding TCS and TGATE bits. operation: 4. Load the timer period value. PR3 or PR5 con- 1. Clear the T32 bit corresponding to that timer. tains the most significant word of the value, 2. Select the timer prescaler ratio using the while PR2 or PR4 contains the least significant TCKPS<1:0> bits. word. 3. Set the Clock and Gating modes using the TCS 5. If interrupts are required, set the interrupt enable and TGATE bits. bits, T3IE or T5IE. Use the priority bits, 4. Load the timer period value into the PRx T3IP<2:0> or T5IP<2:0> to set the interrupt pri- register. ority. While Timer2 or Timer4 controls the timer, the interrupt appears as a Timer3 or Timer5 5. If interrupts are required, set the interrupt enable interrupt. bit, TxIE. Use the priority bits, TxIP<2:0>, to set the interrupt priority. 6. Set the corresponding TON bit. 6. Set the TON bit. The timer value at any point is stored in the register pair, TMR3:TMR2 or TMR5:TMR4, which always Note: Only Timer2 and Timer3 can trigger a contains the most significant word of the count, while DMA data transfer. TMR2 or TMR4 contains the least significant word. 13.2 32-bit Operation A 32-bit timer module can be formed by combining a Type B and a Type C 16-bit timer module. For 32-bit timer operation, the T32 control bit in the Type B Timer Control register (TxCON<3>) must be set. The Type C timer holds the most significant word (msw) and the Type B timer holds the least significant word (lsw) for 32-bit operation. When configured for 32-bit operation, only the Type B Timer Control register (TxCON) bits are required for setup and control. Type C timer control register bits are ignored (except TSIDL bit). DS70292G-page 194 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 13-3: 32-BIT TIMER BLOCK DIAGRAM Gate Falling Edge Sync Detect 1 Set TyIF Flag PRx PRy 0 Equal Comparator TGATE Prescaler 10 FCY (/n) lsw msw ADC SOC trigger Reset 00 TMRx TMRy TCKPS<1:0> Prescaler Sync x1 (/n) TxCK TMRyHLD TCKPS<1:0> TGATE TCS Data Bus <15:0> Note 1: ADC trigger is available only on TMR3:TMR2 and TMR5:TMR2 32-bit timers. 2: Timer x is a Type B Timer (x = 2 and 4). 3: Timer y is a Type C Timer (y = 3 and 5). 13.3 Timer Resources Many useful resources related to Timers are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 13.3.1 KEY RESOURCES • Section 11. “Timers” (DS70205) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools © 2007-2012 Microchip Technology Inc. DS70292G-page 195

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 13.4 Timerx/y Control Registers REGISTER 13-1: TxCON: TIMER CONTROL REGISTER (x = 2 or 4, y = 3 or 5) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS<1:0> T32 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timerx On bit When T32 = 1 (in 32-bit Timer mode): 1 = Starts 32-bit TMRx:TMRy timer pair 0 = Stops 32-bit TMRx:TMRy timer pair When T32 = 0 (in 16-bit Timer mode): 1 = Starts 16-bit timer 0 = Stops 16-bit timer bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue timer operation when device enters Idle mode 0 = Continue timer operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 T32: 32-bit Timerx Mode Select bit 1 = TMRx and TMRy form a 32-bit timer 0 = TMRx and TMRy form separate 16-bit timer bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit 1 = External clock from TxCK pin 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ DS70292G-page 196 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 13-2: TxCON: TIMER CONTROL REGISTER (x = 3 OR 5) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(2) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(2) TCKPS<1:0>(2) — — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timery On bit(2) 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit(1) 1 = Discontinue timer operation when device enters Idle mode 0 = Continue timer operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit(2) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits(2) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit(2) 1 = External clock from TxCK pin 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32=1) in the Timer Control register (TxCON<3>), these bits have no effect. © 2007-2012 Microchip Technology Inc. DS70292G-page 197

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 198 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 14.0 INPUT CAPTURE 1. Simple Capture Event modes: - Capture timer value on every falling edge of Note1: This data sheet summarizes the features input at ICx pin of the dsPIC33FJ32GP302/304, - Capture timer value on every rising edge of dsPIC33FJ64GPX02/X04, and input at ICx pin dsPIC33FJ128GPX02/X04 families of 2. Capture timer value on every edge (rising and devices. It is not intended to be a compre- falling) hensive reference source. To comple- 3. Prescaler Capture Event modes: ment the information in this data sheet, refer to Section 12. “Input Capture” - Capture timer value on every 4th rising (DS70198) of the “dsPIC33F/PIC24H edge of input at ICx pin Family Reference Manual”, which is avail- - Capture timer value on every 16th rising able from the Microchip website edge of input at ICx pin (www.microchip.com). Each input capture channel can select one of two 16- 2: Some registers and associated bits bit timers (Timer2 or Timer3) for the time base. The described in this section may not be avail- selected timer can use either an internal or external able on all devices. Refer to Section4.0 clock. “Memory Organization” in this data Other operational features include: sheet for device-specific register and bit • Device wake-up from capture pin during CPU information. Sleep and Idle modes The input capture module is useful in applications • Interrupt on input capture event requiring frequency (period) and pulse measurement. • 4-word FIFO buffer for capture values The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ - Interrupt optionally generated after 1, 2, 3 or X04, and dsPIC33FJ128GPX02/X04 devices support 4 buffer locations are filled up to four input capture channels. • Use of input capture to provide additional sources The input capture module captures the 16-bit value of of external interrupts the selected Time Base register when an event occurs at the ICx pin. The events that cause a capture event Note: Only IC1 and IC2 can trigger a DMA data are listed below in three categories: transfer. If DMA data transfers are required, the FIFO buffer size must be set to ‘1’ (ICI<1:0> = 00) FIGURE 14-1: INPUT CAPTURE BLOCK DIAGRAM ICM<2:0> Prescaler Mode (16th Rising Edge) 101 TMR2 TMR3 Prescaler Mode (4th Rising Edge) 100 ICTMR Rising Edge Mode ICx pin 011 CaptureEvent To CPU FIFO CONTROL Falling Edge Mode ICxBUF 010 FIFO Edge Detection ICI<1:0> Mode 001 ICM<2:0> /N Set Flag ICxIF (In IFSx Register) Sleep/Idle Wake-up Mode 001 111 Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel. © 2007-2012 Microchip Technology Inc. DS70292G-page 199

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 14.1 Input Capture Resources Many useful resources related to Input Capture are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 14.1.1 KEY RESOURCES • Section 12. “Input Capture” (DS70198) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70292G-page 200 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 14.2 Input Capture Registers REGISTER 14-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER(x = 1, 2, 7 OR 8) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — ICSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 ICTMR: Input Capture Timer Select bits 1 = TMR2 contents are captured on capture event 0 = TMR3 contents are captured on capture event bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM<2:0>: Input Capture Mode Select bits 111 =Input capture functions as interrupt pin only when device is in Sleep or Idle mode (Rising edge detect only, all other control bits are not applicable.) 110 =Unused (module disabled) 101 =Capture mode, every 16th rising edge 100 =Capture mode, every 4th rising edge 011 =Capture mode, every rising edge 010 =Capture mode, every falling edge 001 =Capture mode, every edge (rising and falling) (ICI<1:0> bits do not control interrupt generation for this mode.) 000 =Input capture module turned off © 2007-2012 Microchip Technology Inc. DS70292G-page 201

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 202 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 15.0 OUTPUT COMPARE The Output Compare module can select either Timer2 or Timer3 for its time base. The module compares the Note1: This data sheet summarizes the features value of the timer with the value of one or two compare of the dsPIC33FJ32GP302/304, registers depending on the operating mode selected. dsPIC33FJ64GPX02/X04, and The state of the output pin changes when the timer dsPIC33FJ128GPX02/X04 families of value matches the compare register value. The Output devices. It is not intended to be a Compare module generates either a single output comprehensive reference source. To pulse or a sequence of output pulses, by changing the complement the information in this data state of the output pin on the compare match events. sheet, refer to Section 13. “Output The Output Compare module can also generate Compare” (DS70209) of the “dsPIC33F/ interrupts on compare match events. PIC24H Family Reference Manual”, The Output Compare module has multiple operating which is available from the Microchip modes: website (www.microchip.com). • Active-Low One-Shot mode 2: Some registers and associated bits described in this section may not be avail- • Active-High One-Shot mode able on all devices. Refer to Section4.0 • Toggle mode “Memory Organization” in this data • Delayed One-Shot mode sheet for device-specific register and bit • Continuous Pulse mode information. • PWM mode without Fault protection • PWM mode with Fault protection FIGURE 15-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF OCxRS Output S Q OCxR OCx Logic R 3 Output OCM<2:0> Output Enable Mode Select Enable Logic Comparator OCFA 0 1 OCTSEL 0 1 16 16 TMR2 TMR3 TMR2 TMR3 Rollover Rollover © 2007-2012 Microchip Technology Inc. DS70292G-page 203

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 15.1 Output Compare Modes Note1: Only OC1 and OC2 can trigger a DMA Configure the Output Compare modes by setting the data transfer. appropriate Output Compare Mode bits (OCM<2:0>) in 2: See Section 13. “Output Compare” the Output Compare Control register (OCxCON<2:0>). (DS70209) in the “dsPIC33F/PIC24H Table15-1 lists the different bit settings for the Output Family Reference Manual” for OCxR and Compare modes. Figure15-2 illustrates the output OCxRS register restrictions. compare operation for various modes. The user appli- cation must disable the associated timer when writing to the output compare control registers to avoid malfunctions. TABLE 15-1: OUTPUT COMPARE MODES OCM<2:0> Mode OCx Pin Initial State OCx Interrupt Generation 000 Module Disabled Controlled by GPIO register — 001 Active-Low One-Shot 0 OCx Rising edge 010 Active-High One-Shot 1 OCx Falling edge 011 Toggle Mode Current output is maintained OCx Rising and Falling edge 100 Delayed One-Shot 0 OCx Falling edge 101 Continuous Pulse mode 0 OCx Falling edge 110 PWM mode without fault 0, if OCxR is zero No interrupt protection 1, if OCxR is non-zero 111 PWM mode with fault protection 0, if OCxR is zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero FIGURE 15-2: OUTPUT COMPARE OPERATION Output Compare Timer is reset on Mode enabled period match OCxRS TMRy OCxR Active-Low One-Shot (OCM = 001) Active-High One-Shot (OCM = 010) Toggle Mode (OCM = 011) Delayed One-Shot (OCM = 100) Continuous Pulse Mode (OCM = 101) PWM Mode (OCM = 110 or 111) DS70292G-page 204 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 15.2 Output Compare Resources Many useful resources related to Output Compare are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 15.2.1 KEY RESOURCES • Section 13. “Output Compare” (DS70209) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools © 2007-2012 Microchip Technology Inc. DS70292G-page 205

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 15.3 Output Compare Control Register REGISTER 15-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2, 3 OR 4) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0 HC R/W-0 R/W-0 R/W-0 R/W-0 — — — OCFLT OCTSEL OCM<2:0> bit 7 bit 0 Legend: HC = Cleared in Hardware HS = Set in Hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Stop Output Compare in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode bit 12-5 Unimplemented: Read as ‘0’ bit 4 OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in hardware only) 0 = No PWM Fault condition has occurred (This bit is only used when OCM<2:0> = 111.) bit 3 OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for Compare x 0 = Timer2 is the clock source for Compare x bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx, Fault pin enabled 110 = PWM mode on OCx, Fault pin disabled 101 = Initialize OCx pin low, generate continuous output pulses on OCx pin 100 = Initialize OCx pin low, generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled DS70292G-page 206 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 16.0 SERIAL PERIPHERAL The Serial Peripheral Interface (SPI) module is a syn- INTERFACE (SPI) chronous serial interface useful for communicating with other peripheral or microcontroller devices. These Note1: This data sheet summarizes the features peripheral devices can be serial EEPROMs, shift regis- of the dsPIC33FJ32GP302/304, ters, display drivers, analog-to-digital converters, etc. dsPIC33FJ64GPX02/X04, and The SPI module is compatible with Motorola® SPI and dsPIC33FJ128GPX02/X04 families of SIOP. devices. It is not intended to be a compre- Each SPI module consists of a 16-bit shift register, hensive reference source. To comple- SPIxSR (where x = 1 or 2), used for shifting data in and ment the information in this data sheet, out, and a buffer register, SPIxBUF. A control register, refer to Section 18. “Serial Peripheral SPIxCON, configures the module. Additionally, a status Interface (SPI)” (DS70206) of the register, SPIxSTAT, indicates status conditions. “dsPIC33F/PIC24H Family Reference The serial interface consists of 4 pins: Manual”, which is available from the Microchip website (www.microchip.com). • SDIx (serial data input) • SDOx (serial data output) 2: Some registers and associated bits • SCKx (shift clock input or output) described in this section may not be avail- • SSx (active-low slave select). able on all devices. Refer to Section4.0 “Memory Organization” in this data In Master mode operation, SCK is a clock output. In sheet for device-specific register and bit Slave mode, it is a clock input. information. FIGURE 16-1: SPI MODULE BLOCK DIAGRAM SCKx 1:1 to 1:8 1:1/4/16/64 Secondary Primary FCY Prescaler Prescaler SSx Sync Control Select Control Clock Edge SPIxCON1<1:0> Shift Control SPIxCON1<4:2> SDOx Enable SDIx bit 0 Master Clock SPIxSR Transfer Transfer SPIxRXB SPIxTXB SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus © 2007-2012 Microchip Technology Inc. DS70292G-page 207

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 16.1 SPI Helpful Tips 16.2 SPI Resources 1. In Frame mode, if there is a possibility that the Many useful resources related to SPI are provided on master may not be initialized before the slave: the main product page of the Microchip web site for the a) If FRMPOL (SPIxCON2<13>) = 1, use a devices listed in this data sheet. This product page, pull-down resistor on SSx. which can be accessed using this link, contains the latest updates and additional information. b) If FRMPOL = 0, use a pull-up resistor on SSx. Note: In the event you are not able to access the Note: This insures that the first frame product page using the link above, enter transmission after initialization is not this URL in your browser: shifted or corrupted. http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 2. In non-framed 3-wire mode, (i.e., not using SSx from a master): 16.2.1 KEY RESOURCES a) If CKP (SPIxCON1<6>) = 1, always place a • Section 18. “Serial Peripheral Interface (SPI)” pull-up resistor on SSx. (DS70206) b) If CKP = 0, always place a pull-down • Code Samples resistor on SSx. • Application Notes Note: This will insure that during power-up and • Software Libraries initialization the master/slave will not lose • Webinars sync due to an errant SCK transition that • All related dsPIC33F/PIC24H Family Reference would cause the slave to accumulate data Manuals Sections shift errors for both transmit and receive appearing as corrupted data. • Development Tools 3. FRMEN (SPIxCON2<15>) = 1 and SSEN (SPIxCON1<7>) = 1 are exclusive and invalid. In Frame mode, SCKx is continuous and the Frame sync pulse is active on the SSx pin, which indicates the start of a data frame. Note: Not all third-party devices support Frame mode timing. Refer to the SPI electrical characteristics for details. 4. In Master mode only, set the SMP bit (SPIxCON1<9>) to a ‘1’ for the fastest SPI data rate possible. The SMP bit can only be set at the same time or after the MSTEN bit (SPIxCON1<5>) is set. 5. To avoid invalid slave read data to the master, the user’s master software must guarantee enough time for slave software to fill its write buf- fer before the user application initiates a master write/read cycle. It is always advisable to pre- load the SPIxBUF transmit register in advance of the next master transaction cycle. SPIxBUF is transferred to the SPI shift register and is empty once the data transmission begins. DS70292G-page 208 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 16.3 SPI Control Registers REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 SPIEN — SPISIDL — — — — — bit 15 bit 8 U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0 — SPIROV — — — — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded. The user software has not read the previous data in the SPIxBUF register 0 = No overflow has occurred bit 5-2 Unimplemented: Read as ‘0’ bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. © 2007-2012 Microchip Technology Inc. DS70292G-page 209

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(3) CKP MSTEN SPRE<2:0>(2) PPRE<1:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled, pin functions as I/O 0 = Internal SPI clock is enabled bit 11 DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. bit 8 CKE: SPIx Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) bit 7 SSEN: Slave Select Enable bit (Slave mode)(3) 1 = SSx pin used for Slave mode 0 = SSx pin not used by module. Pin controlled by port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: Do not set both Primary and Secondary prescalers to the value of 1:1. 3: This bit must be cleared when FRMEN = 1. DS70292G-page 210 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(2) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(2) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: Do not set both Primary and Secondary prescalers to the value of 1:1. 3: This bit must be cleared when FRMEN = 1. © 2007-2012 Microchip Technology Inc. DS70292G-page 211

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) 0 = Framed SPIx support disabled bit 14 SPIFSD: Frame Sync Pulse Direction Control bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) bit 13 FRMPOL: Frame Sync Pulse Polarity bit 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low bit 12-2 Unimplemented: Read as ‘0’ bit 1 FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: Read as ‘0’ This bit must not be set to ‘1’ by the user application. DS70292G-page 212 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 17.0 INTER-INTEGRATED 17.1 Operating Modes CIRCUIT™ (I2C™) The hardware fully implements all the master and slave functions of the I2C Standard and Fast mode Note1: This data sheet summarizes the features specifications, as well as 7 and 10-bit addressing. of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and The I2C module can operate either as a slave or a dsPIC33FJ128GPX02/X04 families of master on an I2C bus. devices. It is not intended to be a compre- The following types of I2C operation are supported: hensive reference source. To comple- • I2C slave operation with 7-bit addressing ment the information in this data sheet, • I2C slave operation with 10-bit addressing refer to Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195) of the • I2C master operation with 7-bit or 10-bit addressing “dsPIC33F/PIC24H Family Reference For details about the communication sequence in each Manual”, which is available from the of these modes, refer to the “dsPIC33F/PIC24H Family Microchip website (www.microchip.com). Reference Manual”. Please see the Microchip website 2: Some registers and associated bits (www.microchip.com) for the latest dsPIC33F/PIC24H described in this section may not be Family Reference Manual chapters. available on all devices. Refer to Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Inter-Integrated Circuit (I2C) module provides complete hardware support for both Slave and Multi- Master modes of the I2C serial communication standard, with a 16-bit interface. The I2C module has a 2-pin interface: • The SCLx pin is clock. • The SDAx pin is data. The I2C module offers the following key features: • I2C interface supporting both Master and Slave modes of operation. • I2C Slave mode supports 7-bit and 10-bit addressing • I2C Master mode supports 7 and 10-bit addressing • I2C Port allows bidirectional transfers between master and slaves. • Serial clock synchronization for I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control). • I2C supports multi-master operation, detects bus collision and arbitrates accordingly. © 2007-2012 Microchip Technology Inc. DS70292G-page 213

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 17-1: I2C™ BLOCK DIAGRAM (X = 1) Internal Data Bus I2CxRCV Read Shift SCLx Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation I2CxSTAT c gi Read o CDoelltiseicotn ntrol L Write o C I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read ShiftClock Reload Control Write BRG Down Counter I2CxBRG Read TCY/2 DS70292G-page 214 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 17.2 I2C Resources Many useful resources related to I2C are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 17.2.1 KEY RESOURCES • Section 11. “Inter-Integrated Circuit™ (I2C™)” (DS70195) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools 17.3 I2C Registers I2CxCON and I2CxSTAT are control and status registers, respectively. The I2CxCON register is readable and writable. The lower six bits of I2CxSTAT are read-only. The remaining bits of the I2CSTAT are read/write: • I2CxRSR is the shift register used for shifting data internal to the module and the user application has no access to it. • I2CxRCV is the receive buffer and the register to which data bytes are written, or from which data bytes are read. • I2CxTRN is the transmit register to which bytes are written during a transmit operation. • The I2CxADD register holds the slave address. • A status bit, ADD10, indicates 10-bit Address mode. • The I2CxBRG acts as the Baud Rate Generator (BRG) reload value. In receive operations, I2CxRSR and I2CxRCV together form a double-buffered receiver. When I2CxRSR receives a complete byte, it is transferred to I2CxRCV, and an interrupt pulse is generated. © 2007-2012 Microchip Technology Inc. DS70292G-page 215

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Set in hardware HC = Cleared in hardware -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module. All I2C™ pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters an Idle mode 0 = Continue module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave transmission. bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = IPMI mode is enabled; all addresses Acknowledged 0 = IPMI mode disabled bit 10 A10M: 10-bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching DS70292G-page 216 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence 0 = Acknowledge sequence not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte 0 = Receive sequence not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence 0 = Stop condition not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence 0 = Repeated Start condition not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence 0 = Start condition not in progress © 2007-2012 Microchip Technology Inc. DS70292G-page 217

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0 HSC R-0 HSC U-0 U-0 U-0 R/C-0 HS R-0 HSC R-0 HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0 HS R/C-0 HS R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC R-0 HSC R-0 HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ C = Clear only bit R = Readable bit W = Writable bit HS = Set in hardware HSC = Hardware set/cleared -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C™ master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware set or clear at end of slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. bit 8 ADD10: 10-bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. DS70292G-page 218 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read – indicates data transfer is output from slave 0 = Write – indicates data transfer is input to slave Hardware set or clear after reception of I2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. © 2007-2012 Microchip Technology Inc. DS70292G-page 219

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSKx: Mask for Address Bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position DS70292G-page 220 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 18.0 UNIVERSAL ASYNCHRONOUS The primary features of the UART module are: RECEIVER TRANSMITTER • Full-Duplex, 8-bit or 9-bit Data Transmission (UART) through the UxTX and UxRX pins • Even, Odd or No Parity Options (for 8-bit data) Note1: This data sheet summarizes the features • One or two stop bits of the dsPIC33FJ32GP302/304, • Hardware flow control option with UxCTS and dsPIC33FJ64GPX02/X04, and UxRTS pins dsPIC33FJ128GPX02/X04 families of • Fully integrated Baud Rate Generator with 16-bit devices. It is not intended to be a prescaler comprehensive reference source. To complement the information in this data • Baud rates ranging from 10 Mbps to 38 bps at 40 sheet, refer to Section 17. “UART” MIPS (DS70188) of the “dsPIC33F/PIC24H • 4-deep First-In First-Out (FIFO) Transmit Data Family Reference Manual”, which is buffer available from the Microchip website • 4-deep FIFO Receive Data buffer (www.microchip.com). • Parity, framing and buffer overrun error detection 2: Some registers and associated bits • Support for 9-bit mode with Address Detect described in this section may not be avail- (9th bit = 1) able on all devices. Refer to Section4.0 • Transmit and Receive interrupts “Memory Organization” in this data • A separate interrupt for all UART error conditions sheet for device-specific register and bit • Loopback mode for diagnostic support information. • Support for sync and break characters The Universal Asynchronous Receiver Transmitter • Support for automatic baud rate detection (UART) module is one of the serial I/O modules • IrDA® encoder and decoder logic available in the dsPIC33FJ32GP302/304, • 16x baud clock output for IrDA® support dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 device family. The UART is a full-duplex A simplified block diagram of the UART module is asynchronous system that can communicate with shown in Figure18-1. The UART module consists of peripheral devices, such as personal computers, these key hardware elements: LIN2.0, RS-232 and RS-485 interfaces. The module • Baud Rate Generator also supports a hardware flow control option with the • Asynchronous Transmitter UxCTS and UxRTS pins and also includes an IrDA® encoder and decoder. • Asynchronous Receiver FIGURE 18-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® Hardware Flow Control UxRTS/BLCKx UxCTS UART Receiver UxRX UART Transmitter UxTX Note1: Both UART1 and UART2 can trigger a DMA data transfer. 2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e., UTXISEL<1:0> = 00 and URXISEL<1:0> = 00). © 2007-2012 Microchip Technology Inc. DS70292G-page 221

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 18.1 UART Helpful Tips 18.2 UART Resources 1. In multi-node direct-connect UART networks, Many useful resources related to UART are provided UART receive inputs react to the on the main product page of the Microchip web site for complementary logic level defined by the the devices listed in this data sheet. This product page, URXINV bit (UxMODE<4>), which defines the which can be accessed using this link, contains the idle state, the default of which is logic high, (i.e., latest updates and additional information. URXINV = 0). Because remote devices do not Note: In the event you are not able to access the initialize at the same time, it is likely that one of product page using the link above, enter the devices, because the RX line is floating, will this URL in your browser: trigger a start bit detection and will cause the http://www.microchip.com/wwwproducts/ first byte received after the device has been ini- Devices.aspx?dDocName=en532311 tialized to be invalid. To avoid this situation, the user should use a pull-up or pull-down resistor 18.2.1 KEY RESOURCES on the RX pin depending on the value of the URXINV bit. • Section 17. “UART” (DS70188) a) If URXINV = 0, use a pull-up resistor on the • Code Samples RX pin. • Application Notes b) If URXINV = 1, use a pull-down resistor on • Software Libraries the RX pin. • Webinars 2. The first character received on a wake-up from • All related dsPIC33F/PIC24H Family Reference Sleep mode caused by activity on the UxRX pin Manuals Sections of the UART module will be invalid. In Sleep • Development Tools mode, peripheral clocks are disabled. By the time the oscillator system has restarted and stabilized from Sleep mode, the baud rate bit sampling clock relative to the incoming UxRX bit timing is no longer synchronized, resulting in the first character being invalid. This is to be expected. DS70292G-page 222 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 18.3 UART Control Registers REGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UARTEN(1) — USIDL IREN(2) RTSMD — UEN<1:0> bit 15 bit 8 R/W-0 HC R/W-0 R/W-0 HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL bit 7 bit 0 Legend: HC = Hardware cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2) 1 = IrDA® encoder and decoder enabled 0 = IrDA® encoder and decoder disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin in Simplex mode 0 = UxRTS pin in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by port latches bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit 1 = UARTx continues to sample the UxRX pin; interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = No wake-up enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h) before other data; cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH=0). © 2007-2012 Microchip Technology Inc. DS70292G-page 223

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH=0). DS70292G-page 224 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 HC R/W-0 R-0 R-1 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware cleared C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift register, and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: Transmit Polarity Inversion bit If IREN = 0: 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ If IREN = 1: 1 = IrDA® encoded UxTX Idle state is ‘1’ 0 = IrDA® encoded UxTX Idle state is ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission disabled or completed bit 10 UTXEN: Transmit Enable bit(1) 1 = Transmit enabled, UxTX pin controlled by UARTx 0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by port bit 9 UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 = Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive buffer. Receive buffer has one or more characters. Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. © 2007-2012 Microchip Technology Inc. DS70292G-page 225

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data=1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect 0 = Address Detect mode disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (read/clear only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1→ 0 transition) resets the receiver buffer and the UxRSR to the empty state. bit 0 URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. DS70292G-page 226 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 19.0 ENHANCED CAN (ECAN™) The module features are as follows: MODULE • Implementation of the CAN protocol, CAN1.2, CAN2.0A and CAN2.0B Note1: This data sheet summarizes the features • Standard and extended data frames of the dsPIC33FJ32GP302/304, • 0-8 bytes data length dsPIC33FJ64GPX02/X04, and • Programmable bit rate up to 1 Mbit/sec dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a compre- • Automatic response to remote transmission hensive reference source. To comple- requests ment the information in this data sheet, • Up to eight transmit buffers with application speci- refer to Section 21. “Enhanced Control- fied prioritization and abort capability (each buffer ler Area Network (ECAN™)” (DS70185) can contain up to 8 bytes of data) of the “dsPIC33F/PIC24H Family Refer- • Up to 32 receive buffers (each buffer can contain up ence Manual”, which is available from the to 8 bytes of data) Microchip website (www.microchip.com). • Up to 16 full (standard/extended identifier) 2: Some registers and associated bits acceptance filters described in this section may not be avail- • Three full acceptance filter masks able on all devices. Refer to Section4.0 • DeviceNet™ addressing support “Memory Organization” in this data • Programmable wake-up functionality with integrated sheet for device-specific register and bit low-pass filter information. • Programmable Loopback mode supports self-test operation 19.1 Overview • Signaling via interrupt capabilities for all CAN The Enhanced Controller Area Network (ECAN™) receiver and transmitter error states module is a serial interface, useful for communicating • Programmable clock source with other CAN modules or microcontroller devices. • Programmable link to input capture module (IC2 for This interface/protocol was designed to allow commu- CAN1) for time-stamping and network synchroniza- nications within noisy environments. The tion dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, • Low-power Sleep and Idle mode and dsPIC33FJ128GPX02/X04 devices contain up to two ECAN modules. The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine The ECAN module is a communication controller handles all functions for receiving and transmitting implementing the CAN 2.0 A/B protocol, as defined in messages on the CAN bus. Messages are transmitted the BOSCH CAN specification. The module supports by first loading the appropriate data registers. Status CAN1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B and errors can be checked by reading the appropriate Active versions of the protocol. The module implemen- registers. Any message detected on the CAN bus is tation is a full CAN system. The CAN specification is checked for errors and then matched against filters to not covered within this data sheet. The reader can refer see if it should be received and stored in one of the to the BOSCH CAN specification for further details. receive registers. © 2007-2012 Microchip Technology Inc. DS70292G-page 227

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 19.2 Frame Types The ECAN module transmits various types of frames which include data messages, or remote transmission requests initiated by the user, as other frames that are automatically generated for control purposes. The following frame types are supported: • Standard Data Frame: A standard data frame is generated by a node when the node wishes to transmit data. It includes an 11-bit Standard Identifier (SID), but not an 18- bit Extended Identifier (EID). • Extended Data Frame: An extended data frame is similar to a standard data frame, but includes an extended identifier as well. • Remote Frame: It is possible for a destination node to request the data from the source. For this purpose, the destination node sends a remote frame with an identifier that matches the identifier of the required data frame. The appropriate data source node sends a data frame as a response to this remote request. • Error Frame: An error frame is generated by any node that detects a bus error. An error frame consists of two fields: an error flag field and an error delimiter field. • Overload Frame: An overload frame can be generated by a node as a result of two conditions. First, the node detects a dominant bit during interframe space which is an illegal condition. Second, due to internal condi- tions, the node is not yet able to start reception of the next message. A node can generate a maxi- mum of 2 sequential overload frames to delay the start of the next message. • Interframe Space: Interframe space separates a proceeding frame (of whatever type) from a following data or remote frame. DS70292G-page 228 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 19-1: ECAN™ MODULE BLOCK DIAGRAM RXF15 Filter RXF14 Filter RXF13 Filter RXF12 Filter RXF11 Filter DMA Controller RXF10 Filter RXF9 Filter RXF8 Filter TRB7 TX/RX Buffer Control Register RXF7 Filter TRB6 TX/RX Buffer Control Register RXF6 Filter TRB5 TX/RX Buffer Control Register RXF5 Filter TRB4 TX/RX Buffer Control Register RXF4 Filter TRB3 TX/RX Buffer Control Register RXF3 Filter TRB2 TX/RX Buffer Control Register RXF2 Filter RXM2 Mask TRB1 TX/RX Buffer Control Register RXF1 Filter RXM1 Mask TRB0 TX/RX Buffer Control Register RXF0 Filter RXM0 Mask Transmit Byte Message Assembly Sequencer Buffer Control CPU Configuration Bus Logic CAN Protocol Engine Interrupts C1Tx C1Rx © 2007-2012 Microchip Technology Inc. DS70292G-page 229

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 19.3 Modes of Operation The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or The ECAN module can operate in one of several the CPU is in Sleep mode. The WAKFIL bit operation modes selected by the user. These modes (CiCFG2<14>) enables or disables the filter. include: • Initialization mode Note: Typically, if the ECAN module is allowed to transmit in a particular mode of operation • Disable mode and a transmission is requested immedi- • Normal Operation mode ately after the ECAN module has been • Listen Only mode placed in that mode of operation, the mod- • Listen All Messages mode ule waits for 11 consecutive recessive bits • Loopback mode on the bus before starting transmission. If Modes are requested by setting the REQOP<2:0> bits the user switches to Disable mode within (CiCTRL1<10:8>). Entry into a mode is Acknowledged this 11-bit period, then this transmission is by monitoring the OPMODE<2:0> bits aborted and the corresponding TXABT bit (CiCTRL1<7:5>). The module does not change the is set and TXREQ bit is cleared. mode and the OPMODE bits until a change in mode is 19.3.3 NORMAL OPERATION MODE acceptable, generally during bus Idle time, which is defined as at least 11 consecutive recessive bits. Normal Operation mode is selected when REQOP<2:0>=000. In this mode, the module is 19.3.1 INITIALIZATION MODE activated and the I/O pins assumes the CAN bus In the Initialization mode, the module does not transmit functions. The module transmits and receive CAN bus or receive. The error counters are cleared and the inter- messages via the CiTX and CiRX pins. rupt flags remain unchanged. The user application has 19.3.4 LISTEN ONLY MODE access to Configuration registers that are access restricted in other modes. The module protects the user If the Listen Only mode is activated, the module on the from accidentally violating the CAN protocol through CAN bus is passive. The transmitter buffers revert to programming errors. All registers which control the the port I/O function. The receive pins remain inputs. configuration of the module cannot be modified while For the receiver, no error flags or Acknowledge signals the module is on-line. The ECAN module is not allowed are sent. The error counters are deactivated in this to enter the Configuration mode while a transmission is state. The Listen Only mode can be used for detecting taking place. The Configuration mode serves as a lock the baud rate on the CAN bus. To use this, it is to protect the following registers: necessary that there are at least two further nodes that • All Module Control registers communicate with each other. • Baud Rate and Interrupt Configuration registers 19.3.5 LISTEN ALL MESSAGES MODE • Bus Timing registers • Identifier Acceptance Filter registers The module can be set to ignore all errors and receive any message. The Listen All Messages mode is acti- • Identifier Acceptance Mask registers vated by setting REQOP<2:0> = ‘111’. In this mode, 19.3.2 DISABLE MODE the data which is in the message assembly buffer, until the time an error occurred, is copied in the receive buf- In Disable mode, the module does not transmit or fer and can be read via the CPU interface. receive. The module has the ability to set the WAKIF bit due to bus activity, however, any pending interrupts 19.3.6 LOOPBACK MODE remains and the error counters retains their value. If the Loopback mode is activated, the module con- If the REQOP<2:0> bits (CiCTRL1<10:8>) = 001, the nects the internal transmit signal to the internal receive module enters the Module Disable mode. If the module is signal at the module boundary. The transmit and active, the module waits for 11 recessive bits on the CAN receive pins revert to their port I/O function. bus, detect that condition as an Idle bus, then accept the module disable command. When the OPMODE<2:0> bits (CiCTRL1<7:5>)=001, that indicates whether the module successfully went into Module Disable mode. The I/O pins reverts to normal I/O function when the module is in the Module Disable mode. DS70292G-page 230 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 19.4 ECAN Resources Many useful resources related to ECAN are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 19.4.1 KEY RESOURCES • Section 21. “Enhanced Controller Area Network (ECAN™)” (DS70185) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools © 2007-2012 Microchip Technology Inc. DS70292G-page 231

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 19.5 ECAN Control Registers REGISTER 19-1: CiCTRL1: ECAN™ CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 r-0 R/W-1 R/W-0 R/W-0 — — CSIDL ABAT — REQOP<2:0> bit 15 bit 8 R-1 R-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0 OPMODE<2:0> — CANCAP — — WIN bit 7 bit 0 Legend: r = Bit is reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 ABAT: Abort All Pending Transmissions bit 1 = Signal all transmit buffers to abort transmission. 0 = Module will clear this bit when all transmissions are aborted bit 11 Reserved: Do not use bit 10-8 REQOP<2:0>: Request Operation Mode bits 111 = Set Listen All Messages mode 110 = Reserved 101 = Reserved 100 = Set Configuration mode 011 = Set Listen Only Mode 010 = Set Loopback mode 001 = Set Disable mode 000 = Set Normal Operation mode bit 7-5 OPMODE<2:0>: Operation Mode bits 111 = Module is in Listen All Messages mode 110 = Reserved 101 = Reserved 100 = Module is in Configuration mode 011 = Module is in Listen Only mode 010 = Module is in Loopback mode 001 = Module is in Disable mode 000 = Module is in Normal Operation mode bit 4 Unimplemented: Read as ‘0’ bit 3 CANCAP: CAN Message Receive Timer Capture Event Enable bit 1 = Enable input capture based on CAN message receive 0 = Disable CAN capture bit 2-1 Unimplemented: Read as ‘0’ bit 0 WIN: SFR Map Window Select bit 1 = Use filter window 0 = Use buffer window DS70292G-page 232 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-2: CiCTRL2: ECAN™ CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — DNCNT<4:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare up to data byte 3, bit 6 with EID<17> • • • 00001 = Compare up to data byte 1, bit 7 with EID<0> 00000 = Do not compare data bytes © 2007-2012 Microchip Technology Inc. DS70292G-page 233

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-3: CiVEC: ECAN™ INTERRUPT CODE REGISTER U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — FILHIT<4:0> bit 15 bit 8 U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0 — ICODE<6:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit Number bits 10000-11111 = Reserved 01111 = Filter 15 • • • 00001 = Filter 1 00000 = Filter 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 ICODE<6:0>: Interrupt Flag Code bits 1000101-1111111 = Reserved 1000100 = FIFO almost full interrupt 1000011 = Receiver overflow interrupt 1000010 = Wake-up interrupt 1000001 = Error interrupt 1000000 = No interrupt • • • 0010000-0111111 = Reserved 0001111 = RB15 buffer Interrupt • • • 0001001 = RB9 buffer interrupt 0001000 = RB8 buffer interrupt 0000111 = TRB7 buffer interrupt 0000110 = TRB6 buffer interrupt 0000101 = TRB5 buffer interrupt 0000100 = TRB4 buffer interrupt 0000011 = TRB3 buffer interrupt 0000010 = TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 Buffer interrupt DS70292G-page 234 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-4: CiFCTRL: ECAN™ FIFO CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 DMABS<2:0> — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FSA<4:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in DMA RAM 101 = 24 buffers in DMA RAM 100 = 16 buffers in DMA RAM 011 = 12 buffers in DMA RAM 010 = 8 buffers in DMA RAM 001 = 6 buffers in DMA RAM 000 = 4 buffers in DMA RAM bit 12-5 Unimplemented: Read as ‘0’ bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = Read buffer RB31 11110 = Read buffer RB30 • • • 00001 = TX/RX buffer TRB1 00000 = TX/RX buffer TRB0 © 2007-2012 Microchip Technology Inc. DS70292G-page 235

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-5: CiFIFO: ECAN™ FIFO STATUS REGISTER U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — FBP<5:0> bit 15 bit 8 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — FNRB<5:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FBP<5:0>: FIFO Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer • • • 000001 = TRB1 buffer 000000 = TRB0 buffer bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 FNRB<5:0>: FIFO Next Read Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer • • • 000001 = TRB1 buffer 000000 = TRB0 buffer DS70292G-page 236 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-6: CiINTF: ECAN™ INTERRUPT FLAG REGISTER U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — TXBO TXBP RXBP TXWAR RXWAR EWARN bit 15 bit 8 R/C-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 TXBO: Transmitter in Error State Bus Off bit 1 = Transmitter is in Bus Off state 0 = Transmitter is not in Bus Off state bit 12 TXBP: Transmitter in Error State Bus Passive bit 1 = Transmitter is in Bus Passive state 0 = Transmitter is not in Bus Passive state bit 11 RXBP: Receiver in Error State Bus Passive bit 1 = Receiver is in Bus Passive state 0 = Receiver is not in Bus Passive state bit 10 TXWAR: Transmitter in Error State Warning bit 1 = Transmitter is in Error Warning state 0 = Transmitter is not in Error Warning state bit 9 RXWAR: Receiver in Error State Warning bit 1 = Receiver is in Error Warning state 0 = Receiver is not in Error Warning state bit 8 EWARN: Transmitter or Receiver in Error State Warning bit 1 = Transmitter or Receiver is in Error State Warning state 0 = Transmitter or Receiver is not in Error State Warning state bit 7 IVRIF: Invalid Message Received Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred bit 6 WAKIF: Bus Wake-up Activity Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred bit 5 ERRIF: Error Interrupt Flag bit (multiple sources in CiINTF<13:8> register) 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred bit 4 Unimplemented: Read as ‘0’ bit 3 FIFOIF: FIFO Almost Full Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred bit 1 RBIF: RX Buffer Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred bit 0 TBIF: TX Buffer Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred © 2007-2012 Microchip Technology Inc. DS70292G-page 237

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-7: CiINTE: ECAN™ INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IVRIE: Invalid Message Received Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled bit 6 WAKIE: Bus Wake-up Activity Interrupt Flag bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled bit 5 ERRIE: Error Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled bit 4 Unimplemented: Read as ‘0’ bit 3 FIFOIE: FIFO Almost Full Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled bit 2 RBOVIE: RX Buffer Overflow Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled bit 1 RBIE: RX Buffer Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled bit 0 TBIE: TX Buffer Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled DS70292G-page 238 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-8: CiEC: ECAN™ TRANSMIT/RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TERRCNT<7:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RERRCNT<7:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 TERRCNT<7:0>: Transmit Error Count bits bit 7-0 RERRCNT<7:0>: Receive Error Count bits REGISTER 19-9: CiCFG1: ECAN™ BAUD RATE CONFIGURATION REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW<1:0> BRP<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 SJW<1:0>: Synchronization Jump Width bits 11 = Length is 4 x TQ 10 = Length is 3 x TQ 01 = Length is 2 x TQ 00 = Length is 1 x TQ bit 5-0 BRP<5:0>: Baud Rate Prescaler bits 11 1111 = TQ = 2 x 64 x 1/FCAN • • • 00 0010 = TQ = 2 x 3 x 1/FCAN 00 0001 = TQ = 2 x 2 x 1/FCAN 00 0000 = TQ = 2 x 1 x 1/FCAN © 2007-2012 Microchip Technology Inc. DS70292G-page 239

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-10: CiCFG2: ECAN™ BAUD RATE CONFIGURATION REGISTER 2 U-0 R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x — WAKFIL — — — SEG2PH<2:0> bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 WAKFIL: Select CAN bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up bit 13-11 Unimplemented: Read as ‘0’ bit 10-8 SEG2PH<2:0>: Phase Segment 2 bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of SEG1PH bits or Information Processing Time (IPT), whichever is greater bit 6 SAM: Sample of the CAN bus Line bit 1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sample point bit 5-3 SEG1PH<2:0>: Phase Segment 1 bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ bit 2-0 PRSEG<2:0>: Propagation Time Segment bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ DS70292G-page 240 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-11: CiFEN1: ECAN™ ACCEPTANCE FILTER ENABLE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 FLTENn: Enable Filter n to Accept Messages bits 1 = Enable Filter n 0 = Disable Filter n REGISTER 19-12: CiBUFPNT1: ECAN™ FILTER 0-3 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F3BP<3:0> F2BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F1BP<3:0> F0BP<3:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F3BP<3:0>: RX Buffer mask for Filter 3 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F2BP<3:0>: RX Buffer mask for Filter 2 (same values as bit 15-12) bit 7-4 F1BP<3:0>: RX Buffer mask for Filter 1 (same values as bit 15-12) bit 3-0 F0BP<3:0>: RX Buffer mask for Filter 0 (same values as bit 15-12) © 2007-2012 Microchip Technology Inc. DS70292G-page 241

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-13: CiBUFPNT2: ECAN™ FILTER 4-7 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7BP<3:0> F6BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F5BP<3:0> F4BP<3:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F7BP<3:0>: RX Buffer mask for Filter 7 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F6BP<3:0>: RX Buffer mask for Filter 6 (same values as bit 15-12) bit 7-4 F5BP<3:0>: RX Buffer mask for Filter 5 (same values as bit 15-12) bit 3-0 F4BP<3:0>: RX Buffer mask for Filter 4 (same values as bit 15-12) REGISTER 19-14: CiBUFPNT3: ECAN™ FILTER 8-11 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F11BP<3:0> F10BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F9BP<3:0> F8BP<3:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F11BP<3:0>: RX Buffer mask for Filter 11 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F10BP<3:0>: RX Buffer mask for Filter 10 (same values as bit 15-12) bit 7-4 F9BP<3:0>: RX Buffer mask for Filter 9 (same values as bit 15-12) bit 3-0 F8BP<3:0>: RX Buffer mask for Filter 8 (same values as bit 15-12) DS70292G-page 242 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-15: CiBUFPNT4: ECAN™ FILTER 12-15 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15BP<3:0> F14BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F13BP<3:0> F12BP<3:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F15BP<3:0>: RX Buffer mask for Filter 15 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 bit 11-8 F14BP<3:0>: RX Buffer mask for Filter 14 (same values as bit 15-12) bit 7-4 F13BP<3:0>: RX Buffer mask for Filter 13 (same values as bit 15-12) bit 3-0 F12BP<3:0>: RX Buffer mask for Filter 12 (same values as bit 15-12) © 2007-2012 Microchip Technology Inc. DS70292G-page 243

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-16: CiRXFnSID: ECAN™ ACCEPTANCE FILTER STANDARD IDENTIFIER REGISTER n (n = 0-15) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 SID<10:0>: Standard Identifier bits 1 = Message address bit SIDx must be ‘1’ to match filter 0 = Message address bit SIDx must be ‘0’ to match filter bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDE: Extended Identifier Enable bit If MIDE = 1: 1 = Match only messages with extended identifier addresses 0 = Match only messages with standard identifier addresses If MIDE = 0: Ignore EXIDE bit. bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits 1 = Message address bit EIDx must be ‘1’ to match filter 0 = Message address bit EIDx must be ‘0’ to match filter DS70292G-page 244 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-17: CiRXFnEID: ECAN™ ACCEPTANCE FILTER EXTENDED IDENTIFIER REGISTER n (n = 0-15) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 EID<15:0>: Extended Identifier bits 1 = Message address bit EIDx must be ‘1’ to match filter 0 = Message address bit EIDx must be ‘0’ to match filter REGISTER 19-18: CiFMSKSEL1: ECAN™ FILTER 7-0 MASK SELECTION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 F7MSK<1:0>: Mask Source for Filter 7 bit 11 = No mask 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask bit 13-12 F6MSK<1:0>: Mask Source for Filter 6 bit (same values as bit 15-14) bit 11-10 F5MSK<1:0>: Mask Source for Filter 5 bit (same values as bit 15-14) bit 9-8 F4MSK<1:0>: Mask Source for Filter 4 bit (same values as bit 15-14) bit 7-6 F3MSK<1:0>: Mask Source for Filter 3 bit (same values as bit 15-14) bit 5-4 F2MSK<1:0>: Mask Source for Filter 2 bit (same values as bit 15-14) bit 3-2 F1MSK<1:0>: Mask Source for Filter 1 bit (same values as bit 15-14) bit 1-0 F0MSK<1:0>: Mask Source for Filter 0 bit (same values as bit 15-14) © 2007-2012 Microchip Technology Inc. DS70292G-page 245

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-19: CiFMSKSEL2: ECAN™ FILTER 15-8 MASK SELECTION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 F15MSK<1:0>: Mask Source for Filter 15 bit 11 = No mask 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask bit 13-12 F14MSK<1:0>: Mask Source for Filter 14 bit (same values as bit 15-14) bit 11-10 F13MSK<1:0>: Mask Source for Filter 13 bit (same values as bit 15-14) bit 9-8 F12MSK<1:0>: Mask Source for Filter 12 bit (same values as bit 15-14) bit 7-6 F11MSK<1:0>: Mask Source for Filter 11 bit (same values as bit 15-14) bit 5-4 F10MSK<1:0>: Mask Source for Filter 10 bit (same values as bit 15-14) bit 3-2 F9MSK<1:0>: Mask Source for Filter 9 bit (same values as bit 15-14) bit 1-0 F8MSK<1:0>: Mask Source for Filter 8 bit (same values as bit 15-14) DS70292G-page 246 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-20: CiRXMnSID: ECAN™ ACCEPTANCE FILTER MASK STANDARD IDENTIFIER REGISTER n (n = 0-2) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — MIDE — EID17 EID16 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 SID<10:0>: Standard Identifier bits 1 = Include bit SIDx in filter comparison 0 = Bit SIDx is don’t care in filter comparison bit 4 Unimplemented: Read as ‘0’ bit 3 MIDE: Identifier Receive Mode bit 1 =Match only message types (standard or extended address) that correspond to EXIDE bit in filter 0 =Match either standard or extended address message if filters match (i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID)) bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits 1 =Include bit EIDx in filter comparison 0 =Bit EIDx is don’t care in filter comparison REGISTER 19-21: CiRXMnEID: ECAN™ ACCEPTANCE FILTER MASK EXTENDED IDENTIFIER REGISTER n (n = 0-2) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 EID<15:0>: Extended Identifier bits 1 =Include bit EIDx in filter comparison 0 =Bit EIDx is don’t care in filter comparison © 2007-2012 Microchip Technology Inc. DS70292G-page 247

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-22: CiRXFUL1: ECAN™ RECEIVE BUFFER FULL REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXFUL<15:0>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty REGISTER 19-23: CiRXFUL2: ECAN™ RECEIVE BUFFER FULL REGISTER 2 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXFUL<31:16>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty DS70292G-page 248 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-24: CiRXOVF1: ECAN™ RECEIVE BUFFER OVERFLOW REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXOVF<15:0>: Receive Buffer n Overflow bits 1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition REGISTER 19-25: CiRXOVF2: ECAN™ RECEIVE BUFFER OVERFLOW REGISTER 2 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXOVF<31:16>: Receive Buffer n Overflow bits 1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition © 2007-2012 Microchip Technology Inc. DS70292G-page 249

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-26: CiTRmnCON: ECAN™ TX/RX BUFFER m CONTROL REGISTER (m = 0,2,4,6; n = 1,3,5,7) R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn TXnPRI<1:0> bit 15 bit 8 R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXENm TXABTm(1) TXLARBm(1) TXERRm(1) TXREQm RTRENm TXmPRI<1:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 See Definition for Bits 7-0, Controls Buffer n bit 7 TXENm: TX/RX Buffer Selection bit 1 = Buffer TRBn is a transmit buffer 0 = Buffer TRBn is a receive buffer bit 6 TXABTm: Message Aborted bit(1) 1 = Message was aborted 0 = Message completed transmission successfully bit 5 TXLARBm: Message Lost Arbitration bit(1) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERRm: Error Detected During Transmission bit(1) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQm: Message Send Request bit 1 = Requests that a message be sent. The bit automatically clears when the message is successfully sent 0 = Clearing the bit to ‘0’ while set requests a message abort bit 2 RTRENm: Auto-Remote Transmit Enable bit 1 = When a remote transmit is received, TXREQ will be set 0 = When a remote transmit is received, TXREQ will be unaffected bit 1-0 TXmPRI<1:0>: Message Transmission Priority bits 11 = Highest message priority 10 = High intermediate message priority 01 = Low intermediate message priority 00 = Lowest message priority Note 1: This bit is cleared when the TXREQ bit is set. Note: The buffers, SID, EID, DLC, Data Field and Receive Status registers are located in DMA RAM. DS70292G-page 250 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 19.6 ECAN Message Buffers ECAN Message Buffers are part of DMA RAM Memory. They are not ECAN special function registers. The user application must directly write into the DMA RAM area that is configured for ECAN Message Buffers. The location and size of the buffer area is defined by the user application. BUFFER 19-1: ECAN™ MESSAGE BUFFER WORD 0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — SID10 SID9 SID8 SID7 SID6 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID5 SID4 SID3 SID2 SID1 SID0 SRR IDE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-2 SID<10:0>: Standard Identifier bits bit 1 SRR: Substitute Remote Request bit 1 = Message will request remote transmission 0 = Normal message bit 0 IDE: Extended Identifier bit 1 = Message will transmit extended identifier 0 = Message will transmit standard identifier BUFFER 19-2: ECAN™ MESSAGE BUFFER WORD 1 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x — — — — EID17 EID16 EID15 EID14 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 EID<17:6>: Extended Identifier bits © 2007-2012 Microchip Technology Inc. DS70292G-page 251

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 (BUFFER 19-3: ECAN™ MESSAGE BUFFER WORD 2 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID5 EID4 EID3 EID2 EID1 EID0 RTR RB1 bit 15 bit 8 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 EID<5:0>: Extended Identifier bits bit 9 RTR: Remote Transmission Request bit 1 = Message will request remote transmission 0 = Normal message bit 8 RB1: Reserved Bit 1 User must set this bit to ‘0’ per CAN protocol. bit 7-5 Unimplemented: Read as ‘0’ bit 4 RB0: Reserved Bit 0 User must set this bit to ‘0’ per CAN protocol. bit 3-0 DLC<3:0>: Data Length Code bits BUFFER 19-4: ECAN™ MESSAGE BUFFER WORD 3 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 1 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 1<15:8>: ECAN™ Message Byte 0 bit 7-0 Byte 0<7:0>: ECAN Message Byte 1 DS70292G-page 252 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 BUFFER 19-5: ECAN™ MESSAGE BUFFER WORD 4 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 3 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 3<15:8>: ECAN™ Message Byte 3 bit 7-0 Byte 2<7:0>: ECAN Message Byte 2 BUFFER 19-6: ECAN™ MESSAGE BUFFER WORD 5 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 5 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 4 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 5<15:8>: ECAN™ Message Byte 5 bit 7-0 Byte 4<7:0>: ECAN Message Byte 4 © 2007-2012 Microchip Technology Inc. DS70292G-page 253

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 BUFFER 19-7: ECAN™ MESSAGE BUFFER WORD 6 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 7 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 6 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 7<15:8>: ECAN™ Message Byte 7 bit 7-0 Byte 6<7:0>: ECAN Message Byte 6 BUFFER 19-8: ECAN™ MESSAGE BUFFER WORD 7 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — FILHIT<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit Code bits(1) Encodes number of filter that resulted in writing this buffer. bit 7-0 Unimplemented: Read as ‘0’ Note1: These bits are only written by the module for receive buffers, and are unused for transmit buffers. DS70292G-page 254 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 20.0 DATA CONVERTER 20.1 Module Introduction INTERFACE (DCI) MODULE The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 Data Converter Note1: This data sheet summarizes the features Interface (DCI) module allows simple interfacing of of the dsPIC33FJ32GP302/304, devices, such as audio coder/decoders (Codecs), ADC dsPIC33FJ64GPX02/X04, and and D/A converters. The following interfaces are dsPIC33FJ128GPX02/X04 families of supported: devices. It is not intended to be a compre- • Framed Synchronous Serial Transfer (Single or hensive reference source. To comple- Multi-Channel) ment the information in this data sheet, refer to Section 20. “Data Converter • Inter-IC Sound (I2S) Interface Interface (DCI)” (DS70288) of the • AC-Link Compliant mode “dsPIC33F/PIC24H Family Reference • The DCI module provides the following general Manual”, which is available from the features: Microchip website (www.microchip.com). • Programmable word size up to 16 bits 2: Some registers and associated bits • Supports up to 16 time slots, for a maximum described in this section may not be avail- frame size of 256 bits able on all devices. Refer to Section4.0 • Data buffering for up to 4 samples without CPU “Memory Organization” in this data overhead sheet for device-specific register and bit information. FIGURE 20-1: DCI MODULE BLOCK DIAGRAM BCG Control bits SCKD Sample Rate FOSC/4 CSCK Generator FSD Word Size Selection bits Frame Frame Length Selection bits Synchronization COFS DCI Mode Selection bits Generator s u B a at D bit Receive Buffer 6- Registers w/Shadow 1 DCI Buffer Control Unit 15 0 Transmit Buffer DCI Shift Register CSDI Registers w/Shadow CSDO © 2007-2012 Microchip Technology Inc. DS70292G-page 255

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 20.2 DCI Resources Many useful resources related to DCI are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 20.2.1 KEY RESOURCES • Section 20. “Data Converter Interface (DCI)” (DS70288) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70292G-page 256 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 20.3 DCI Control Registers REGISTER 20-1: DCICON1: DCI CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 DCIEN — DCISIDL — DLOOP CSCKD CSCKE COFSD bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 UNFM CSDOM DJST — — — COFSM<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DCIEN: DCI Module Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 DCISIDL: DCI Stop in Idle Control bit 1 = Module will halt in CPU Idle mode 0 = Module will continue to operate in CPU Idle mode bit 12 Unimplemented: Read as ‘0’ bit 11 DLOOP: Digital Loopback Mode Control bit 1 = Digital Loopback mode is enabled. CSDI and CSDO pins internally connected. 0 = Digital Loopback mode is disabled bit 10 CSCKD: Sample Clock Direction Control bit 1 = CSCK pin is an input when DCI module is enabled 0 = CSCK pin is an output when DCI module is enabled bit 9 CSCKE: Sample Clock Edge Control bit 1 = Data changes on serial clock falling edge, sampled on serial clock rising edge 0 = Data changes on serial clock rising edge, sampled on serial clock falling edge bit 8 COFSD: Frame Synchronization Direction Control bit 1 = COFS pin is an input when DCI module is enabled 0 = COFS pin is an output when DCI module is enabled bit 7 UNFM: Underflow Mode bit 1 = Transmit last value written to the transmit registers on a transmit underflow 0 = Transmit ‘0’s on a transmit underflow bit 6 CSDOM: Serial Data Output Mode bit 1 = CSDO pin will be tri-stated during disabled transmit time slots 0 = CSDO pin drives ‘0’s during disabled transmit time slots bit 5 DJST: DCI Data Justification Control bit 1 = Data transmission/reception is begun during the same serial clock cycle as the frame synchronization pulse 0 = Data transmission/reception is begun one serial clock cycle after frame synchronization pulse bit 4-2 Unimplemented: Read as ‘0’ bit 1-0 COFSM<1:0>: Frame Sync Mode bits 11 = 20-bit AC-Link mode 10 = 16-bit AC-Link mode 01 = I2S Frame Sync mode 00 = Multi-Channel Frame Sync mode © 2007-2012 Microchip Technology Inc. DS70292G-page 257

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 20-2: DCICON2: DCI CONTROL REGISTER 2 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 — — — — BLEN<1:0> — COFSG3 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 COFSG<2:0> — WS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-10 BLEN<1:0>: Buffer Length Control bits 11 = Four data words will be buffered between interrupts 10 = Three data words will be buffered between interrupts 01 = Two data words will be buffered between interrupts 00 = One data word will be buffered between interrupts bit 9 Unimplemented: Read as ‘0’ bit 8-5 COFSG<3:0>: Frame Sync Generator Control bits 1111 = Data frame has 16 words • • • 0010 = Data frame has 3 words 0001 = Data frame has 2 words 0000 = Data frame has 1 word bit 4 Unimplemented: Read as ‘0’ bit 3-0 WS<3:0>: DCI Data Word Size bits 1111 = Data word size is 16 bits • • • 0100 = Data word size is 5 bits 0011 = Data word size is 4 bits 0010 = Invalid Selection. Do not use. Unexpected results may occur. 0001 = Invalid Selection. Do not use. Unexpected results may occur. 0000 = Invalid Selection. Do not use. Unexpected results may occur. DS70292G-page 258 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 20-3: DCICON3: DCI CONTROL REGISTER 3 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — BCG<11:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BCG<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 BCG<11:0>: DCI Bit Clock Generator Control bits © 2007-2012 Microchip Technology Inc. DS70292G-page 259

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 20-4: DCISTAT: DCI STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — SLOT<3:0> bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ROV RFUL TUNF TMPTY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SLOT<3:0>: DCI Slot Status bits 1111 = Slot 15 is currently active • • • 0010 = Slot 2 is currently active 0001 = Slot 1 is currently active 0000 = Slot 0 is currently active bit 7-4 Unimplemented: Read as ‘0’ bit 3 ROV: Receive Overflow Status bit 1 = A receive overflow has occurred for at least one receive register 0 = A receive overflow has not occurred bit 2 RFUL: Receive Buffer Full Status bit 1 = New data is available in the receive registers 0 = The receive registers have old data bit 1 TUNF: Transmit Buffer Underflow Status bit 1 = A transmit underflow has occurred for at least one transmit register 0 = A transmit underflow has not occurred bit 0 TMPTY: Transmit Buffer Empty Status bit 1 = The transmit registers are empty 0 = The transmit registers are not empty DS70292G-page 260 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 20-5: RSCON: DCI RECEIVE SLOT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RSE<15:0>: Receive Slot Enable bits 1 = CSDI data is received during the individual time slot n 0 = CSDI data is ignored during the individual time slot n REGISTER 20-6: TSCON: DCI TRANSMIT SLOT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TSE15 TSE14 TSE13 TSE12 TSE11 TSE10 TSE9 TSE8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TSE7 TSE6 TSE5 TSE4 TSE3 TSE2 TSE1 TSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 TSE<15:0>: Transmit Slot Enable Control bits 1 = Transmit buffer contents are sent during the individual time slot n 0 = CSDO pin is tri-stated or driven to logic ‘0’, during the individual time slot, depending on the state of the CSDOM bit © 2007-2012 Microchip Technology Inc. DS70292G-page 261

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 262 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 21.0 10-BIT/12-BIT ANALOG-TO- Depending on the particular device pinout, the ADC DIGITAL CONVERTER (ADC) can have up to 13 analog input pins, designated AN0 through AN12. In addition, there are two analog input Note1: This data sheet summarizes the features pins for external voltage reference connections. These of the dsPIC33FJ32GP302/304, voltage reference inputs can be shared with other ana- dsPIC33FJ64GPX02/X04, and log input pins. The actual number of analog input pins dsPIC33FJ128GPX02/X04 families of and external voltage reference input configuration devices. It is not intended to be a compre- depends on the specific device. hensive reference source. To comple- Block diagrams of the ADC module are shown in ment the information in this data sheet, Figure21-1 and Figure21-2. refer to Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) of the 21.2 ADC Initialization “dsPIC33F/PIC24H Family Reference Manual”, which is available from the The following configuration steps should be performed. Microchip website (www.microchip.com). 1. Configure the ADC module: 2: Some registers and associated bits a) Select port pins as analog inputs described in this section may not be avail- (AD1PCFGH<15:0> or AD1PCFGL<15:0>) able on all devices. Refer to Section4.0 b) Select voltage reference source to match “Memory Organization” in this data expected range on analog inputs sheet for device-specific register and bit (AD1CON2<15:13>) information. c) Select the analog conversion clock to The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ match desired data rate with processor X04, and dsPIC33FJ128GPX02/X04 devices have up clock (AD1CON3<7:0>) to 13 ADC input channels. d) Determine how many S/H channels are used (AD1CON2<9:8> and The AD12B bit (AD1CON1<10>) allows each of the AD1PCFGH<15:0> or AD1PCFGL<15:0>) ADC modules to be configured by the user as either a 10-bit, 4-sample/hold ADC (default configuration) or a e) Select the appropriate sample/conversion 12-bit, 1-sample/hold ADC. sequence (AD1CON1<7:5> and AD1CON3<12:8>) Note: The ADC module needs to be disabled f) Select how conversion results are before modifying the AD12B bit. presented in the buffer (AD1CON1<9:8>) g) Turn on ADC module (AD1CON1<15>) 21.1 Key Features 2. Configure ADC interrupt (if required): The 10-bit ADC configuration has the following key a) Clear the AD1IF bit features: b) Select ADC interrupt priority • Successive Approximation (SAR) conversion 21.3 ADC and DMA • Conversion speeds of up to 1.1 Msps • Up to 13 analog input pins If more than one conversion result needs to be buffered • External voltage reference input pins before triggering an interrupt, DMA data transfers can • Simultaneous sampling of up to four analog input be used. ADC1 can trigger a DMA data transfer. If pins ADC1 is selected as the DMA IRQ source, a DMA transfer occurs when the AD1IF bit gets set as a result • Automatic Channel Scan mode of an ADC1 sample conversion sequence. • Selectable conversion trigger source The SMPI<3:0> bits (AD1CON2<5:2>) are used to • Selectable Buffer Fill modes select how often the DMA RAM buffer pointer is • Four result alignment options (signed/unsigned, incremented. fractional/integer) The ADDMABM bit (AD1CON1<12>) determines how • Operation during CPU Sleep and Idle modes the conversion results are filled in the DMA RAM buffer The 12-bit ADC configuration supports all the above area being used for ADC. If this bit is set, DMA buffers features, except: are written in the order of conversion. The module • In the 12-bit configuration, conversion speeds of provides an address to the DMA channel that is the up to 500 ksps are supported same as the address used for the non-DMA stand- alone buffer. If the ADDMABM bit is cleared, then DMA • There is only one sample/hold amplifier in the buffers are written in Scatter/Gather mode. The module 12-bit configuration, so simultaneous sampling of provides a scatter/gather address to the DMA channel, multiple channels is not supported based on the index of the analog input and the size of the DMA buffer. © 2007-2012 Microchip Technology Inc. DS70292G-page 263

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 21-1: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ32GP304, dsPIC33FJ64GP204/804 AND dsPIC33FJ128GP204/804 DEVICES AN0 AN12 S/H0 CHANNEL SCAN + CH0SB<4:0> CH0SA<4:0> - CH0 CSCNA AN1 VREFL CH0NA CH0NB AN0 AVDD VREF-(1) AN3 S/H1 VREF+(1) AVSS + CH123SA CH123SB - CH1(2) AN6 AN9 VCFG<2:0> VREFL VREFH VREFL CH123NA CH123NB SAR ADC ADC1BUF0 AN1 AN4 S/H2 + CH123SACH123SB - CH2(2) AN7 AN10 VREFL CH123NA CH123NB AN2 AN5 S/H3 + CH123SA CH123SB CH3(2) - AN8 AN11 VREFL CH123NA CH123NB Alternate Input Selection Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. DS70292G-page 264 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 21-2: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ32GP302, dsPIC33FJ64GP202/802 AND dsPIC33FJ128GP202/802 DEVICES AN0 AN12 S/H0 CHANNEL SCAN + CH0SA<4:0> CH0SB<4:0> - CH0 CSCNA AN1 VREFL CH0NA CH0NB AN0 AVDD VREF-(1) AN3 S/H1 VREF+(1) AVSS + CH123SA CH123SB - CH1(2) AN9 VCFG<2:0> VREFL VREFH VREFL CH123NA CH123NB SAR ADC ADC1BUF0 AN1 AN4 S/H2 + CH123SACH123SB - CH2(2) AN10 VREFL CH123NA CH123NB AN2 AN5 S/H3 + CH123SA CH123SB CH3(2) - AN11 VREFL CH123NA CH123NB Alternate Input Selection Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. © 2007-2012 Microchip Technology Inc. DS70292G-page 265

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 21-3: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM AD1CON3<15> ADC Internal RC Clock(2) 1 TAD AD1CON3<5:0> 0 6 ADC Conversion TCY Clock Multiplier TOSC(1) X2 1, 2, 3, 4, 5,..., 64 Note 1: Refer to Figure9-2 for the derivation of Fosc when the PLL is enabled. If the PLL is not used, Fosc is equal to the clock source frequency. Tosc = 1/Fosc. 2: See the ADC electrical characteristics for the exact RC clock value. DS70292G-page 266 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 21.4 ADC Helpful Tips 21.5 ADC Resources 1. The SMPI<3:0> (AD1CON2<5:2>) control bits: Many useful resources related to ADC are provided on a) Determine when the ADC interrupt flag is the main product page of the Microchip web site for the set and an interrupt is generated if enabled. devices listed in this data sheet. This product page, which can be accessed using this link, contains the b) When the CSCNA bit (AD1CON2<10>) is latest updates and additional information. set to ‘1’, determines when the ADC analog scan channel list defined in the AD1CSSL/ Note: In the event you are not able to access the AD1CSSH registers starts over from the product page using the link above, enter beginning. this URL in your browser: c) On devices without a DMA peripheral, http://www.microchip.com/wwwproducts/ determines when ADC result buffer pointer Devices.aspx?dDocName=en532311 to ADC1BUF0-ADC1BUFF, gets reset back to the beginning at ADC1BUF0. 21.5.1 KEY RESOURCES 2. On devices without a DMA module, the ADC has • Section 16. “Analog-to-Digital Converter 16 result buffers. ADC conversion results are (ADC)” (DS70183) stored sequentially in ADC1BUF0-ADC1BUFF • Code Samples regardless of which analog inputs are being • Application Notes used subject to the SMPI<3:0> bits (AD1CON2<5:2>) and the condition described • Software Libraries in 1c above. There is no relationship between • Webinars the ANx input being measured and which ADC • All related dsPIC33F/PIC24H Family Reference buffer (ADC1BUF0-ADC1BUFF) that the Manuals Sections conversion results will be placed in. • Development Tools 3. On devices with a DMA module, the ADC mod- ule has only 1 ADC result buffer, (i.e., ADC1BUF0), per ADC peripheral and the ADC conversion result must be read either by the CPU or DMA controller before the next ADC conversion is complete to avoid overwriting the previous value. 4. The DONE bit (AD1CON1<0>) is only cleared at the start of each conversion and is set at the completion of the conversion, but remains set indefinitely even through the next sample phase until the next conversion begins. If application code is monitoring the DONE bit in any kind of software loop, the user must consider this behavior because the CPU code execution is faster than the ADC. As a result, in manual sam- ple mode, particularly where the users code is setting the SAMP bit (AD1CON1<1>), the DONE bit should also be cleared by the user application just before setting the SAMP bit. 5. On devices with two ADC modules, the ADCxPCFG registers for both ADC modules must be set to a logic ‘1’ to configure a target I/O pin as a digital I/O pin. Failure to do so means that any alternate digital input function will always see only a logic ‘0’ as the digital input buffer is held in Disable mode. © 2007-2012 Microchip Technology Inc. DS70292G-page 267

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 21.6 ADC Control Registers REGISTER 21-1: AD1CON1: ADC1 CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 ADON — ADSIDL ADDMABM — AD12B FORM<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/C-0 HC,HS HC, HS SSRC<2:0> — SIMSAM ASAM SAMP DONE bit 7 bit 0 Legend: HC = Cleared by hardware HS = Set by hardware C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: ADC Operating Mode bit 1 = ADC module is operating 0 = ADC is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 ADDMABM: DMA Buffer Build Mode bit 1 = DMA buffers are written in the order of conversion. The module provides an address to the DMA channel that is the same as the address used for the non-DMA stand-alone buffer 0 = DMA buffers are written in Scatter/Gather mode. The module provides a scatter/gather address to the DMA channel, based on the index of the analog input and the size of the DMA buffer bit 11 Unimplemented: Read as ‘0’ bit 10 AD12B: 10-bit or 12-bit Operation Mode bit 1 = 12-bit, 1-channel ADC operation 0 = 10-bit, 4-channel ADC operation bit 9-8 FORM<1:0>: Data Output Format bits For 10-bit operation: 11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s =.NOT.d<9>) 10 = Fractional (DOUT = dddd dddd dd00 0000) 01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>) 00 = Integer (DOUT = 0000 00dd dddd dddd) For 12-bit operation: 11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s = .NOT.d<11>) 10 = Fractional (DOUT = dddd dddd dddd 0000) 01 = Signed Integer (DOUT = ssss sddd dddd dddd, where s = .NOT.d<11>) 00 = Integer (DOUT = 0000 dddd dddd dddd) bit 7-5 SSRC<2:0>: Sample Clock Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 101 = Reserved 100 = GP timer (Timer5 for ADC1) compare ends sampling and starts conversion 011 = Reserved 010 = GP timer (Timer3 for ADC1) compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing sample bit ends sampling and starts conversion bit 4 Unimplemented: Read as ‘0’ DS70292G-page 268 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 21-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ 1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01) 0 = Samples multiple channels individually in sequence bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion. SAMP bit is auto-set 0 = Sampling begins when SAMP bit is set bit 1 SAMP: ADC Sample Enable bit 1 = ADC sample/hold amplifiers are sampling 0 = ADC sample/hold amplifiers are holding If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000, automatically cleared by hardware to end sampling and start conversion. bit 0 DONE: ADC Conversion Status bit 1 = ADC conversion cycle is completed. 0 = ADC conversion not started or in progress Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion. © 2007-2012 Microchip Technology Inc. DS70292G-page 269

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 21-2: AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 VCFG<2:0> — — CSCNA CHPS<1:0> bit 15 bit 8 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS — SMPI<3:0> BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits ADREF+ ADREF- 000 AVDD AVSS 001 External VREF+ AVSS 010 AVDD External VREF- 011 External VREF+ External VREF- 1xx AVDD Avss bit 12-11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Scan Input Selections for CH0+ during Sample A bit 1 = Scan inputs 0 = Do not scan inputs bit 9-8 CHPS<1:0>: Selects Channels Utilized bits When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’ 1x = Converts CH0, CH1, CH2 and CH3 01 = Converts CH0 and CH1 00 = Converts CH0 bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1) 1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7 0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF bit 6 Unimplemented: Read as ‘0’ bit 5-2 SMPI<3:0>: Selects Increment Rate for DMA Addresses bits or number of sample/conversion operations per interrupt 1111 = Increments the DMA address or generates interrupt after completion of every 16th sample/ conversion operation 1110 = Increments the DMA address or generates interrupt after completion of every 15th sample/ conversion operation • • • 0001 = Increments the DMA address after completion of every 2nd sample/conversion operation 0000 = Increments the DMA address after completion of every sample/conversion operation bit 1 BUFM: Buffer Fill Mode Select bit 1 = Starts buffer filling at address 0x0 on first interrupt and 0x8 on next interrupt 0 = Always starts filling buffer at address 0x0 bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A DS70292G-page 270 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 21-3: AD1CON3: ADC1 CONTROL REGISTER 3 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — — SAMC<4:0>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from system clock bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 SAMC<4:0>: Auto Sample Time bits(1) 11111 = 31 TAD • • • 00001 = 1 TAD 00000 = 0 TAD bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2) 11111111 = Reserved • • • • 01000000 = Reserved 00111111 = TCY · (ADCS<7:0> + 1) = 64 · TCY = TAD • • • 00000010 = TCY · (ADCS<7:0> + 1) = 3 · TCY = TAD 00000001 = TCY · (ADCS<7:0> + 1) = 2 · TCY = TAD 00000000 = TCY · (ADCS<7:0> + 1) = 1 · TCY = TAD Note 1: This bit only used if AD1CON1<7:5> (SSRC<2:0>) = 111. 2: This bit is not used if AD1CON3<15> (ADRC) = 1. © 2007-2012 Microchip Technology Inc. DS70292G-page 271

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 21-4: AD1CON4: ADC1 CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — DMABL<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits 111 = Allocates 128 words of buffer to each analog input 110 = Allocates 64 words of buffer to each analog input 101 = Allocates 32 words of buffer to each analog input 100 = Allocates 16 words of buffer to each analog input 011 = Allocates 8 words of buffer to each analog input 010 = Allocates 4 words of buffer to each analog input 001 = Allocates 2 words of buffer to each analog input 000 = Allocates 1 word of buffer to each analog input DS70292G-page 272 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 21-5: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CH123NB<1:0> CH123SB bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CH123NA<1:0> CH123SA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits When AD12B = 1, CHxNB is: U-0, Unimplemented, Read as ‘0’ 11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8(1) 0x = CH1, CH2, CH3 negative input is VREF- bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’ 1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 bit 7-3 Unimplemented: Read as ‘0’ bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits When AD12B = 1, CHxNA is: U-0, Unimplemented, Read as ‘0’ 11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8(1) 0x = CH1, CH2, CH3 negative input is VREF- bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’ 1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 Note 1: This bit setting is Reserved in dsPIC33FJ128GPX02, dsPIC33FJ64GPX02 and dsPIC33FJGPX02 (28-pin) devices. © 2007-2012 Microchip Technology Inc. DS70292G-page 273

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 21-6: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB — — CH0SB<4:0> bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — CH0SA<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit Same definition as bit 7. bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits 01100 = Channel 0 positive input is AN12 01011 = Channel 0 positive input is AN11 • • • 01000 = Channel 0 positive input is AN8(1) 00111 = Channel 0 positive input is AN7(1) 00110 = Channel 0 positive input is AN6(1) • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREF- bit 6-5 Unimplemented: Read as ‘0’ bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits 01100 = Channel 0 positive input is AN12 01011 = Channel 0 positive input is AN11 • • • 01000 = Channel 0 positive input is AN8(1) 00111 = Channel 0 positive input is AN7(1) 00110 = Channel 0 positive input is AN6(1) • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 Note 1: These bit settings are reserved on dsPIC33FJ128GPX02, dsPIC33FJ64GPX02 and dsPIC33FJ32GPX02 (28-pin) devices. DS70292G-page 274 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 21-7: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1,2) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CSS12 CSS11 CSS10 CSS9 CSS8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 CSS<11:0>: ADC Input Scan Selection bits 1 = Select ANx for input scan 0 = Skip ANx for input scan Note 1: On devices without 13 analog inputs, all AD1CSSL bits can be selected by the user application. However, inputs selected for scan without a corresponding input on device converts VREFL. 2: CSSx = ANx, where x = 0 through 12. REGISTER 21-8: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW(1,2,3) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-0 PCFG<12:0>: ADC Port Configuration Control bits 1 = Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AVSS 0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage Note 1: On devices without 13 analog inputs, all PCFG bits are R/W by user software. However, the PCFG bits are ignored on ports without a corresponding input on device. 2: PCFGx = ANx, where x = 0 through 12. 3: PCFGx bits have no effect if ADC module is disabled by setting ADxMD bit in the PMDx Register. In this case all port pins multiplexed with ANx will be in Digital mode. © 2007-2012 Microchip Technology Inc. DS70292G-page 275

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 276 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 22.0 AUDIO DIGITAL-TO-ANALOG control applications where the DAC output controls an CONVERTER (DAC) important processor or machinery. The DACDFLT register should be initialized with a “safe” output value. Often the safe output value is either the midpoint value Note1: This data sheet summarizes the features (0x8000) or a zero value (0x0000). of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and The digital interpolator up-samples the input signals, dsPIC33FJ128GPX02/X04 families of where the over-sampling ratio is 256x which creates devices. It is not intended to be a compre- data points between the user supplied data points. hensive reference source. To comple- The interpolator also includes processing by digital ment the information in this data sheet, filters to provide “noise shaping” to move the refer to Section 33. “Audio Digital-to- converter noise above 20 kHz (upper limit of the pass Analog Converter (DAC)” (DS70211) of band). The output of the interpolator drives the Sigma- the “dsPIC33F/PIC24H Family Reference Delta modulator. The serial data bit stream from the Manual”, which is available from the Sigma-Delta modulator is processed by the Microchip website (www.microchip.com). reconstruction filter. The differential outputs of the reconstruction filter are amplified by Op Amps to 2: Some registers and associated bits provide the required peak-to-peak voltage swing. described in this section may not be avail- able on all devices. Refer to Section4.0 Note: The DAC module is designed specifically “Memory Organization” in this data for audio applications and is not sheet for device-specific register and bit recommended for control type information. applications. The Audio Digital-to-Analog Converter (DAC) module is a 16-bit Delta-Sigma signal converter designed for 22.3 DAC Output Format audio applications. It has two output channels, left and The DAC output data stream can be in a two’s comple- right to support stereo applications. Each DAC output ment signed number format or as an unsigned number channel provides three voltage outputs, positive DAC format. output, negative DAC output, and the midpoint voltage output for the dsPIC33FJ64GP804 and The Audio DAC module features the ability to accept dsPIC33FJ128GP804 devices. The the 16-bit input data in a two’s complement signed dsPIC33FJ64GP802 and dsPIC33FJ128GP802 number format or as an unsigned number format. devices provide positive DAC output and negative DAC The data formatting is controlled by the Data Format output voltages. Control bit (FORM<8>) in the DAC1CON register. The supported formats are: 22.1 Key Features • 1 = Signed (two’s complement) • 0 = Unsigned • 16-bit resolution (14-bit accuracy) • Second-Order Digital Delta-Sigma Modulator If the FORM bit is configured for “Unsigned data” then the user input data yields the following behavior: • 256 X Over-Sampling Ratio • 128-Tap FIR Current-Steering Analog Recon- • 0xFFFF = most positive output voltage struction Filter • 0x8000 = mid point output voltage • 100 ksps Maximum Sampling Rate • 0x7FFF = a value just below the midpoint • User controllable Sample Clock • 0x0000 = minimum output voltage • Input Frequency 45 kHz max If the FORM bit is configured for “signed data” then the • Differential Analog Outputs user input data yields the following behavior: • Signal-To-Noise: 90 dB • 0x7FFF = most positive output voltage • 4-deep input Buffer • 0x0000 = mid point output voltage • 16-bit Processor I/O, and DMA interfaces • 0xFFFF = value just below the midpoint • 0x8000 = minimum output voltage 22.2 DAC Module Operation The Audio DAC provides an analog output proportional The functional block diagram of the Audio DAC module to the digital input value. The maximum 100,000 is shown in Figure22-1. The Audio DAC module samples per second (100 ksps) update rate provides provides a 4-deep data input FIFO buffer for each good quality audio reproduction. output channel. If the DMA module and/or the processor cannot provide output data in a timely manner, and the FIFO becomes empty, the DAC accepts data from the DAC Default Data register (DACDFLT). This safety feature is useful for industrial © 2007-2012 Microchip Technology Inc. DS70292G-page 277

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 22.4 DAC Clock The divisor ratio is programmed by clock divider bits (DACFDIV<6:0>) in the DAC Control register The DAC clock signal clocks the internal logic of the (DAC1CON). The resulting DAC clock must not exceed Audio DAC module. The data sample rate of the Audio 25.6 MHz. If lower sample rates are to be used, then DAC is an integer division of the rate of the DAC clock. the DAC filter clock frequency may be reduced to The DAC clock is generated via a clock divider circuit reduce power consumption. The DAC clock frequency that accepts an auxiliary clock from the auxiliary is 256 times the sampling frequency. oscillator. FIGURE 22-1: BLOCK DIAGRAM OF AUDIO DIGITAL-TO-ANALOG (DAC) CONVERTER Right Channel DAC1RM DAC1RDAT DAC1RP D/A Amp DAC1RN Note 1 s u B ACLK a Dat CONTROL DACFDIV<6:0> CLK DIV DACDFLT bit 6- 1 DAC1LM DAC1LP D/A Amp DAC1LN DAC1LDAT Note 1 Left Channel Note 1: If DAC1RDAT and DAC1LDAT are empty, data will be taken from the DACDFLT register. FIGURE 22-2: AUDIO DAC OUTPUT FOR RAMP INPUT (UNSIGNED) 0xFFFF DAC input Count (DAC1RDAT) 0x0000 VDACH VDACM Positive DAC Output (DAC1RP) VDACL VDACH Negative DAC VDACM Output (DAC1RN) VDACL Note: VOD+ = VDACH – VDACL, VOD- = VDACL – VDACH; refer to Audio DAC Module Specifications, Table30-46, for typical values. DS70292G-page 278 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 22.5 DAC Resources Many useful resources related to DAC are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 22.5.1 KEY RESOURCES • Section 33. “Audio Digital-to-Analog Converter (DAC)” (DS70211) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools © 2007-2012 Microchip Technology Inc. DS70292G-page 279

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 22.6 DAC Control Registers REGISTER 22-1: DAC1CON: DAC CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 DACEN — DACSIDL AMPON — — — FORM bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 — DACFDIV<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DACEN: DAC1 Enable bit 1 = Enables module 0 = Disables module bit 14 Unimplemented: Read as ‘0’ bit 13 DACSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 AMPON: Enable Analog Output Amplifier in Sleep Mode/Stop in Idle Mode bit 1 = Analog Output Amplifier is enabled during Sleep Mode/Stop in Idle mode 0 = Analog Output Amplifier is disabled during Sleep Mode/Stop in Idle mode bit 11-9 Unimplemented: Read as ‘0’ bit 8 FORM: Data Format Select bit 1 = Signed integer 0 = Unsigned integer bit 7 Unimplemented: Read as ‘0’ bit 6-0 DACFDIV<6:0>: DAC Clock Divider bit 1111111 = Divide input clock by 128 • • • 0000101 = Divide input clock by 6 (default) • • • 0000010 = Divide input clock by 3 0000001 = Divide input clock by 2 0000000 = Divide input clock by 1 (no divide) DS70292G-page 280 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 22-2: DAC1STAT: DAC STATUS REGISTER R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R-0 R-0 LOEN — LMVOEN — — LITYPE LFULL LEMPTY bit 15 bit 8 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R-0 R-0 ROEN — RMVOEN — — RITYPE RFULL REMPTY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 LOEN: Left Channel DAC Output Enable bit 1 = Positive and negative DAC outputs are enabled 0 = DAC outputs are disabled bit 14 Unimplemented: Read as ‘0’ bit 13 LMVOEN: Left Channel Midpoint DAC Output Voltage Enable bit 1 = Midpoint DAC output is enabled 0 = Midpoint output is disabled bit 12-11 Unimplemented: Read as ‘0’ bit 10 LITYPE: Left Channel Type of Interrupt bit 1 = Interrupt if FIFO is Empty 0 = Interrupt if FIFO is not Full bit 9 LFULL: Status, Left Channel Data Input FIFO is Full bit 1 = FIFO is Full 0 = FIFO is not full bit 8 LEMPTY: Status, Left Channel Data Input FIFO is Empty bit 1 = FIFO is Empty 0 = FIFO is not Empty bit 7 ROEN: Right Channel DAC Output Enable bit 1 = Positive and negative DAC outputs are enabled 0 = DAC outputs are disabled bit 6 Unimplemented: Read as ‘0’ bit 5 RMVOEN: Right Channel Midpoint DAC Output Voltage Enable bit 1 = Midpoint DAC output is enabled 0 = Midpoint output is disabled bit 4-3 Unimplemented: Read as ‘0’ bit 2 RITYPE: Right Channel Type of Interrupt bit 1 = Interrupt if FIFO is Empty 0 = Interrupt if FIFO is not Full bit 1 RFULL: Status, Right Channel Data Input FIFO is Full bit 1 = FIFO is Full 0 = FIFO is not full bit 0 REMPTY: Status, Right Channel Data Input FIFO is Empty bit 1 = FIFO is Empty 0 = FIFO is not Empty © 2007-2012 Microchip Technology Inc. DS70292G-page 281

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 R EGISTER 22-3: DAC1DFLT: DAC DEFAULT DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACDFLT<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACDFLT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DACDFLT<15:0>: DAC Default Value bits REGISTER 22-4: DAC1LDAT: DAC LEFT DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACLDAT<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACLDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DACLDAT<15:0>: Left Channel Data Port bits REGISTER 22-5: DAC1RDAT: DAC RIGHT DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACRDAT<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACRDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DACRDAT<15:0>: Right Channel Data Port bits DS70292G-page 282 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 23.0 COMPARATOR MODULE The Comparator module provides a set of dual input comparators. The inputs to the comparator can be con- Note1: This data sheet summarizes the features figured to use any one of the four pin inputs (C1IN+, of the dsPIC33FJ32GP302/304, C1IN-, C2IN+ and C2IN-) as well as the Comparator dsPIC33FJ64GPX02/X04, and Voltage Reference Input (CVREF). dsPIC33FJ128GPX02/X04 families of Note: This peripheral contains output func- devices. It is not intended to be a tions that may need to be configured by comprehensive reference source. To the peripheral pin select feature. For complement the information in this data more information, see Section11.6 sheet, refer to Section 34. “Peripheral Pin Select”. “Comparator” (DS70212) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be avail- able on all devices. Refer to Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 23-1: COMPARATOR I/O OPERATING MODES C1NEG C1EN C1OUT (CMCON<6>) C1INV C1IN+ VIN- C1IN- C1OUT(1) C1POS C1 C1IN+ VIN+ C1OUTEN CVREF C2NEG C2OUT (CMCON<7>) C2EN C2INV C2IN+ VIN- C2IN- C2OUT(1) C2POS C2 C2IN+ VIN+ C2OUTEN CVREF Note1: This peripheral’s outputs must be assigned to an available RPn pin before use. Refer to Section11.6 “Peripheral Pin Select” for more information. © 2007-2012 Microchip Technology Inc. DS70292G-page 283

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 23.1 Comparator Resources Many useful resources related to Comparators are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 23.1.1 KEY RESOURCES • Section 34. “Comparator” (DS70212) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70292G-page 284 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 23.2 Comparator Control Register REGISTER 23-1: CMCON: COMPARATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMIDL — C2EVT C1EVT C2EN C1EN C2OUTEN(1) C1OUTEN(2) bit 15 bit 8 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT C2INV C1INV C2NEG C2POS C1NEG C1POS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMIDL: Stop in Idle Mode bit 1 = When device enters Idle mode, module does not generate interrupts. Module is still enabled. 0 = Continue normal module operation in Idle mode bit 14 Unimplemented: Read as ‘0’ bit 13 C2EVT: Comparator 2 Event bit 1 = Comparator output changed states 0 = Comparator output did not change states bit 12 C1EVT: Comparator 1 Event bit 1 = Comparator output changed states 0 = Comparator output did not change states bit 11 C2EN: Comparator 2 Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 10 C1EN: Comparator 1 Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 9 C2OUTEN: Comparator 2 Output Enable bit(1) 1 = Comparator output is driven on the output pad 0 = Comparator output is not driven on the output pad bit 8 C1OUTEN: Comparator 1 Output Enable bit(2) 1 = Comparator output is driven on the output pad 0 = Comparator output is not driven on the output pad bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 0 = C2 VIN+ > C2 VIN- 1 = C2 VIN+ < C2 VIN- Note 1: If C2OUTEN=1, the C2OUT peripheral output must be configured to an available RPx pin. See Section11.6 “Peripheral Pin Select” for more information. 2: If C1OUTEN=1, the C1OUT peripheral output must be configured to an available RPx pin. See Section11.6 “Peripheral Pin Select” for more information. © 2007-2012 Microchip Technology Inc. DS70292G-page 285

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 23-1: CMCON: COMPARATOR CONTROL REGISTER (CONTINUED) bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 0 = C1 VIN+ > C1 VIN- 1 = C1 VIN+ < C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 C2NEG: Comparator 2 Negative Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to VIN- See Figure23-1 for the comparator modes. bit 2 C2POS: Comparator 2 Positive Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to CVREF See Figure23-1 for the comparator modes. bit 1 C1NEG: Comparator 1 Negative Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to VIN- See Figure23-1 for the comparator modes. bit 0 C1POS: Comparator 1 Positive Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to CVREF See Figure23-1 for the comparator modes. Note 1: If C2OUTEN=1, the C2OUT peripheral output must be configured to an available RPx pin. See Section11.6 “Peripheral Pin Select” for more information. 2: If C1OUTEN=1, the C1OUT peripheral output must be configured to an available RPx pin. See Section11.6 “Peripheral Pin Select” for more information. DS70292G-page 286 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 23.3 Comparator Voltage Reference The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and 23.3.1 CONFIGURING THE COMPARATOR VREF-. The voltage source is selected by the CVRSS VOLTAGE REFERENCE bit (CVRCON<4>). The voltage reference module is controlled through the The settling time of the comparator voltage reference CVRCON register (Register23-2). The comparator must be considered when changing the CVREF voltage reference provides two ranges of output output. voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR3:CVR0), with one range offering finer resolution. FIGURE 23-2: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 VREF+ CVRSRC CVRCON<3:0> 3210 AVDD CVRSS = 0 8R VRVRVRVR CCCC CVREN R CVREFIN R R R X U M 16 Steps 1 CVREF o- 6-t 1 R CVROE (CVRCON<6>) R R CVRR 8R CVRSS = 1 VREF- AVSS CVRSS = 0 © 2007-2012 Microchip Technology Inc. DS70292G-page 287

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 23-2: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ – VREF- 0 = Comparator reference source CVRSRC = AVDD – AVSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection 0 ≤ CVR<3:0> ≤ 15 bits When CVRR = 1: CVREF = (CVR<3:0>/ 24) • (CVRSRC) When CVRR = 0: CVREF = 1/4 • (CVRSRC)+ (CVR<3:0>/32) • (CVRSRC) DS70292G-page 288 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 24.0 REAL-TIME CLOCK AND • Time: hours, minutes, and seconds CALENDAR (RTCC) • 24-hour format (military time) • Calendar: weekday, date, month and year Note1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, • Alarm configurable dsPIC33FJ64GPX02/X04, and • Year range: 2000 to 2099 dsPIC33FJ128GPX02/X04 families of • Leap year correction devices. It is not intended to be a compre- hensive reference source. To comple- • BCD format for compact firmware ment the information in this data sheet, • Optimized for low-power operation refer to Section 37. “Real-Time Clock • User calibration with auto-adjust and Calendar (RTCC)” (DS70301) of the “dsPIC33F/PIC24H Family Reference • Calibration range: ±2.64 seconds error per month Manual”, which is available from the • Requirements: External 32.768 kHz clock crystal Microchip website (www.microchip.com). • Alarm pulse or seconds clock output on RTCC pin 2: Some registers and associated bits described in this section may not be avail- The RTCC module is intended for applications where able on all devices. Refer to Section4.0 accurate time must be maintained for extended periods “Memory Organization” in this data of time with minimum to no intervention from the CPU. sheet for device-specific register and bit The RTCC module is optimized for low-power usage to information. provide extended battery lifetime while keeping track of time. This chapter discusses the Real-Time Clock and The RTCC module is a 100-year clock and calendar Calendar (RTCC) module, available on with automatic leap year detection. The range of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, clock is from 00:00:00 (midnight) on January 1, 2000 to and dsPIC33FJ128GPX02/X04 devices, and its 23:59:59 on December 31, 2099. operation. The following are some of the key features of this module: The hours are available in 24-hour (military time) format. The clock provides a granularity of one second with half-second visibility to the user. FIGURE 24-1: RTCC BLOCK DIAGRAM RTCC Clock Domain CPU Clock Domain 32.768 kHz Input RCFGCAL from SOSC Oscillator RTCC Prescalers ALCFGRPT 0.5s RTCC Timer RTCVAL Alarm Event Comparator Compare Registers ALRMVAL with Masks Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE © 2007-2012 Microchip Technology Inc. DS70292G-page 289

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 24.1 RTCC Module Registers By writing the ALRMVALH byte, the Alarm Pointer value, ALRMPTR<1:0> bits, decrement by one until The RTCC module registers are organized into three they reach ‘00’. Once they reach ‘00’, the ALRMMIN categories: and ALRMSEC value will be accessible through • RTCC Control Registers ALRMVALH and ALRMVALL until the pointer value is • RTCC Value Registers manually changed. • Alarm Value Registers TABLE 24-2: ALRMVAL REGISTER 24.1.1 REGISTER MAPPING MAPPING To limit the register interface, the RTCC Timer and Alarm Value Register Window ALRMPTR Alarm Time registers are accessed through corre- <1:0> ALRMVAL<15:8> ALRMVAL<7:0> sponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR 00 ALRMMIN ALRMSEC bits (RCFGCAL<9:8>) to select the desired timer 01 ALRMWD ALRMHR register pair (see Table24-1). 10 ALRMMNTH ALRMDAY By writing the RTCVALH byte, the RTCC Pointer value, 11 — — RTCPTR<1:0> bits, decrement by one until they reach ‘00’. Once they reach ‘00’, the MINUTES and Considering that the 16-bit core does not distinguish SECONDS value will be accessible through RTCVALH between 8-bit and 16-bit read operations, the user must and RTCVALL until the pointer value is manually be aware that when reading either the ALRMVALH or changed. ALRMVALL bytes will decrement the ALRMPTR<1:0> value. The same applies to the RTCVALH or RTCVALL TABLE 24-1: RTCVAL REGISTER MAPPING bytes with the RTCPTR<1:0> being decremented. RTCC Value Register Window Note: This only applies to read operations and RTCPTR not write operations. <1:0> RTCVAL<15:8> RTCVAL<7:0> 00 MINUTES SECONDS 24.1.2 WRITE LOCK 01 WEEKDAY HOURS In order to perform a write to any of the RTCC Timer 10 MONTH DAY registers, the RTCWREN bit (RCFGCAL<13>) must be set (refer to Example24-1). 11 — YEAR Note: To avoid accidental writes to the timer, it is The Alarm Value register window (ALRMVALH and recommended that the RTCWREN bit ALRMVALL) uses the ALRMPTR bits (RCFGCAL<13>) is kept clear at any (ALCFGRPT<9:8>) to select the desired Alarm register other time. For the RTCWREN bit to be pair (see Table24-2). set, there is only 1 instruction cycle time window allowed between the 55h/AA sequence and the setting of RTCWREN; therefore, it is recommended that code follow the procedure in Example24-1. EXAMPLE 24-1: SETTING THE RTCWREN BIT MOV #NVMKEY, W1 ;move the address of NVMKEY into W1 MOV #0x55, W2 MOV #0xAA, W3 MOV W2, [W1] ;start 55/AA sequence MOV W3, [W1] BSET RCFGCAL, #13 ;set the RTCWREN bit DS70292G-page 290 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 24.2 RTCC Resources Many useful resources related to RTCC are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 24.2.1 KEY RESOURCES • Section 37. “Real-Time Clock and Calendar (RTCC)” (DS70301) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools © 2007-2012 Microchip Technology Inc. DS70292G-page 291

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 24.3 RTCC Registers REGISTER 24-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 RTCEN(2) — RTCWREN RTCSYNC HALFSEC(3) RTCOE RTCPTR<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple bit 11 HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second bit 10 RTCOE: RTCC Output Enable bit 1 = RTCC output enabled 0 = RTCC output disabled bit 9-8 RTCPTR<1:0>: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers; the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’. RTCVAL<15:8>: 00 = MINUTES 01 = WEEKDAY 10 = MONTH 11 = Reserved RTCVAL<7:0>: 00 = SECONDS 01 = HOURS 10 = DAY 11 = YEAR Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register. DS70292G-page 292 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) bit 7-0 CAL<7:0>: RTC Drift Calibration bits 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute • • • 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute • • • 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register. © 2007-2012 Microchip Technology Inc. DS70292G-page 293

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RTSECSEL(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers Note 1: To enable the actual RTCC output, the RTCOE bit (RCFGCAL<10>) needs to be set. DS70292G-page 294 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK<3:0> ALRMPTR<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0>=0x00 and CHIME=0) 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit 1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 0x00 to 0xFF 0 = Chime is disabled; ARPT<7:0> bits stop once they reach 0x00 bit 13-10 AMASK<3:0>: Alarm Mask Configuration bits 11xx =Reserved – do not use 101x =Reserved – do not use 1001 =Once a year (except when configured for February 29th, once every 4 years) 1000 =Once a month 0111 =Once a week 0110 =Once a day 0101 =Every hour 0100 =Every 10 minutes 0011 =Every minute 0010 =Every 10 seconds 0001 =Every second 0000 =Every half second bit 9-8 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers; the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVAL<15:8>: 11 = Unimplemented 10 = ALRMMNTH 01 = ALRMWD 00 = ALRMMIN ALRMVAL<7:0>: 11 = Unimplemented 10 = ALRMDAY 01 = ALRMHR 00 = ALRMSEC bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 =Alarm will repeat 255 more times • • • 00000000 =Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 0x00 to 0xFF unless CHIME=1. © 2007-2012 Microchip Technology Inc. DS70292G-page 295

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-4: RTCVAL (WHEN RTCPTR<1:0> = 11): YEAR VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN<3:0> YRONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit; contains a value from 0 to 9 bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit; contains a value from 0 to 9 Note 1: A write to the YEAR register is only allowed when RTCWREN=1. REGISTER 24-5: RTCVAL (WHEN RTCPTR<1:0> = 10): MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R-x R-x R-x R-x R-x — — — MTHTEN0 MTHONE<3:0> bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN<1:0> DAYONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; contains a value of 0 or 1 bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit; contains a value from 0 to 9 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit; contains a value from 0 to 3 bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit; contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN=1. DS70292G-page 296 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-6: RTCVAL (WHEN RTCPTR<1:0> = 01): WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY<2:0> bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN<1:0> HRONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit; contains a value from 0 to 6 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit; contains a value from 0 to 2 bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit; contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 24-7: RTCVAL (WHEN RTCPTR<1:0> = 00): MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN<2:0> MINONE<3:0> bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN<2:0> SECONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit; contains a value from 0 to 5 bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit; contains a value from 0 to 9 bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit; contains a value from 0 to 5 bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit; contains a value from 0 to 9 © 2007-2012 Microchip Technology Inc. DS70292G-page 297

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-8: ALRMVAL (WHEN ALRMPTR<1:0> = 10): ALARM MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE<3:0> bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN<1:0> DAYONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; contains a value of 0 or 1 bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit; contains a value from 0 to 9 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit; contains a value from 0 to 3 bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit; contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 24-9: ALRMVAL (WHEN ALRMPTR<1:0> = 01): ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN<1:0> HRONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit; contains a value from 0 to 6 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit; contains a value from 0 to 2 bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit; contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN=1. DS70292G-page 298 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-10: ALRMVAL (WHEN ALRMPTR<1:0> = 00): ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN<2:0> MINONE<3:0> bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN<2:0> SECONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit; contains a value from 0 to 5 bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit; contains a value from 0 to 9 bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit; contains a value from 0 to 5 bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit; contains a value from 0 to 9 © 2007-2012 Microchip Technology Inc. DS70292G-page 299

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 300 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 25.0 PROGRAMMABLE CYCLIC 25.1 Overview REDUNDANCY CHECK (CRC) The module implements a software configurable CRC GENERATOR generator. The terms of the polynomial and its length can be programmed using the CRCXOR bits (X<15:1>) Note1: This data sheet summarizes the features and the CRCCON bits (PLEN<3:0>), respectively. of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and EQUATION 25-1: CRC EQUATION dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a 16 12 5 comprehensive reference source. To x +x +x +1 complement the information in this data sheet, refer to Section 36. “Programmable Cyclic Redundancy To program this polynomial into the CRC generator, Check (CRC)” (DS70298) of the the CRC register bits should be set as shown in “dsPIC33F/PIC24H Family Reference Table25-1. Manual”, which is available from the Microchip website (www.microchip.com). TABLE 25-1: EXAMPLE CRC SETUP 2: Some registers and associated bits Bit Name Bit Value described in this section may not be PLEN<3:0> 1111 available on all devices. Refer to Section4.0 “Memory Organization” in X<15:1> 000100000010000 this data sheet for device-specific register For the value of X<15:1>, the 12th bit and the 5th bit are and bit information. set to ‘1’, as required by the CRC equation. The 0th bit required by the CRC equation is always XORed. For a The programmable CRC generator offers the following 16-bit polynomial, the 16th bit is also always assumed features: to be XORed; therefore, the X<15:1> bits do not have • User-programmable polynomial CRC equation the 0th bit or the 16th bit. • Interrupt output The topology of a standard CRC generator is shown in • Data FIFO Figure25-2. FIGURE 25-1: CRC SHIFTER DETAILS PLEN<3:0> 0 1 2 15 CRC Shift Register Hold X1 Hold X2 Hold X3 X15 Hold XOR OUT 0 OUT 0 OUT 0 0 OUT IN IN IN IN DOUT BIT 0 BIT 1 BIT 2 BIT 15 1 1 1 1 p_clk p_clk p_clk p_clk CRC Read Bus CRC Write Bus © 2007-2012 Microchip Technology Inc. DS70292G-page 301

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 25-2: CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 1 XOR D Q D Q D Q D Q D Q SDOx BIT 0 BIT 4 BIT 5 BIT 12 BIT 15 p_clk p_clk p_clk p_clk p_clk CRC Read Bus CRC Write Bus 25.2 User Interface To empty words already written into a FIFO, the CRCGO bit must be set to ‘1’ and the CRC shifter 25.2.1 DATA INTERFACE allowed to run until the CRCMPT bit is set. To start serial shifting, a ‘1’ must be written to the Also, to get the correct CRC reading, it will be CRCGO bit. necessary to wait for the CRCMPT bit to go high before reading the CRCWDAT register. The module incorporates a FIFO that is 8 deep when PLEN (PLEN<3:0>)>7, and 16 deep, otherwise. The If a word is written when the CRCFUL bit is set, the data for which the CRC is to be calculated must first be VWORD Pointer will roll over to 0. The hardware will written into the FIFO. The smallest data element that then behave as if the FIFO is empty. However, the con- can be written into the FIFO is one byte. For example, dition to generate an interrupt will not be met; therefore, if PLEN=5, then the size of the data is PLEN+1=6. no interrupt will be generated (See Section25.2.2 The data must be written as follows: “Interrupt Operation”). data[5:0] = crc_input[5:0] At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORD bits is done. data[7:6] = ‘bxx Once data is written into the CRCWDAT MSb (as 25.2.2 INTERRUPT OPERATION defined by PLEN), the value of VWORD When the VWORD<4:0> bits make a transition from a (VWORD<4:0>) increments by one. The serial shifter value of ‘1’ to ‘0’, an interrupt will be generated. starts shifting data into the CRC engine when CRCGO=1 and VWORD>0. When the MSb is 25.3 Operation in Power-Saving Modes shifted out, VWORD decrements by one. The serial shifter continues shifting until the VWORD reaches 0. 25.3.1 SLEEP MODE Therefore, for a given value of PLEN, it will take (PLEN+1)*VWORD number of clock cycles to If Sleep mode is entered while the module is operating, complete the CRC calculations. the module will be suspended in its current state until clock execution resumes. When VWORD reaches 8 (or 16), the CRCFUL bit will be set. When VWORD reaches 0, the CRCMPT bit will 25.3.2 IDLE MODE be set. To continue full module operation in Idle mode, the To continually feed data into the CRC engine, the rec- CSIDL bit must be cleared prior to entry into the mode. ommended mode of operation is to initially “prime” the FIFO with a sufficient number of words so no interrupt If CSIDL=1, the module will behave the same way as is generated before the next word can be written. Once it does in Sleep mode; pending interrupt events will be that is done, start the CRC by setting the CRCGO bit to passed on, even though the module clocks are not ‘1’. From that point onward, the VWORD<4:0> bits available. should be polled. If they read less than 8 or 16, another word can be written into the FIFO. DS70292G-page 302 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 25.4 Programmable CRC Resources Many useful resources related to Programmable CRC are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 25.4.1 KEY RESOURCES • Section 36. “Programmable Cyclic Redundancy Check (CRC)” (DS70298) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools © 2007-2012 Microchip Technology Inc. DS70292G-page 303

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 25.5 Programmable CRC Registers REGISTER 25-1: CRCCON: CRC CONTROL REGISTER U-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0 — — CSIDL VWORD<4:0> bit 15 bit 8 R-0 R-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CRCFUL CRCMPT — CRCGO PLEN<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-8 VWORD<4:0>: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<3:0> is greater than 7, or 16 when PLEN<3:0> is less than or equal to 7. bit 7 CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: FIFO Empty bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 Unimplemented: Read as ‘0’ bit 4 CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = Turn off CRC serial shifter after FIFO is empty bit 3-0 PLEN<3:0>: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1. DS70292G-page 304 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 25-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 X<7:1> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 X<15:1>: XOR of Polynomial Term Xn Enable bits bit 0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. DS70292G-page 305

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 306 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 26.0 PARALLEL MASTER PORT devices and microcontrollers. Because the interface (PMP) to parallel peripherals varies significantly, the PMP is highly configurable. Note1: This data sheet summarizes the features Key features of the PMP module include: of the dsPIC33FJ32GP302/304, • Fully multiplexed address/data mode dsPIC33FJ64GPX02/X04, and • Demultiplexed or partially multiplexed address/ dsPIC33FJ128GPX02/X04 families of data mode: devices. It is not intended to be a compre- hensive reference source. To comple- - Up to 11 address lines with single chip select ment the information in this data sheet, - Up to 12 address lines without chip select refer to Section 35. “Parallel Master • One Chip Select Line Port (PMP)” (DS70299) of the • Programmable Strobe Options “dsPIC33F/PIC24H Family Reference - Individual Read and Write Strobes or; Manual”, which is available from the Microchip website (www.microchip.com). - Read/Write Strobe with Enable Strobe • Address Auto-Increment/Auto-Decrement 2: Some registers and associated bits • Programmable Address/Data Multiplexing described in this section may not be avail- able on all devices. Refer to Section4.0 • Programmable Polarity on Control Signals “Memory Organization” in this data • Legacy Parallel Slave Port Support sheet for device-specific register and bit • Enhanced Parallel Slave Support: information. - Address Support The Parallel Master Port (PMP) module is a parallel - 4-Byte Deep Auto-Incrementing Buffer 8-bit I/O module, specifically designed to communi- • Programmable Wait States cate with a wide variety of parallel devices, such as • Selectable Input Voltage Levels communication peripherals, LCDs, external memory FIGURE 26-1: PMP MODULE OVERVIEW Address Bus Data Bus dsPIC33F PMA<0> Control Lines PMALL Parallel Master Port PMA<1> PMALH Up to 11-bit Address EEPROM PMA<10:2>(1) PMA<14> PMCS1 PMBE PMRD PMRD/PMWR PMWR PMENB FIFO Microcontroller LCD Buffer PMD<7:0> PMA<7:0> PMA<10:8> 8-bit Data Note1: 28-pin devices do not have PMA<10:2>. © 2007-2012 Microchip Technology Inc. DS70292G-page 307

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 26.1 PMP Resources Many useful resources related to PMP are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 26.1.1 KEY RESOURCES • Section 35. “Parallel Master Port (PMP)” (DS70299) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70292G-page 308 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 26.2 PMP Control Registers REGISTER 26-1: PMCON: PARALLEL MASTER PORT CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN bit 15 bit 8 R/W-0 R/W-0 R/W-0(1) U-0 R/W-0(1) R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP — CS1P BEP WRSP RDSP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PMPEN: Parallel Master Port Enable bit 1 = PMP enabled 0 = PMP disabled, no off-chip access performed bit 14 Unimplemented: Read as ‘0’ bit 13 PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits(1) 11 = Reserved 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 3 bits are multiplexed on PMA<10:8> 00 = Address and data appear on separate pins bit 10 PTBEEN: Byte Enable Port Enable bit (16-bit Master mode) 1 = PMBE port enabled 0 = PMBE port disabled bit 9 PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled bit 8 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled bit 7-6 CSF1:CSF0: Chip Select Function bits 11 = Reserved 10 = PMCS1 functions as chip select 0x = PMCS1 functions as address bit 14 bit 5 ALP: Address Latch Polarity bit(1) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 4 Unimplemented: Read as ‘0’ bit 3 CS1P: Chip Select 1 Polarity bit(1) 1 = Active-high (PMCS1/PMCS1) 0 = Active-low (PMCS1/PMCS1) Note 1: These bits have no effect when their corresponding pins are used as address lines. © 2007-2012 Microchip Technology Inc. DS70292G-page 309

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-1: PMCON: PARALLEL MASTER PORT CONTROL REGISTER (CONTINUED) bit 2 BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) bit 1 WRSP: Write Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE<9:8>=00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (PMMODE<9:8>=11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 0 RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE<9:8>=00,01,10): 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master mode 1 (PMMODE<9:8>=11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. DS70292G-page 310 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-2: PMMODE: PARALLEL PORT MODE REGISTER R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAITB<1:0>(1) WAITM<3:0> WAITE<1:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 BUSY: Busy bit (Master mode only) 1 = Port is busy (not useful when the processor stall is active) 0 = Port is not busy bit 14-13 IRQM<1:0>: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = No interrupt generated, processor stall activated 01 = Interrupt generated at the end of the read/write cycle 00 = No interrupt generated bit 12-11 INCM<1:0>: Increment Mode bits 11 = PSP read and write buffers auto-increment (Legacy PSP mode only) 10 = Decrement ADDR<10:0> by 1 every read/write cycle 01 = Increment ADDR<10:0> by 1 every read/write cycle 00 = No increment or decrement of address bit 10 MODE16: 8-bit/16-bit Mode bit 1 = 16-bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers 0 = 8-bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer bit 9-8 MODE<1:0>: Parallel Port Mode Select bits 11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>) 10 = Master mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>) 01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD<7:0>) bit 7-6 WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits(1) 11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY 10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY 01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY 00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY bit 5-2 WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TCY • • • 0001 = Wait of additional 1 TCY 0000 = No additional wait cycles (operation forced into one TCY) bit 1-0 WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits(1) 11 = Wait of 4 TCY 10 = Wait of 3 TCY 01 = Wait of 2 TCY 00 = Wait of 1 TCY Note 1: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000. © 2007-2012 Microchip Technology Inc. DS70292G-page 311

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-3: PMADDR: PARALLEL PORT ADDRESS REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR15 CS1 ADDR<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADDR15: Parallel Port Destination Address bits bit 14 CS1: Chip Select 1 bit 1 = Chip select 1 is active 0 = Chip select 1 is inactive bit 13-0 ADDR13:ADDR0: Parallel Port Destination Address bits REGISTER 26-4: PMAEN: PARALLEL PORT ENABLE REGISTER U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — PTEN14 — — — PTEN<10:8>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<7:2>(1) PTEN<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 PTEN14: PMCS1 Strobe Enable bit 1 = PMA14 functions as either PMA<14> bit or PMCS1 0 = PMA14 pin functions as port I/O bit 13-11 Unimplemented: Read as ‘0’ bit 10-2 PTEN<10:2>: PMP Address Port Enable bits(1) 1 = PMA<10:2> function as PMP address lines 0 = PMA<10:2> function as port I/O bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O Note 1: Devices with 28 pins do not have PMA<10:2>. DS70292G-page 312 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-5: PMSTAT: PARALLEL PORT STATUS REGISTER R-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV — — IB3F IB2F IB1F IB0F bit 15 bit 8 R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: HS = Hardware Set bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty bit 14 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte register occurred (must be cleared in software) 0 = No overflow occurred bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 IB3F:IB0F: Input Buffer x Status Full bits 1 = Input buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input buffer does not contain any unread data bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bits 1 = A read occurred from an empty output byte register (must be cleared in software) 0 = No underflow occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 OB3E:OB0E: Output Buffer x Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted © 2007-2012 Microchip Technology Inc. DS70292G-page 313

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RTSECSEL(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers Note 1: To enable the actual RTCC output, the RTCOE bit (RCFGCAL<10>) needs to be set. DS70292G-page 314 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 27.0 SPECIAL FEATURES 27.1 Configuration Bits Note1: This data sheet summarizes the features The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ of the dsPIC33FJ32GP302/304, X04, and dsPIC33FJ128GPX02/X04 devices provide dsPIC33FJ64GPX02/X04, and nonvolatile memory implementation for device dsPIC33FJ128GPX02/X04 families of configuration bits. Refer to Section 25. “Device Con- devices. It is not intended to be a compre- figuration” (DS70194), in the “dsPIC33F/PIC24H hensive reference source. To comple- Family Reference Manual” for more information on this ment the information in this data sheet, implementation. refer to the “dsPIC33F/PIC24H Family The Configuration bits can be programmed (read as Reference Manual”. Please see the ‘0’), or left unprogrammed (read as ‘1’), to select vari- Microchip web site (www.microchip.com) ous device configurations. These bits are mapped for the latest dsPIC33F/PIC24H Family starting at program memory location 0xF80000. Reference Manual sections. The individual Configuration bit descriptions for the 2: Some registers and associated bits Configuration registers are shown in Table27-2. described in this section may not be avail- Note that address 0xF80000 is beyond the user program able on all devices. Refer to Section4.0 memory space. It belongs to the configuration memory “Memory Organization” in this data space (0x800000-0xFFFFFF), which can only be sheet for device-specific register and bit accessed using table reads and table writes. information. The Device Configuration register map is shown in dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, Table27-1. and dsPIC33FJ128GPX02/X04 devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • Flexible configuration • Watchdog Timer (WDT) • Code Protection and CodeGuard™ Security • JTAG Boundary Scan Interface • In-Circuit Serial Programming™ (ICSP™) • In-Circuit emulation TABLE 27-1: DEVICE CONFIGURATION REGISTER MAP Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0xF80000 FBS RBS<1:0> — — BSS<2:0> BWRP 0xF80002 FSS(1) RSS<1:0> — — SSS<2:0> SWRP 0xF80004 FGS — — — — — GSS<1:0> GWRP 0xF80006 FOSCSEL IESO — — — FNOSC<2:0> 0xF80008 FOSC FCKSM<1:0> IOL1WAY — — OSCIOFNC POSCMD<1:0> 0xF8000A FWDT FWDTEN WINDIS — WDTPRE WDTPOST<3:0> 0xF8000C FPOR Reserved(2) ALTI2C — FPWRT<2:0> 0xF8000E FICD Reserved(3) JTAGEN — — — ICS<1:0> 0xF80010 FUID0 User Unit ID Byte 0 0xF80012 FUID1 User Unit ID Byte 1 0xF80014 FUID2 User Unit ID Byte 2 0xF80016 FUID3 User Unit ID Byte 3 Legend: — = unimplemented bit, read as ‘0’. Note 1: This Configuration register is not available and reads as 0xFF on dsPIC33FJ32GP302/304 devices. 2: These bits are reserved and always read as ‘1’. 3: These bits are reserved for use by development tools and must be programmed as ‘1’. © 2007-2012 Microchip Technology Inc. DS70292G-page 315

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 27-2: dsPIC CONFIGURATION BITS DESCRIPTION Bit Field Register RTSP Effect Description BWRP FBS Immediate Boot Segment Program Flash Write Protection 1 = Boot segment can be written 0 = Boot segment is write-protected BSS<2:0> FBS Immediate Boot Segment Program Flash Code Protection Size X11 = No Boot program Flash segment Boot space is 1K Instruction Words (except interrupt vectors) 110 = Standard security; boot program Flash segment ends at 0x0007FE 010 = High security; boot program Flash segment ends at 0x0007FE Boot space is 4K Instruction Words (except interrupt vectors) 101 = Standard security; boot program Flash segment, ends at 0x001FFE 001 = High security; boot program Flash segment ends at 0x001FFE Boot space is 8K Instruction Words (except interrupt vectors) 100 = Standard security; boot program Flash segment ends at 0x003FFE 000 = High security; boot program Flash segment ends at 0x003FFE RBS<1:0>(1) FBS Immediate Boot Segment RAM Code Protection Size 11 = No Boot RAM defined 10 = Boot RAM is 128 bytes 01 = Boot RAM is 256 bytes 00 = Boot RAM is 1024 bytes SWRP(1) FSS(1) Immediate Secure Segment Program Flash Write-Protect bit 1 = Secure Segment can bet written 0 = Secure Segment is write-protected SSS<2:0>(1) FSS(1) Immediate Secure Segment Program Flash Code Protection Size (Secure segment is not implemented on 32K devices) X11 = No Secure program flash segment Secure space is 4K IW less BS 110 = Standard security; secure program flash segment starts at End of BS, ends at 0x001FFE 010 = High security; secure program flash segment starts at End of BS, ends at 0x001FFE Secure space is 8K IW less BS 101 = Standard security; secure program flash segment starts at End of BS, ends at 0x003FFE 001 = High security; secure program flash segment starts at End of BS, ends at 0x003FFE Secure space is 16K IW less BS 100 = Standard security; secure program flash segment starts at End of BS, ends at 007FFEh 000 = High security; secure program flash segment starts at End of BS, ends at 0x007FFE Note1: This Configuration register is not available on dsPIC33FJ32GP302/304 devices. DS70292G-page 316 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 27-2: dsPIC CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register RTSP Effect Description RSS<1:0>(1) FSS(1) Immediate Secure Segment RAM Code Protection 11 = No Secure RAM defined 10 = Secure RAM is 256 Bytes less BS RAM 01 = Secure RAM is 2048 Bytes less BS RAM 00 = Secure RAM is 4096 Bytes less BS RAM GSS<1:0> FGS Immediate General Segment Code-Protect bit 11 = User program memory is not code-protected 10 = Standard security 0x = High security GWRP FGS Immediate General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected IESO FOSCSEL Immediate Two-speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start-up device with user-selected oscillator source FNOSC<2:0> FOSCSEL If clock switch Initial Oscillator Source Selection bits is enabled, 111 = Internal Fast RC (FRC) oscillator with postscaler RTSP effect is 110 = Internal Fast RC (FRC) oscillator with divide-by-16 on any device 101 = LPRC oscillator Reset; 100 = Secondary (LP) oscillator otherwise, 011 = Primary (XT, HS, EC) oscillator with PLL Immediate 010 = Primary (XT, HS, EC) oscillator 001 = Internal Fast RC (FRC) oscillator with PLL 000 = FRC oscillator FCKSM<1:0> FOSC Immediate Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled IOL1WAY FOSC Immediate Peripheral pin select configuration 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations OSCIOFNC FOSC Immediate OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin POSCMD<1:0> FOSC Immediate Primary Oscillator Mode Select bits 11 = Primary oscillator disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode FWDTEN FWDT Immediate Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register has no effect.) 0 = Watchdog Timer enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) WINDIS FWDT Immediate Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode Note1: This Configuration register is not available on dsPIC33FJ32GP302/304 devices. © 2007-2012 Microchip Technology Inc. DS70292G-page 317

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 27-2: dsPIC CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register RTSP Effect Description WDTPRE FWDT Immediate Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 WDTPOST<3:0> FWDT Immediate Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 FPWRT<2:0> FPOR Immediate Power-on Reset Timer Value Select bits 111 = PWRT = 128 ms 110 = PWRT = 64 ms 101 = PWRT = 32 ms 100 = PWRT = 16 ms 011 = PWRT = 8 ms 010 = PWRT = 4 ms 001 = PWRT = 2 ms 000 = PWRT = Disabled ALTI2C FPOR Immediate Alternate I2C™ pins 1 = I2C mapped to SDA1/SCL1 pins 0 = I2C mapped to ASDA1/ASCL1 pins JTAGEN FICD Immediate JTAG Enable bit 1 = JTAG enabled 0 = JTAG disabled ICS<1:0> FICD Immediate ICD Communication Channel Select bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use Note1: This Configuration register is not available on dsPIC33FJ32GP302/304 devices. DS70292G-page 318 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 27.2 On-Chip Voltage Regulator 27.3 BOR: Brown-out Reset All of the dsPIC33FJ32GP302/304, The Brown-out Reset (BOR) module is based on an dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ internal voltage reference circuit that monitors the reg- X04 devices power their core digital logic at a nominal ulated supply voltage VCAP. The main purpose of the 2.5V. This can create a conflict for designs that are BOR module is to generate a device Reset when a required to operate at a higher typical voltage, such as brown-out condition occurs. Brown-out conditions are 3.3V. To simplify system design, all devices in the generally caused by glitches on the AC mains (for dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, example, missing portions of the AC cycle waveform and dsPIC33FJ128GPX02/X04 family incorporate an due to bad power transmission lines, or voltage sags on-chip regulator that allows the device to run its core due to excessive current draw when a large inductive logic from VDD. load is turned on). The regulator provides power to the core from the other A BOR generates a Reset pulse, which resets the VDD pins. When the regulator is enabled, a low-ESR device. The BOR selects the clock source, based on (less than 5 Ohms) capacitor (such as tantalum or the device Configuration bit values (FNOSC<2:0> and ceramic) must be connected to the VCAP pin POSCMD<1:0>). (Figure27-1). This helps to maintain the stability of the If an oscillator mode is selected, the BOR activates the regulator. The recommended value for the filter capac- Oscillator Start-up Timer (OST). The system clock is itor is provided in Table30-13 located in Section30.1 held until OST expires. If the PLL is used, the clock is “DC Characteristics”. held until the LOCK bit (OSCCON<5>) is ‘1’. Note: It is important for the low-ESR capacitor to Concurrently, the PWRT time-out (TPWRT) is applied be placed as close as possible to the VCAP before the internal Reset is released. If TPWRT = 0 and pin. a crystal oscillator is being used, then a nominal delay On a POR, it takes approximately 20μs for the on-chip of TFSCM = 100 is applied. The total delay in this case is TFSCM. voltage regulator to generate an output voltage. During this time, designated as TSTARTUP, code execution is The BOR Status bit (RCON<1>) is set to indicate that a disabled. TSTARTUP is applied every time the device BOR has occurred. The BOR circuit continues to oper- resumes operation after any power-down. ate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold voltage. FIGURE 27-1: CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1,2,3) 3.3V dsPIC33F VDD VCAP CEFC 10 µF VSS Tantalum Note 1: These are typical operating voltages. Refer to Table30-13, located in Section30.1 “DC Characteristics” for the full operating ranges of VDD and VCAP. 2: It is important for the low-ESR capacitor to be placed as close as possible to the VCAP pin. 3: Typical VCAP pin voltage = 2.5V when VDD ≥ VDDMIN. © 2007-2012 Microchip Technology Inc. DS70292G-page 319

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 27.4 Watchdog Timer (WDT) 27.4.2 SLEEP AND IDLE MODES For dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ If the WDT is enabled, it continues to run during Sleep or X04, and dsPIC33FJ128GPX02/X04 devices, the WDT Idle modes. When the WDT time-out occurs, the device is driven by the LPRC oscillator. When the WDT is wakes the device and code execution continues from enabled, the clock source is also enabled. where the PWRSAV instruction was executed. The corre- sponding SLEEP or IDLE bits (RCON<3,2>) needs to be 27.4.1 PRESCALER/POSTSCALER cleared in software after the device wakes up. The nominal WDT clock source from LPRC is 32kHz. 27.4.3 ENABLING WDT This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The WDT is enabled or disabled by the FWDTEN The prescaler is set by the WDTPRE Configuration bit. Configuration bit in the FWDT Configuration register. With a 32kHz input, the prescaler yields a nominal When the FWDTEN Configuration bit is set, the WDT is WDT time-out period (TWDT) of 1ms in 5-bit mode, or always enabled. 4ms in 7-bit mode. The WDT can be optionally controlled in software A variable postscaler divides down the WDT prescaler when the FWDTEN Configuration bit has been output and allows for a wide range of time-out periods. programmed to ‘0’. The WDT is enabled in software The postscaler is controlled by the WDTPOST<3:0> by setting the SWDTEN control bit (RCON<5>). The Configuration bits (FWDT<3:0>), which allow the selec- SWDTEN control bit is cleared on any device Reset. tion of 16 settings, from 1:1 to 1:32,768. Using the pres- The software WDT option allows the user application caler and postscaler, time-out periods ranging from to enable the WDT for critical code segments and 1ms to 131 seconds can be achieved. disable the WDT during non-critical segments for maximum power savings. The WDT, prescaler and postscaler are reset: Note: If the WINDIS bit (FWDT<6>) is cleared, the • On any form of device Reset CLRWDT instruction should be executed by • On the completion of a clock switch, whether the application software only during the last invoked by software (i.e., setting the OSWEN bit 1/4 of the WDT period. This CLRWDT win- after changing the NOSC bits) or by hardware dow can be determined by using a timer. If (i.e., Fail-Safe Clock Monitor) a CLRWDT instruction is executed before • When a PWRSAV instruction is executed this window, a WDT Reset occurs. (i.e., Sleep or Idle mode is entered) The WDT flag, WDTO bit (RCON<4>), is not automatically • When the device exits Sleep or Idle mode to cleared following a WDT time-out. To detect subsequent resume normal operation WDT events, the flag must be cleared in software. • By a CLRWDT instruction during normal execution Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. FIGURE 27-2: WDT BLOCK DIAGRAM All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle WDTPRE WDTPOST<3:0> SWDTEN WDT FWDTEN Wake-up RS RS 1 Prescaler Postscaler LPRC Clock (divide by N1) (divide by N2) WDT Reset 0 WINDIS WDT Window Select CLRWDT Instruction DS70292G-page 320 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 27.5 JTAG Interface 27.8 Code Protection and CodeGuard™ Security dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices implement a The dsPIC33FJ64GPX02/X04 and JTAG interface, which supports boundary scan device dsPIC33FJ128GPX02/X04 devices offer advanced testing, as well as in-circuit programming. Detailed implementation of CodeGuard Security that supports information on this interface is provided in future BS, SS and GS while, the dsPIC33FJ32GP302/304 revisions of the document. devices offer the intermediate level of CodeGuard Security that supports only BS and GS. CodeGuard Note: Refer to Section 24. “Programming and Security enables multiple parties to securely share Diagnostics” (DS70207) of the resources (memory, interrupts and peripherals) on a “dsPIC33F/PIC24H Family Reference single chip. This feature helps protect individual Manual” for further information on usage, Intellectual Property in collaborative system designs. configuration and operation of the JTAG interface. When coupled with software encryption libraries, CodeGuard Security can be used to securely update 27.6 In-Circuit Serial Programming™ Flash even when multiple IPs reside on the single chip. The code protection features vary depending on the (ICSP)™ actual dsPIC33F implemented. The following sections The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ provide an overview of these features. X04, and dsPIC33FJ128GPX02/X04 devices can be Secure segment and RAM protection is implemented serially programmed while in the end application circuit. on the dsPIC33FJ64GPX02/X04 and This is done with two lines for clock and data and three dsPIC33FJ128GPX02/X04 devices. The other lines for power, ground and the programming dsPIC33FJ32GP302/304 devices do not support sequence. Serial programming allows customers to secure segment and RAM protection. manufacture boards with unprogrammed devices and Note: Refer to Section 23. “CodeGuard™ then program the digital signal controller just before Security” (DS70199) of the “dsPIC33F/ shipping the product. Serial programming also allows PIC24H Family Reference Manual” for the most recent firmware or a custom firmware to be further information on usage, programmed. Refer to the “dsPIC33F/PIC24H Flash configuration and operation of CodeGuard Programming Specification” (DS70152) for details about In-Circuit Serial Programming (ICSP). Security. Any of the three pairs of programming clock/data pins can be used: • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 27.7 In-Circuit Debugger When MPLAB® ICD 3 is selected as a debugger, the in- circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pin functions. Any of the three pairs of debugging clock/data pins can be used: • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS, PGC, PGD and the PGECx and PGEDx pin pairs. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. © 2007-2012 Microchip Technology Inc. DS70292G-page 321

D TABLE 27-3: CODE FLASH SECURITY SEGMENT SIZES FOR 32 KB DEVICES d S s 70 CONFIG BITS BSS<2:0> = x11 0K BSS<2:0> = x10 1K BSS<2:0> = x01 4K BSS<2:0> = x00 8K P 29 IC 2G VS = 256 IW 0x000000h VS = 256 IW 0x000000h VS = 256 IW 0x000000h VS = 256 IW 0x000000h 3 -p 0x0001FEh 0x0001FEh 0x0001FEh 0x0001FEh 3 age 00xx000000270F0Ehh BS = 768 IW 00xx000000270F0Ehh BS = 3840 IW 00xx00000072F00Ehh BS = 7936 IW 00xx000000270F0Ehh FJ 3 0x000800h 0x000800h 0x000800h 0x000800h 3 22 SSS<2:0> = x11 00xx000012F00F0Ehh 00xx0000210F0F0Ehh 00xx0000210F0F0Ehh 00xx0000210F0F0Ehh 2G 0x003FFEh 0x003FFEh 0x003FFEh 0x003FFEh P 0K GS = 11008 IW 0x004000h GS = 10240 IW 0x004000h GS = 7168 IW 0x004000h GS = 3072 IW 0x004000h 3 0x0057FEh 0x0057FEh 0x0057FEh 0x0057FEh 0 2 / 3 0 0x0157FEh 0x0157FEh 0x0157FEh 0x0157FEh 4 , d s P I C 3 3 F J 6 4 G P X 0 2 / X 0 4 , A N D d © s 2 P 00 IC 7-20 33 1 F 2 M J1 ic 2 ro 8 ch G ip T P e X ch 0 n 2 olo /X gy 0 In 4 c .

© TABLE 27-4: CODE FLASH SECURITY SEGMENT SIZES FOR 64 KB DEVICES 2 d 00 CONFIG BITS BSS<2:0> = x11 0K BSS<2:0> = x10 1K BSS<2:0> = x01 4K BSS<2:0> = x00 8K s 7 P -201 VS = 256 IW 00xx00000010F00Ehh VS = 256 IW 00xx00000010F00Ehh VS = 256 IW 00xx00000010F00Ehh VS = 256 IW 00xx00000010F00Ehh IC 2 M 00xx00000072F00Ehh BS = 768 IW 00xx00000072F00Ehh BS = 3840 IW 00xx00000072F00Ehh BS = 7936 IW 00xx00000072F00Ehh 33 ic 0x000800h 0x000800h 0x000800h 0x000800h F ro 0x001FFEh 0x001FFEh 0x001FFEh 0x001FFEh J chip SSS<2:0> = x11 00xx0000230F0F0Ehh 00xx0000230F0F0Ehh 00xx0000230F0F0Ehh 00xx0000230F0F0Ehh 32 Te 0K 00xx0000470F0F0Ehh 00xx000074F00F0Ehh 00xx0000470F0F0Ehh 00xx0000470F0F0Ehh GP chno GS = 21760 IW 00xx0000A80B0F0Ehh GS = 20992 IW 00xx00008A0B0F0Ehh GS = 17920 IW 00xx0000A80B0F0Ehh GS = 13824 IW 00xx0000A80B0F0Ehh 30 lo 2 g / y In 0x0157FEh 0x0157FEh 0x0157FEh 0x0157FEh 30 c 4 . VS = 256 IW 00xx000000010F0Ehh VS = 256 IW 00xx00000010F00Ehh VS = 256 IW 00xx00000010F00Ehh VS = 256 IW 00xx00000010F00Ehh , d 00xx00000072F00Ehh BS = 768 IW 00xx00000072F00Ehh BS = 3840 IW 00xx00000072F00Ehh BS = 7936 IW 00xx00000072F00Ehh sP SSS<2:0> = x10 SS = 3840 IW 000xxx0000000128F000F00Ehhh SS = 3072 IW 000xxx0000000128F000F00Ehhh 000xxx0000000128F000F00Ehhh 000xxx0000000128F000F00Ehhh IC3 0x003FFEh 0x003FFEh 0x003FFEh 0x003FFEh 3 4K 00xx000074F0F00Ehh 00xx0000470F0F0Ehh 00xx0000470F0F0Ehh 00xx0000470F0F0Ehh F J GS = 17920 IW 0x008000h GS = 17920 IW 0x008000h GS = 17920 IW 0x008000h GS = 13824 IW 0x008000h 6 0x00ABFEh 0x00ABFEh 0x00ABFEh 0x00ABFEh 4 G 0x0157FEh 0x0157FEh 0x0157FEh 0x0157FEh P X 0x000000h 0x000000h 0x000000h 0x000000h 0 VS = 256 IW 0x0001FEh VS = 256 IW 0x0001FEh VS = 256 IW 0x0001FEh VS = 256 IW 0x0001FEh 2 0000xxxx00000000001028F700FF00EEhhhh BS = 768 IW 0000xxxx000000000001728FF00F00EEhhhh BS = 3840 IW 0000xxxx000000000001728FF00F00EEhhhh BS = 7936 IW 0000xxxx000000000001728FF00F00EEhhhh /X04 SSS<2:0> = x01 0x002000h 0x002000h 0x002000h 0x002000h , SS = 7936 IW 0x003FFEh SS = 7168 IW 0x003FFEh SS = 4096 IW 0x003FFEh 0x003FFEh A 0x004000h 0x004000h 0x004000h 0x004000h N 8K 0x007FFEh 0x007FFEh 0x007FFEh 0x007FFEh D GS = 13824 IW 0x008000h GS = 13824 IW 0x008000h GS = 13824 IW 0x008000h GS = 13824 IW 0x008000h 0x00ABFEh 0x00ABFEh 0x00ABFEh 0x00ABFEh d s P 0x0157FEh 0x0157FEh 0x0157FEh 0x0157FEh I C 0x000000h 0x000000h 0x000000h 0x000000h 3 VS = 256 IW 0x0001FEh VS = 256 IW 0x0001FEh VS = 256 IW 0x0001FEh VS = 256 IW 0x0001FEh 3 0x000200h 0x000200h 0x000200h 0x000200h F 0x0007FEh BS = 768 IW 0x0007FEh BS = 3840 IW 0x0007FEh BS = 7936 IW 0x0007FEh J 0x000800h 0x000800h 0x000800h 0x000800h 1 D 0x001FFEh 0x001FFEh 0x001FFEh 0x001FFEh 2 S70 SSS<2:0> = x00 00xx0000230F0F0Ehh 00xx0000230F0F0Ehh 00xx0000230F0F0Ehh 00xx0000230F0F0Ehh 8G 292 16K SS = 16128 IW 00xx0000470F0F0Ehh SS = 15360 IW 00xx0000470F0F0Ehh SS = 12288 IW 00xx0000470F0F0Ehh SS = 8192 IW 00xx0000470F0F0Ehh PX G 0x008000h 0x008000h 0x008000h 0x008000h -pa GS = 5632 IW 0x00ABFEh GS = 5632 IW 0x00ABFEh GS = 5632 IW 0x00ABFEh GS = 5632 IW 0x00ABFEh 02 g / e X 3 0x0157FEh 0x0157FEh 0x0157FEh 0x0157FEh 0 23 4

D TABLE 27-5: CODE FLASH SECURITY SEGMENT SIZES FOR 128 KB DEVICES d S s 70 CONFIG BITS BSS<2:0> = x11 0K BSS<2:0> = x10 1K BSS<2:0> = x01 4K BSS<2:0> = x00 8K P 29 IC 2G-pag VS = 256 IW 0000xxxx00000000000001720FF000EEhhhh VBSS == 275668 IIWW 0000xxxx000000000000207100FF00EEhhhh BVSS == 3285460 I IWW 0000xxxx0000000000001702FF000EE0hhhh BVSS == 7295366 I IWW 0000xxxx00000000000001720FF00EE0hhhh 33F e 324 SSS<2:0> = x11 0000xxxx0000000023100FF800FF00EEhhhh 0000xxxx000000003120FF080FF000EEhhhh 0000xxxx000000003201F08F00FF00EEhhhh 0000xxxx000000001320FF8000FF00EEhhhh J32G 0x004000h 0x004000h 0x004000h 0x004000h P 0K 0x007FFEh 0x007FFEh 0x007FFEh 0x007FFEh 3 0x008000h 0x008000h 0x008000h 0x008000h 0 0x00FFFEh 0x00FFFEh 0x00FFFEh 0x00FFFEh 2 GS = 43776 IW 0x010000h GS = 43008 IW 0x010000h GS = 39936 IW 0x010000h GS = 35840 IW 0x010000h /3 0 0x0157FEh 0x0157FEh 0x0157FEh 0x0157FEh 4 , VS = 256 IW 00xx000000010F0Ehh VS = 256 IW 00xx000000010F0Ehh VS = 256 IW 00xx000000010F0Ehh VS = 256 IW 00xx000000010F0Ehh ds 00xx00000072F00Ehh BS = 768 IW 00xx00000072F00Ehh BS = 3840 IW 00xx000000270F0Ehh BS = 7936 IW 00xx000000270F0Ehh PI SS = 3840 IW 0x000800h SS = 3072 IW 0x000800h 0x000800h 0x000800h C SSS<2:0> = x10 00xx000012F00F0Ehh 00xx0000210F0F0Ehh 00xx000012F00F0Ehh 00xx0000210F0F0Ehh 33 0x003FFEh 0x003FFEh 0x003FFEh 0x003FFEh F 4K 00xx000074F00F0Ehh 00xx000074F00F0Ehh 00xx0000470F0F0Ehh 00xx000074F00F0Ehh J6 0x008000h 0x008000h 0x008000h 0x008000h 4 0x00ABFEh 0x00ABFEh 0x00ABFEh 0x00ABFEh G GS = 39936 IW GS = 39936 IW GS = 39936 IW GS = 35840 IW P 0x0157FEh 0x0157FEh 0x0157FEh 0x0157FEh X 0 0x000000h 0x000000h 0x000000h 0x000000h 2 VS = 256 IW 0x0001FEh VS = 256 IW 0x0001FEh VS = 256 IW 0x0001FEh VS = 256 IW 0x0001FEh /X 00xx00000072F0E0hh BS = 768 IW 00xx000000270F0Ehh BS = 3840 IW 00xx000000270F0Ehh BS = 7936 IW 00xx00000072F00Ehh 04 0x000800h 0x000800h 0x000800h 0x000800h , SSS<2:0> = x01 00xx0000210F0F0Ehh 00xx0000210F0F0Ehh 00xx0000210F0F0Ehh 00xx000012F00F0Ehh A SS = 7936 IW 0x003FFEh SS = 7168 IW 0x003FFEh SS = 4096 IW 0x003FFEh 0x003FFEh N 0x004000h 0x004000h 0x004000h 0x004000h D 8K 0x007FFEh 0x007FFEh 0x007FFEh 0x007FFEh 0x008000h 0x008000h 0x008000h 0x008000h d © 0x00FFFEh 0x00FFFEh 0x00FFFEh 0x00FFFEh s 2 GS = 35840 IW 0x010000h GS = 35840 IW 0x010000h GS = 35840 IW 0x010000h GS = 35840 IW 0x010000h P 007-20 00xx00105070F0E0hh 00xx00105070F0E0hh 00xx00105070F0E0hh 00xx000105070F0Ehh IC33 12 Microchip Techn SSS<21:60K> = x00 SVSS = = 1 2651268 I WIW 0000000000xxxxxxxxxx000000000000000000007318420000FFF0008217000FFF00FF000EEE00EEhhhhhhhhhh SVBSSS = == 1 2575366680 II WWIW 0000000000xxxxxxxxxx000000000000000000007310084002FFF7100280FFFFF00000EEE0E0000Ehhhhhhhhhh SBVSSS = == 1 32285248608 I IWIWW 0000000000xxxxxxxxxx00000000000000000000241730080000FFF2807100000FFFFF00000EEEEEhhhhhhhhhh BSVSSS === 78291539662 I IIWWW 0000000000xxxxxxxxxx000000000000000000007384000021FF0017280F00FFFF000F00000EEEEEhhhhhhhhhh FJ128GPX02 ology GS = 27648 IW 00xx0001F00F0F0Ehh GS = 27648 IW 00xx0001F00F0F0Ehh GS = 27648 IW 00xx0001F00F0F0Ehh GS = 27648 IW 00xx0001F00F0F0Ehh /X0 In 0x0157FEh 0x0157FEh 0x0157FEh 0x0157FEh 4 c .

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 28.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: Note: This data sheet summarizes the features • The W register (with or without an address of the dsPIC33FJ32GP302/304, modifier) or file register (specified by the value of dsPIC33FJ64GPX02/X04, and ‘Ws’ or ‘f’) dsPIC33FJ128GPX02/X04 families of • The bit in the W register or file register (specified devices. It is not intended to be a compre- by a literal value or indirectly by the contents of hensive reference source. To complement register ‘Wb’) the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference The literal instructions that involve data movement can Manual”. Please see the Microchip web use some of the following operands: site (www.microchip.com) for the latest • A literal value to be loaded into a W register or file reference manual sections. register (specified by ‘k’) The dsPIC33F instruction set is identical to that of the • The W register or file register where the literal dsPIC30F. value is to be loaded (specified by ‘Wb’ or ‘f’) Most instructions are a single program memory word However, literal instructions that involve arithmetic or (24 bits). Only three instructions require two program logical operations use some of the following operands: memory locations. • The first source operand, which is a register ‘Wb’ Each single-word instruction is a 24-bit word, divided without any address modifier into an 8-bit opcode, which specifies the instruction • The second source operand, which is a literal type and one or more operands, which further specify value the operation of the instruction. • The destination of the result (only if not the same The instruction set is highly orthogonal and is grouped as the first source operand), which is typically a into five basic categories: register ‘Wd’ with or without an address modifier • Word or byte-oriented operations The MAC class of DSP instructions can use some of the following operands: • Bit-oriented operations • Literal operations • The accumulator (A or B) to be used (required operand) • DSP operations • The W registers to be used as the two operands • Control operations • The X and Y address space prefetch operations Table28-1 shows the general symbols used in • The X and Y address space prefetch destinations describing the instructions. • The accumulator write back destination The dsPIC33F instruction set summary in Table28-2 lists all the instructions, along with the status flags The other DSP instructions do not involve any affected by each instruction. multiplication and can include: Most word or byte-oriented W register instructions • The accumulator to be used (required) (including barrel shift instructions) have three • The source or destination operand (designated as operands: Wso or Wdo, respectively) with or without an address modifier • The first source operand, which is typically a register ‘Wb’ without any address modifier • The amount of shift specified by a W register ‘Wn’ or a literal value • The second source operand, which is typically a register ‘Ws’ with or without an address modifier The control instructions can use some of the following • The destination of the result, which is typically a operands: register ‘Wd’ with or without an address modifier • A program memory address However, word or byte-oriented file register instructions • The mode of the table read and table write have two operands: instructions • The file register specified by the value ‘f’ • The destination, which could be either the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2007-2012 Microchip Technology Inc. DS70292G-page 325

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Most instructions are a single word. Certain double- (unconditional/computed branch), indirect CALL/GOTO, word instructions are designed to provide all the all table reads and writes and RETURN/RETFIE instruc- required information in these 48 bits. In the second tions, which are single-word instructions but take two or word, the 8MSbs are ‘0’s. If this second word is three cycles. Certain instructions that involve skipping executed as an instruction (by itself), it executes as a over the subsequent instruction require either two or NOP. three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or The double-word instructions execute in two instruction two-word instruction. Moreover, double-word moves cycles. require two cycles. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the Note: For more details on the instruction set, program counter is changed as a result of the refer to the “16-bit MCU and DSC instruction. In these cases, the execution takes two Programmer’s Reference Manual” instruction cycles with the additional instruction cycle(s) (DS70157). executed as a NOP. Notable exceptions are the BRA TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator write back destination address register ∈ {W13, [W13]+ = 2} bit4 4-bitbit selection field (used in word addressed instructions) ∈ {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address ∈ {0x0000...0x1FFF} lit1 1-bit unsigned literal ∈ {0,1} lit4 4-bit unsigned literal ∈ {0...15} lit5 5-bit unsigned literal ∈ {0...31} lit8 8-bit unsigned literal ∈ {0...255} lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal ∈ {0...16384} lit16 16-bit unsigned literal ∈ {0...65535} lit23 23-bit unsigned literal ∈ {0...8388608}; LSb must be ‘0’ None Field does not require an entry, can be blank OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate PC Program Counter Slit10 10-bit signed literal ∈ {-512...511} Slit16 16-bit signed literal ∈ {-32768...32767} Slit6 6-bit signed literal ∈ {-16...16} Wb Base W register ∈ {W0...W15} Wd Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register ∈ { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing) DS70292G-page 326 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈ {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈ {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 working registers ∈ {W0...W15} Wnd One of 16 destination working registers ∈ {W0...W15} Wns One of 16 source working registers ∈ {W0...W15} WREG W0 (working register used in file register instructions) Ws Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register ∈ { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wx X data space prefetch address register for DSP instructions ∈ {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none} Wxd X data space prefetch destination register for DSP instructions ∈ {W4...W7} Wy Y data space prefetch address register for DSP instructions ∈ {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Wyd Y data space prefetch destination register for DSP instructions ∈ {W4...W7} © 2007-2012 Microchip Technology Inc. DS70292G-page 327

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: INSTRUCTION SET OVERVIEW Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB 2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z 3 AND AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z 4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z 5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None 6 BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if greater than or equal 1 1 (2) None BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None BRA GT,Expr Branch if greater than 1 1 (2) None BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None BRA LE,Expr Branch if less than or equal 1 1 (2) None BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None BRA LT,Expr Branch if less than 1 1 (2) None BRA LTU,Expr Branch if unsigned less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OA,Expr Branch if Accumulator A overflow 1 1 (2) None BRA OB,Expr Branch if Accumulator B overflow 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA SA,Expr Branch if Accumulator A saturated 1 1 (2) None BRA SB,Expr Branch if Accumulator B saturated 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None 7 BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None 8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None 9 BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None DS70292G-page 328 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3) 11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) 12 BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z 13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z 14 CALL CALL lit23 Call subroutine 2 2 None CALL Wn Call indirect subroutine 1 2 None 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB 16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep 17 COM COM f f = f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z 18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z 19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z 20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z (Wb – Ws – C) 21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1 None (2 or 3) 22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1 None (2 or 3) 23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1 None (2 or 3) 24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if ≠ 1 1 None (2 or 3) 25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C 26 DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z 27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z 28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None © 2007-2012 Microchip Technology Inc. DS70292G-page 329

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV 30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV 31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 None DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indirect 1 2 None 39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z 41 IOR IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 43 LNK LNK #lit14 Link Frame Pointer 1 1 None 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z 45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply and Accumulate 1 1 OA,OB,OAB, , SA,SB,SAB AWB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB 46 MOV MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 None MOV f,WREG Move f to WREG 1 1 N,Z MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 None MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None 47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store accumulator 1 1 None DS70292G-page 330 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 48 MPY MPY Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, Wm*Wn,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB MPY Square Wm to Accumulator 1 1 OA,OB,OAB, Wm*Wm,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB 49 MPY.N MPY.N -(Multiply Wm by Wn) to Accumulator 1 1 None Wm*Wn,Acc,Wx,Wxd,Wy,Wyd 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, , SA,SB,SAB AWB 51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(Ws) MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(lit5) MUL f W3:W2 = f * WREG 1 1 None 52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f = f + 1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 53 NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None 54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None W(nd):W(nd + 1) POP.S Pop Shadow Registers 1 1 All 55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None 56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep 57 RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None 58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None 59 RESET RESET Software device Reset 1 1 None 60 RETFIE RETFIE Return from interrupt 1 3 (2) None 61 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None 62 RETURN RETURN Return from Subroutine 1 3 (2) None 63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z 64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z 65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z © 2007-2012 Microchip Technology Inc. DS70292G-page 331

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None 68 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z 69 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None 70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB 71 SL SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z 72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f – WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z 73 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z 74 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z 75 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z 76 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None SWAP Wn Wn = byte swap Wn 1 1 None 77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None 78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None 79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 81 ULNK ULNK Unlink Frame Pointer 1 1 None 82 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z 83 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N DS70292G-page 332 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 29.0 DEVELOPMENT SUPPORT 29.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2007-2012 Microchip Technology Inc. DS70292G-page 333

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 29.2 MPLAB C Compilers for Various 29.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 29.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 29.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 29.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS70292G-page 334 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 29.7 MPLAB SIM Software Simulator 29.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 29.10 PICkit 3 In-Circuit Debugger/ Programmer and 29.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and MPLAB REAL ICE In-Circuit Emulator System is programming of PIC® and dsPIC® Flash Microchip’s next generation high-speed emulator for microcontrollers at a most affordable price point using Microchip Flash DSC and MCU devices. It debugs and the powerful graphical user interface of the MPLAB programs PIC® Flash MCUs and dsPIC® Flash DSCs Integrated Development Environment (IDE). The with the easy-to-use, powerful graphical user interface of MPLAB PICkit 3 is connected to the design engineer's the MPLAB Integrated Development Environment (IDE), PC using a full speed USB interface and can be included with each kit. connected to the target via an Microchip debug (RJ-11) The emulator is connected to the design engineer’s PC connector (compatible with MPLAB ICD 3 and MPLAB using a high-speed USB 2.0 interface and is connected REAL ICE). The connector uses two device I/O pins to the target with either a connector compatible with in- and the reset line to implement in-circuit debugging and circuit debugger systems (RJ11) or with the new high- In-Circuit Serial Programming™ (ICSP)™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2007-2012 Microchip Technology Inc. DS70292G-page 335

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 29.11 PICkit 2 Development 29.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use evaluation boards for various PIC MCUs and dsPIC interface for programming and debugging Microchip’s DSCs allows quick application development on fully func- Flash families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® The demonstration and development boards can be microcontrollers. In-Circuit-Debugging runs, halts and used in teaching environments, for prototyping custom single steps the program while the PIC microcontroller circuits and for learning about various microcontroller is embedded in the application. When halted at a applications. breakpoint, the file registers can be examined and In addition to the PICDEM™ and dsPICDEM™ demon- modified. stration/development board series of circuits, Microchip The PICkit 2 Debug Express include the PICkit 2, demo has a line of evaluation kits and demonstration software board and microcontroller, hookup cables and CDROM for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® with user’s guide, lessons, tutorial, compiler and evaluation system, Sigma-Delta ADC, flow rate MPLAB IDE software. sensing, plus many more. 29.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything needed to experience the specified device. This usually The MPLAB PM3 Device Programmer is a universal, includes a single application and debug capability, all CE compliant device programmer with programmable on one board. voltage verification at VDDMIN and VDDMAX for Check the Microchip web page (www.microchip.com) maximum reliability. It features a large LCD display for the complete list of demonstration, development (128 x 64) for menus and error messages and a modu- and evaluation kits. lar, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS70292G-page 336 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 30.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 electrical characteristics. Additional information is provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 family are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +160°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(4) ....................................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V(4) .................................................. -0.3V to +5.6V Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V(4)......................................................-0.3V to 3.6V Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin(2)...........................................................................................................................250 mA Maximum current sourced/sunk by any 2x I/O pin(3)................................................................................................8 mA Maximum current sourced/sunk by any 4x I/O pin(3)..............................................................................................15 mA Maximum current sourced/sunk by any 8x I/O pin(3)..............................................................................................25 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports(2)...............................................................................................................200 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods can affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table30-2). 3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGECx and PGEDx pins, which are able to sink/source 12 mA. 4: See the “Pin Diagrams” section for 5V tolerant pins. © 2007-2012 Microchip Technology Inc. DS70292G-page 337

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 30.1 DC Characteristics TABLE 30-1: OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic VDD Range Temp Range dsPIC33FJ32GP302/304, (in Volts) (in °C) dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 — 3.0-3.6V(1) -40°C to +85°C 40 — 3.0-3.6V(1) -40°C to +125°C 40 Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules such as the ADC will have degraded performance. Device functionality is tested but not characterized. Refer to parameter BO10 in Table30-11 for the minimum and maximum BOR values. TABLE 30-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Industrial Temperature Devices Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Extended Temperature Devices Operating Junction Temperature Range TJ -40 — +155 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD – Σ IOH) PD PINT + PI/O W I/O Pin Power Dissipation: I/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/θJA W TABLE 30-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Note θ Package Thermal Resistance, 44-pin QFN JA 30 — °C/W 1 θ Package Thermal Resistance, 44-pin TFQP JA 40 — °C/W 1 θ Package Thermal Resistance, 28-pin SPDIP JA 45 — °C/W 1 θ Package Thermal Resistance, 28-pin SOIC JA 50 — °C/W 1 θ Package Thermal Resistance, 28-pin QFN-S JA 30 — °C/W 1 θ Note 1: Junction to ambient thermal resistance, Theta-JA ( JA) numbers are achieved by package simulations. DS70292G-page 338 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Operating Voltage DC10 Supply Voltage VDD — 3.0 — 3.6 V Industrial and Extended DC12 VDR RAM Data Retention Voltage(2) 1.8 — — V — DC16 VPOR VDD Start Voltage — — VSS V — to ensure internal Power-on Reset signal DC17 SVDD VDD Rise Rate 0.03 — — V/ms 0-3.0V in 0.1s to ensure internal Power-on Reset signal Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: This is the limit to which VDD can be lowered without losing RAM data. © 2007-2012 Microchip Technology Inc. DS70292G-page 339

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Parameter Typical(2) Max Units Conditions No.(3) Operating Current (IDD)(1) DC20d 18 21 mA -40°C DC20a 18 22 mA +25°C 3.3V 10 MIPS DC20b 18 22 mA +85°C DC20c 18 25 mA +125°C DC21d 30 35 mA -40°C DC21a 30 34 mA +25°C 3.3V 16 MIPS DC21b 30 34 mA +85°C DC21c 30 36 mA +125°C DC22d 34 42 mA -40°C DC22a 34 41 mA +25°C 3.3V 20 MIPS DC22b 34 42 mA +85°C DC22c 35 44 mA +125°C DC23d 49 58 mA -40°C DC23a 49 57 mA +25°C 3.3V 30 MIPS DC23b 49 57 mA +85°C DC23c 49 60 mA +125°C DC24d 63 75 mA -40°C DC24a 63 74 mA +25°C 3.3V 40 MIPS DC24b 63 74 mA +85°C DC24c 63 76 mA +125°C Note 1: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode, no PLL until 10 MIPS, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (defined PMDx bits are set to zero) • CPU executing while(1) statement • JTAG is disabled 2: Data in “Typ” column is at 3.3V, +25ºC unless otherwise stated. 3: These parameters are characterized but not tested in manufacturing. DS70292G-page 340 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Parameter Typical(2) Max Units Conditions No.(3) Idle Current (IIDLE): Core OFF Clock ON Base Current(1) DC40d 8 10 mA -40°C DC40a 8 10 mA +25°C 10 MIPS DC40b 9 10 mA +85°C 3.3V DC40c 10 13 mA +125°C DC41d 13 15 mA -40°C DC41a 13 15 mA +25°C 3.3V 16 MIPS DC41b 13 16 mA +85°C DC41c 13 19 mA +125°C DC42d 15 18 mA -40°C DC42a 16 18 mA +25°C 3.3V 20 MIPS DC42b 16 19 mA +85°C DC42c 17 22 mA +125°C DC43a 23 27 mA +25°C DC43d 23 26 mA -40°C 3.3V 30 MIPS DC43b 24 28 mA +85°C DC43c 25 31 mA +125°C DC44d 31 42 mA -40°C DC44a 31 36 mA +25°C 3.3V 40 MIPS DC44b 32 39 mA +85°C DC44c 34 43 mA +125°C Note 1: Base IIDLE current is measured as follows: • CPU core is off (i.e., Idle mode), oscillator is configured in EC mode and external clock active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration word • External Secondary Oscillator disabled (i.e., SOSCO and SOSCI pins configured as digital I/O inputs) • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • No peripheral modules are operating; however, every peripheral is being clocked (defined PMDx bits are set to zero) • JTAG is disabled 2: Data in “Typ” column is at 3.3V, +25ºC unless otherwise stated. 3: These parameters are characterized but not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70292G-page 341

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Parameter Typical(2) Max Units Conditions No.(3) Power-Down Current (IPD)(1) DC60d 24 68 μA -40°C DC60a 28 87 μA +25°C 3.3V Base Power-Down Current(3,4) DC60b 124 292 μA +85°C DC60c 350 1000 μA +125°C DC61d 8 13 μA -40°C DC61a 10 15 μA +25°C 3.3V Watchdog Timer Current: ΔIWDT(3,5) DC61b 12 20 μA +85°C DC61c 13 25 μA +125°C Note 1: IPD (Sleep) current is measured as follows: • CPU core is off (i.e., Sleep mode), oscillator is configured in EC mode and external clock active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled, all peripheral modules are disabled (PMDx bits are all ‘1’s) • RTCC is disabled • JTAG is disabled 2: Data in the “Typ” column is at 3.3V, +25ºC unless otherwise stated. 3: The Watchdog Timer Current is the additional current consumed when the WDT module is enabled. This current should be added to the base IPD current. 4: These currents are measured on the device containing the most memory in this family. 5: These parameters are characterized, but are not tested in manufacturing. DS70292G-page 342 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Doze Parameter No. Typical(1) Max Units Conditions Ratio DC73a 20 50 1:2 mA DC73f 17 30 1:64 mA -40°C 3.3V 40 MIPS DC73g 17 30 1:128 mA DC70a 20 50 1:2 mA DC70f 17 30 1:64 mA +25°C 3.3V 40 MIPS DC70g 17 30 1:128 mA DC71a 20 50 1:2 mA DC71f 17 30 1:64 mA +85°C 3.3V 40 MIPS DC71g 17 30 1:128 mA DC72a 21 50 1:2 mA DC72f 18 30 1:64 mA +125°C 3.3V 40 MIPS DC72g 18 30 1:128 mA Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. © 2007-2012 Microchip Technology Inc. DS70292G-page 343

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VIL Input Low Voltage DI10 I/O pins VSS — 0.2VDD V DI11 PMP pins VSS — 0.15VDD V PMPTTL = 1 DI15 MCLR VSS — 0.2VDD V DI16 I/O Pins with OSC1 or SOSCI VSS — 0.2VDD V DI18 I/O Pins with SDAx, SCLx VSS — 0.3 VDD V SMBus disabled DI19 I/O Pins with SDAx, SCLx VSS — 0.8 VDD V SMBus enabled VIH Input High Voltage DI20 I/O Pins Not 5V Tolerant(4) 0.7VDD — VDD V I/O Pins 5V Tolerant(4) 0.7VDD — 5.5 V DI21 I/O Pins Not 5V Tolerant with 0.24 VDD + 0.8 — VDD V PMP(4) I/O Pins 5V Tolerant with 0.24 VDD + 0.8 — 5.5 V PMP(4) DI28 SDAx, SCLx 0.7 VDD — 5.5 V SMBus disabled DI29 SDAx, SCLx 2.1 — 5.5 V SMBus enabled ICNPU CNx Pull-up Current DI30 50 250 400 μA VDD = 3.3V, VPIN = VSS Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See the “Pin Diagrams” section for the 5V tolerant I/O pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro- vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. DS70292G-page 344 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. IIL Input Leakage Current(2,3) DI50 I/O pins 5V Tolerant(4) — — ±2 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance DI51 I/O Pins Not 5V Tolerant(4) — — ±1 μA VSS ≤ VPIN ≤ VDD, (Excluding AN9 through Pin at high-impedance, AN12) 40°C≤ TA ≤+85°C DI51a I/O Pins Not 5V Tolerant(4) — — ±2 μA Shared with external reference pins, 40°C≤ TA ≤ +85°C DI51b I/O Pins Not 5V Tolerant(4) — — ±3.5 μA VSS ≤ VPIN ≤ VDD, Pin at (Excluding AN9 through high-impedance, AN12) -40°C≤TA ≤+125°C DI51c I/O Pins Not 5V Tolerant(4) — — ±8 μA Analog pins shared with external reference pins, -40°C≤TA ≤+125°C DI51d AN9 through AN12 — — ±11 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance, -40°C≤TA ≤+85°C DI51e AN9 through AN12 — — ±13 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance, -40°C≤TA ≤+125°C DI55 MCLR — — ±2 μA VSS ≤ VPIN ≤ VDD DI56 OSC1 — — ±2 μA VSS ≤ VPIN ≤ VDD, XT and HS modes Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See the “Pin Diagrams” section for the 5V tolerant I/O pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro- vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. © 2007-2012 Microchip Technology Inc. DS70292G-page 345

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. IICL Input Low Injection Current DI60a 0 — -5(5,8) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO, and RB14 IICH Input High Injection Current DI60b 0 — +5(6,7,8) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO, RB14, and digital 5V-tol- erant designated pins ∑IICT Total Input Injection Current DI60c (sum of all I/O and control -20(9) — +20(9) mA Absolute instantaneous pins) sum of all ± input injection currents from all I/O pins (| IICL + | IICH |) ≤ ∑IICT Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See the “Pin Diagrams” section for the 5V tolerant I/O pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro- vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. DS70292G-page 346 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param. Symbol Characteristic Min. Typ. Max. Units Conditions Output Low Voltage I/O Pins: IOL ≤ 3 mA, VDD = 3.3V 2x Sink Driver Pins - RA2, RA7- — — 0.4 V See Note 1 RA10, RB10, RB11, RB7, RB4, RC3-RC9 Output Low Voltage DO10 VOL I/O Pins: IOL ≤ 6 mA, VDD = 3.3V 4x Sink Driver Pins - RA0, RA1, — — 0.4 V See Note 1 RB0-RB3, RB5, RB6, RB8, RB9, RB12-RB15, RC0-RC2 Output Low Voltage IOL ≤ 10 mA, VDD = 3.3V I/O Pins: — — 0.4 V See Note 1 8x Sink Driver Pins - RA3, RA4 Output High Voltage I/O Pins: IOH≥-3 mA, VDD = 3.3V 2x Source Driver Pins - RA2, 2.4 — — V See Note 1 RA7-RA10, RB4, RB7, RB10, RB11, RC3-RC9 Output High Voltage I/O Pins: DO20 VOH IOH≥-6 mA, VDD = 3.3V 4x Source Driver Pins - RA0, 2.4 — — V See Note 1 RA1, RB0-RB3, RB5, RB6, RB8, RB9, RB12-RB15, RC0-RC2 Output High Voltage I/O Pins: IOH≥-10 mA, VDD = 3.3V 2.4 — — V 8x Source Driver Pins - RA4, See Note 1 RA3 Output High Voltage IOH≥-6 mA, VDD = 3.3V 1.5 — — I/O Pins: See Note 1 2x Source Driver Pins - RA2, IOH≥-5 mA, VDD = 3.3V RA7-RA10, RB4, RB7, RB10, 2.0 — — V See Note 1 RB11, RC3-RC9 IOH≥-2 mA, VDD = 3.3V 3.0 — — See Note 1 Output High Voltage IOH≥-12 mA, VDD = 3.3V 1.5 — — 4x Source Driver Pins - RA0, See Note 1 RA1, RB0-RB3, RB5, RB6, RB8, IOH≥-11 mA, VDD = 3.3V DO20A VOH1 RB9, RB12-RB15, RC0-RC2 2.0 — — V See Note 1 IOH≥-3 mA, VDD = 3.3V 3.0 — — See Note 1 Output High Voltage IOH≥-16 mA, VDD = 3.3V 1.5 — — I/O Pins: See Note 1 8x Source Driver Pins - RA3, IOH≥-12 mA, VDD = 3.3V RA4 2.0 — — V See Note 1 IOH≥-4 mA, VDD = 3.3V 3.0 — — See Note 1 Note 1: Parameters are characterized, but not tested. © 2007-2012 Microchip Technology Inc. DS70292G-page 347

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min(1) Typ Max(1) Units Conditions No. BO10 VBOR BOR Event on VDD transition high-to-low 2.40 — 2.55 V VDD Note 1: Parameters are for design guidance only and are not tested in manufacturing. TABLE 30-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Program Flash Memory D130a EP Cell Endurance 10,000 — — E/W -40°C to +125°C D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132B VPEW VDD for Self-Timed Write VMIN — 3.6 V VMIN = Minimum operating voltage D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated D135 IDDP Supply Current during — 10 — mA Programming D136a TRW Row Write Time 1.32 — 1.74 ms TRW = 11064 FRC cycles, TA = +85°C, See Note 2 D136b TRW Row Write Time 1.28 — 1.79 ms TRW = 11064 FRC cycles, TA = +125°C, See Note 2 D137a TPE Page Erase Time 20.1 — 26.5 ms TPE = 168517 FRC cycles, TA = +85°C, See Note 2 D137b TPE Page Erase Time 19.5 — 27.3 ms TPE = 168517 FRC cycles, TA = +125°C, See Note 2 D138a TWW Word Write Cycle Time 42.3 — 55.9 µs TWW = 355 FRC cycles, TA = +85°C, See Note 2 D138b TWW Word Write Cycle Time 41.1 — 57.6 µs TWW = 355 FRC cycles, TA = +125°C, See Note 2 Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max). This parameter depends on the FRC accuracy (see Table30-19) and the value of the FRC Oscillator Tuning register (see Register9-4). For complete details on calculating the Minimum and Maximum time see Section5.3 “Programming Operations”. TABLE 30-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated): Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristics Min Typ Max Units Comments No. — CEFC External Filter Capacitor 4.7 10 — μF Capacitor must be low series Value(1) resistance (< 5 Ohms) Note 1: Typical VCAP voltage = 2.5V when VDD ≥ VDDMIN. DS70292G-page 348 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 30.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 AC characteristics and timing parameters. TABLE 30-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Operating voltage VDD range as described in Table30-1. FIGURE 30-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS CL Pin RL = 464Ω CL = 50 pF for all pins except OSC2 VSS 15 pF for OSC2 output TABLE 30-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol Characteristic Min Typ Max Units Conditions No. DO50 COSCO OSC2/SOSCO pin — — 15 pF In XT and HS modes when external clock is used to drive OSC1 DO56 CIO All I/O pins and OSC2 — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode © 2007-2012 Microchip Technology Inc. DS70292G-page 349

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 30-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS10 FIN External CLKI Frequency DC — 40 MHz EC (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency 3.5 — 10 MHz XT 10 — 40 MHz HS — — 33 kHz SOSC 3.5 — 10 MHz AUX_OSC_FIN OS20 TOSC TOSC = 1/FOSC 12.5 — DC ns — OS25 TCY Instruction Cycle Time(2) 25 — DC ns — OS30 TosL, External Clock in (OSC1) 0.375 x TOSC — 0.625 x TOSC ns EC TosH High or Low Time OS31 TosR, External Clock in (OSC1) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(3) — 5.2 — ns — OS41 TckF CLKO Fall Time(3) — 5.2 — ns — OS42 GM External Oscillator 14 16 18 mA/V VDD = 3.3V Transconductance(4) TA = +25ºC Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. 4: Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing. DS70292G-page 350 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS50 FPLLI PLL Voltage Controlled 0.8 — 8 MHz ECPLL, HSPLL, XTPLL Oscillator (VCO) Input modes Frequency Range OS51 FSYS On-Chip VCO System 100 — 200 MHz — Frequency OS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 mS — OS53 DCLK CLKO Stability (Jitter)(2) -3 0.5 3 % Measured over 100 ms period Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases or communication clocks use this formula: DCLK Peripheral Clock Jitter = ------------------------------------------------------------------------ ⎛ FOSC ⎞ -------------------------------------------------------------- ⎝ ⎠ Peripheral Bit Rate Clock For example: Fosc = 32 MHz, DCLK = 3%, SPI bit rate clock, (i.e., SCK) is 2 MHz. DCLK 3% 3% SPI SCK Jitter = ------------------------------ = ---------- = -------- = 0.75% ⎛32 MHz⎞ 16 4 -------------------- ⎝ ⎠ 2 MHz TABLE 30-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Characteristic Min Typ Max Units Conditions No. Internal FRC Accuracy @ 7.3728 MHz(1) F20a FRC -2 — +2 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V F20b FRC -5 — +5 % -40°C ≤ TA ≤ +125°C VDD = 3.0-3.6V Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift. TABLE 30-19: INTERNAL RC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Characteristic Min Typ Max Units Conditions No. LPRC @ 32.768 kHz(1) F21a LPRC -20 ±6 +20 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V F21b LPRC -30 — +30 % -40°C ≤ TA ≤ +125°C VDD = 3.0-3.6V Note 1: Change of LPRC frequency as VDD changes. © 2007-2012 Microchip Technology Inc. DS70292G-page 351

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-3: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure30-1 for load conditions. TABLE 30-20: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. DO31 TIOR Port Output Rise Time — 10 25 ns — DO32 TIOF Port Output Fall Time — 10 25 ns — DI35 TINP INTx Pin High or Low Time (input) 20 — — ns — DI40 TRBP CNx High or Low Time (input) 2 — — TCY — Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS70292G-page 352 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD SY12 MCLR Internal SY10 POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 353

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 T A B LE 30-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SY10 TMCL MCLR Pulse Width (low) 2 — — μs -40°C to +85°C SY11 TPWRT Power-up Timer Period — 2 — ms -40°C to +85°C 4 User programmable 8 16 32 64 128 SY12 TPOR Power-on Reset Delay 3 10 30 μs -40°C to +85°C SY13 TIOZ I/O High-Impedance 0.68 0.72 1.2 μs — from MCLR Low or Watchdog Timer Reset SY20 TWDT1 Watchdog Timer — — — — See Section27.4 “Watchdog Time-out Period Timer (WDT)” and LPRC specification F21 (Table30-19) SY30 TOST Oscillator Start-up — 1024TOSC — — TOSC = OSC1 period Timer Period SY35 TFSCM Fail-Safe Clock — 500 900 μs -40°C to +85°C Monitor Delay Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS70292G-page 354 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-5: TIMER1, 2, 3 AND 4 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRx Note: Refer to Figure30-1 for load conditions. TABLE 30-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TA10 TTXH TxCK High Time Synchronous, TCY + 20 — — ns Must also meet no prescaler parameter TA15. Synchronous, (TCY + 20)/N — — ns N = prescale value with prescaler (1, 8, 64, 256) Asynchronous 20 — — ns TA11 TTXL TxCK Low Time Synchronous, (TCY + 20) — — ns Must also meet no prescaler parameter TA15. Synchronous, (TCY + 20)/N — — ns N = prescale value with prescaler (1, 8, 64, 256) Asynchronous 20 — — ns TA15 TTXP TxCK Input Synchronous, 2 TCY + 40 — — ns — Period no prescaler Synchronous, Greater of: — — — N = prescale with prescaler 40 ns or value (2 TCY + 40)/ (1, 8, 64, 256) N Asynchronous 40 — — ns — OS60 Ft1 SOSCI/T1CK Oscillator Input DC — 50 kHz — frequency Range (oscillator enabled by setting bit TCS (T1CON<1>)) TA20 TCKEXTMRL Delay from External TxCK Clock 0.75 TCY + — 1.75 TCY + — — Edge to Timer Increment 40 40 Note 1: Timer1 is a Type A. © 2007-2012 Microchip Technology Inc. DS70292G-page 355

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 T ABLE 30-23: TIMER2 AND TIMER 4 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. TB10 TtxH TxCK High Synchronous Greater of: — — ns Must also meet Time mode 20 or parameter TB15 (TCY + 20)/N N = prescale value (1, 8, 64, 256) TB11 TtxL TxCK Low Synchronous Greater of: — — ns Must also meet Time mode 20 or parameter TB15 (TCY + 20)/N N = prescale value (1, 8, 64, 256) TB15 TtxP TxCK Synchronous Greater of: — — ns N = prescale Input mode 40 or value Period (2 TCY + 40)/N (1, 8, 64, 256) TB20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns — Clock Edge to Timer Incre- ment Note 1: These parameters are characterized, but are not tested in manufacturing. TABLE 30-24: TIMER3 AND TIMER5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. TC10 TtxH TxCK High Synchronous TCY + 20 — — ns Must also meet Time parameter TC15 TC11 TtxL TxCK Low Synchronous TCY + 20 — — ns Must also meet Time parameter TC15 TC15 TtxP TxCK Input Synchronous, 2 TCY + 40 — — ns N = prescale Period with prescaler value (1, 8, 64, 256) TC20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns — Clock Edge to Timer Incre- ment Note 1: These parameters are characterized, but are not tested in manufacturing. DS70292G-page 356 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure30-1 for load conditions. TABLE 30-25: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Max Units Conditions No. IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns — With Prescaler 10 — ns IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns — With Prescaler 10 — ns IC15 TccP ICx Input Period (TCY + 40)/N — ns N = prescale value (1, 4, 16) Note 1: These parameters are characterized but not tested in manufacturing. FIGURE 30-7: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure30-1 for load conditions. TABLE 30-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. OC10 TccF OCx Output Fall Time — — — ns See parameter D032 OC11 TccR OCx Output Rise Time — — — ns See parameter D031 Note 1: These parameters are characterized but not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70292G-page 357

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-8: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 OCx Active Tri-state TABLE 30-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. OC15 TFD Fault Input to PWM I/O — — TCY + 20 ns — Change OC20 TFLT Fault Input Pulse-Width TCY + 20 — — ns — Note 1: These parameters are characterized but not tested in manufacturing. DS70292G-page 358 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-28: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Master Master Slave Maximum Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP Data Rate (Half-Duplex) (Full-Duplex) (Full-Duplex) 15 MHz Table30-29 — — 0,1 0,1 0,1 9 MHz — Table30-30 — 1 0,1 1 9 MHz — Table30-31 — 0 0,1 1 15 MHz — — Table30-32 1 0 0 11 MHz — — Table30-33 1 1 0 15 MHz — — Table30-34 0 1 0 11 MHz — — Table30-35 0 0 0 FIGURE 30-9: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 Note: Refer to Figure30-1 for load conditions. FIGURE 30-10: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 Note: Refer to Figure30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 359

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-29: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCK Frequency — — 15 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdiV2scH, SDOx Data Output Setup to 30 — — ns — TdiV2scL First SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70292G-page 360 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-11: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP40 SDIx MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure30-1 for load conditions. TABLE 30-30: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCK Frequency — — 9 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdoV2sc, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns — TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. © 2007-2012 Microchip Technology Inc. DS70292G-page 361

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-12: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure30-1 for load conditions. TABLE 30-31: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCK Frequency — — 9 MHz -40ºC to +125ºC and see Note 3 SP20 TscF SCKx Output Fall Time — — — ns See parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns — TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70292G-page 362 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-13: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 363

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-32: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCK Input Frequency — — 15 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns — TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge SP50 TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input 120 — — ns — TssL2scL SP51 TssH2doZ SSx ↑ to SDOx Output 10 — 50 ns — High-Impedance(4) SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns — SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70292G-page 364 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-14: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SP52 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 365

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCK Input Frequency — — 11 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns — TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge SP50 TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input 120 — — ns — TssL2scL SP51 TssH2doZ SSx ↑ to SDOx Output 10 — 50 ns — High-Impedance(4) SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns — SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70292G-page 366 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-15: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 367

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCK Input Frequency — — 15 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns — TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge SP50 TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input 120 — — ns — TssL2scL SP51 TssH2doZ SSx ↑ to SDOx Output 10 — 50 ns — High-Impedance(4) SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70292G-page 368 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-16: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 369

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCK Input Frequency — — 11 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns — TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge SP50 TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input 120 — — ns — TssL2scL SP51 TssH2doZ SSx ↑ to SDOx Output 10 — 50 ns — High-Impedance(4) SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70292G-page 370 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-17: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Start Stop Condition Condition Note: Refer to Figure30-1 for load conditions. FIGURE 30-18: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM21 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 371

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 T ABLE 30-36: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min(1) Max Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — μs — 400 kHz mode TCY/2 (BRG + 1) — μs — 1 MHz mode(2) TCY/2 (BRG + 1) — μs — IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — μs — 400 kHz mode TCY/2 (BRG + 1) — μs — 1 MHz mode(2) TCY/2 (BRG + 1) — μs — IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 100 ns IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns — Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) 40 — ns IM26 THD:DAT Data Input 100 kHz mode 0 — μs — Hold Time 400 kHz mode 0 0.9 μs 1 MHz mode(2) 0.2 — μs IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — μs Only relevant for Setup Time 400 kHz mode TCY/2 (BRG + 1) — μs Repeated Start 1 MHz mode(2) TCY/2 (BRG + 1) — μs condition IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — μs After this period the Hold Time 400 kHz mode TCY/2 (BRG + 1) — μs first clock pulse is 1 MHz mode(2) TCY/2 (BRG + 1) — μs generated IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — μs — Setup Time 400 kHz mode TCY/2 (BRG + 1) — μs 1 MHz mode(2) TCY/2 (BRG + 1) — μs IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns — Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns 1 MHz mode(2) TCY/2 (BRG + 1) — ns IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns — From Clock 400 kHz mode — 1000 ns — 1 MHz mode(2) — 400 ns — IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be 400 kHz mode 1.3 — μs free before a new 1 MHz mode(2) 0.5 — μs transmission can start IM50 CB Bus Capacitive Loading — 400 pF — IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 3 Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip website (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual chapters. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: Typical value for this parameter is 130 ns. DS70292G-page 372 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-19: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS34 IS30 IS33 SDAx Start Stop Condition Condition FIGURE 30-20: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out © 2007-2012 Microchip Technology Inc. DS70292G-page 373

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-37: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param. Symbol Characteristic Min Max Units Conditions IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — μs — IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — μs — IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns — Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — μs — Hold Time 400 kHz mode 0 0.9 μs 1 MHz mode(1) 0 0.3 μs IS30 TSU:STA Start Condition 100 kHz mode 4.7 — μs Only relevant for Repeated Setup Time 400 kHz mode 0.6 — μs Start condition 1 MHz mode(1) 0.25 — μs IS31 THD:STA Start Condition 100 kHz mode 4.0 — μs After this period, the first Hold Time 400 kHz mode 0.6 — μs clock pulse is generated 1 MHz mode(1) 0.25 — μs IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — μs — Setup Time 400 kHz mode 0.6 — μs 1 MHz mode(1) 0.6 — μs IS34 THD:ST Stop Condition 100 kHz mode 4000 — ns — O Hold Time 400 kHz mode 600 — ns 1 MHz mode(1) 250 ns IS40 TAA:SCL Output Valid 100 kHz mode 0 3500 ns — From Clock 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode 1.3 — μs before a new transmission can start 1 MHz mode(1) 0.5 — μs IS50 CB Bus Capacitive Loading — 400 pF — Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS70292G-page 374 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-21: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING CHARACTERISTICS CSCK (SCKE = 0) CS11 CS10 CS21 CS20 CSCK (SCKE = 1) CS20 CS21 COFS CS55CS56 CS35 CS51 CS50 70 High-Z MSb LSb High-Z CSDO CS30 CS31 CSDI MSb In LSb In CS40 CS41 Note: Refer to Figure30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 375

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-38: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. CS10 TCSCKL CSCK Input Low Time TCY/2 + 20 — — ns — (CSCK pin is an input) CSCK Output Low Time(3) 30 — — ns — (CSCK pin is an output) CS11 TCSCKH CSCK Input High Time TCY/2 + 20 — — ns — (CSCK pin is an input) CSCK Output High Time(3) 30 — — ns — (CSCK pin is an output) CS20 TCSCKF CSCK Output Fall Time(4) — 10 25 ns — (CSCK pin is an output) CS21 TCSCKR CSCK Output Rise Time(4) — 10 25 ns — (CSCK pin is an output) CS30 TCSDOF CSDO Data Output Fall Time(4) — 10 25 ns — CS31 TCSDOR CSDO Data Output Rise Time(4) — 10 25 ns — CS35 TDV Clock Edge to CSDO Data Valid — — 10 ns — CS36 TDIV Clock Edge to CSDO Tri-Stated 10 — 20 ns — CS40 TCSDI Setup Time of CSDI Data Input to 20 — — ns — CSCK Edge (CSCK pin is input or output) CS41 THCSDI Hold Time of CSDI Data Input to 20 — — ns — CSCK Edge (CSCK pin is input or output) CS50 TCOFSF COFS Fall Time — 10 25 ns See Note 1 (COFS pin is output) CS51 TCOFSR COFS Rise Time — 10 25 ns See Note 1 (COFS pin is output) CS55 TSCOFS Setup Time of COFS Data Input 20 — — ns — to CSCK Edge (COFS pin is input) CS56 THCOFS Hold Time of COFS Data Input to 20 — — ns — CSCK Edge (COFS pin is input) Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all DCI pins. DS70292G-page 376 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-22: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 CS62 CS21 CS20 CS71 CS70 CS72 SYNC (COFS) CS76 CS75 CS80 LSb MSb LSb SDOx (CSDO) CS76 CS75 SDIx MSb In (CSDI) CS65 CS66 © 2007-2012 Microchip Technology Inc. DS70292G-page 377

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-39: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1,2) Min Typ(3) Max Units Conditions No. CS60 TBCLKL BIT_CLK Low Time 36 40.7 45 ns — CS61 TBCLKH BIT_CLK High Time 36 40.7 45 ns — CS62 TBCLK BIT_CLK Period — 81.4 — ns Bit clock is input CS65 TSACL Input Setup Time to — — 10 ns — Falling Edge of BIT_CLK CS66 THACL Input Hold Time from — — 10 ns — Falling Edge of BIT_CLK CS70 TSYNCLO SYNC Data Output Low Time — 19.5 — μs See Note 1 CS71 TSYNCHI SYNC Data Output High Time — 1.3 — μs See Note 1 CS72 TSYNC SYNC Data Output Period — 20.8 — μs See Note 1 CS75 TRACL Rise Time, SYNC, SDATA_OUT — — 30 ns CLOAD = 50 pF, VDD = 3V CS76 TFACL Fall Time, SYNC, SDATA_OUT — — 30 ns CLOAD = 50 pF, VDD = 3V CS80 TOVDACL Output Valid Delay from Rising — — 15 ns — Edge of BIT_CLK Note 1: These parameters are characterized but not tested in manufacturing. 2: These values assume BIT_CLK frequency is 12.288 MHz. 3: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70292G-page 378 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-23: ECAN™ MODULE I/O TIMING CHARACTERISTICS CiTx Pin Old Value New Value (output) CA10 CA11 CiRx Pin (input) CA20 TABLE 30-40: ECAN™ MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. CA10 TioF Port Output Fall Time — — — ns See parameter D032 CA11 TioR Port Output Rise Time — — — ns See parameter D031 CA20 Tcwf Pulse-Width to Trigger 120 ns — CAN Wake-up Filter Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2007-2012 Microchip Technology Inc. DS70292G-page 379

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-41: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of — Lesser of V VDD – 0.3 VDD + 0.3 — or 3.0 or 3.6 AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V — Reference Inputs AD05 VREFH Reference Voltage High AVSS + 2.5 — AVDD V AD05a 3.0 — 3.6 V VREFH = AVDD VREFL = AVSS = 0 AD06 VREFL Reference Voltage Low AVSS — AVDD – 2.5 V AD06a 0 — 0 V VREFH = AVDD VREFL = AVSS = 0 AD07 VREF Absolute Reference 2.5 — 3.6 V VREF = VREFH - VREFL Voltage AD08 IREF Current Drain — — 10 μA ADC off AD09 IAD Operating Current — 7.0 9.0 mA ADC operating in 10-bit mode, see Note 1 — 2.7 3.2 mA ADC operating in 12-bit mode, see Note 1 Analog Input AD12 VINH Input Voltage Range VINH VINL — VREFH V This voltage reflects Sample and Hold Channels 0, 1, 2, and 3 (CH0-CH3), positive input AD13 VINL Input Voltage Range VINL VREFL — AVSS + 1V V This voltage reflects Sample and Hold Channels 0, 1, 2, and 3 (CH0-CH3), negative input AD17 RIN Recommended Imped- — — 200 Ω 10-bit ADC ance of Analog Voltage — — 200 Ω 12-bit ADC Source Note 1: These parameters are not characterized or tested in manufacturing. DS70292G-page 380 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-42: ADC MODULE SPECIFICATIONS (12-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. ADC Accuracy (12-bit Mode) – Measurements with external VREF+/VREF- AD20a Nr Resolution(1) 12 data bits bits AD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD22a DNL Differential Nonlinearity > -1 — < 1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD23a GERR Gain Error — 3.4 10 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD24a EOFF Offset Error — 0.9 5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD25a — Monotonicity — — — — Guaranteed ADC Accuracy (12-bit Mode) – Measurements with internal VREF+/VREF- AD20a Nr Resolution(1) 12 data bits bits AD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = 0V, AVDD = 3.6V AD22a DNL Differential Nonlinearity > -1 — < 1 LSb VINL = AVSS = 0V, AVDD = 3.6V AD23a GERR Gain Error 2 10.5 20 LSb VINL = AVSS = 0V, AVDD = 3.6V AD24a EOFF Offset Error 2 3.8 10 LSb VINL = AVSS = 0V, AVDD = 3.6V AD25a — Monotonicity — — — — Guaranteed Dynamic Performance (12-bit Mode) AD30a THD Total Harmonic Distortion — — -75 dB — AD31a SINAD Signal to Noise and 68.5 69.5 — dB — Distortion AD32a SFDR Spurious Free Dynamic 80 — — dB — Range AD33a FNYQ Input Signal Bandwidth — — 250 kHz — AD34a ENOB Effective Number of Bits 11.09 11.3 — bits — Note 1: Injection currents > |0| can affect the ADC results by approximately 4 to 6 counts (i.e., VIH source > (VDD + 0.3V) or VIL source < (VSS – 0.3V). © 2007-2012 Microchip Technology Inc. DS70292G-page 381

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-43: ADC MODULE SPECIFICATIONS (10-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. ADC Accuracy (10-bit Mode) – Measurements with external VREF+/VREF- AD20b Nr Resolution(1) 10 data bits bits — AD21b INL Integral Nonlinearity -1.5 — +1.5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD22b DNL Differential Nonlinearity > -1 — < 1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD23b GERR Gain Error — 3 6 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD24b EOFF Offset Error — 2 5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD25b — Monotonicity — — — — Guaranteed ADC Accuracy (10-bit Mode) – Measurements with internal VREF+/VREF- AD20b Nr Resolution(1) 10 data bits bits — AD21b INL Integral Nonlinearity -1 — +1 LSb VINL = AVSS = 0V, AVDD = 3.6V AD22b DNL Differential Nonlinearity > -1 — < 1 LSb VINL = AVSS = 0V, AVDD = 3.6V AD23b GERR Gain Error 3 7 15 LSb VINL = AVSS = 0V, AVDD = 3.6V AD24b EOFF Offset Error 1.5 3 7 LSb VINL = AVSS = 0V, AVDD = 3.6V AD25b — Monotonicity — — — — Guaranteed Dynamic Performance (10-bit Mode) AD30b THD Total Harmonic Distortion — — -64 dB — AD31b SINAD Signal to Noise and 57 58.5 — dB — Distortion AD32b SFDR Spurious Free Dynamic 72 — — dB — Range AD33b FNYQ Input Signal Bandwidth — — 550 kHz — AD34b ENOB Effective Number of Bits 9.16 9.4 — bits — Note 1: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. DS70292G-page 382 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-24: ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP AD61 AD60 TSAMP AD55 DONE AD1IF 1 2 3 4 5 6 7 8 9 1 – Software sets AD1CON. SAMP to start sampling. 5 – Convert bit 11. 2 – Sampling starts after discharge period. TSAMP is described in 6 – Convert bit 10. Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) 7 – Convert bit 1. in the “dsPIC33F/PIC24H Family Reference Manual”. 3 – Software clears AD1CON. SAMP to start conversion. 8 – Convert bit 0. 4 – Sampling ends, conversion sequence starts. 9 – One TAD for end of conversion. © 2007-2012 Microchip Technology Inc. DS70292G-page 383

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-44: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min. Typ(2) Max. Units Conditions No. Clock Parameters(1) AD50 TAD ADC Clock Period 117.6 — — ns — AD51 tRC ADC Internal RC Oscillator — 250 — ns — Period Conversion Rate AD55 tCONV Conversion Time — 14 TAD ns — AD56 FCNV Throughput Rate — — 500 ksps — AD57 TSAMP Sample Time 3 TAD — — — — Timing Parameters AD60 tPCS Conversion Start from Sample 2 TAD — 3 TAD — Auto convert trigger not Trigger(2) selected AD61 tPSS Sample Start from Setting 2 TAD — 3 TAD — — Sample (SAMP) bit(2) AD62 tCSS Conversion Completion to — 0.5 TAD — — — Sample Start (ASAM = 1)(2) AD63 tDPU Time to Stabilize Analog Stage — — 20 μs — from ADC Off to ADC On(2,3) Note 1: Because the sample caps eventually loses charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures. 2: These parameters are characterized but not tested in manufacturing. 3: The tDPU is the time required for the ADC module to stabilize at the appropriate level when the module is turned on ADON bit (AD1CON1<15>) = ‘1’. During this time, the ADC result is indeterminate. DS70292G-page 384 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-25: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP AD61 AD60 TSAMP AD55 AD55 DONE AD1IF 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets AD1CON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33F/PIC24H Family Reference Manual”. 3 – Software clears AD1CON. SAMP to start conversion. 4 – Sampling ends, conversion sequence starts. 5 – Convert bit 9. 6 – Convert bit 8. 7 – Convert bit 0. 8 – One TAD for end of conversion. FIGURE 30-26: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Set ADON Execution SAMP TSAMP AD55 AD55 TSAMP AD55 AD1IF DONE 1 2 3 4 5 6 7 3 4 5 6 8 1 – Software sets AD1CON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. TSAMP is described in 6 – One TAD for end of conversion. Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33F/PIC24H Family Reference Manual'. 7 – Begin conversion of next channel. 3 – Convert bit 9. 8 – Sample for time specified by SAMC<4:0>. 4 – Convert bit 8. © 2007-2012 Microchip Technology Inc. DS70292G-page 385

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-45: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min. Typ(2) Max. Units Conditions No. Clock Parameters(1) AD50 TAD ADC Clock Period 76 — — ns — AD51 tRC ADC Internal RC Oscillator Period — 250 — ns — Conversion Rate AD55 tCONV Conversion Time — 12 TAD — — — AD56 FCNV Throughput Rate — — 1.1 Msps — AD57 TSAMP Sample Time 2 TAD — — — — Timing Parameters AD60 tPCS Conversion Start from Sample 2 TAD — 3 TAD — Auto-Convert Trigger Trigger(2) not selected AD61 tPSS Sample Start from Setting 2 TAD — 3 TAD — — Sample (SAMP) bit(2) AD62 tCSS Conversion Completion to — 0.5 TAD — — — Sample Start (ASAM = 1)(2) AD63 tDPU Time to Stabilize Analog Stage — — 20 μs — from ADC Off to ADC On(2,3) Note 1: Because the sample caps eventually loses charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures. 2: These parameters are characterized but not tested in manufacturing. 3: The tDPU is the time required for the ADC module to stabilize at the appropriate level when the module is turned on ADON bit (AD1CON1<15>) = 1. During this time, the ADC result is indeterminate. TABLE 30-46: AUDIO DAC MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC/DC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Clock Parameters DA01 VOD+ Positive Output Differential 1 1.15 2 V VOD+ = VDACH – VDACL Voltage See Note 1, 2 DA02 VOD- Negative Output Differential -2 -1.15 -1 V VOD- = VDACL – VDACH Voltage See Note 1, 2 DA03 VRES Resolution — 16 — bits — DA04 GERR Gain Error — 3.1 — % — DA08 FDAC Clock frequency — — 25.6 MHz — DA09 FSAMP Sample Rate 0 — 100 kHz — DA10 FINPUT Input data frequency 0 — 45 kHz Sampling frequency = 100 kHz DA11 TINIT Initialization period 1024 — — Clks Time before first sample DA12 SNR Signal-to-Noise Ratio — 61 dB Sampling frequency = 96 kHz Note 1: Measured VDACH and VDACL output with respect to VSS, with 15 µA load and FORM bit (DACXCON<8>) = 0. 2: This parameter is tested at -40°C ≤ TA ≤ 85°C only. DS70292G-page 386 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-47: COMPARATOR TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. 300 TRESP Response Time(1,2) — 150 400 ns — 301 TMC2OV Comparator Mode Change — — 10 μs — to Output Valid(1) Note 1: Parameters are characterized but not tested. 2: Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD. TABLE 30-48: COMPARATOR MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. D300 VIOFF Input Offset Voltage(1) — ±10 — mV — D301 VICM Input Common Mode Voltage(1) 0 — AVDD-1.5V V — D302 CMRR Common Mode Rejection Ratio (1) -54 — — dB — Note 1: Parameters are characterized but not tested. TABLE 30-49: COMPARATOR REFERENCE VOLTAGE SETTLING TIME SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. VR310 TSET Settling Time(1) — — 10 μs — Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 bits transition from ‘0000’ to ‘1111’. TABLE 30-50: COMPARATOR REFERENCE VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. VRD310 CVRES Resolution CVRSRC/24 — CVRSRC/32 LSb — VRD311 CVRAA Absolute Accuracy — — 0.5 LSb — VRD312 CVRUR Unit Resistor Value (R) — 2k — Ω — © 2007-2012 Microchip Technology Inc. DS70292G-page 387

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-27: PARALLEL SLAVE PORT TIMING DIAGRAM CS RD WR PS4 PMD<7:0> PS3 PS1 PS2 TABLE 30-51: PARALLEL SLAVE PORT TIME SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. PS1 TdtV2wrH Data in Valid before WR or CS 20 — — ns — Inactive (setup time) PS2 TwrH2dtI WR or CS Inactive to Data-In 20 — — ns — Invalid (hold time) PS3 TrdL2dtV RD and CS to Active Data-Out — — 80 ns — Valid PS4 TrdH2dtI RD Active or CS Inactive to 10 — 30 ns — Data-Out Invalid DS70292G-page 388 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-28: PARALLEL MASTER PORT READ TIMING DIAGRAM P1 P2 P3 P4 P1 P2 P3 P4 P1 P2 System Clock PMA<13:8> Address PMD<7:0> Address <7:0> Data PM6 PM7 PM2 PM3 PMRD PM5 PMWR PMALL/PMALH PM1 PMCS1 TABLE 30-52: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Characteristic Min. Typ Max. Units Conditions No. PM1 PMALL/PMALH Pulse-Width — 0.5 TCY — ns — PM2 Address Out Valid to PMALL/PMALH Invalid — 0.75 TCY — ns — (address setup time) PM3 PMALL/PMALH Invalid to Address Out Invalid — 0.25 TCY — ns — (address hold time) PM5 PMRD Pulse-Width — 0.5 TCY — ns — PM6 PMRD or PMENB Active to Data In Valid (data 150 — — ns — setup time) PM7 PMRD or PMENB Inactive to Data In Invalid — — 5 ns — (data hold time) © 2007-2012 Microchip Technology Inc. DS70292G-page 389

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-29: PARALLEL MASTER PORT WRITE TIMING DIAGRAM P1 P2 P3 P4 P1 P2 P3 P4 P1 P2 System Clock PMA<13:8> Address PMD<7:0> Address <7:0> DaDtaata PM12 PM13 PMRD PMWR PM11 PMALL/PMALH PMCS1 PM16 TABLE 30-53: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Characteristic Min. Typ Max. Units Conditions No. PM11 PMWR Pulse-Width — 0.5 TCY — ns — PM12 Data Out Valid before PMWR or PMENB goes — — — ns — Inactive (data setup time) PM13 PMWR or PMEMB Invalid to Data Out Invalid — — — ns — (data hold time) PM16 PMCSx Pulse-Width TCY - 5 — — ns — TABLE 30-54: DMA READ/WRITE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Characteristic Min. Typ Max. Units Conditions No. DM1 DMA Read/Write Cycle Time — — 1 TCY ns — DS70292G-page 390 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 31.0 HIGH TEMPERATURE ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 electrical characteristics for devices operating in an ambient temperature range of -40°C to +150°C. The specifications between -40°C to +150°C are identical to those shown in Section30.0 “Electrical Characteristics” for operation between -40°C to +125°C, with the exception of the parameters listed in this section. Parameters in this section begin with an H, which denotes High temperature. For example, parameter DC10 in Section30.0 “Electrical Characteristics” is the Industrial and Extended temperature equivalent of HDC10. Absolute maximum ratings for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 high temperature devices are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias(4).........................................................................................................-40°C to +150°C Storage temperature.............................................................................................................................. -65°C to +160°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(5) ....................................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(5) ....................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V(5) .................................................... -0.3V to 5.6V Maximum current out of VSS pin.............................................................................................................................60 mA Maximum current into VDD pin(2).............................................................................................................................60 mA Maximum junction temperature.............................................................................................................................+155°C Maximum current sourced/sunk by any 2x I/O pin(3)................................................................................................2 mA Maximum current sourced/sunk by any 4x I/O pin(3)................................................................................................4 mA Maximum current sourced/sunk by any 8x I/O pin(3)................................................................................................8 mA Maximum current sunk by all ports combined ........................................................................................................70 mA Maximum current sourced by all ports combined(2)................................................................................................70 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods can affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table31-2). 3: Unlike devices at 125°C and below, the specifications in this section also apply to the CLKOUT, VREF+, VREF-, SCLx, SDAx, PGCx, and PGDx pins. 4: AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 hours. Any design in which the total operating time from 125°C to 150°C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc. 5: Refer to the “Pin Diagrams” section for 5V tolerant pins. © 2007-2012 Microchip Technology Inc. DS70292G-page 391

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 31.1 High Temperature DC Characteristics TABLE 31-1: OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic VDD Range Temperature Range dsPIC33FJ32GP302/304, (in Volts) (in °C) dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 — 3.0V to 3.6V(1) -40°C to +150°C 20 Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules such as the ADC will have degraded performance. Device functionality is tested but not characterized. TABLE 31-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit High Temperature Devices Operating Junction Temperature Range TJ -40 — +155 °C Operating Ambient Temperature Range TA -40 — +150 °C Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD - Σ IOH) PD PINT + PI/O W I/O Pin Power Dissipation: I/O = Σ ({VDD - VOH} x IOH) + Σ (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ - TA)/θJA W TABLE 31-3: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Parameter Symbol Characteristic Min Typ Max Units Conditions No. Operating Voltage HDC10 Supply Voltage VDD — 3.0 3.3 3.6 V -40°C to +150°C Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules such as the ADC will have degraded performance. Device functionality is tested but not characterized. DS70292G-page 392 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Parameter Typical Max Units Conditions No. Power-Down Current (IPD) HDC60e 250 2000 μA +150°C 3.3V Base Power-Down Current(1,3) HDC61c 3 5 μA +150°C 3.3V Watchdog Timer Current: ΔIWDT(2,4) Note 1: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled to VSS. WDT, etc., are all switched off, and VREGS (RCON<8>) = 1. 2: The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 3: These currents are measured on the device containing the most memory in this family. 4: These parameters are characterized, but are not tested in manufacturing. TABLE 31-5: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +150ºC for High Temperature Parameter Doze Typical(1) Max Units Conditions No. Ratio HDC72a 39 45 1:2 mA HDC72f 18 25 1:64 mA +150°C 3.3V 20 MIPS HDC72g 18 25 1:128 mA Note 1: Parameters with Doze ratios of 1:2 and 1:64 are characterized, but are not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70292G-page 393

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-6: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param. Symbol Characteristic Min. Typ. Max. Units Conditions Output Low Voltage I/O Pins: IOL ≤ 1.8 mA, VDD = 3.3V 2x Sink Driver Pins - RA2, RA7- — — 0.4 V See Note 1 RA10, RB10, RB11, RB7, RB4, RC3-RC9 Output Low Voltage DO10 VOL I/O Pins: IOL ≤ 3.6 mA, VDD = 3.3V 4x Sink Driver Pins - RA0, RA1, — — 0.4 V See Note 1 RB0-RB3, RB5, RB6, RB8, RB9, RB12-RB15, RC0-RC2 Output Low Voltage IOL ≤ 6 mA, VDD = 3.3V I/O Pins: — — 0.4 V See Note 1 8x Sink Driver Pins - RA3, RA4 Output High Voltage I/O Pins: IOL≥-1.8 mA, VDD = 3.3V 2x Source Driver Pins - RA2, 2.4 — — V See Note 1 RA7-RA10, RB4, RB7, RB10, RB11, RC3-RC9 Output High Voltage I/O Pins: DO20 VOH IOL≥-3 mA, VDD = 3.3V 4x Source Driver Pins - RA0, 2.4 — — V See Note 1 RA1, RB0-RB3, RB5, RB6, RB8, RB9, RB12-RB15, RC0-RC2 Output High Voltage I/O Pins: IOL≥-6 mA, VDD = 3.3V 2.4 — — V 8x Source Driver Pins - RA4, See Note 1 RA3 Output High Voltage IOH≥-1.9 mA, VDD = 3.3V 1.5 — — I/O Pins: See Note 1 2x Source Driver Pins - RA2, IOH≥-1.85 mA, VDD = 3.3V RA7-RA10, RB4, RB7, RB10, 2.0 — — V See Note 1 RB11, RC3-RC9 IOH≥-1.4 mA, VDD = 3.3V 3.0 — — See Note 1 Output High Voltage IOH≥-3.9 mA, VDD = 3.3V 1.5 — — 4x Source Driver Pins - RA0, See Note 1 RA1, RB0-RB3, RB5, RB6, RB8, IOH≥-3.7 mA, VDD = 3.3V DO20A VOH1 RB9, RB12-RB15, RC0-RC2 2.0 — — V See Note 1 IOH≥-2 mA, VDD = 3.3V 3.0 — — See Note 1 Output High Voltage IOH≥-7.5 mA, VDD = 3.3V 1.5 — — I/O Pins: See Note 1 8x Source Driver Pins - RA3, IOH≥-6.8 mA, VDD = 3.3V RA4 2.0 — — V See Note 1 IOH≥-3 mA, VDD = 3.3V 3.0 — — See Note 1 Note 1: Parameters are characterized, but not tested. DS70292G-page 394 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-7: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. Program Flash Memory HD130 EP Cell Endurance 10,000 — — E/W -40°C to +150ºC(2) HD134 TRETD Characteristic Retention 20 — — Year 1000 E/W cycles or less and no other specifications are violated Note 1: These parameters are assured by design, but are not characterized or tested in manufacturing. 2: Programming of the Flash memory is allowed up to 150°C. © 2007-2012 Microchip Technology Inc. DS70292G-page 395

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 31.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 AC characteristics and timing parameters for high temperature devices. However, all AC timing specifications in this section are the same as those in Section30.2 “AC Characteristics and Timing Parameters”, with the exception of the parameters listed in this section. Parameters in this section begin with an H, which denotes High temperature. For example, parameter OS53 in Section30.2 “AC Characteristics and Timing Parameters” is the Industrial and Extended temperature equivalent of HOS53. TABLE 31-8: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Operating voltage VDD range as described in Table31-1. FIGURE 31-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS Pin CL RL = 464Ω CL = 50 pF for all pins except OSC2 VSS 15 pF for OSC2 output TABLE 31-9: PLL CLOCK TIMING SPECIFICATIONS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic Min Typ Max Units Conditions No. HOS53 DCLK CLKO Stability (Jitter)(1) -5 0.5 5 % Measured over 100 ms period Note 1: These parameters are characterized, but are not tested in manufacturing. DS70292G-page 396 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-10: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. HSP35 TscH2doV, SDOx Data Output Valid after — 10 25 ns — TscL2doV SCKx Edge HSP40 TdiV2scH, Setup Time of SDIx Data Input 28 — — ns — TdiV2scL to SCKx Edge HSP41 TscH2diL, Hold Time of SDIx Data Input 35 — — ns — TscL2diL to SCKx Edge Note 1: These parameters are characterized but not tested in manufacturing. TABLE 31-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. HSP35 TscH2doV, SDOx Data Output Valid after — 10 25 ns — TscL2doV SCKx Edge HSP36 TdoV2sc, SDOx Data Output Setup to 35 — — ns — TdoV2scL First SCKx Edge HSP40 TdiV2scH, Setup Time of SDIx Data Input 28 — — ns — TdiV2scL to SCKx Edge HSP41 TscH2diL, Hold Time of SDIx Data Input 35 — — ns — TscL2diL to SCKx Edge Note 1: These parameters are characterized but not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70292G-page 397

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. HSP35 TscH2doV, SDOx Data Output Valid after — — 35 ns — TscL2doV SCKx Edge HSP40 TdiV2scH, Setup Time of SDIx Data Input 25 — — ns — TdiV2scL to SCKx Edge HSP41 TscH2diL, Hold Time of SDIx Data Input to 25 — — ns — TscL2diL SCKx Edge HSP51 TssH2doZ SSx ↑ to SDOx Output 15 — 55 ns See Note 2 High-Impedance Note 1: These parameters are characterized but not tested in manufacturing. 2: Assumes 50 pF load on all SPIx pins. TABLE 31-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. HSP35 TscH2doV, SDOx Data Output Valid after — — 35 ns — TscL2doV SCKx Edge HSP40 TdiV2scH, Setup Time of SDIx Data Input 25 — — ns — TdiV2scL to SCKx Edge HSP41 TscH2diL, Hold Time of SDIx Data Input 25 — — ns — TscL2diL to SCKx Edge HSP51 TssH2doZ SSx ↑ to SDOX Output 15 — 55 ns See Note 2 High-Impedance HSP60 TssL2doV SDOx Data Output Valid after — — 55 ns — SSx Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Assumes 50 pF load on all SPIx pins. DS70292G-page 398 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-14: ADC MODULE SPECIFICATIONS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic Min Typ Max Units Conditions No. Reference Inputs HAD08 IREF Current Drain — 250 600 μA ADC operating, See Note 1 — — 50 μA ADC off, See Note 1 Note 1: These parameters are not characterized or tested in manufacturing. 2: These parameters are characterized, but are not tested in manufacturing. TABLE 31-15: ADC MODULE SPECIFICATIONS (12-BIT MODE) AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic Min Typ Max Units Conditions No. ADC Accuracy (12-bit Mode) – Measurements with External VREF+/VREF-(1) HAD20a Nr Resolution(3) 12 data bits bits — HAD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD22a DNL Differential Nonlinearity > -1 — < 1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD23a GERR Gain Error -2 — 10 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD24a EOFF Offset Error -3 — 5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V ADC Accuracy (12-bit Mode) – Measurements with Internal VREF+/VREF-(1) HAD20a Nr Resolution(3) 12 data bits bits — HAD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = 0V, AVDD = 3.6V HAD22a DNL Differential Nonlinearity > -1 — < 1 LSb VINL = AVSS = 0V, AVDD = 3.6V HAD23a GERR Gain Error 2 — 20 LSb VINL = AVSS = 0V, AVDD = 3.6V HAD24a EOFF Offset Error 2 — 10 LSb VINL = AVSS = 0V, AVDD = 3.6V Dynamic Performance (12-bit Mode)(2) HAD33a FNYQ Input Signal Bandwidth — — 200 kHz — Note 1: These parameters are characterized, but are tested at 20 ksps only. 2: These parameters are characterized by similarity, but are not tested in manufacturing. 3: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. © 2007-2012 Microchip Technology Inc. DS70292G-page 399

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-16: ADC MODULE SPECIFICATIONS (10-BIT MODE) AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic Min Typ Max Units Conditions No. ADC Accuracy (10-bit Mode) – Measurements with External VREF+/VREF-(1) HAD20b Nr Resolution(3) 10 data bits bits — HAD21b INL Integral Nonlinearity -3 — 3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD22b DNL Differential Nonlinearity > -1 — < 1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD23b GERR Gain Error -5 — 6 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD24b EOFF Offset Error -1 — 5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V ADC Accuracy (10-bit Mode) – Measurements with Internal VREF+/VREF-(1) HAD20b Nr Resolution(3) 10 data bits bits — HAD21b INL Integral Nonlinearity -2 — 2 LSb VINL = AVSS = 0V, AVDD = 3.6V HAD22b DNL Differential Nonlinearity > -1 — < 1 LSb VINL = AVSS = 0V, AVDD = 3.6V HAD23b GERR Gain Error -5 — 15 LSb VINL = AVSS = 0V, AVDD = 3.6V HAD24b EOFF Offset Error -1.5 — 7 LSb VINL = AVSS = 0V, AVDD = 3.6V Dynamic Performance (10-bit Mode)(2) HAD33b FNYQ Input Signal Bandwidth — — 400 kHz — Note 1: These parameters are characterized, but are tested at 20 ksps only. 2: These parameters are characterized by similarity, but are not tested in manufacturing. 3: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. DS70292G-page 400 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-17: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic Min Typ Max Units Conditions No. Clock Parameters HAD50 TAD ADC Clock Period(1) 147 — — ns — Conversion Rate HAD56 FCNV Throughput Rate(1) — — 400 Ksps — Note 1: These parameters are characterized but not tested in manufacturing. TABLE 31-18: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic Min Typ Max Units Conditions No. Clock Parameters HAD50 TAD ADC Clock Period(1) 104 — — ns — Conversion Rate HAD56 FCNV Throughput Rate(1) — — 800 Ksps — Note 1: These parameters are characterized but not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70292G-page 401

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 402 © 2007-2012 Microchip Technology Inc.

© 32.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS 2 d 00 s 7 Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. P -20 The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range IC 1 2 (e.g., outside specified power supply range) and therefore, outside the warranted range. 3 M 3 ic F ro J c FIGURE 32-1: VOH – 2x DRIVER PINS FIGURE 32-3: VOH – 8x DRIVER PINS 3 hip 2 T --00..001166 --00..004400 G e P chno --00..001144 3.6V --00..003355 3.6V 30 lo 2 g --00..001122 --00..003300 3.3V / y In 3.3V 30 c. H (A)H (A) ----0000....000010100808 3V H (A)H (A) ----0000....000022225050 3V 4, ds OO OO P II --00..000066 II --00..001155 I C --00..000044 -0.010 33 F -0.002 -0.005 J 6 0.000 4 0.000 G 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 1.00 2.00 3.00 4.00 P VOH (V) X VOH (V) 0 2 / X FIGURE 32-2: VOH – 4x DRIVER PINS FIGURE 32-4: VOH – 16x DRIVER PINS 0 4 --00..003300 --00..008800 , A 3.6V --00..007700 N 3.6V --00..002255 D 3.3V --00..006600 3.3V d s --00..002200 --00..005500 P A)A) 3V A)A) 3V IC H (H ( --00..001155 H (H ( --00..004400 3 OO OO 3 II II --00..003300 F --00..001100 J --00..002200 1 D 2 S70 -0.005 -0.010 8G 29 P 2G 0.000 0.000 X -pa 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 1.00 2.00 3.00 4.00 02 ge VOH (V) VOH (V) /X 4 0 03 4

D FIGURE 32-5: VOL – 2x DRIVER PINS FIGURE 32-7: VOL – 8x DRIVER PINS d S s 70 P 292 00..002200 00..006600 IC G 3 -p 00..001188 3 ag 3.6V 00..005500 3.6V F e 00..001166 J 404 00..001144 3.3V 00..004400 3.3V 32G 00..001122 3V 3V P A)A) A)A) 3 OL (OL ( 00..001100 OL (OL ( 00..003300 02 II 00..000088 II /3 00..002200 0 00..000066 4 , 0.004 d 0.010 s 0.002 P I 0.000 0.000 C 3 0.00 1.00 2.00 3.00 4.00 0.00 1.00 2.00 3.00 4.00 3 F VOL (V) VOL (V) J 6 4 G P X FIGURE 32-6: VOL – 4x DRIVER PINS FIGURE 32-8: VOL – 16x DRIVER PINS 0 2 / X 00..004400 00..112200 0 4 , 00..003355 3.6V 00..110000 3.6V A N 00..003300 3.3V 3.3V D 00..008800 d © 00..002255 3V 3V s 200 L (A)L (A) 00..002200 L (A)L (A) 00..006600 PIC 7-201 IOIO 00..001155 IOIO 00..004400 33F 2 M 00..001100 J1 icroch 0.005 0.020 28G ip T 0.000 0.000 P e X ch 0.00 1.00 2.00 3.00 4.00 0.00 1.00 2.00 3.00 4.00 0 n 2 olo VOL (V) VOL (V) /X gy 0 In 4 c .

© FIGURE 32-9: TYPICAL IPD CURRENT @ VDD = 3.3V, +85ºC FIGURE 32-11: TYPICAL IDOZE CURRENT @ VDD = 3.3V, +85ºC 2 d 00 s 7-2 11220000 8800..0000 PI 0 C 1 2 7700..0000 3 M 3 ic 11000000 F ro 6600..0000 J c 3 hip 880000 A)A) 2 Tec uA)uA) nt (mnt (m 5500..0000 GP hnolo I(I(PDPD 660000 CurreCurre 4400..0000 302 gy In 440000 IIDOZEDOZE 3300..0000 /30 c 4 . 2200..0000 , 200 d 10.00 s P 0 I C 0.00 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 3 1:1 2:1 64:1 128:1 3 F Temperature (Celsius) Doze Ratio J 6 4 G P FIGURE 32-10: TYPICAL IDD CURRENT @ VDD = 3.3V, +85ºC FIGURE 32-12: TYPICAL IIDLE CURRENT @ VDD = 3.3V, +85ºC X 0 2 6600 3355 / X 0 4 5500 PMD = 0, with PLL 3300 , A N 2255 D 4400 PMD = 1, with PLL mA)mA) d A)A) nt (nt ( 2200 s (m(mDD 3300 CurreCurre 1155 PIC IIDD 2200 IIIDLEIDLE 1100 33F J PMD = 0, no PLL 1 DS 10 PMD = 1, no PLL 5 28 70 G 29 0 P 2G-pag 0 0 5 10 15 20 25 30 35 40 45 10 20 MIPS 30 40 X02/ e 4 MIPS X0 05 4

D FIGURE 32-13: TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 32-14: TYPICAL LPRC FREQUENCY @ VDD = 3.3V d S s 70 P 29 7500 3355 IC 2 G 3 -p 3 a F g e J 4 3 06 Hz) 7400 Hz)Hz) 2G ncy (k ncy (kncy (k P3 que queque 3300 02 e ee / Fr FrFr 3 RC 7300 RC RC 04 F PP , LL d s P I C 3 7200 25 3 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110120 F J Temperature (Celsius) Temperature (Celsius) 6 4 G P X 0 2 / X 0 4 , A N D d © s 2 P 00 IC 7-20 33 1 F 2 M J1 ic 2 ro 8 ch G ip T P e X ch 0 n 2 olo /X gy 0 In 4 c .

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 33.0 PACKAGING INFORMATION 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX dsPIC33FJ32GP XXXXXXXXXXXXXXXXX 302-E/SP e3 YYWWNNN 0730235 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX dsPIC33FJ32GP XXXXXXXXXXXXXXXXXXXX 302-E/SO e3 XXXXXXXXXXXXXXXXXXXX 0730235 YYWWNNN 28-Lead QFN-S Example XXXXXXXX 33FJ32GP XXXXXXXX 302E/MM e3 YYWWNNN 0730235 44-Lead QFN Example XXXXXXXXXX dsPIC XXXXXXXXXX 33FJ32GP304 XXXXXXXXXX -E/ML e3 YYWWNNN 0730235 44-Lead TQFP Example dsPIC XXXXXXXXXX 33FJ32GP304 XXXXXXXXXX -I/PT e3 XXXXXXXXXX 0730235 YYWWNNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007-2012 Microchip Technology Inc. DS70292G-page 407

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 33.1 Package Details 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L c A1 b1 b e eB Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e .100 BSC Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .335 Molded Package Width E1 .240 .285 .295 Overall Length D 1.345 1.365 1.400 Tip to Seating Plane L .110 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .050 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-070B DS70292G-page 408 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2007-2012 Microchip Technology Inc. DS70292G-page 409

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70292G-page 410 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2007-2012 Microchip Technology Inc. DS70292G-page 411

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 28-Lead Plastic Quad Flat, No Lead Package (MM) – 6x6x0.9 mm Body [QFN-S] with 0.40 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E2 E b 2 2 1 1 K N N L NOTE 1 TOP VIEW BOTTOM VIEW A A3 A1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e 0.65 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E 6.00 BSC Exposed Pad Width E2 3.65 3.70 4.70 Overall Length D 6.00 BSC Exposed Pad Length D2 3.65 3.70 4.70 Contact Width b 0.23 0.38 0.43 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-124B DS70292G-page 412 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:8)(cid:9)(cid:18)(cid:11)(cid:7)(cid:13)(cid:19)(cid:9)(cid:20)(cid:21)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:22)(cid:7)(cid:23)(cid:6)(cid:9)(cid:24)(cid:25)(cid:25)(cid:26)(cid:9)(cid:27)(cid:9)(cid:28)(cid:29)(cid:28)(cid:29)(cid:30)(cid:31) (cid:9)!!(cid:9)"(cid:21)(cid:8)#(cid:9)$(cid:16)(cid:18)(cid:20)(cid:4)%& ’(cid:14)(cid:13)((cid:9)(cid:30)(cid:31))(cid:30)(cid:9)!!(cid:9)*(cid:21)+(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)+(cid:23)(cid:13)( (cid:20)(cid:21)(cid:13)(cid:6), (cid:31)(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)!(cid:10)" (cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)%(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) © 2007-2012 Microchip Technology Inc. DS70292G-page 413

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E E2 b 2 2 1 1 N NOTE 1 N L K TOP VIEW BOTTOM VIEW A A3 A1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 44 Pitch e 0.65 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E 8.00 BSC Exposed Pad Width E2 6.30 6.45 6.80 Overall Length D 8.00 BSC Exposed Pad Length D2 6.30 6.45 6.80 Contact Width b 0.25 0.30 0.38 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-103B DS70292G-page 414 © 2007-2012 Microchip Technology Inc.

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DS70292G-page 415

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70292G-page 416 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 APPENDIX A: REVISION HISTORY Revision A (September 2007) This is the initial released version of this document. Revision B (March 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. In addition, redundant information was removed that is now available in the respective chapters of the dsPIC33F/PIC24H Family Reference Manual, which can be obtained from the Microchip website (www.microchip.com). The major changes are referenced by their respective section in the following table. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Signal Note 1 added to all pin diagrams (see “Pin Diagrams”). Controllers” Add External Interrupts column and Note 3 to the “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” table. Section1.0 “Device Overview” Updated parameters PMA0, PMA1, and PMD0 through PMPD7 (Table1-1). Section6.0 “Interrupt Controller” IFS0-IFSO4 changed to IFSX (see Section6.3.2 “IFSx”). IEC0-IEC4 changed to IECX (see Section6.3.3 “IECx”). IPC0-IPC19 changed to IPCx (see Section6.3.4 “IPCx”). Section7.0 “Direct Memory Access (DMA)” Updated parameter PMP (see Table7-1). Section8.0 “Oscillator Configuration” Updated the third clock source item (External Clock) in Section8.1.1 “System Clock Sources”. Updated TUN<5:0> (OSCTUN<5:0>) bit description (see Register8-4). Section20.0 “10-bit/12-bit Analog-to-Digital Added Note 2 to Figure20-3. Converter (ADC1)” Section26.0 “Special Features” Added Note 2 to Figure26-1. Added Note after second paragraph in Section26.2 “On-Chip Voltage Regulator”. Section29.0 “Electrical Characteristics” Updated Max MIPS for temperature range of -40ºC to +125ºC in Table29-1. Updated typical values in Thermal Packaging Characteristics in Table29-3. Added parameters DI11 and DI12 to Table29-9. Updated minimum values for parameters D136 (TRW) and D137 (TPE) and removed typical values in Table29-12. Added Extended temperature range to Table29-13. Updated parameter AD63 and added Note 3 to Table29-40 and Table29-41. © 2007-2012 Microchip Technology Inc. DS70292G-page 417

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Revision C (May 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: • Changed all instances of OSCI to OSC1 and OSCO to OSC2 • Changed all instances of VDDCORE and VDDCORE/ VCAP to VCAP/VDDCORE The other changes are referenced by their respective section in the following table. TABLE A-2: MAJOR SECTION UPDATES Section Name Update Description High-Performance, 16-bit Digital Updated all pin diagrams to denote the pin voltage tolerance (see “Pin Signal Controllers Diagrams”). Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which references pin connections to VSS. Section1.0 “Device Overview” Updated AVDD in the PINOUT I/O Descriptions (see Table1-1). Added Peripheral Pin Select (PPS) capability column to Pinout I/O Descriptions (see Table1-1). Section2.0 “Guidelines for Getting Added new section to the data sheet that provides guidelines on getting Started with 16-bit Digital Signal started with 16-bit Digital Signal Controllers. Controllers” Section3.0 “CPU” Updated CPU Core Block Diagram with a connection from the DSP Engine to the Y Data Bus (see Figure3-1). Vertically extended the X and Y Data Bus lines in the DSP Engine Block Diagram (see Figure3-3). Section4.0 “Memory Organization” Updated Reset value for CORCON in the CPU Core Register Map (see Table4-1). Updated the Reset values for IPC14 and IPC15 and removed the FLTA1IE bit (IEC3) from the Interrupt Controller Register Map (see Table4-4). Updated bit locations for RPINR25 in the Peripheral Pin Select Input Register Map (see Table4-21). Updated the Reset value for CLKDIV in the System Control Register Map (see Table4-33). Section5.0 “Flash Program Updated Section5.3 “Programming Operations” with programming time Memory” formula. Section9.0 “Oscillator Updated the Oscillator System Diagram and added Note 2 (see Figure9-1). Configuration” Added Note 1 and Note 2 to the OSCON register (see Register9-1). Updated default bit values for DOZE<2:0> and FRCDIV<2:0> in the Clock Divisor (CLKDIV) Register (see Register9-2). Added a paragraph regarding FRC accuracy at the end of Section9.1.1 “System Clock Sources”. Added Note 3 to Section9.2.2 “Oscillator Switching Sequence”. Added Note 1 to the FRC Oscillator Tuning (OSCTUN) Register (see Register9-4). DS70292G-page 418 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section10.0 “Power-Saving Added the following registers: Features” • PMD1: Peripheral Module Disable Control Register 1 (Register10-1) • PMD2: Peripheral Module Disable Control Register 2 (Register10-2) • PMD3: Peripheral Module Disable Control Register 3 (Register10-3) Section11.0 “I/O Ports” Removed Table 11-1 and added reference to pin diagrams for I/O pin availability and functionality. Added paragraph on ADPCFG register default values to Section11.3 “Configuring Analog Port Pins”. Added Note box regarding PPS functionality with input mapping to Section11.6.2.1 “Input Mapping”. Section16.0 “Serial Peripheral Added Note 2 and 3 to the SPIxCON1 register (see Register16-2). Interface (SPI)” Section18.0 “Universal Updated the Notes in the UxMODE register (see Register18-1). Asynchronous Receiver Transmitter (UART)” Updated the UTXINV bit settings in the UxSTA register and added Note 1 (see Register18-2). Section19.0 “Enhanced CAN Changed bit 11 in the ECAN Control Register 1 (CiCTRL1) to Reserved (see (ECAN™) Module” Register19-1). Section21.0 “10-bit/12-bit Analog- Replaced the ADC1 Module Block Diagrams with new diagrams (see to-Digital Converter (ADC)” Figure21-1 and Figure21-2). Updated bit values for ADCS<7:0> and added Notes 1 and 2 to the ADC1 Control Register 3 (AD1CON3) (see Register21-3). Added Note 2 to the ADC1 Input Scan Select Register Low (AD1CSSL) (see Register21-7). Added Note 2 to the ADC1 Port Configuration Register Low (AD1PCFGL) (see Register21-8). Section22.0 “Audio Digital-to- Updated the midpoint voltage in the last sentence of the first paragraph. Analog Converter (DAC)” Updated the voltage swing values in the last sentence of the last paragraph in Section22.3 “DAC Output Format”. Section23.0 “Comparator Module” Updated the Comparator Voltage Reference Block Diagram (see Figure23-2). Section24.0 “Real-Time Clock and Updated the minimum positive adjust value for CAL<7:0> in the RTCC Calendar (RTCC)” Calibration and Configuration (RCFGCAL) Register (see Register24-1). Section27.0 “Special Features” Added Note 1 to the Device Configuration Register Map (see Table27-1). Updated Note 1 in the dsPIC33F Configuration Bits Description (see Table27-2). © 2007-2012 Microchip Technology Inc. DS70292G-page 419

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section30.0 “Electrical Updated Typical values for Thermal Packaging Characteristics (see Characteristics” Table30-3). Updated Min and Max values for parameter DC12 (RAM Data Retention Voltage) and added Note 4 (see Table30-4). Updated Power-Down Current Max values for parameters DC60b and DC60c (see Table30-7). Updated Characteristics for I/O Pin Input Specifications and added parameter DI21 (see Table30-9). Updated Program Memory values for parameters 136, 137, and 138 (renamed to 136a, 137a, and 138a), added parameters 136b, 137b, and 138b, and added Note 2 (see Table30-12). Added parameter OS42 (GM) to the External Clock Timing Requirements (see Table30-16). Updated Watchdog Timer Time-out Period parameter SY20 (see Table30-21). Updated the IREF Current Drain parameter AD08 (see Table30-37). Updated parameters AD30a, AD31a, AD32a, AD33a, and AD34a (see Table30-38) Updated parameters AD30b, AD31b, AD32b, AD33b, and AD34b (see Table30-39) DS70292G-page 420 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Revision D (November 2009) The revision includes the following global update: • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-3: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Signal Added information on high temperature operation (see “Operating Controllers” Range:”). Section11.0 “I/O Ports” Changed the reference to digital-only pins to 5V tolerant pins in the second paragraph of Section11.2 “Open-Drain Configuration”. Section18.0 “Universal Asynchronous Updated the two baud rate range features to: 10 Mbps to 38 bps at Receiver Transmitter (UART)” 40 MIPS. Section21.0 “10-bit/12-bit Analog-to-Digital Updated the ADC block diagrams (see Figure21-1 and Figure21-2). Converter (ADC)” Section22.0 “Audio Digital-to-Analog Removed last sentence of the first paragraph in the section. Converter (DAC)” Added a shaded note to Section22.2 “DAC Module Operation”. Updated Figure22-2: “Audio DAC Output for Ramp Input (Unsigned)”. Section27.0 “Special Features” Updated the second paragraph and removed the fourth paragraph in Section27.1 “Configuration Bits”. Updated the Device Configuration Register Map (see Table27-1). Section30.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings for high temperature and added Note 4. Removed parameters DI26, DI28, and DI29 from the I/O Pin Input Specifications (see Table30-9). Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics (see Figure30-12). Removed Table 30-43: Audio DAC Module Specifications. Original contents were updated and combined with Table30-42 of the same name. Section31.0 “High Temperature Electrical Added new chapter with high temperature specifications. Characteristics” “Product Identification System” Added the “H” definition for high temperature. © 2007-2012 Microchip Technology Inc. DS70292G-page 421

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Revision E (January 2011) This includes typographical and formatting changes throughout the data sheet text. In addition, the Preliminary marking in the footer was removed. All instances of VDDCORE have been removed. All other major changes are referenced by their respective section in the following table. TABLE A-4: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Signal The high temperature end range was updated to +150ºC (see Controllers” “Operating Range:”). Section2.0 “Guidelines for Getting Started Updated the title of Section2.3 “CPU Logic Filter Capacitor with 16-bit Digital Signal Controllers” Connection (VCAP)”. The frequency limitation for device PLL start-up conditions was updated in Section2.7 “Oscillator Value Conditions on Device Start-up”. The second paragraph in Section2.9 “Unused I/Os” was updated. Section4.0 “Memory Organization” The All Resets values for the following SFRs in the Timer Register Map were changed (see Table4-5): • TMR1 • TMR2 • TMR3 • TMR4 • TMR5 Section9.0 “Oscillator Configuration” Added Note 3 to the OSCCON: Oscillator Control Register (see Register9-1). Added Note 2 to the CLKDIV: Clock Divisor Register (see Register9-2). Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see Register9-3). Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see Register9-4). Added Note 1 to the ACLKCON: Auxiliary Control Register (see Register9-5). Section21.0 “10-bit/12-bit Analog-to-Digital Updated the VREFL references in the ADC1 module block diagrams Converter (ADC)” (see Figure21-1 and Figure21-2). Section27.0 “Special Features” Added a new paragraph and removed the third paragraph in Section27.1 “Configuration Bits”. Added the column “RTSP Effects” to the dsPIC33F Configuration Bits Descriptions (see Table27-2). DS70292G-page 422 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE A-4: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section30.0 “Electrical Characteristics” Updated the maximum value for Extended Temperature Devices in the Thermal Operating Conditions (see Table30-2). Removed Note 4 from the DC Temperature and Voltage Specifications (see Table30-4). Updated all typical and maximum Operating Current (IDD) values (see Table30-5). Updated all typical and maximum Idle Current (IIDLE) values (see Table30-6). Updated the maximum Power-Down Current (IPD) values for parameters DC60d, DC60a, and DC60b (see Table30-7). Updated all typical Doze Current (Idoze) values (see Table30-8). Updated the maximum value for parameter DI19 and added parameters DI28, DI29, DI60a, DI60b, and DI60c to the I/O Pin Input Specifications (see Table30-9). Removed Note 2 from the AC Characteristics: Internal RC Accuracy (see Table30-18). Added Note 2 to the PLL Clock Timing Specifications (see Table30-17) Updated the Internal RC Accuracy minimum and maximum values for parameter F21b (see Table30-19). Updated the characteristic description for parameter DI35 in the I/O Timing Requirements (see Table30-20). Updated all SPI specifications (see Table30-28 through Table30-35 and Figure30-9 through Figure30-16) Updated the ADC Module Specification minimum values for parameters AD05 and AD07, and updated the maximum value for parameter AD06 (see Table30-41). Updated the ADC Module Specifications (12-bit Mode) minimum and maximum values for parameter AD21a (see Table30-42). Updated all ADC Module Specifications (10-bit Mode) values, with the exception of Dynamic Performance (see Table30-43). Updated the minimum value for parameter PM6 and the maximum value for parameter PM7 in the Parallel Master Port Read Timing Requirements (see Table30-52). Added DMA Read/Write Timing Requirements (see Table30-54). © 2007-2012 Microchip Technology Inc. DS70292G-page 423

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE A-4: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section31.0 “High Temperature Electrical Updated all ambient temperature end range values to +150ºC Characteristics” throughout the chapter. Updated the storage temperature end range to +160ºC. Updated the maximum junction temperature from +145ºC to +155ºC. Updated the maximum values for High Temperature Devices in the Thermal Operating Conditions (see Table31-2). Updated the ADC Module Specifications (12-bit Mode) (see Table31-14). Updated the ADC Module Specifications (10-bit Mode) (see Table31-15). “Product Identification System” Updated the end range temperature value for H (High) devices. DS70292G-page 424 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Revision F (August 2011) This revision includes typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-5: MAJOR SECTION UPDATES Section Name Update Description Section 2.0 “Guidelines for Getting Started Updated the Recommendation Minimum Connection (see with 16-bit Digital Signal Controllers” Figure 2-1). Section27.0 “Special Features” Added Note 3 to the Connections for the On-chip Voltage Regulator diagram (see Figure27-1). Section30.0 “Electrical Characteristics” Removed Voltage on VCAP with respect to Vss from the Absolute Maximum Ratings. Removed Note 3 and parameter DC10 (VCORE) from the DC Temperature and Voltage Specifications (see Table30-4). Updated the Characteristics definition and Conditions for parameter BO10 in the Electrical Characteristics: BOR (see Table30-11). Added Note 1 to the Internal Voltage Regulator Specifications (see Table30-13). Revision G (April 2012) This revision includes typographical and formatting changes throughout the data sheet text. In addition, where applicable, new sections were added to each peripheral chapter that provide information and links to related resources, as well as helpful tips. For examples, see Section9.2 “Oscillator Resources” and Section21.4 “ADC Helpful Tips”. All other major changes are referenced by their respective section in the following table. TABLE A-6: MAJOR SECTION UPDATES Section Name Update Description Section2.0 “Guidelines for Getting Started Added two new tables: with 16-bit Digital Signal Controllers” • Crystal Recommendations (see Table2-1) • Resonator Recommendations (see Table2-2) Section30.0 “Electrical Characteristics” Updated parameters DO10 and DO20 and removed parameters DO16 and DO26 in the DC Characteristics: I/O Pin Output Specifications (see Table30-10) © 2007-2012 Microchip Technology Inc. DS70292G-page 425

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 426 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 INDEX A CPU Clocking System......................................................142 PLL Configuration.....................................................143 AC Characteristics....................................................349, 396 Selection...................................................................142 ADC Module..............................................................399 Sources....................................................................142 ADC Module (10-bit Mode).......................................400 Customer Change Notification Service.............................431 ADC Module (12-bit Mode).......................................399 Customer Notification Service..........................................431 Internal RC Accuracy................................................351 Customer Support.............................................................431 Load Conditions................................................349, 396 Alternate Interrupt Vector Table (AIVT)..............................87 D Analog-to-Digital Converter...............................................263 Data Accumulators and Adder/Subtracter..........................32 ADC1 Register Map....................................................49 Data Space Write Saturation......................................34 DMA..........................................................................263 Overflow and Saturation.............................................32 Initialization...............................................................263 Round Logic...............................................................33 Key Features.............................................................263 Write Back..................................................................33 Arithmetic Logic Unit (ALU).................................................30 Data Address Space...........................................................37 Assembler Alignment....................................................................37 MPASM Assembler...................................................334 Memory Map for dsPIC33FJ128GP202/204 B and dsPIC33FJ64GP202/204 Devices with 8 KB RAM......................................39 Barrel Shifter.......................................................................34 Memory Map for dsPIC33FJ128GP802/804 Bit-Reversed Addressing....................................................64 and dsPIC33FJ64GP802/804 Example......................................................................65 Devices with 16 KB RAM....................................40 Implementation...........................................................64 Memory Map for dsPIC33FJ32GP302/304 Devices Sequence Table (16-Entry).........................................65 with 4 KB RAM...................................................38 Block Diagrams Near Data Space........................................................37 16-bit Timer1 Module................................................189 Software Stack...........................................................61 ADC1 Module....................................................264, 265 Width..........................................................................37 Connections for On-Chip Voltage Regulator.............319 Data Converter Interface (DCI) Module............................255 DCI Module...............................................................255 DC and AC Characteristics Device Clock.....................................................141, 143 Graphs and Tables...................................................403 DSP Engine................................................................31 DC Characteristics............................................................338 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04..........................14 Doze Current (IDOZE)................................................393 High Temperature.....................................................392 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, I/O Pin Input Specifications......................................344 and dsPIC33FJ128GPX02/X04 CPU Core.........24 I/O Pin Output Specifications............................347, 394 ECAN Module...........................................................229 Input Capture............................................................199 Idle Current (IDOZE)..................................................343 Output Compare.......................................................203 Idle Current (IIDLE)....................................................341 PLL............................................................................143 Operating Current (IDD)............................................340 Operating MIPS vs. Voltage.....................................392 Reset System..............................................................77 Shared Port Structure...............................................159 Power-Down Current (IPD)........................................342 SPI............................................................................207 Power-down Current (IPD)........................................393 Program Memory..............................................348, 395 Timer2 (16-bit)..........................................................193 Temperature and Voltage.........................................392 Timer2/3 (32-bit).......................................................195 Temperature and Voltage Specifications..................339 UART........................................................................221 Thermal Operating Conditions..................................392 Watchdog Timer (WDT)............................................320 DCI C Introduction...............................................................255 DCI Module C Compilers Register Map..............................................................54 MPLAB C18..............................................................334 Development Support.......................................................333 Clock Switching.................................................................151 DMA Module Enabling....................................................................151 DMA Register Map.....................................................50 Sequence..................................................................151 DMAC Registers...............................................................131 Code Examples DMAxCNT................................................................131 Erasing a Program Memory Page...............................75 DMAxCON................................................................131 Initiating a Programming Sequence............................76 DMAxPAD................................................................131 Loading Write Buffers.................................................76 DMAxREQ................................................................131 Port Write/Read........................................................160 DMAxSTA.................................................................131 PWRSAV Instruction Syntax.....................................153 DMAxSTB.................................................................131 Code Protection........................................................315, 321 Doze Mode.......................................................................154 Comparator Module..........................................................277 DSP Engine........................................................................30 Configuration Bits..............................................................315 Multiplier.....................................................................32 Configuration Register Map..............................................315 Configuring Analog Port Pins............................................160 E CPU ECAN Module Control Register..........................................................27 CiBUFPNT1 register.................................................241 © 2007-2012 Microchip Technology Inc. DS70292G-page 427

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 CiBUFPNT2 register.................................................242 Errata..................................................................................11 CiBUFPNT3 register.................................................242 F CiBUFPNT4 register.................................................243 CiCFG1 register........................................................239 Flash Program Memory......................................................71 CiCFG2 register........................................................240 Control Registers........................................................72 CiCTRL1 register......................................................232 Operations..................................................................72 CiCTRL2 register......................................................233 Programming Algorithm..............................................75 CiEC register.............................................................239 RTSP Operation.........................................................72 CiFCTRL register......................................................235 Table Instructions.......................................................71 CiFEN1 register........................................................241 Flexible Configuration.......................................................315 CiFIFO register.........................................................236 H CiFMSKSEL1 register...............................................245 CiFMSKSEL2 register...............................................246 High Temperature Electrical Characteristics....................391 CiINTE register.........................................................238 I CiINTF register..........................................................237 CiRXFnEID register..................................................245 I/O Ports............................................................................159 CiRXFnSID register..................................................244 Parallel I/O (PIO)......................................................159 CiRXFUL1 register....................................................248 Write/Read Timing....................................................160 CiRXFUL2 register....................................................248 I2C CiRXMnEID register..................................................247 Operating Modes......................................................213 CiRXMnSID register..................................................247 Registers..................................................................215 CiRXOVF1 register...................................................249 In-Circuit Debugger...........................................................321 CiRXOVF2 register...................................................249 In-Circuit Emulation..........................................................315 CiTRmnCON register................................................250 In-Circuit Serial Programming (ICSP).......................315, 321 CiVEC register..........................................................234 Input Capture....................................................................199 ECAN1 Register Map (C1CTRL1.WIN = 0 or 1).........52 Registers..................................................................201 ECAN1 Register Map (C1CTRL1.WIN = 0)................52 Input Change Notification.................................................160 ECAN1 Register Map (C1CTRL1.WIN = 1)................53 Instruction Addressing Modes............................................61 Frame Types.............................................................228 File Register Instructions............................................61 Modes of Operation..................................................230 Fundamental Modes Supported.................................62 Overview...................................................................227 MAC Instructions........................................................62 ECAN Registers MCU Instructions........................................................61 Acceptance Filter Enable Register (CiFEN1)............241 Move and Accumulator Instructions............................62 Acceptance Filter Extended Identifier Register n Other Instructions.......................................................62 (CiRXFnEID).....................................................245 Instruction Set Acceptance Filter Mask Extended Identifier Register n Overview...................................................................328 (CiRXMnEID)....................................................247 Summary..................................................................325 Acceptance Filter Mask Standard Identifier Register n Instruction-Based Power-Saving Modes...........................153 (CiRXMnSID)....................................................247 Idle............................................................................154 Acceptance Filter Standard Identifier Register n Sleep........................................................................153 (CiRXFnSID).....................................................244 Internal RC Oscillator Baud Rate Configuration Register 1 (CiCFG1).........239 Use with WDT...........................................................320 Baud Rate Configuration Register 2 (CiCFG2).........240 Internet Address...............................................................431 Control Register 1 (CiCTRL1)...................................232 Interrupt Control and Status Registers...............................91 Control Register 2 (CiCTRL2)...................................233 IECx............................................................................91 FIFO Control Register (CiFCTRL)............................235 IFSx............................................................................91 FIFO Status Register (CiFIFO).................................236 INTCON1....................................................................91 Filter 0-3 Buffer Pointer Register (CiBUFPNT1).......241 INTCON2....................................................................91 Filter 12-15 Buffer Pointer Register (CiBUFPNT4)...243 IPCx............................................................................91 Filter 15-8 Mask Selection Register (CiFMSKSEL2).246 Interrupt Setup Procedures...............................................127 Filter 4-7 Buffer Pointer Register (CiBUFPNT2).......242 Initialization...............................................................127 Filter 7-0 Mask Selection Register (CiFMSKSEL1)...245 Interrupt Disable.......................................................127 Filter 8-11 Buffer Pointer Register (CiBUFPNT3).....242 Interrupt Service Routine..........................................127 Interrupt Code Register (CiVEC)..............................234 Trap Service Routine................................................127 Interrupt Enable Register (CiINTE)...........................238 Interrupt Vector Table (IVT)................................................87 Interrupt Flag Register (CiINTF)...............................237 Interrupts Coincident with Power Save Instructions.........154 Receive Buffer Full Register 1 (CiRXFUL1)..............248 J Receive Buffer Full Register 2 (CiRXFUL2)..............248 JTAG Boundary Scan Interface........................................315 Receive Buffer Overflow Register 2 (CiRXOVF2).....249 JTAG Interface..................................................................321 Receive Overflow Register (CiRXOVF1)..................249 ECAN Transmit/Receive Error Count Register (CiEC).....239 M ECAN TX/RX Buffer m Control Register (CiTRmnCON)..250 Memory Organization.........................................................35 Electrical Characteristics...................................................337 Microchip Internet Web Site..............................................431 AC.....................................................................349, 396 Modes of Operation Enhanced CAN Module.....................................................227 Disable......................................................................230 Equations Initialization...............................................................230 Device Operating Frequency....................................142 DS70292G-page 428 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Listen All Messages..................................................230 AD1CON4 (ADC1 Control 4)....................................272 Listen Only................................................................230 AD1CSSL (ADC1 Input Scan Select Low)...............275 Loopback..................................................................230 AD1PCFGL (ADC1 Port Configuration Low)............275 Normal Operation......................................................230 CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)..........241 Modulo Addressing.............................................................63 CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)..........242 Applicability.................................................................64 CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)........242 Operation Example.....................................................63 CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer)......243 Start and End Address................................................63 CiCFG1 (ECAN Baud Rate Configuration 1)............239 W Address Register Selection....................................63 CiCFG2 (ECAN Baud Rate Configuration 2)............240 MPLAB ASM30 Assembler, Linker, Librarian...................334 CiCTRL1 (ECAN Control 1)......................................232 MPLAB Integrated Development Environment Software..333 CiCTRL2 (ECAN Control 2)......................................233 MPLAB PM3 Device Programmer....................................336 CiEC (ECAN Transmit/Receive Error Count)...........239 MPLAB REAL ICE In-Circuit Emulator System.................335 CiFCTRL (ECAN FIFO Control)...............................235 MPLINK Object Linker/MPLIB Object Librarian................334 CiFEN1 (ECAN Acceptance Filter Enable)...............241 CiFIFO (ECAN FIFO Status)....................................236 N CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection)....245, NVM Module 246 Register Map...............................................................60 CiINTE (ECAN Interrupt Enable)..............................238 CiINTF (ECAN Interrupt Flag)..................................237 O CiRXFnEID (ECAN Acceptance Filter n Open-Drain Configuration.................................................160 Extended Identifier)..........................................245 Output Compare...............................................................203 CiRXFnSID (ECAN Acceptance Filter n P Standard Identifier)...........................................244 CiRXFUL1 (ECAN Receive Buffer Full 1).................248 Packaging.........................................................................407 CiRXFUL2 (ECAN Receive Buffer Full 2).................248 Marking.....................................................................407 CiRXMnEID (ECAN Acceptance Filter Mask n Peripheral Module Disable (PMD)....................................154 Extended Identifier)..........................................247 Pinout I/O Descriptions (table)............................................15 CiRXMnSID (ECAN Acceptance Filter Mask n PMD Module Standard Identifier)...........................................247 Register Map...............................................................60 CiRXOVF1 (ECAN Receive Buffer Overflow 1)........249 PORTA CiRXOVF2 (ECAN Receive Buffer Overflow 2)........249 Register Map.........................................................58, 59 CiTRBnSID (ECAN Buffer n Standard Identifier).....251, PORTB 252, 254 Register Map...............................................................59 CiTRmnCON (ECAN TX/RX Buffer m Control)........250 Power-on Reset (POR).......................................................83 CiVEC (ECAN Interrupt Code).................................234 Power-Saving Features....................................................153 CLKDIV (Clock Divisor)............................................147 Clock Frequency and Switching................................153 CORCON (Core Control)......................................29, 92 Program Address Space.....................................................35 DCICON1 (DCI Control 1)........................................257 Construction................................................................66 DCICON2 (DCI Control 2)........................................258 Data Access from Program Memory Using DCICON3 (DCI Control 3)........................................259 Program Space Visibility.....................................69 DCISTAT (DCI Status).............................................260 Data Access from Program Memory Using DMACS0 (DMA Controller Status 0)........................136 Table Instructions...............................................68 DMACS1 (DMA Controller Status 1)........................138 Data Access from, Address Generation......................67 DMAxCNT (DMA Channel x Transfer Count)...........135 Memory Map...............................................................35 DMAxCON (DMA Channel x Control).......................132 Table Read Instructions DMAxPAD (DMA Channel x Peripheral Address)....135 TBLRDH.............................................................68 DMAxREQ (DMA Channel x IRQ Select).................133 TBLRDL..............................................................68 DMAxSTA (DMA Channel x RAM Start Address A).134 Visibility Operation......................................................69 DMAxSTB (DMA Channel x RAM Start Address B).134 Program Memory DSADR (Most Recent DMA RAM Address).............139 Interrupt Vector...........................................................36 I2CxCON (I2Cx Control)...........................................216 Organization................................................................36 I2CxMSK (I2Cx Slave Mode Address Mask)............220 Reset Vector...............................................................36 I2CxSTAT (I2Cx Status)...........................................218 R IFS0 (Interrupt Flag Status 0).............................96, 103 IFS1 (Interrupt Flag Status 1).............................98, 105 Reader Response.............................................................432 IFS2 (Interrupt Flag Status 2)...........................100, 107 Register Map IFS3 (Interrupt Flag Status 3)...........................101, 108 CRC............................................................................58 IFS4 (Interrupt Flag Status 4)...........................102, 109 Dual Comparator.........................................................58 INTCON1 (Interrupt Control 1)...................................93 Parallel Master/Slave Port..........................................57 INTCON2 (Interrupt Control 2)...................................95 Real-Time Clock and Calendar...................................58 INTTREG Interrupt Control and Status Register......126 Registers IPC0 (Interrupt Priority Control 0).............................110 AD1CHS0 (ADC1 Input Channel 0 Select................274 IPC1 (Interrupt Priority Control 1).............................111 AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)...273 IPC11 (Interrupt Priority Control 11).........................120 AD1CON1 (ADC1 Control 1)....................................268 IPC14 (Interrupt Priority Control 14).........................121 AD1CON2 (ADC1 Control 2)....................................270 IPC15 (Interrupt Priority Control 15).........................122 AD1CON3 (ADC1 Control 3)....................................271 IPC16 (Interrupt Priority Control 16).........................123 © 2007-2012 Microchip Technology Inc. DS70292G-page 429

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 IPC17 (Interrupt Priority Control 17).........................124 10-bit ADC (CHPS<1:0> = 01, IPC18 (Interrupt Priority Control 18).........................125 SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, IPC2 (Interrupt Priority Control 2).............................112 SAMC<4:0> = 00001).......................................385 IPC3 (Interrupt Priority Control 3).............................113 12-bit ADC (ASAM = 0, IPC4 (Interrupt Priority Control 4).............................114 SSRC<2:0> = 000)...........................................383 IPC5 (Interrupt Priority Control 5).............................115 Brown-out Situations...................................................84 IPC6 (Interrupt Priority Control 6).............................116 DCI AC-Link Mode....................................................377 IPC7 (Interrupt Priority Control 7).............................117 DCI Multi -Channel, I2S Modes.................................375 IPC8 (Interrupt Priority Control 8).............................118 ECAN I/O..................................................................379 IPC9 (Interrupt Priority Control 9).............................119 External Clock...........................................................350 NVMCON (Flash Memory Control).............................73 I2Cx Bus Data (Master Mode)..................................371 NVMKEY (Nonvolatile Memory Key)..........................74 I2Cx Bus Data (Slave Mode)....................................373 OCxCON (Output Compare x Control).....................206 I2Cx Bus Start/Stop Bits (Master Mode)...................371 OSCCON (Oscillator Control)...................................145 I2Cx Bus Start/Stop Bits (Slave Mode).....................373 OSCTUN (FRC Oscillator Tuning)............................149 Input Capture (CAPx)...............................................357 PLLFBD (PLL Feedback Divisor)..............................148 OC/PWM...................................................................358 PMD1 (Peripheral Module Disable Output Compare (OCx).............................................357 Control Register 1)............................................156 Reset, Watchdog Timer, Oscillator Start-up Timer PMD2 (Peripheral Module Disable and Power-up Timer.........................................353 Control Register 2)............................................157 Timer1, 2 and 3 External Clock................................355 PMD3 (Peripheral Module Disable Timing Requirements Control Register 3)............................................158 ADC Conversion (10-bit mode).................................401 PxTCON (PWM Time Base Control).........280, 281, 282 ADC Conversion (12-bit Mode).................................401 RCON (Reset Control)................................................79 CLKO and I/O...........................................................352 RSCON (DCI Receive Slot Control)..........................261 DCI AC-Link Mode....................................................378 SPIxCON1 (SPIx Control 1)......................................210 DCI Multi-Channel, I2S Modes..................................376 SPIxCON2 (SPIx Control 2)......................................212 External Clock...........................................................350 SPIxSTAT (SPIx Status and Control).......................209 Input Capture............................................................357 SR (CPU Status)...................................................27, 92 SPIx Master Mode (CKE = 0)...................................397 T1CON (Timer1 Control)...........................................191 SPIx Module Master Mode (CKE = 1)......................397 TCxCON (Input Capture x Control)...........................201 SPIx Module Slave Mode (CKE = 0)........................398 TSCON (DCI Transmit Slot Control).........................261 SPIx Module Slave Mode (CKE = 1)........................398 TxCON (Type B Time Base Control)........................196 Timing Specifications TyCON (Type C Time Base Control)........................197 10-bit ADC Conversion Requirements......................386 UxMODE (UARTx Mode)..........................................223 12-bit ADC Conversion Requirements......................384 UxSTA (UARTx Status and Control).........................225 CAN I/O Requirements.............................................379 Reset I2Cx Bus Data Requirements (Master Mode)...........372 Illegal Opcode.......................................................77, 85 I2Cx Bus Data Requirements (Slave Mode).............374 Trap Conflict..........................................................84, 85 Output Compare Requirements................................357 Uninitialized W Register........................................77, 85 PLL Clock.........................................................351, 396 Reset Sequence..................................................................87 QEI External Clock Requirements............................356 Resets.................................................................................77 QEI Index Pulse Requirements................................358 Reset, Watchdog Timer, Oscillator Start-up Timer, S Power-up Timer and Brown-out Serial Peripheral Interface (SPI).......................................207 Reset Requirements.........................................354 Software Reset Instruction (SWR)......................................84 Simple OC/PWM Mode Requirements.....................358 Software Simulator (MPLAB SIM).....................................335 Timer1 External Clock Requirements.......................355 Software Stack Pointer, Frame Pointer Timer2 External Clock Requirements.......................356 CALLL Stack Frame....................................................61 Timer3 External Clock Requirements.......................356 Special Features of the CPU.............................................315 U SPI Module SPI1 Register Map......................................................48 UART Module Symbols Used in Opcode Descriptions.............................326 UART1 Register Map............................................47, 48 System Control Universal Asynchronous Receiver Transmitter (UART)...221 Register Map...............................................................60 Using the RCON Status Bits...............................................85 T V Temperature and Voltage Specifications Voltage Regulator (On-Chip)............................................319 AC.....................................................................349, 396 W Timer1...............................................................................189 Timer2/3............................................................................193 Watchdog Time-out Reset (WDTR)....................................84 Timing Characteristics Watchdog Timer (WDT)............................................315, 320 CLKO and I/O...........................................................352 Programming Considerations...................................320 Timing Diagrams WWW Address.................................................................431 10-bit ADC (CHPS<1:0> = 01, WWW, On-Line Support.....................................................11 SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)...........................................385 DS70292G-page 430 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design • Development Systems Information Line resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQs), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. © 2007-2012 Microchip Technology Inc. DS70292G-page 431

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and Literature Number: DS70292G dsPIC33FJ128GPX02/X04 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70292G-page 432 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 32 GP3 02 T E / SP - XXX Examples: a)dsPIC33FJ32GP302-E/SP: Microchip Trademark General Purpose dsPIC33, 32KB program memory, 28-pin, Extended temperature, Architecture SPDIP package. Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture: 33 = 16-bit Digital Signal Controller Flash Memory Family: FJ = Flash program memory, 3.3V Product Group: GP2 = General Purpose family GP3 = General Purpose family GP8 = General Purpose family Pin Count: 02 = 28-pin 04 = 44-pin Temperature Range: I = -40°C to+85°C (Industrial) E = -40°C to+125°C (Extended) H = -40°C to+150°C (High) Package: SP = Skinny Plastic Dual In-Line - 300 mil body (SPDIP) SO = Plastic Small Outline - Wide - 7.5 mil body (SOIC) ML = Plastic Quad, No Lead Package - 8x8 mm body (QFN) MM = Plastic Quad, No Lead Package - 6x6x0.9 mm body (QFN-S) PT = Plastic Thin Quad Flatpack - 10x10x1 mm body (TQFP) © 2007-2012 Microchip Technology Inc. DS70292G-page 433

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 434 © 2007-2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT, devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC, intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-235-6 QUALITY MANAGEMENT  SYSTEM  Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV  Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping     devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2007-2012 Microchip Technology Inc. DS70292G-page 435

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