dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 16-bit Digital Signal Controllers (up to 32 KB Flash and 2 KB SRAM) with Motor Control and Advanced Analog Operating Conditions • Six analog inputs on 28-pin devices and up to nine analog inputs on 44-pin devices • 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS • Flexible and independent ADC trigger sources • 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS Timers/Output Compare/Input Capture Core: 16-bit dsPIC33F CPU • Three 16-bit timers/counters. Can pair up two to • Code-efficient (C and Assembly) architecture make one 32-bit. • Two 40-bit wide accumulators • Two Output Capture modules configurable as • Single-cycle (MAC/MPY) with dual data fetch timers/counters • Single-cycle mixed-sign MUL plus hardware divide • Four Input Capture modules • Peripheral Pin Select (PPS) to allow function Clock Management remap • 2% internal oscillator Communication Interfaces • Programmable PLLs and oscillator clock sources • One UART module (10 Mbps) • Fail-Safe Clock Monitor (FSCM) • With support for LIN 2.0 protocols and IrDA® • Independent Watchdog Timer (WDT) • One 4-wire SPI module (15 Mbps) • Fast wake-up and start-up • One I2C™ module (up to 1 Mbaud) with SMBus Power Management support • Low-power management modes (Sleep, Idle, Doze) • PPS to allow function remap • Integrated Power-on Reset and Brown-out Reset Input/Output • 1.35 mA/MHz dynamic current (typical) • Sink/Source up to 10 mA (pin specific) for stan- • 55 μA IPD current (typical) dard VOH/VOL, up to 16 mA (pin specific) for High-Speed PWM non-standard VOH1 • 5V-tolerant pins • Up to four PWM pairs with independent timing • Selectable open drain, pull-ups, and pull-downs • Dead time for rising and falling edges • Up to 5 mA overvoltage clamp current • 12.5 ns PWM resolution • External interrupts on all I/O pins • PWM support for: - DC/DC, AC/DC, Inverters, PFC, Lighting Qualification and Class B Support - BLDC, PMSM, ACIM, SRM • AEC-Q100 REVG (Grade 0 -40ºC to +150ºC) • Programmable Fault inputs • Class B Safety Library, IEC 60730 • Flexible trigger configurations for ADC conversions Debugger Development Support Advanced Analog Features • In-circuit and in-application programming • ADC module: • Two program and two complex data breakpoints - Configurable as 10-bit, 1.1 Msps with four • IEEE 1149.2-compatible (JTAG) boundary scan S&H or 12-bit, 500 ksps with one S&H • Trace and run-time watch Packages Type SPDIP SOIC SSOP QFN-S QFN TQFP Pin Count 28 28 28 28 44 44 Contact Lead/Pitch .100'' 1.27 0.65 0.65 0.65 0.80 I/O Pins 21 21 21 21 35 35 Dimensions 1.365x.285x.135'' 17.9xx7.50x2.05 10.2x5.3x1.75 6x6x0.9 8x8x0.9 10x10x1 Note: All dimensions are in millimeters (mm) unless specified. © 2007-2012 Microchip Technology Inc. DS70283K-page 1

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Product Families The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CONTROLLER FAMILIES e) Remappable Peripherals yt b K Device Pins gram Flash Memory ( RAM (Kbyte) Remappable Pins 16-bit Timer Input Capture Output CompareStandard PWM Motor Control PWM Quadrature Encoder Interface UART (3)External Interrupts SPI 10-Bit/12-Bit ADC 2IC™ I/O Pins Packages o r P dsPIC33FJ32MC202 28 32 2 16 3(1) 4 2 6ch(2) 1 1 3 1 1ADC, 1 21 SPDIP 2ch(2) 6 ch SOIC SSOP QFN-S dsPIC33FJ32MC204 44 32 2 26 3(1) 4 2 6ch(2) 1 1 3 1 1ADC, 1 35 QFN 2ch(2) 9 ch TQFP dsPIC33FJ16MC304 44 16 2 26 3(1) 4 2 6ch(2) 1 1 3 1 1ADC, 1 35 QFN 2ch(2) 9 ch TQFP Note 1: Only two out of three timers are remappable. 2: Only PWM fault inputs are remappable. 3: Only two out of three interrupts are remappable. DS70283K-page 2 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Pin Diagrams 28-PIN SPDIP, SOIC, SSOP = Pins are up to 5V tolerant MCLR 1 28 AVDD AN0/VREF+/CN2/RA0 2 27 AVSS AN1/VREF-/CN3/RA1 3 d 26 PWM1L1/RP15(1)/CN11/RB15 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 4 sP 25 PWM1H1/RP14(1)/CN12/RB14 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 5 IC 24 PWM1L2/RP13(1)/CN13/RB13 AN4/RP2(1)/CN6/RB2 6 33 23 PWM1H2/RP12(1)/CN14/RB12 AN5/RP3(1)/CN7/RB3 7 FJ 22 PGEC2/TMS/PWM1L3/RP11(1)/CN15/RB11 VSS 8 32 21 PGED2/TDI/PWM1H3/RP10(1)/CN16/RB10 OSC1/CLKI/CN30/RA2 9 M 20 VCAP C OSC2/CLKO/CN29/RA3 10 2 19 VSS SOSCI/RP4(1)/CN1/RB4 11 02 18 TDO/PWM2L1/SDA1/RP9(1)/CN21/RB9 SOSCO/T1CK/CN0/RA4 12 17 TCK/PWM2H1/SCL1/RP8(1)/CN22/RB8 VDD 13 16 INT0/RP7/CN23/RB7 PGED3/ASDA1/RP5(1)/CN27/RB5 14 15 PGEC3/ASCL1/RP6(1)/CN24/RB6 28-Pin QFN-S(2) = Pins are up to 5V tolerant RB15 RB14 CN3/RA1 CN2/RA0 (1)P15/CN11/(1)P14/CN12/ AN1/V-/REF AN0/V+/REF MCLR AVDD AVSSPWM1L1/R PWM1H1/R 28272625242322 PGED1/EMUD1/AN2/C2IN-/RP0(1)/CN4/RB0 1 21 PWM1L2/RP13(1)/CN13/RB13 PGEC1/EMUC1/AN3/C2IN+/RP1(1)/CN5/RB1 2 20 PWM1H2/RP12(1)/CN14/RB12 AN4/RP2(1)/CN6/RB2 3 19 PGEC2/EMUC2/TMS/PWM1L3/RP11(1)/CN15/RB11 AN5/RP3(1)/CN7/RB3 4 dsPIC33FJ32MC202 18 PGED2/EMUD2/TDI/PWM1H3/RP10(1)/CN16/RB10 VSS 5 17 VCAP OSC1/CLKI/CN30/RA2 6 16 VSS OSC2/CLKO/CN29/RA3 7 15 TDO/PWM2L1/SDA1/RP9(1)/CN21/RB9 8 9 1011121314 4 4 D 5 6 7 8 B A D B B B B R R V R R R R 1/ 0/ 7/ 4/ 3/ 2/ N N 2 2 2 2 C C N N N N SOSCI/RP4/ OSCO/T1CK/ (1)DA1/RP5/C(1)CL1/RP6/C(1)NT0/RP7/C(1)CL1/RP8/C S S S I S 3/A 3/A H1/ D C 2 U U M M M W E E P 3/ 3/ K/ D C C E E T G G P P Note1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. © 2007-2012 Microchip Technology Inc. DS70283K-page 3

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Pin Diagrams (Continued) 44-Pin QFN(2) = Pins are up to 5V tolerant RB1 RB0 N5/ N4/ C C (1)UC1/AN3/C2IN+/RP1/(1)UD1/AN2/C2IN-/RP0/ CN3/RA1 CN2/RA0 (1)P15/CN11/RB15(1)P14/CN12/RB14 PGEC1/EM PGED1/EM AN1/V-/REF AN0/V+/REF MCLR AVDD AVSS PWM1L1/R PWM1H1/R TCK/RA7 TMS/RA10 22 21 20 19 18 17 16 15 14 13 12 AN4/RP2(1)/CN6/RB2 23 11 PWM1L2/RP13(1)/CN13/RB13 AN5/RP3(1)/CN7/RB3 24 10 PWM1H2/RP12(1)/CN14/RB12 AN6/RP16(1)/CN8/RC0 25 9 PGEC2/EMUC2/PWM1L3/RP11(1)/CN15/RB11 AN7/RP17(1)/CN9/RC1 26 8 PGED2/EMUD2/PWM1H3/RP10(1)/CN16/RB10 AN8/RP18(1)/CN10/RC2 27 dsPIC33FJ32MC204 7 VCAP VDD 28 dsPIC33FJ16MC304 6 VSS VSS 29 5 RP25/CN19/RC9 OSC1/CLKI/CN30/RA2 30 4 RP24/CN20/RC8 OSC2/CLKO/CN29/RA3 31 3 PWM2L1/RP23(1)/CN17/RC7 TDO/RA8 32 2 PWM2H1/RP22(1)/CN18/RC6 SOSCI/RP4(1)/CN1/RB4 33 1 SDA1/RP9(1)/CN21/RB9 34 35 36 37 38 39 40 41 42 43 44 4 9 3 4 5 S D 5 6 7 8 A A C C C S D B B B B R R R R R V V R R R R CN0/ TDI/ N28/ N25/ N26/ N27/ N24/ N23/ N22/ O/T1CK/ (1)P19/C(1)P20/C(1)P21/C (1)RP5/C(1)RP6/C 0/RP7/C(1)RP8/C OSC R R R DA1/ CL1/ INT CL1/ S S S S A A 3/ 3/ D C U U M M E E 3/ 3/ D C E E G G P P Note1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70283K-page 4 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Pin Diagrams (Continued) 44-Pin TQFP = Pins are up to 5V tolerant RB1RB0 N5/N4/ CC (1)UC1/AN3/C2IN+/RP1/(1)UD1/AN2/C2IN-/RP0/CN3/RA1CN2/RA0 (1)P15/CN11/RB15(1)P14/CN12/RB14 PGEC1/EMPGED1/EMAN1/V-/REF AN0/V+/REF MCLR AVDD AVSS PWM1L1/RPWM1H1/RTCK/RA7TMS/RA10 222 1 11111 11 AN4/RP2(1)/CN6/RB2 23210 9 87654 3211 PWM1L2/RP13(1)/CN13/RB13 AN5/RP3(1)/CN7/RB3 24 10 PWM1H2/RP12(1)/CN14/RB12 AN6/RP16(1)/CN8/RC0 25 9 PGEC2/EMUC2/PWM1L3/RP11(1)/CN15/RB11 AN7/RP17(1)/CN9/RC1 26 8 PGED2/EMUD2/PWM1H3/RP10(1)/CN16/RB10 AN8/RP18(1)/CN10/RC2 27 7 VCAP VDD 28 dsPIC33FJ32MC204 6 VSS VSS 29 dsPIC33FJ16MC304 5 RP25(1)/CN19/RC9 OSC1/CLKI/CN30/RA2 30 4 RP24(1)/CN20/RC8 OSC2/CLKO/CN29/RA3 31 3 PWM2L1/RP23(1)/CN17/RC7 TDO/RA8 32 2 PWM2H1/RP22(1)/CN18/RC6 SOSCI/RP4(1)/CN1/RB4 33 1 SDA1/RP9(1)/CN21/RB9 34353637 383940 4142 4344 4 9345 S D5678 A ACCC S DBBBB R RRRRV VRRRR CN0/ TDI/N28/N25/N26/ N27/N24/N23/N22/ O/T1CK/ (1)P19/C(1)P20/C(1)P21/C (1)RP5/C(1)RP6/C(1)RP7/C(1)RP8/C C RRR 1/1/0/1/ S ALTL O DCNC S SSIS AA 3/3/ DC UU MM EE 3/3/ DC EE GG PP Note1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. © 2007-2012 Microchip Technology Inc. DS70283K-page 5

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Table of Contents dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Product Families..................................................................................................2 1.0 Device Overview..........................................................................................................................................................................9 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers..........................................................................................13 3.0 CPU............................................................................................................................................................................................17 4.0 Memory Organization.................................................................................................................................................................29 5.0 Flash Program Memory..............................................................................................................................................................55 6.0 Resets .......................................................................................................................................................................................61 7.0 Interrupt Controller.....................................................................................................................................................................71 8.0 Oscillator Configuration............................................................................................................................................................101 9.0 Power-Saving Features............................................................................................................................................................111 10.0 I/O Ports...................................................................................................................................................................................117 11.0 Timer1......................................................................................................................................................................................143 12.0 Timer2/3 feature ......................................................................................................................................................................147 13.0 Input Capture............................................................................................................................................................................151 14.0 Output Compare.......................................................................................................................................................................155 15.0 Motor Control PWM Module.....................................................................................................................................................159 16.0 Quadrature Encoder Interface (QEI) Module...........................................................................................................................173 17.0 Serial Peripheral Interface (SPI)...............................................................................................................................................179 18.0 Inter-Integrated Circuit™ (I2C™)..............................................................................................................................................185 19.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................193 20.0 10-bit/12-bit Analog-to-Digital Converter (ADC).......................................................................................................................199 21.0 Special Features......................................................................................................................................................................211 22.0 Instruction Set Summary..........................................................................................................................................................219 23.0 Development Support...............................................................................................................................................................227 24.0 Electrical Characteristics..........................................................................................................................................................231 25.0 High Temperature Electrical Characteristics............................................................................................................................281 26.0 DC and AC Device Characteristics Graphs..............................................................................................................................291 27.0 Packaging Information..............................................................................................................................................................295 Appendix A: Revision History.............................................................................................................................................................309 Index................................................................................................................................................................................................. 321 The Microchip Web Site.....................................................................................................................................................................325 Customer Change Notification Service..............................................................................................................................................325 Customer Support..............................................................................................................................................................................325 Reader Response..............................................................................................................................................................................326 Product Identification System.............................................................................................................................................................327 DS70283K-page 6 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We wel- come your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products © 2007-2012 Microchip Technology Inc. DS70283K-page 7

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33F/PIC24H Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note1: To access the documents listed below, browse to the documentation section of the dsPIC33FJ32MC204 product page of the Microchip web site (www.microchip.com) or select a family reference manual section from the following list. In addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections. • Section 1. “Introduction” (DS70197) • Section 2. “CPU” (DS70204) • Section 3. “Data Memory” (DS70202) • Section 4. “Program Memory” (DS70202) • Section 5. “Flash Programming” (DS70191) • Section 7. “Oscillator” (DS70186) • Section 8. “Reset” (DS70192) • Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196) • Section 10. “I/O Ports” (DS70193) • Section 11. “Timers” (DS70205) • Section 12. “Input Capture” (DS70198) • Section 13. “Output Compare” (DS70209) • Section 14. “Motor Control PWM” (DS70187) • Section 15. “Quadrature Encoder Interface (QEI)” (DS70208) • Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) • Section 17. “UART” (DS70188) • Section 18. “Serial Peripheral Interface (SPI)” (DS70206) • Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195) • Section 23. “CodeGuard™ Security” (DS70199) • Section 25. “Device Configuration” (DS70194) • Section 32. “Interrupts (Part III)” (DS70214) DS70283K-page 8 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 1.0 DEVICE OVERVIEW Note1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices. It is not intended to be a comprehensive refer- ence source. To complement the infor- mation in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. This document contains device-specific information for the following Digital Signal Controller (DSC) devices: • dsPIC33FJ32MC202 • dsPIC33FJ32MC204 • dsPIC33FJ16MC304 The dsPIC33F devices contain extensive Digital Signal Processor (DSP) functionality with a high performance 16-bit microcontroller (MCU) architecture. Figure1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. Table1-1 lists the functions of the various pins shown in the pinout diagrams. © 2007-2012 Microchip Technology Inc. DS70283K-page 9

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 1-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus Interrupt X Data Bus PORTA Controller 16 8 16 16 16 Data Latch Data Latch 23 PCU PCH PCL X RAM Y RAM PORTB 23 Program Counter Stack Loop Address Address Control Control Latch Latch Logic Logic 16 23 16 16 PORTC Address Generator Units Address Latch Program Memory Remapp a ble EA MUX Pins Data Latch ROM Latch 24 16 16 a at Instruction D Decode and al Control Instruction Reg er Lit 16 Control Signals to Various Blocks DSP Engine 16 x 16 OSC2/CLKO Timing Power-up W Register Array OSC1/CLKI Generation Timer Divide Support 16 Oscillator FRC/LPRC Start-up Timer Oscillators Power-on Reset 16-bit ALU Precision Band Gap Watchdog Reference Timer 16 Brown-out Voltage Reset Regulator VCAP VDD, VSS MCLR Timers UART1 SPI1 ADC1 OC/ PWM 1-3 PWM1-2 2 Ch IC1,2,7,8 CNx I2C1 QEI PWM 6 Ch Note: Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins and features present on each device. DS70283K-page 10 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name PPS Description Type Type AN0-AN8 I Analog No Analog input channels. CLKI I ST/CMOS No External clock source input. Always associated with OSC1 pin function. CLKO O — No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. OSC1 I ST/CMOS No Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. OSC2 I/O — No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. SOSCI I ST/CMOS No 32.768 kHz low-power oscillator crystal input; CMOS otherwise. SOSCO O — No 32.768 kHz low-power oscillator crystal output. CN0-CN30 I ST No Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. IC1-IC2 I ST Yes Capture inputs 1/2. IC7-IC8 I ST Yes Capture inputs 7/8. OCFA I ST Yes Compare Fault A input (for Compare Channels 1 and 2). OC1-OC2 O — Yes Compare outputs 1 through 2. INT0 I ST No External interrupt 0. INT1 I ST Yes External interrupt 1. INT2 I ST Yes External interrupt 2. RA0-RA4 I/O ST No PORTA is a bidirectional I/O port. RA7-RA10 No RB0-RB15 I/O ST No PORTB is a bidirectional I/O port. RC0-RC9 I/O ST No PORTC is a bidirectional I/O port. T1CK I ST No Timer1 external clock input. T2CK I ST Yes Timer2 external clock input. T3CK I ST Yes Timer3 external clock input. U1CTS I ST Yes UART1 clear to send. U1RTS O — Yes UART1 ready to send. U1RX I ST Yes UART1 receive. U1TX O — Yes UART1 transmit. SCK1 I/O ST Yes Synchronous serial clock input/output for SPI1. SDI1 I ST Yes SPI1 data in. SDO1 O — Yes SPI1 data out. SS1 I/O ST Yes SPI1 slave synchronization or frame pulse I/O. SCL1 I/O ST No Synchronous serial clock input/output for I2C1. SDA1 I/O ST No Synchronous serial data input/output for I2C1. ASCL1 I/O ST No Alternate synchronous serial clock input/output for I2C1. ASDA1 I/O ST No Alternate synchronous serial data input/output for I2C1. TMS I ST No JTAG Test mode select pin. TCK I ST No JTAG test clock input pin. TDI I ST No JTAG test data input pin. TDO O — No JTAG test data output pin. Legend: CMOS = CMOS compatible input or output; Analog = Analog input; P = Power ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input PPS = Peripheral Pin Select © 2007-2012 Microchip Technology Inc. DS70283K-page 11

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name PPS Description Type Type INDX I ST Yes Quadrature Encoder Index Pulse input. QEA I ST Yes Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. QEB I ST Yes Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. UPDN O CMOS Yes Position Up/Down Counter Direction State. FLTA1 I ST Yes PWM1 Fault A input. PWM1L1 O — No PWM1 Low output 1. PWM1H1 O — No PWM1 High output 1. PWM1L2 O — No PWM1 Low output 2. PWM1H2 O — No PWM1 High output 2. PWM1L3 O — No PWM1 Low output 3. PWM1H3 O — No PWM1 High output 3. FLTA2 I ST Yes PWM2 Fault A input. PWM2L1 O — No PWM2 Low output 1. PWM2H1 O — No PWM2 High output 1. PGED1 I/O ST No Data I/O pin for programming/debugging communication channel 1. PGEC1 I ST No Clock input pin for programming/debugging communication channel 1. PGED2 I/O ST No Data I/O pin for programming/debugging communication channel 2. PGEC2 I ST No Clock input pin for programming/debugging communication channel 2. PGED3 I/O ST No Data I/O pin for programming/debugging communication channel 3. PGEC3 I ST No Clock input pin for programming/debugging communication channel 3. MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device. AVDD P P No Positive supply for analog modules. This pin must be connected at all times. AVSS P P No Ground reference for analog modules. VDD P — No Positive supply for peripheral logic and I/O pins. VCAP P — No CPU logic filter capacitor connection. VSS P — No Ground reference for logic and I/O pins. VREF+ I Analog No Analog voltage reference (high) input. VREF- I Analog No Analog voltage reference (low) input. Legend: CMOS = CMOS compatible input or output; Analog = Analog input; P = Power ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input PPS = Peripheral Pin Select DS70283K-page 12 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors STARTED WITH 16-BIT The use of decoupling capacitors on every pair of DIGITAL SIGNAL power supply pins, such as VDD, VSS, AVDD and CONTROLLERS AVSS is required. Consider the following criteria when using decoupling Note1: This data sheet summarizes the features capacitors: of the dsPIC33FJ32MC202/204 and • Value and type of capacitor: Recommendation dsPIC33FJ16MC304 family of devices. It of 0.1 µF (100 nF), 10-20V. This capacitor should is not intended to be a comprehensive be a low-ESR and have a resonance frequency in reference source. To complement the the range of 20MHz and higher. It is information in this data sheet, refer to the recommended that ceramic capacitors be used. “dsPIC33F/PIC24H Family Reference Manual”, which is available from the • Placement on the printed circuit board: The Microchip web site (www.microchip.com). decoupling capacitors should be placed as close to the pins as possible. It is recommended to 2: Some registers and associated bits place the capacitors on the same side of the described in this section may not be board as the device. If space is constricted, the available on all devices. Refer to capacitor can be placed on another layer on the Section4.0 “Memory Organization” in PCB using a via; however, ensure that the trace this data sheet for device-specific register length from the pin to the capacitor is within and bit information. one-quarter inch (6mm) in length. • Handling high frequency noise: If the board is 2.1 Basic Connection Requirements experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor Getting started with the dsPIC33FJ32MC202/204 and in parallel to the above described decoupling dsPIC33FJ16MC304 family of 16-bit Digital Signal capacitor. The value of the second capacitor can Controllers (DSCs) requires attention to a minimal set be in the range of 0.01µF to 0.001µF. Place this of device pin connections before proceeding with second capacitor next to the primary decoupling development. The following is a list of pin names, which capacitor. In high-speed circuit designs, consider must always be connected: implementing a decade pair of capacitances as • All VDD and VSS pins close to the power and ground pins as possible. (see Section2.2 “Decoupling Capacitors”) For example, 0.1 µF in parallel with 0.001 µF. • All AVDD and AVSS pins (even if the ADC module is • Maximizing performance: On the board layout not used) from the power supply circuit, run the power and (see Section2.2 “Decoupling Capacitors”) return traces to the decoupling capacitors first, • VCAP and then to the device pins. This ensures that the (see Section2.3 “CPU Logic Filter Capacitor decoupling capacitors are first in the power chain. Connection (VCAP)”) Equally important is to keep the trace length • MCLR pin between the capacitor and the power pins to a (see Section2.4 “Master Clear (MCLR) Pin”) minimum thereby reducing PCB track inductance. • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section2.6 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of the ADC voltage reference source. © 2007-2012 Microchip Technology Inc. DS70283K-page 13

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 2-1: RECOMMENDED The placement of this capacitor should be close to the MINIMUM CONNECTION VCAP. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section21.2 0.1 µF “On-Chip Voltage Regulator” for details. VDD 10 µF Ceramic Tantalum 2.4 Master Clear (MCLR) Pin R CAP VDD VSS The MCLR pin provides for two specific device R1 V functions: MCLR • Device Reset C • Device programming and debugging dsPIC33F During device programming and debugging, the VSS VDD resistance and capacitance that can be added to the pin must be considered. Device programmers and 0.1 µF VDD D S VSS 0.1 µF debuggers drive the MCLR pin. Consequently, Ceramic VD VS DD SS Ceramic specific voltage levels (VIH and VIL) and fast signal A A V V transitions must not be adversely affected. Therefore, 0.1 µF 0.1 µF specific values of R and C will need to be adjusted Ceramic Ceramic based on the application and PCB requirements. L1(1) For example, as shown in Figure2-2, it is recommended that capacitor C is isolated from the Note 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and MCLR pin during programming and debugging AVDD to improve ADC noise rejection. The inductor operations. impedance should be less than 1Ω and the inductor capacity greater than 10 mA. Place the components shown in Figure2-2 within one-quarter inch (6mm) from the MCLR pin. Where: FCNV f = -------------- (i.e., ADC conversion rate/2) FIGURE 2-2: EXAMPLE OF MCLR PIN 2 CONNECTIONS 1 f = ----------------------- (2π LC) VDD ⎛ 1 ⎞2 L = ⎝---------------------⎠ (2πf C) R(1) R1(2) MCLR 2.2.1 TANK CAPACITORS JP dsPIC33F On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor C for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that con- Note 1: R≤ 10kΩ is recommended. A suggested nects the power supply source to the device, and the starting value is 10kΩ. Ensure that the MCLR maximum current drawn by the device in the applica- pin VIH and VIL specifications are met. tion. In other words, select the tank capacitor so that it 2: R1 ≤ 470W will limit any current flowing into meets the acceptable voltage sag at the device. Typical MCLR from the external capacitor C, in the values range from 4.7µF to 47µF. event of MCLR pin breakdown, due to Elec- trostatic Discharge (ESD) or Electrical 2.3 CPU Logic Filter Capacitor Overstress (EOS). Ensure that the MCLR pin Connection (VCAP) VIH and VIL specifications are met. A low-ESR (<5 Ohms) capacitor is required on the VCAP pin, which is used to stabilize the voltage regulator output voltage. The VCAP pin must not be connected to VDD, and must have a capacitor between 4.7µF and 10 µF, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section24.0 “Electrical Characteristics” for additional information. DS70283K-page 14 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 2.5 ICSP Pins 2.6 External Oscillator Pins The PGECx and PGEDx pins are used for In-Circuit Many DSCs have options for at least two oscillators: a Serial Programming (ICSP) and debugging purposes. high-frequency primary oscillator and a low-frequency It is recommended to keep the trace length between secondary oscillator (refer to Section8.0 “Oscillator the ICSP connector and the ICSP pins on the device as Configuration” for details). short as possible. If the ICSP connector is expected to The oscillator circuit should be placed on the same experience an ESD event, a series resistor is side of the board as the device. Also, place the recommended, with the value in the range of a few tens oscillator circuit close to the respective oscillator pins, of Ohms, not to exceed 100 Ohms. not exceeding one-half inch (12mm) distance Pull-up resistors, series diodes and capacitors on the between them. The load capacitors should be placed PGECx and PGEDx pins are not recommended as they next to the oscillator itself, on the same side of the will interfere with the programmer/debugger communi- board. Use a grounded copper pour around the cations to the device. If such discrete components are oscillator circuit to isolate them from surrounding an application requirement, they should be removed circuits. The grounded copper pour should be routed from the circuit during programming and debugging. directly to the MCU ground. Do not run any signal Alternatively, refer to the AC/DC characteristics and traces or power traces inside the ground pour. Also, if timing requirements information in the respective using a two-sided board, avoid any traces on the device Flash programming specification for information other side of the board where the crystal is placed. A on capacitive loading limits and pin input voltage high suggested layout is shown in Figure2-3. (VIH) and input low (VIL) requirements. FIGURE 2-3: SUGGESTED PLACEMENT Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device OF THE OSCILLATOR matches the physical connections for the ICSP to CIRCUIT MPLAB® ICD 3 or MPLAB REAL ICE™ in-circuit emu- lator. Main Oscillator For more information on MPLAB ICD 3 or MPLAB 13 REAL ICE™ in-circuit emulator connection Guard Ring 14 requirements, refer to the following documents that are available on the Microchip web site. 15 Guard Trace • “Using MPLAB® ICD 3” (poster) DS51765 16 • “MPLAB® ICD 3 Design Advisory” DS51764 Secondary 17 • “MPLAB® REAL ICE™ In-Circuit Emulator User’s Oscillator 18 Guide” DS51616 19 • “Using MPLAB® REAL ICE™ In-Circuit Emulator” 20 (poster) DS51749 © 2007-2012 Microchip Technology Inc. DS70283K-page 15

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to ≤ 8 MHz for start-up with PLL enabled. This means that if the external oscillator frequency is outside this range, the application must start-up in FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed. Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration word. 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, MPLAB ICD 3 or MPLAB REAL ICE™ in-circuit emulator is selected as a debugger, it auto- matically initializes all of the A/D input pins (ANx) as “digital” pins, by setting all bits in the AD1PCFGL regis- ter. The bits in the registers that correspond to the A/D pins that are initialized by MPLAB ICD 3 or MPLAB REAL ICE™ in-circuit emulator, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the AD1PCFGL register during initialization of the ADC module. When MPLAB ICD 3 or MPLAB REAL ICE™ in-circuit emulator is used as a programmer, the user application firmware must correctly configure the AD1PCFGL register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect a 1k to 10k resistor between VSS and the unused pins. DS70283K-page 16 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 3.0 CPU 3.1 Data Addressing Overview The data space can be addressed as 32K words or Note1: This data sheet summarizes the features 64Kbytes and is split into two blocks, referred to as X of the dsPIC33FJ32MC202/204 and and Y data memory. Each memory block has its own dsPIC33FJ16MC304 family of devices. It independent Address Generation Unit (AGU). The is not intended to be a comprehensive MCU class of instructions operates solely through the reference source. To complement the X memory AGU, which accesses the entire memory information in this data sheet, refer to map as one linear data space. Certain DSP instructions Section 2. “CPU” (DS70204) of the operate through the X and Y AGUs to support dual “dsPIC33F/PIC24H Family Reference operand reads, which splits the data address space Manual”, which is available from the into two parts. The X and Y data space boundary is Microchip web site (www.microchip.com). device-specific. 2: Some registers and associated bits Overhead-free circular buffers (Modulo Addressing described in this section may not be mode) are supported in both X and Y address spaces. available on all devices. Refer to The Modulo Addressing removes the software Section4.0 “Memory Organization” in boundary checking overhead for DSP algorithms. this data sheet for device-specific register Furthermore, the X AGU circular addressing can be and bit information. used with any of the MCU class of instructions. The X The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 AGU also supports Bit-Reversed Addressing to greatly CPU module has a 16-bit (data) modified Harvard simplify input or output data reordering for radix-2 FFT architecture with an enhanced instruction set, including algorithms. significant support for DSP. The CPU has a 24-bit The upper 32 Kbytes of the data space memory map instruction word with a variable length opcode field. The can optionally be mapped into program space at any Program Counter (PC) is 23bits wide and addresses up 16K program word boundary defined by the 8-bit to 4M x 24 bits of user program memory space. The Program Space Visibility Page register (PSVPAG). The actual amount of program memory implemented varies program-to-data-space mapping feature lets any by device. A single-cycle instruction prefetch mechanism instruction access program space as if it were data is used to help maintain throughput and provides space. predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the 3.2 DSP Engine Overview program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop The DSP engine features a high-speed 17-bit by 17-bit constructs are supported using the DO and REPEAT multiplier, a 40-bit ALU, two 40-bit saturating instructions, both of which are interruptible at any point. accumulators and a 40-bit bidirectional barrel shifter. The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 The barrel shifter is capable of shifting a 40-bit value up devices have sixteen, 16-bit working registers in the to 16 bits right or left, in a single cycle. The DSP programmer’s model. Each of the working registers can instructions operate seamlessly with all other serve as a data, address or address offset register. The instructions and have been designed for optimal 16th working register (W15) operates as a software Stack real-time performance. The MAC instruction and other Pointer (SP) for interrupts and calls. associated instructions can concurrently fetch two data operands from memory while multiplying two W There are two classes of instruction in the registers and accumulating and optionally saturating dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 the result in the same cycle. This instruction devices: MCU and DSP. These two instruction classes functionality requires that the RAM data space be split are seamlessly integrated into a single CPU. The for these instructions and linear for all others. Data instruction set includes many addressing modes and is space partitioning is achieved in a transparent and designed for optimum C compiler efficiency. For most flexible manner through dedicating certain working instructions, the dsPIC33FJ32MC202/204 and registers to each address space. dsPIC33FJ16MC304 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A+B=C operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure3-1, and the programmer’s model for the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 is shown in Figure3-2. © 2007-2012 Microchip Technology Inc. DS70283K-page 17

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 3.3 Special MCU Features The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 supports 16/16 and 32/16 divide operations, both The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 fractional and integer. All divide instructions are iterative features a 17-bit by 17-bit single-cycle multiplier that is operations. They must be executed within a REPEAT loop, shared by both the MCU ALU and DSP engine. The resulting in a total execution time of 19 instruction cycles. multiplier can perform signed, unsigned and mixed-sign The divide operation can be interrupted during any of multiplication. Using a 17-bit by 17-bit multiplier for 16-bit those 19cycles without loss of data. by 16-bit multiplication not only allows you to perform A 40-bit barrel shifter is used to perform up to a 16-bit mixed-sign multiplication, it also achieves accurate results left or right shift in a single cycle. The barrel shifter can for special operations, such as (-1.0) x (-1.0). be used by both MCU and DSP instructions. FIGURE 3-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus 16 Interrupt X Data Bus Controller 8 16 16 16 16 Data Latch Data Latch 23 PCU PCH PCL X RAM Y RAM 16 23 Program Counter Stack Loop Address Address Control Control Latch Latch Logic Logic 23 16 16 16 16 Address Latch Address Generator Units Program Memory 16 EA MUX Data Latch ROM Latch 24 16 16 24 a at Instruction D Decode and al Control Instruction Reg er Lit Control Signals to Various Blocks 16 DSP Engine 16 16 x 16 W Register Array Divide Support 16 16 16-bit ALU 16 To Peripheral Modules DS70283K-page 18 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 3-2: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 DSP Operand W5 Registers W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register AD39 AD31 AD15 AD0 DSP ACCA Accumulators ACCB PC22 PC0 0 Program Counter 7 0 TBLPAG Data Table Page Address 7 0 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address 22 DOEND DO Loop End Address 15 0 CORCON Core Configuration Register OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRH SRL © 2007-2012 Microchip Technology Inc. DS70283K-page 19

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 3.4 CPU Resources Many useful resources are provided on the main prod- uct page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334 3.4.1 KEY RESOURCES • Section 2. “CPU” (DS70204) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70283K-page 20 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 3.5 CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA(1) SB(1) OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL<2:0>(2) RA N OV Z C bit 7 bit 0 Legend: C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OA: Accumulator A Overflow Status bit 1 = Accumulator A overflowed 0 = Accumulator A has not overflowed bit 14 OB: Accumulator B Overflow Status bit 1 = Accumulator B overflowed 0 = Accumulator B has not overflowed bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit 1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated Note: This bit may be read or cleared (not set). Clearing this bit will clear SA and SB. bit 9 DA: DO Loop Active bit 1 = DO loop in progress 0 = DO loop not in progress bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred Note 1: This bit can be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). © 2007-2012 Microchip Technology Inc. DS70283K-page 21

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 1 Z: MCU ALU Zero bit 1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: This bit can be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). DS70283K-page 22 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT(1) DL<2:0> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 15-13 Unimplemented: Read as ‘0’ bit 12 US: DSP Multiply Unsigned/Signed Control bit 1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed bit 11 EDT: Early DO Loop Termination Control bit(1) 1 = Terminate executing DO loop at end of current loop iteration 0 = No effect bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits 111 = 7 DO loops active • • • 001 = 1 DO loop active 000 = 0 DO loops active bit 7 SATA: ACCA Saturation Enable bit 1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled bit 6 SATB: ACCB Saturation Enable bit 1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation enabled 0 = Data space write saturation disabled bit 4 ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space bit 1 RND: Rounding Mode Select bit 1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled bit 0 IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Note 1: This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2007-2012 Microchip Technology Inc. DS70283K-page 23

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 3.6 Arithmetic Logic Unit (ALU) 3.7 DSP Engine The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 The DSP engine consists of a high-speed 17-bit x ALU is 16 bits wide and is capable of addition, subtraction, 17-bit multiplier, a barrel shifter and a 40-bit bit shifts and logic operations. Unless otherwise adder/subtracter (with two target accumulators, round mentioned, arithmetic operations are 2’s complement in and saturation logic). nature. Depending on the operation, the ALU can affect The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 the values of the Carry (C), Zero (Z), Negative (N), is a single-cycle instruction flow architecture; therefore, Overflow (OV) and Digit Carry (DC) Status bits in the SR concurrent operation of the DSP engine with MCU register. The C and DC Status bits operate as Borrow and instruction flow is not possible. However, some MCU ALU Digit Borrow bits, respectively, for subtraction operations. and DSP engine resources can be used concurrently by The ALU can perform 8-bit or 16-bit operations, the same instruction (e.g., ED, EDAC). depending on the mode of the instruction that is used. The DSP engine can also perform inherent accumula- Data for the ALU operation can come from the W tor-to-accumulator operations that require no additional register array or data memory, depending on the data. These instructions are ADD, SUB and NEG. addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array The DSP engine has options selected through bits in or a data memory location. the CPU Core Control register (CORCON), as listed below: Refer to the “16-bit MCU and DSC Programmer’s Ref- erence Manual” (DS70157) for information on the SR • Fractional or integer DSP multiply (IF) bits affected by each instruction. • Signed or unsigned DSP multiply (US) • Conventional or convergent rounding (RND) The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 • Automatic saturation on/off for ACCA (SATA) CPU incorporates hardware support for both • Automatic saturation on/off for ACCB (SATB) multiplication and division. This includes a dedicated • Automatic saturation on/off for writes to data hardware multiplier and support hardware for memory (SATDW) 16-bit-divisor division. • Accumulator Saturation mode selection (ACCSAT) 3.6.1 MULTIPLIER A block diagram of the DSP engine is shown in Figure3-3. Using the high-speed 17-bit x 17-bit multiplier of the DSP engine, the ALU supports unsigned, signed or TABLE 3-1: DSP INSTRUCTIONS mixed-sign operation in several MCU multiplication SUMMARY modes: • 16-bit x 16-bit signed Algebraic ACC Write Instruction • 16-bit x 16-bit unsigned Operation Back • 16-bit signed x 5-bit (literal) unsigned CLR A = 0 Yes • 16-bit unsigned x 16-bit unsigned ED A = (x - y)2 No • 16-bit unsigned x 5-bit (literal) unsigned • 16-bit unsigned x 16-bit signed EDAC A = A + (x – y)2 No • 8-bit unsigned x 8-bit unsigned MAC A = A + (x * y) Yes MAC A = A + x2 No 3.6.2 DIVIDER MOVSAC No change in A Yes The divide block supports 32-bit/16-bit and 16-bit/16-bit MPY A = x• y No signed and unsigned integer divide operations with the MPY A = x2 No following data sizes: MPY.N A = – x•y No 1. 32-bit signed/16-bit signed divide MSC A = A – x•y Yes 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. DS70283K-page 24 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM S 40 40-bit Accumulator A a 40 Round t 16 40-bit Accumulator B u Logic r Carry/Borrow Out a Saturate t e Adder Carry/Borrow In Negate 40 40 40 Barrel 16 Shifter 40 us B a Sign-Extend at D X s u B a 32 16 at Zero Backfill D Y 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array © 2007-2012 Microchip Technology Inc. DS70283K-page 25

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 3.7.1 MULTIPLIER 3.7.2.1 Adder/Subtracter, Overflow and Saturation The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a The adder/subtracter is a 40-bit adder with an optional scaler to support either 1.31 fractional (Q31) or 32-bit zero input into one side, and either true or complement integer results. Unsigned operands are zero-extended data into the other input. into the 17th bit of the multiplier input value. Signed • In the case of addition, the Carry/Borrow input is operands are sign-extended into the 17th bit of the active-high and the other input is true data (not multiplier input value. The output of the 17-bit x 17-bit complemented). multiplier/scaler is a 33-bit value that is sign-extended • In the case of subtraction, the Carry/Borrow input to 40 bits. Integer data is inherently represented as a is active-low and the other input is complemented. signed 2’s complement value, where the Most Significant bit (MSb) is defined as a sign bit. The range The adder/subtracter generates Overflow Status bits, of an N-bit 2’s complement integer is -2N-1 to 2N-1 - 1. SA/SB and OA/OB, which are latched and reflected in the STATUS register: • For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including 0. • Overflow from bit 39: this is a catastrophic • For a 32-bit integer, the data range is overflow in which the sign of the accumulator is -2,147,483,648 (0x80000000) to 2,147,483,647 destroyed. (0x7FFF FFFF). • Overflow into guard bits 32 through 39: this is a recoverable overflow. This bit is set whenever all When the multiplier is configured for fractional multipli- the guard bits are not identical to each other. cation, the data is represented as a 2’s complement fraction, where the MSb is defined as a sign bit and the The adder has an additional saturation block that radix point is implied to lie just after the sign bit (QX controls accumulator data saturation, if selected. It format). The range of an N-bit 2’s complement fraction uses the result of the adder, the Overflow Status bits with this implied radix point is -1.0 to (1 - 21-N). For a described previously and the SAT<A:B> 16-bit fraction, the Q15 data range is -1.0 (0x8000) to (CORCON<7:6>) and ACCSAT (CORCON<4>) mode 0.999969482 (0x7FFF) including 0 and has a precision control bits to determine when and to what value to of 3.01518x10-5. In Fractional mode, the 16 x 16 multi- saturate. ply operation generates a 1.31 product that has a pre- Six STATUS register bits support saturation and cision of 4.65661 x 10-10. overflow: The same multiplier is used to support the MCU multi- • OA: ACCA overflowed into guard bits ply instructions, which include integer 16-bit signed, • OB: ACCB overflowed into guard bits unsigned and mixed sign multiply operations. • SA: ACCA saturated (bit 31 overflow and The MUL instruction can be directed to use byte or saturation) word-sized operands. Byte operands will direct a 16-bit or result, and word operands will direct a 32-bit result to ACCA overflowed into guard bits and saturated the specified register(s) in the W array. (bit 39 overflow and saturation) 3.7.2 DATA ACCUMULATORS AND • SB: ACCB saturated (bit 31 overflow and saturation) ADDER/SUBTRACTER or The data accumulator consists of a 40-bit ACCB overflowed into guard bits and saturated adder/subtracter with automatic sign extension logic. It (bit 39 overflow and saturation) can select one of two accumulators (A or B) as its • OAB: Logical OR of OA and OB pre-accumulation source and post-accumulation • SAB: Logical OR of SA and SB destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled The OA and OB bits are modified each time data using the barrel shifter prior to accumulation. passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits(bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding Overflow Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1 register are set (refer to Section7.0 “Interrupt Controller”). This allows the user application to take immediate action, for example, to correct system gain. DS70283K-page 26 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 The SA and SB bits are modified each time data into data space memory. The write is performed across passes through the adder/subtracter, but can only be the X bus into combined X and Y address space. The cleared by the user application. When set, they indicate following addressing modes are supported: that the accumulator has overflowed its maximum • W13, Register Direct: range (bit 31 for 32-bit saturation or bit 39 for 40-bit The rounded contents of the non-target saturation) and will be saturated (if saturation is accumulator are written into W13 as a enabled). When saturation is not enabled, SA and SB 1.15fraction. default to bit 39 overflow and thus indicate that a • [W13] + = 2, Register Indirect with Post-Increment: catastrophic overflow has occurred. If the COVTE bit in The rounded contents of the non-target the INTCON1 register is set, SA and SB bits will gener- accumulator are written into the address pointed ate an arithmetic warning trap when saturation is to by W13 as a 1.15 fraction. W13 is then disabled. incremented by 2 (for a word write). The Overflow and Saturation Status bits can optionally be viewed in the STATUS Register (SR) as the logical 3.7.3.1 Round Logic OR of OA and OB (in bit OAB) and the logical OR of SA The round logic is a combinational block that performs and SB (in bit SAB). Programmers can check one bit in a conventional (biased) or convergent (unbiased) the STATUS register to determine if either accumulator round function during an accumulator write (store). The has overflowed, or one bit to determine if either Round mode is determined by the state of the RND bit accumulator has saturated. This is useful for complex in the CORCON register. It generates a 16-bit, 1.15 number arithmetic, which typically uses both data value that is passed to the data space write accumulators. saturation logic. If rounding is not indicated by the The device supports three Saturation and Overflow instruction, a truncated 1.15 data value is stored and modes: the least significant word (lsw) is simply discarded. • Bit 39 Overflow and Saturation: Conventional rounding zero-extends bit 15 of the When bit 39 overflow and saturation occurs, the accumulator and adds it to the ACCxH word (bits 16 saturation logic loads the maximally positive 9.31 through 31 of the accumulator). (0x7FFFFFFFFF) or maximally negative 9.31 value • If the ACCxL word (bits0 through 15 of the (0x8000000000) into the target accumulator. The accumulator) is between 0x8000 and 0xFFFF SA or SB bit is set and remains set until cleared by (0x8000 included), ACCxH is incremented. the user application. This condition is referred to as • If ACCxL is between 0x0000 and 0x7FFF, ACCxH ‘super saturation’ and provides protection against is left unchanged. erroneous data or unexpected algorithm problems (such as gain calculations). A consequence of this algorithm is that over a • Bit 31 Overflow and Saturation: succession of random rounding operations, the value When bit 31 overflow and saturation occurs, the tends to be biased slightly positive. saturation logic then loads the maximally positive Convergent (or unbiased) rounding operates in the 1.31 value (0x007FFFFFFF) or maximally nega- same manner as conventional rounding, except when tive 1.31 value (0x0080000000) into the target ACCxL equals 0x8000. In this case, the Least accumulator. The SA or SB bit is set and remains Significant bit(bit16 of the accumulator) of ACCxH is set until cleared by the user application. When examined: this Saturation mode is in effect, the guard bits are • If it is ‘1’, ACCxH is incremented. not used, so the OA, OB or OAB bits are never • If it is ‘0’, ACCxH is not modified. set. Assuming that bit 16 is effectively random in nature, • Bit 39 Catastrophic Overflow: this scheme removes any rounding bias that may The bit 39 Overflow Status bit from the adder is accumulate. used to set the SA or SB bit, which remains set until cleared by the user application. No saturation The SAC and SAC.R instructions store either a operation is performed, and the accumulator is truncated (SAC), or rounded (SAC.R) version of the allowed to overflow, destroying its sign. If the contents of the target accumulator to data memory via COVTE bit in the INTCON1 register is set, a the X bus, subject to data saturation (see catastrophic overflow can initiate a trap exception. Section3.7.3.2 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator 3.7.3 ACCUMULATOR ‘WRITE BACK’ write-back operation functions in the same manner, The MAC class of instructions (with the exception of addressing combined MCU (X and Y) data space MPY, MPY.N, ED and EDAC) can optionally write a though the X bus. For this class of instructions, the data rounded version of the high word (bits 31 through 16) is always subject to rounding. of the accumulator that is not targeted by the instruction © 2007-2012 Microchip Technology Inc. DS70283K-page 27

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 3.7.3.2 Data Space Write Saturation 3.7.4 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data The barrel shifter can perform up to 16-bit arithmetic or space can also be saturated, but without affecting the logic right shifts, or up to 16-bit left shifts in a single contents of the source accumulator. The data space cycle. The source can be either of the two DSP accu- write saturation logic block accepts a 16-bit, 1.15 frac- mulators or the X bus (to support multi-bit shifts of tional value from the round logic block as its input, register or memory data). together with overflow status from the original source The shifter requires a signed binary value to determine (accumulator) and the 16-bit round adder. These inputs both the magnitude (number of bits) and direction of the are combined and used to select the appropriate 1.15 shift operation. A positive value shifts the operand right. fractional value as output to write to data space A negative value shifts the operand left. A value of ‘0’ memory. does not modify the operand. If the SATDW bit in the CORCON register is set, data The barrel shifter is 40 bits wide, thereby obtaining a (after rounding or truncation) is tested for overflow and 40-bit result for DSP shift operations and a 16-bit result adjusted accordingly: for MCU shift operations. Data from the X bus is pre- • For input data greater than 0x007FFF, data writ- sented to the barrel shifter between bit positions 16 and ten to memory is forced to the maximum positive 31 for right shifts, and between bit positions 0 and 16 1.15 value, 0x7FFF. for left shifts. • For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. DS70283K-page 28 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.0 MEMORY ORGANIZATION 4.1 Program Address Space The program address memory space of the Note: This data sheet summarizes the features dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 of the dsPIC33FJ32MC202/204 and devices is 4M instructions. The space is addressable dsPIC33FJ16MC304 family of devices. It by a 24-bit value derived either from the 23-bit Program is not intended to be a comprehensive Counter (PC) during program execution, or from table reference source. To complement the operation or data space remapping as described in information in this data sheet, refer to Section4.8 “Interfacing Program and Data Memory Section 4. “Program Memory” Spaces”. (DS70202) of the “dsPIC33F/PIC24H Family Reference Manual”, which is avail- User application access to the program memory space able from the Microchip web site is restricted to the lower half of the address range (www.microchip.com). (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 permit access to the Configuration bits and Device ID architecture features separate program and data memory sections of the configuration memory space. spaces and buses. This architecture also allows the direct The memory maps for the dsPIC33FJ32MC202/204 access of program memory from the data space during and dsPIC33FJ16MC304 devices are shown in code execution. Figure4-1. FIGURE 4-1: PROGRAM MEMORY MAPS FOR dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 DEVICES dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 GOTO Instruction 0x000000 GOTO Instruction 0x000000 0x000002 0x000002 Reset Address Reset Address 0x000004 0x000004 Interrupt Vector Table Interrupt Vector Table 0x0000FE 0x0000FE Reserved 0x000100 Reserved 0x000100 0x000104 0x000104 Alternate Vector Table Alternate Vector Table 0x0001FE 0x0001FE 0x000200 0x000200 User Program User Program Flash Memory Flash Memory e e c (11264 instructions) c (5632 instructions) pa 0x0057FE pa 0x002BFE S 0x005800 S 0x002C00 y y or or m m e e M M er Unimplemented er Unimplemented Us (Read ‘0’s) Us (Read ‘0’s) 0x7FFFFE 0x7FFFFE 0x800000 0x800000 Reserved Reserved e e c c a a p p S S y 0xF7FFFE y 0xF7FFFE or Device Configuration 0xF80000 or Device Configuration 0xF80000 m m e Registers 0xF80017 e Registers 0xF80017 M 0xF80018 M 0xF80018 n n o o ati ati ur ur g g nfi Reserved nfi Reserved o o C C 0xFEFFFE 0xFEFFFE 0xFF0000 0xFF0000 DEVID (2) DEVID (2) 0xFFFFFE 0xFFFFFE © 2007-2012 Microchip Technology Inc. DS70283K-page 29

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.1.1 PROGRAM MEMORY 4.1.2 INTERRUPT AND TRAP VECTORS ORGANIZATION All dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 The program memory space is organized in devices reserve the addresses between 0x00000 and word-addressable blocks. Although it is treated as 0x000200 for hard-coded program execution vectors. 24bits wide, it is more appropriate to think of each A hardware Reset vector is provided to redirect code address of the program memory as a lower and upper execution from the default value of the PC on device word, with the upper byte of the upper word being Reset to the actual start of code. A GOTO instruction is unimplemented. The lower word always has an even programmed by the user application at 0x000000, with address, while the upper word has an odd address the actual address for the start of code at 0x000002. (Figure4-2). dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Program memory addresses are always word-aligned devices also have two interrupt vector tables, located on the lower word, and addresses are incremented or from 0x000004 to 0x0000FF and 0x000100 to decremented by two during code execution. This 0x0001FF. These vector tables allow each of the arrangement provides compatibility with data memory device interrupt sources to be handled by separate space addressing and makes data in the program Interrupt Service Routines (ISRs). A more detailed memory space accessible. discussion of the interrupt vector tables is provided in Section7.1 “Interrupt Vector Table”. FIGURE 4-2: PROGRAM MEMORY ORGANIZATION msw most significant word least significant word PC Address Address (lsw Address) 23 16 8 0 0x000001 00000000 0x000000 0x000003 00000000 0x000002 0x000005 00000000 0x000004 0x000007 00000000 0x000006 Program Memory Instruction Width ‘Phantom’ Byte (read as ‘0’) DS70283K-page 30 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.2 Data Address Space All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 care must be taken when mixing byte and word CPU has a separate 16-bit-wide data memory space. The operations, or translating from 8-bit MCU code. If a data space is accessed using separate Address misaligned read or write is attempted, an address error Generation Units (AGUs) for read and write operations. trap is generated. If the error occurred on a read, the The data memory maps is shown in Figure4-3. instruction underway is completed. If the error occurred All Effective Addresses (EAs) in the data memory space on a write, the instruction is executed but the write does are 16 bits wide and point to bytes within the data space. not occur. In either case, a trap is then executed, This arrangement gives a data space address range of allowing the system and/or user application to examine 64Kbytes or 32Kwords. The lower half of the data the machine state prior to execution of the address memory space (that is, when EA<15> = 0) is used for Fault. implemented memory addresses, while the upper half All byte loads into any W register are loaded into the (EA<15> = 1) is reserved for the Program Space Least Significant Byte. The Most Significant Byte is not Visibility area (see Section4.8.3 “Reading Data from modified. Program Memory Using Program Space Visibility”). A sign-extend instruction (SE) is provided to allow user dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 applications to translate 8-bit signed data to 16-bit devices implement up to 2Kbytes of data memory. signed values. Alternatively, for 16-bit unsigned data, Should an EA point to a location outside of this area, an user applications can clear the MSB of any W register all-zero word or byte will be returned. by executing a zero-extend (ZE) instruction on the appropriate address. 4.2.1 DATA SPACE WIDTH The data memory space is organized in byte 4.2.3 SFR SPACE addressable, 16-bit wide blocks. Data is aligned in data The first 2Kbytes of the Near Data Space, from 0x0000 memory and registers as 16-bit words, but all data to 0x07FF, is primarily occupied by Special Function space EAs resolve to bytes. The Least Significant Registers (SFRs). These are used by the Bytes (LSBs) of each word have even addresses, while dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 the Most Significant Bytes (MSBs) have odd core and peripheral modules for controlling the addresses. operation of the device. 4.2.2 DATA MEMORY ORGANIZATION SFRs are distributed among the modules that they AND ALIGNMENT control, and are generally grouped together by module. Much of the SFR space contains unused addresses; To maintain backward compatibility with PIC® MCU these are read as ‘0’. devices and improve data space memory usage efficiency, the dsPIC33FJ32MC202/204 and Note: The actual set of peripheral features and dsPIC33FJ16MC304 instruction set supports both interrupts varies by the device. Refer to word and byte operations. As a consequence of byte the corresponding device tables and accessibility, all effective address calculations are pinout diagrams for device-specific internally scaled to step through word-aligned memory. information. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in 4.2.4 NEAR DATA SPACE a value of Ws+ 1for byte operations and Ws + 2 for The 8 Kbyte area between 0x0000 and 0x1FFF is word operations. referred to as the near data space. Locations in this Data byte reads will read the complete word that space are directly addressable via a 13-bit absolute contains the byte, using the LSB of any EA to address field within all memory direct instructions. determine which byte to select. The selected byte is Additionally, the whole data space is addressable using placed onto the LSB of the data path. That is, data MOV instructions, which support Memory Direct memory and registers are organized as two parallel Addressing mode with a 16-bit address field, or by byte-wide entities with shared (word) address decode using Indirect Addressing mode using a working but separate write lines. Data byte writes only write to register as an address pointer. the corresponding side of the array or register that matches the byte address. © 2007-2012 Microchip Technology Inc. DS70283K-page 31

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 DEVICES WITH 2 KB RAM MSB LSB Address 16 bits Address MSb LSb 0x0001 0x0000 2 Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 X Data RAM (X) 8 Kbyte 0x0BFF 0x0BFE Near Data 2 Kbyte 0x0001 0x0C00 Y Data RAM (Y) Space SRAM Space 0x0FFF 0x0FFE 0x1001 0x1000 0x1FFF 0x1FFE 0x2001 0x2000 0x8001 0x8000 X Data Optionally Unimplemented (X) Mapped into Program Memory 0xFFFF 0xFFFE DS70283K-page 32 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.2.5 X AND Y DATA SPACES 4.3 Program Memory Resources The core has two data spaces, X and Y. These data Many useful resources are provided on the main prod- spaces can beconsidered either separate (for some uct page of the Microchip web site for the devices listed DSP instructions), or as one unified linear address in this data sheet. This product page, which can be range (for MCU instructions). The data spaces are accessed using this link, contains the latest updates accessed using two Address Generation Units (AGUs) and additional information. and separate data paths. This feature allows certain instructions to concurrently fetch two words from RAM, Note: In the event you are not able to access thereby enabling efficient execution of DSP algorithms the product page using the link above, such as Finite Impulse Response (FIR) filtering and enter this URL in your browser: Fast Fourier Transform (FFT). http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334 The X data space is used by all instructions and supports all addressing modes. X data space has 4.3.1 KEY RESOURCES separate read and write data buses. The X read data bus is the read data path for all instructions that view • Section 4. “Program Memory” (DS70202) data space as combined X and Y address space. It is • Code Samples also the X data prefetch path for the dual operand DSP • Application Notes instructions (MAC class). • Software Libraries The Y data space is used in concert with the X data • Webinars space by the MAC class of instructions (CLR, ED, • All related dsPIC33F/PIC24H Family Reference EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide Manuals Sections two concurrent data read paths. • Development Tools Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X data space. All data memory writes, including in DSP instructions, view data space as combined X and Y address space. The boundary between the X and Y data spaces is device-dependent and is not user-programmable. All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. © 2007-2012 Microchip Technology Inc. DS70283K-page 33

D 4.4 Special Function Register Maps d S 7 s 02 TABLE 4-1: CPU CORE REGISTERS MAP P 8 3 K SFR All I -p SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets C a g 3 e 3 WREG0 0000 Working Register 0 0000 3 4 WREG1 0002 Working Register 1 0000 F WREG2 0004 Working Register 2 0000 J WREG3 0006 Working Register 3 0000 3 WREG4 0008 Working Register 4 0000 2 WREG5 000A Working Register 5 0000 M WREG6 000C Working Register 6 0000 C WREG7 000E Working Register 7 0000 2 WREG8 0010 Working Register 8 0000 0 WREG9 0012 Working Register 9 0000 2 WREG10 0014 Working Register 10 0000 / 2 WREG11 0016 Working Register 11 0000 0 WREG12 0018 Working Register 12 0000 4 WREG13 001A Working Register 13 0000 a WREG14 001C Working Register 14 0000 n WREG15 001E Working Register 15 0800 d SPLIM 0020 Stack Pointer Limit Register xxxx d ACCAL 0022 Accumulator A Low Word Register 0000 s ACCAH 0024 Accumulator A High Word Register 0000 P ACCAU 0026 Accumulator A Upper Word Register 0000 I ACCBL 0028 Accumulator B Low Word Register 0000 C ACCBH 002A Accumulator B High Word Register 0000 3 ACCBU 002C Accumulator B Upper Word Register 0000 3 PCL 002E Program Counter Low Word Register 0000 F 2© PCH 0030 — — — — — — — — Program Counter High Byte Register 0000 J 00 TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register 0000 1 7 6 -2 PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register 0000 0 M 1 RCOUNT 0036 Repeat Loop Counter Register xxxx 2 M DCOUNT 0038 DCOUNT<15:0> xxxx C ic ro DOSTARTL 003A DOSTARTL<15:1> 0 xxxx 3 ch DOSTARTH 003C — — — — — — — — — — DOSTARTH<5:0> 00xx 0 ip T DOENDL 003E DOENDL<15:1> 0 xxxx 4 e c DOENDH 0040 — — — — — — — — — — DOENDH 00xx h n o SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 lo g CORCON 0044 — — — US EDT DL<2:0> SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0020 y In Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

© TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED) 2 007 SFR Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts -2 01 MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 2 M XMODSRT 0048 XS<15:1> 0 xxxx d icro XMODEND 004A XE<15:1> 1 xxxx s ch YMODSRT 004C YS<15:1> 0 xxxx P ip T YMODEND 004E YE<15:1> 1 xxxx I e C c XBREV 0050 BREN XB<14:0> xxxx h no DISICNT 0052 — — Disable Interrupts Counter Register xxxx 3 log Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 y F Inc J . TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32MC202 3 2 NSaFmRe ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts M C CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE — — — CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 2 CNEN2 0062 — CN30IE CN29IE — CN27IE — — CN24IE CN23IE CN22IE CN21IE — — — — CN16IE 0000 0 CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE — — — CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 2 CNPU2 006A — CN30PUE CN29PUE — CN27PUE — — CN24PUE CN23PUE CN22PUE CN21PUE — — — — CN16PUE 0000 / 2 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 4 TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32MC204 and dsPIC33FJ16MC304 a n SFR SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets d CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 d CNEN2 0062 — CN30IE CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 s CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 P CNPU2 006A — CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 IC Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 3 F J 1 DS 6 70 M 2 8 3 C K -p 3 a g 0 e 3 4 5

D TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP d S 7 s 0283 NSaFmRe ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts P K I -p INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — 0000 C a ge INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 3 3 3 6 IFS0 0084 — — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 F IFS1 0086 — — INT2IF — — — — — IC8IF IC7IF — INT1IF CNIF — MI2C1IF SI2C1IF 0000 J IFS3 008A FLTA1IF — — — — QEIIF PWM1IF — — — — — — — — — 0000 3 IFS4 008C — — — — — FLTA2IF PWM2IF — — — — — — — U1EIF — 0000 2 IEC0 0094 — — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000 M IEC1 0096 — — INT2IE — — — — — IC8IE IC7IE — INT1IE CNIE — MI2C1IE SI2C1IE 0000 C IEC3 009A FLTA1IE — — — — QEIIE PWM1IE — — — — — — — — — 0000 2 IEC4 009C — — — — — FLTA2IE PWM2IE — — — — — — — U1EIE — 0000 0 IPC0 00A4 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444 2 / IPC1 00A6 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — — — — 4440 2 IPC2 00A8 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 0 IPC3 00AA — — — — — — — — — AD1IP<2:0> — U1TXIP<2:0> 0044 4 IPC4 00AC — CNIP<2:0> — — — — — MI2C1IP<2:0> — SI2C1IP<2:0> 4044 a IPC5 00AE — IC8IP<2:0> — IC7IP<2:0> — — — — — INT1IP<2:0> 4404 n IPC7 00B2 — — — — — — — — — INT2IP<2:0> — — — — 0040 d IPC14 00C0 — — — — — QEIIP<2:0> — PWM1IP<2:0> — — — — 0440 d IPC15 00C2 — FLTA1IP<2:0> — — — — — — — — — — — — 4000 s IPC16 00C4 — — — — — — — — — U1EIP<2:0> — — — — 0040 P IPC18 00C8 — — — — — FLTA2IP<2:0> — PWM2IP<2:0> — — — — 0440 I C INTTREG 00E0 — — — — ILR<3:0> — VECNUM<6:0> 0000 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 F © J 2 0 1 0 7 6 -2 0 M 1 2 M C ic ro 3 ch 0 ip T 4 e c h n o lo g y In c .

© TABLE 4-5: TIMER REGISTER MAP 2 0 0 SFR SFR All 7-2 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 1 2 TMR1 0100 Timer1 Register 0000 Mic PR1 0102 Period Register 1 FFFF d roc T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — TSYNC TCS — 0000 s h P ip TMR2 0106 Timer2 Register 0000 T I e TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx C c hn TMR3 010A Timer3 Register 0000 3 o lo PR2 010C Period Register 2 FFFF 3 g y Inc. PT2RC3ON 001101E0 TON — TSIDL — — — — P—eriod Regist—er 3 TGATE TCKPS<1:0> T32 — TCS — F0F0F0F0 FJ 3 T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 2 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. M C TABLE 4-6: INPUT CAPTURE REGISTER MAP 2 0 SFR All SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 Addr Resets / 2 IC1BUF 0140 Input 1 Capture Register xxxx 0 IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 4 IC2BUF 0144 Input 2 Capture Register xxxx a IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 n IC7BUF 0158 Input 7 Capture Register xxxx d IC7CON 015A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 d IC8BUF 015C Input 8 Capture Register xxxx s IC8CON 015E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 P Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. I C TABLE 4-7: OUTPUT COMPARE REGISTER MAP 3 3 SFR All SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets F J OC1RS 0180 Output Compare 1 Secondary Register xxxx 1 DS OC1R 0182 Output Compare 1 Register xxxx 6 70 OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 M 2 8 OC2RS 0186 Output Compare 2 Secondary Register xxxx 3 C K-p OC2R 0188 Output Compare 2 Register xxxx 3 ag OC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0 e 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 7

D TABLE 4-8: 6-OUTPUT PWM1 REGISTER MAP d S 7 s 0 2 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State P 8 3 K P1TCON 01C0 PTEN — PTSIDL — — — — — PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> 0000 0000 0000 0000 I -p C a P1TMR 01C2 PTDIR PWM Timer Count Value Register 0000 0000 0000 0000 g 3 e 3 P1TPER 01C4 — PWM Time Base Period Register 0000 0000 0000 0000 3 8 P1SECMP 01C6 SEVTDIR PWM Special Event Compare Register 0000 0000 0000 0000 F PWM1CON1 01C8 — — — — — PMOD3 PMOD2 PMOD1 — PEN3H PEN2H PEN1H — PEN3L PEN2L PEN1L 0000 0000 1111 1111 J PWM1CON2 01CA — — — — SEVOPS<3:0> — — — — — IUE OSYNC UDIS 0000 0000 0000 0000 3 2 P1DTCON1 01CC DTBPS<1:0> DTB<5:0> DTAPS<1:0> DTA<5:0> 0000 0000 0000 0000 M P1DTCON2 01CE — — — — — — — — — — DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I 0000 0000 0000 0000 C P1FLTACON 01D0 — — FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM — — — — FAEN3 FAEN2 FAEN1 0000 0000 0000 0000 P1OVDCON 01D4 — — POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L — — POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 1111 1111 0000 0000 2 0 P1DC1 01D6 PWM Duty Cycle #1 Register 0000 0000 0000 0000 2 P1DC2 01D8 PWM Duty Cycle #2 Register 0000 0000 0000 0000 / 2 P1DC3 01DA PWM Duty Cycle #3 Register 0000 0000 0000 0000 0 Legend: u = uninitialized bit, — = unimplemented, read as ‘0’ 4 TABLE 4-9: 2-OUTPUT PWM2 REGISTER MAP a n SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State d P2TCON 05C0 PTEN — PTSIDL — — — — — PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> 0000 0000 0000 0000 d P2TMR 05C2 PTDIR PWM Timer Count Value Register 0000 0000 0000 0000 s P2TPER 05C4 — PWM Time Base Period Register 0000 0000 0000 0000 P P2SECMP 05C6 SEVTDIR PWM Special Event Compare Register 0000 0000 0000 0000 I C PWM2CON1 05C8 — — — — — — — PMOD1 — — — PEN1H — — — PEN1L 0000 0000 1111 1111 3 PWM2CON2 05CA — — — — SEVOPS<3:0> — — — — — IUE OSYNC UDIS 0000 0000 0000 0000 3 P2DTCON1 05CC DTBPS<1:0> DTB<5:0> DTAPS<1:0> DTA<5:0> 0000 0000 0000 0000 F © P2DTCON2 05CE — — — — — — — — — — — — — — DTS1A DTS1I 0000 0000 0000 0000 J 2 0 P2FLTACON 05D0 — — — — — — FAOV1H FAOV1L FLTAM — — — — — — FAEN1 0000 0000 0000 0000 1 0 7-2 P2OVDCON 05D4 — — — — — — POVD1H POVD1L — — — — — — POUT1H POUT1L 1111 1111 0000 0000 6 0 M 1 P2DC1 05D6 PWM Duty Cycle #1 Register 0000 0000 0000 0000 2 M Legend: u = uninitialized bit, — = unimplemented, read as ‘0’ C ic ro 3 ch 0 ip T 4 e c h n o lo g y In c .

© TABLE 4-10: QEI1 REGISTER MAP 2 0 07 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State -2 Name 10 0 1 2 QEI1CON 01E0 CNTERR — QEISIDL INDEX UPDN QEIM<2:0> SWPAB PCDOUT TQGATE TQCKPS<1:0> POSRES TQCS UPDN_SRC 0000 0000 0000 0000 M d ic DFLT1CON 01E2 — — — — — IMV<1:0> CEID QEOUT QECK<2:0> — — — — 0000 0000 0000 0000 roc POS1CNT 01E4 Position Counter<15:0> 0000 0000 0000 0000 s h P ip MAX1CNT 01E6 Maximum Count<15:0> 1111 1111 1111 1111 T I e Legend: u = uninitialized bit, — = unimplemented, read as ‘0’ C c h no TABLE 4-11: I2C1 REGISTER MAP 3 lo 3 g y SFR All F Inc SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets J . I2C1RCV 0200 — — — — — — — — Receive Register 0000 3 2 I2C1TRN 0202 — — — — — — — — Transmit Register 00FF M I2C1BRG 0204 — — — — — — — Baud Rate Generator Register 0000 C I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 2 0 I2C1ADD 020A — — — — — — Address Register 0000 2 I2C1MSK 020C — — — — — — Address Mask Register 0000 / 2 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 TABLE 4-12: UART1 REGISTER MAP 4 a SFR All SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets n d U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000 U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 d U1TXREG 0224 — — — — — — — UART Transmit Register xxxx s P U1RXREG 0226 — — — — — — — UART Receive Register 0000 I U1BRG 0228 Baud Rate Generator Prescaler 0000 C Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 3 TABLE 4-13: SPI1 REGISTER MAP F SFR SFR All J Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets 1 DS SPI1STAT 0240 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 6 702 SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000 M 8 3K SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY — 0000 C -p SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000 3 a g 0 e Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 4 9

D TABLE 4-14: ADC1 REGISTER MAP FOR dsPIC33FJ32MC202 d S 7 s 0 2 All P 83 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset K-p s IC a g ADC1BUF0 0300 ADC Data Buffer 0 xxxx 3 e 40 ADC1BUF1 0302 ADC Data Buffer 1 xxxx 3 F ADC1BUF2 0304 ADC Data Buffer 2 xxxx J ADC1BUF3 0306 ADC Data Buffer 3 xxxx 3 ADC1BUF4 0308 ADC Data Buffer 4 xxxx 2 ADC1BUF5 030A ADC Data Buffer 5 xxxx M ADC1BUF6 030C ADC Data Buffer 6 xxxx C ADC1BUF7 030E ADC Data Buffer 7 xxxx 2 0 ADC1BUF8 0310 ADC Data Buffer 8 xxxx 2 ADC1BUF9 0312 ADC Data Buffer 9 xxxx / 2 ADC1BUFA 0314 ADC Data Buffer 10 xxxx 0 ADC1BUFB 0316 ADC Data Buffer 11 xxxx 4 ADC1BUFC 0318 ADC Data Buffer 12 xxxx a ADC1BUFD 031A ADC Data Buffer 13 xxxx n ADC1BUFE 031C ADC Data Buffer 14 xxxx d ADC1BUFF 031E ADC Data Buffer 15 xxxx d AD1CON1 0320 ADON — ADSIDL — — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000 s AD1CON2 0322 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000 P AD1CON3 0324 ADRC — — SAMC<4:0> ADCS<7:0> 0000 I C AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000 3 AD1CHS0 0328 CH0NB — — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000 3 AD1PCFGL 032C — — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 F 2© AD1CSSL 0330 — — — — — — — — — — CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000 J 00 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 7 6 -2 0 M 1 2 M C ic ro 3 ch 0 ip T 4 e c h n o lo g y In c .

© TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 2 0 07 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All -2 Resets 0 1 2 ADC1BUF0 0300 ADC Data Buffer 0 xxxx M d ic ADC1BUF1 0302 ADC Data Buffer 1 xxxx ro s c ADC1BUF2 0304 ADC Data Buffer 2 xxxx h P ip T ADC1BUF3 0306 ADC Data Buffer 3 xxxx I ec ADC1BUF4 0308 ADC Data Buffer 4 xxxx C h no ADC1BUF5 030A ADC Data Buffer 5 xxxx 3 lo 3 gy ADC1BUF6 030C ADC Data Buffer 6 xxxx F Inc ADC1BUF7 030E ADC Data Buffer 7 xxxx J . ADC1BUF8 0310 ADC Data Buffer 8 xxxx 3 2 ADC1BUF9 0312 ADC Data Buffer 9 xxxx M ADC1BUFA 0314 ADC Data Buffer 10 xxxx C ADC1BUFB 0316 ADC Data Buffer 11 xxxx 2 ADC1BUFC 0318 ADC Data Buffer 12 xxxx 0 ADC1BUFD 031A ADC Data Buffer 13 xxxx 2 ADC1BUFE 031C ADC Data Buffer 14 xxxx /2 ADC1BUFF 031E ADC Data Buffer 15 xxxx 0 4 AD1CON1 0320 ADON — ADSIDL — — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000 AD1CON2 0322 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000 a AD1CON3 0324 ADRC — — SAMC<4:0> ADCS<7:0> 0000 n d AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000 AD1CHS0 0328 CH0NB — — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000 d AD1PCFGL 032C — — — — — — — PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 s AD1CSSL 0330 — — — — — — — CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000 P Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. IC 3 3 F J 1 DS 6 70 M 2 8 3 C K -p 3 a g 0 e 4 4 1

D d S TABLE 4-16: PERIPHERAL PIN SELECT INPUT REGISTER MAP 7 s 0 28 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All P 3 Name Resets K I -pa RPINR0 0680 — — — INT1R<4:0> — — — — — — — — 1F00 C g 3 e 4 RPINR1 0682 — — — — — — — — — — — INT2R<4:0> 001F 3 2 RPINR3 0686 — — — T3CKR<4:0> — — — T2CKR<4:0> 1F1F F RPINR7 068E — — — IC2R<4:0> — — — IC1R<4:0> 1F1F J 3 RPINR10 0694 — — — IC8R<4:0> — — — IC7R<4:0> 1F1F 2 RPINR11 0696 — — — — — — — — — — — OCFAR<4:0> 001F M RPINR12 0698 — — — — — — — — — — — FLTA1R<4:0> 001F C RPINR13 069A — — — — — — — — — — — FLTA2R<4:0> 001F 2 RPINR14 069C — — — QEB1R<4:0> — — — QEA1R<4:0> 1F1F 0 RPINR15 069E — — — — — — — — — — — INDX1R<4:0> 001F 2 RPINR18 06A4 — — — U1CTSR<4:0> — — — U1RXR<4:0> 1F1F /2 RPINR20 06A8 — — — SCK1R<4:0> — — — SDI1R<4:0> 1F1F 0 4 RPINR21 06AA — — — — — — — — — — — SS1R<4:0> 001F Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. a n TABLE 4-17: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32MC202 d File All d Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets s RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> 0000 P RPOR1 06C2 — — — RP3R<4:0> — — — RP2R<4:0> 0000 IC RPOR2 06C4 — — — RP5R<4:0> — — — RP4R<4:0> 0000 3 RPOR3 06C6 — — — RP7R<4:0> — — — RP6R<4:0> 0000 3 RPOR4 06C8 — — — RP9R<4:0> — — — RP8R<4:0> 0000 F 2© RPOR5 06CA — — — RP11R<4:0> — — — RP10R<4:0> 0000 J 00 RPOR6 06CC — — — RP13R<4:0> — — — RP12R<4:0> 0000 1 7-2 RPOR7 06CE — — — RP15R<4:0> — — — RP14R<4:0> 0000 6 0 M 1 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 M C ic ro 3 ch 0 ip T 4 e c h n o lo g y In c .

TABLE 4-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 © 200 NFaimlee Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 7 -20 RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> 0000 1 2 M RPOR1 06C2 — — — RP3R<4:0> — — — RP2R<4:0> 0000 d ic RPOR2 06C4 — — — RP5R<4:0> — — — RP4R<4:0> 0000 ro s ch RPOR3 06C6 — — — RP7R<4:0> — — — RP6R<4:0> 0000 P ip T RPOR4 06C8 — — — RP9R<4:0> — — — RP8R<4:0> 0000 I ec RPOR5 06CA — — — RP11R<4:0> — — — RP10R<4:0> 0000 C h no RPOR6 06CC — — — RP13R<4:0> — — — RP12R<4:0> 0000 3 log RPOR7 06CE — — — RP15R<4:0> — — — RP14R<4:0> 0000 3 y F Inc RPOR8 06D0 — — — RP17R<4:0> — — — RP16R<4:0> 0000 J . RPOR9 06D2 — — — RP19R<4:0> — — — RP18R<4:0> 0000 3 RPOR10 06D4 — — — RP21R<4:0> — — — RP20R<4:0> 0000 2 RPOR11 06D6 — — — RP23R<4:0> — — — RP22R<4:0> 0000 M RPOR12 06D8 — — — RP25R<4:0> — — — RP24R<4:0> 0000 C Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 0 TABLE 4-19: PORTA REGISTER MAP FOR dsPIC33FJ32MC202 2 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets /2 Name 0 TRISA 02C0 — — — — — — — — — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001F 4 PORTA 02C2 — — — — — — — — — — — RA4 RA3 RA2 RA1 RA0 xxxx a LATA 02C4 — — — — — — — — — — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx n ODCA 02C6 — — — — — — — — — — — ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 d Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d s TABLE 4-20: PORTA REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 P File I Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets C Name 3 TRISA 02C0 — — — — — TRISA10 TRISA9 TRISA8 TRISA7 — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 079F 3 PORTA 02C2 — — — — — RA10 RA9 RA8 RA7 — — RA4 RA3 RA2 RA1 RA0 xxxx F LATA 02C4 — — — — — LAT10 LAT8 LAT8 LAT7 — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx J ODCA 02C6 — — — — — ODCA10 ODCA9 ODCA8 ODCA7 — — ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 1 DS Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 70 M 2 8 3 C K -p 3 a g 0 e 4 4 3

D d S TABLE 4-21: PORTB REGISTER MAP 7 s 0 28 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets P 3 Name K I -pa TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB6 TRISB5 TRISB1 TRISB0 FFFF C g 3 e PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB6 RB5 RB1 RB0 xxxx 4 3 4 LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB6 LATB5 LATB1 LATB0 xxxx F ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB6 ODCB5 ODCB1 ODCB0 0000 J Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices. 3 2 TABLE 4-22: PORTC REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 M File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets C TRISC 02D0 — — — — — — TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC6 TRISC5 TRISC1 TRISC0 03FF 2 0 PORTC 02D2 — — — — — — RC9 RC8 RC7 RC6 RC5 RC4 RC6 RC5 RC1 RC0 xxxx 2 LATC 02D4 — — — — — — LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC6 LATC5 LATC1 LATC0 xxxx / 2 ODCC 02D6 — — — — — — ODCC9 ODCC8 ODCC7 ODCC6 ODCC5 ODCC4 ODCC6 ODCC5 ODCC1 ODCC0 0000 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 a TABLE 4-23: SYSTEM CONTROL REGISTER MAP n d All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets d RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1) s P OSCCON 0742 — COSC<2:0> — NOSC<2:0> CLKLOCK IOLOCK LOCK — CF — LPOSCEN OSWEN 0300(2) I CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> PLLPOST<1:0> — PLLPRE<4:0> 3040 C PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0030 3 OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000 3 F Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2© Note 1: RCON register Reset values dependent on type of Reset. J 0 2: OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset. 1 0 7 6 -2 0 M 1 2 M C ic ro 3 ch 0 ip T 4 e c h n o lo g y In c .

© TABLE 4-24: NVM REGISTER MAP 2 0 0 All 7 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Resets 0 12 NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP<3:0> 0000(1) Mic NVMKEY 0766 — — — — — — — — NVMKEY<7:0> 0000 d roc Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. s hip Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. P T I e C c TABLE 4-25: PMD REGISTER MAP h n 3 o lo File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 3 gy Resets F Inc PMD1 0770 — — T3MD T2MD T1MD QEIMD PWM1MD — I2C1MD — U1MD — SPI1MD — — AD1MD 0000 J . 3 PMD2 0772 IC8MD IC7MD — — — — IC2MD IC1MD — — — — — — OC2MD OC1MD 0000 2 PMD3 0774 — — — — — — — — — — — PWM2MD — — — — 0000 M Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. C 2 0 2 / 2 0 4 a n d d s P I C 3 3 F J 1 DS 6 70 M 2 8 3 C K -p 3 a g 0 e 4 4 5

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.4.1 SOFTWARE STACK 4.4.2 DATA RAM PROTECTION FEATURE In addition to its use as a working register, the W15 The dsPIC33F product family supports Data RAM register in the dsPIC33FJ32MC202/204 and protection features that enable segments of RAM to be dsPIC33FJ16MC304 devices is also used as a protected when used in conjunction with Boot and software Stack Pointer. The Stack Pointer always Secure Code Segment Security. BSRAM (Secure RAM points to the first available free word and grows from segment for BS) is accessible only from the Boot lower to higher addresses. It predecrements for stack Segment Flash code when enabled. SSRAM (Secure pops and post-increments for stack pushes, as shown RAM segment for RAM) is accessible only from the in Figure4-4. For a PC push during any CALL Secure Segment Flash code when enabled. See instruction, the MSb of the PC is zero-extended before Table4-1 for an overview of the BSRAM and SSRAM the push, ensuring that the MSb is always clear. SFRs. Note: A PC push during exception processing 4.5 Instruction Addressing Modes concatenates the SRL register to the MSb of the PC prior to the push. The addressing modes shown in Table4-26 form the basis of the addressing modes optimized to support the The Stack Pointer Limit register (SPLIM) associated specific features of individual instructions. The with the Stack Pointer sets an upper address boundary addressing modes provided in the MAC class of for the stack. SPLIM is uninitialized at Reset. As is the instructions differ from those in the other instruction case for the Stack Pointer, SPLIM<0> is forced to ‘0’ types. because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source 4.5.1 FILE REGISTER INSTRUCTIONS or destination pointer, the resulting address is Most file register instructions use a 13-bit address field compared with the value in SPLIM. If the contents of (f) to directly address data present in the first 8192 the Stack Pointer (W15) and the SPLIM register are bytes of data memory (near data space). Most file equal and a push operation is performed, a stack error register instructions employ a working register, W0, trap will not occur. The stack error trap will occur on a which is denoted as WREG in these instructions. The subsequent push operation. For example, to cause a destination is typically either the same file register or stack error trap when the stack grows beyond address WREG (with the exception of the MUL instruction), 0x1000 in RAM, initialize the SPLIM with the value which writes the result to a register or register pair. The 0x0FFE. MOV instruction allows additional flexibility and can Similarly, a Stack Pointer underflow (stack error) trap is access the entire data space. generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from 4.5.2 MCU INSTRUCTIONS interfering with the Special Function Register (SFR) The three-operand MCU instructions are of the form: space. Operand 3 = Operand 1 <function> Operand 2 A write to the SPLIM register should not be immediately where Operand 1 is always a working register (that is, followed by an indirect read operation using W15. the addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, FIGURE 4-4: CALL STACK FRAME fetched from data memory, or a 5-bit literal. The result 0x0000 15 0 location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions: d • Register Direct waress • Register Indirect Todr s Ad • Register Indirect Post-Modified Growgher 000000P0C0<015P:C0><22:16> W15 (before CALL) • Register Indirect Pre-Modified ck Hi <Free Word> W15 (after CALL) • 5-bit or 10-bit Literal a St Note: Not all instructions support all the POP : [--W15] addressing modes given above. Individ- PUSH: [W15++] ual instructions can support different subsets of these addressing modes. DS70283K-page 46 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 4-26: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. 4.5.3 MOVE AND ACCUMULATOR 4.5.4 MAC INSTRUCTIONS INSTRUCTIONS The dual source operand DSP instructions (CLR, ED, Move instructions and the DSP accumulator class of EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred instructions provide a greater degree of addressing to as MAC instructions, use a simplified set of addressing flexibility than other instructions. In addition to the modes to allow the user application to effectively addressing modes supported by most MCU manipulate the data pointers through register indirect instructions, move and accumulator instructions also tables. support Register Indirect with Register Offset The two-source operand prefetch registers must be Addressing mode, also referred to as Register Indexed members of the set {W8, W9, W10, W11}. For data mode. reads, W8 and W9 are always directed to the X RAGU, Note: For the MOV instructions, the addressing and W10 and W11 are always directed to the Y AGU. mode specified in the instruction can differ The effective addresses generated (before and after for the source and destination EA. modification) must, therefore, be valid addresses within However, the 4-bit Wb (Register Offset) X data space for W8 and W9 and Y data space for W10 field is shared by both source and and W11. destination (but typically only used by Note: Register Indirect with Register Offset one). Addressing mode is available only for W9 (in X space) and W11 (in Y space). In summary, the following addressing modes are supported by move and accumulator instructions: In summary, the following addressing modes are • Register Direct supported by the MAC class of instructions: • Register Indirect • Register Indirect • Register Indirect Post-modified • Register Indirect Post-Modified by 2 • Register Indirect Pre-modified • Register Indirect Post-Modified by 4 • Register Indirect with Register Offset (Indexed) • Register Indirect Post-Modified by 6 • Register Indirect with Literal Offset • Register Indirect with Register Offset (Indexed) • 8-bit Literal 4.5.5 OTHER INSTRUCTIONS • 16-bit Literal Besides the addressing modes outlined previously, some Note: Not all instructions support all the instructions use literal constants of various sizes. For addressing modes given above. Individual example, BRA (branch) instructions use 16-bit signed instructions may support different subsets literals to specify the branch destination directly, whereas of these addressing modes. the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. © 2007-2012 Microchip Technology Inc. DS70283K-page 47

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.6 Modulo Addressing Note: Y space Modulo Addressing EA Modulo Addressing mode is a method of providing an calculations assume word-sized data automated means to support circular data buffers using (LSb of every EA is always clear). hardware. The objective is to remove the need for The length of a circular buffer is not directly specified. It software to perform data address boundary checks is determined by the difference between the when executing tightly looped code, as is typical in corresponding start and end addresses. The maximum many DSP algorithms. possible length of the circular buffer is 32K words Modulo Addressing can operate in either data or program (64Kbytes). space (since the data pointer mechanism is essentially 4.6.2 W ADDRESS REGISTER the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into SELECTION program space) and Y data spaces. Modulo Addressing The Modulo and Bit-Reversed Addressing Control can operate on any W register pointer. However, it is not register, MODCON<15:0>, contains enable flags as well advisable to use W14 or W15 for Modulo Addressing as a W register field to specify the W Address registers. since these two registers are used as the Stack Frame The XWM and YWM fields select the registers that will Pointer and Stack Pointer, respectively. operate with Modulo Addressing: In general, any particular circular buffer can be • If XWM = 15, XRAGU and X WAGU Modulo configured to operate in only one direction as there are Addressing is disabled. certain restrictions on the buffer start address (for incre- • If YWM = 15, Y AGU Modulo Addressing is menting buffers), or end address (for decrementing disabled. buffers), based upon the direction of the buffer. The X Address Space Pointer W register (XWM), to The only exception to the usage restrictions is for which Modulo Addressing is to be applied, is stored in buffers that have a power-of-two length. As these MODCON<3:0> (see Table4-1). Modulo Addressing is buffers satisfy the start and end address criteria, they enabled for X data space when XWM is set to any value can operate in a bidirectional mode (that is, address other than ‘15’ and the XMODEN bit is set at boundary checks are performed on both the lower and MODCON<15>. upper address boundaries). The Y Address Space Pointer W register (YWM) to 4.6.1 START AND END ADDRESS which Modulo Addressing is to be applied is stored in MODCON<7:4>. Modulo Addressing is enabled for Y The Modulo Addressing scheme requires that a data space when YWM is set to any value other than starting and ending address be specified and loaded ‘15’ and the YMODEN bit is set at MODCON<14>. into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table4-1). FIGURE 4-5: MODULO ADDRESSING OPERATION EXAMPLE Byte MOV #0x1100, W0 Address MOV W0, XMODSRT ;set modulo start address MOV #0x1163, W0 MOV W0, MODEND ;set modulo end address 0x1100 MOV #0x8001, W0 MOV W0, MODCON ;enable W1, X AGU for modulo MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer 0x1163 DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words DS70283K-page 48 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.6.3 MODULO ADDRESSING If the length of a bit-reversed buffer is M = 2N bytes, APPLICABILITY the last ‘N’ bits of the data buffer start address must be zeros. Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W XB<14:0> is the Bit-Reversed Address modifier, or register. Address boundaries check for addresses ‘pivot point’, which is typically a constant. In the case of equal to: an FFT computation, its value is equal to half of the FFT data buffer size. • The upper boundary addresses for incrementing buffers Note: All bit-reversed EA calculations assume • The lower boundary addresses for decrementing word-sized data (LSb of every EA is buffers always clear). The XB value is scaled accordingly to generate compatible (byte) It is important to realize that the address boundaries addresses. check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing When enabled, Bit-Reversed Addressing is executed buffers) boundary addresses (not just equal to). only for Register Indirect with Pre-Increment or Address changes can, therefore, jump beyond Post-Increment Addressing and word-sized data boundaries and still be adjusted correctly. writes. It will not function for any other addressing mode or for byte-sized data, and normal addresses are Note: The modulo corrected effective address is generated instead. When Bit-Reversed Addressing is written back to the register only when active, the W Address Pointer is always added to the Pre-Modify or Post-Modify Addressing address modifier (XB), and the offset associated with mode is used to compute the effective the Register Indirect Addressing mode is ignored. In address. When an address offset (such as addition, as word-sized data is a requirement, the LSb [W7 + W2]) is used, Modulo Address of the EA is ignored (and always clear). correction is performed but the contents of the register remain unchanged. Note: Modulo Addressing and Bit-Reversed Addressing should not be enabled 4.7 Bit-Reversed Addressing together. If an application attempts to do so, Bit-Reversed Addressing will assume Bit-Reversed Addressing mode is intended to simplify priority when active for the X WAGU and X data re-ordering for radix-2 FFT algorithms. It is WAGU, Modulo Addressing will be supported by the X AGU for data writes only. disabled. However, Modulo Addressing will continue to function in the X RAGU. The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The If Bit-Reversed Addressing has already been enabled address source and destination are kept in normal order. by setting the BREN bit (XBREV<15>), a write to the Thus, the only operand requiring reversal is the modifier. XBREV register should not be immediately followed by an indirect read operation using the W register that has 4.7.1 BIT-REVERSED ADDRESSING been designated as the bit-reversed pointer. IMPLEMENTATION Bit-Reversed Addressing mode is enabled in any of these situations: • BWM bits (W register selection) in the MODCON register are any value other than ‘15’ (the stack cannot be accessed using Bit-Reversed Addressing) • The BREN bit is set in the XBREV register • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment © 2007-2012 Microchip Technology Inc. DS70283K-page 49

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 4-6: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-27: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 DS70283K-page 50 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.8 Interfacing Program and Data 4.8.1 ADDRESSING PROGRAM SPACE Memory Spaces Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is The dsPIC33FJ32MC202/204 and needed to create a 23-bit or 24-bit program address dsPIC33FJ16MC304 architecture uses a 24-bit-wide from 16-bit data registers. The solution depends on the program space and a 16-bit-wide data space. The interface method to be used. architecture is also a modified Harvard scheme, meaning that data can also be present in the program For table operations, the 8-bit Table Page register space. To use this data successfully, it must be (TBLPAG) is used to define a 32Kword region within accessed in a way that preserves the alignment of the program space. This is concatenated with a 16-bit information in both spaces. EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used Aside from normal execution, the to determine if the operation occurs in the user memory dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 (TBLPAG<7> = 0) or the configuration memory architecture provides two methods by which program (TBLPAG<7> = 1). space can be accessed during operation: For remapping operations, the 8-bit Program Space • Using table instructions to access individual bytes Visibility register (PSVPAG) is used to define a or words anywhere in the program space 16Kword page in the program space. When the Most • Remapping a portion of the program space into Significant bit of the EA is ‘1’, PSVPAG is concatenated the data space (Program Space Visibility) with the lower 15 bits of the EA to form a 23-bit program Table instructions allow an application to read or write space address. Unlike table operations, this limits to small areas of the program memory. This capability remapping operations strictly to the user memory area. makes the method ideal for accessing data tables that Table4-28 and Figure4-7 show how the program EA is need to be updated periodically. It also allows access created for table operations and remapping accesses to all bytes of the program word. The remapping from the data EA. Here, P<23:0> refers to a program method allows an application to access a large block of space word, and D<15:0> refers to a data space word. data on a read-only basis, which is ideal for look-ups from a large table of static data. The application can only access the least significant word of the program word. TABLE 4-28: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 (Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0>(1) (Block Remap/Read) 0 xxxx xxxx xxx xxxx xxxx xxxx Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. © 2007-2012 Microchip Technology Inc. DS70283K-page 51

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 4-7: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 0 23 bits EA 1/0 Table Operations(2) 1/0 TBLPAG 8 bits 16 bits 24 bits Select 1 EA 0 Program Space Visibility(1) 0 PSVPAG (Remapping) 8 bits 15 bits 23 bits User/Configuration Byte Select Space Select Note1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS70283K-page 52 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.8.2 DATA ACCESS FROM PROGRAM - In Byte mode, either the upper or lower byte MEMORY USING TABLE of the lower program word is mapped to the INSTRUCTIONS lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower The TBLRDL and TBLWTL instructions offer a direct byte is selected when it is ‘0’. method of reading or writing the lower word of any • TBLRDH (Table Read High): address within the program space without going through data space. The TBLRDH and TBLWTH - In Word mode, this instruction maps the entire instructions are the only method to read or write the upper word of a program address (P<23:16>) upper 8bits of a program space word as data. to a data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’. The PC is incremented by two for each successive - In Byte mode, this instruction maps the upper 24-bit program word. This allows program memory or lower byte of the program word to D<7:0> addresses to directly map to data space addresses. of the data address, in the TBLRDL instruc- Program memory can thus be regarded as two tion. The data is always ‘0’ when the upper 16-bit-wide word address spaces, residing side by side, ‘phantom’ byte is selected (Byte Select = 1). each with the same address range. TBLRDL and TBLWTL access the space that contains the least In a similar fashion, two table instructions, TBLWTH significant data word. TBLRDH and TBLWTH access the and TBLWTL, are used to write individual bytes or space that contains the upper data byte. words to a program space address. The details of their operation are explained in Section5.0 “Flash Two table instructions are provided to move byte or Program Memory”. word-sized (16-bit) data to and from program space. Both function as either byte or word operations. For all table operations, the area of program memory space to be accessed is determined by the Table Page • TBLRDL (Table Read Low): register (TBLPAG). TBLPAG covers the entire program - In Word mode, this instruction maps the memory space of the device, including user and lower word of the program space configuration spaces. When TBLPAG<7> = 0, the table location (P<15:0>) to a data address page is located in the user memory space. When (D<15:0>). TBLPAG<7> = 1, the page is located in configuration space. FIGURE 4-8: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG 02 23 15 0 0x000000 23 16 8 0 00000000 00000000 0x020000 00000000 0x030000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 0x800000 Only read operations are shown; write operations are also valid in the user memory area. © 2007-2012 Microchip Technology Inc. DS70283K-page 53

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.8.3 READING DATA FROM PROGRAM 24-bit program word are used to contain the data. The MEMORY USING PROGRAM SPACE upper 8 bits of any program space location used as VISIBILITY data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible The upper 32Kbytes of data space may optionally be issues should the area of code ever be accidentally mapped into any 16Kword page of the program space. executed. This option provides transparent access to stored constant data from the data space without the need to Note: PSV access is temporarily disabled during use special instructions (such as TBLRDL/H). table reads/writes. Program space access through the data space occurs For operations that use PSV and are executed outside if the Most Significant bit of the data space EA is ‘1’ and a REPEAT loop, the MOV and MOV.D instructions program space visibility is enabled by setting the PSV require one instruction cycle in addition to the specified bit in the Core Control register (CORCON<2>). The execution time. All other instructions require two location of the program memory space to be mapped instruction cycles in addition to the specified execution into the data space is determined by the Program time. Space Visibility Page register (PSVPAG). This 8-bit For operations that use PSV, and are executed inside register defines any one of 256 possible pages of a REPEAT loop, these instances require two instruction 16Kwords in program space. In effect, PSVPAG cycles in addition to the specified execution time of the functions as the upper 8 bits of the program memory instruction: address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each • Execution in the first iteration program memory word, the lower 15 bits of data space • Execution in the last iteration addresses directly map to the lower 15 bits in the • Execution prior to exiting the loop due to an corresponding program space addresses. interrupt Data reads to this area add a cycle to the instruction • Execution upon re-entering the loop after an being executed, since two program memory fetches interrupt is serviced are required. Any other iteration of the REPEAT loop will allow the Although each data space address 8000h and higher instruction using PSV to access data, to execute in a maps directly into a corresponding program memory single cycle. address (see Figure4-9), only the lower 16bits of the FIGURE 4-9: PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space Data Space PSVPAG 23 15 0 02 0x000000 0x0000 Data EA<14:0> 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory 0x8000 space... PSV Area ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 0x800000 DS70283K-page 54 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 5.0 FLASH PROGRAM MEMORY customers to manufacture boards with unprogrammed devices and then program the digital signal controller Note1: This data sheet summarizes the features just before shipping the product. This also allows the of the dsPIC33FJ32MC202/204 and most recent firmware or a custom firmware to be pro- dsPIC33FJ16MC304 devices. It is not grammed. intended to be a comprehensive refer- RTSP is accomplished using TBLRD (table read) and ence source. To complement the infor- TBLWT (table write) instructions. With RTSP, the user mation in this data sheet, refer to Section application can write program memory data either in 5. “Flash Programming” (DS70191) of blocks or ‘rows’ of 64 instructions (192 bytes) at a time the “dsPIC33F/PIC24H Family Refer- or a single program memory word, and erase program ence Manual” which is available from the memory in blocks or ‘pages’ of 512 instructions (1536 Microchip web site (www.microchip.com) bytes) at a time. 2: Some registers and associated bits described in this section may not be 5.1 Table Instructions and Flash available on all devices. Refer to Programming Section4.0 “Memory Organization” in this data sheet for device-specific register Regardless of the method used, all programming of and bit information. Flash memory is done with the table read and table write instructions. These allow direct read and write The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 access to the program memory space from the data devices contain internal Flash program memory for memory while the device is in normal operating mode. storing and executing application code. The memory is The 24-bit target address in the program memory is readable, writable and erasable during normal operation formed using bits <7:0> of the TBLPAG register and the over the entire VDD range. Effective Address (EA) from a W register specified in Flash memory can be programmed in two ways: the table instruction, as shown in Figure5-1. • In-Circuit Serial Programming™ (ICSP™) The TBLRDL and the TBLWTL instructions are used to programming capability read or write to bits <15:0> of program memory. • Run-Time Self-Programming (RTSP) TBLRDL and TBLWTL can access program memory in both Word and Byte modes. ICSP allows a dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 device to be serially programmed The TBLRDH and TBLWTH instructions are used to read while in the end application circuit. This is done with or write to bits <23:16> of program memory. TBLRDH two lines for programming clock and programming data and TBLWTH can also access program memory in Word (one of the alternate programming pin pairs: or Byte mode. PGECx/PGEDx), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 bits Using 0 Program Counter 0 Program Counter Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 bits 16 bits User/Configuration Byte Space Select 24-bit EA Select © 2007-2012 Microchip Technology Inc. DS70283K-page 55

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 5.2 RTSP Operation EQUATION 5-2: MINIMUM ROW WRITE TIME The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Flash program memory array is organized into rows of 64 11064 Cycles instructions or 192 bytes. RTSP allows the user T =------------------------------------------------------------------------------------------------=1.435ms RW 7.37 MHz× (1+0.05)× (1–0.00375) application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table24-12 shows typical The maximum row write time is equal to Equation5-3. erase and programming times. The 8-row erase pages and single row write rows are edge-aligned from the EQUATION 5-3: MAXIMUM ROW WRITE beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. TIME The program memory implements holding buffers that 11064 Cycles can contain 64 instructions of programming data. Prior T =------------------------------------------------------------------------------------------------=1.586ms RW 7.37 MHz× (1–0.05)× (1–0.00375) to the actual programming operation, the write data must be loaded into the buffers sequentially. The instruction words loaded must always be from a group Setting the WR bit (NVMCON<15>) starts the opera- of 64 boundary. tion, and the WR bit is automatically cleared when the The basic sequence for RTSP programming is to set up operation is finished. a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by 5.4 Flash Memory Resources setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required Many useful resources are provided on the main prod- to load the instructions. uct page of the Microchip web site for the devices listed in this data sheet. This product page, which can be All of the table write operations are single-word writes accessed using this link, contains the latest updates (two instruction cycles) because only the buffers are and additional information. written. A programming cycle is required for programming each row. Note: In the event you are not able to access the product page using the link above, 5.3 Programming Operations enter this URL in your browser: http://www.microchip.com/wwwproducts/ A complete programming sequence is necessary for Devices.aspx?dDocName=en530334 programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the 5.4.1 KEY RESOURCES programming operation is finished. • Section 5. “Flash Programming” (DS70191) The programming time depends on the FRC accuracy • Code Samples (see Table24-18, “AC Characteristics: Internal RC Accuracy”) and the value of the FRC Oscillator Tuning • Application Notes register (see Register8-4). Use the following formula to • Software Libraries calculate the minimum and maximum values for the • Webinars Row Write Time, Page Erase Time, and Word Write • All related dsPIC33F/PIC24H Family Reference Cycle Time parameters (see Table24-12, “DC Manuals Sections Characteristics: Program Memory”). • Development Tools EQUATION 5-1: PROGRAMMING TIME 5.5 Control Registers T 7---.--3---7--- --M-----H----z----×------(--F----R----C---- -A----c--c---u---r--a---c---y---)---%------×------(--F----R----C---- -T---u---n---i--n---g----)--%---- Two SFRs are used to read and write the program Flash memory: NVMCON and NVMKEY. For example, if the device is operating at +125°C, the The NVMCON register (Register5-1) controls which blocks are to be erased, which memory type is to be FRC accuracy will be ±5%. If the TUN<5:0> bits (see programmed and the start of the programming cycle. Register8-4) are set to ‘b111111,the minimum row write time is equal to Equation5-2. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section5.3 “Programming Operations” for further details. DS70283K-page 56 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — ERASE — — NVMOP<3:0>(2) bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command 0 = Perform the program operation specified by NVMOP<3:0> on the next WR command bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation Select bits(2) If ERASE = 1: 1111 = Memory bulk erase operation 1101 = Erase General Segment 1100 = Erase Secure Segment 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte If ERASE = 0: 1111 = No operation 1101 = No operation 1100 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be Reset on a POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2007-2012 Microchip Technology Inc. DS70283K-page 57

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits DS70283K-page 58 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 5.5.1 PROGRAMMING ALGORITHM FOR 4. Write the first 64 instructions from data RAM into FLASH PROGRAM MEMORY the program memory buffers (see Example5-2). 5. Write the program block to Flash memory: Programmers can program one row of program Flash memory at a time. To do this, it is necessary to erase a) Set the NVMOP bits to ‘0001’ to configure the 8-row erase page that contains the desired row. for row programming. Clear the ERASE bit The general process is: and set the WREN bit. b) Write 0x55 to NVMKEY. 1. Read eight rows of program memory (512instructions) and store in data RAM. c) Write 0xAA to NVMKEY. 2. Update the program data in RAM with the d) Set the WR bit. The programming cycle desired new data. begins and the CPU stalls for the duration of the write cycle. When the write to Flash 3. Erase the block (see Example5-1): memory is done, the WR bit is cleared a) Set the NVMOP bits (NVMCON<3:0>) to automatically. ‘0010’ to configure for block erase. Set the 6. Repeat steps 4 and 5, using the next available ERASE (NVMCON<6>) and WREN 64 instructions from the block in data RAM by (NVMCON<14>) bits. incrementing the value in TBLPAG, until all b) Write the starting address of the page to be 512instructions are written back to Flash memory. erased into the TBLPAG and W registers. For protection against accidental operations, the write c) Write 0x55 to NVMKEY. initiate sequence for NVMKEY must be used to allow d) Write 0xAA to NVMKEY. any erase or program operation to proceed. After the e) Set the WR bit (NVMCON<15>). The erase programming command has been executed, the user cycle begins and the CPU stalls for the application must wait for the programming time until duration of the erase cycle. When the erase is programming is complete. The two instructions done, the WR bit is cleared automatically. following the start of the programming sequence should be NOPs, as shown in Example5-3. EXAMPLE 5-1: ERASING A PROGRAM MEMORY PAGE ; Set up NVMCON for block erase operation MOV #0x4042, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted © 2007-2012 Microchip Technology Inc. DS70283K-page 59

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch • (cid:129) (cid:129) ; 63rd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch EXAMPLE 5-3: INITIATING A PROGRAMMING SEQUENCE DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the NOP ; erase command is asserted DS70283K-page 60 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 6.0 RESETS A simplified block diagram of the Reset module is shown in Figure6-1. Note1: This data sheet summarizes the features Any active source of reset will make the SYSRST of the dsPIC33FJ32MC202/204 and signal active. On system Reset, some of the registers dsPIC33FJ16MC304 family of devices. It associated with the CPU and peripherals are forced to is not intended to be a comprehensive a known Reset state and some are unaffected. reference source. To complement the information in this data sheet, refer to Note: Refer to the specific peripheral section or Section 8. “Reset” (DS70192) of the Section3.0 “CPU” of this manual for “dsPIC33F/PIC24H Family Reference register Reset states. Manual”, which is available from the All types of device Reset sets a corresponding status Microchip web site (www.microchip.com). bit in the RCON register to indicate the type of Reset 2: Some registers and associated bits (see Register6-1). described in this section may not be A POR clears all the bits, except for the POR bit available on all devices. Refer to (RCON<0>), that are set. The user application can set Section4.0 “Memory Organization” in or clear any bit at any time during code execution. The this data sheet for device-specific register RCON bits only serve as status bits. Setting a particular and bit information. Reset status bit in software does not cause a device The Reset module combines all reset sources and Reset to occur. controls the device Master Reset Signal, SYSRST. The The RCON register also has other bits associated with following is a list of device Reset sources: the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections • POR: Power-on Reset of this manual. • BOR: Brown-out Reset • MCLR: Master Clear Pin Reset Note: The status bits in the RCON register should be cleared after they are read so • SWR: RESET Instruction that the next RCON register value after a • WDTO: Watchdog Timer Reset device Reset is meaningful. • CM: Configuration Mismatch Reset • TRAPR: Trap Conflict Reset • IOPUWR: Illegal Condition Device Reset - Illegal Opcode Reset - Uninitialized W Register Reset - Security Reset FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle BOR Internal Regulator SYSRST VDD VDD Rise POR Detect Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2007-2012 Microchip Technology Inc. DS70283K-page 61

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 6.1 Resets Resources Many useful resources are provided on the main prod- uct page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334 6.1.1 KEY RESOURCES • Section 8. “Reset” (DS70192) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70283K-page 62 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 6.2 Reset Control Registers REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 TRAPR IOPUWR — — — — CM VREGS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred bit 13-10 Unimplemented: Read as ‘0’ bit 9 CM: Configuration Mismatch Flag bit 1 = A configuration mismatch Reset has occurred 0 = A configuration mismatch Reset has NOT occurred bit 8 VREGS: Voltage Regulator Standby During Sleep bit 1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Standby mode during Sleep bit 7 EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2007-2012 Microchip Technology Inc. DS70283K-page 63

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70283K-page 64 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 6.3 System Reset A warm Reset is the result of all other reset sources, including the RESET instruction. On warm Reset, the The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 device will continue to operate from the current clock family of devices have two types of Reset: source as indicated by the Current Oscillator Selection • Cold Reset bits (COSC<2:0>) in the Oscillator Control register • Warm Reset (OSCCON<14:12>). A cold Reset is the result of a Power-on Reset (POR) The device is kept in a Reset state until the system or a Brown-out Reset (BOR). On a cold Reset, the power supplies have stabilized at appropriate levels FNOSC configuration bits in the FOSC device and the oscillator clock is ready. The sequence in configuration register selects the device clock source. which this occurs is shown in Figure6-2. TABLE 6-1: OSCILLATOR PARAMETERS Oscillator Oscillator Start-up Oscillator Mode PLL Lock Time Total Delay Start-up Delay Timer FRC, FRCDIV16, TOSCD — — TOSCD FRCDIVN FRCPLL TOSCD — TLOCK TOSCD + TLOCK XT TOSCD TOST — TOSCD + TOST HS TOSCD TOST — TOSCD + TOST EC — — — — XTPLL TOSCD TOST TLOCK TOSCD + TOST + TLOCK HSPLL TOSCD TOST TLOCK TOSCD + TOST + TLOCK ECPLL — — TLOCK TLOCK SOSC TOSCD TOST — TOSCD + TOST LPRC TOSCD — — TOSCD Note 1: TOSCD = Oscillator Start-up Delay (1.1μs max for FRC, 70μs max for LPRC). Crystal Oscillator start-up times vary with crystal characteristics, load capacitance, etc. 2: TOST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4μs for a 10MHz crystal and TOST=32ms for a 32kHz crystal. 3: TLOCK = PLL lock time (1.5ms nominal), if PLL is enabled. © 2007-2012 Microchip Technology Inc. DS70283K-page 65

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 6-2: SYSTEM RESET TIMING Vbor VBOR VPOR VDD TPOR 1 POR TBOR 2 BOR 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 TFSCM FSCM 5 Device Status Reset Run Time Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay TPOR has elapsed. 2: BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output becomes stable. 3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (TPWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay TPWRT has elapsed, the SYSRST becomes inactive, which in turn enables the selected oscillator to start generating clock cycles. 4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in Table6-1. Refer to Section8.0 “Oscillator Configuration” for more information. 5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay TFSCM elapsed. DS70283K-page 66 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 6-2: OSCILLATOR DELAY Symbol Parameter Value VPOR POR threshold 1.8V nominal TPOR POR extension time 30μs maximum VBOR BOR threshold 2.5V nominal TBOR BOR extension time 100μs maximum TPWRT Programmable power-up time delay 0-128ms nominal TFSCM Fail-Safe Clock Monitor Delay 900μs maximum 6.4.1 Brown-out Reset (BOR) and Note: When the device exits the Reset Power-up timer (PWRT) condition (begins normal operation), the device operating parameters (voltage, The on-chip regulator has a Brown-out Reset (BOR) frequency, temperature, etc.) must be circuit that resets the device when the VDD is too low within their operating ranges, other- (VDD < VBOR) for proper device operation. The BOR wise the device may not function cor- circuit keeps the device in Reset until VDD crosses rectly. The user application must VBOR threshold and the delay TBOR has elapsed. The ensure that the delay between the time delay TBOR ensures the voltage regulator output power is first applied, and the time becomes stable. SYSRST becomes inactive, is long enough to get all operating parameters The BOR status bit (BOR) in the Reset Control register within specification. (RCON<1>) is set to indicate the Brown-out Reset. The device will not run at full speed after a BOR as the 6.4 Power-on Reset (POR) VDD should rise to acceptable levels for full-speed operation. The PWRT provides power-up time delay A Power-on Reset (POR) circuit ensures the device is (TPWRT) to ensure that the system power supplies have reset from power-on. The POR circuit is active until stabilized at the appropriate levels for full-speed VDD crosses the VPOR threshold and the delay TPOR operation before the SYSRST is released. has elapsed. The delay TPOR ensures the internal The power-up timer delay (TPWRT) is programmed by device bias circuits become stable. the Power-on Reset Timer Value Select bits The device supply voltage characteristics must meet (FPWRT<2:0>) in the POR Configuration register the specified starting voltage and rise rate (FPOR<2:0>), which provides eight settings (from 0ms requirements to generate the POR. Refer to to 128ms). Refer to Section21.0 “Special Features” Section24.0 “Electrical Characteristics” for details. for further details. The POR status bit (POR) in the Reset Control register Figure6-3 shows the typical brown-out scenarios. The (RCON<0>) is set to indicate the Power-on Reset. reset delay (TBOR + TPWRT) is initiated each time VDD rises above the VBOR trip point © 2007-2012 Microchip Technology Inc. DS70283K-page 67

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 6-3: BROWN-OUT SITUATIONS VDD VBOR TBOR + TPWRT SYSRST VDD VBOR TBOR + TPWRT SYSRST VDD dips before PWRT expires VDD VBOR TBOR + TPWRT SYSRST 6.5 External Reset (EXTR) The Software Reset (Instruction) Flag (SWR) bit in the Reset Control register (RCON<6>) is set to indicate The external Reset is generated by driving the MCLR the software Reset. pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than 6.7 Watchdog Time-out Reset (WDTO) the minimum pulse-width will generate a Reset. Refer to Section24.0 “Electrical Characteristics” for Whenever a Watchdog time-out occurs, the device will minimum pulse-width specifications. The External asynchronously assert SYSRST. The clock source will Reset (MCLR) Pin (EXTR) bit in the Reset Control remain unchanged. A WDT time-out during Sleep or register (RCON) is set to indicate the MCLR Reset. Idle mode will wake-up the processor, but will not reset the processor. 6.5.1 EXTERNAL SUPERVISORY CIRCUIT The Watchdog Timer Time-out Flag bit (WDTO) in the Many systems have external supervisory circuits that Reset Control register (RCON<4>) is set to indicate generate reset signals to Reset multiple devices in the the Watchdog Reset. Refer to Section21.4 system. This external Reset signal can be directly “Watchdog Timer (WDT)” for more information on connected to the MCLR pin to Reset the device when Watchdog Reset. the rest of system is Reset. 6.8 Trap Conflict Reset 6.5.2 INTERNAL SUPERVISORY CIRCUIT If a lower-priority hard trap occurs while a When using the internal power supervisory circuit to higher-priority trap is being processed, a hard trap Reset the device, the external reset pin (MCLR) should conflict Reset occurs. The hard traps include be tied directly or resistively to VDD. In this case, the exceptions of priority level 13 through level 15, MCLR pin will not be used to generate a Reset. The inclusive. The address error (level13) and oscillator external reset pin (MCLR) does not have an internal error (level 14) traps fall into this category. pull-up and must not be left unconnected. The Trap Reset Flag bit (TRAPR) in the Reset Control register (RCON<15>) is set to indicate the Trap Conflict 6.6 Software RESET Instruction (SWR) Reset. Refer to Section7.0 “Interrupt Controller” for Whenever the RESET instruction is executed, the more information on trap conflict Resets. device will assert SYSRST, placing the device in a special Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST is released at the next instruction cycle, and the reset vector fetch will commence. DS70283K-page 68 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 6.9 Configuration Mismatch Reset each program memory section to store the data values. The upper 8 bits should be programmed with 3Fh, To maintain the integrity of the peripheral pin select which is an illegal opcode value. control registers, they are constantly monitored with shadow registers in hardware. If an unexpected 6.10.2 UNINITIALIZED W REGISTER change in any of the registers occur (such as cell RESET disturbances caused by ESD or other external events), a configuration mismatch Reset occurs. Any attempts to use the uninitialized W register as an address pointer will Reset the device. The W register The Configuration Mismatch Flag bit (CM) in the array (with the exception of W15) is cleared during all Reset Control register (RCON<9>) is set to indicate resets and is considered uninitialized until written to. the configuration mismatch Reset. Refer to Section10.0 “I/O Ports” for more information on the 6.10.3 SECURITY RESET configuration mismatch Reset. If a Program Flow Change (PFC) or Vector Flow Note: The configuration mismatch feature and Change (VFC) targets a restricted location in a associated reset flag is not available on all protected segment (Boot and Secure Segment), that devices. operation will cause a security Reset. The PFC occurs when the Program Counter is 6.10 Illegal Condition Device Reset reloaded as a result of a Call, Jump, Computed Jump, Return, Return from Subroutine, or other form of An illegal condition device Reset occurs due to the branch instruction. following sources: The VFC occurs when the Program Counter is • Illegal Opcode Reset reloaded with an Interrupt or Trap vector. • Uninitialized W Register Reset Refer to Section21.8 “Code Protection and • Security Reset CodeGuard™ Security” for more information on The Illegal Opcode or Uninitialized W Access Reset Security Reset. Flag bit (IOPUWR) in the Reset Control register (RCON<14>) is set to indicate the illegal condition 6.11 Using the RCON Status Bits device Reset. The user application can read the Reset Control regis- 6.10.1 ILLEGAL OPCODE RESET ter (RCON) after any device Reset to determine the cause of the reset. A device Reset is generated if the device attempts to execute an illegal opcode value that is fetched from Note: The status bits in the RCON register program memory. should be cleared after they are read so that the next RCON register value after a The illegal opcode Reset function can prevent the device Reset will be meaningful. device from executing program memory sections that are used to store constant data. To take advantage of Table6-3 provides a summary of the reset flag bit the illegal opcode Reset, use only the lower 16 bits of operation. TABLE 6-3: RESET FLAG BIT OPERATION Flag Bit Set by: Cleared by: TRAPR (RCON<15>) Trap conflict event POR,BOR IOPWR (RCON<14>) Illegal opcode or uninitialized POR,BOR W register access or Security Reset CM (RCON<9>) Configuration Mismatch POR,BOR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET instruction POR,BOR WDTO (RCON<4>) WDT time-out PWRSAV instruction, CLRWDT instruction, POR,BOR SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR,BOR IDLE (RCON<2>) PWRSAV #IDLE instruction POR,BOR BOR (RCON<1>) POR, BOR — POR (RCON<0>) POR — Note: All Reset flag bits can be set or cleared by user software. © 2007-2012 Microchip Technology Inc. DS70283K-page 69

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 70 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 7.0 INTERRUPT CONTROLLER Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the Note1: This data sheet summarizes the features vector table. Lower addresses generally have a higher of the dsPIC33FJ32MC202/204 and natural priority. For example, the interrupt associated dsPIC33FJ16MC304 devices. It is not with vector 0 will take priority over interrupts at any intended to be a comprehensive refer- other vector address. ence source. To complement the infor- dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 mation in this data sheet, refer to Section devices implement up to 26 unique interrupts and 4 32. “Interrupts (Part III)” (DS70214) of nonmaskable traps. These are summarized in the “dsPIC33F/PIC24H Family Reference Table7-1 and Table7-2. Manual”, which is available from the Microchip web site (www.microchip.com). 7.1.1 ALTERNATE INTERRUPT VECTOR 2: Some registers and associated bits TABLE described in this section may not be The Alternate Interrupt Vector Table (AIVT) is located available on all devices. Refer to after the IVT, as shown in Figure7-1. Access to the Section4.0 “Memory Organization” in AIVT is provided by the ALTIVT control bit this data sheet for device-specific register (INTCON2<15>). If the ALTIVT bit is set, all interrupt and bit information. and exception processes use the alternate vectors instead of the default vectors. The alternate vectors are The dsPIC33FJ32MC202/204 and organized in the same manner as the default vectors. dsPIC33FJ16MC304 interrupt controller reduces the numerous peripheral interrupt request signals to a The AIVT supports debugging by providing a means to single interrupt request signal to the switch between an application and a support dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 environment without requiring the interrupt vectors to CPU. It has the following features: be reprogrammed. This feature also enables switching between applications for evaluation of different • Up to 8 processor exceptions and software traps software algorithms at run time. If the AIVT is not • 7 user-selectable priority levels needed, the AIVT should be programmed with the • Interrupt Vector Table (IVT) with up to 118 vectors same addresses used in the IVT. • A unique vector for each interrupt or exception source 7.2 Reset Sequence • Fixed priority within a specified user priority level A device Reset is not a true exception because the • Alternate Interrupt Vector Table (AIVT) for debug interrupt controller is not involved in the Reset process. support The dsPIC33FJ32MC202/204 and • Fixed interrupt entry and return latencies dsPIC33FJ16MC304 device clears its registers in response to a Reset, which forces the PC to zero. The 7.1 Interrupt Vector Table digital signal controller then begins program execution at location 0x000000. A GOTO instruction at the Reset The Interrupt Vector Table (IVT) is shown in Figure7-1. address can redirect program execution to the The IVT resides in program memory, starting at location appropriate start-up routine. 000004h. The IVT contains 126 vectors consisting of 8nonmaskable trap vectors plus up to 118 sources of Note: Any unimplemented or unused vector interrupt. In general, each interrupt source has its own locations in the IVT and AIVT should be vector. Each interrupt vector contains a 24-bit-wide programmed with the address of a default address. The value programmed into each interrupt interrupt handler routine that contains a vector location is the starting address of the associated RESET instruction. Interrupt Service Routine (ISR). © 2007-2012 Microchip Technology Inc. DS70283K-page 71

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 7-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 INTERRUPT VECTOR TABLE Reset – GOTO Instruction 0x000000 Reset – GOTO Address 0x000002 Reserved 0x000004 Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 0x000014 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 0x00007C Interrupt Vector Table (IVT)(1) Interrupt Vector 53 0x00007E ority Interrupt ~Vector 54 0x000080 Pri ~ der ~ Or Interrupt Vector 116 0x0000FC al Interrupt Vector 117 0x0000FE atur Reserved 0x000100 N Reserved 0x000102 g n Reserved si a Oscillator Fail Trap Vector e cr Address Error Trap Vector e D Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 0x000114 Interrupt Vector 1 ~ ~ ~ Alternate Interrupt Vector Table (AIVT)(1) Interrupt Vector 52 0x00017C Interrupt Vector 53 0x00017E Interrupt Vector 54 0x000180 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 0x0001FE Start of Code 0x000200 Note 1: See Table7-1 for the list of implemented interrupt vectors. DS70283K-page 72 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 7-1: INTERRUPT VECTORS Interrupt Vector Request (IRQ) IVT Address AIVT Address Interrupt Source Number Number 8 0 0x000014 0x000114 INT0 – External Interrupt 0 9 1 0x000016 0x000116 IC1 – Input Capture 1 10 2 0x000018 0x000118 OC1 – Output Compare 1 11 3 0x00001A 0x00011A T1 – Timer1 12 4 0x00001C 0x00011C Reserved 13 5 0x00001E 0x00011E IC2 – Input Capture 2 14 6 0x000020 0x000120 OC2 – Output Compare 2 15 7 0x000022 0x000122 T2 – Timer2 16 8 0x000024 0x000124 T3 – Timer3 17 9 0x000026 0x000126 SPI1E – SPI1 Error 18 10 0x000028 0x000128 SPI1 – SPI1 Transfer Done 19 11 0x00002A 0x00012A U1RX – UART1 Receiver 20 12 0x00002C 0x00012C U1TX – UART1 Transmitter 21 13 0x00002E 0x00012E ADC1 – ADC1 22-23 14-15 0x000030-0x000032 0x000130-0x000132 Reserved 24 16 0x000034 0x000134 SI2C1 – I2C1 Slave Events 25 17 0x000036 0x000136 MI2C1 – I2C1 Master Events 26 18 0x000038 0x000138 Reserved 27 19 0x00003A 0x00013A Change Notification Interrupt 28 20 0x00003C 0x00013C INT1 – External Interrupt 1 29 21 0x00003E 0x00013E Reserved 30 22 0x000040 0x000140 IC7 – Input Capture 7 31 23 0x000042 0x000142 IC8 – Input Capture 8 32-36 24-28 0x000044-0x00004C 0x000144-0x00014C Reserved 37 29 0x00004E 0x00014E INT2 – External Interrupt 2 38-64 30-56 0x000050-0x000084 0x000150-0x000184 Reserved 65 57 0x000086 0x000186 PWM1 – PWM1 Period Match 66 58 0x000088 0x000188 QEI – Position Counter Compare 67-70 59-62 0x00008A-0x000090 0x00018A-0x000190 Reserved 71 63 0x000092 0x000192 FLTA1 – PWM1 Fault A 72 64 0x000094 0x000194 Reserved 73 65 0x000096 0x000196 U1E – UART1 Error 74-80 66-72 0x000098-0x0000A4 0x000198-0x0001A4 Reserved 81 73 0x0000A6 0x0001A6 PWM2 – PWM2 Period Match 82 74 0x0000A8 0x0001A8 FLTA2 – PWM2 Fault A 83-125 75-117 0x0000AA-0x0000FE 0x0001AA-0x0001FE Reserved TABLE 7-2: TRAP VECTORS Vector Number IVT Address AIVT Address Trap Source 0 0x000004 0x000104 Reserved 1 0x000006 0x000106 Oscillator Failure 2 0x000008 0x000108 Address Error 3 0x00000A 0x00010A Stack Error 4 0x00000C 0x00010C Math Error 5 0x00000E 0x00010E Reserved 6 0x000010 0x000110 Reserved 7 0x000012 0x000112 Reserved © 2007-2012 Microchip Technology Inc. DS70283K-page 73

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 7.3 Interrupt Resources 7.4.2 IFSx Many useful resources are provided on the main prod- The IFS registers maintain all of the interrupt request uct page of the Microchip web site for the devices listed flags. Each source of interrupt has a status bit, which is in this data sheet. This product page, which can be set by the respective peripherals or external signal and accessed using this link, contains the latest updates is cleared via software. and additional information. 7.4.3 IECx Note: In the event you are not able to access The IEC registers maintain all of the interrupt enable the product page using the link above, bits. These control bits are used to individually enable enter this URL in your browser: interrupts from the peripherals or external signals. http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334 7.4.4 IPCx 7.3.1 KEY RESOURCES The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt • Section 6. “Interrupts” (DS70184) source can be assigned to one of eight priority levels. • Code Samples 7.4.5 INTTREG • Application Notes • Software Libraries The INTTREG register contains the associated • Webinars interrupt vector number and the new CPU interrupt priority level, which are latched into vector number • All related dsPIC33F/PIC24H Family Reference (VECNUM<6:0>) and Interrupt level bit (ILR<3:0>) Manuals Sections fields in the INTTREG register. The new interrupt • Development Tools priority level is the priority of the pending interrupt. 7.4 Interrupt Control and Status The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are Registers listed in Table7-1. For example, the INT0 (External dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Interrupt 0) is shown as having vector number 8 and a devices implement a total of 22 registers for the natural order priority of 0. Thus, the INT0IF bit is found interrupt controller: in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP bits in the first position of IPC0 (IPC0<2:0>). • INTCON1 • INTCON2 7.4.6 STATUS/CONTROL REGISTERS • IFSx Although they are not specifically part of the interrupt • IECx control hardware, two of the CPU Control registers • IPCx contain bits that control interrupt functionality. • INTTREG • The CPU STATUS register, SR, contains the IPL<2:0> bits (SR<7:5>). These bits indicate the 7.4.1 INTCON1 AND INTCON2 current CPU interrupt priority level. The user can Global interrupt control functions are controlled from change the current CPU priority level by writing to INTCON1 and INTCON2. INTCON1 contains the the IPL bits. Interrupt Nesting Disable bit (NSTDIS) as well as the • The CORCON register contains the IPL3 bit control and status flags for the processor trap sources. which, together with IPL<2:0>, also indicates the The INTCON2 register controls the external interrupt current CPU priority level. IPL3 is a read-only bit request signal behavior and the use of the Alternate so that trap events cannot be masked by the user Interrupt Vector Table. software. All Interrupt registers are described in Register7-1 through Register7-24 in the following pages. DS70283K-page 74 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-1: SR: CPU STATUS REGISTER(1) R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: For complete register details, see Register 3-1: “SR: CPU STATUS Register”. 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1. REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT DL<2:0> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less Note 1: For complete register details, see Register 3-2: “CORCON: CORE Control Register”. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. © 2007-2012 Microchip Technology Inc. DS70283K-page 75

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14 OVAERR: Accumulator A Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A bit 13 OVBERR: Accumulator B Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B bit 10 OVATE: Accumulator A Overflow Trap Enable bit 1 = Trap overflow of Accumulator A 0 = Trap disabled bit 9 OVBTE: Accumulator B Overflow Trap Enable bit 1 = Trap overflow of Accumulator B 0 = Trap disabled bit 8 COVTE: Catastrophic Overflow Trap Enable bit 1 = Trap on catastrophic overflow of Accumulator A or B enabled 0 = Trap disabled bit 7 SFTACERR: Shift Accumulator Error Status bit 1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift bit 6 DIV0ERR: Arithmetic Error Status bit 1 = Math error trap was caused by a divide by zero 0 = Math error trap was not caused by a divide by zero bit 5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred DS70283K-page 76 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. DS70283K-page 77

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table 0 = Use standard (default) vector table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-3 Unimplemented: Read as ‘0’ bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge DS70283K-page 78 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 SPI1EIF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 Unimplemented: Read as ‘0’ bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007-2012 Microchip Technology Inc. DS70283K-page 79

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70283K-page 80 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — INT2IF — — — — — bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 IC8IF IC7IF — INT1IF CNIF — MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-8 Unimplemented: Read as ‘0’ bit 7 IC8IF: Input Capture Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 IC7IF: Input Capture Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 Unimplemented: Read as ‘0’ bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007-2012 Microchip Technology Inc. DS70283K-page 81

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-7: IFS3: INTERRUPT FLAG STATUS REGISTER 3 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 FLTA1IF — — — — QEIIF PWM1IF — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTA1IF: PWM1 Fault A Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14-11 Unimplemented: Read as ‘0’ bit 10 QEIIF: QEI Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 PWM1IF: PWM1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’ DS70283K-page 82 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-8: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — FLTA2IF PWM2IF — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — U1EIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 FLTA2IF: PWM2 Fault A Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 PWM2IF: PWM2 Error Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-2 Unimplemented: Read as ‘0’ bit 1 U1EIF: UART1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. DS70283K-page 83

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-9: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 SPI1IE: SPI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 SPI1EIE: SPI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 Unimplemented: Read as ‘0’ bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70283K-page 84 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-9: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007-2012 Microchip Technology Inc. DS70283K-page 85

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-10: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — INT2IE — — — — — bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 IC8IE IC7IE — INT1IE CNIE — MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12-8 Unimplemented: Read as ‘0’ bit 7 IC8IE: Input Capture Channel 8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 IC7IE: Input Capture Channel 7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 Unimplemented: Read as ‘0’ bit 4 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70283K-page 86 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-11: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 FLTA1IE — — — — QEIIE PWM1IE — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTA1IE: PWM1 Fault A Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 14-11 Unimplemented: Read as ‘0’ bit 10 QEIIE: QEI Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 PWM1IE: PWM1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8-0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. DS70283K-page 87

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-12: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — FLA2IE PWM2IE — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — U1EIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 FLA2IE: PWM2 Fault A Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 PWM2IE: PWM2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ DS70283K-page 88 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-13: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP<2:0> — OC1IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP<2:0> — INT0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007-2012 Microchip Technology Inc. DS70283K-page 89

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-14: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP<2:0> — OC2IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC2IP<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70283K-page 90 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-15: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP<2:0> — SPI1IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI1EIP<2:0> — T3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007-2012 Microchip Technology Inc. DS70283K-page 91

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-16: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP<2:0> — U1TXIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70283K-page 92 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-17: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CNIP<2:0> — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP<2:0> — SI2C1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007-2012 Microchip Technology Inc. DS70283K-page 93

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-18: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC8IP<2:0> — IC7IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70283K-page 94 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-19: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT2IP<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. DS70283K-page 95

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 7-20: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — QEIIP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — PWM1IP<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 10-8 QEIIP<2:0>: QEI Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70283K-page 96 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-21: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — FLTA1IP<2:0> — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 FLTA1IP<2:0>: PWM1 Fault A Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’ REGISTER 7-22: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1EIP<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. DS70283K-page 97

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-23: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — FLTA2IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — PWM2IP<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 8-10 FLTA2IP<2:0>: PWM2 Fault A Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 PWM2IP<2:0>: PWM2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70283K-page 98 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-24: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ILR<3:0> bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 © 2007-2012 Microchip Technology Inc. DS70283K-page 99

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 7.5 Interrupt Setup Procedures 7.5.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, 7.5.1 INITIALIZATION except that the appropriate trap status flag in the To configure an interrupt source at initialization: INTCON1 register must be cleared to avoid re-entry into the TSR. 1. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. 7.5.4 INTERRUPT DISABLE 2. Select the user-assigned priority level for the All user interrupts can be disabled using this interrupt source by writing the control bits in the procedure: appropriate IPCx register. The priority level will depend on the specific application and type of 1. Push the current SR value onto the software interrupt source. If multiple priority levels are not stack using the PUSH instruction. desired, the IPCx register control bits for all 2. Force the CPU to priority level 7 by inclusive enabled interrupt sources can be programmed ORing the value OEh with SRL. to the same non-zero value. To enable user interrupts, the POP instruction can be Note: At a device Reset, the IPCx registers are used to restore the previous SR value. initialized such that all user interrupt sources are assigned to priority level 4. Note: Only user interrupts with a priority level of 7 or lower can be disabled. Trap sources 3. Clear the interrupt flag status bit associated with (level 8-level 15) cannot be disabled. the peripheral in the associated IFSx register. 4. Enable the interrupt source by setting the The DISI instruction provides a convenient way to interrupt enable control bit associated with the disable interrupts of priority levels 1-6 for a fixed period source in the appropriate IECx register. of time. Level 7 interrupt sources are not disabled by the DISI instruction. 7.5.2 INTERRUPT SERVICE ROUTINE The method used to declare an Interrupt Service Rou- tine (ISR) and initialize the IVT with the correct vector address depends on the programming language (C or assembler) and the language development tool suite used to develop the application. In general, the user application must clear the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, program will re-enter the ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. DS70283K-page 100 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 8.0 OSCILLATOR The oscillator system for dsPIC33FJ32MC202/204 and CONFIGURATION dsPIC33FJ16MC304 devices provides: • External and internal oscillator options as clock Note1: This data sheet summarizes the features sources. of the dsPIC33FJ32MC202/204 and • An on-chip Phase-Locked Loop (PLL) to scale the dsPIC33FJ16MC304 devices. It is not internal operating frequency to the required intended to be a comprehensive refer- system clock frequency. ence source. To complement the infor- • An internal FRC oscillator that can also be used mation in this data sheet, refer to Section with the PLL, thereby allowing full-speed 7. “Oscillator” (DS70186) of the operation without any external clock generation dsPIC33F/PIC24H Family Reference hardware. Manual”, which is available from the • Clock switching between various clock sources. Microchip web site (www.microchip.com). • Programmable clock postscaler for system power savings. 2: Some registers and associated bits • A Fail-Safe Clock Monitor (FSCM) that detects described in this section may not be clock failure and takes fail-safe measures. available on all devices. Refer to Section4.0 “Memory Organization” in • A Clock Control register (OSCCON). this data sheet for device-specific register • Nonvolatile Configuration bits for main oscillator and bit information. selection. A simplified diagram of the oscillator system is shown in Figure8-1. FIGURE 8-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator (POSC) OSC1 XT, HS, EC DOZE<2:0> S2 R(2) S3 XTPLL, HSPLL, S1 PLL(1) ECPLL, FRCPLL S1/S3 ZE FCY(3) O OSC2 D POSCMD<1:0> FP(3) OsFcRillCator CDIV FRCDIVN S7 ÷ 2 R F FOSC FRCDIV<2:0> TUN<5:0> FRCDIV16 S6 ÷ 16 FRC S0 LPRC LPRC S5 Oscillator Secondary Oscillator (SOSC) SOSC SOSCO S4 LPOSCEN SOSCI Clock Fail Clock Switch Reset S7 NOSC<2:0> FNOSC<2:0> WDT, PWRT, FSCM Timer 1 Note 1: See Figure8-2 for PLL details. 2: If the Oscillator is used with XT or HS modes, an external parallel resistor with the value of 1MΩmust be connected. 3: The term FP refers to the clock source for all of the peripherals, while FCY refers to the clock source for the CPU. Throughout this document, FCY and FP are used interchangeably, except in the case of DOZE mode. FP and FCY will be different when DOZE mode is used with any ratio other than 1:1 which is the default. © 2007-2012 Microchip Technology Inc. DS70283K-page 101

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 8.1 CPU Clocking System 8.1.2 SYSTEM CLOCK SELECTION The dsPIC33FJ32MC202/204 and The oscillator source used at a device Power-on dsPIC33FJ16MC304 devices provide seven system Reset event is selected using Configuration bit clock options: settings. The oscillator Configuration bit settings are located in the Configuration registers in the program • Fast RC (FRC) Oscillator memory. (Refer to Section21.1 “Configuration • FRC Oscillator with PLL Bits” for further details.) The Initial Oscillator • Primary (XT, HS or EC) Oscillator Selection Configuration bits, FNOSC<2:0> • Primary Oscillator with PLL (FOSCSEL<2:0>), and the Primary Oscillator Mode Select Configuration bits, POSCMD<1:0> • Secondary (LP) Oscillator (FOSC<1:0>), select the oscillator source that is used • Low-Power RC (LPRC) Oscillator at a Power-on Reset. The FRC primary oscillator is • FRC Oscillator with postscaler the default (unprogrammed) selection. 8.1.1 SYSTEM CLOCK SOURCES The Configuration bits allow users to choose among 12 different clock modes, shown in Table8-1. 8.1.1.1 Fast RC The output of the oscillator (or the output of the PLL if The Fast RC (FRC) internal oscillator runs at a nominal a PLL mode has been selected) FOSC is divided by 2 to frequency of 7.37 MHz. User software can tune the generate the device instruction clock (FCY) and the FRC frequency. User software can optionally specify a peripheral clock time base (FP). FCY defines the factor (ranging from 1:2 to 1:256) by which the FRC operating speed of the device, and speeds up to 40 clock frequency is divided. This factor is selected using MHz are supported by the dsPIC33FJ32MC202/204 the FRCDIV<2:0> bits (CLKDIV<10:8>). and dsPIC33FJ16MC304 architecture. 8.1.1.2 Primary Instruction execution speed or device operating frequency, FCY, is given by: The primary oscillator can use one of the following as its clock source: EQUATION 8-1: DEVICE OPERATING FREQUENCY • XT (Crystal): Crystals and ceramic resonators in the range of 3 MHz to 10 MHz. The crystal is connected to the OSC1 and OSC2 pins. FCY = F----O----S---C-- 2 • HS (High-Speed Crystal): Crystals in the range of 10 MHz to 40 MHz. The crystal is connected to the OSC1 and OSC2 pins. 8.1.3 PLL CONFIGURATION • EC (External Clock): The external clock signal is The primary oscillator and internal FRC oscillator can directly applied to the OSC1 pin. optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in 8.1.1.3 Secondary selecting the device operating speed. A block diagram The secondary (LP) oscillator is designed for low power of the PLL is shown in Figure8-2. and uses a 32.768 kHz crystal or ceramic resonator. The output of the primary oscillator or FRC, denoted as The LP oscillator uses the SOSCI and SOSCO pins. ‘FIN’, is divided down by a prescale factor (N1) of 2, 3, ... or 33 before being provided to the PLL’s Voltage 8.1.1.4 Low-Power RC Controlled Oscillator (VCO). The input to the VCO must The LPRC (Low-Power RC) internal oscIllator runs at a be selected in the range of 0.8 MHz to 8 MHz. The nominal frequency of 32.768 kHz. It is also used as a prescale factor ‘N1’ is selected using the reference clock by the Watchdog Timer (WDT) and PLLPRE<4:0> bits (CLKDIV<4:0>). Fail-Safe Clock Monitor (FSCM). The PLL Feedback Divisor, selected using the PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M’, 8.1.1.5 FRC by which the input to the VCO is multiplied. This factor The clock signals generated by the FRC and primary must be selected such that the resulting VCO output oscillators can be optionally applied to an on-chip frequency is in the range of 100 MHz to 200 MHz. Phase Locked Loop (PLL) to provide a wide range of The VCO output is further divided by a postscale factor output frequencies for device operation. PLL ‘N2.’ This factor is selected using the PLLPOST<1:0> configuration is described in Section8.1.3 “PLL bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and Configuration”. must be selected such that the PLL output frequency The FRC frequency depends on the FRC accuracy (FOSC) is in the range of 12.5 MHz to 80 MHz, which (see Table24-18) and the value of the FRC Oscillator generates device operating speeds of 6.25-40 MIPS. Tuning register (see Register8-4). DS70283K-page 102 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 For a primary oscillator or FRC oscillator, output ‘FIN’, • If PLLDIV<8:0> = 0x1E, then the PLL output ‘FOSC’ is given by: M = 32. This yields a VCO output of 5 x 32 = 160 MHz, which is within the 100-200 MHz ranged EQUATION 8-2: FOSC CALCULATION needed. • If PLLPOST<1:0> = 0, then N2 = 2. This provides ⎛ M ⎞ FOSC = FIN⋅ ⎝N-----1----⋅------N----2---⎠ a Fosc of 160/2 = 80 MHz. The resultant device operating speed is 80/2 = 40 MIPS. For example, suppose a 10 MHz crystal is being used EQUATION 8-3: XT WITH PLL MODE with the selected oscillator mode of XT with PLL. EXAMPLE • If PLLPRE<4:0> = 0, then N1 = 2. This yields a VacCcOep itnapbulet oraf n1g0e/2 o =f 05. 8M-H8 zM, Hwzh.ich is within the FCY = F----O--2--S---C-- = 12---⋅ ⎝⎛1---0----0---0--0-2--0--⋅-0---0--2---⋅------3---2--⎠⎞ =40 MIPS FIGURE 8-2: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PLL BLOCK DIAGRAM FVCO 0.8-8.0 MHz 12.5-80 MHz Here(1) 100H-2e0re0( 1M)Hz Here(1) Source (Crystal, External Clock or Internal RC) PLLPRE X VCO PLLPOST FOSC PLLDIV N1 N2 Divide by Divide by 2-33 M 2, 4, 8 Divide by 2-513 Note1: This frequency range must be satisfied at all times. TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> See Note Fast RC Oscillator with Divide-by-N Internal xx 111 1, 2 (FRCDIVN) Fast RC Oscillator with Divide-by-16 Internal xx 110 1 (FRCDIV16) Low-Power RC Oscillator (LPRC) Internal xx 101 1 Secondary (Timer1) Oscillator (Sosc) Secondary xx 100 1 Primary Oscillator (HS) with PLL Primary 10 011 — (HSPLL) Primary Oscillator (XT) with PLL Primary 01 011 — (XTPLL) Primary Oscillator (EC) with PLL Primary 00 011 1 (ECPLL) Primary Oscillator (HS) Primary 10 010 — Primary Oscillator (XT) Primary 01 010 — Primary Oscillator (EC) Primary 00 010 1 Fast RC Oscillator with PLL (FRCPLL) Internal xx 001 1 Fast RC Oscillator (FRC) Internal xx 000 1 Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2007-2012 Microchip Technology Inc. DS70283K-page 103

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 8.2 Oscillator Resources Many useful resources are provided on the main prod- uct page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334 8.2.1 KEY RESOURCES • Section 7. “Oscillator” (DS70186) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70283K-page 104 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 8.3 Oscillator Control Registers REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,3) U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y — COSC<2:0> — NOSC<2:0>(2) bit 15 bit 8 R/W-0 R/W-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0 CLKLOCK IOLOCK LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only) 111 = Fast RC oscillator (FRC) with Divide-by-n 110 = Fast RC oscillator (FRC) with Divide-by-16 101 = Low-Power RC oscillator (LPRC) 100 = Secondary oscillator (Sosc) 011 = Primary oscillator (XT, HS, EC) with PLL 010 = Primary oscillator (XT, HS, EC) 001 = Fast RC oscillator (FRC) with PLL 000 = Fast RC oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2) 111 = Fast RC oscillator (FRC) with Divide-by-n 110 = Fast RC oscillator (FRC) with Divide-by-16 101 = Low-Power RC oscillator (LPRC) 100 = Secondary oscillator (Sosc) 011 = Primary oscillator (XT, HS, EC) with PLL 010 = Primary oscillator (XT, HS, EC) 001 = Fast RC oscillator (FRC) with PLL 000 = Fast RC oscillator (FRC) bit 7 CLKLOCK: Clock Lock Enable bit If clock switching is enabled and FSCM is disabled, (FOSC<FCKSM> = 0b01) 1 = Clock switching is disabled, system clock source is locked 0 = Clock switching is enabled, system clock source can be modified by clock switching bit 6 IOLOCK: Peripheral Pin Select Lock bit 1 = Peripherial pin select is locked, write to peripheral pin select registers not allowed 0 = Peripherial pin select is not locked, write to peripheral pin select registers allowed bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled bit 4 Unimplemented: Read as ‘0’ Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70186) in the “dsPIC33F/PIC24H Family Reference Manual” for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). © 2007-2012 Microchip Technology Inc. DS70283K-page 105

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,3) (CONTINUED) bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70186) in the “dsPIC33F/PIC24H Family Reference Manual” for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). DS70283K-page 106 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER(2) R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 ROI DOZE<2:0> DOZEN(1) FRCDIV<2:0> bit 15 bit 8 R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PLLPOST<1:0> — PLLPRE<4:0> bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits 111 = FCY/128 110 = FCY/64 101 = FCY/32 100 = FCY/16 011 = FCY/8 (default) 010 = FCY/4 001 = FCY/2 000 = FCY/1 bit 11 DOZEN: DOZE Mode Enable bit(1) 1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock/peripheral clock ratio forced to 1:1 bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits 111 = FRC divide by 256 110 = FRC divide by 64 101 = FRC divide by 32 100 = FRC divide by 16 011 = FRC divide by 8 010 = FRC divide by 4 001 = FRC divide by 2 000 = FRC divide by 1 (default) bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler) 11 = Output/8 10 = Reserved 01 = Output/4 (default) 00 = Output/2 bit 5 Unimplemented: Read as ‘0’ bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 • • • 11111 = Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. 2: This register is reset only on a Power-on Reset (POR). © 2007-2012 Microchip Technology Inc. DS70283K-page 107

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 8-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV<8> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 Note 1: This register is reset only on a Power-on Reset (POR). DS70283K-page 108 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER(2) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Center frequency + 11.625% (8.23 MHz) 011110 = Center frequency + 11.25% (8.20 MHz) • • • 000001 = Center frequency + 0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency -0.375% (7.345 MHz) • • • 100001 = Center frequency -11.625% (6.52 MHz) 100000 = Center frequency -12% (6.49 MHz) Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. 2: This register is reset only on a Power-on Reset (POR). © 2007-2012 Microchip Technology Inc. DS70283K-page 109

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 8.4 Clock Switching Operation 2. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and the CF Applications are free to switch among any of the four (OSCCON<3>) status bits are cleared. clock sources (Primary, LP, FRC and LPRC) under 3. The new oscillator is turned on by the hardware software control at any time. To limit the possible side if it is not currently running. If a crystal oscillator effects of this flexibility, dsPIC33FJ32MC202/204 and must be turned on, the hardware waits until the dsPIC33FJ16MC304 devices have a safeguard lock Oscillator Start-up Timer (OST) expires. If the built into the switch process. new source is using the PLL, the hardware waits Note: Primary Oscillator mode has three different until a PLL lock is detected (LOCK = 1). submodes (XT, HS and EC), which are 4. The hardware waits for 10 clock cycles from the determined by the POSCMD<1:0> new clock source and then performs the clock Configuration bits. While an application switch. can switch to and from Primary Oscillator 5. The hardware clears the OSWEN bit to indicate a mode in software, it cannot switch among successful clock transition. In addition, the NOSC the different primary submodes without bit values are transferred to the COSC status bits. reprogramming the device. 6. The old clock source is turned off at this time, 8.4.1 ENABLING CLOCK SWITCHING with the exception of LPRC (if WDT or FSCM are enabled) or LP (if LPOSCEN remains set). To enable clock switching, the FCKSM1 Configuration bit in the Configuration register must be programmed to Note1: The processor continues to execute code ‘0’. (Refer to Section21.1 “Configuration Bits” for throughout the clock switching sequence. further details.) If the FCKSM1 Configuration bit is Timing-sensitive code should not be unprogrammed (‘1’), the clock switching function and executed during this time. Fail-Safe Clock Monitor function are disabled. This is 2: Direct clock switches between any pri- the default setting. mary oscillator mode with PLL and The NOSC control bits (OSCCON<10:8>) do not FRCPLL mode are not permitted. This control the clock selection when clock switching is applies to clock switches in either direc- disabled. However, the COSC bits (OSCCON<14:12>) tion. In these instances, the application reflect the clock source selected by the FNOSC must switch to FRC mode as a transition Configuration bits. clock source between the two PLL modes. The OSWEN control bit (OSCCON<0>) has no effect 3: Refer to Section 7. “Oscillator” when clock switching is disabled. It is held at ‘0’ at all (DS70186) in the “dsPIC33F/PIC24H times. Family Reference Manual” for details. 8.4.2 OSCILLATOR SWITCHING 8.5 Fail-Safe Clock Monitor (FSCM) SEQUENCE The Fail-Safe Clock Monitor (FSCM) allows the device Performing a clock switch requires this basic to continue to operate even in the event of an oscillator sequence: failure. The FSCM function is enabled by programming. 1. If desired, read the COSC bits If the FSCM function is enabled, the LPRC internal (OSCCON<14:12>) to determine the current oscillator runs at all times (except during Sleep mode) oscillator source. and is not subject to control by the Watchdog Timer. 2. Perform the unlock sequence to allow a write to In the event of an oscillator failure, the FSCM the OSCCON register high byte. generates a clock failure trap event and switches the 3. Write the appropriate value to the NOSC control system clock over to the FRC oscillator. Then the bits (OSCCON<10:8>) for the new oscillator application program can either attempt to restart the source. oscillator or execute a controlled shutdown. The trap 4. Perform the unlock sequence to allow a write to can be treated as a warm Reset by simply loading the the OSCCON register low byte. Reset address into the oscillator fail trap vector. 5. Set the OSWEN bit (OSCCON<0>) to initiate If the PLL multiplier is used to scale the system clock, the oscillator switch. the internal FRC is also multiplied by the same factor Once the basic sequence is completed, the system on clock failure. Essentially, the device switches to clock hardware responds automatically as follows: FRC with PLL on a clock failure. 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits. If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. DS70283K-page 110 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 9.0 POWER-SAVING FEATURES 9.2 Instruction-Based Power-Saving Modes Note1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 dsPIC33FJ16MC304 devices. It is not devices have two special power-saving modes that are intended to be a comprehensive entered through the execution of a special PWRSAV reference source. To complement the instruction. Sleep mode stops clock operation and halts information in this data sheet, refer to all code execution. Idle mode halts the CPU and code Section 9. “Watchdog Timer and execution, but allows peripheral modules to continue Power-Saving Modes” (DS70196) the operation. The assembler syntax of the PWRSAV “dsPIC33F/PIC24H Family Reference instruction is shown in Example9-1. Manual”, which is available from the Note: SLEEP_MODE and IDLE_MODE are con- Microchip web site (www.microchip.com). stants defined in the assembler include 2: Some registers and associated bits file for the selected device. described in this section may not be Sleep and Idle modes can be exited as a result of an available on all devices. Refer to enabled interrupt, WDT time-out or a device Reset. When Section4.0 “Memory Organization” in the device exits these modes, it is said to wake-up. this data sheet for device-specific register and bit information. 9.2.1 SLEEP MODE The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 The following occur in Sleep mode: devices provide the ability to manage power consumption • The system clock source is shut down. If an by selectively managing clocking to the CPU and the on-chip oscillator is used, it is turned off. peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked • The device current consumption is reduced to a constitutes lower consumed power. minimum, provided that no I/O pin is sourcing dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 current. devices can manage power consumption in four different • The Fail-Safe Clock Monitor does not operate, ways: since the system clock source is disabled. • Clock frequency • The LPRC clock continues to run in Sleep mode if the WDT is enabled. • Instruction-based Sleep and Idle modes • The WDT, if enabled, is automatically cleared • Software-controlled Doze mode prior to entering Sleep mode. • Selective peripheral control in software • Some device features or peripherals may continue Combinations of these methods can be used to selec- to operate. This includes items such as the input tively tailor an application’s power consumption while change notification on the I/O ports, or peripherals still maintaining critical application features, such as that use an external clock input. timing-sensitive communications. • Any peripheral that requires the system clock source for its operation is disabled. 9.1 Clock Frequency and Clock The device will wake-up from Sleep mode on any of the Switching these events: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 • Any interrupt source that is individually enabled devices allow a wide range of clock frequencies to be • Any form of device Reset selected under application control. If the system clock • A WDT time-out configuration is not locked, users can choose low-power or high-precision oscillators by simply On wake-up from Sleep mode, the processor restarts changing the NOSC bits (OSCCON<10:8>). The with the same clock source that was active when Sleep process of changing a system clock during operation, mode was entered. as well as limitations to the process, are discussed in more detail in Section8.0 “Oscillator Configuration”. EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2007-2012 Microchip Technology Inc. DS70283K-page 111

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 9.2.2 IDLE MODE Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core The following occur in Idle mode: clock speed is determined by the DOZE<2:0> bits • The CPU stops executing instructions. (CLKDIV<14:12>). There are eight possible • The WDT is automatically cleared. configurations, from 1:1 to 1:128, with 1:1 being the • The system clock source remains active. By default setting. default, all peripheral modules continue to operate Programs can use Doze mode to selectively reduce normally from the system clock source, but can power consumption in event-driven applications. This also be selectively disabled (see Section9.4 allows clock-sensitive functions, such as synchronous “Peripheral Module Disable”). communications, to continue without interruption while • If the WDT or FSCM is enabled, the LPRC also the CPU idles, waiting for something to invoke an remains active. interrupt routine. An automatic return to full-speed CPU operation on interrupts can be enabled by setting the The device will wake from Idle mode on any of these ROI bit (CLKDIV<15>). By default, interrupt events events: have no effect on Doze mode operation. • Any interrupt that is individually enabled For example, suppose the device is operating at • Any device Reset 20MIPS and the CAN module has been configured for • A WDT time-out 500 kbps based on this device operating speed. If the On wake-up from Idle mode, the clock is reapplied to device is placed in Doze mode with a clock frequency the CPU and instruction execution will begin (2-4 ratio of 1:4, the CAN module continues to communicate cycles later), starting with the instruction following the at the required bit rate of 500 kbps, but the CPU now PWRSAV instruction, or the first instruction in the ISR. starts executing instructions at a frequency of 5 MIPS. 9.2.3 INTERRUPTS COINCIDENT WITH 9.4 Peripheral Module Disable POWER SAVE INSTRUCTIONS The Peripheral Module Disable registers (PMD) Any interrupt that coincides with the execution of a provide a method to disable a peripheral module by PWRSAV instruction is held off until entry into Sleep or stopping all clock sources supplied to that module. Idle mode has completed. The device then wakes up When a peripheral is disabled using the appropriate from Sleep or Idle mode. PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers 9.3 Doze Mode associated with the peripheral are also disabled, so writes to those registers will have no effect and read The preferred strategies for reducing power values will be invalid. consumption are changing clock speed and invoking one of the power-saving modes. In some A peripheral module is enabled only if both the circumstances, this may not be practical. For example, associated bit in the PMD register is cleared and the it may be necessary for an application to maintain peripheral is supported by the specific dsPIC® DSC uninterrupted synchronous communication, even while variant. If the peripheral is present in the device, it is it is doing nothing else. Reducing system clock speed enabled in the PMD register by default. can introduce communication errors, while using a Note: If a PMD bit is set, the corresponding power-saving mode can stop communications module is disabled after a delay of one completely. instruction cycle. Similarly, if a PMD bit is Doze mode is a simple and effective alternative method cleared, the corresponding module is to reduce power consumption while the device is still enabled after a delay of one instruction executing code. In this mode, the system clock cycle (assuming the module control continues to operate from the same source and at the registers are already configured to enable same speed. Peripheral modules continue to be module operation). clocked at the same speed, while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. DS70283K-page 112 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 9.5 Power-Saving Resources Many useful resources are provided on the main prod- uct page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334 9.5.1 KEY RESOURCES • Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools © 2007-2012 Microchip Technology Inc. DS70283K-page 113

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 9.6 Power-Saving Control Registers REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — T3MD T2MD T1MD QEIMD PWM1MD — bit 15 bit 8 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 I2C1MD — U1MD — SPI1MD — — AD1MD(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 T3MD: Timer3 Module Disable bit 1 = Timer3 module is disabled 0 = Timer3 module is enabled bit 12 T2MD: Timer2 Module Disable bit 1 = Timer2 module is disabled 0 = Timer2 module is enabled bit 11 T1MD: Timer1 Module Disable bit 1 = Timer1 module is disabled 0 = Timer1 module is enabled bit 10 QEIMD: QEI Module Disable bit 1 = QEI module is disabled 0 = QEI module is enabled bit 9 PWM1MD: PWM1 Module Disable bit 1 = PWM1 module is disabled 0 = PWM1 module is enabled bit 8 Unimplemented: Read as ‘0’ bit 7 I2C1MD: I2C1 Module Disable bit 1 = I2C1 module is disabled 0 = I2C1 module is enabled bit 6 Unimplemented: Read as ‘0’ bit 5 U1MD: UART1 Module Disable bit 1 = UART1 module is disabled 0 = UART1 module is enabled bit 4 Unimplemented: Read as ‘0’ bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2-1 Unimplemented: Read as ‘0’ bit 0 AD1MD: ADC1 Module Disable bit(1) 1 = ADC1 module is disabled 0 = ADC1 module is enabled Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. In this case, all port pins multiplexed with ANx will be in Digital mode. DS70283K-page 114 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 IC8MD IC7MD — — — — IC2MD IC1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IC8MD: Input Capture 8 Module Disable bit 1 = Input Capture 8 module is disabled 0 = Input Capture 8 module is enabled bit 14 IC7MD: Input Capture 2 Module Disable bit 1 = Input Capture 7 module is disabled 0 = Input Capture 7 module is enabled bit 13-10 Unimplemented: Read as ‘0’ bit 9 IC2MD: Input Capture 2 Module Disable bit 1 = Input Capture 2 module is disabled 0 = Input Capture 2 module is enabled bit 8 IC1MD: Input Capture 1 Module Disable bit 1 = Input Capture 1 module is disabled 0 = Input Capture 1 module is enabled bit 7-2 Unimplemented: Read as ‘0’ bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled © 2007-2012 Microchip Technology Inc. DS70283K-page 115

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 — — — PWM2MD — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 PWM2MD: PWM2 Module Disable bit 1 = PWM2 module is disabled 0 = PWM2 module is enabled bit 3-0 Unimplemented: Read as ‘0’ DS70283K-page 116 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 10.0 I/O PORTS the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a Note1: This data sheet summarizes the features peripheral that shares the same pin. Figure10-1 shows of the dsPIC33FJ32MC202/204 and how ports are shared with other peripherals and the dsPIC33FJ16MC304 devices. It is not associated I/O pin to which they are connected. intended to be a comprehensive refer- When a peripheral is enabled and the peripheral is ence source. To complement the infor- actively driving an associated pin, the use of the pin as mation in this data sheet, refer to Section a general purpose output pin is disabled. The I/O pin 10. “I/O Ports” (DS70193) of the can be read, but the output driver for the parallel port bit “dsPIC33F/PIC24H Family Reference is disabled. If a peripheral is enabled, but the peripheral Manual”, which is available on Microchip is not actively driving a pin, that pin can be driven by a web site (www.microchip.com). port. 2: Some registers and associated bits All port pins have three registers directly associated described in this section may not be with their operation as digital I/O. The data direction available on all devices. Refer to register (TRISx) determines whether the pin is an input Section4.0 “Memory Organization” in this data sheet for device-specific register or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a and bit information. Reset. Reads from the latch (LATx) read the latch. All of the device pins (except VDD, VSS, MCLR and Writes to the latch write the latch. Reads from the port OSC1/CLKI) are shared among the peripherals and the (PORTx) read the port pins, while writes to the port pins parallel I/O ports. All I/O input ports feature Schmitt write the latch. Trigger inputs for improved noise immunity. Any bit and its associated data and control registers that are not valid for a particular device will be 10.1 Parallel I/O (PIO) Ports disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. Generally a parallel I/O port that shares a pin with a peripheral is subservient to the peripheral. The When a pin is shared with another peripheral or peripheral’s output buffer data and control signals are function that is defined as an input only, it is provided to a pair of multiplexers. The multiplexers nevertheless regarded as a dedicated port because select whether the peripheral or the associated port there is no other competing source of outputs. has ownership of the output data and control signals of FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data Read TRIS 0 Data Bus D Q I/O Pin WR TRIS CK TRIS Latch D Q WR LAT + CK WR Port Data Latch Read LAT Input Data Read Port © 2007-2012 Microchip Technology Inc. DS70283K-page 117

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 10.2 Open-Drain Configuration 10.4 I/O Port Write/Read Timing In addition to the PORT, LAT and TRIS registers for One instruction cycle is required between a port data control, some port pins can also be individually direction change or port write operation and a read configured for either digital or open-drain output. This is operation of the same port. Typically this instruction controlled by the Open-Drain Control register, ODCx, would be an NOP. Examples are shown in associated with each port. Setting any of the bits con- Example10-1 and Example10-2. This also applies to figures the corresponding pin to act as an open-drain PORT bit operations, such as BSET PORTB, # RB0, output. which are single cycle read-modify-write. All PORT bit operations, such as MOV PORTB, W0 or BSET PORTB, The open-drain feature allows the generation of # RBx, read the pin and not the latch. outputs higher than VDD (e.g., 5V) on any desired 5V tolerant pins by using external pull-up resistors. The 10.5 Input Change Notification maximum open-drain voltage allowed is the same as the maximum VIH specification. The input change notification function of the I/O ports See the “Pin Diagrams” section for the available pins allows the dsPIC33FJ32MC202/204 and and their functionality. dsPIC33FJ16MC304 devices to generate interrupt requests to the processor in response to a 10.3 Configuring Analog Port Pins change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, The AD1PCFG and TRIS registers control the opera- when the clocks are disabled. Depending on the device tion of the analog-to-digital (A/D) port pins. The port pin count, up to 31 external signals (CNx pin) can be pins that are to function as analog inputs must have selected (enabled) for generating an interrupt request their corresponding TRIS bit set (input). If the TRIS bit on a change-of-state. is cleared (output), the digital output level (VOH or VOL) Four control registers are associated with the CN mod- will be converted. ule. The CNEN1 and CNEN2 registers contain the The AD1PCFGL register has a default value of 0x0000; interrupt enable control bits for each of the CN input therefore, all pins that share ANx functions are analog pins. Setting any of these bits enables a CN interrupt (not digital) by default. for the corresponding pins. When the PORT register is read, all pins configured as Each CN pin also has a weak pull-up connected to it. analog input channels will read as cleared (a low level). The pull-ups act as a current source connected to the Pins configured as digital inputs will not convert an pin, and eliminate the need for external resistors when analog input. Analog levels on any pin defined as a dig- push-button or keypad devices are connected. The ital input (including the ANx pins) can cause the input pull-ups are enabled separately using the CNPU1 and buffer to consume current that exceeds the device CNPU2 registers, which contain the control bits for specifications. each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. EXAMPLE 10-1: PORT WRITE/READ EXAMPLE MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs MOV W0, TRISBB ; and PORTB<7:0> as outputs NOP ; Delay 1 cycle btss PORTB, #13 ; Next Instruction EXAMPLE 10-2: PORT BIT OPERATIONS Incorrect: BSET PORTB, #RB1 ;Set PORTB<RB1> high BSET PORTB, #RB6 ;Set PORTB<RB6> high Correct: BSET PORTB, #RB1 ;Set PORTB<RB1> high NOP BSET PORTB, #RB6 ;Set PORTB<RB6> high NOP Preferred: BSET LATB, LATB1 ;Set PORTB<RB1> high BSET LATB, LATB6 ;Set PORTB<RB6> high DS70283K-page 118 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 10.6 Peripheral Pin Select 10.6.2.1 Input Mapping Peripheral pin select configuration enables peripheral The inputs of the peripheral pin select options are set selection and placement on a wide range of I/O mapped on the basis of the peripheral. A control pins. By increasing the pinout options available on a register associated with a peripheral dictates the pin it particular device, programmers can better tailor the will be mapped to. The RPINRx registers are used to microcontroller to their entire application, rather than configure peripheral input mapping (see Register10-1 trimming the application to fit the device. through Register10-13). Each register contains sets of 5-bit fields, with each set associated with one of the The peripheral pin select configuration feature remappable peripherals. Programming a given operates over a fixed subset of digital I/O pins. peripheral’s bit field with an appropriate 5-bit value Programmers can independently map the input and/or maps the RPn pin with that value to that peripheral. For output of most digital peripherals to any one of these any given device, the valid range of values for any bit I/O pins. Peripheral pin select is performed in software, field corresponds to the maximum number of peripheral and generally does not require the device to be pin selections supported by the device. reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the Figure10-2 illustrates remappable pin selection for peripheral mapping, once it has been established. U1RX input. Note: For input mapping only, the Peripheral Pin 10.6.1 AVAILABLE PINS Select (PPS) functionality does not have The peripheral pin select feature is used with a range priority over the TRISx settings. There- of up to 26 pins. The number of available pins depends fore, when configuring the RPn pin for on the particular device and its pin count. Pins that input, the corresponding bit in the TRISx support the peripheral pin select feature include the register must also be configured for input designation “RPn” in their full pin designation, where (i.e., set to ‘1’). “RP” designates a remappable peripheral and “n” is the remappable pin number. FIGURE 10-2: REMAPPABLE MUX INPUT FOR U1RX 10.6.2 CONTROLLING PERIPHERAL PIN SELECT U1RXR<4:0> Peripheral pin select features are controlled through two sets of special function registers: one to map 0 peripheral inputs, and one to map outputs. Because RP0 they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be 1 placed on any selectable function pin without constraint. RP1 U1RX input The association of a peripheral to a peripheral to peripheral 2 selectable pin is handled in two different ways, RP2 depending on whether an input or output is being mapped. 25 RP25 © 2007-2012 Microchip Technology Inc. DS70283K-page 119

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Configuration Input Name Function Name Register Bits External Interrupt 1 INT1 RPINR0 INT1R<4:0> External Interrupt 2 INT2 RPINR1 INT2R<4:0> Timer2 External Clock T2CK RPINR3 T2CKR<4:0> Timer3 External Clock T3CK RPINR3 T3CKR<4:0> Input Capture 1 IC1 RPINR7 IC1R<4:0> Input Capture 2 IC2 RPINR7 IC2R<4:0> Input Capture 7 IC7 RPINR10 IC7R<4:0> Input Capture 8 IC8 RPINR10 IC8R<4:0> Output Compare Fault A OCFA RPINR11 OCFAR<4:0> PWM1 Fault FLTA1 RPINR12 FLTA1R<4:0> PWM2 Fault FLTA2 RPINR13 FLTA2R<4:0> QEI1 Phase A QEA RPINR14 QEA1R<4:0> QEI1 Phase B QEB RPINR14 QEB1R<4:0> QEI1 Index INDX RPINR15 INDX1R<4:0> UART1 Receive U1RX RPINR18 U1RXR<4:0> UART1 Clear To Send U1CTS RPINR18 U1CTSR<4:0> SPI1 Data Input SDI1 RPINR20 SDI1R<4:0> SPI1 Clock Input SCK1 RPINR20 SCK1R<4:0> SPI1 Slave Select Input SS1 RPINR21 SS1R<4:0> Note 1: Unless otherwise noted, all inputs use the Schmitt input buffers. DS70283K-page 120 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 10.6.2.2 Output Mapping FIGURE 10-3: MULTIPLEXING OF REMAPPABLE OUTPUT In contrast to inputs, the outputs of the peripheral pin FOR RPn select options are mapped on the basis of the pin. In this case, a control register associated with a particular RPnR<4:0> pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Default Like the RPINRx registers, each register contains sets 0 of 5-bit fields, with each set associated with one RPn U1TX Output Enable 3 pin (see Register10-14 through Register10-26). The U1RTS Output Enable 4 value of the bit field corresponds to one of the periph- erals, and that peripheral’s output is mapped to the pin Output Enable (see Table10-2 and Figure10-3). The list of peripherals for output mapping also includes a null value of 00000 because of the mapping tech- OC2 Output Enable 19 nique. This permits any given pin to remain uncon- UPDN Output Enable nected from the output of any of the pin selectable 26 peripherals. Default 0 U1TX Output 3 U1RTS Output 4 RPn Output Data OC2 Output 19 UPDN Output 26 TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn) Function RPnR<4:0> Output Name NULL 00000 RPn tied to default port pin U1TX 00011 RPn tied to UART1 Transmit U1RTS 00100 RPn tied to UART1 Ready To Send SDO1 00111 RPn tied to SPI1 Data Output SCK1OUT 01000 RPn tied to SPI1 Clock Output SS1OUT 01001 RPn tied to SPI1 Slave Select Output OC1 10010 RPn tied to Output Compare 1 OC2 10011 RPn tied to Output Compare 2 UPDN 11010 RPn tied to QEI direction (UPDN) status © 2007-2012 Microchip Technology Inc. DS70283K-page 121

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 10.6.3 CONTROLLING CONFIGURATION 10.6.3.2 Continuous State Monitoring CHANGES In addition to being protected from direct writes, the Because peripheral remapping can be changed during contents of the RPINRx and RPORx registers are run time, some restrictions on peripheral remapping constantly monitored in hardware by shadow registers. are needed to prevent accidental configuration If an unexpected change in any of the registers occurs changes. dsPIC33F devices include three features to (such as cell disturbances caused by ESD or other prevent alterations to the peripheral map: external events), a configuration mismatch Reset will be triggered. • Control register lock sequence • Continuous state monitoring 10.6.3.3 Configuration Bit Pin Select Lock • Configuration bit pin select lock As an additional level of safety, the device can be configured to prevent more than one write session to 10.6.3.1 Control Register Lock the RPINRx and RPORx registers. The IOL1WAY Under normal operation, writes to the RPINRx and (FOSC<IOL1WAY>) configuration bit blocks the RPORx registers are not allowed. Attempted writes IOLOCK bit from being cleared after it has been set appear to execute normally, but the contents of the once. If IOLOCK remains set, the register unlock registers remain unchanged. To change these procedure will not execute, and the peripheral pin registers, they must be unlocked in hardware. The select control registers cannot be written to. The only register lock is controlled by the IOLOCK bit way to clear the bit and re-enable peripheral remapping (OSCCON<6>). Setting IOLOCK prevents writes to the is to perform a device Reset. control registers; clearing IOLOCK allows writes. In the default (unprogrammed) state, IOL1WAY is set, To set or clear IOLOCK, a specific command sequence restricting users to one write session. Programming must be executed: IOL1WAY allows user applications unlimited access 1. Write 0x46 to OSCCON<7:0>. (with the proper use of the unlock sequence) to the peripheral pin select registers. 2. Write 0x57 to OSCCON<7:0>. 3. Clear (or set) IOLOCK as a single operation. Note: MPLAB® C30 provides built-in C language functions for unlocking the OSCCON register: __builtin_write_OSCCONL(value) __builtin_write_OSCCONH(value) See MPLAB Help for more information. Unlike the similar sequence with the oscillator’s LOCK bit, IOLOCK remains in one state until changed. This allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. DS70283K-page 122 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 10.7 I/O Helpful Tips 4. Each CN pin has a configurable internal weak pull-up resistor. The pull-ups act as a current 1. In some cases, certain pins as defined in TABLE source connected to the pin, and eliminates the 24-9: “DC Characteristics: I/O Pin Input Speci- need for external resistors in certain applica- fications” under “Injection Current”, have internal tions. The internal pull-up is to ~(VDD-0.8) not protection diodes to VDD and VSS. The term VDD. This is still above the minimum VIH of “Injection Current” is also referred to as “Clamp CMOS and TTL devices. Current”. On designated pins, with sufficient exter- 5. When driving LEDs directly, the I/O pin can source nal current limiting precautions by the user, I/O pin or sink more current than what is specified in the input voltages are allowed to be greater or less VOH/IOH and VOL/IOL DC characteristic specifica- than the data sheet absolute maximum ratings tion. The respective IOH and IOL current rating only with nominal VDD with respect to the VSS and VDD applies to maintaining the corresponding output at supplies. Note that when the user application for- or above the VOH and at or below the VOL levels. ward biases either of the high or low side internal However, for LEDs unlike digital inputs of an exter- input clamp diodes, that the resulting current being nally connected device, they are not governed by injected into the device that is clamped internally the same minimum VIH/VIL levels. An I/O pin out- by the VDD and VSS power rails, may affect the put can safely sink or source any current less than ADC accuracy by four to six counts. that listed in the absolute maximum rating section 2. I/O pins that are shared with any analog input pin, of the data sheet. For example: (i.e., ANx), are always analog pins by default after any reset. Consequently, any pin(s) configured as VOH = 2.4v @ IOH = -8 mA and VDD = 3.3V an analog input pin, automatically disables the dig- The maximum output current sourced by any 8mA ital input pin buffer. As such, any attempt to read a I/O pin = 12 mA. digital input pin will always return a ‘0’ regardless LED source current < 12 mA is technically of the digital logic level on the pin if the analog pin permitted. Refer to the VOH/IOH graphs in is configured. To use a pin as a digital I/O pin on a Section24.0 “Electrical Characteristics” for shared ANx pin, the user application needs to con- additional information. figure the analog pin configuration registers in the ADC module, (i.e., ADxPCFGL, AD1PCFGH), by 10.8 I/O Resources setting the appropriate bit that corresponds to that I/O port pin to a ‘1’. On devices with more than one Many useful resources are provided on the main prod- ADC, both analog pin configurations for both ADC uct page of the Microchip web site for the devices listed modules must be configured as a digital I/O pin for in this data sheet. This product page, which can be that pin to function as a digital I/O pin. accessed using this link, contains the latest updates and additional information. Note: Although it is not possible to use a digital input pin when its analog function is Note: In the event you are not able to access enabled, it is possible to use the digital I/O the product page using the link above, output function, TRISx = 0x0, while the enter this URL in your browser: analog function is also enabled. However, http://www.microchip.com/wwwproducts/ this is not recommended, particularly if the Devices.aspx?dDocName=en530334 analog input is connected to an external analog voltage source, which would cre- 10.8.1 KEY RESOURCES ate signal contention between the analog • Section 10. “I/O Ports” (DS70193) signal and the output pin driver. • Code Samples 3. Most I/O pins have multiple functions. Referring to • Application Notes the device pin diagrams in the data sheet, the pri- • Software Libraries orities of the functions allocated to any pins are • Webinars indicated by reading the pin name from left-to-right. The left most function name takes pre- • All related dsPIC33F/PIC24H Family Reference cedence over any function to its right in the naming Manuals Sections convention. For example: AN16/T2CK/T7CK/RC1. • Development Tools This indicates that AN16 is the highest priority in this example and will supersede all other functions to its right in the list. Those other functions to its right, even if enabled, would not work as long as any other function to its left was enabled. This rule applies to all of the functions listed for a given pin. © 2007-2012 Microchip Technology Inc. DS70283K-page 123

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 10.9 Peripheral Pin Select Registers The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices implement 21 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (13) • Output Remappable Peripheral Registers (8) Note: Input and Output Register values can only be changed if OSCCON[IOLOCK] = 0. See Section10.6.3.1 “Control Register Lock” for a specific command sequence. REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — INT1R<4:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ DS70283K-page 124 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — INT2R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007-2012 Microchip Technology Inc. DS70283K-page 125

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T3CKR<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T2CKR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70283K-page 126 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC2R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC2R<4:0>: Assign Input Capture 2 (IC2) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007-2012 Microchip Technology Inc. DS70283K-page 127

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-5: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC8R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC7R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC8R<4:0>: Assign Input Capture 8 (IC8) to the corresponding pin RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC7R<4:0>: Assign Input Capture 7 (IC7) to the corresponding pin RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70283K-page 128 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — OCFAR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 REGISTER 10-7: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — FLTA1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 FLTA1R<4:0>: Assign PWM1 Fault (FLTA1) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007-2012 Microchip Technology Inc. DS70283K-page 129

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-8: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — FLTA2R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 FLTA2R<4:0>: Assign PWM2 Fault (FLTA2) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70283K-page 130 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-9: RPINR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — QEB1R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — QEA1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 QEB1R<4:0>: Assign B (QEB) to the corresponding pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 QEA1R<4:0>: Assign A(QEA) to the corresponding pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007-2012 Microchip Technology Inc. DS70283K-page 131

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-10: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — INDX1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 INDX1R<4:0>: Assign QEI INDEX (INDX) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70283K-page 132 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-11: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — U1CTSR<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — U1RXR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 U1CTSR<4:0>: Assign UART1 Clear to Send (U1CTS) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007-2012 Microchip Technology Inc. DS70283K-page 133

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-12: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SCK1R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SDI1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 SCK1R<4:0>: Assign SPI1 Clock Input (SCK1IN) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70283K-page 134 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-13: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SS1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the corresponding RPn pin bits 11111 = Input tied VSS 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007-2012 Microchip Technology Inc. DS70283K-page 135

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-14: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP1R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP0R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table10-2 for peripheral function numbers) REGISTER 10-15: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP3R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP2R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table10-2 for peripheral function numbers) DS70283K-page 136 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-16: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP5R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP4R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table10-2 for peripheral function numbers) REGISTER 10-17: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP7R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP6R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table10-2 for peripheral function numbers) © 2007-2012 Microchip Technology Inc. DS70283K-page 137

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-18: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP9R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP8R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table10-2 for peripheral function numbers) REGISTER 10-19: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP11R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP10R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table10-2 for peripheral function numbers) DS70283K-page 138 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-20: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP13R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP12R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table10-2 for peripheral function numbers) REGISTER 10-21: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP15R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP14R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table10-2 for peripheral function numbers) © 2007-2012 Microchip Technology Inc. DS70283K-page 139

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-22: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP17R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP16R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP16R<4:0>: Peripheral Output Function is Assigned to RP16 Output Pin bits (see Table10-2 for peripheral function numbers) REGISTER 10-23: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP19R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP18R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits (see Table10-2 for peripheral function numbers) DS70283K-page 140 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-24: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP21R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP20R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP21R<4:0>: Peripheral Output Function is Assigned to RP21 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table10-2 for peripheral function numbers) REGISTER 10-25: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP23R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP22R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table10-2 for peripheral function numbers) © 2007-2012 Microchip Technology Inc. DS70283K-page 141

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-26: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP25R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP24R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP25R<4:0>: Peripheral Output Function is Assigned to RP25 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table10-2 for peripheral function numbers) DS70283K-page 142 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 11.0 TIMER1 Timer1 also supports these features: • Timer gate operation Note1: This data sheet summarizes the features • Selectable prescaler settings of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It • Timer operation during CPU Idle and Sleep is not intended to be a comprehensive modes reference source. To complement the • Interrupt on 16-bit Period register match or falling information in this data sheet, refer to edge of external gate signal Section 11. “Timers” (DS70205) of the Figure11-1 presents a block diagram of the 16-bit timer dsPIC33F/PIC24H Family Reference module. Manual, which is available from the Micro- To configure Timer1 for operation: chip web site (www.microchip.com). 1. Set the TON bit (= 1) in the T1CON register. 2: Some registers and associated bits described in this section may not be 2. Select the timer prescaler ratio using the available on all devices. Refer to TCKPS<1:0> bits in the T1CON register. Section4.0 “Memory Organization” in 3. Set the Clock and Gating modes using the TCS this data sheet for device-specific register and TGATE bits in the T1CON register. and bit information. 4. Set or clear the TSYNC bit in T1CON to select synchronous or asynchronous operation. The Timer1 module is a 16-bit timer, which can serve 5. Load the timer period value into the PR1 as the time counter for the real-time clock, or operate register. as a free-running interval timer/counter. Timer1 can operate in three modes: 6. If interrupts are required, set the interrupt enable bit, T1IE. Use the priority bits, T1IP<2:0>, to set • 16-bit Timer the interrupt priority. • 16-bit Synchronous Counter • 16-bit Asynchronous Counter FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM TCKPS<1:0> TON 2 SOSCO/ 1x T1CK Gate Prescaler SOSCEN Sync 01 1, 8, 64, 256 SOSCI TCY 00 TGATE TGATE TCS 1 Q D Set T1IF Q CK 0 0 Reset TMR1 1 Sync Comparator TSYNC Equal PR1 © 2007-2012 Microchip Technology Inc. DS70283K-page 143

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 11.1 Timer Resources Many useful resources are provided on the main prod- uct page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334 11.1.1 KEY RESOURCES • Section 11. “Timers” (DS70205) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70283K-page 144 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 11.2 Timer1 Control Register REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS<1:0> — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0> Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = External clock from pin T1CK (on the rising edge) 0 = Internal clock (FCY) bit 0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. DS70283K-page 145

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 146 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 12.0 TIMER2/3 FEATURE For 32-bit timer/counter operation, Timer2 is the least significant word (lsw), and Timer3 is the most Note1: This data sheet summarizes the features significant word (msw) of the 32-bit timers. of the dsPIC33FJ32MC202/204 and Note: For 32-bit operation, T3CON control bits dsPIC33FJ16MC304 family of devices. It are ignored. Only T2CON control bits are is not intended to be a comprehensive used for setup and control. Timer2 clock reference source. To complement the and gate inputs are used for the 32-bit information in this data sheet, refer to timer modules, but an interrupt is Section 11. “Timers” (DS70205) of the generated with the Timer3 interrupt flags. “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). 12.1 32-bit Operation 2: Some registers and associated bits To configure the Timer2/3 feature timers for 32-bit described in this section may not be operation: available on all devices. Refer to 1. Set the T32 control bit. Section4.0 “Memory Organization” in 2. Select the prescaler ratio for Timer2 using the this data sheet for device-specific register TCKPS<1:0> bits. and bit information. 3. Set the Clock and Gating modes using the The Timer2/3 feature has three 2-bit timers that can corresponding TCS and TGATE bits. also be configured as two independent 16-bit timers 4. Load the timer period value. PR3 contains the with selectable operating modes. most significant word of the value, while PR2 As a 32-bit timer, the Timer2/3 feature permits contains the least significant word. operation in three modes: 5. If interrupts are required, set the interrupt enable • Two Independent 16-bit timers (e.g., Timer2 and bit, T3IE. Use the priority bits, T3IP<2:0>, to set Timer3) with all 16-bit operating modes (except the interrupt priority. While Timer2 controls the Asynchronous Counter mode) timer, the interrupt appears as a Timer3 interrupt. • Single 32-bit timer (Timer2/3) 6. Set the corresponding TON bit. • Single 32-bit synchronous counter (Timer2/3) The timer value at any point is stored in the register The Timer2/3 feature also supports: pair, TMR3:TMR2, which always contains the most sig- • Timer gate operation nificant word of the count, while TMR2 contains the • Selectable prescaler settings least significant word. • Timer operation during Idle and Sleep modes • Interrupt on a 32-bit period register match 12.2 16-bit Operation • Time base for Input Capture and Output Compare To configure any of the timers for individual 16-bit modules (Timer2 and Timer3 only) operation: • ADC1 event trigger (Timer2/3 only) 1. Clear the T32 bit corresponding to that timer. Individually, all eight of the 16-bit timers can function as 2. Select the timer prescaler ratio using the synchronous timers or counters. They also offer the TCKPS<1:0> bits. features listed above, except for the event trigger. The 3. Set the Clock and Gating modes using the TCS operating modes and enabled features are determined and TGATE bits. by setting the appropriate bit(s) in the T2CON, T3CON 4. Load the timer period value into the PRx registers. T2CON registers are shown in generic form register. in Register12-1. T3CON registers are shown in Register12-2. 5. If interrupts are required, set the interrupt enable bit, TxIE. Use the priority bits, TxIP<2:0>, to set the interrupt priority. 6. Set the TON bit. © 2007-2012 Microchip Technology Inc. DS70283K-page 147

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM(1) TCKPS<1:0> TON 2 T2CK 1x Gate Prescaler Sync 01 1, 8, 64, 256 TGATE TCY 00 TGATE 1 Q D TCS Set T3IF Q CK 0 PR3 PR2 ADC Event Trigger(2) Equal Comparator MSb LSb TMR3 TMR2 Sync Reset 16 Read TMR2 Write TMR2 16 16 TMR3HLD 16 Data Bus<15:0> Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM TCKPS<1:0> TON 2 T2CK 1x Gate Prescaler Sync 01 1, 8, 64, 256 TGATE 00 1 Q D Set T2IF TCY TCS Q CK TGATE 0 Reset TMR2 Sync Comparator Equal PR2 DS70283K-page 148 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 12.3 Timer2/3 Control Registers REGISTER 12-1: T2CON CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS<1:0> T32 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer2 On bit When T32 = 1: 1 = Starts 32-bit Timer2/3 0 = Stops 32-bit Timer2/3 When T32 = 0: 1 = Starts 16-bit Timer2 0 = Stops 16-bit Timer2 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer2 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0>: Timer2 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 T32: 32-bit Timer Mode Select bit 1 = Timer2 and Timer3 form a single 32-bit timer 0 = Timer2 and Timer3 act as two 16-bit timers bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer2 Clock Source Select bit 1 = External clock from pin T2CK (on the rising edge) 0 = Internal clock (FCY) bit 0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. DS70283K-page 149

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 12-2: T3CON CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(2) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(2) TCKPS<1:0>(2) — — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer3 On bit(2) 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit(1) 1 = Discontinue timer operation when device enters Idle mode 0 = Continue timer operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer3 Gated Time Accumulation Enable bit(2) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(2) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer3 Clock Source Select bit(2) 1 = External clock from T3CK pin 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32=1) in the Timer Control register (T2CON<3>), these bits have no effect. DS70283K-page 150 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 13.0 INPUT CAPTURE 1. Simple Capture Event modes: - Capture timer value on every falling edge of Note1: This data sheet summarizes the features input at ICx pin of the dsPIC33FJ32MC202/204 and - Capture timer value on every rising edge of dsPIC33FJ16MC304 family of devices. It input at ICx pin is not intended to be a comprehensive 2. Capture timer value on every edge (rising and reference source. To complement the falling). information in this data sheet, refer to Section 12. “Input Capture” (DS70198) 3. Prescaler Capture Event modes: of the “dsPIC33F/PIC24H Family Refer- - Capture timer value on every 4th rising edge ence Manual”, which is available from the of input at ICx pin Microchip web site (www.microchip.com). - Capture timer value on every 16th rising 2: Some registers and associated bits edge of input at ICx pin described in this section may not be Each input capture channel can select one of two available on all devices. Refer to 16-bit timers (Timer2 or Timer3) for the time base. Section4.0 “Memory Organization” in The selected timer can use either an internal or this data sheet for device-specific register external clock. and bit information. Other operational features include: The input capture module is useful in applications • Device wake-up from capture pin during CPU requiring frequency (period) and pulse measurement. Sleep and Idle modes The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 • Interrupt on input capture event devices support up to eight input capture channels. • 4-word FIFO buffer for capture values The input capture module captures the 16-bit value of - Interrupt optionally generated after 1, 2, 3 or the selected Time Base register when an event occurs 4 buffer locations are filled at the ICx pin. The events that cause a capture event • Use of input capture to provide additional sources are listed below in three categories: of external interrupts FIGURE 13-1: INPUT CAPTURE BLOCK DIAGRAM From 16-bit Timers TMR2 TMR3 16 16 ICTMR 1 0 (ICxCON<7>) Prescaler Edge Detection Logic FIFO Counter and R/W (1, 4, 16) Clock Synchronizer Logic ICx Pin ICM<2:0> (ICxCON<2:0>) 3 Mode Select O F ICOV, ICBNE (ICxCON<4:3>) FI ICxBUF ICxI<1:0> Interrupt ICxCON Logic System Bus Set Flag ICxIF (in IFSn Register) Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel. © 2007-2012 Microchip Technology Inc. DS70283K-page 151

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 13.1 Input Capture Resources Many useful resources are provided on the main prod- uct page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334 13.1.1 KEY RESOURCES • Section 12. “Input Capture” (DS70198) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70283K-page 152 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 13.2 Input Capture Registers REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — ICSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> bit 7 bit 0 Legend: HC = Cleared in Hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture Module Stop in Idle Control bit 1 = Input capture module will halt in CPU Idle mode 0 = Input capture module will continue to operate in CPU Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 ICTMR: Input Capture Timer Select bits 1 = TMR2 contents are captured on capture event 0 = TMR3 contents are captured on capture event bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM<2:0>: Input Capture Mode Select bits 111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode (Rising edge detect only, all other control bits are not applicable.) 110 = Unused (module disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge (rising and falling) (ICI<1:0> bits do not control interrupt generation for this mode.) 000 = Input capture module turned off © 2007-2012 Microchip Technology Inc. DS70283K-page 153

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 154 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 14.0 OUTPUT COMPARE The Output Compare module can select either Timer2 or Timer3 for its time base. The module compares the Note1: This data sheet summarizes the features value of the timer with the value of one or two compare of the dsPIC33FJ32MC202/204 and registers depending on the operating mode selected. dsPIC33FJ16MC304 family of devices. It The state of the output pin changes when the timer is not intended to be a comprehensive value matches the compare register value. The Output reference source. To complement the Compare module generates either a single output information in this data sheet, refer to pulse or a sequence of output pulses, by changing the Section 13. “Output Compare” state of the output pin on the compare match events. (DS70209) of the “dsPIC33F/PIC24H The Output Compare module can also generate Family Reference Manual”, which is interrupts on compare match events. available from the Microchip web site The Output Compare module has multiple operating (www.microchip.com). modes: 2: Some registers and associated bits • Active-Low One-Shot mode described in this section may not be available on all devices. Refer to • Active-High One-Shot mode Section4.0 “Memory Organization” in • Toggle mode this data sheet for device-specific register • Delayed One-Shot mode and bit information. • Continuous Pulse mode • PWM mode without fault protection • PWM mode with fault protection FIGURE 14-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF OCxRS Output S Q OCxR OCx Logic R 3 Output OCM<2:0> Output Enable Mode Select Enable Logic Comparator OCFA 0 1 OCTSEL 0 1 16 16 TMR2 TMR3 TMR2 TMR3 Rollover Rollover © 2007-2012 Microchip Technology Inc. DS70283K-page 155

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 14.1 Output Compare Modes application must disable the associated timer when writing to the output compare control registers to avoid Configure the Output Compare modes by setting the malfunctions. appropriate Output Compare Mode bits (OCM<2:0>) in the Output Compare Control register (OCxCON<2:0>). Note: See Section 13. “Output Compare” Table14-1 lists the different bit settings for the Output (DS70209) in the “dsPIC33F/PIC24H Compare modes. Figure14-2 illustrates the output Family Reference Manual” (DS70209) for compare operation for various modes. The user OCxR and OCxRS register restrictions. TABLE 14-1: OUTPUT COMPARE MODES OCM<2:0> Mode OCx Pin Initial State OCx Interrupt Generation 000 Module Disabled Controlled by GPIO register — 001 Active-Low One-Shot 0 OCx Rising edge 010 Active-High One-Shot 1 OCx Falling edge 011 Toggle Mode Current output is maintained OCx Rising and Falling edge 100 Delayed One-Shot 0 OCx Falling edge 101 Continuous Pulse mode 0 OCx Falling edge 110 PWM mode without fault 0, if OCxR is zero No interrupt protection 1, if OCxR is non-zero 111 PWM mode with fault protection 0, if OCxR is zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero FIGURE 14-2: OUTPUT COMPARE OPERATION Output Compare Timer is reset on Mode enabled period match OCxRS TMRy OCxR Active-Low One-Shot (OCM = 001) Active-High One-Shot (OCM = 010) Toggle Mode (OCM = 011) Delayed One-Shot (OCM = 100) Continuous Pulse Mode (OCM = 101) PWM Mode (OCM = 110 or 111) DS70283K-page 156 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 14.2 Output Compare Resources Many useful resources are provided on the main prod- uct page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334 14.2.1 KEY RESOURCES • Section 13. “Output Compare” (DS70209) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools © 2007-2012 Microchip Technology Inc. DS70283K-page 157

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 14.3 Output Compare Control Register REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0 HC R/W-0 R/W-0 R/W-0 R/W-0 — — — OCFLT OCTSEL OCM<2:0> bit 7 bit 0 Legend: HC = Cleared in Hardware HS = Set in Hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Stop Output Compare in Idle Mode Control bit 1 = Output Compare x will halt in CPU Idle mode 0 = Output Compare x will continue to operate in CPU Idle mode bit 12-5 Unimplemented: Read as ‘0’ bit 4 OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in hardware only) 0 = No PWM Fault condition has occurred (This bit is only used when OCM<2:0> = 111.) bit 3 OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for Compare x 0 = Timer2 is the clock source for Compare x bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx, Fault pin enabled 110 = PWM mode on OCx, Fault pin disabled 101 = Initialize OCx pin low, generate continuous output pulses on OCx pin 100 = Initialize OCx pin low, generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled DS70283K-page 158 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 15.0 MOTOR CONTROL PWM 15.1 PWM1: 6-Channel PWM Module MODULE This module simplifies the task of generating multiple synchronized PWM outputs. The following power and Note1: This data sheet summarizes the features motion control applications are supported by the PWM of the dsPIC33FJ32MC202/204 and module: dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive • 3-Phase AC Induction Motor reference source. To complement the • Switched Reluctance (SR) Motor information in this data sheet, refer to • Brushless DC (BLDC) Motor Section 14. “Motor Control PWM” • Uninterruptible Power Supply (UPS) (DS70187) of the “dsPIC33F/PIC24H Family Reference Manual”, which is This module contains three duty cycle generators, available from the Microchip web site numbered 1 through 3. The module has six PWM (www.microchip.com). output pins, numbered PWM1H1/PWM1L1 through PWM1H3/PWM1L3. The six I/O pins are grouped into 2: Some registers and associated bits high/low numbered pairs, denoted by the suffix H or L, described in this section may not be respectively. For complementary loads, the low PWM available on all devices. Refer to pins are always the complement of the corresponding Section4.0 “Memory Organization” in high I/O pin. this data sheet for device-specific register and bit information. 15.2 PWM2: 2-Channel PWM Module The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 This module provides an additional pair of device supports up to two dedicated Pulse-Width complimentary PWM outputs that can be used for: Modulation (PWM) modules. The PWM1 module is a 6-channel PWM generator, and the PWM2 module is a • Independent PFC correction in a motor system 2-channel PWM generator. • Induction cooking The PWM module has the following features: This module contains a duty cycle generator that provides two PWM outputs, numbered • Up to 16-bit resolution. PWM2H1/PWM2L1. • On-the-fly PWM frequency changes. • Edge and Center-Aligned Output modes. • Single Pulse Generation mode. • Interrupt support for asymmetrical updates in Center-Aligned mode. • Output override control for Electrically Commutative Motor (ECM) operation or BLDC. • Special Event comparator for scheduling other peripheral events. • Fault pins to optionally drive each of the PWM output pins to a defined state. Duty cycle updates configurable to be immediate or synchronized to the PWM time base. © 2007-2012 Microchip Technology Inc. DS70283K-page 159

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 15-1: 6-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM1) PWM1CON1 PWM Enable and Mode SFRs PWM1CON2 P1DTCON1 Dead-Time Control SFRs P1DTCON2 P1FLTACON Fault Pin Control SFRs PWM Manual P1OVDCON Control SFR PWM Generator 3 P1DC3 Buffer s u B a P1DC3 at D 16-bit Comparator ChaOGnnveeenrle r3rida Deto eLra oadgn-iTdcime PPWWMM11HL33 PWM P1TMR Generator 2 Channel 2 Dead-Time PWM1H2 Generator and Override Logic Output PWM1L2 Comparator Driver PWM Block PWM1H1 Generator 1 Channel 1 Dead-Time Generator and P1TPER Override Logic PWM1L1 P1TPER Buffer P1TCON FLTA1 Comparator Special Event Special Event Trigger Postscaler SEVTDIR P1SECMP PTDIR PWM Time Base Note: Details of PWM Generator 1and PWM Generator 2 are not shown for clarity. DS70283K-page 160 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 15-2: 2-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM2) PWM2CON1 PWM Enable and Mode SFRs PWM2CON2 P2DTCON1 Dead-Time Control SFRs P2DTCON2 P2FLTACON Fault Pin Control SFRs PWM Manual P2OVDCON Control SFR PWM Generator 1 P2DC1Buffer s u B a P2DC1 at D 16-bit Comparator ChaOGnnveeenrle r1rida Deto eLra oadgn-iTdcime PPWWMM22HL11 P2TMR Output Comparator Driver Block P2TPER P2TPER Buffer P2TCON FLTA2 Comparator Special Event Special Event Trigger Postscaler SEVTDIR P2SECMP PTDIR PWM Time Base © 2007-2012 Microchip Technology Inc. DS70283K-page 161

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 15.3 Motor Control Resources Many useful resources are provided on the main prod- uct page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334 15.3.1 KEY RESOURCES • Section 14. “Motor Control PWM” (DS70187) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70283K-page 162 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 15.4 PWM Control Registers REGISTER 15-1: PxTCON: PWM TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 PTEN — PTSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTEN: PWM Time Base Timer Enable bit 1 = PWM time base is on 0 = PWM time base is off bit 14 Unimplemented: Read as ‘0’ bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit 1 = PWM time base halts in CPU Idle mode 0 = PWM time base runs in CPU Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7-4 PTOPS<3:0>: PWM Time Base Output Postscale Select bits 1111 = 1:16 postscale • • • 0001 = 1:2 postscale 0000 = 1:1 postscale bit 3-2 PTCKPS<1:0>: PWM Time Base Input Clock Prescale Select bits 11 = PWM time base input clock period is 64 TCY (1:64 prescale) 10 = PWM time base input clock period is 16 TCY (1:16 prescale) 01 = PWM time base input clock period is 4 TCY (1:4 prescale) 00 = PWM time base input clock period is TCY (1:1 prescale) bit 1-0 PTMOD<1:0>: PWM Time Base Mode Select bits 11 = PWM time base operates in a Continuous Up/Down Count mode with interrupts for double PWM updates 10 = PWM time base operates in a Continuous Up/Down Count mode 01 = PWM time base operates in Single Pulse mode 00 = PWM time base operates in a Free-Running mode © 2007-2012 Microchip Technology Inc. DS70283K-page 163

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 15-2: PxTMR: PWM TIMER COUNT VALUE REGISTER R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTDIR PTMR<14:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTMR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTDIR: PWM Time Base Count Direction Status bit (read-only) 1 = PWM time base is counting down 0 = PWM time base is counting up bit 14-0 PTMR <14:0>: PWM Time Base Register Count Value bits REGISTER 15-3: PxTPER: PWM TIME BASE PERIOD REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — PTPER<14:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTPER<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-0 PTPER<14:0>: PWM Time Base Period Value bits DS70283K-page 164 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 15-4: PxSECMP: SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTDIR(1) SEVTCMP<14:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SEVTDIR: Special Event Trigger Time Base Direction bit(1) 1 = A Special Event Trigger will occur when the PWM time base is counting downward 0 = A Special Event Trigger will occur when the PWM time base is counting upward bit 14-0 SEVTCMP<14:0>: Special Event Compare Value bits(2) Note 1: SEVTDIR is compared with PTDIR (PXTMR<15>) to generate the Special Event Trigger. 2: PxSECMP<14:0> is compared with PXTMR<14:0> to generate the Special Event Trigger. © 2007-2012 Microchip Technology Inc. DS70283K-page 165

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 15-5: PWMxCON1: PWM CONTROL REGISTER 1(2) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PMOD3 PMOD2 PMOD1 bit 15 bit 8 U-0 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — PEN3H(1) PEN2H(1) PEN1H(1) — PEN3L(1) PEN2L(1) PEN1L(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 PMOD3:PMOD1: PWM I/O Pair Mode bits 1 = PWM I/O pin pair is in the Independent PWM Output mode 0 = PWM I/O pin pair is in the Complementary Output mode bit 7 Unimplemented: Read as ‘0’ bit 6-4 PEN3H:PEN1H: PWMxH I/O Enable bits(1) 1 = PWMxH pin is enabled for PWM output 0 = PWMxH pin disabled, I/O pin becomes general purpose I/O bit 3 Unimplemented: Read as ‘0’ bit 2-0 PEN3L:PEN1L: PWMxL I/O Enable bits(1) 1 = PWMxL pin is enabled for PWM output 0 = PWMxL pin disabled, I/O pin becomes general purpose I/O Note 1: Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in the FPOR Configuration register. 2: PWM2 supports only 1 PWM I/O pin pair. DS70283K-page 166 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 15-6: PWMxCON2: PWM CONTROL REGISTER 2 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SEVOPS<3:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — IUE OSYNC UDIS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits 1111 = 1:16 postscale • • • 0001 = 1:2 postscale 0000 = 1:1 postscale bit 7-3 Unimplemented: Read as ‘0’ bit 2 IUE: Immediate Update Enable bit 1 = Updates to the active PxDC registers are immediate 0 = Updates to the active PxDC registers are synchronized to the PWM time base bit 1 OSYNC: Output Override Synchronization bit 1 = Output overrides via the PxOVDCON register are synchronized to the PWM time base 0 = Output overrides via the PxOVDCON register occur on next TCY boundary bit 0 UDIS: PWM Update Disable bit 1 = Updates from Duty Cycle and Period Buffer registers are disabled 0 = Updates from Duty Cycle and Period Buffer registers are enabled © 2007-2012 Microchip Technology Inc. DS70283K-page 167

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 15-7: PxDTCON1: DEAD-TIME CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTBPS<1:0> DTB<5:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTAPS<1:0> DTA<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 DTBPS<1:0>: Dead-Time Unit B Prescale Select bits 11 = Clock period for Dead-Time Unit B is 8 TCY 10 = Clock period for Dead-Time Unit B is 4 TCY 01 = Clock period for Dead-Time Unit B is 2 TCY 00 = Clock period for Dead-Time Unit B is TCY bit 13-8 DTB<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit B bits bit 7-6 DTAPS<1:0>: Dead-Time Unit A Prescale Select bits 11 = Clock period for Dead-Time Unit A is 8 TCY 10 = Clock period for Dead-Time Unit A is 4 TCY 01 = Clock period for Dead-Time Unit A is 2 TCY 00 = Clock period for Dead-Time Unit A is TCY bit 5-0 DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits DS70283K-page 168 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 15-8: PxDTCON2: DEAD-TIME CONTROL REGISTER 2(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 DTS3A: Dead-Time Select for PWM3 Signal Going Active bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A bit 4 DTS3I: Dead-Time Select for PWM3 Signal Going Inactive bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A bit 3 DTS2A: Dead-Time Select for PWM2 Signal Going Active bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A bit 2 DTS2I: Dead-Time Select for PWM2 Signal Going Inactive bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A bit 1 DTS1A: Dead-Time Select for PWM1 Signal Going Active bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A bit 0 DTS1I: Dead-Time Select for PWM1 Signal Going Inactive bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A Note 1: PWM2 supports only 1 PWM I/O pin pair. © 2007-2012 Microchip Technology Inc. DS70283K-page 169

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 15-9: PxFLTACON: FAULT A CONTROL REGISTER(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 FLTAM — — — — FAEN3 FAEN2 FAEN1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FAOVxH<3:1>:FAOVxL<3:1>: Fault Input A PWM Override Value bits 1 = The PWM output pin is driven active on an external Fault input event 0 = The PWM output pin is driven inactive on an external Fault input event bit 7 FLTAM: Fault A Mode bit 1 = The Fault A input pin functions in the Cycle-by-Cycle mode 0 = The Fault A input pin latches all control pins to the programmed states in PxFLTACON<13:8> bit 6-3 Unimplemented: Read as ‘0’ bit 2 FAEN3: Fault Input A Enable bit 1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input A 0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input A bit 1 FAEN2: Fault Input A Enable bit 1 = PWMxH2/PWMxL2 pin pair is controlled by Fault Input A 0 = PWMxH2/PWMxL2 pin pair is not controlled by Fault Input A bit 0 FAEN1: Fault Input A Enable bit 1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input A 0 = PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A Note 1: PWM2 supports only 1 PWM I/O pin pair. DS70283K-page 170 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 15-10: PxOVDCON: OVERRIDE CONTROL REGISTER(1) U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 POVDxH<3:1>:POVDxL<3:1>: PWM Output Override bits 1 = Output on PWMx I/O pin is controlled by the PWM generator 0 = Output on PWMx I/O pin is controlled by the value in the corresponding POUTxH:POUTxL bit bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 POUTxH<3:1>:POUTxL<3:1>: PWM Manual Output bits 1 = PWMx I/O pin is driven active when the corresponding POVDxH:POVDxL bit is cleared 0 = PWMx I/O pin is driven inactive when the corresponding POVDxH:POVDxL bit is cleared Note 1: PWM2 supports only 1 PWM I/O pin pair. © 2007-2012 Microchip Technology Inc. DS70283K-page 171

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 15-11: PxDC1: PWM DUTY CYCLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC1<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC1<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PDC1<15:0>: PWM Duty Cycle 1 Value bits REGISTER 15-12: P1DC2: PWM DUTY CYCLE REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC2<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC2<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PDC2<15:0>: PWM Duty Cycle 2 Value bits REGISTER 15-13: P1DC3: PWM DUTY CYCLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC3<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC3<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PDC3<15:0>: PWM Duty Cycle 3 Value bits DS70283K-page 172 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 16.0 QUADRATURE ENCODER This section describes the Quadrature Encoder Inter- INTERFACE (QEI) MODULE face (QEI) module and associated operational modes. The QEI module provides the interface to incremental Note1: This data sheet summarizes the features encoders for obtaining mechanical position data. of the dsPIC33FJ32MC202/204 and The operational features of the QEI include: dsPIC33FJ16MC304 family of devices. It • Three input channels for two phase signals and is not intended to be a comprehensive index pulse reference source. To complement the • 16-bit up/down position counter information in this data sheet, refer to Section 15. “Quadrature Encoder • Count direction status Interface (QEI)” (DS70208) of the • Position Measurement (x2 and x4) mode “dsPIC33F/PIC24H Family Reference • Programmable digital noise filters on inputs Manual”, which is available from the • Alternate 16-bit Timer/Counter mode Microchip website (www.microchip.com). • Quadrature Encoder Interface interrupts 2: Some registers and associated bits These operating modes are determined by setting the described in this section may not be appropriate bits, QEIM<2:0> in (QEIxCON<10:8>). available on all devices. Refer to Figure16-1 depicts the Quadrature Encoder Interface Section4.0 “Memory Organization” in block diagram. this data sheet for device-specific register and bit information. FIGURE 16-1: QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM TQCKPS<1:0> Sleep Input TQCS 2 TCY 0 Synchronize Prescaler Det 1, 8, 64, 256 1 1 QEIM<2:0> 0 QEIIF D Q TQGATE Event CK Q Flag 16-bit Up/Down Counter Programmable 2 (POSCNT) QEAx Digital Filter Quadrature Reset Encoder UPDN_SRC Interface Logic Comparator/ Zero Detect Equal QEIxCON<11> 0 3 QEIM<2:0> 1 Mode Select Max Count Register (MAXCNT) Programmable QEBx Digital Filter Programmable INDXx Digital Filter PCDOUT 3 Existing Pin Logic 0 UPDNx Up/Down 1 © 2007-2012 Microchip Technology Inc. DS70283K-page 173

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 16.1 Ouadrature Encoder Interface 16.2 Control and Status Registers Resources The QEI module has four user-accessible registers, Many useful resources are provided on the main prod- accessible in either Byte or Word mode: uct page of the Microchip web site for the devices listed • Control/Status Register (QEICON) – Allows in this data sheet. This product page, which can be control of the QEI operation and status flags accessed using this link, contains the latest updates indicating the module state. and additional information. • Digital Filter Control Register (DFLTCON) – Note: In the event you are not able to access Allows control of the digital input filter operation. the product page using the link above, • Position Count Register (POSCNT) – Allows enter this URL in your browser: reading and writing of the 16-bit position counter. http://www.microchip.com/wwwproducts/ • Maximum Count Register (MAXCNT) – Holds a Devices.aspx?dDocName=en530334 value that is compared to the POSCNT counter in some operations. 16.1.1 KEY RESOURCES Note: The POSCNT register allows byte • Section 15. “Quadrature Encoder Interface accesses. However, reading the register (QEI)” (DS70208) in Byte mode can result in partially • Code Samples updated values in subsequent reads. • Application Notes Either use Word mode reads/writes, or ensure that the counter is not counting • Software Libraries during Byte operations. • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70283K-page 174 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 16-1: QEIxCON: QEI CONTROL REGISTER R/W-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 CNTERR — QEISIDL INDEX UPDN QEIM<2:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SWPAB PCDOUT TQGATE TQCKPS<1:0> POSRES TQCS UPDN_SRC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CNTERR: Count Error Status Flag bit 1 = Position count error has occurred 0 = No position count error has occurred Note: CNTERR flag only applies when QEIM<2:0> = ‘110’ or ‘100’. bit 14 Unimplemented: Read as ‘0’ bit 13 QEISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 INDEX: Index Pin State Status bit (Read-Only) 1 = Index pin is High 0 = Index pin is Low bit 11 UPDN: Position Counter Direction Status bit 1 = Position Counter Direction is positive (+) 0 = Position Counter Direction is negative (-) (Read-only bit when QEIM<2:0> = ‘1XX’) (Read/Write bit when QEIM<2:0> = ‘001’) bit 10-8 QEIM<2:0>: Quadrature Encoder Interface Mode Select bits 111 = Quadrature Encoder Interface enabled (x4 mode) with position counter reset by match (MAXCNT) 110 = Quadrature Encoder Interface enabled (x4 mode) with Index Pulse reset of position counter 101 = Quadrature Encoder Interface enabled (x2 mode) with position counter reset by match (MAXCNT) 100 = Quadrature Encoder Interface enabled (x2 mode) with Index Pulse reset of position counter 011 = Unused (Module disabled) 010 = Unused (Module disabled) 001 = Starts 16-bit Timer 000 = Quadrature Encoder Interface/Timer off bit 7 SWPAB: Phase A and Phase B Input Swap Select bit 1 = Phase A and Phase B inputs swapped 0 = Phase A and Phase B inputs not swapped bit 6 PCDOUT: Position Counter Direction State Output Enable bit 1 = Position Counter Direction Status Output Enable (QEI logic controls state of I/O pin) 0 = Position Counter Direction Status Output Disabled (Normal I/O pin operation) bit 5 TQGATE: Timer Gated Time Accumulation Enable bit 1 = Timer gated time accumulation enabled 0 = Timer gated time accumulation disabled © 2007-2012 Microchip Technology Inc. DS70283K-page 175

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 16-1: QEIxCON: QEI CONTROL REGISTER (CONTINUED) bit 4-3 TQCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value (Prescaler utilized for 16-bit Timer mode only) bit 2 POSRES: Position Counter Reset Enable bit 1 = Index Pulse resets Position Counter 0 = Index Pulse does not reset Position Counter Note: Bit applies only when QEIM<2:0> = 100 or 110. bit 1 TQCS: Timer Clock Source Select bit 1 = External clock from pin QEA (on the rising edge) 0 = Internal clock (TCY) bit 0 UPDN_SRC: Position Counter Direction Selection Control bit 1 = QEB pin state defines position counter direction 0 = Control/Status bit, UPDN (QEICON<11>), defines timer counter (POSCNT) direction Note: When configured for QEI mode, control bit is a ‘don’t care’. DS70283K-page 176 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 16-2: DFLTxCON: DIGITAL FILTER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — IMV<1:0> CEID bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 QEOUT QECK<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 IMV<1:0>: Index Match Value bits – These bits allow the user application to specify the state of the QEA and QEB input pins during an Index pulse when the POSxCNT register is to be reset. In 4X Quadrature Count Mode: IMV1 = Required State of Phase B input signal for match on index pulse IMV0 = Required State of Phase A input signal for match on index pulse In 2X Quadrature Count Mode: IMV1 = Selects Phase input signal for Index state match (0 = Phase A, 1 = Phase B) IMV0 = Required state of the selected Phase input signal for match on index pulse bit 8 CEID: Count Error Interrupt Disable bit 1 = Interrupts due to count errors are disabled 0 = Interrupts due to count errors are enabled bit 7 QEOUT: QEA/QEB/INDX Pin Digital Filter Output Enable bit 1 = Digital filter outputs enabled 0 = Digital filter outputs disabled (normal pin operation) bit 6-4 QECK<2:0>: QEA/QEB/INDX Digital Filter Clock Divide Select Bits 111 = 1:256 Clock Divide 110 = 1:128 Clock Divide 101 = 1:64 Clock Divide 100 = 1:32 Clock Divide 011 = 1:16 Clock Divide 010 = 1:4 Clock Divide 001 = 1:2 Clock Divide 000 = 1:1 Clock Divide bit 3-0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. DS70283K-page 177

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 178 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 17.0 SERIAL PERIPHERAL The Serial Peripheral Interface (SPI) module is a syn- INTERFACE (SPI) chronous serial interface useful for communicating with other peripheral or microcontroller devices. These Note1: This data sheet summarizes the features peripheral devices can be serial EEPROMs, shift regis- of the dsPIC33FJ32MC202/204 and ters, display drivers, analog-to-digital converters, etc. dsPIC33FJ16MC304 family of devices. It The SPI module is compatible with SPI and SIOP from is not intended to be a comprehensive Motorola®. reference source. To complement the Each SPI module consists of a 16-bit shift register, information in this data sheet, refer to SPIxSR (where x = 1 or 2), used for shifting data in and Section 18. “Serial Peripheral out, and a buffer register, SPIxBUF. A control register, Interface (SPI)” (DS70206) of the SPIxCON, configures the module. Additionally, a status “dsPIC33F/PIC24H Family Reference register, SPIxSTAT, indicates status conditions. Manual”, which is available on the The serial interface consists of these four pins: Microchip website (www.microchip.com). • SDIx (serial data input) 2: Some registers and associated bits • SDOx (serial data output) described in this section may not be • SCKx (shift clock input or output) available on all devices. Refer to • SSx (active-low slave select) Section4.0 “Memory Organization” in this data sheet for device-specific register In Master mode operation, SCK is a clock output. In and bit information. Slave mode, it is a clock input. FIGURE 17-1: SPI MODULE BLOCK DIAGRAM SCKx 1:1 to 1:8 1:1/4/16/64 Secondary Primary FCY Prescaler Prescaler SSx Sync Control Select Control Clock Edge SPIxCON1<1:0> Shift Control SPIxCON1<4:2> SDOx Enable SDIx bit 0 Master Clock SPIxSR Transfer Transfer SPIxRXB SPIxTXB SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus © 2007-2012 Microchip Technology Inc. DS70283K-page 179

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 17.1 SPI Helpful Tips 17.2 SPI Resources 1. In Frame mode, if there is a possibility that the Many useful resources are provided on the main prod- master may not be initialized before the slave: uct page of the Microchip web site for the devices listed a) If FRMPOL (SPIxCON2<13>) = 1, use a in this data sheet. This product page, which can be pull-down resistor on SSx. accessed using this link, contains the latest updates and additional information. b) If FRMPOL = 0, use a pull-up resistor on SSx. Note: In the event you are not able to access Note: This insures that the first frame the product page using the link above, transmission after initialization is not enter this URL in your browser: shifted or corrupted. http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530334 2. In non-framed 3-wire mode, (i.e., not using SSx from a master): 17.2.1 KEY RESOURCES a) If CKP (SPIxCON1<6>) = 1, always place a • Section 18. “Serial Peripheral Interface (SPI)” pull-up resistor on SSx. (DS70206) b) If CKP = 0, always place a pull-down • Code Samples resistor on SSx. • Application Notes Note: This will insure that during power-up and • Software Libraries initialization the master/slave will not lose • Webinars sync due to an errant SCK transition that • All related dsPIC33F/PIC24H Family Reference would cause the slave to accumulate data Manuals Sections shift errors for both transmit and receive appearing as corrupted data. • Development Tools 3. FRMEN (SPIxCON2<15>) = 1 and SSEN (SPIxCON1<7>) = 1 are exclusive and invalid. In Frame mode, SCKx is continuous and the Frame sync pulse is active on the SSx pin, which indicates the start of a data frame. Note: Not all third-party devices support Frame mode timing. Refer to the SPI electrical characteristics for details. 4. In Master mode only, set the SMP bit (SPIxCON1<9>) to a ‘1’ for the fastest SPI data rate possible. The SMP bit can only be set at the same time or after the MSTEN bit (SPIxCON1<5>) is set. 5. To avoid invalid slave read data to the master, the user’s master software must guarantee enough time for slave software to fill its write buf- fer before the user application initiates a master write/read cycle. It is always advisable to pre- load the SPIxBUF transmit register in advance of the next master transaction cycle. SPIxBUF is transferred to the SPI shift register and is empty once the data transmission begins. DS70283K-page 180 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 17.3 SPI Control Registers REGISTER 17-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 SPIEN — SPISIDL — — — — — bit 15 bit 8 U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0 — SPIROV — — — — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded. The user software has not read the previous data in the SPIxBUF register 0 = No overflow has occurred. bit 5-2 Unimplemented: Read as ‘0’ bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. © 2007-2012 Microchip Technology Inc. DS70283K-page 181

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 17-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(2) CKP MSTEN SPRE<2:0>(3) PPRE<1:0>(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled, pin functions as I/O 0 = Internal SPI clock is enabled bit 11 DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. bit 8 CKE: SPIx Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) bit 7 SSEN: Slave Select Enable bit (Slave mode)(2) 1 = SSx pin used for Slave mode 0 = SSx pin not used by module. Pin controlled by port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = 1. 3: Do not set both Primary and Secondary prescalers to a value of 1:1. DS70283K-page 182 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 17-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(3) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(3) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = 1. 3: Do not set both Primary and Secondary prescalers to a value of 1:1. © 2007-2012 Microchip Technology Inc. DS70283K-page 183

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 17-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) 0 = Framed SPIx support disabled bit 14 SPIFSD: Frame Sync Pulse Direction Control bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) bit 13 FRMPOL: Frame Sync Pulse Polarity bit 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low bit 12-2 Unimplemented: Read as ‘0’ bit 1 FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application DS70283K-page 184 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 18.0 INTER-INTEGRATED 18.1 Operating Modes CIRCUIT™ (I2C™) The hardware fully implements all the master and slave functions of the I2C Standard and Fast mode Note1: This data sheet summarizes the features specifications, as well as 7-bit and 10-bit addressing. of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It The I2C module can operate either as a slave or a is not intended to be a comprehensive master on an I2C bus. reference source. To complement the The following types of I2C operation are supported: information in this data sheet, refer to • I2C slave operation with 7-bit addressing Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195) of the • I2C slave operation with 10-bit addressing “dsPIC33F/PIC24H Family Reference • I2C master operation with 7-bit or 10-bit addressing Manual”, which is available from the For details about the communication sequence in each Microchip website (www.microchip.com). of these modes, refer to the “dsPIC33F/PIC24H Family 2: Some registers and associated bits Reference Manual”. Please see the Microchip web site described in this section may not be (www.microchip.com) for the latest dsPIC33F/PIC24H available on all devices. Refer to Family Reference Manual sections. Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Inter-Integrated Circuit (I2C) module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard, with a 16-bit interface. The I2C module has a 2-pin interface: • The SCLx pin is clock • The SDAx pin is data The I2C module offers the following key features: • I2C interface supporting both Master and Slave modes of operation • I2C Slave mode supports 7-bit and 10-bit addressing • I2C Master mode supports 7-bit and 10-bit addressing • I2C port allows bidirectional transfers between master and slaves • Serial clock synchronization for I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control) • I2C supports multi-master operation, detects bus collision and arbitrates accordingly © 2007-2012 Microchip Technology Inc. DS70283K-page 185

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 18-1: I2C™ BLOCK DIAGRAM (X = 1) Internal Data Bus I2CxRCV Read Shift SCLx Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation I2CxSTAT c gi Read o CDoelltiseicotn ntrol L Write o C I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read ShiftClock Reload Control Write BRG Down Counter I2CxBRG Read TCY/2 DS70283K-page 186 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 18.2 I2C Resources 18.3 I2C Registers Many useful resources are provided on the main prod- I2CxCON and I2CxSTAT are control and status uct page of the Microchip web site for the devices listed registers, respectively. The I2CxCON register is in this data sheet. This product page, which can be readable and writable. The lower six bits of I2CxSTAT accessed using this link, contains the latest updates are read-only. The remaining bits of the I2CSTAT are and additional information. read/write: Note: In the event you are not able to access • I2CxRSR is the shift register used for shifting the product page using the link above, data. enter this URL in your browser: • I2CxRCV is the receive buffer and the register to http://www.microchip.com/wwwproducts/ which data bytes are written, or from which data Devices.aspx?dDocName=en530334 bytes are read. • I2CxTRN is the transmit register to which bytes 18.2.1 KEY RESOURCES are written during a transmit operation. • Section 13. “Inter-Integrated Circuit™ (I2C™)” • The I2CxADD register holds the slave address. (DS70195) • A status bit, ADD10, indicates 10-bit Address • Code Samples mode. • Application Notes • The I2CxBRG acts as the Baud Rate Generator • Software Libraries (BRG) reload value. • Webinars In receive operations, I2CxRSR and I2CxRCV together • All related dsPIC33F/PIC24H Family Reference form a double-buffered receiver. When I2CxRSR Manuals Sections receives a complete byte, it is transferred to I2CxRCV, and an interrupt pulse is generated. • Development Tools © 2007-2012 Microchip Technology Inc. DS70283K-page 187

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 18.4 I2C Control Registers REGISTER 18-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Set in hardware HC = Cleared in hardware -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module. All I2C pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters an Idle mode 0 = Continue module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave transmission. bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = IPMI mode is enabled; all addresses Acknowledged 0 = IPMI mode disabled bit 10 A10M: 10-bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching DS70283K-page 188 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 18-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence 0 = Acknowledge sequence not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte 0 = Receive sequence not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence 0 = Stop condition not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence 0 = Repeated Start condition not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence 0 = Start condition not in progress © 2007-2012 Microchip Technology Inc. DS70283K-page 189

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 18-2: I2CxSTAT: I2Cx STATUS REGISTER R-0 HSC R-0 HSC U-0 U-0 U-0 R/C-0 HS R-0 HSC R-0 HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0 HS R/C-0 HS R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC R-0 HSC R-0 HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ C = Clear only bit R = Readable bit W = Writable bit HS = Set in hardware HSC = Hardware set/cleared -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware set or clear at end of slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. bit 8 ADD10: 10-bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. DS70283K-page 190 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 18-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read – indicates data transfer is output from slave 0 = Write – indicates data transfer is input to slave Hardware set or clear after reception of I2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. © 2007-2012 Microchip Technology Inc. DS70283K-page 191

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 18-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position DS70283K-page 192 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 19.0 UNIVERSAL ASYNCHRONOUS The primary features of the UART module are: RECEIVER TRANSMITTER • Full-Duplex, 8-bit or 9-bit Data Transmission (UART) through the UxTX and UxRX pins • Even, Odd or No Parity Options (for 8-bit data) Note1: This data sheet summarizes the features • One or two stop bits of the dsPIC33FJ32MC202/204 and • Hardware flow control option with UxCTS and dsPIC33FJ16MC304 family of devices. It UxRTS pins is not intended to be a comprehensive • Fully integrated Baud Rate Generator with 16-bit reference source. To complement the prescaler information in this data sheet, refer to Section 17. “UART” (DS70188) of the • Baud rates ranging from 10 Mbps to 38 bps at 40 “dsPIC33F/PIC24H Family Reference MIPS Manual”, which is available on the Micro- • 4-deep First-In First-Out (FIFO) Transmit Data chip web site (www.microchip.com). buffer 2: Some registers and associated bits • 4-deep FIFO Receive Data buffer described in this section may not be • Parity, framing and buffer overrun error detection available on all devices. Refer to • Support for 9-bit mode with Address Detect Section4.0 “Memory Organization” in (9th bit = 1) this data sheet for device-specific register • Transmit and Receive interrupts and bit information. • A separate interrupt for all UART error conditions The Universal Asynchronous Receiver Transmitter • Loopback mode for diagnostic support (UART) module is one of the serial I/O modules • Support for sync and break characters available in the dsPIC33FJ32MC202/204 and • Support for automatic baud rate detection dsPIC33FJ16MC304 device family. The UART is a • IrDA® encoder and decoder logic full-duplex asynchronous system that can • 16x baud clock output for IrDA® support communicate with peripheral devices, such as personal computers, LIN, and RS-232 and RS-485 A simplified block diagram of the UART module is interfaces. The module also supports a hardware flow shown in Figure19-1. The UART module consists of control option with the UxCTS and UxRTS pins and these key hardware elements: also includes an IrDA® encoder and decoder. • Baud Rate Generator • Asynchronous Transmitter • Asynchronous Receiver FIGURE 19-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® Hardware Flow Control UxRTS/BCLK UxCTS UART Receiver UxRX UART Transmitter UxTX © 2007-2012 Microchip Technology Inc. DS70283K-page 193

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 19.1 UART Helpful Tips 19.2 UART Resources 1. In multi-node direct-connect UART networks, Many useful resources are provided on the main prod- UART receive inputs react to the uct page of the Microchip web site for the devices listed complementary logic level defined by the in this data sheet. This product page, which can be URXINV bit (UxMODE<4>), which defines the accessed using this link, contains the latest updates idle state, the default of which is logic high, (i.e., and additional information. URXINV = 0). Because remote devices do not Note: In the event you are not able to access initialize at the same time, it is likely that one of the product page using the link above, the devices, because the RX line is floating, will enter this URL in your browser: trigger a start bit detection and will cause the http://www.microchip.com/wwwproducts/ first byte received after the device has been ini- Devices.aspx?dDocName=en530334 tialized to be invalid. To avoid this situation, the user should use a pull-up or pull-down resistor 19.2.1 KEY RESOURCES on the RX pin depending on the value of the URXINV bit. • Section 17. “UART” (DS70188) a) If URXINV = 0, use a pull-up resistor on the • Code Samples RX pin. • Application Notes b) If URXINV = 1, use a pull-down resistor on • Software Libraries the RX pin. • Webinars 2. The first character received on a wake-up from • All related dsPIC33F/PIC24H Family Reference Sleep mode caused by activity on the UxRX pin Manuals Sections of the UART module will be invalid. In Sleep • Development Tools mode, peripheral clocks are disabled. By the time the oscillator system has restarted and stabilized from Sleep mode, the baud rate bit sampling clock relative to the incoming UxRX bit timing is no longer synchronized, resulting in the first character being invalid. This is to be expected. DS70283K-page 194 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 19.3 UART Control Registers REGISTER 19-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UARTEN(1) — USIDL IREN(2) RTSMD — UEN<1:0> bit 15 bit 8 R/W-0 HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL bit 7 bit 0 Legend: HC = Hardware Clearable R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder enabled 0 = IrDA encoder and decoder disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin in Simplex mode 0 = UxRTS pin in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Pin Enable bits 11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by port latches bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = No wake-up enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h) before other data; cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH=0). © 2007-2012 Microchip Technology Inc. DS70283K-page 195

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 19-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH=0). DS70283K-page 196 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 HC R/W-0 R-0 R-1 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware cleared C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: Transmit Polarity Inversion bit If IREN = 0: 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ If IREN = 1: 1 = IrDA® encoded UxTX Idle state is ‘1’ 0 = IrDA® encoded UxTX Idle state is ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission disabled or completed bit 10 UTXEN: Transmit Enable bit(1) 1 = Transmit enabled, UxTX pin controlled by UARTx 0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by port bit 9 UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 = Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive buffer. Receive buffer has one or more characters Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. © 2007-2012 Microchip Technology Inc. DS70283K-page 197

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data=1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect 0 = Address Detect mode disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (read/clear only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1→0 transition) will reset the receiver buffer and the UxRSR to the empty state bit 0 URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. DS70283K-page 198 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 20.0 10-BIT/12-BIT The 12-bit ADC configuration supports all the above ANALOG-TO-DIGITAL features, except: CONVERTER (ADC) • In the 12-bit configuration, conversion speeds of up to 500 ksps are supported. Note1: This data sheet summarizes the features • There is only 1 sample-and-hold amplifier in the of the dsPIC33FJ32MC202/204 and 12-bit configuration, so simultaneous sampling of dsPIC33FJ16MC304 family of devices. It multiple channels is not supported. is not intended to be a comprehensive Depending on the particular device pinout, the ADC reference source. To complement the can have up to nine analog input pins, designated AN0 information in this data sheet, refer to through AN8. In addition, there are two analog input Section 16. “Analog-to-Digital pins for external voltage reference connections. These Converter (ADC)” (DS70183) of the voltage reference inputs can be shared with other “dsPIC33F/PIC24H Family Reference analog input pins. Manual”, which is available on the Microchip website (www.microchip.com). The actual number of analog input pins and external voltage reference input configuration will depend on the 2: Some registers and associated bits specific device. Refer to the device data sheet for described in this section may not be further details. available on all devices. Refer to Section4.0 “Memory Organization” in A block diagram of the ADC is shown in Figure20-1. this data sheet for device-specific register and bit information. 20.2 ADC Initialization The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 To configure the ADC module: devices have up to nine Analog-to-Digital Converter 1. Select port pins as analog inputs (ADC) module input channels. (AD1PCFGH<15:0> or AD1PCFGL<15:0>). The AD12B bit (AD1CON1<10>) allows each of the 2. Select voltage reference source to match ADC modules to be configured as either a 10-bit, expected range on analog inputs 4sample-and-hold ADC (default configuration), or a (AD1CON2<15:13>). 12-bit, 1 sample-and-hold ADC. 3. Select the analog conversion clock to match the desired data rate with the processor clock Note: The ADC module must be disabled before (AD1CON3<7:0>). the AD12B bit can be modified. 4. Determine how many sample-and-hold chan- nels will be used (AD1CON2<9:8> and 20.1 Key Features AD1PCFGH<15:0> or AD1PCFGL<15:0>). The 10-bit ADC configuration has the following key 5. Select the appropriate sample/conversion features: sequence (AD1CON1<7:5> and AD1CON3<12:8>). • Successive Approximation (SAR) conversion 6. Select the way conversion results are presented • Conversion speeds of up to 1.1 Msps in the buffer (AD1CON1<9:8>). • Up to 9 analog input pins 7. Turn on the ADC module (AD1CON1<15>). • External voltage reference input pins 8. Configure ADC interrupt (if required): • Simultaneous sampling of up to four analog input a) Clear the AD1IF bit. pins b) Select the ADC interrupt priority. • Automatic Channel Scan mode • Selectable conversion trigger source • Selectable Buffer Fill modes • Four result alignment options (signed/unsigned, fractional/integer) • Operation during CPU Sleep and Idle modes • 16-word conversion result buffer © 2007-2012 Microchip Technology Inc. DS70283K-page 199

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 20-1: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ16MC304 AND dsPIC33FJ32MC204 DEVICES AN0 AN8 S/H0 CHANNEL SCAN + CH0SB<4:0> CH0SA<4:0> - CH0 CSCNA AN1 VREFL CH0NA CH0NB AN0 VREF+(1)AVDDVREF-(1)AVSS AN3 S/H1 + CH1(2) CH123SA CH123SB - AN6 VCFG<2:0> ADC1BUF0 VREFL ADC1BUF1 ADC1BUF2 VREFH VREFL CH123NA CH123NB SAR ADC AN1 AN4 S/H2 + ADC1BUFE CH123SACH123SB - ADC1BUFF CH2(2) AN7 VREFL CH123NA CH123NB AN2 AN5 S/H3 + CH3(2) CH123SA CH123SB - AN8 VREFL CH123NA CH123NB Alternate Input Selection Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. DS70283K-page 200 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 20-2: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ32MC202 DEVICE AN0 AN5 S/H0 CHANNEL SCAN + CH0SB<4:0> CH0SA<4:0> - CH0 CSCNA AN1 VREFL CH0NA CH0NB AN0 VREF+(1)AVDDVREF-(1)AVSS AN3 S/H1 + CH123SA CH123SB - CH1(2) VCFG<2:0> ADC1BUF0 VREFL ADC1BUF1 ADC1BUF2 VREFH VREFL CH123NA CH123NB SAR ADC AN1 AN4 S/H2 + ADC1BUFE CH123SACH123SB - ADC1BUFF CH2(2) VREFL CH123NA CH123NB AN2 AN5 S/H3 + CH123SA CH123SB CH3(2) - VREFL CH123NA CH123NB Alternate Input Selection Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. © 2007-2012 Microchip Technology Inc. DS70283K-page 201

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 20-3: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM AD1CON3<15> ADC Internal RC Clock(2) 0 TAD AD1CON3<5:0> 1 6 ADC Conversion TCY Clock Multiplier TOSC(1) X2 1, 2, 3, 4, 5,..., 64 Note 1: Refer to Figure8-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal to the clock frequency. TOSC = 1/FOSC. 2: See the ADC Electrical Characteristics for the exact RC clock value. 20.3 ADC Helpful Tips behavior because the CPU code execution is faster than the ADC. As a result, in manual sam- 1. The SMPI<3:0> (AD1CON2<5:2>) control bits: ple mode, particularly where the users code is a) Determine when the ADC interrupt flag is setting the SAMP bit (AD1CON1<1>), the set and an interrupt is generated if enabled. DONE bit should also be cleared by the user b) When the CSCNA bit (AD1CON2<10>) is application just before setting the SAMP bit. set to ‘1’, determines when the ADC analog 5. On devices with two ADC modules, the scan channel list defined in the ADCxPCFG registers for both ADC modules AD1CSSL/AD1CSSH registers starts over must be set to a logic ‘1’ to configure a target from the beginning. I/O pin as a digital I/O pin. Failure to do so c) On devices without a DMA peripheral, means that any alternate digital input function determines when ADC result buffer pointer will always see only a logic ‘0’ as the digital to ADC1BUF0-ADC1BUFF, gets reset back input buffer is held in Disable mode. to the beginning at ADC1BUF0. 2. On devices without a DMA module, the ADC has 20.4 ADC Resources 16 result buffers. ADC conversion results are Many useful resources are provided on the main prod- stored sequentially in ADC1BUF0-ADC1BUFF uct page of the Microchip web site for the devices listed regardless of which analog inputs are being in this data sheet. This product page, which can be used subject to the SMPI<3:0> bits accessed using this link, contains the latest updates (AD1CON2<5:2>) and the condition described and additional information. in 1c above. There is no relationship between the ANx input being measured and which ADC Note: In the event you are not able to access buffer (ADC1BUF0-ADC1BUFF) that the the product page using the link above, conversion results will be placed in. enter this URL in your browser: 3. On devices with a DMA module, the ADC mod- http://www.microchip.com/wwwproducts/ ule has only 1 ADC result buffer, (i.e., Devices.aspx?dDocName=en530334 ADC1BUF0), per ADC peripheral and the ADC conversion result must be read either by the 20.4.1 KEY RESOURCES CPU or DMA controller before the next ADC • Section 16. “Analog-to-Digital Converter conversion is complete to avoid overwriting the (ADC)” (DS70183) previous value. • Code Samples 4. The DONE bit (AD1CON1<0>) is only cleared at • Application Notes the start of each conversion and is set at the • Software Libraries completion of the conversion, but remains set indefinitely even through the next sample phase • Webinars until the next conversion begins. If application • All related dsPIC33F/PIC24H Family Reference code is monitoring the DONE bit in any kind of Manuals Sections software loop, the user must consider this • Development Tools DS70283K-page 202 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 20.5 ADC Control Registers REGISTER 20-1: AD1CON1: ADC1 CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 ADON — ADSIDL — — AD12B FORM<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/C-0 HC,HS HC, HS SSRC<2:0> — SIMSAM ASAM SAMP DONE bit 7 bit 0 Legend: HC = Cleared by hardware HS = Set by hardware C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: ADC Operating Mode bit 1 = ADC module is operating 0 = ADC is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 Unimplemented: Read as ‘0’ bit 10 AD12B: 10-bit or 12-bit Operation Mode bit 1 = 12-bit, 1-channel ADC operation 0 = 10-bit, 4-channel ADC operation bit 9-8 FORM<1:0>: Data Output Format bits For 10-bit operation: 11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d<9>) 10 = Fractional (DOUT = dddd dddd dd00 0000) 01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>) 00 = Integer (DOUT = 0000 00dd dddd dddd) For 12-bit operation: 11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s = .NOT.d<11>) 10 = Fractional (DOUT = dddd dddd dddd 0000) 01 = Signed Integer (DOUT = ssss sddd dddd dddd, where s = .NOT.d<11>) 00 = Integer (DOUT = 0000 dddd dddd dddd) bit 7-5 SSRC<2:0>: Sample Clock Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 101 = Motor Control PWM2 interval ends sampling and starts conversion 100 = Reserved 011 = Motor Control PWM1 interval ends sampling and starts conversion 010 = GP timer 3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing sample bit ends sampling and starts conversion bit 4 Unimplemented: Read as ‘0’ bit 3 SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> = 01 or 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ 1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01) 0 = Samples multiple channels individually in sequence © 2007-2012 Microchip Technology Inc. DS70283K-page 203

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 20-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion. SAMP bit is auto-set 0 = Sampling begins when SAMP bit is set bit 1 SAMP: ADC Sample Enable bit 1 = ADC sample-and-hold amplifiers are sampling 0 = ADC sample-and-hold amplifiers are holding If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000, automatically cleared by hardware to end sampling and start conversion. bit 0 DONE: ADC Conversion Status bit 1 = ADC conversion cycle is completed 0 = ADC conversion not started or in progress Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion. DS70283K-page 204 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 20-2: AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 VCFG<2:0> — — CSCNA CHPS<1:0> bit 15 bit 8 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS — SMPI<3:0> BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits ADREF+ ADREF- 000 AVDD AVSS 001 External VREF+ AVSS 010 AVDD External VREF- 011 External VREF+ External VREF- 1xx AVDD AVSS bit 12-11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Scan Input Selections for CH0+ during Sample A bit 1 = Scan inputs 0 = Do not scan inputs bit 9-8 CHPS<1:0>: Select Channels Utilized bits When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’ 1x = Converts CH0, CH1, CH2 and CH3 01 = Converts CH0 and CH1 00 = Converts CH0 bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = ADC is currently filling second half of buffer, user should access data in the first half 0 = ADC is currently filling first half of buffer, user application should access data in the second half bit 6 Unimplemented: Read as ‘0’ bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence • • • 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence bit 1 BUFM: Buffer Fill Mode Select bit 1 = Starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt 0 = Always starts filling buffer from the beginning bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A © 2007-2012 Microchip Technology Inc. DS70283K-page 205

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 20-3: AD1CON3: ADC1 CONTROL REGISTER 3 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — — SAMC<4:0>(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from system clock bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 SAMC<4:0>: Auto Sample Time bits(1) 11111 = 31 TAD • • • 00001 = 1 TAD 00000 = 0 TAD bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2) 11111111 = Reserved • • • • 01000000 = Reserved 00111111 = TCY · (ADCS<7:0> + 1) = 64 · TCY = TAD • • • 00000010 = TCY · (ADCS<7:0> + 1) = 3 · TCY = TAD 00000001 = TCY · (ADCS<7:0> + 1) = 2 · TCY = TAD 00000000 = TCY · (ADCS<7:0> + 1) = 1 · TCY = TAD Note 1: This bit only used if AD1CON1<7:5> (SSRC2:0) = 111. 2: This bit is not used if AD1CON3<15> (ADRC) = 1. DS70283K-page 206 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 20-4: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CH123NB<1:0> CH123SB bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CH123NA<1:0> CH123SA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits dsPIC33FJ32MC202 devices only: If AD12B = 1: 11 = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = 0: 11 = Reserved 10 = Reserved 01 = CH1, CH2, CH3 negative input is VREF- 00 = CH1, CH2, CH3 negative input is VREF- dsPIC33FJ32MC204 and dsPIC33FJ16MC304 devices only: If AD12B = 1: 11 = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = 0: 11 = Reserved 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8 01 = CH1, CH2, CH3 negative input is VREF- 00 = CH1, CH2, CH3 negative input is VREF- bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit If AD12B = 1: 1 = Reserved 0 = Reserved If AD12B = 0: 1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 bit 7-3 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. DS70283K-page 207

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 20-4: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER (CONTINUED) bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits dsPIC33FJ32MC202 devices only: If AD12B = 1: 11 = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = 0: 11 = Reserved 10 = Reserved 01 = CH1, CH2, CH3 negative input is VREF- 00 = CH1, CH2, CH3 negative input is VREF- dsPIC33FJ32MC204 and dsPIC33FJ16MC304 devices only: If AD12B = 1: 11 = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = 0: 11 = Reserved 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8 01 = CH1, CH2, CH3 negative input is VREF- 00 = CH1, CH2, CH3 negative input is VREF- bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit If AD12B = 1: 1 = Reserved 0 = Reserved If AD12B = 0: 1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 DS70283K-page 208 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R EGISTER 20-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB — — CH0SB<4:0> bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — CH0SA<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREF- bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits dsPIC33FJ32MC204 and dsPIC33FJ16MC304 devices only: 01000 = Channel 0 positive input is AN8 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 dsPIC33FJ32MC202 devices only: 00101 = Channel 0 positive input is AN5 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0. bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREF- bit 6-5 Unimplemented: Read as ‘0’ bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits dsPIC33FJ32MC204 and dsPIC33FJ16MC304 devices only: 01000 = Channel 0 positive input is AN8 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 dsPIC33FJ32MC202 devices only: 00101 = Channel 0 positive input is AN5 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 © 2007-2012 Microchip Technology Inc. DS70283K-page 209

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 R ,2EGISTER 20-6: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1,2) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CSS8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 CSS<8:0>: ADC Input Scan Selection bits 1 = Select ANx for input scan 0 = Skip ANx for input scan Note1: On devices without 9 analog inputs, all AD1CSSL bits can be selected by the user application. However, inputs selected for scan without a corresponding input on device converts VREFL. 2: CSSx = ANx, where x = 0 through 8. REGISTER 20-7: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW(1,2,3) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PCFG8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PCFG<8:0>: ADC Port Configuration Control bits 1 = Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AVSS 0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage Note 1: On devices without 9 analog inputs, all PCFG bits are R/W by user software. However, the PCFG bits are ignored on ports without a corresponding input on device. 2: PCFGx = ANx, where x = 0 through 8. 3: The PCFGx bits have no effect if the ADC module is disabled by setting ADxMD bit in the PMDx Register. In this case, all port pins multiplexed with ANx will be in Digital mode. DS70283K-page 210 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 21.0 SPECIAL FEATURES 21.1 Configuration Bits Note: This data sheet summarizes the features dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 of the dsPIC33FJ32MC202/204 and devices provide nonvolatile memory implementation dsPIC33FJ16MC304 devices. It is not for device configuration bits. Refer to Section 25. intended to be a comprehensive refer- “Device Configuration” (DS70194) of the ence source. To complement the informa- “dsPIC33F/PIC24H Family Reference Manual”, for tion in this data sheet, refer to the more information on this implementation. “dsPIC33F/PIC24H Family Reference The Configuration bits can be programmed (read as Manual”. Please see the Microchip web ‘0’), or left unprogrammed (read as ‘1’), to select site (www.microchip.com) for the latest various device configurations. These bits are mapped dsPIC33F/PIC24H Family Reference starting at program memory location 0xF80000. Manual sections. The individual Configuration bit descriptions for the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Configuration registers are shown in Table21-2. devices include several features intended to maximize Note that address 0xF80000 is beyond the user program application flexibility and reliability, and minimize cost memory space. It belongs to the configuration memory through elimination of external components. These are: space (0x800000-0xFFFFFF), which can only be • Flexible configuration accessed using table reads and table writes. • Watchdog Timer (WDT) The Device Configuration register map is shown in • Code Protection and CodeGuard™ Security Table21-1. • JTAG Boundary Scan Interface • In-Circuit Serial Programming™ (ICSP™) • In-Circuit emulation TABLE 21-1: DEVICE CONFIGURATION REGISTER MAP Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0xF80000 FBS — — — — BSS<2:0> BWRP 0xF80002 RESERVED — — — — — — — — 0xF80004 FGS — — — — — GSS<1:0> GWRP 0xF80006 FOSCSEL IESO — — — FNOSC<2:0> 0xF80008 FOSC FCKSM<1:0> IOL1WAY — — OSCIOFNC POSCMD<1:0> 0xF8000A FWDT FWDTEN WINDIS — WDTPRE WDTPOST<3:0> 0xF8000C FPOR PWMPIN HPOL LPOL ALTI2C — FPWRT<2:0> 0xF8000E FICD Reserved(1) JTAGEN — — — ICS<1:0> 0xF80010 FUID0 User Unit ID Byte 0 0xF80012 FUID1 User Unit ID Byte 1 0xF80014 FUID2 User Unit ID Byte 2 0xF80016 FUID3 User Unit ID Byte 3 Legend: — = unimplemented bit, read as ‘0’. Note 1: These bits are reserved for use by development tools and must be programmed as ‘1’. © 2007-2012 Microchip Technology Inc. DS70283K-page 211

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 21-2: CONFIGURATION BITS DESCRIPTION RTSP Bit Field Register Description Effect BWRP FBS Immediate Boot Segment Program Flash Write Protection 1 = Boot segment can be written 0 = Boot segment is write-protected BSS<2:0> FBS Immediate dsPIC33FJ32MC202 and dsPIC33FJ32MC204 Devices Only Boot Segment Program Flash Code Protection Size X11 = No Boot program Flash segment Boot space is 768 Instruction Words (except interrupt vectors) 110 = Standard security; boot program Flash segment ends at 0x0007FE 010 = High security; boot program Flash segment ends at 0x0007FE Boot space is 3840 Instruction Words (except interrupt vectors) 101 = Standard security; boot program Flash segment, ends at 0x001FFE 001 = High security; boot program Flash segment ends at 0x001FFE Boot space is 7936 Instruction Words (except interrupt vectors) 100 = Standard security; boot program Flash segment ends at 0x003FFE 000 = High security; boot program Flash segment ends at 0x003FFE BSS<2:0> FBS Immediate dsPIC33FJ16MC304 Device Only Boot Segment Program Flash Code Protection Size X11 = No Boot program Flash segment Boot space is 768 Instruction Words (except interrupt vectors) 110 = Standard security; boot program Flash segment ends at 0x0007FE 010 = High security; boot program Flash segment ends at 0x0007FE Boot space is 3840 Instruction Words (except interrupt vectors) 101 = Standard security; boot program Flash segment, ends at 0x001FFE 001 = High security; boot program Flash segment ends at 0x001FFE Boot space is 5376 Instruction Words (except interrupt vectors) 100 = Standard security; boot program Flash segment ends at 0x002BFE 000 = High security; boot program Flash segment ends at 0x002BFE GSS<1:0> FGS Immediate General Segment Code-Protect bit 11 = User program memory is not code-protected 10 = Standard security 0x = High security GWRP FGS Immediate General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected IESO FOSCSEL Immediate Two-speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start-up device with user-selected oscillator source FNOSC<2:0> FOSCSEL If clock Initial Oscillator Source Selection bits switch is 111 = Internal Fast RC (FRC) oscillator with postscaler enabled, 110 = Internal Fast RC (FRC) oscillator with divide-by-16 RTSP 101 = LPRC oscillator effect is 100 = Secondary (LP) oscillator on any 011 = Primary (XT, HS, EC) oscillator with PLL device 010 = Primary (XT, HS, EC) oscillator Reset; 001 = Internal Fast RC (FRC) oscillator with PLL otherwise, 000 = FRC oscillator Immediate DS70283K-page 212 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 21-2: CONFIGURATION BITS DESCRIPTION (CONTINUED) RTSP Bit Field Register Description Effect FCKSM<1:0> FOSC Immediate Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled IOL1WAY FOSC Immediate Peripheral pin select configuration 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations OSCIOFNC FOSC Immediate OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin POSCMD<1:0> FOSC Immediate Primary Oscillator Mode Select bits 11 = Primary oscillator disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode FWDTEN FWDT Immediate Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register will have no effect.) 0 = Watchdog Timer enabled/disabled by user software (LPRC can be dis- abled by clearing the SWDTEN bit in the RCON register) WINDIS FWDT Immediate Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode WDTPRE FWDT Immediate Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 WDTPOST<3:0> FWDT Immediate Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 PWMPIN FPOR Immediate Motor Control PWM Module Pin Mode bit 1 = PWM module pins controlled by PORT register at device Reset (tri-stated) 0 = PWM module pins controlled by PWM module at device Reset (configured as output pins) © 2007-2012 Microchip Technology Inc. DS70283K-page 213

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 21-2: CONFIGURATION BITS DESCRIPTION (CONTINUED) RTSP Bit Field Register Description Effect HPOL FPOR Immediate Motor Control PWM High Side Polarity bit 1 = PWM module high side output pins have active-high output polarity 0 = PWM module high side output pins have active-low output polarity LPOL FPOR Immediate Motor Control PWM Low Side Polarity bit 1 = PWM module low side output pins have active-high output polarity 0 = PWM module low side output pins have active-low output polarity FPWRT<2:0> FPOR Immediate Power-on Reset Timer Value Select bits 111 = PWRT = 128 ms 110 = PWRT = 64 ms 101 = PWRT = 32 ms 100 = PWRT = 16 ms 011 = PWRT = 8 ms 010 = PWRT = 4 ms 001 = PWRT = 2 ms 000 = PWRT = Disabled ALTI2C FPOR Immediate Alternate I2C™ pins 1 = I2C mapped to SDA1/SCL1 pins 0 = I2C mapped to ASDA1/ASCL1 pins JTAGEN FICD Immediate JTAG Enable bit 1 = JTAG enabled 0 = JTAG disabled ICS<1:0> FICD Immediate ICD Communication Channel Select bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use DS70283K-page 214 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 21.2 On-Chip Voltage Regulator 21.3 BOR: Brown-out Reset (BOR) The dsPIC33FJ32MC202/204 and The Brown-out Reset (BOR) module is based on an dsPIC33FJ16MC304 devices power their core digital internal voltage reference circuit that monitors the reg- logic at a nominal 2.5V. This can create a conflict for ulated supply voltage VCAP. The main purpose of the designs that are required to operate at a higher typical BOR module is to generate a device Reset when a voltage, such as 3.3V. To simplify system design, all brown-out condition occurs. Brown-out conditions are devices in the dsPIC33FJ32MC202/204 and generally caused by glitches on the AC mains (for dsPIC33FJ16MC304 family incorporate an on-chip example, missing portions of the AC cycle waveform regulator that allows the device to run its core logic from due to bad power transmission lines, or voltage sags VDD. due to excessive current draw when a large inductive load is turned on). The regulator provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR A BOR generates a Reset pulse, which resets the (less than 5 ohms) capacitor (such as tantalum or device. The BOR selects the clock source, based on ceramic) must be connected to the VCAP pin the device Configuration bit values (FNOSC<2:0> and (Figure21-1). This helps to maintain the stability of the POSCMD<1:0>). regulator. The recommended value for the filter capac- If an oscillator mode is selected, the BOR activates the itor is provided in Table24-13 located in Section24.1 Oscillator Start-up Timer (OST). The system clock is “DC Characteristics”. held until OST expires. If the PLL is used, the clock is Note: It is important for low-ESR capacitors to held until the LOCK bit (OSCCON<5>) is ‘1’. be placed as close as possible to the VCAP Concurrently, the PWRT time-out (TPWRT) is applied pin. before the internal Reset is released. If TPWRT = 0 and On a POR, it takes approximately 20μs for the on-chip a crystal oscillator is being used, then a nominal delay of TFSCM = 100 is applied. The total delay in this case voltage regulator to generate an output voltage. During is TFSCM. this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device The BOR Status bit (RCON<1>) is set to indicate that a resumes operation after any power-down. BOR has occurred. The BOR circuit continues to oper- ate while in Sleep or Idle modes and resets the device FIGURE 21-1: CONNECTIONS FOR THE should VDD fall below the BOR threshold voltage. ON-CHIP VOLTAGE REGULATOR(1,2,3) 3.3V dsPIC33F VDD VCAP CEFC 10 µF VSS Note 1: These are typical operating voltages. Refer to Table24-13 located in Section24.1 “DC Characteristics” for the full operating ranges of VDD and VCAP. 2: It is important for low-ESR capacitors to be placed as close as possible to the VCAP pin. 3: Typical VCAP pin voltage = 2.5V when VDD ≥ VDDMIN. © 2007-2012 Microchip Technology Inc. DS70283K-page 215

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 21.4 Watchdog Timer (WDT) 21.4.2 SLEEP AND IDLE MODES For dsPIC33FJ32MC202/204 and If the WDT is enabled, it will continue to run during Sleep dsPIC33FJ16MC304 devices, the WDT is driven by the or Idle modes. When the WDT time-out occurs, the LPRC oscillator. When the WDT is enabled, the clock device will wake the device and code execution will con- source is also enabled. tinue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON<3,2>) will 21.4.1 PRESCALER/POSTSCALER need to be cleared in software after the device wakes up. The nominal WDT clock source from LPRC is 32kHz. 21.4.3 ENABLING WDT This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The WDT is enabled or disabled by the FWDTEN The prescaler is set by the WDTPRE Configuration bit. Configuration bit in the FWDT Configuration register. With a 32kHz input, the prescaler yields a nominal When the FWDTEN Configuration bit is set, the WDT is WDT time-out period (TWDT) of 1ms in 5-bit mode, or always enabled. 4ms in 7-bit mode. The WDT can be optionally controlled in software when A variable postscaler divides down the WDT prescaler the FWDTEN Configuration bit has been programmed output and allows for a wide range of time-out periods. to ‘0’. The WDT is enabled in software by setting the The postscaler is controlled by the WDTPOST<3:0> SWDTEN control bit (RCON<5>). The SWDTEN Configuration bits (FWDT<3:0>), which allow the selec- control bit is cleared on any device Reset. The software tion of 16 settings, from 1:1 to 1:32,768. Using the pres- WDT option allows the user application to enable the caler and postscaler, time-out periods ranging from WDT for critical code segments and disable the WDT 1ms to 131 seconds can be achieved. during non-critical segments for maximum power savings. The WDT, prescaler and postscaler are reset: Note: If the WINDIS bit (FWDT<6>) is cleared, • On any device Reset the CLRWDT instruction should be executed • On the completion of a clock switch, whether by the application software only during the invoked by software (i.e., setting the OSWEN bit last 1/4 of the WDT period. This CLRWDT after changing the NOSC bits) or by hardware window can be determined by using a timer. (i.e., Fail-Safe Clock Monitor) If a CLRWDT instruction is executed before • When a PWRSAV instruction is executed this window, a WDT Reset occurs. (i.e., Sleep or Idle mode is entered) The WDT flag bit, WDTO (RCON<4>), is not automatically • When the device exits Sleep or Idle mode to cleared following a WDT time-out. To detect subsequent resume normal operation WDT events, the flag must be cleared in software. • By a CLRWDT instruction during normal execution Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. FIGURE 21-2: WDT BLOCK DIAGRAM All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle WDTPRE WDTPOST<3:0> SWDTEN WDT FWDTEN Wake-up RS RS 1 Prescaler Postscaler LPRC Clock (divide by N1) (divide by N2) WDT 0 Reset WINDIS WDT Window Select CLRWDT Instruction DS70283K-page 216 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 21.5 JTAG Interface 21.7 In-Circuit Debugger dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 When MPLAB® ICD 2 is selected as a debugger, the devices implement a JTAG interface, which supports in-circuit debugging functionality is enabled. This boundary scan device testing, as well as in-circuit function allows simple debugging functions when used programming. Detailed information on this interface will with MPLAB IDE. Debugging functionality is controlled be provided in future revisions of the document. through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pin functions. 21.6 In-Circuit Serial Programming Any of the three pairs of debugging clock/data pins can be used: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family digital signal controllers can be serially • PGEC1 and PGED1 programmed while in the end application circuit. This is • PGEC2 and PGED2 done with two lines for clock and data and three other • PGEC3 and PGED3 lines for power, ground and the programming To use the in-circuit debugger function of the device, sequence. Serial programming allows customers to the design must implement ICSP connections to manufacture boards with unprogrammed devices and then program the digital signal controller just before MCLR, VDD, VSS, and the PGECx/PGEDx pin pair. In addition, when the feature is enabled, some of the shipping the product. Serial programming also allows resources are not available for general use. These the most recent firmware or a custom firmware to be resources include the first 80 bytes of data RAM and programmed. Refer to the “dsPIC33F/PIC24H Flash two I/O pins. Programming Specification” (DS70152) document for details about In-Circuit Serial Programming (ICSP). Any of the three pairs of programming clock/data pins can be used: • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 © 2007-2012 Microchip Technology Inc. DS70283K-page 217

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 21.8 Code Protection and When coupled with software encryption libraries, Code- CodeGuard™ Security Guard™ Security can be used to securely update Flash even when multiple IPs reside on the single chip. The dsPIC33FJ32MC202/204 and The code protection features are controlled by the dsPIC33FJ16MC304 devices offer the intermediate Configuration registers: FBS and FGS. implementation of CodeGuard™ Security. CodeGuard Security enables multiple parties to securely share Secure segment and RAM protection is not resources (memory, interrupts and peripherals) on a implemented in dsPIC33FJ32MC202/204 and single chip. This feature helps protect individual dsPIC33FJ16MC304 devices. Intellectual Property in collaborative system designs. Note: Refer to Section 23. “CodeGuard™ Security” (DS70199) in the “dsPIC33F/PIC24H Family Reference Manual” for further information on usage, configuration and operation of CodeGuard Security. TABLE 21-3: CODE FLASH SECURITY TABLE 21-4: CODE FLASH SECURITY SEGMENT SIZES FOR SEGMENT SIZES FOR 32KBYTE DEVICES 16KBYTE DEVICES CONFIG BITS CONFIG BITS 0x000000 0x000000 VS = 256 IW VS = 256 IW 0x0001FE 0x0001FE 0x000200 0x000200 BSS<2:0>=x11 0x0007FE BSS<2:0>=x11 0x0007FE 0x000800 0x000800 0x001FFE 0x001FFE 0K 0x002000 0K 0x002000 GS = 11008 IW 0x003FFE GS = 5376 IW 0x004000 0x0057FE 0x002BFE 0x000000 0x000000 VS = 256 IW VS = 256 IW 0x0001FE 0x0001FE 0x000200 0x000200 BS = 768 IW 0x0007FE BS = 768 IW 0x0007FE BSS<2:0>=x10 0x000800 BSS<2:0>=x10 0x000800 0x001FFE 0x001FFE 0x002000 0x002000 256 0x003FFE 256 0x004000 GS = 10240 IW GS = 4608 IW 0x0057FE 0x002BFE 0x000000 0x000000 VS = 256 IW 0x0001FE VS = 256 IW 0x0001FE 0x000200 0x000200 BSS<2:0>=x01 BS = 3840 IW 00xx00000078F00E BSS<2:0>=x01 BS = 3840 IW 00xx00000078F00E 0x001FFE 0x001FFE 0x002000 0x002000 768 0x003FFE 768 0x004000 GS = 7168 IW GS = 1536 IW 0x0057FE 0x002BFE 0x000000 0x000000 VS = 256 IW VS = 256 IW 0x0001FE 0x0001FE 0x000200 0x000200 BSS<2:0>=x00 BS = 7936 IW 00xx00000078F00E BSS<2:0>=x00 BS = 5376 IW 00xx00000078F00E 0x001FFE 0x001FFE 0x002000 0x002000 1792 0x003FFE 1792 0x004000 GS = 3072 IW 0x0057FE 0x002BFE DS70283K-page 218 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 22.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/shift instructions) have two operands: Note: This data sheet summarizes the features • The W register (with or without an address of the dsPIC33FJ32MC202/204 and modifier) or file register (specified by the value of dsPIC33FJ16MC304 devices. It is not ‘Ws’ or ‘f’) intended to be a comprehensive refer- • The bit in the W register or file register ence source. To complement the informa- (specified by a literal value or indirectly by the tion in this data sheet, refer to the contents of register ‘Wb’) “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web The literal instructions that involve data movement can site (www.microchip.com) for the latest use some of the following operands: dsPIC33F/PIC24H Family Reference • A literal value to be loaded into a W register or file Manual sections. register (specified by ‘k’) The dsPIC33F instruction set is identical to that of the • The W register or file register where the literal dsPIC30F. value is to be loaded (specified by ‘Wb’ or ‘f’) Most instructions are a single program memory word However, literal instructions that involve arithmetic or (24 bits). Only three instructions require two program logical operations use some of the following operands: memory locations. • The first source operand, which is a register ‘Wb’ Each single-word instruction is a 24-bit word, divided without any address modifier into an 8-bit opcode, which specifies the instruction • The second source operand, which is a literal type and one or more operands, which further specify value the operation of the instruction. • The destination of the result (only if not the same The instruction set is highly orthogonal and is grouped as the first source operand), which is typically a into five basic categories: register ‘Wd’ with or without an address modifier • Word or byte-oriented operations The MAC class of DSP instructions can use some of the following operands: • Bit-oriented operations • Literal operations • The accumulator (A or B) to be used (required operand) • DSP operations • The W registers to be used as the two operands • Control operations • The X and Y address space prefetch operations Table22-1 shows the general symbols used in • The X and Y address space prefetch destinations describing the instructions. • The accumulator write-back destination The dsPIC33F instruction set summary in Table22-2 lists all the instructions, along with the status flags The other DSP instructions do not involve any affected by each instruction. multiplication and can include: Most word or byte-oriented W register instructions • The accumulator to be used (required) (including barrel shift instructions) have three • The source or destination operand (designated as operands: Wso or Wdo, respectively) with or without an address modifier • The first source operand, which is typically a register ‘Wb’ without any address modifier • The amount of shift specified by a W register ‘Wn’ or a literal value • The second source operand, which is typically a register ‘Ws’ with or without an address modifier The control instructions can use some of the following • The destination of the result, which is typically a operands: register ‘Wd’ with or without an address modifier • A program memory address However, word or byte-oriented file register instructions • The mode of the table read and table write have two operands: instructions • The file register specified by the value ‘f’ • The destination, which could be either the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2007-2012 Microchip Technology Inc. DS70283K-page 219

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Most instructions are a single word. Certain (unconditional/computed branch), indirect CALL/GOTO, double-word instructions are designed to provide all the all table reads and writes and RETURN/RETFIE required information in these 48 bits. In the second instructions, which are single-word instructions but take word, the 8MSbs are ‘0’s. If this second word is exe- two or three cycles. Certain instructions that involve skip- cuted as an instruction (by itself), it will execute as a ping over the subsequent instruction require either two NOP. or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or The double-word instructions execute in two instruction two-word instruction. Moreover, double-word moves cycles. require two cycles. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the Note: For more details on the instruction set, program counter is changed as a result of the refer to the “16-bit MCU and DSC instruction. In these cases, the execution takes two Programmer’s Reference Manual” instruction cycles with the additional instruction cycle(s) (DS70157). executed as a NOP. Notable exceptions are the BRA TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator write back destination address register ∈ {W13, [W13]+ = 2} bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address ∈ {0x0000...0x1FFF} lit1 1-bit unsigned literal ∈ {0,1} lit4 4-bit unsigned literal ∈ {0...15} lit5 5-bit unsigned literal ∈ {0...31} lit8 8-bit unsigned literal ∈ {0...255} lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal ∈ {0...16384} lit16 16-bit unsigned literal ∈ {0...65535} lit23 23-bit unsigned literal ∈ {0...8388608}; LSb must be ‘0’ None Field does not require an entry, can be blank OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate PC Program Counter Slit10 10-bit signed literal ∈ {-512...511} Slit16 16-bit signed literal ∈ {-32768...32767} Slit6 6-bit signed literal ∈ {-16...16} Wb Base W register ∈ {W0..W15} Wd Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register ∈ { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing) DS70283K-page 220 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈ {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈ {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 working registers ∈ {W0..W15} Wnd One of 16 destination working registers ∈ {W0...W15} Wns One of 16 source working registers ∈ {W0...W15} WREG W0 (working register used in file register instructions) Ws Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register ∈ { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wx X data space prefetch address register for DSP instructions ∈ {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none} Wxd X data space prefetch destination register for DSP instructions ∈ {W4...W7} Wy Y data space prefetch address register for DSP instructions ∈ {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Wyd Y data space prefetch destination register for DSP instructions ∈ {W4...W7} © 2007-2012 Microchip Technology Inc. DS70283K-page 221

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 22-2: INSTRUCTION SET OVERVIEW Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB 2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z 3 AND AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z 4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z 5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None 6 BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if greater than or equal 1 1 (2) None BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None BRA GT,Expr Branch if greater than 1 1 (2) None BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None BRA LE,Expr Branch if less than or equal 1 1 (2) None BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None BRA LT,Expr Branch if less than 1 1 (2) None BRA LTU,Expr Branch if unsigned less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OA,Expr Branch if Accumulator A overflow 1 1 (2) None BRA OB,Expr Branch if Accumulator B overflow 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA SA,Expr Branch if Accumulator A saturated 1 1 (2) None BRA SB,Expr Branch if Accumulator B saturated 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None 7 BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None 8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None DS70283K-page 222 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 9 BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None 10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3) 11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) 12 BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z 13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z 14 CALL CALL lit23 Call subroutine 2 2 None CALL Wn Call indirect subroutine 1 2 None 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB 16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep 17 COM COM f f = f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z 18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z 19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z 20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z (Wb - Ws - C) 21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1 None (2 or 3) 22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1 None (2 or 3) 23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1 None (2 or 3) 24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if ≠ 1 1 None (2 or 3) 25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C 26 DEC DEC f f = f - 1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f - 1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws - 1 1 1 C,DC,N,OV,Z 27 DEC2 DEC2 f f = f - 2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f - 2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws - 2 1 1 C,DC,N,OV,Z 28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None © 2007-2012 Microchip Technology Inc. DS70283K-page 223

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV 30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV 31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 None DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indirect 1 2 None 39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z 41 IOR IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 43 LNK LNK #lit14 Link Frame Pointer 1 1 None 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z 45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply and Accumulate 1 1 OA,OB,OAB, , SA,SB,SAB AWB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB 46 MOV MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 N,Z MOV f,WREG Move f to WREG 1 1 None MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 None MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None 47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store accumulator 1 1 None DS70283K-page 224 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 48 MPY MPY Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, Wm*Wn,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB MPY Square Wm to Accumulator 1 1 OA,OB,OAB, Wm*Wm,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB 49 MPY.N MPY.N -(Multiply Wm by Wn) to Accumulator 1 1 None Wm*Wn,Acc,Wx,Wxd,Wy,Wyd 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, , SA,SB,SAB AWB 51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(Ws) MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(lit5) MUL f W3:W2 = f * WREG 1 1 None 52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f = f + 1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 53 NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None 54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None W(nd):W(nd + 1) POP.S Pop Shadow Registers 1 1 All 55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None 56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep 57 RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None 58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None 59 RESET RESET Software device Reset 1 1 None 60 RETFIE RETFIE Return from interrupt 1 3 (2) None 61 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None 62 RETURN RETURN Return from Subroutine 1 3 (2) None 63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z 64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z 65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z © 2007-2012 Microchip Technology Inc. DS70283K-page 225

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None 68 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z 69 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None 70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB 71 SL SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z 72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f - WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f - WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn - lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb - Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb - lit5 1 1 C,DC,N,OV,Z 73 SUBB SUBB f f = f - WREG - (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f - WREG - (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn - lit10 - (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb - Ws - (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb - lit5 - (C) 1 1 C,DC,N,OV,Z 74 SUBR SUBR f f = WREG - f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG - f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws - Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 - Wb 1 1 C,DC,N,OV,Z 75 SUBBR SUBBR f f = WREG - f - (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG - f - (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws - Wb - (C) 1 1 C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 - Wb - (C) 1 1 C,DC,N,OV,Z 76 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None SWAP Wn Wn = byte swap Wn 1 1 None 77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None 78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None 79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 81 ULNK ULNK Unlink Frame Pointer 1 1 None 82 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z 83 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N DS70283K-page 226 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 23.0 DEVELOPMENT SUPPORT 23.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® • Integrated Development Environment operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C® for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2007-2012 Microchip Technology Inc. DS70283K-page 227

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 23.2 MPLAB C Compilers for Various 23.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 23.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 23.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 23.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS70283K-page 228 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 23.7 MPLAB SIM Software Simulator 23.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 23.10 PICkit 3 In-Circuit Debugger/ Programmer and 23.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2007-2012 Microchip Technology Inc. DS70283K-page 229

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 23.11 PICkit 2 Development 23.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 23.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS70283K-page 230 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 24.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +160°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(4) ....................................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to Vss when VDD ≥ 3.0V(4)....................................................-0.3V to +5.6V Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(4)..................................................... -0.3V to 3.6V Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin(2)...........................................................................................................................250 mA Maximum current sourced/sunk by any 2x I/O pin(3)................................................................................................8 mA Maximum current sourced/sunk by any 4x I/O pin(3)..............................................................................................15 mA Maximum current sourced/sunk by any 8x I/O pin(3)..............................................................................................25 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports(2)...............................................................................................................200 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table24-2). 3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGECx and PGEDx pins, which are able to sink/source 12 mA. 4: Refer to the “Pin Diagrams” section for 5V tolerant pins. © 2007-2012 Microchip Technology Inc. DS70283K-page 231

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 24.1 DC Characteristics TABLE 24-1: OPERATING MIPS VS. VOLTAGE Max MIPS VDD Range Temp Range Characteristic (in Volts) (in °C) dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 — VBOR-3.6V(1) -40°C to +85°C 40 — VBOR-3.6V(1) -40°C to +125°C 40 Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules such as the ADC will have degraded performance. Device functionality is tested but not characterized. Refer to parameter BO10 in Table24-11 for the minimum and maximum BOR values. TABLE 24-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Industrial Temperature Devices Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Extended Temperature Devices Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD - Σ IOH) PD PINT + PI/O W I/O Pin Power Dissipation: I/O = Σ ({VDD - VOH} x IOH) + Σ (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ - TA)/θJA W TABLE 24-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes θ Package Thermal Resistance, 44-pin QFN JA 32 — °C/W 1 θ Package Thermal Resistance, 44-pin TFQP JA 45 — °C/W 1 θ Package Thermal Resistance, 28-pin SPDIP JA 45 — °C/W 1 θ Package Thermal Resistance, 28-pin SOIC JA 50 — °C/W 1 θ Package Thermal Resistance, 28-pin SSOP JA 71 — °C/W 1 θ Package Thermal Resistance, 28-pin QFN-S JA 35 — °C/W 1 θ Note 1: Junction to ambient thermal resistance, Theta-JA ( JA) numbers are achieved by package simulations. DS70283K-page 232 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Operating Voltage DC10 Supply Voltage VDD — 3.0 — 3.6 V Industrial and Extended DC12 VDR RAM Data Retention Voltage(2) 1.8 — — V — DC16 VPOR VDD Start Voltage — — VSS V — to ensure internal Power-on Reset signal DC17 SVDD VDD Rise Rate 0.03 — — V/ms 0-3.0V in 0.1s to ensure internal Power-on Reset signal Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: This is the limit to which VDD may be lowered without losing RAM data. © 2007-2012 Microchip Technology Inc. DS70283K-page 233

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Parameter Typical(2) Max Units Conditions No.(3) Operating Current (IDD)(1) DC20d 20 30 mA -40°C DC20a 19 22 mA +25°C 3.3V 10 MIPS(3) DC20b 19 25 mA +85°C DC20c 19 30 mA +125°C DC21d 28 40 mA -40°C DC21a 27 30 mA +25°C 3.3V 16 MIPS(3) DC21b 27 32 mA +85°C DC21c 27 36 mA +125°C DC22d 33 50 mA -40°C DC22a 33 40 mA +25°C 3.3V 20 MIPS(3) DC22b 33 40 mA +85°C DC22c 33 50 mA +125°C DC23d 44 60 mA -40°C DC23a 43 50 mA +25°C 3.3V 30 MIPS(3) DC23b 42 55 mA +85°C DC23c 41 65 mA +125°C DC24d 55 75 mA -40°C DC24a 54 65 mA +25°C 3.3V 40 MIPS DC24b 52 70 mA +85°C DC24c 51 80 mA +125°C Note 1: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (defined PMDx bits are set to zero and unimplemented PMDx bits are set to one) • CPU executing while(1) statement • JTAG is disabled 2: These parameters are characterized but not tested in manufacturing. 3: Data in “Typ” column is at 3.3V, +25ºC unless otherwise stated. DS70283K-page 234 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Parameter Typical(2) Max Units Conditions No.(3) Idle Current (IIDLE): Core OFF Clock ON Base Current(1) DC40d 7 20 mA -40°C DC40a 6 7 mA +25°C 10 MIPS DC40b 6 10 mA +85°C 3.3V DC40c 6 20 mA +125°C DC41d 10 20 mA -40°C DC41a 8 9 mA +25°C 3.3V 16 MIPS DC41b 8 10 mA +85°C DC41c 8 20 mA +125°C DC42d 11 20 mA -40°C DC42a 10 10 mA +25°C 3.3V 20 MIPS DC42b 10 12 mA +85°C DC42c 10 20 mA +125°C DC43d 14 25 mA -40°C DC43a 13 14 mA +25°C 3.3V 30 MIPS DC43b 13 15 mA +85°C DC43c 13 25 mA +125°C DC44d 14 25 mA -40°C DC44a 17 20 mA +25°C 3.3V 40 MIPS DC44b 17 20 mA +85°C DC44c 18 30 mA +125°C Note 1: Base IIDLE current is measured as follows: • CPU core is off, oscillator is configured in EC mode and external clock active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • No peripheral modules are operating; however, every peripheral is being clocked (defined PMDx bits are set to zero and unimplemented PMDx bits are set to one) • JTAG is disabled 2: These parameters are characterized but not tested in manufacturing. 3: Data in “Typ” column is at 3.3V, +25ºC unless otherwise stated. © 2007-2012 Microchip Technology Inc. DS70283K-page 235

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Parameter Typical(2) Max Units Conditions No.(3) Power-Down Current (IPD)(1) DC60d 55 500 μA -40°C DC60a 63 300 μA +25°C 3.3V Base Power-Down Current(3,4) DC60b 85 350 μA +85°C DC60c 146 600 μA +125°C DC61d 8 15 μA -40°C DC61a 2 3 μA +25°C 3.3V Watchdog Timer Current: ΔIWDT(3,5) DC61b 2 2 μA +85°C DC61c 3 5 μA +125°C Note 1: IPD (Sleep) current is measured as follows: • CPU core is off, oscillator is configured in EC mode and external clock active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled, all peripheral modules are disabled (PMDx bits are all ones) • VREGS bit (RCON<8>) = 0 (i.e., core regulator is set to stand-by while the device is in Sleep mode) • RTCC is disabled. • JTAG is disabled 2: Data in the “Typ” column is at 3.3V, +25ºC unless otherwise stated. 3: The Watchdog Timer Current is the additional current consumed when the WDT module is enabled. This current should be added to the base IPD current. 4: These currents are measured on the device containing the most memory in this family. 5: These parameters are characterized, but are not tested in manufacturing. DS70283K-page 236 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Doze Parameter No.(3) Typical(2) Max Units Conditions Ratio Doze Current (IDOZE)(1) DC73a 41 51 1:2 mA DC73f 20 28 1:64 mA -40°C 3.3V 40 MIPS DC73g 19 24 1:128 mA DC70a 40 46 1:2 mA DC70f 18 20 1:64 mA +25°C 3.3V 40 MIPS DC70g 18 20 1:128 mA DC71a 40 46 1:2 mA DC71f 18 25 1:64 mA +85°C 3.3V 40 MIPS DC71g 18 20 1:128 mA DC72a 39 55 1:2 mA DC72f 18 30 1:64 mA +125°C 3.3V 40 MIPS DC72g 18 25 1:128 mA Note 1: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDOZE measurements are as follows: • Oscillator is configured in EC mode and external clock active, OSC1 is driven with external square wave from rail-to-rail with overshoot/undershoot < 250 mV • CLKO is configured as an I/O input pin in the Configuration word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (defined PMDx bits are set to zero and unimplemented PMDx bits are set to one) • CPU executing while(1) statement • JTAG is disabled 2: Data in the “Typ” column is at 3.3V, +25ºC unless otherwise stated. © 2007-2012 Microchip Technology Inc. DS70283K-page 237

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA≤ +85°C for Industrial -40°C≤ TA≤+125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VIL Input Low Voltage DI10 I/O pins VSS — 0.2VDD V DI15 MCLR VSS — 0.2VDD V DI16 I/O Pins with OSC1 or SOSCI VSS — 0.2VDD V DI18 SDAx, SCLx VSS — 0.3 VDD V SMBus disabled DI19 SDAx, SCLx VSS — 0.8 V V SMBus enabled VIH Input High Voltage DI20 I/O Pins Not 5V Tolerant(4) 0.7VDD — VDD V I/O Pins 5V Tolerant(4) 0.7VDD — 5.5 V DI28 SDAx, SCLx 0.7 VDD — 5.5 V SMBus disabled DI29 SDAx, SCLx 2.1 — 5.5 V SMBus enabled ICNPU CNx Pull-up Current DI30 50 250 400 μA VDD = 3.3V, VPIN = VSS Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See “Pin Diagrams” for a list of digital-only and analog pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro- vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. DS70283K-page 238 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA≤ +85°C for Industrial -40°C≤ TA≤+125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. IIL Input Leakage Current(2,3) DI50 I/O Pins 5V Tolerant(4) — — ±2 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance DI51 I/O Pins Not 5V Tolerant(4) — — ±1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance, -40°C≤TA ≤+85°C DI51a I/O Pins Not 5V Tolerant(4) — — ±2 μA Shared with external refer- ence pins, -40°C≤TA ≤+85°C DI51b I/O Pins Not 5V Tolerant(4) — — ±3.5 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance, -40°C≤TA ≤+125°C DI51c I/O Pins Not 5V Tolerant(4) — — ±8 μA Analog pins shared with external reference pins, -40°C≤TA ≤+125°C DI55 MCLR — — ±2 μA VSS ≤ VPIN ≤ VDD DI56 OSC1 — — ±2 μA VSS ≤ VPIN ≤ VDD, XT and HS modes Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See “Pin Diagrams” for a list of digital-only and analog pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro- vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. © 2007-2012 Microchip Technology Inc. DS70283K-page 239

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C≤ TA≤ +85°C for Industrial -40°C≤ TA≤+125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. IICL Input Low Injection Current DI60a 0 — -5(5,8) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO, and RB14 IICH Input High Injection Current DI60b 0 — +5(6,7,8) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO, RB14, and digital 5V-tolerant designated pins ∑IICT Total Input Injection Current DI60c (sum of all I/O and control pins) -20(9) — +20(9) mA Absolute instantaneous sum of all ± input injection currents from all I/O pins (| IICL + | IICH |) ≤ ∑IICT Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See “Pin Diagrams” for a list of digital-only and analog pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro- vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. DS70283K-page 240 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param. Symbol Characteristic Min. Typ. Max. Units Conditions Output Low Voltage I/O Pins: — — 0.4 V IOL ≤ 3 mA, VDD = 3.3V 2x Sink Driver Pins - All pins not defined by 4x or 8x driver pins Output Low Voltage I/O Pins: DO10 VOL — — 0.4 V IOL ≤ 6 mA, VDD = 3.3V 4x Sink Driver Pins - RA0, RA1, RB5, RB6, RB8, RB9, RB14 Output Low Voltage I/O Pins: — — 0.4 V IOL ≤ 10 mA, VDD = 3.3V 8x Sink Driver Pins - OSCO, CLKO, RA3 Output High Voltage I/O Pins: 2x Source Driver Pins - All pins 2.4 — — V IOL≥-3 mA, VDD = 3.3V not defined by 4x or 8x driver pins Output High Voltage I/O Pins: DO20 VOH 4x Source Driver Pins - RA0, 2.4 — — V IOL≥-6 mA, VDD = 3.3V RA1, RB5, RB6, RB8, RB9, RB14 Output High Voltage I/O Pins: 8x Source Driver Pins - OSCO, 2.4 — — V IOL≥-10 mA, VDD = 3.3V CLKO, RA3 Output High Voltage IOH≥-6 mA, VDD = 3.3V 1.5 — — I/O Pins: See Note 1 2x Source Driver Pins - All pins IOH≥-5 mA, VDD = 3.3V not defined by 4x or 8x driver 2.0 — — V See Note 1 pins IOH≥-2 mA, VDD = 3.3V 3.0 — — See Note 1 Output High Voltage IOH≥-12 mA, VDD = 3.3V 1.5 — — 4x Source Driver Pins - RA0, See Note 1 RA1, RB5, RB6, RB8, RB9, IOH≥-11 mA, VDD = 3.3V DO20A VOH1 RB14 2.0 — — V See Note 1 IOH≥-3 mA, VDD = 3.3V 3.0 — — See Note 1 Output High Voltage IOH≥-16 mA, VDD = 3.3V 1.5 — — 8x Source Driver Pins - OSCO, See Note 1 CLKO, RA3 IOH≥-12 mA, VDD = 3.3V 2.0 — — V See Note 1 IOH≥-4 mA, VDD = 3.3V 3.0 — — See Note 1 Note 1: Parameters are characterized, but not tested. © 2007-2012 Microchip Technology Inc. DS70283K-page 241

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. BO10 VBOR BOR Event on VDD transition 2.40 — 2.55 V See Note 2 Note 1: Parameters are for design guidance only and are not tested in manufacturing. 2: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules such as the ADC will have degraded performance. Device functionality is tested but not characterized. TABLE 24-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(3) Min Typ(1) Max Units Conditions No. Program Flash Memory D130 EP Cell Endurance 10,000 — — E/W -40°C to +125°C D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132B VPEW VDD for Self-Timed Write VMIN — 3.6 V VMIN = Minimum operating voltage D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated, -40°C to +125°C D135 IDDP Supply Current during — 10 — mA Programming D136a TRW Row Write Time 1.32 — 1.74 ms TRW = 11064 FRC cycles, TA = +85°C, See Note 2 D136b TRW Row Write Time 1.28 — 1.79 ms TRW = 11064 FRC cycles, TA = +150°C, See Note 2 D137a TPE Page Erase Time 20.1 — 26.5 ms TPE = 168517 FRC cycles, TA = +85°C, See Note 2 D137b TPE Page Erase Time 19.5 — 27.3 ms TPE = 168517 FRC cycles, TA = +150°C, See Note 2 D138a TWW Word Write Cycle Time 42.3 — 55.9 μs TWW = 355 FRC cycles, TA = +85°C, See Note 2 D138b TWW Word Write Cycle Time 41.1 — 57.6 μs TWW = 355 FRC cycles, TA = +150°C, See Note 2 Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max). This parameter depends on the FRC accuracy (see Table24-18) and the value of the FRC Oscillator Tun- ing register (see Register8-4). For complete details on calculating the Minimum and Maximum time see Section5.3 “Programming Operations”. 3: These parameters are assured by design, but are not characterized or tested in manufacturing. DS70283K-page 242 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristics Min Typ Max Units Comments No. — CEFC External Filter Capacitor 4.7 10 — μF Capacitor must be low series Value(1) resistance (< 5 ohms) Note 1: Typical VCAP voltage = 2.5V when VDD ≥ VDDMIN. © 2007-2012 Microchip Technology Inc. DS70283K-page 243

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 24.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 AC characteristics and timing parameters. TABLE 24-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Operating voltage VDD range as described in Table24-1. FIGURE 24-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS CL Pin RL = 464Ω CL = 50 pF for all pins except OSC2 VSS 15 pF for OSC2 output TABLE 24-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol Characteristic Min Typ Max Units Conditions No. DO50 COSC2 OSC2/SOSC2 pin — — 15 pF In XT and HS modes when external clock is used to drive OSC1 DO56 CIO All I/O pins and OSC2 — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode DS70283K-page 244 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 24-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symb Characteristic Min Typ(1) Max Units Conditions No. OS10 FIN External CLKI Frequency(4) DC — 40 MHz EC (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency(5) 3.5 — 10 MHz XT 10 — 40 MHz HS — 33 kHz Sosc OS20 TOSC TOSC = 1/FOSC(4) 12.5 — DC ns — OS25 TCY Instruction Cycle Time(2,4) 25 — DC ns — OS30 TosL, External Clock in (OSC1)(5) 0.375 x TOSC — 0.625 x TOSC ns EC TosH High or Low Time OS31 TosR, External Clock in (OSC1)(5) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(3,5) — 5.2 — ns — OS41 TckF CLKO Fall Time(3,5) — 5.2 — ns — OS42 GM External Oscillator 14 16 18 mA/V VDD = 3.3V Transconductance(6) TA = +25ºC Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. 4: These parameters are characterized by similarity, but are tested in manufacturing at FIN = 40 MHz only. 5: These parameters are characterized by similarity, but are not tested in manufacturing. 6: Data for this parameter is preliminary. This parameter is characterized, but is not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70283K-page 245

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS50 FPLLI PLL Voltage Controlled 0.8 — 8 MHz ECPLL, XTPLL modes Oscillator (VCO) Input Frequency Range(2) OS51 FSYS On-Chip VCO System 100 — 200 MHz — Frequency(3) OS52 TLOCK PLL Start-up Time (Lock Time)(3) 0.9 1.5 3.1 mS — OS53 DCLK CLKO Stability (Jitter)(3) -3 0.5 3 % Measured over 100 ms period Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized by similarity, but are tested in manufacturing at 7.7 MHz input only. 3: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases or communication clocks use this formula: DCLK Peripheral Clock Jitter = ------------------------------------------------------------------------ ⎛ FOSC ⎞ -------------------------------------------------------------- ⎝ ⎠ Peripheral Bit Rate Clock For example: Fosc = 32 MHz, DCLK = 3%, SPI bit rate clock, (i.e., SCK) is 2 MHz. DCLK 3% 3% SPI SCK Jitter = ------------------------------ = ---------- = -------- = 0.75% ⎛32 MHz⎞ 16 4 -------------------- ⎝ ⎠ 2 MHz TABLE 24-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) ≤ ≤ AC CHARACTERISTICS Operating temperature -40°C TA +85°C for industrial -40°C ≤ TA ≤ +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1) F20a FRC -2 — +2 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V F20b FRC -5 — +5 % -40°C ≤ TA ≤ +125°C VDD = 3.0-3.6V Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift. TABLE 24-19: INTERNAL RC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. LPRC @ 32.768 kHz(1,2) F21a LPRC -15 ±6 +15 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V F21b LPRC -40 — +40 % -40°C ≤ TA ≤ +125°C VDD = 3.0-3.6V Note 1: Change of LPRC frequency as VDD changes. 2: LPRC impacts the Watchdog Timer Time-out Period (TWDT1). See Section21.4 “Watchdog Timer (WDT)” for more information. DS70283K-page 246 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure24-1 for load conditions. TABLE 24-20: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(2) Min Typ(1) Max Units Conditions No. DO31 TIOR Port Output Rise Time — 10 25 ns — DO32 TIOF Port Output Fall Time — 10 25 ns — DI35 TINP INTx Pin High or Low Time (input) 25 — — ns — DI40 TRBP CNx High or Low Time (input) 2 — — TCY — Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: These parameters are characterized, but are not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70283K-page 247

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD SY12 MCLR Internal SY10 POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure24-1 for load conditions. DS70283K-page 248 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 T A B LE 24-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(2) Max Units Conditions No. SY10 TMCL MCLR Pulse Width (low)(1) 2 — — μs -40°C to +85°C SY11 TPWRT Power-up Timer Period(1) — 2 — ms -40°C to +85°C 4 User programmable 8 16 32 64 128 SY12 TPOR Power-on Reset Delay(3) 3 10 30 μs -40°C to +85°C SY13 TIOZ I/O High-Impedance from 0.68 0.72 1.2 μs — MCLR Low or Watchdog Timer Reset(1) SY20 TWDT1 Watchdog Timer Time-out — — — ms See Section21.4 “Watchdog Period (1) Timer (WDT)” and LPRC parameter F21a (Table24-21). SY30 TOST Oscillator Start-up Time — 1024 — — TOSC = OSC1 period TOSC SY35 TFSCM Fail-Safe Clock Monitor — 500 900 μs -40°C to +85°C Delay(1) Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: These parameters are characterized by similarity, but are not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70283K-page 249

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-5: TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRx Note: Refer to Figure24-1 for load conditions. TABLE 24-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(2) Min Typ Max Units Conditions No. TA10 TTXH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TA15 Synchronous, 10 — — ns with prescaler Asynchronous 10 — — ns TA11 TTXL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TA15 Synchronous, 10 — — ns with prescaler Asynchronous 10 — — ns TA15 TTXP TxCK Input Period Synchronous, TCY + 40 — — ns — no prescaler Synchronous, Greater of: — — — N = prescale with prescaler 20 ns or value (TCY + 40)/N (1, 8, 64, 256) Asynchronous 20 — — ns — OS60 Ft1 SOSC1/T1CK Oscillator Input DC — 50 kHz — frequency Range (oscillator enabled by setting bit TCS (T1CON<1>)) TA20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY 1.5 TCY — — Edge to Timer Increment Note 1: Timer1 is a Type A. 2: These parameters are characterized by similarity, but are not tested in manufacturing. DS70283K-page 250 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 T ABLE 24-23: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. TB10 TtxH TxCK High Synchronous Greater of: — — ns Must also meet Time mode 20 or parameter TB15 (TCY + 20)/N N = prescale value (1, 8, 64, 256) TB11 TtxL TxCK Low Synchronous Greater of: — — ns Must also meet Time mode 20 or parameter TB15 (TCY + 20)/N N = prescale value (1, 8, 64, 256) TB15 TtxP TxCK Synchronous Greater of: — — ns N = prescale Input mode 40 or value Period (2 TCY + 40)/N (1, 8, 64, 256) TB20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns — Clock Edge to Timer Incre- ment Note 1: These parameters are characterized, but are not tested in manufacturing. TABLE 24-24: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. TC10 TtxH TxCK High Synchronous TCY + 20 — — ns Must also meet Time parameter TC15 TC11 TtxL TxCK Low Synchronous TCY + 20 — — ns Must also meet Time parameter TC15 TC15 TtxP TxCK Input Synchronous, 2 TCY + 40 — — ns N = prescale Period with prescaler value (1, 8, 64, 256) TC20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns — Clock Edge to Timer Incre- ment Note 1: These parameters are characterized, but are not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70283K-page 251

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-6: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEB TQ10 TQ11 TQ15 TQ20 POSCNT TABLE 24-25: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. TQ10 TtQH TQCK High Time Synchronous, TCY + 20 — — ns Must also meet with prescaler parameter TQ15 TQ11 TtQL TQCK Low Time Synchronous, TCY + 20 — — ns Must also meet with prescaler parameter TQ15 TQ15 TtQP TQCP Input Synchronous, 2 * TCY + 40 — — ns — Period with prescaler TQ20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — — Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing. DS70283K-page 252 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure24-1 for load conditions. TABLE 24-26: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Max Units Conditions No. IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns — With Prescaler 10 — ns IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns — With Prescaler 10 — ns IC15 TccP ICx Input Period (TCY + 40)/N — ns N = prescale value (1, 4, 16) Note 1: These parameters are characterized but not tested in manufacturing. FIGURE 24-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure24-1 for load conditions. TABLE 24-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. OC10 TccF OCx Output Fall Time — — — ns See parameter D032 OC11 TccR OCx Output Rise Time — — — ns See parameter D031 Note 1: These parameters are characterized but not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70283K-page 253

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-9: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 OCx Active Tri-state TABLE 24-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. OC15 TFD Fault Input to PWM I/O — — TCY + 20 ns — Change OC20 TFLT Fault Input Pulse-Width TCY + 20 — — ns — Note 1: These parameters are characterized but not tested in manufacturing. DS70283K-page 254 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-10: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTA MP20 PWMx FIGURE 24-11: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure24-1 for load conditions. TABLE 24-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. MP10 TFPWM PWM Output Fall Time — — — ns See parameter D032 MP11 TRPWM PWM Output Rise Time — — — ns See parameter D031 TFD Fault Input ↓ to PWM — — 50 ns — MP20 I/O Change MP30 TFH Minimum Pulse-Width 50 — — ns — Note 1: These parameters are characterized but not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70283K-page 255

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-12: QEA/QEB INPUT CHARACTERISTICS TQ36 QEA (input) TQ31 TQ30 TQ35 QEB (input) TQ41 TQ40 TQ31 TQ30 TQ35 QEB Internal TABLE 24-30: QUADRATURE DECODER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Typ(2) Max Units Conditions No. TQ30 TQUL Quadrature Input Low Time 6 TCY — ns — TQ31 TQUH Quadrature Input High Time 6 TCY — ns — TQ35 TQUIN Quadrature Input Period 12 TCY — ns — TQ36 TQUP Quadrature Phase Period 3 TCY — ns — TQ40 TQUFL Filter Time to Recognize Low, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 3) TQ41 TQUFH Filter Time to Recognize High, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 3) Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: N = Index Channel Digital Filter Clock Divide Select bits. Refer to Section 15. “Quadrature Encoder Interface (QEI)” (DS70208) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site for the latest dsPIC33F/PIC24H Family Reference Manual sections. DS70283K-page 256 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-13: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ50 TQ51 Index Internal TQ55 Position Coun- ter Reset TABLE 24-31: QEI INDEX PULSE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Max Units Conditions No. TQ50 TqIL Filter Time to Recognize Low, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) TQ51 TqiH Filter Time to Recognize High, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) TQ55 Tqidxr Index Pulse Recognized to Position 3 TCY — ns — Counter Reset (ungated index) Note 1: These parameters are characterized but not tested in manufacturing. 2: Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but index pulse recognition occurs on falling edge. © 2007-2012 Microchip Technology Inc. DS70283K-page 257

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-32: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Master Master Slave Maximum Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP Data Rate (Half-Duplex) (Full-Duplex) (Full-Duplex) 15 MHz Table24-33 — — 0,1 0,1 0,1 9 MHz — Table24-34 — 1 0,1 1 9 MHz — Table24-35 — 0 0,1 1 15 MHz — — Table24-36 1 0 0 11 MHz — — Table24-37 1 1 0 15 MHz — — Table24-38 0 1 0 11 MHz — — Table24-39 0 0 0 FIGURE 24-14: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 Note: Refer to Figure24-1 for load conditions. DS70283K-page 258 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-15: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 Note: Refer to Figure24-1 for load conditions. TABLE 24-33: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCK Frequency — — 15 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdiV2scH, SDOx Data Output Setup to 30 — — ns — TdiV2scL First SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. © 2007-2012 Microchip Technology Inc. DS70283K-page 259

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-16: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP40 SDIx MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure24-1 for load conditions. TABLE 24-34: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCK Frequency — — 9 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdoV2sc, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns — TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70283K-page 260 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-17: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure24-1 for load conditions. TABLE 24-35: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCK Frequency — — 9 MHz -40ºC to +125ºC and see Note 3 SP20 TscF SCKx Output Fall Time — — — ns See parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns — TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. © 2007-2012 Microchip Technology Inc. DS70283K-page 261

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-18: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure24-1 for load conditions. DS70283K-page 262 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCK Input Frequency — — 15 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns — TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge SP50 TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input 120 — — ns — TssL2scL SP51 TssH2doZ SSx ↑ to SDOx Output 10 — 50 ns — High-Impedance(4) SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns — SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. © 2007-2012 Microchip Technology Inc. DS70283K-page 263

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-19: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SP52 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure24-1 for load conditions. DS70283K-page 264 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-37: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCK Input Frequency — — 11 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns — TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge SP50 TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input 120 — — ns — TssL2scL SP51 TssH2doZ SSx ↑ to SDOx Output 10 — 50 ns — High-Impedance(4) SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns — SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. © 2007-2012 Microchip Technology Inc. DS70283K-page 265

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-20: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure24-1 for load conditions. DS70283K-page 266 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-38: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCK Input Frequency — — 15 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns — TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge SP50 TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input 120 — — ns — TssL2scL SP51 TssH2doZ SSx ↑ to SDOx Output 10 — 50 ns — High-Impedance(4) SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. © 2007-2012 Microchip Technology Inc. DS70283K-page 267

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-21: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure24-1 for load conditions. DS70283K-page 268 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-39: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCK Input Frequency — — 11 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns — TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge SP50 TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input 120 — — ns — TssL2scL SP51 TssH2doZ SSx ↑ to SDOx Output 10 — 50 ns — High-Impedance(4) SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. © 2007-2012 Microchip Technology Inc. DS70283K-page 269

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-22: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Start Stop Condition Condition Note: Refer to Figure24-1 for load conditions. FIGURE 24-23: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM21 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure24-1 for load conditions. DS70283K-page 270 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 T ABLE 24-40: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(3) Min(1) Max Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — μs — 400 kHz mode TCY/2 (BRG + 1) — μs — 1 MHz mode(2) TCY/2 (BRG + 1) — μs — IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — μs — 400 kHz mode TCY/2 (BRG + 1) — μs — 1 MHz mode(2) TCY/2 (BRG + 1) — μs — IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 100 ns IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns — Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) 40 — ns IM26 THD:DAT Data Input 100 kHz mode 0 — μs — Hold Time 400 kHz mode 0 0.9 μs 1 MHz mode(2) 0.2 — μs IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — μs Only relevant for Setup Time 400 kHz mode TCY/2 (BRG + 1) — μs Repeated Start 1 MHz mode(2) TCY/2 (BRG + 1) — μs condition IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — μs After this period the Hold Time 400 kHz mode TCY/2 (BRG + 1) — μs first clock pulse is 1 MHz mode(2) TCY/2 (BRG + 1) — μs generated IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — μs — Setup Time 400 kHz mode TCY/2 (BRG + 1) — μs 1 MHz mode(2) TCY/2 (BRG + 1) — μs IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns — Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns 1 MHz mode(2) TCY/2 (BRG + 1) — ns IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns — From Clock 400 kHz mode — 1000 ns — 1 MHz mode(2) — 400 ns — IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be 400 kHz mode 1.3 — μs free before a new 1 MHz mode(2) 0.5 — μs transmission can start IM50 CB Bus Capacitive Loading — 400 pF — IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 4 Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit (I2C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: These parameters are characterized by similarity, but are not tested in manufacturing. 4: Typical value for this parameter is 130 ns. © 2007-2012 Microchip Technology Inc. DS70283K-page 271

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-24: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS34 IS30 IS33 SDAx Start Stop Condition Condition FIGURE 24-25: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS70283K-page 272 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-41: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param. Symbol Characteristic(2) Min Max Units Conditions IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — μs — IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — μs — IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns — Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — μs — Hold Time 400 kHz mode 0 0.9 μs 1 MHz mode(1) 0 0.3 μs IS30 TSU:STA Start Condition 100 kHz mode 4.7 — μs Only relevant for Repeated Setup Time 400 kHz mode 0.6 — μs Start condition 1 MHz mode(1) 0.25 — μs IS31 THD:STA Start Condition 100 kHz mode 4.0 — μs After this period, the first Hold Time 400 kHz mode 0.6 — μs clock pulse is generated 1 MHz mode(1) 0.25 — μs IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — μs — Setup Time 400 kHz mode 0.6 — μs 1 MHz mode(1) 0.6 — μs IS34 THD:ST Stop Condition 100 kHz mode 4000 — ns — O Hold Time 400 kHz mode 600 — ns 1 MHz mode(1) 250 ns IS40 TAA:SCL Output Valid 100 kHz mode 0 3500 ns — From Clock 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode 1.3 — μs before a new transmission 1 MHz mode(1) 0.5 — μs can start IS50 CB Bus Capacitive Loading — 400 pF — Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 2: These parameters are characterized by similarity, but are not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70283K-page 273

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-42: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symb Characteristic Min. Typ Max. Units Conditions No. ol Device Supply AD01 AVDD Module VDD Supply(2) Greater of — Lesser of V VDD – 0.3 VDD + 0.3 — or 3.0 or 3.6 AD02 AVSS Module VSS Supply(2) VSS – 0.3 — VSS + 0.3 V — Reference Inputs AD05 VREFH Reference Voltage High AVSS + 2.5 — AVDD V See Note 1 AD05a 3.0 — 3.6 V VREFH = AVDD VREFL = AVSS = 0, see Note 2 AD06 VREFL Reference Voltage Low AVSS — AVDD – 2.5 V See Note 1 AD06a 0 — 0 V VREFH = AVDD VREFL = AVSS = 0, see Note 2 AD07 VREF Absolute Reference 2.5 — 3.6 V VREF = VREFH - VREFL Voltage(2) AD08 IREF Current Drain — 250 550 μA ADC operating, See Note 1 — — 10 μA ADC off, See Note 1 AD08a IAD Operating Current — 7.0 9.0 mA 10-bit ADC mode, See Note 2 — 2.7 3.2 mA 12-bit ADC mode, See Note 2 Analog Input AD12 VINH Input Voltage Range VINH(2) VINL — VREFH V This voltage reflects Sample and Hold Channels 0, 1, 2, and 3 (CH0-CH3), positive input AD13 VINL Input Voltage Range VINL(2) VREFL — AVSS + 1V V This voltage reflects Sample and Hold Channels 0, 1, 2, and 3 (CH0-CH3), negative input AD17 RIN Recommended Impedance — — 200 Ω 10-bit ADC of Analog Voltage Source(3) — — 200 Ω 12-bit ADC Note 1: These parameters are not characterized or tested in manufacturing. 2: These parameters are characterized, but are not tested in manufacturing. 3: These parameters are assured by design, but are not characterized or tested in manufacturing. DS70283K-page 274 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-43: ADC MODULE SPECIFICATIONS (12-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. ADC Accuracy (12-bit Mode) – Measurements with external VREF+/VREF-(3) AD20a Nr Resolution(4) 12 data bits bits — AD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD22a DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD23a GERR Gain Error — 3.4 10 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD24a EOFF Offset Error — 0.9 5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD25a — Monotonicity — — — — Guaranteed(1) ADC Accuracy (12-bit Mode) – Measurements with internal VREF+/VREF-(3) AD20a Nr Resolution(4) 12 data bits bits — AD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = 0V, AVDD = 3.6V AD22a DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = 0V, AVDD = 3.6V AD23a GERR Gain Error — 10.5 20 LSb VINL = AVSS = 0V, AVDD = 3.6V AD24a EOFF Offset Error — 3.8 10 LSb VINL = AVSS = 0V, AVDD = 3.6V AD25a — Monotonicity — — — — Guaranteed(1) Dynamic Performance (12-bit Mode)(2) AD30a THD Total Harmonic Distortion — — -75 dB — AD31a SINAD Signal to Noise and 68.5 69.5 — dB — Distortion AD32a SFDR Spurious Free Dynamic 80 — — dB — Range AD33a FNYQ Input Signal Bandwidth — — 250 kHz — AD34a ENOB Effective Number of Bits 11.09 11.3 — bits — Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: These parameters are characterized by similarity, but are not tested in manufacturing. 3: These parameters are characterized, but are tested at 20 ksps only. 4: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. © 2007-2012 Microchip Technology Inc. DS70283K-page 275

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-44: ADC MODULE SPECIFICATIONS (10-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial -40°C≤TA ≤+125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. ADC Accuracy (10-bit Mode) – Measurements with external VREF+/VREF-(3) AD20b Nr Resolution(4) 10 data bits bits — AD21b INL Integral Nonlinearity -1.5 — +1.5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD22b DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD23b GERR Gain Error — 3 6 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD24b EOFF Offset Error — 2 5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD25b — Monotonicity — — — — Guaranteed(1) ADC Accuracy (10-bit Mode) – Measurements with internal VREF+/VREF-(3) AD20b Nr Resolution(4) 10 data bits bits — AD21b INL Integral Nonlinearity -1 — +1 LSb VINL = AVSS = 0V, AVDD = 3.6V AD22b DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = 0V, AVDD = 3.6V AD23b GERR Gain Error — 7 15 LSb VINL = AVSS = 0V, AVDD = 3.6V AD24b EOFF Offset Error — 3 7 LSb VINL = AVSS = 0V, AVDD = 3.6V AD25b — Monotonicity — — — — Guaranteed(1) Dynamic Performance (10-bit Mode)(2) AD30b THD Total Harmonic Distortion — — -64 dB — AD31b SINAD Signal to Noise and 57 58.5 — dB — Distortion AD32b SFDR Spurious Free Dynamic 72 — — dB — Range AD33b FNYQ Input Signal Bandwidth — — 550 kHz — AD34b ENOB Effective Number of Bits 9.16 9.4 — bits — Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: These parameters are characterized by similarity, but are not tested in manufacturing. 3: These parameters are characterized, but are tested at 20 ksps only. 4: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. DS70283K-page 276 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-26: ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP AD61 AD60 TSAMP AD55 DONE AD1IF 1 2 3 4 5 6 7 8 9 1 – Software sets AD1CON. SAMP to start sampling. 5 – Convert bit 11. 2 – Sampling starts after discharge period. TSAMP is described in 6 – Convert bit 10. Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33F/PIC24H Family Reference Manual”. 7 – Convert bit 1. 3 – Software clears AD1CON. SAMP to start conversion. 8 – Convert bit 0. 4 – Sampling ends, conversion sequence starts. 9 – One TAD for end of conversion. TABLE 24-45: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Clock Parameters AD50 TAD ADC Clock Period(2) 117.6 — — ns — AD51 tRC ADC Internal RC Oscillator — 250 — ns — Period(2) Conversion Rate AD55 tCONV Conversion Time(2) — 14 TAD — ns — AD56 FCNV Throughput Rate(2) — — 500 Ksps — AD57 TSAMP Sample Time(2) 3.0 TAD — — — — Timing Parameters AD60 tPCS Conversion Start from Sample 2.0 TAD — 3.0 TAD — Auto convert trigger not Trigger(2) selected AD61 tPSS Sample Start from Setting 2.0 TAD — 3.0 TAD — — Sample (SAMP) bit(2) AD62 tCSS Conversion Completion to — 0.5 TAD — — — Sample Start (ASAM = 1)(2) AD63 tDPU Time to Stabilize Analog Stage — — 20 μs — from ADC Off to ADC On(2) Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures. 2: These parameters are characterized but not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70283K-page 277

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-27: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP AD61 AD60 TSAMP AD55 AD55 DONE AD1IF 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets AD1CON. SAMP to start sampling. 5 – Convert bit 9. 2 – Sampling starts after discharge period. TSAMP is described in 6 – Convert bit 8. Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33F/PIC24H Family Reference Manual”. 7 – Convert bit 0. 3 – Software clears AD1CON. SAMP to start conversion. 8 – One TAD for end of conversion. 4 – Sampling ends, conversion sequence starts. FIGURE 24-28: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Set ADON Execution SAMP TSAMP AD55 AD55 TSAMP AD55 AD1IF DONE 1 2 3 4 5 6 7 3 4 5 6 8 1 – Software sets AD1CON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. TSAMP is described in 6 – One TAD for end of conversion. Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33F/PIC24H Family Reference Manual”. 7 – Begin conversion of next channel. 3 – Convert bit 9. 8 – Sample for time specified by SAMC<4:0>. 4 – Convert bit 8. DS70283K-page 278 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-46: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min. Typ(1) Max. Units Conditions No. Clock Parameters AD50 TAD ADC Clock Period(1) 76 — — ns — AD51 tRC ADC Internal RC Oscillator — 250 — ns — Period(1) Conversion Rate AD55 tCONV Conversion Time(1) — 12 TAD — — — AD56 FCNV Throughput Rate(1) — — 1.1 Msps — AD57 TSAMP Sample Time(1) 2.0 TAD — — — — Timing Parameters AD60 tPCS Conversion Start from Sample 2.0 TAD — 3.0 TAD — Auto-Convert Trigger Trigger(1) not selected AD61 tPSS Sample Start from Setting 2.0 TAD — 3.0 TAD — — Sample (SAMP) bit(1) AD62 tCSS Conversion Completion to — 0.5 TAD — — — Sample Start (ASAM = 1)(1) AD63 tDPU Time to Stabilize Analog Stage — — 20 μs — from ADC Off to ADC On(1) Note 1: These parameters are characterized but not tested in manufacturing. 2: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures. © 2007-2012 Microchip Technology Inc. DS70283K-page 279

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 280 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 25.0 HIGH TEMPERATURE ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 electrical characteristics for devices operating in an ambient temperature range of -40°C to +150°C. The specifications between -40°C to +150°C are identical to those shown in Section24.0 “Electrical Characteristics” for operation between -40°C to +125°C, with the exception of the parameters listed in this section. Parameters in this section begin with an H, which denotes High temperature. For example, parameter DC10 in Section24.0 “Electrical Characteristics” is the Industrial and Extended temperature equivalent of HDC10. Absolute maximum ratings for the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 high temperature devices are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias(4).........................................................................................................-40°C to +150°C Storage temperature.............................................................................................................................. -65°C to +160°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(5) ....................................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(5) .................................................... -0.3V to 3.6V Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V(5) .................................................... -0.3V to 5.6V Maximum current out of VSS pin.............................................................................................................................60 mA Maximum current into VDD pin(2).............................................................................................................................60 mA Maximum junction temperature.............................................................................................................................+155°C Maximum current sourced/sunk by any 2x I/O pin(3)................................................................................................2 mA Maximum current sourced/sunk by any 4x I/O pin(3)................................................................................................4 mA Maximum current sourced/sunk by any 8x I/O pin(3)................................................................................................8 mA Maximum current sunk by all ports combined ........................................................................................................70 mA Maximum current sourced by all ports combined(2)................................................................................................70 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods can affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table25-2). 3: Unlike devices at 125°C and below, the specifications in this section also apply to the CLKOUT, VREF+, VREF-, SCLx, SDAx, PGCx and PGDx pins. 4: AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 hours. Any design in which the total operating time from 125°C to 150°C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc. 5: Refer to the “Pin Diagrams” section for 5V tolerant pins. © 2007-2012 Microchip Technology Inc. DS70283K-page 281

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 25.1 High Temperature DC Characteristics TABLE 25-1: OPERATING MIPS VS. VOLTAGE Max MIPS VDD Range Temperature Range Characteristic (in Volts) (in °C) dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 HDC5 VBOR to 3.6V(1) -40°C to +150°C 20 Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules such as the ADC will have degraded performance. Device functionality is tested but not characterized. Refer to parameter BO10 in Table24-11 for the minimum and maximum BOR values. TABLE 25-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit High Temperature Devices Operating Junction Temperature Range TJ -40 — +155 °C Operating Ambient Temperature Range TA -40 — +150 °C Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD - Σ IOH) PD PINT + PI/O W I/O Pin Power Dissipation: I/O = Σ ({VDD - VOH} x IOH) + Σ (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ - TA)/θJA W TABLE 25-3: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Parameter Symbol Characteristic Min Typ Max Units Conditions No. Operating Voltage HDC10 Supply Voltage VDD — 3.0 3.3 3.6 V -40°C to +150°C DS70283K-page 282 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Parameter Typical Max Units Conditions No. Power-Down Current (IPD) HDC60e 250 2000 μA +150°C 3.3V Base Power-Down Current(1,3) HDC61c 3 5 μA +150°C 3.3V Watchdog Timer Current: ΔIWDT(2,4) Note 1: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled to VSS. WDT, etc., are all switched off, and VREGS (RCON<8>) = 1. 2: The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 3: These currents are measured on the device containing the most memory in this family. 4: These parameters are characterized, but are not tested in manufacturing. TABLE 25-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Parameter Typical(1) Max Units Conditions No. HDC20 19 35 mA +150°C 3.3V 10 MIPS HDC21 27 45 mA +150°C 3.3V 16 MIPS HDC22 33 55 mA +150°C 3.3V 20 MIPS Note 1: These parameters are characterized, but are not tested in manufacturing. TABLE 25-6: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Parameter Doze Typical(1) Max Units Conditions No. Ratio HDC72a 39 45 1:2 mA HDC72f 18 25 1:64 mA +150°C 3.3V 20 MIPS HDC72g 18 25 1:128 mA Note 1: Parameters with Doze ratios of 1:2 and 1:64 are characterized, but are not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70283K-page 283

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-7: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param. Symbol Characteristic Min. Typ. Max. Units Conditions Output Low Voltage I/O Pins: IOL ≤ 1.8 mA, VDD = 3.3V — — 0.4 V 2x Sink Driver Pins - All pins not See Note 1 defined by 4x or 8x driver pins Output Low Voltage I/O Pins: IOL ≤ 3.6 mA, VDD = 3.3V DO10 VOL — — 0.4 V 4x Sink Driver Pins - RA0, RA1, See Note 1 RB5, RB6, RB8, RB9, RB14 Output Low Voltage I/O Pins: IOL ≤ 6 mA, VDD = 3.3V — — 0.4 V 8x Sink Driver Pins - OSCO, See Note 1 CLKO, RA3 Output High Voltage I/O Pins: IOL≥-1.8 mA, VDD = 3.3V 2x Source Driver Pins - All pins 2.4 — — V See Note 1 not defined by 4x or 8x driver pins Output High Voltage I/O Pins: IOL≥-3 mA, VDD = 3.3V DO20 VOH 4x Source Driver Pins - RA0, 2.4 — — V See Note 1 RA1, RB5, RB6, RB8, RB9, RB14 Output High Voltage I/O Pins: IOL≥-6 mA, VDD = 3.3V 8x Source Driver Pins - OSCO, 2.4 — — V See Note 1 CLKO, RA3 Output High Voltage IOH≥-1.9 mA, VDD = 3.3V 1.5 — — I/O Pins: See Note 1 2x Source Driver Pins - All pins IOH≥-1.85 mA, VDD = 3.3V not defined by 4x or 8x driver 2.0 — — V See Note 1 pins IOH≥-1.4 mA, VDD = 3.3V 3.0 — — See Note 1 Output High Voltage IOH≥-3.9 mA, VDD = 3.3V 1.5 — — 4x Source Driver Pins - RA0, See Note 1 RA1, RB5, RB6, RB8, RB9, IOH≥-3.7 mA, VDD = 3.3V DO20A VOH1 RB14 2.0 — — V See Note 1 IOH≥-2 mA, VDD = 3.3V 3.0 — — See Note 1 Output High Voltage IOH≥-7.5 mA, VDD = 3.3V 1.5 — — 8x Source Driver Pins -OSCO, See Note 1 CLKO, RA3 IOH≥-6.8 mA, VDD = 3.3V 2.0 — — V See Note 1 IOH≥-3 mA, VDD = 3.3V 3.0 — — See Note 1 Note 1: Parameters are characterized, but not tested. DS70283K-page 284 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 25.2 AC Characteristics and Timing Parameters in this section begin with an H, which Parameters denotes High temperature. For example, parameter OS53 in Section24.2 “AC Characteristics and The information contained in this section defines Timing Parameters” is the Industrial and Extended dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 temperature equivalent of HOS53. AC characteristics and timing parameters for high temperature devices. However, all AC timing specifications in this section are the same as those in Section24.2 “AC Characteristics and Timing Parameters”, with the exception of the parameters listed in this section. TABLE 25-8: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Operating voltage VDD range as described in Table25-1. FIGURE 25-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS Pin CL RL = 464Ω CL = 50 pF for all pins except OSC2 VSS 15 pF for OSC2 output TABLE 25-9: PLL CLOCK TIMING SPECIFICATIONS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic Min Typ Max Units Conditions No. HOS53 DCLK CLKO Stability (Jitter)(1) -5 0.5 5 % Measured over 100 ms period Note 1: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases or communication clocks use this formula: DCLK Peripheral Clock Jitter = ------------------------------------------------------------------------ ⎛ FOSC ⎞ -------------------------------------------------------------- ⎝ ⎠ Peripheral Bit Rate Clock For example: Fosc = 32 MHz, DCLK = 5%, SPI bit rate clock, (i.e., SCK) is 2 MHz. DCLK 5% 5% SPI SCK Jitter = ------------------------------ = ---------- = -------- = 1.25% ⎛32 MHz⎞ 16 4 -------------------- ⎝ ⎠ 2 MHz © 2007-2012 Microchip Technology Inc. DS70283K-page 285

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-10: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. HSP35 TscH2doV, SDOx Data Output Valid after — 10 25 ns — TscL2doV SCKx Edge HSP40 TdiV2scH, Setup Time of SDIx Data Input 28 — — ns — TdiV2scL to SCKx Edge HSP41 TscH2diL, Hold Time of SDIx Data Input 35 — — ns — TscL2diL to SCKx Edge Note 1: These parameters are characterized but not tested in manufacturing. TABLE 25-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. HSP35 TscH2doV, SDOx Data Output Valid after — 10 25 ns — TscL2doV SCKx Edge HSP36 TdoV2sc, SDOx Data Output Setup to 35 — — ns — TdoV2scL First SCKx Edge HSP40 TdiV2scH, Setup Time of SDIx Data Input 28 — — ns — TdiV2scL to SCKx Edge HSP41 TscH2diL, Hold Time of SDIx Data Input 35 — — ns — TscL2diL to SCKx Edge Note 1: These parameters are characterized but not tested in manufacturing. DS70283K-page 286 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. HSP35 TscH2doV, SDOx Data Output Valid after — — 35 ns — TscL2doV SCKx Edge HSP40 TdiV2scH, Setup Time of SDIx Data Input 25 — — ns — TdiV2scL to SCKx Edge HSP41 TscH2diL, Hold Time of SDIx Data Input to 25 — — ns — TscL2diL SCKx Edge HSP51 TssH2doZ SSx ↑ to SDOx Output 15 — 55 ns See Note 2 High-Impedance Note 1: These parameters are characterized but not tested in manufacturing. 2: Assumes 50 pF load on all SPIx pins. TABLE 25-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. HSP35 TscH2doV, SDOx Data Output Valid after — — 35 ns — TscL2doV SCKx Edge HSP40 TdiV2scH, Setup Time of SDIx Data Input 25 — — ns — TdiV2scL to SCKx Edge HSP41 TscH2diL, Hold Time of SDIx Data Input 25 — — ns — TscL2diL to SCKx Edge HSP51 TssH2doZ SSx ↑ to SDOX Output 15 — 55 ns See Note 2 High-Impedance HSP60 TssL2doV SDOx Data Output Valid after — — 55 ns — SSx Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Assumes 50 pF load on all SPIx pins. TABLE 25-14: INTERNAL RC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤TA≤+150°CforExtended Param Characteristic Min Typ Max Units Conditions No. LPRC @ 32.768 kHz(1,2) HF21 LPRC -70 — +70 % -40°C ≤ TA ≤ +150°C VDD = 3.0-3.6V Note 1: Change of LPRC frequency as VDD changes. 2: LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT1). See Section21.4 “Watchdog Timer (WDT)” for more information. © 2007-2012 Microchip Technology Inc. DS70283K-page 287

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-15: ADC MODULE SPECIFICATIONS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic Min Typ Max Units Conditions No. Reference Inputs HAD08 IREF Current Drain — 250 600 μA ADC operating, See Note 1 — — 50 μA ADC off, See Note 1 Note 1: These parameters are not characterized or tested in manufacturing. 2: These parameters are characterized, but are not tested in manufacturing. TABLE 25-16: ADC MODULE SPECIFICATIONS (12-BIT MODE)(3) AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic Min Typ Max Units Conditions No. ADC Accuracy (12-bit Mode) – Measurements with External VREF+/VREF-(1) HAD20a Nr Resolution(3) 12 data bits bits — HAD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD22a DNL Differential Nonlinearity > -1 — < 1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD23a GERR Gain Error -2 — 10 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD24a EOFF Offset Error -3 — 4 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V ADC Accuracy (12-bit Mode) – Measurements with Internal VREF+/VREF-(1) HAD20a Nr Resolution(3) 12 data bits bits — HAD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = 0V, AVDD = 3.6V HAD22a DNL Differential Nonlinearity > -1 — < 1 LSb VINL = AVSS = 0V, AVDD = 3.6V HAD23a GERR Gain Error 2 — 20 LSb VINL = AVSS = 0V, AVDD = 3.6V HAD24a EOFF Offset Error 2 — 10 LSb VINL = AVSS = 0V, AVDD = 3.6V Dynamic Performance (12-bit Mode)(2) HAD33a FNYQ Input Signal Bandwidth — — 200 kHz — Note 1: These parameters are characterized, but are tested at 20 ksps only. 2: These parameters are characterized by similarity, but are not tested in manufacturing. 3: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. DS70283K-page 288 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-17: ADC MODULE SPECIFICATIONS (10-BIT MODE)(3) AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic Min Typ Max Units Conditions No. ADC Accuracy (10-bit Mode) – Measurements with External VREF+/VREF-(1) HAD20b Nr Resolution(3) 10 data bits bits — HAD21b INL Integral Nonlinearity -3 — 3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD22b DNL Differential Nonlinearity > -1 — < 1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD23b GERR Gain Error -5 — 6 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V HAD24b EOFF Offset Error -1 — 5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V ADC Accuracy (10-bit Mode) – Measurements with Internal VREF+/VREF-(1) HAD20b Nr Resolution(3) 10 data bits bits — HAD21b INL Integral Nonlinearity -2 — 2 LSb VINL = AVSS = 0V, AVDD = 3.6V HAD22b DNL Differential Nonlinearity > -1 — < 1 LSb VINL = AVSS = 0V, AVDD = 3.6V HAD23b GERR Gain Error -5 — 15 LSb VINL = AVSS = 0V, AVDD = 3.6V HAD24b EOFF Offset Error -1.5 — 7 LSb VINL = AVSS = 0V, AVDD = 3.6V Dynamic Performance (10-bit Mode)(2) HAD33b FNYQ Input Signal Bandwidth — — 400 kHz — Note 1: These parameters are characterized, but are tested at 20 ksps only. 2: These parameters are characterized by similarity, but are not tested in manufacturing. 3: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. © 2007-2012 Microchip Technology Inc. DS70283K-page 289

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-18: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic Min Typ Max Units Conditions No. Clock Parameters HAD50 TAD ADC Clock Period(1) 147 — — ns — Conversion Rate HAD56 FCNV Throughput Rate(1) — — 400 Ksps — Note 1: These parameters are characterized but not tested in manufacturing. TABLE 25-19: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param Symbol Characteristic Min Typ Max Units Conditions No. Clock Parameters HAD50 TAD ADC Clock Period(1) 104 — — ns — Conversion Rate HAD56 FCNV Throughput Rate(1) — — 800 Ksps — Note 1: These parameters are characterized but not tested in manufacturing. DS70283K-page 290 © 2007-2012 Microchip Technology Inc.

© 26.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS 2 0 0 7 Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. -20 The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range 1 2 (e.g., outside specified power supply range) and therefore, outside the warranted range. M d ic ro s ch FIGURE 26-1: VOH – 2x DRIVER PINS FIGURE 26-3: VOH – 8x DRIVER PINS P ip T --00..001166 --00..004400 I e C ch 3.6V n --00..001144 --00..003355 3 o 3.6V lo 3 gy Inc. A)A) ----0000....000011112020 3.3V 3V A)A) ----0000....000032320505 3.3V 3V FJ3 H (H ( --00..000088 H (H ( --00..002200 2 OO OO M II --00..000066 II --00..001155 C --00..000044 -0.010 2 -0.002 0 -0.005 2 0.000 0.000 / 2 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 1.00 2.00 3.00 4.00 0 VOH (V) VOH (V) 4 a FIGURE 26-2: VOH – 4x DRIVER PINS FIGURE 26-4: VOH – 16x DRIVER PINS n d --00..003300 --00..008800 d 3.6V --00..007700 --00..002255 3.6V s 3.3V --00..006600 P 3.3V I --00..002200 --00..005500 C 3V A)A) A)A) 3V 3 H (H ( --00..001155 H (H ( --00..004400 3 OO OO II II --00..003300 F --00..001100 J D --00..002200 1 S -0.005 6 7 -0.010 02 M 8 3K 0.000 0.000 C -p 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 1.00 2.00 3.00 4.00 a 3 ge VOH (V) VOH (V) 0 2 9 4 1

D FIGURE 26-5: VOL – 2x DRIVER PINS FIGURE 26-7: VOL – 8x DRIVER PINS d S 7 s 0 2 P 83 00..002200 00..006600 K I -p 00..001188 C ag 3.6V 00..005500 3.6V 3 e 00..001166 29 3.3V 3.3V 3 2 00..001144 00..004400 F 00..001122 3V 3V J A)A) A)A) 3 L (L ( 00..001100 L (L ( 00..003300 2 OO OO II 00..000088 II M 00..002200 00..000066 C 0.004 2 0.010 0 0.002 2 0.000 0.000 / 2 0.00 1.00 2.00 3.00 4.00 0.00 1.00 2.00 3.00 4.00 0 VOL (V) VOL (V) 4 a n d FIGURE 26-6: VOL – 4x DRIVER PINS FIGURE 26-8: VOL – 16x DRIVER PINS d s 00..004400 00..112200 P I 00..003355 3.6V 00..110000 3.6V C 3 00..003300 3.3V 3.3V 3 00..008800 00..002255 3V 3V F 200© L (A)L (A) 00..002200 L (A)L (A) 00..006600 J1 7 OO OO 6 -2 II 00..001155 II 01 00..004400 M 2 M 00..001100 C icroch 0.005 0.020 30 ip T 0.000 0.000 4 e c 0.00 1.00 2.00 3.00 4.00 0.00 1.00 2.00 3.00 4.00 h n o lo VOL (V) VOL (V) g y In c .

© FIGURE 26-9: TYPICAL IPD CURRENT @ VDD = 3.3V, +85ºC FIGURE 26-11: TYPICAL IDOZE CURRENT @ VDD = 3.3V, +85ºC 2 0 0 7 -2 700 0 1 60.00 2 M 600 d icro 50.00 s c h 500 P ip Technology Inc. IPD Current [µA]234200000000 Current (mA)234000...000000 IC33FJ 3 10.00 2 100 M 0.00 C 0 1:1 1:2 1:64 1:128 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110120 2 Doze Ratio 0 Temperature Celsius 2 / 2 FIGURE 26-10: TYPICAL IDD CURRENT @ VDD = 3.3V, +85ºC FIGURE 26-12: TYPICAL IIDLE CURRENT @ VDD = 3.3V, +85ºC 0 4 a 60 25 n d 50 20 d s 40 A) P e (mA) 30 PMD = 0, with PLL ent (m 15 IC erag Curr 10 33 v A 20 LEL F D II J D 10 5 1 S 6 702 PMD = 0, no PLL M 8 0 3K 0 10 20 30 40 50 60 0 C -p 0 10 20 30 40 a FCY(MIPS) 3 g MIPS e 0 2 9 4 3

D FIGURE 26-13: TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 26-14: TYPICAL LPRC FREQUENCY @ VDD = 3.3V d S 7 s 0 2 P 83 7450 35 K I -p 33 C ag 7400 3 e 31 2 3 94 77335500 z) 2299 F H ncy (kHz)quen 77320500 uency (kFreq 222573 J32M Fre RC 21 C 7200 P LL 2 19 0 7150 17 2 / 7100 15 2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 0 Temperature Celsius Temperature Celsius 4 a n d d s P I C 3 3 F © J 2 0 1 0 7 6 -2 0 M 1 2 M C ic ro 3 ch 0 ip T 4 e c h n o lo g y In c .

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX dsPIC33FJ32MC XXXXXXXXXXXXXXXXX 202-E/SPe3 YYWWNNN 0730235 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX dsPIC33FJ32MC XXXXXXXXXXXXXXXXXXXX 202-E/SO e3 XXXXXXXXXXXXXXXXXXXX 0730235 YYWWNNN 28-Lead SSOP Example XXXXXXXXXXXX 33FJ32MC XXXXXXXXXXXX 202-E/SS e3 YYWWNNN 0730235 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007-2012 Microchip Technology Inc. DS70283K-page 295

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 27.1 Package Marking Information (Continued) 28-Lead QFN-S Example XXXXXXXX 33FJ32MC XXXXXXXX 202E/MMe3 YYWWNNN 0730235 44-Lead QFN Example XXXXXXXXXX dsPIC33FJ32 XXXXXXXXXX MC204-E/ML e3 XXXXXXXXXX 0730235 YYWWNNN 44-Lead TQFP Example XXXXXXXXXX dsPIC33FJ XXXXXXXXXX 32MC204 XXXXXXXXXX -E/PTe3 YYWWNNN 0730235 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. DS70283K-page 296 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 27.2 Package Details 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L c A1 b1 b e eB Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e .100 BSC Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .335 Molded Package Width E1 .240 .285 .295 Overall Length D 1.345 1.365 1.400 Tip to Seating Plane L .110 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .050 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-070B © 2007-2012 Microchip Technology Inc. DS70283K-page 297

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70283K-page 298 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2007-2012 Microchip Technology Inc. DS70283K-page 299

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70283K-page 300 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:18)(cid:14)(cid:19)(cid:20)(cid:9)(cid:16)(cid:21)(cid:7)(cid:11)(cid:11)(cid:9)(cid:22)(cid:23)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:24)(cid:16)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:28)(cid:29)(cid:30)(cid:9)(cid:21)(cid:21)(cid:9)(cid:31) (cid:8)!(cid:9)"(cid:16)(cid:16)(cid:22)(cid:10)# $ (cid:13)(cid:6)% 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 5(cid:26)(cid:20)&! (cid:19)(cid:29)66(cid:29)(cid:19)+(cid:25)+(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)6(cid:20)’(cid:20)&! (cid:19)(cid:29)7 78(cid:19) (cid:19)(cid:7)9 7"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)(cid:31)(cid:20)(cid:26)! 7 (cid:17): (cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)(cid:16).(cid:14)/(cid:3)0 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14);(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) < < (cid:17)(cid:30)(cid:4)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:7)(cid:17) (cid:15)(cid:30)(cid:16). (cid:15)(cid:30)(cid:18). (cid:15)(cid:30):. (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4). < < 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)=(cid:20)#&(cid:24) + (cid:18)(cid:30)(cid:5)(cid:4) (cid:18)(cid:30):(cid:4) :(cid:30)(cid:17)(cid:4) (cid:19)(cid:23)(cid:27)#(cid:13)#(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)=(cid:20)#&(cid:24) +(cid:15) .(cid:30)(cid:4)(cid:4) .(cid:30),(cid:4) .(cid:30)(cid:16)(cid:4) 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:6)(cid:30)(cid:6)(cid:4) (cid:15)(cid:4)(cid:30)(cid:17)(cid:4) (cid:15)(cid:4)(cid:30).(cid:4) 2(cid:23)(cid:23)&(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) 6 (cid:4)(cid:30).. (cid:4)(cid:30)(cid:18). (cid:4)(cid:30)(cid:6). 2(cid:23)(cid:23)&(cid:10)(cid:22)(cid:20)(cid:26)& 6(cid:15) (cid:15)(cid:30)(cid:17).(cid:14)(cid:8)+2 6(cid:13)(cid:11)#(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:21) (cid:4)(cid:30)(cid:4)(cid:6) < (cid:4)(cid:30)(cid:17). 2(cid:23)(cid:23)&(cid:14)(cid:7)(cid:26)(cid:12)(cid:27)(cid:13) (cid:3) (cid:4)> (cid:5)> :> 6(cid:13)(cid:11)#(cid:14)=(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:17)(cid:17) < (cid:4)(cid:30),: $ (cid:13)(cid:6)(cid:12)% (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)!(cid:14)(cid:2)(cid:14)(cid:11)(cid:26)#(cid:14)+(cid:15)(cid:14)#(cid:23)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:20)(cid:26)(cid:21)(cid:27)"#(cid:13)(cid:14)’(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:30)(cid:14)(cid:19)(cid:23)(cid:27)#(cid:14)%(cid:27)(cid:11)!(cid:24)(cid:14)(cid:23)(cid:22)(cid:14)(cid:10)(cid:22)(cid:23)&(cid:22)"!(cid:20)(cid:23)(cid:26)!(cid:14)!(cid:24)(cid:11)(cid:27)(cid:27)(cid:14)(cid:26)(cid:23)&(cid:14)(cid:13)$(cid:21)(cid:13)(cid:13)#(cid:14)(cid:4)(cid:30)(cid:17)(cid:4)(cid:14)’’(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)!(cid:20)#(cid:13)(cid:30) ,(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19)+(cid:14)-(cid:15)(cid:5)(cid:30).(cid:19)(cid:30) /(cid:3)01 /(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8)+21 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)(cid:18),/ © 2007-2012 Microchip Technology Inc. DS70283K-page 301

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70283K-page 302 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)&(cid:23)(cid:7)(cid:8)(cid:9)’(cid:11)(cid:7)(cid:13)((cid:9)$ (cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:20)(cid:7))(cid:6)(cid:9)(cid:24)**(cid:25)(cid:9)(cid:26)(cid:9)+,+,(cid:30)(cid:28)-(cid:9)(cid:21)(cid:21)(cid:9)(cid:31) (cid:8)!(cid:9)"&’$(cid:4)(cid:16)# .(cid:14)(cid:13)(cid:17)(cid:9)(cid:30)(cid:28)/(cid:30)(cid:9)(cid:21)(cid:21)(cid:9)0 (cid:19)(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)(cid:19))(cid:13)(cid:17) $ (cid:13)(cid:6)% 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) D D2 EXPOSED PAD e E2 E b 2 2 1 1 K N N L NOTE1 TOPVIEW BOTTOMVIEW A A3 A1 5(cid:26)(cid:20)&! (cid:19)(cid:29)66(cid:29)(cid:19)+(cid:25)+(cid:8)(cid:3) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:14)6(cid:20)’(cid:20)&! (cid:19)(cid:29)7 78(cid:19) (cid:19)(cid:7)9 7"’)(cid:13)(cid:22)(cid:14)(cid:23)%(cid:14)(cid:31)(cid:20)(cid:26)! 7 (cid:17): (cid:31)(cid:20)&(cid:21)(cid:24) (cid:13) (cid:4)(cid:30)(cid:16).(cid:14)/(cid:3)0 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14);(cid:13)(cid:20)(cid:12)(cid:24)& (cid:7) (cid:4)(cid:30):(cid:4) (cid:4)(cid:30)(cid:6)(cid:4) (cid:15)(cid:30)(cid:4)(cid:4) (cid:3)&(cid:11)(cid:26)#(cid:23)%%(cid:14) (cid:7)(cid:15) (cid:4)(cid:30)(cid:4)(cid:4) (cid:4)(cid:30)(cid:4)(cid:17) (cid:4)(cid:30)(cid:4). 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:14)(cid:25)(cid:24)(cid:20)(cid:21)3(cid:26)(cid:13)!! (cid:7), (cid:4)(cid:30)(cid:17)(cid:4)(cid:14)(cid:8)+2 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)=(cid:20)#&(cid:24) + (cid:16)(cid:30)(cid:4)(cid:4)(cid:14)/(cid:3)0 +$(cid:10)(cid:23)!(cid:13)#(cid:14)(cid:31)(cid:11)#(cid:14)=(cid:20)#&(cid:24) +(cid:17) ,(cid:30)(cid:16). ,(cid:30)(cid:18)(cid:4) (cid:5)(cid:30)(cid:18)(cid:4) 8 (cid:13)(cid:22)(cid:11)(cid:27)(cid:27)(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2) (cid:16)(cid:30)(cid:4)(cid:4)(cid:14)/(cid:3)0 +$(cid:10)(cid:23)!(cid:13)#(cid:14)(cid:31)(cid:11)#(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) (cid:2)(cid:17) ,(cid:30)(cid:16). ,(cid:30)(cid:18)(cid:4) (cid:5)(cid:30)(cid:18)(cid:4) 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:14)=(cid:20)#&(cid:24) ) (cid:4)(cid:30)(cid:17), (cid:4)(cid:30),: (cid:4)(cid:30)(cid:5), 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:14)6(cid:13)(cid:26)(cid:12)&(cid:24) 6 (cid:4)(cid:30),(cid:4) (cid:4)(cid:30)(cid:5)(cid:4) (cid:4)(cid:30).(cid:4) 0(cid:23)(cid:26)&(cid:11)(cid:21)&(cid:9)&(cid:23)(cid:9)+$(cid:10)(cid:23)!(cid:13)#(cid:14)(cid:31)(cid:11)# ? (cid:4)(cid:30)(cid:17)(cid:4) < < $ (cid:13)(cid:6)(cid:12)% (cid:15)(cid:30) (cid:31)(cid:20)(cid:26)(cid:14)(cid:15)(cid:14) (cid:20)!"(cid:11)(cid:27)(cid:14)(cid:20)(cid:26)#(cid:13)$(cid:14)%(cid:13)(cid:11)&"(cid:22)(cid:13)(cid:14)’(cid:11)(cid:28)(cid:14) (cid:11)(cid:22)(cid:28)((cid:14))"&(cid:14)’"!&(cid:14))(cid:13)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)*(cid:20)&(cid:24)(cid:20)(cid:26)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:24)(cid:11)&(cid:21)(cid:24)(cid:13)#(cid:14)(cid:11)(cid:22)(cid:13)(cid:11)(cid:30) (cid:17)(cid:30) (cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)(cid:20)!(cid:14)!(cid:11)*(cid:14)!(cid:20)(cid:26)(cid:12)"(cid:27)(cid:11)&(cid:13)#(cid:30) ,(cid:30) (cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:20)(cid:26)(cid:12)(cid:14)(cid:11)(cid:26)#(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:20)(cid:26)(cid:12)(cid:14)(cid:10)(cid:13)(cid:22)(cid:14)(cid:7)(cid:3)(cid:19)+(cid:14)-(cid:15)(cid:5)(cid:30).(cid:19)(cid:30) /(cid:3)01 /(cid:11)!(cid:20)(cid:21)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)(cid:30)(cid:14)(cid:25)(cid:24)(cid:13)(cid:23)(cid:22)(cid:13)&(cid:20)(cid:21)(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)(cid:13)$(cid:11)(cid:21)&(cid:14) (cid:11)(cid:27)"(cid:13)(cid:14)!(cid:24)(cid:23)*(cid:26)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)!(cid:30) (cid:8)+21 (cid:8)(cid:13)%(cid:13)(cid:22)(cid:13)(cid:26)(cid:21)(cid:13)(cid:14)(cid:2)(cid:20)’(cid:13)(cid:26)!(cid:20)(cid:23)(cid:26)((cid:14)"!"(cid:11)(cid:27)(cid:27)(cid:28)(cid:14)*(cid:20)&(cid:24)(cid:23)"&(cid:14)&(cid:23)(cid:27)(cid:13)(cid:22)(cid:11)(cid:26)(cid:21)(cid:13)((cid:14)%(cid:23)(cid:22)(cid:14)(cid:20)(cid:26)%(cid:23)(cid:22)’(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:10)"(cid:22)(cid:10)(cid:23)!(cid:13)!(cid:14)(cid:23)(cid:26)(cid:27)(cid:28)(cid:30) (cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:25)(cid:13)(cid:21)(cid:24)(cid:26)(cid:23)(cid:27)(cid:23)(cid:12)(cid:28)(cid:2)(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:15)(cid:17)(cid:5)/ © 2007-2012 Microchip Technology Inc. DS70283K-page 303

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)&(cid:23)(cid:7)(cid:8)(cid:9)’(cid:11)(cid:7)(cid:13)((cid:9)$ (cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:20)(cid:7))(cid:6)(cid:9)(cid:24)**(cid:25)(cid:9)(cid:26)(cid:9)+,+,(cid:30)(cid:28)-(cid:9)(cid:21)(cid:21)(cid:9)(cid:31) (cid:8)!(cid:9)"&’$(cid:4)(cid:16)# .(cid:14)(cid:13)(cid:17)(cid:9)(cid:30)(cid:28)/(cid:30)(cid:9)(cid:21)(cid:21)(cid:9)0 (cid:19)(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)(cid:19))(cid:13)(cid:17) $ (cid:13)(cid:6)% 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) DS70283K-page 304 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E E2 b 2 2 1 1 N NOTE 1 N L K TOP VIEW BOTTOM VIEW A A3 A1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 44 Pitch e 0.65 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E 8.00 BSC Exposed Pad Width E2 6.30 6.45 6.80 Overall Length D 8.00 BSC Exposed Pad Length D2 6.30 6.45 6.80 Contact Width b 0.25 0.30 0.38 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-103B © 2007-2012 Microchip Technology Inc. DS70283K-page 305

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 //(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)&(cid:23)(cid:7)(cid:8)(cid:9)’(cid:11)(cid:7)(cid:13)((cid:9)$ (cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:20)(cid:7))(cid:6)(cid:9)(cid:24)*(cid:5)(cid:25)(cid:9)(cid:26)(cid:9)(cid:3),(cid:3)(cid:9)(cid:21)(cid:21)(cid:9)(cid:31) (cid:8)!(cid:9)"&’$# $ (cid:13)(cid:6)% 2(cid:23)(cid:22)(cid:14)&(cid:24)(cid:13)(cid:14)’(cid:23)!&(cid:14)(cid:21)"(cid:22)(cid:22)(cid:13)(cid:26)&(cid:14)(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:13)(cid:14)#(cid:22)(cid:11)*(cid:20)(cid:26)(cid:12)!((cid:14)(cid:10)(cid:27)(cid:13)(cid:11)!(cid:13)(cid:14)!(cid:13)(cid:13)(cid:14)&(cid:24)(cid:13)(cid:14)(cid:19)(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:14)(cid:31)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:21)(cid:20)%(cid:20)(cid:21)(cid:11)&(cid:20)(cid:23)(cid:26)(cid:14)(cid:27)(cid:23)(cid:21)(cid:11)&(cid:13)#(cid:14)(cid:11)&(cid:14) (cid:24)&&(cid:10)144***(cid:30)’(cid:20)(cid:21)(cid:22)(cid:23)(cid:21)(cid:24)(cid:20)(cid:10)(cid:30)(cid:21)(cid:23)’4(cid:10)(cid:11)(cid:21)3(cid:11)(cid:12)(cid:20)(cid:26)(cid:12) DS70283K-page 306 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A c φ β A1 A2 L L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 44 Lead Pitch e 0.80 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.30 0.37 0.45 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-076B © 2007-2012 Microchip Technology Inc. DS70283K-page 307

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70283K-page 308 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 APPENDIX A: REVISION HISTORY • The following tables in Section24.0 “Electrical Characteristics” have been updated with preliminary values: Revision A (February 2007) - Updated Max MIPS for -40°C to +125°C This is the initial released version of the document. Temp Range (see Table24-1) - Updated parameter DC18 (see Table24-4) Revision B (May 2007) - Added new parameters for +125°C, and updated Typical and Max values for most This revision includes the following corrections and parameters (see Table24-5) updates: - Added new parameters for +125°C, and • Minor typographical and formatting corrections updated Typical and Max values for most throughout the data sheet text. parameters (see Table24-6) • New content: - Added new parameters for +125°C, and - Addition of bullet item (16-word conversion updated Typical and Max values for most result buffer) (see Section20.1 “Key parameters (see Table24-7) Features”) - Added new parameters for +125°C, and • Updated register map information for RPINR14 updated Typical and Max values for most and RPINR15 (see Table4-16) parameters (see Table24-8) • Figure updates: - Updated parameter DI51, added parameters - Updated Oscillator System Diagram (see DI51a, DI51b, and DI51c (see Table 24-9) Figure8-1) - Added Note 1 (see Table24-11) - Updated WDT Block Diagram (see - Updated parameters OS10 and OS30 (see Figure21-2) Table24-16) • Equation update: - Updated parameter OS52 (see Table24-17) - Serial Clock Rate (see Equation17-1) - Updated parameter F20, added Note 2 (see • Register updates: Table24-18) - Peripheral Pin Select Input Registers (see - Updated parameter F21 (see Table24-19) Register10-1 through Register10-13) - Updated parameter TA15 (see Table24-22) - Updated ADC1 Input Channel 0 Select - Updated parameter TB15 (see Table24-23) register (see Register20-5) - Updated parameter TC15 (see Table24-24) - Updated parameter IC15 (see Table24-26) - Updated parameters AD05, AD06, AD07, AD08, AD10 through AD13 and AD17; added parameters AD05a and AD06a; added Note 2; modified ADC Accuracy headings to include measurement information (see Table24-38) - Separated the ADC Module Specifications table into three tables (see Table24-38, Table24-39, and Table24-40) - Updated parameter AD50 (see Table24-41) - Updated parameters AD50 and AD57 (see Table24-42) © 2007-2012 Microchip Technology Inc. DS70283K-page 309

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision C (June 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in the following table. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Added Extended Interrupts column to Remappable Peripherals in the Signal Controllers” Controller Families table and Note 3 (see Table1). Added Note 1 to all pin diagrams, which references RPn pin usage by remappable peripherals (see “Pin Diagrams”). Section1.0 “Device Overview” Changed PORTA pin name from RA15 to RA10 (see Table1-1). Section4.0 “Memory Organization” Added SFR definitions (ACCAL, ACCAH, ACCAU, ACCBL, ACCBH, and ACCBU) to the CPU Core Register Map (see Table4-1). Updated Reset value for CORCON (see Table4-1). Updated Reset values for the following SFRs: IPC1, IPC3-IPC5, IPC7, IPC16, and INTTREG (see Table4-4). Updated all SFR names in QEI1 Register Map (see Table4-10). Updated the bit range for AD1CON3 from ADCS<5:0> to ADCS<7:0>) (see Table4-14 and Table4-15). Updated the Reset value for CLKDIV in the System Control Register Map (see Table4-23). Section6.0 “Resets” Entire section was replaced to maintain consistency with other dsPIC33F data sheets. Section8.0 “Oscillator Removed the first sentence of the third clock source item (External Clock) in Configuration” Section8.1.1.2 “Primary”. Updated the default bit values for DOZE and FRCDIV in the Clock Divisor Register (see Register8-2). Added the center frequency in the OSCTUN register for the FRC Tuning bits (TUN<5:0>) value 011111 and updated the center frequency for bits value 011110 (see Register8-4). Section9.0 “Power-Saving Added the following two registers: Features” • PMD1: Peripheral Module Disable Control Register 1 • PMD2: Peripheral Module Disable Control Register 2 • PMD3: Peripheral Module Disable Control Register 3 Section10.0 “I/O Ports” Added paragraph and Table 10-1 to Section10.2 “Open-Drain Configuration”, which provides details on I/O pins and their functionality. Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • 9.4.2 “Available Peripherals” • 9.4.3.3 “Mapping” • 9.4.5 “Considerations for Peripheral Pin Selection” Section14.0 “Output Compare” Replaced sections 13.1, 13.2, and 13.3 and related figures and tables with entirely new content. DS70283K-page 310 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section15.0 “Motor Control PWM Removed the following sections, which are now available in the related Module” section of the dsPIC33F/PIC24H Family Reference Manual: • 14.3 “PWM Time Base” • 14.4 “PWM Period” • 14.5 “Edge-Aligned PWM” • 14.6 “Center-Aligned PWM” • 14.7 “PWM Duty Cycle Comparison Units” • 14.8 “Complementary PWM Operation” • 14.9 “Dead-Time Generators” • 14.10 “Independent PWM Output” • 14.11 “Single Pulse PWM Operation” • 14.12 “PWM Output Override” • 14.13 “PWM Output and Polarity Control” • 14.14 “PWM Fault Pins” • 14.15 “PWM Update Lockout” • 14.16 “PWM Special Event Trigger” • 14.17 “PWM Operation During CPU Sleep Mode” • 14.18 “PWM Operation During CPU Idle Mode” Section16.0 “Quadrature Encoder Removed the following sections, which are now available in the related Interface (QEI) Module” section of the dsPIC33F/PIC24H Family Reference Manual: • 15.1 “Quadrature Encoder Interface Logic” • 15.2 “16-bit Up/Down Position Counter Mode” • 15.3 “Position Measurement Mode” • 15.4 “Programmable Digital Noise Filters” • 15.5 “Alternate 16-bit Timer/Counter” • 15.6 QEI Module Operation During CPU Sleep Mode” • 15.7 “QEI Module Operation During CPU Idle Mode” • 15.8 “Quadrature Encoder Interface Interrupts” Section17.0 “Serial Peripheral Removed the following sections, which are now available in the related Interface (SPI)” section of the dsPIC33F/PIC24H Family Reference Manual: • 16.1 “Interrupts” • 16.2 “Receive Operations” • 16.3 “Transmit Operations” • 16.4 “SPI Setup” (retained Figure17-1: SPI Module Block Diagram) © 2007-2012 Microchip Technology Inc. DS70283K-page 311

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section18.0 “Inter-Integrated Removed the following sections, which are now available in the related Circuit™ (I2C™)” section of the dsPIC33F/PIC24H Family Reference Manual: • 17.3 “I2C Interrupts” • 17.4 “Baud Rate Generator” (retained Figure 15-1: I2C Block Diagram) • 17.5 “I2C Module Addresses” • 17.6 “Slave Address Masking” • 17.7 “IPMI Support” • 17.8 “General Call Address Support” • 17.9 “Automatic Clock Stretch” • 17.10 “Software Controlled Clock Stretching (STREN = 1)” • 17.11 “Slope Control” • 17.12 “Clock Arbitration” • 17.13 “Multi-Master Communication, Bus Collision, and Bus Arbitration” • 17.14 “Peripheral Pin Select Limitations” Section19.0 “Universal Removed the following sections, which are now available in the related Asynchronous Receiver Transmitter section of the dsPIC33F/PIC24H Family Reference Manual: (UART)” • 18.1 “UART Baud Rate Generator” • 18.2 “Transmitting in 8-bit Data Mode” • 18.3 “Transmitting in 9-bit Data Mode” • 18.4 “Break and Sync Transmit Sequence” • 18.5 “Receiving in 8-bit or 9-bit Data Mode” • 18.6 “Flow Control Using UxCTS and UxRTS Pins” • 18.7 “Infrared Support” Removed IrDA references and Note 1, and updated the bit and bit value descriptions for UTXINV (UxSTA<14>) in the UARTx Status and Control Register (see Register19-2). Section20.0 “10-bit/12-bit Removed Equation 19-1: ADC Conversion Clock Period and Figure 19-2: Analog-to-Digital Converter (ADC)” ADC Transfer Function (10-Bit Example). Added ADC1 Module Block Diagram for dsPIC33FJ16MC304 and dsPIC33FJ32MC204 Devices (Figure20-1) and ADC1 Module Block Diagram FOR dsPIC33FJ32MC202 Devices (Figure20-2). Added Note 2 to Figure20-3: ADC Conversion Clock Period Block Diagram. Updated ADC Conversion Clock Select bits in the AD1CON3 register from ADCS<5:0> to ADCS<7:0>. Any references to these bits have also been updated throughout this data sheet (Register20-3). Added device-specific information to Note 1 in the ADC1 Input Scan Select Register Low (see Register20-6), and updated the default bit value for bits 12-10 (CSS12-CSS10) from U-0 to R/W-0. Added device-specific information to Note 1 in the ADC1 Port Configuration Register Low (see Register20-7), and updated the default bit value for bits 12-10 (PCFG12-PCFG10) from U-0 to R/W-0. DS70283K-page 312 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section21.0 “Special Features” Added FICD register information for address 0xF8000E in the Device Configuration Register Map (see Table21-1). Added FICD register content (BKBUG, COE, JTAGEN, and ICS<1:0> to the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Configuration Bits Description (see Table21-2). Added a note regarding the placement of low-ESR capacitors, after the second paragraph of Section21.2 “On-Chip Voltage Regulator” and to Figure19-1. Removed the words “if enabled” from the second sentence in the fifth paragraph of Section21.3 “BOR: Brown-out Reset”. Section24.0 “Electrical Updated Max MIPS value for -40ºC to +125ºC temperature range in Characteristics” Operating MIPS vs. Voltage (see Table24-1). Removed Typ value for parameter DC12 (see Table24-4). Updated MIPS conditions for parameters DC24c, DC44c, DC72a, DC72f and DC72g (see Table24-5, Table24-6, and Table24-8). Added Note 4 (reference to new table containing digital-only and analog pin information to I/O Pin Input Specifications (see Table24-4). Updated Typ, Min and Max values for Program Memory parameters D136, D137 and D138 (see Table24-12). Updated Max value for Internal RC Accuracy parameter F21 for -40°C ≤ TA ≤ +125°C condition and added Note 2 (see Table24-19). Removed all values for Reset, Watchdog Timer, Oscillator Start-up Timer, and Power-up Timer parameter SY20 and updated conditions, which now refers to Section21.4 “Watchdog Timer (WDT)” and LPRC parameter F21a (see Table24-21). Updated Min and Typ values for parameters AD60, AD61, AD62 and AD63 and removed Note 3 (see Table24-41). Updated Min and Typ values for parameters AD60, AD61, AD62 and AD63 and removed Note 3 (see Table24-42). © 2007-2012 Microchip Technology Inc. DS70283K-page 313

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision D (December 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in the following table. TABLE A-2: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Updated all pin diagrams to denote the pin voltage tolerance (see “Pin Signal Controllers” Diagrams”). Section2.0 “Guidelines for Getting Added new section to the data sheet that provides guidelines on getting Started with 16-bit Digital Signal started with 16-bit Digital Signal Controllers. Controllers” Section10.0 “I/O Ports” Updated 5V tolerant status for I/O pin RB4 from Yes to No (see Table 10-1). Section24.0 “Electrical Removed the maximum value for parameter DC12 (RAM Data Retention Characteristics” Voltage) in Table24-4. Updated typical values for Operating Current (IDD) and added Note 3 in Table24-5. Updated typical and maximum values for Idle Current (IIDLE): Core OFF Clock ON Base Current and added Note 3 in Table24-6. Updated typical and maximum values for Power Down Current (IPD) and added Note 5 in Table24-7. Updated typical and maximum values for Doze Current (IDOZE) and added Note 2 in Table24-8. Added Note 3 to Table24-12. Updated minimum value for Internal Voltage Regulator Specifications in Table24-13. Added parameter OS42 (GM) and Notes 4, 5 and 6 to Table24-16. Added Notes 2 and 3 to Table24-17. Added Note 2 to Table24-20. Added Note 2 to Table24-21. Added Note 2 to Table24-22. Added Note 1 to Table24-23. Added Note 1 to Table24-24. Added Note 3 to Table24-36. Added Note 2 to Table24-37. Updated typical value for parameter AD08 (ADC in operation) and added Notes 2 and 3 in Table24-38. Updated minimum, typical, and maximum values for parameters AD23a, AD24a, AD30a, AD32a, AD32a and AD34a, and added Notes 2 and 3 in Table24-39. Updated minimum, typical, and maximum values for parameters AD23b, AD24b, AD30b, AD32b, AD32b and AD34b, and added Notes 2 and 3 in Table24-40. DS70283K-page 314 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision E (June 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: • Changed all instances of OSCI to OSC1 and OSCO to OSC2 • Changed all instances of PGCx/EMUCx and PGDx/EMUDx (where x = 1, 2 or 3) to PGECx and PGEDx Changed all instances of VDDCORE and VDDCORE/VCAP to VCAP/VDDCORE All other major changes are referenced by their respective section in the following table. TABLE A-3: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Signal Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin Controllers” diagrams, which references pin connections to VSS. Section7.0 “Interrupt Controller” Updated addresses for interrupt vectors 80, 81, 82 and 83-125 (see Table7-1). Section8.0 “Oscillator Configuration” Updated the Oscillator System Diagram (see Figure8-1). Added Note 1 to the Oscillator Tuning register (OSCTUN) (see Register8-4). Section10.0 “I/O Ports” Removed Table 10-1 and added reference to pin diagrams for I/O pin availability and functionality. Section17.0 “Serial Peripheral Interface (SPI)” Added Note 2 to the SPIx Control Register 1 (see Register17-2). Section19.0 “Universal Asynchronous Updated the UTXINV bit settings in the UxSTA register and Receiver Transmitter (UART)” added Note 1 (see Register19-2). Section24.0 “Electrical Characteristics” Updated the Min value for parameter DC12 (RAM Retention Voltage) and added Note 4 to the DC Temperature and Voltage Specifications (see Table24-4). Updated the Min value for parameter DI35 (see Table24-20). Updated AD08 and added reference to Note 2 for parameters AD05a, AD06a and AD08a (see Table24-38). © 2007-2012 Microchip Technology Inc. DS70283K-page 315

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision F (November 2009) The revision includes the following global update: • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-4: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Signal Added information on high temperature operation (see Controllers” “Operating Range:”). Section10.0 “I/O Ports” Changed the reference to digital-only pins to 5V tolerant pins in the second paragraph of Section10.2 “Open-Drain Configuration”. Section19.0 “Universal Asynchronous Updated the two baud rate range features to: 10 Mbps to 38 bps Receiver Transmitter (UART)” at 40 MIPS. Section20.0 “10-bit/12-bit Analog-to-Digital Updated the ADC1 block diagrams (see Figure20-1 and Converter (ADC)” Figure20-2). Section21.0 “Special Features” Updated the second paragraph and removed the fourth paragraph in Section21.1 “Configuration Bits”. Updated the Device Configuration Register Map (see Table21-1). Section24.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings for high temperature and added Note 4. Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics (see Figure24-17). Updated the Internal RC Accuracy parameter numbers (see Table24-18 and Table24-19). Section25.0 “High Temperature Electrical Added new chapter with high temperature specifications. Characteristics” “Product Identification System” Added the “H” definition for high temperature. Revision G (November 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-5: MAJOR SECTION UPDATES Section Name Update Description Section25.0 “High Temperature Electrical Updated MIPS rating from 16 to 20 for high temperature devices Characteristics” in “Operating Range:” and in Table25-1: Operating MIPS vs. Voltage. DS70283K-page 316 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision H (February 2011) This revision includes typographical and formatting changes throughout the data sheet text. In addition, all instances of VDDCORE have been removed. All other major changes are referenced by their respective section in the following table. TABLE A-6: MAJOR SECTION UPDATES Section Name Update Description High-Performance, 16-bit Digital Signal Added the SSOP package information (see “Packaging:”, Table1, Controllers and “Pin Diagrams”). Section2.0 “Guidelines for Getting Started Updated the title of Section2.3 “CPU Logic Filter Capacitor with 16-bit Digital Signal Controllers” Connection (VCAP)”. The frequency limitation for device PLL start-up conditions was updated in Section2.7 “Oscillator Value Conditions on Device Start-up”. The second paragraph in Section2.9 “Unused I/Os” was updated. Section3.0 “CPU” Removed references to DMA in the CPU Core Block Diagram (see Figure3-1). Section4.0 “Memory Organization” Updated the data memory reference in the third paragraph in Section4.2 “Data Address Space”. All Resets values for the following SFRs in the Timer Register Map were changed (see Table4-5): • TMR1 • TMR2 • TMR3 Section8.0 “Oscillator Configuration” Added Note 3 to the OSCCON: Oscillator Control Register (see Register8-1). Added Note 2 to the CLKDIV: Clock Divisor Register (see Register8-2). Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see Register8-3). Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see Register8-4). Section20.0 “10-bit/12-bit Analog-to-Digital Updated the VREFL references in the ADC1 module block diagrams Converter (ADC)” (see Figure20-1 and Figure20-2). Section21.0 “Special Features” Added a new paragraph and removed the third paragraph in Section21.1 “Configuration Bits”. Added the column “RTSP Effects” to the Configuration Bits Descriptions (see Table21-2). © 2007-2012 Microchip Technology Inc. DS70283K-page 317

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE A-6: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section24.0 “Electrical Characteristics” Added the 28-pin SSOP Thermal Packaging Characteristics (see Table24-3). Removed Note 4 from the DC Temperature and Voltage Specifications (see Table24-4). Updated the maximum value for parameter DI19 and added parameters DI28, DI29, DI60a, DI60b, and DI60c to the I/O Pin Input Specifications (see Table24-9). Updated Note 3 of the PLL Clock Timing Specifications (see Table24-17). Removed Note 2 from the AC Characteristics: Internal RC Accuracy (see Table24-18). Updated the characteristic description for parameter DI35 in the I/O Timing Requirements (see Table24-20). Updated all SPI specifications (see Table24-32 through Table24-39 and Figure24-14 through Figure24-21). Added Note 4 to the 12-bit mode ADC Module Specifications (see Table24-43). Added Note 4 to the 10-bit mode ADC Module Specifications (see Table24-44). Section25.0 “High Temperature Electrical Updated all ambient temperature and range values to +150ºC Characteristics” throughout the chapter. Updated the storage temperature and range to +160ºC. Updated the maximum junction temperature from +145ºC to +155ºC. Updated Note 1 in the PLL Clock Timing Specifications (see Table25-10). Added Note 3 to the 12-bit Mode ADC Module Specifications (see Table25-17). Added Note 3 to the 10-bit Mode ADC Module Specifications (see Table25-18). Section26.0 “Packaging Information” Added the 28-Lead SSOP package information (see Section26.1 “Package Marking Information” and Section26.2 “Package Details”). “Product Identification System” Added the “SS” definition for the SSOP package. DS70283K-page 318 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision J (July 2011) This revision includes typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-7: MAJOR SECTION UPDATES Section Name Update Description Section21.0 “Special Features” Added Note 3 to the Connections for the On-chip Voltage Regulator diagram (see Figure21-1). Section24.0 “Electrical Characteristics” Removed Note 3 and parameter DC10 (VCORE) from the DC Temperature and Voltage Specifications (see Table24-4). Updated the Characteristics definition and Conditions for parameter BO10 in the Electrical Characteristics: BOR (see Table24-11). Added Note 1 to the Internal Voltage Regulator Specifications (see Table24-13). Revision K (June 2012) This revision includes typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-8: MAJOR SECTION UPDATES Section Name Update Description Section24.0 “Electrical Characteristics” Added Note 1 to the Operating MIPS vs. Voltage (see Table24-1). Updated the notes in the following tables: • Operating Current (IDD) (see Table24-5) • Idle Current (IIDLE) (see Table24-6) • Power-Down Current (IPD) (see Table24-7) • Doze Current (IDOZE) (see Table24-8) Updated the conditions for Program Memory parameters D136b, D137b, and D138b (TA = +150ºC) (see Table24-12). Section25.0 “High Temperature Electrical Removed Table 23-8: DC Characteristics: Program Memory. Characteristics” Section26.0 “DC and AC Device Added new chapter. Characteristics Graphs” © 2007-2012 Microchip Technology Inc. DS70283K-page 319

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 320 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 INDEX A Configuration Register Map..............................................211 Configuring Analog Port Pins............................................118 AC Characteristics....................................................244, 285 CPU ADC Module..............................................................288 Control Register..........................................................21 ADC Module (10-bit Mode).......................................289 CPU Clocking System......................................................102 ADC Module (12-bit Mode).......................................288 PLL Configuration.....................................................102 Internal RC Accuracy................................................246 Selection...................................................................102 Load Conditions................................................244, 285 Sources....................................................................102 ADC Customer Change Notification Service.............................325 Initialization...............................................................199 Customer Notification Service..........................................325 Key Features.............................................................199 Customer Support.............................................................325 ADC Module ADC1 Register Map for dsPIC33FJ32MC202............40 D ADC1 Register Map for dsPIC33FJ32MC204 and Data Accumulators and Adder/Subtracter..........................26 dsPIC33FJ16MC304..........................................41 Data Space Write Saturation......................................28 Alternate Interrupt Vector Table (AIVT)..............................71 Overflow and Saturation.............................................26 Analog-to-Digital Converter (ADC)....................................199 Round Logic...............................................................27 Arithmetic Logic Unit (ALU).................................................24 Write Back..................................................................27 Assembler Data Address Space...........................................................31 MPASM Assembler...................................................228 Alignment....................................................................31 B Memory Map for dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Devices with 2 KBs RAM.32 Barrel Shifter.......................................................................28 Near Data Space........................................................31 Bit-Reversed Addressing....................................................49 Software Stack...........................................................46 Example......................................................................50 Width..........................................................................31 Implementation...........................................................49 DC and AC Characteristics Sequence Table (16-Entry).........................................50 Graphs and Tables...................................................291 Block Diagrams DC Characteristics............................................................232 16-bit Timer1 Module................................................143 A/D Module.......................................................200, 201 Doze Current (IDOZE)................................................283 High Temperature.....................................................282 Connections for On-Chip Voltage Regulator.............215 I/O Pin Input Specifications......................................238 Device Clock.............................................................101 I/O Pin Output Specifications............................241, 284 DSP Engine................................................................25 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304..10 Idle Current (IDOZE)..................................................237 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Idle Current (IIDLE)....................................................235 CPU Core...........................................................18 Operating Current (IDD)............................................234 Operating MIPS vs. Voltage.....................................282 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PLL 103 Power-Down Current (IPD)........................................236 Input Capture............................................................151 Power-down Current (IPD)........................................283 Program Memory......................................................242 Output Compare.......................................................155 Temperature and Voltage.........................................282 PLL............................................................................103 Temperature and Voltage Specifications..................233 PWM Module....................................................160, 161 Thermal Operating Conditions..................................282 Quadrature Encoder Interface..................................173 Development Support.......................................................227 Reset System..............................................................61 Doze Mode.......................................................................112 Shared Port Structure...............................................117 DSP Engine........................................................................24 SPI............................................................................179 Multiplier.....................................................................26 Timer2 (16-bit)..........................................................148 Timer2/3 (32-bit).......................................................148 E UART........................................................................193 Electrical Characteristics..................................................231 Watchdog Timer (WDT)............................................216 AC.....................................................................244, 285 C Equations Device Operating Frequency....................................102 C Compilers Errata....................................................................................7 MPLAB C18..............................................................228 Clock Switching.................................................................110 F Enabling....................................................................110 Fail-Safe Clock Monitor....................................................110 Sequence..................................................................110 Flash Program Memory......................................................55 Code Examples Control Registers........................................................56 Erasing a Program Memory Page...............................59 Operations..................................................................56 Initiating a Programming Sequence............................60 Programming Algorithm..............................................59 Loading Write Buffers.................................................60 RTSP Operation.........................................................56 Port Write/Read........................................................118 Table Instructions.......................................................55 PWRSAV Instruction Syntax.....................................111 Flexible Configuration.......................................................211 Code Protection........................................................211, 218 Configuration Bits..............................................................211 © 2007-2012 Microchip Technology Inc. DS70283K-page 321

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 H 6-Output Register Map for dsPIC33FJ12MC202........38 MPLAB ASM30 Assembler, Linker, Librarian...................228 High Temperature Electrical Characteristics.....................281 MPLAB Integrated Development Environment Software..227 I MPLAB PM3 Device Programmer....................................230 MPLAB REAL ICE In-Circuit Emulator System................229 I/O Ports............................................................................117 MPLINK Object Linker/MPLIB Object Librarian................228 Parallel I/O (PIO).......................................................117 Write/Read Timing....................................................118 N I2C NVM Module Addresses.................................................................187 Register Map..............................................................45 Operating Modes......................................................185 Registers...................................................................187 O Software Controlled Clock Stretching (STREN = 1)..187 Open-Drain Configuration.................................................118 I2C Module Oscillator Configuration....................................................101 I2C1 Register Map......................................................39 Output Compare...............................................................155 In-Circuit Debugger...........................................................217 In-Circuit Emulation...........................................................211 P In-Circuit Serial Programming (ICSP).......................211, 217 Packaging.........................................................................295 Input Capture....................................................................151 Details.......................................................................297 Registers...................................................................153 Marking.............................................................295, 296 Input Change Notification..................................................118 Peripheral Module Disable (PMD)....................................112 Instruction Addressing Modes.............................................46 Pinout I/O Descriptions (table)............................................11 File Register Instructions............................................46 PMD Module Fundamental Modes Supported..................................47 Register Map..............................................................45 MAC Instructions.........................................................47 PORTA MCU Instructions........................................................46 Register Map for dsPIC33FJ32MC202.......................43 Move and Accumulator Instructions............................47 Register Map for dsPIC33FJ32MC204 and Other Instructions........................................................47 dsPIC33FJ16MC304..........................................43 Instruction Set PORTB Overview...................................................................222 Register Map..............................................................44 Summary...................................................................219 PORTC Instruction-Based Power-Saving Modes...........................111 Register Map dsPIC33FJ32MC204 and Idle............................................................................112 dsPIC33FJ16MC304..........................................44 Sleep.........................................................................111 Power-on Reset (POR).......................................................67 Interfacing Program and Data Memory Spaces..................51 Power-Saving Features....................................................111 Internal RC Oscillator Clock Frequency and Switching...............................111 Use with WDT...........................................................216 Program Address Space.....................................................29 Internet Address................................................................325 Construction...............................................................51 Interrupt Control and Status Registers................................74 Data Access from Program Memory Using IECx............................................................................74 Program Space Visibility.....................................54 IFSx.............................................................................74 Data Access from Program Memory INTCON1....................................................................74 Using Table Instructions.....................................53 INTCON2....................................................................74 Data Access from, Address Generation.....................52 IPCx............................................................................74 Memory Map...............................................................29 Interrupt Setup Procedures...............................................100 Table Read Instructions Initialization...............................................................100 TBLRDH.............................................................53 Interrupt Disable........................................................100 TBLRDL..............................................................53 Interrupt Service Routine..........................................100 Visibility Operation......................................................54 Trap Service Routine................................................100 Program Memory Interrupt Vector Table (IVT)................................................71 Interrupt Vector...........................................................30 Interrupts Coincident with Power Save Instructions..........112 Organization...............................................................30 J Reset Vector...............................................................30 PWM Time Base...............................................................163 JTAG Boundary Scan Interface........................................211 JTAG Interface..................................................................217 Q M Quadrature Encoder Interface (QEI).................................173 Quadrature Encoder Interface (QEI) Module Memory Organization..........................................................29 Register Map..............................................................39 Microchip Internet Web Site..............................................325 Modulo Addressing.............................................................48 R Applicability.................................................................49 Reader Response.............................................................326 Operation Example.....................................................48 Registers Start and End Address................................................48 AD1CHS0 (ADC1 Input Channel 0 Select................209 W Address Register Selection....................................48 AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)...207 Motor Control PWM...........................................................159 AD1CON1 (ADC1 Control 1)....................................203 Motor Control PWM Module AD1CON2 (ADC1 Control 2)....................................205 2-Output Register Map................................................38 AD1CON3 (ADC1 Control 3)....................................206 DS70283K-page 322 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 AD1CSSL (ADC1 Input Scan Select Low)................210 T1CON (Timer1 Control)..........................................145 AD1PCFGL (ADC1 Port Configuration Low)............210 T2CON Control)........................................................149 CLKDIV (Clock Divisor).............................................107 T3CON Control.........................................................150 CORCON (Core Control)......................................23, 75 UxMODE (UARTx Mode).........................................195 DFLTCON (QEI Control)...........................................177 UxSTA (UARTx Status and Control)........................197 I2CxCON (I2Cx Control)...........................................188 Reset I2CxMSK (I2Cx Slave Mode Address Mask)............192 Illegal Opcode.......................................................61, 69 I2CxSTAT (I2Cx Status)...........................................190 Trap Conflict.........................................................68, 69 ICxCON (Input Capture x Control)............................153 Uninitialized W Register.......................................61, 69 IEC0 (Interrupt Enable Control 0)...............................84 Reset Sequence.................................................................71 IEC1 (Interrupt Enable Control 1)...............................86 Resets................................................................................61 IEC3 (Interrupt Enable Control 3)...............................87 S IEC4 (Interrupt Enable Control 4)...............................88 IFS0 (Interrupt Flag Status 0).....................................79 Serial Peripheral Interface (SPI).......................................179 IFS1 (Interrupt Flag Status 1).....................................81 Software Reset Instruction (SWR)......................................68 IFS3 (Interrupt Flag Status 3).....................................82 Software Simulator (MPLAB SIM)....................................229 IFS4 (Interrupt Flag Status 4).....................................83 Software Stack Pointer, Frame Pointer INTCON1 (Interrupt Control 1)....................................76 CALLL Stack Frame...................................................46 INTCON2 (Interrupt Control 2)....................................78 Special Features of the CPU............................................211 INTTREG Interrupt Control and Status Register.........99 SPI Module IPC0 (Interrupt Priority Control 0)...............................89 SPI1 Register Map.....................................................39 IPC1 (Interrupt Priority Control 1)...............................90 Symbols Used in Opcode Descriptions............................220 IPC14 (Interrupt Priority Control 14)...........................96 System Control IPC15 (Interrupt Priority Control 15)...........................97 Register Map..............................................................44 IPC16 (Interrupt Priority Control 16)...........................97 T IPC18 (Interrupt Priority Control 18)...........................98 IPC2 (Interrupt Priority Control 2)...............................91 Temperature and Voltage Specifications IPC3 (Interrupt Priority Control 3)...............................92 AC.....................................................................244, 285 IPC4 (Interrupt Priority Control 4)...............................93 Timer1..............................................................................143 IPC5 (Interrupt Priority Control 5)...............................94 Timer2/3...........................................................................147 IPC7 (Interrupt Priority Control 7)...............................95 Timing Characteristics NVMCON (Flash Memory Control).............................57 CLKO and I/O...........................................................247 NVMKEY (Nonvolatile Memory Key)..........................58 Timing Diagrams OCxCON (Output Compare x Control).....................158 10-bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0, OSCCON (Oscillator Control)...................................105 ASAM = 0, SSRC<2:0> = 000).........................278 OSCTUN (FRC Oscillator Tuning)............................109 10-bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0, P1DC2 (PWM Duty Cycle 2).....................................172 ASAM = 1, SSRC<2:0> = 111, P1DC3 (PWM Duty Cycle 3).....................................172 SAMC<4:0> = 00001).......................................278 PDC1 (PWM Duty Cycle 1).......................................172 12-bit ADC Conversion (ASAM = 0, PLLFBD (PLL Feedback Divisor)..............................108 SSRC<2:0> = 000)...........................................277 PMD1 (Peripheral Module Disable Control Brown-out Situations..................................................68 Register 1)........................................................114 External Clock..........................................................245 PMD1 (Peripheral Module Disable Control Register 1).. I2Cx Bus Data (Master Mode)..................................270 114 I2Cx Bus Data (Slave Mode)....................................272 PMD2 (Peripheral Module Disable Control I2Cx Bus Start/Stop Bits (Master Mode)...................270 Register 2)........................................................115 I2Cx Bus Start/Stop Bits (Slave Mode).....................272 PMD3 (Peripheral Module Disable Control Input Capture (CAPx)...............................................253 Register 3)........................................................116 Motor Control PWM..................................................255 PMD3 (Peripheral Module Disable Control Register 3).. Motor Control PWM Fault.........................................255 116 OC/PWM..................................................................254 PTCON (PWM Time Base Control)..........................163 Output Compare (OCx)............................................253 PTMR (PWM Timer Count Value).............................164 QEA/QEB Input........................................................256 PTPER (PWM Time Base Period)............................164 QEI Module Index Pulse...........................................257 PWMxCON1 (PWM Control 1)..................................166 Reset, Watchdog Timer, Oscillator Start-up Timer PWMxCON2 (PWM Control 2)..................................167 and Power-up Timer.........................................248 PxDTCON1 (Dead-Time Control 1)..........................168 Timer1, 2, 3 External Clock......................................250 PxDTCON2 (Dead-Time Control 2)..........................169 TimerQ (QEI Module) External Clock.......................252 PxFLTACON (Fault A Control)..................................170 Timing Requirements PxOVDCON (Override Control)................................171 ADC Conversion (10-bit mode)................................290 PxSECMP (Special Event Compare)........................165 ADC Conversion (12-bit Mode)................................290 QEICON (QEI Control)..............................................175 CLKO and I/O...........................................................247 RCON (Reset Control)................................................63 External Clock..........................................................245 SPIxCON1 (SPIx Control 1)......................................182 Input Capture............................................................253 SPIxCON2 (SPIx Control 2)......................................184 SPIx Master Mode (CKE = 0)...................................286 SPIxSTAT (SPIx Status and Control).......................181 SPIx Module Master Mode (CKE = 1)......................286 SR (CPU Status)...................................................21, 75 SPIx Module Slave Mode (CKE = 0)........................287 © 2007-2012 Microchip Technology Inc. DS70283K-page 323

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 SPIx Module Slave Mode (CKE = 1).........................287 Timer3 External Clock Requirements.......................251 Timing Specifications U 10-bit ADC Conversion Requirements......................279 12-bit ADC Conversion Requirements......................277 UART Module I2Cx Bus Data Requirements (Master Mode)...........271 UART1 Register Map..................................................39 I2Cx Bus Data Requirements (Slave Mode).............273 Universal Asynchronous Receiver Transmitter (UART)...193 Motor Control PWM Requirements...........................255 Using the RCON Status Bits...............................................69 Output Compare Requirements................................253 V PLL Clock..........................................................246, 285 QEI External Clock Requirements............................252 Voltage Regulator (On-Chip)............................................215 QEI Index Pulse Requirements.................................257 W Quadrature Decoder Requirements..........................256 Reset, Watchdog Timer, Oscillator Start-up Timer, Watchdog Time-out Reset (WDTR)....................................68 Power-up Timer and Brown-out Watchdog Timer (WDT)............................................211, 216 Reset Requirements.........................................249 Programming Considerations...................................216 Simple OC/PWM Mode Requirements.....................254 WWW Address.................................................................325 Timer1 External Clock Requirements.......................250 WWW, On-Line Support.......................................................7 Timer2 External Clock Requirements.......................251 DS70283K-page 324 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design • Development Systems Information Line resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQs), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. © 2007-2012 Microchip Technology Inc. DS70283K-page 325

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Literature Number: DS70283K Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70283K-page 326 © 2007-2012 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 32 MC2 02 T E / SP - XXX Examples: a) dsPIC33FJ32MC202TE/SP: Microchip Trademark Motor Control dsPIC33, 32 KB program memory, 28-pin, Extended temp., Architecture SPDIP package. Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture: 33 = 16-bit Digital Signal Controller Flash Memory Family: FJ = Flash program memory, 3.3V Product Group: MC2 = Motor Control family MC3 = Motor Control family Pin Count: 02 = 28-pin 04 = 44-pin Temperature Range: I = -40°C to+85°C (Industrial) E = -40°C to+125°C (Extended) H = -40°C to+150°C (High) Package: SP = Skinny Plastic Dual In-Line - 300 mil body (SPDIP) SO = Plastic Small Outline - Wide - 7.50 mil body (SOIC) SS = Plastic Shrink Small Outline - 5.3 mm body (SSOP) ML = Plastic Quad, No Lead Package - 8x8 mm body (QFN) PT = Plastic Thing Quad Flatpack - 10x10x1 mm body (TQFP) MM = Plastic Quad, No Lead Package - 6x6 mm body (QFN-S) © 2007-2012 Microchip Technology Inc. DS70283K-page 327

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 328 © 2007-2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT, devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC, intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-335-3 QUALITY MANAGEMENT  SYSTEM  Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV  Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping     devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2007-2012 Microchip Technology Inc. DS70283K-page 329

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