dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 16-Bit Digital Signal Controllers (up to 32-Kbyte Flash and 2-Kbyte SRAM) Operating Conditions Advanced Analog Features • 3.0V to 3.6V, -40°C to +125°C, DC to 16 MIPS • ADC module: • 3.0V to 3.6V, -40°C to +150°C, DC to 5 MIPS - 10-bit, 1.1 Msps with four S&H - Four analog inputs on 18-pin devices and up to 14 analog inputs on 44-pin devices Core: 16-Bit dsPIC33F CPU • Flexible and Independent ADC Trigger Sources • Code-Efficient (C and Assembly) Architecture • Three Comparator modules • Two 40-Bit Wide Accumulators • Charge Time Measurement Unit (CTMU): • Single-Cycle (MAC/MPY) with Dual Data Fetch - Supports mTouch™ capacitive touch sensing • Single-Cycle Mixed-Sign MUL plus Hardware Divide - Provides high-resolution time measurement (1 ns) - On-chip temperature measurement • 32-Bit Multiply Support Timers/Output Compare/Input Capture Clock Management • Up to Five General Purpose Timers: • ±0.25% Internal Oscillator - One 16-bit and up to two 32-bit timers/counters • Programmable PLLs and Oscillator Clock Sources • Two Output Compare modules • Fail-Safe Clock Monitor (FSCM) • Three Input Capture modules • Independent Watchdog Timer (WDT) • Peripheral Pin Select (PPS) to allow Function Remap • Fast Wake-up and Start-up Communication Interfaces Power Management • UART module (4 Mbps): - With support for LIN/J2602 Protocols and IrDA® • Low-Power Management modes (Sleep, Idle, Doze) • 4-Wire SPI module (8 MHz maximum speed): • Integrated Power-on Reset and Brown-out Reset - Remappable pins in 32-Kbyte Flash devices • 1 mA/MHz Dynamic Current (typical) • I2C™ module (400 kHz) • 30 µA IPD Current (typical) Input/Output PWM • Sink/Source 10 mA or 6 mA, Pin-Specific for Standard • Up to Three PWM Pairs VOH/VOL, up to 16 mA or 12 mA for Non-Standard VOH1 • Two Dead-Time Generators • 5V Tolerant Pins • 31.25 ns PWM Resolution • Up to 20 Selectable Open-Drain and Pull-ups • PWM Support for: • Three External Interrupts (two are remappable) - Inverters, PFC, UPS Qualification and Class B Support - BLDC, PMSM, ACIM, SRM • AEC-Q100 REV G (Grade 0 -40°C to +150°C) • Class B-Compliant Fault Inputs • Class B Safety Library, IEC 60730, UDE Certified • Possibility of ADC Synchronization with PWM Signal Debugger Development Support • In-Circuit and In-Application Programming • Up to Three Complex Data Breakpoints • Trace and Run-Time Watch  2011-2014 Microchip Technology Inc. DS70000652F-page 1

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed in Table1. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ16(GP/MC)101/102 DEVICE FEATURES Device Pins Program Flash (Kbyte) RAM (Kbytes) Remappable Pins R(1,2)16-bit TimeremaInput CaptureppabOutput Comparele PeUARTriph(3)external Interruptsrals SPI Motor Control PWM PWM Faults 10-Bit, 1.1 Msps ADC RTCC 2IC™ Comparators CTMU I/O Pins Packages E dsPIC33FJ16GP101 18 16 1 8 3 3 2 1 3 1 — — 1 ADC, Y 1 3 Y 13 PDIP, 4-ch SOIC 20 16 1 8 3 3 2 1 3 1 — — 1 ADC, Y 1 3 Y 15 SSOP 4-ch dsPIC33FJ16GP102 28 16 1 16 3 3 2 1 3 1 — — 1 ADC, Y 1 3 Y 21 SPDIP, 6-ch SOIC, SSOP, QFN 36 16 1 16 3 3 2 1 3 1 — — 1 ADC, Y 1 3 Y 21 VTLA 6-ch dsPIC33FJ16MC101 20 16 1 10 3 3 2 1 3 1 6-ch 1 1 ADC, Y 1 3 Y 15 PDIP, 4-ch SOIC, SSOP dsPIC33FJ16MC102 28 16 1 16 3 3 2 1 3 1 6-ch 2 1 ADC, Y 1 3 Y 21 SPDIP, 6-ch SOIC, SSOP, QFN 36 16 1 16 3 3 2 1 3 1 6-ch 2 1 ADC, Y 1 3 Y 21 VTLA 6-ch Note 1: Two out of three timers are remappable. 2: One pair can be combined to create one 32-bit timer. 3: Two out of three interrupts are remappable. DS70000652F-page 2  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 2: dsPIC33FJ32(GP/MC)101/102/104 DEVICE FEATURES Remappable Peripherals Device Pins Program Flash (Kbyte) RAM (Kbytes) Remappable Pins (1,2)16-bit Timer Input Capture Output Compare UART (3)xternal Interrupts SPI Motor Control PWM PWM Faults 10-Bit, 1.1 Msps ADC RTCC 2IC™ Comparators CTMU I/O Pins Packages E dsPIC33FJ32GP101 18 32 2 8 5 3 2 1 3 1 — — 1 ADC, Y 1 3 Y 13 PDIP, 6-ch SOIC 20 32 2 8 5 3 2 1 3 1 — — 1 ADC, Y 1 3 Y 15 SSOP 6-ch dsPIC33FJ32GP102 28 32 2 16 5 3 2 1 3 1 — — 1 ADC, Y 1 3 Y 21 SPDIP, 8-ch SOIC, SSOP, QFN 36 32 2 16 5 3 2 1 3 1 — — 1 ADC, Y 1 3 Y 21 VTLA 8-ch dsPIC33FJ32GP104 44 32 2 26 5 3 2 1 3 1 — — 1 ADC, Y 1 3 Y 35 TQFP, 14-ch QFN, VTLA dsPIC33FJ32MC101 20 32 2 10 5 3 2 1 3 1 6-ch 1 1 ADC, Y 1 3 Y 15 PDIP, 6-ch SOIC, SSOP dsPIC33FJ32MC102 28 32 2 16 5 3 2 1 3 1 6-ch 2 1 ADC, Y 1 3 Y 21 SPDIP, 8-ch SOIC, SSOP, QFN 36 32 2 16 5 3 2 1 3 1 6-ch 2 1 ADC, Y 1 3 Y 21 VTLA 8-ch dsPIC33FJ32MC104 44 32 2 26 5 3 2 1 3 1 6-ch 2 1 ADC, Y 1 3 Y 35 TQFP, 14-ch QFN, VTLA Note 1: Four out of five timers are remappable. 2: Two pairs can be combined to have up to two 32-bit timers. 3: Two out of three interrupts are remappable.  2011-2014 Microchip Technology Inc. DS70000652F-page 3

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams = Pins are up to 5V tolerant 18-Pin PDIP/SOIC MCLR 1 18 VDD PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 2 ds 17 VSS PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 3 P 16 RP15(1)/CN11/RB15 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 4 IC3 15 RTCC/RP14(1)/CN12/RB14 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 5 3F 14 VCAP J OSCI/CLKI/CN30/RA2 6 1 13 VSS OSCO/CLKO/CN29/RA3 7 6G 12 SDA1/SDI1/RP9(1)/CN21/RB9 PGED3/SOSCI/RP4(1)/CN1/RB4 8 P1 11 SCL1/SDO1/RP8(1)/CN22/RB8 PGEC3/SOSCO/T1CK/CN0/RA4 9 01 10 SCK1/INT0/RP7(1)/CN23/RB7 MCLR 1 18 VDD PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 2 ds 17 VSS PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 3 P 16 RP15(1)/CN11/RB15 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 4 IC3 15 RTCC/RP14(1)/CN12/RB14 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 5 3F 14 VCAP J OSCI/CLKI/CN30/RA2 6 3 13 VSS OSCO/CLKO/CN29/RA3 7 2G 12 SDA1/RP9(1)/CN21/RB9 PGED3/SOSCI/AN9/RP4(1)/CN1/RB4 8 P1 11 SCL1/RP8(1)/CN22/RB8 PGEC3/SOSCO/AN10/T1CK/CN0/RA4 9 01 10 INT0/RP7(1)/CN23/RB7 Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. DS70000652F-page 4  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 20-Pin SSOP = Pins are up to 5V tolerant MCLR 1 20 AVDD PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 2 d 19 AVSS PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 3 sP 18 RP15(1)/CN11/RB15 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 4 IC 17 RTCC/RP14(1)/CN12/RB14 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 5 33 16 VDD F VSS 6 J1 15 VCAP OSCI/CLKI/CN30/RA2 7 6 14 VSS G OSCO/CLKO/CN29/RA3 8 P 13 SDA1/SDI1/RP9(1)/CN21/RB9 PGED3/SOSCI/RP4(1)/CN1/RB4 9 10 12 SCL1/SDO1/RP8(1)/CN22/RB8 PGEC3/SOSCO/T1CK/CN0/RA4 10 1 11 SCK1/INT0/RP7(1)/CN23/RB7 MCLR 1 20 AVDD PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 2 d 19 AVSS PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 3 sP 18 RP15(1)/CN11/RB15 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 4 IC 17 RTCC/RP14(1)/CN12/RB14 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 5 33 16 VDD F VSS 6 J3 15 VCAP OSCI/CLKI/CN30/RA2 7 2 14 VSS G OSCO/CLKO/CN29/RA3 8 P 13 SDA1/RP9(1)/CN21/RB9 PGED3/SOSCI/AN9/RP4(1)/CN1/RB4 9 10 12 SCL1/RP8(1)/CN22/RB8 PGEC3/SOSCO/AN10/T1CK/CN0/RA4 10 1 11 INT0/RP7(1)/CN23/RB7 Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals.  2011-2014 Microchip Technology Inc. DS70000652F-page 5

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 28-Pin SPDIP/SOIC/SSOP = Pins are up to 5V tolerant MCLR 1 28 AVDD PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 2 27 AVSS PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 3 26 RP15(1)/CN11/RB15 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 4 d 25 RTCC/RP14(1)/CN12/RB14 s PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 5 P 24 RP13(1)/CN13/RB13 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 6 IC3 23 RP12(1)/CN14/RB12 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 7 3F 22 RP11(1)/CN15/RB11 VSS 8 J1 21 RP10(1)/CN16/RB10 6 OSCI/CLKI/CN30/RA2 9 G 20 VCAP OSCO/CLKO/CN29/RA3 10 P1 19 VSS PGED3/SOSCI/RP4(1)/CN1/RB4 11 02 18 SDA1/SDI1/RP9(1)/CN21/RB9 PGEC3/SOSCO/T1CK/CN0/RA4 12 17 SCL1/SDO1/RP8(1)/CN22/RB8 VDD 13 16 SCK1/INT0/RP7(1)/CN23/RB7 ASDA1/RP5(1)/CN27/RB5 14 15 ASCL1/RP6(1)/CN24/RB6 MCLR 1 28 AVDD PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 2 27 AVSS PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 3 26 RP15(1)/CN11/RB15 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 4 ds 25 RTCC/RP14(1)/CN12/RB14 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 5 P 24 RP13(1)/CN13/RB13 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 6 IC3 23 RP12(1)/CN14/RB12 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 7 3F 22 RP11(1)/CN15/RB11 VSS 8 J3 21 RP10(1)/CN16/RB10 2 OSCI/CLKI/CN30/RA2 9 G 20 VCAP OSCO/CLKO/CN29/RA3 10 P1 19 VSS PGED3/SOSCI/AN9/RP4(1)/CN1/RB4 11 02 18 SDA1/RP9(1)/CN21/RB9 PGEC3/SOSCO/AN10/T1CK/CN0/RA4 12 17 SCL1/RP8(1)/CN22/RB8 VDD 13 16 INT0/RP7(1)/CN23/RB7 ASDA1/RP5(1)/CN27/RB5 14 15 ASCL1/RP6(1)/CN24/RB6 Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. DS70000652F-page 6  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 20-Pin PDIP/SOIC/SSOP = Pins are up to 5V tolerant MCLR 1 20 VDD PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 2 d 19 VSS PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 3 sP 18 PWM1L1/RP15(1)/CN11/RB15 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 4 IC 17 PWM1H1/RTCC/RP14(1)/CN12/RB14 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 5 33 16 PWM1L2/RP13(1)/CN13/RB13 F VSS 6 J1 15 PWM1H2/RP12(1)/CN14/RB12 OSCI/CLKI/CN30/RA2 7 6M 14 VCAP OSCO/CLKO/CN29/RA3 8 C 13 SDA1/SDI1/PWM1L3/RP9(1)/CN21/RB9 PGED3/SOSCI/RP4(1)/CN1/RB4 9 10 12 SCL1/SDO1/PWM1H3/RP8(1)/CN22/RB8 PGEC3/SOSCO/T1CK/CN0/RA4 10 1 11 FLTA1(2)/SCK1/INT0/RP7(1)/CN23/RB7 MCLR 1 20 VDD PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 2 d 19 VSS PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 3 sP 18 PWM1L1/RP15(1)/CN11/RB15 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 4 IC 17 PWM1H1/RTCC/RP14(1)/CN12/RB14 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 5 33 16 PWM1L2/RP13(1)/CN13/RB13 F VSS 6 J3 15 PWM1H2/RP12(1)/CN14/RB12 OSCI/CLKI/CN30/RA2 7 2M 14 VCAP OSCO/CLKO/CN29/RA3 8 C 13 SDA1/PWM1L3/RP9(1)/CN21/RB9 PGED3/SOSCI/AN9/RP4(1)/CN1/RB4 9 10 12 SCL1/PWM1H3/RP8(1)/CN22/RB8 PGEC3/SOSCO/AN10/T1CK/CN0/RA4 10 1 11 FLTA1(2)/INT0/RP7(1)/CN23/RB7 Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section15.2 “PWM Faults” for more information on the PWM Faults.  2011-2014 Microchip Technology Inc. DS70000652F-page 7

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 28-Pin SPDIP/SOIC/SSOP = Pins are up to 5V tolerant MCLR 1 28 AVDD PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 2 27 AVSS PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 3 26 PWM1L1/RP15(1)/CN11/RB15 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 4 d 25 PWM1H1/RTCC/RP14(1)/CN12/RB14 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 5 sP 24 PWM1L2/RP13(1)/CN13/RB13 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 6 IC3 23 PWM1H2/RP12(1)/CN14/RB12 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 7 3F 22 PWM1L3/RP11(1)/CN15/RB11 VSS 8 J1 21 PWM1H3/RP10(1)/CN16/RB10 OSCI/CLKI/CN30/RA2 9 6M 20 VCAP OSCO/CLKO/CN29/RA3 10 C 19 VSS PGED3/SOSCI/RP4(1)/CN1/RB4 11 10 18 SDA1/SDI1/RP9(1)/CN21/RB9 2 PGEC3/SOSCO/T1CK/CN0/RA4 12 17 SCL1/SDO1/RP8(1)/CN22/RB8 VDD 13 16 SCK1/INT0/RP7(1)/CN23/RB7 FLTB1(2)/ASDA1/RP5(1)/CN27/RB5 14 15 FLTA1(2)/ASCL1/RP6(1)/CN24/RB6 MCLR 1 28 AVDD PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0 2 27 AVSS PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1 3 26 PWM1L1/RP15(1)/CN11/RB15 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 4 d 25 PWM1H1/RTCC/RP14(1)/CN12/RB14 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 5 sP 24 PWM1L2/RP13(1)/CN13/RB13 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 6 IC3 23 PWM1H2/RP12(1)/CN14/RB12 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 7 3F 22 PWM1L3/RP11(1)/CN15/RB11 VSS 8 J3 21 PWM1H3/RP10(1)/CN16/RB10 OSCI/CLKI/CN30/RA2 9 2M 20 VCAP OSCO/CLKO/CN29/RA3 10 C 19 VSS PGED3/SOSCI/AN9/RP4(1)/CN1/RB4 11 10 18 SDA1/RP9(1)/CN21/RB9 2 PGEC3/SOSCO/AN10/T1CK/CN0/RA4 12 17 SCL1/RP8(1)/CN22/RB8 VDD 13 16 INT0/RP7(1)/CN23/RB7 FLTB1(2)/ASDA1/RP5(1)/CN27/RB5 14 15 FLTA1(2)/ASCL1/RP6(1)/CN24/RB6 Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section15.2 “PWM Faults” for more information on the PWM Faults. DS70000652F-page 8  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 28-Pin QFN(2) = Pins are up to 5V tolerant 1 0 A A R R 3/ 2/ N N C C 2/ 1/ D D E E T T C C B/ A/ 4 1IN 1IN RB1 N1/C3INA/C N0/C3INB/C N11/RB15(1)14/CN12/ A A C P PGEC2/ PGED2/ MCLR AVDD AVSS (1)RP15/ RTCC/R 28 27 26 25 24 2322 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 1 21 RP13(1)/CN13/RB13 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 2 20 RP12(1)/CN14/RB12 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 3 19 RP11(1)/CN15/RB11 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 4 dsPIC33FJ16GP102 18 RP10(1)/CN16/RB10 VSS 5 17 VCAP OSCI/CLKI/CN30/RA2 6 16 VSS OSCO/CLKO/CN29/RA3 7 15 SDA1/SDI1/RP9(1)/CN21/RB9 8 9 10 11 12 13 14 4 4 D 5 6 7 8 B A D B B B B R R V R R R R 1/ 0/ 7/ 4/ 3/ 2/ N N 2 2 2 2 C C N N N N (1)CI/RP4/ CO/T1CK/ (1)1/RP5/C(1)1/RP6/C (1)0/RP7/C (1)1/RP8/C S S A L T O O O D C N D D3/S C3/S AS AS CK1/I L1/S GE GE S SC P P Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.  2011-2014 Microchip Technology Inc. DS70000652F-page 9

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 28-Pin QFN(2) = Pins are up to 5V tolerant 1 0 A A R R 3/ 2/ N N C C 2/ 1/ D D E E T T C C B/ A/ 4 1IN 1IN RB1 N1/C3INA/C N0/C3INB/C N11/RB15(1)14/CN12/ A A C P PGEC2/ PGED2/ MCLR AVDD AVSS (1)RP15/ RTCC/R 28 27 26 25 24 2322 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 1 21 RP13(1)/CN13/RB13 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 2 20 RP12(1)/CN14/RB12 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 3 19 RP11(1)/CN15/RB11 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 4 dsPIC33FJ32GP102 18 RP10(1)/CN16/RB10 VSS 5 17 VCAP OSCI/CLKI/CN30/RA2 6 16 VSS OSCO/CLKO/CN29/RA3 7 15 SDA1/RP9(1)/CN21/RB9 8 9 10 11 12 13 14 4 4 D 5 6 7 8 B A D B B B B R R V R R R R 1/ 0/ 7/ 4/ 3/ 2/ N N 2 2 2 2 C C N N N N (1)N9/RP4/ 10//T1CK/ (1)1/RP5/C(1)1/RP6/C (1)0/RP7/C (1)1/RP8/C CI/A OAN SDA SCL INT SCL S C A A O S S O D3/ 3/S E C G E P G P Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70000652F-page 10  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 28-Pin QFN(2) = Pins are up to 5V tolerant 1 0 A A R R 3/ 2/ N N C C 4 2/ 1/ B1 D D R CTE CTE 15 N12/ B/ A/ B C A/C1IN B/C1IN CN11/R(1)P14/ C3IN C3IN (1)15/ CC/R N1/ N0/ RP RT GEC2/A GED2/A CLR VDD VSS WM1L1/ WM1H1/ P P M A A P P 28 27 26 25 24 23 22 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 1 21 PWM1L2/RP13(1)/CN13/RB13 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 2 20 PWM1H2/RP12(1)/CN14/RB12 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 3 19 PWM1L3/RP11(1)/CN15/RB11 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 4 dsPIC33FJ16MC102 18 PWM1H3/RP10(1)/CN16/RB10 VSS 5 17 VCAP OSCI/CLKI/CN30/RA2 6 16 VSS OSCO/CLKO/CN29/RA3 7 15 SDA1/SDI1/RP9(1)/CN21/RB9 8 9 10 11 12 13 14 4 4 D 5 6 7 8 B A D B B B B R R V R R R R 1/ 0/ 7/ 4/ 3/ 2/ N N 2 2 2 2 C C N N N N (1)CI/RP4/ CO/T1CK/ (1)1/RP5/C(1)1/RP6/C (1)0/RP7/C (1)1/RP8/C S S A L T O O O D C N D GED3/S GEC3/S (3)B1/AS(3)A1/AS SCK1/I SCL1/S P P FLT FLT Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 3: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section15.2 “PWM Faults” for more information on the PWM Faults.  2011-2014 Microchip Technology Inc. DS70000652F-page 11

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 28-Pin QFN(2) = Pins are up to 5V tolerant 1 0 A A R R 3/ 2/ N N C C 4 2/ 1/ B1 D D R CTE CTE 15 N12/ B/ A/ B C A/C1IN B/C1IN CN11/R(1)P14/ C3IN C3IN (1)15/ CC/R N1/ N0/ RP RT GEC2/A GED2/A CLR VDD VSS WM1L1/ WM1H1/ P P M A A P P 28 27 26 25 24 23 22 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 1 21 PWM1L2/RP13(1)/CN13/RB13 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 2 20 PWM1H2/RP12(1)/CN14/RB12 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 3 19 PWM1L3/RP11(1)/CN15/RB11 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 4 dsPIC33FJ32MC102 18 PWM1H3/RP10(1)/CN16/RB10 VSS 5 17 VCAP OSCI/CLKI/CN30/RA2 6 16 VSS OSCO/CLKO/CN29/RA3 7 15 SDA1/RP9(1)/CN21/RB9 8 9 10 11 12 13 14 4 4 D 5 6 7 8 B A D B B B B R R V R R R R 1/ 0/ 7/ 4/ 3/ 2/ N N 2 2 2 2 C C N N N N (1)CI/AN9/RP4/ O/AN10/T1CK/ (1)SDA1/RP5/C(1)SCL1/RP6/C (1)INT0/RP7/C (1)SCL1/RP8/C S C A A GED3/SO EC3/SOS (3)FLTB1/(3)FLTA1/ P G P Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 3: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section15.2 “PWM Faults” for more information on the PWM Faults. DS70000652F-page 12  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 36-Pin VTLA(2) = Pins are up to 5V tolerant 1 0 A A R R 3/ 2/ N N C C 2/ 1/ D D E E T T C C B/ A/ 4 1IN 1IN RB1 N1/C3INA/C N0/C3INB/C N11/RB15 (1)14/CN12/ A A C P PGEC2/ PGED2/ N/C N/C MCLR AVDD AVSS (1)RP15/ RTCC/R 36 35 34 33 32 31 30 29 28 27 RP13(1)/CN13/RB13 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 1 26 RP12(1)/CN14/RB12 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 2 25 RP11(1)/CN15/RB11 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 3 24 RP10(1)/CN16/RB10 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 4 23 VDD dsPIC33FJ16GP102 VDD 5 22 VCAP VSS 6 21 VSS OSCI/CLKI/CN30/RA2 7 20 N/C OSCO/CLKO/CN29/RA3 8 19 SDA1/SDI1/RP9(1)/CN21/RB9 PGED3/SOSCI/RP4(1)/CN1/RB4 9 10 11 12 13 14 15 16 17 18 RA4 N/C Vss) VDD V)DD RB5 RB6 RB7 RB8 N0/ C ( C ( 27/ 24/ 23/ 22/ CK/C N/ N/ 1)/CN 1)/CN 1)/CN 1)/CN T1 (P5 (P6 (P7 (P8 O/ R R R R C 1/ 1/ 0/ 1/ S A L T O O D C N D 3/S AS AS K1/I 1/S C C L E S C G S P Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.  2011-2014 Microchip Technology Inc. DS70000652F-page 13

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 36-Pin VTLA(2) = Pins are up to 5V tolerant 1 0 A A R R 3/ 2/ N N C C 2/ 1/ D D E E T T C C B/ A/ 4 1IN 1IN RB1 N1/C3INA/C N0/C3INB/C N11/RB15 (1)14/CN12/ A A C P PGEC2/ PGED2/ N/C N/C MCLR AVDD AVSS (1)RP15/ RTCC/R 36 35 34 33 32 31 30 29 28 27 RP13(1)/CN13/RB13 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 1 26 RP12(1)/CN14/RB12 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 2 25 RP11(1)/CN15/RB11 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 3 24 RP10(1)/CN16/RB10 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 4 23 VDD dsPIC33FJ32GP102 VDD 5 22 VCAP VSS 6 21 VSS OSCI/CLKI/CN30/RA2 7 20 N/C OSCO/CLKO/CN29/RA3 8 19 SDA1/RP9(1)/CN21/RB9 PGED3/SOSCI/AN9/RP4(1)/CN1/RB4 9 10 11 12 13 14 15 16 17 18 RA4 N/C Vss) VDD V)DD RB5 RB6 RB7 RB8 N0/ C ( C ( 27/ 24/ 23/ 22/ CK/C N/ N/ 1)/CN 1)/CN 1)/CN 1)/CN T1 (P5 (P6 (P7 (P8 0/ R R R R O/AN1 SDA1/ SCL1/ INT0/ SCL1/ C A A S O S 3/ C E G P Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70000652F-page 14  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 36-Pin VTLA(2) = Pins are up to 5V tolerant 1 0 A A R R 3/ 2/ N N C C 4 2/ 1/ B1 D D R CTE CTE 15 N12/ C1INB/ C1INA/ N11/RB (1)14/C A/ B/ C P C3IN C3IN (1)15/ CC/R N1/ N0/ RP RT PGEC2/A PGED2/A N/C N/C MCLR AVDD AVSS PWM1L1/ PWM1H1/ 36 35 34 33 32 31 30 29 28 27 PWM1L2/RP13(1)/CN13/RB13 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 1 26 PWM1H2/RP12(1)/CN14/RB12 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 2 25 PWM1L3/RP11(1)/CN15/RB11 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 3 24 PWM1H3/RP10(1)/CN16/RB10 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 4 dsPIC33FJ16MC102 23 VDD VDD 5 22 VCAP VSS 6 21 VSS OSCI/CLKI/CN30/RA2 7 20 N/C OSCO/CLKO/CN29/RA3 8 19 SDA1/SDI1/RP9(1)/CN21/RB9 PGED3/SOSCI/RP4(1)/CN1/RB4 9 10 11 12 13 14 15 16 17 18 RA4 N/C Vss) VDD V)DD RB5 RB6 RB7 RB8 N0/ C ( C ( 27/ 24/ 23/ 22/ CK/C N/ N/ 1)/CN 1)/CN 1)/CN 1)/CN T1 (P5 (P6 (P7 (P8 O/ R R R R C 1/ 1/ 0/ 1/ S A L T O O D C N D GEC3/S (3)B1/AS (3)A1/AS SCK1/I SCL1/S P FLT FLT Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 3: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section15.2 “PWM Faults” for more information on the PWM Faults.  2011-2014 Microchip Technology Inc. DS70000652F-page 15

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 36-Pin VTLA(2) = Pins are up to 5V tolerant 1 0 A A R R 3/ 2/ N N C C 4 D2/ D1/ B1 E E R T T 2/ C C 5 1 C1INB/ C1INA/ 11/RB1 (1)4/CN PGEC2/AN1/C3INA/ PGED2/AN0/C3INB/ N/C N/C MCLR AVDD AVSS (1)PWM1L1/RP15/CN PWM1H1/RTCC/RP1 36 35 34 33 32 31 30 29 28 27 PWM1L2/RP13(1)/CN13/RB13 PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0 1 26 PWM1H2/RP12(1)/CN14/RB12 PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1 2 25 PWM1L3/RP11(1)/CN15/RB11 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 3 24 PWM1H3/RP10(1)/CN16/RB10 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 4 dsPIC33FJ32MC102 23 VDD VDD 5 22 VCAP VSS 6 21 VSS OSCI/CLKI/CN30/RA2 7 20 N/C OSCO/CLKO/CN29/RA3 8 19 SDA1/RP9(1)/CN21/RB9 PGED3/SOSCI/AN9/RP4(1)/CN1/RB4 9 10 11 12 13 14 15 16 17 18 RA4 N/C Vss) VDD V)DD RB5 RB6 RB7 RB8 N0/ C ( C ( 27/ 24/ 23/ 22/ CK/C N/ N/ 1)/CN 1)/CN 1)/CN 1)/CN T1 (P5 (P6 (P7 (P8 0/ R R R R O/AN1 SDA1/ SCL1/ INT0/ SCL1/ C A A EC3/SOS (3)FLTB1/ (3)FLTA1/ G P Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 3: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section15.2 “PWM Faults” for more information on the PWM Faults. DS70000652F-page 16  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 44-Pin TQFP = Pins are up to 5V tolerant 4 A R 0/ N C K/ C (1)SCL1/RP8/CN22/RB8 (1)INT0/RP7/CN23/RB7 (1)ASCL1/RP6/CN24/RB6 (1)ASDA1/RP5/CN27/RB5 VDD VSS (1)AN15/RP21/CN26/RC5 (1)AN12/RP20/CN25/RC4 (1)AN11/RP19/CN28/RC3 RA9 PGEC3/SOSCO/AN10/T1 44 43 42 41 40 39 38 37 36 35 34 SDA1/RP9(1)/CN21/RB9 1 33 PEGED3/SOSCI/AN9/RP4(1)/CN1/RB4 RP22(1)/CN18/RC6 2 32 RA8 RP23(1)/CN17/RC7 3 31 OSC2/CLK0/CN29/RA3 RP24(1)/CN20/RC8 4 30 OSC1/CLKI/CN30/RA2 RP25(1)/CN19/RC9 5 29 VSS VSS 6 dsPIC33FJ32GP104 28 VDD VCAP 7 27 AN8/RP18(1)/CN10/RC2 RP10/CN16/RB10 8 26 AN7/RP17(1)/CN9/RC1 RP11(1)/CN15/RB11 9 25 AN6/RP16(1)/CN8/RC0 RP12(1)/CN14/RB12 10 24 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 RP13(1)/CN13/RB13 11 23 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 12 13 14 15 16 17 18 19 20 21 22 0 7 4 5 S D R 0 1 0 1 RA1 RA 2/RB1 1/RB1 AVS AVD MCL N2/RA N3/RA N4/RB N5/RB (1)RTCC/RP14/CN1 (1)RP15/CN1 PGED2/AN0/C3INB/C1INA/CTED1/C PGEC2/AN1/C3INA/C1INB/CTED2/C (1)PGED1/AN2/C2INA/C1INC/RP0/C (1)/CV/C2INB/C1IND/RP1/CFINREFOUT E R V C 3/ N A 1/ C E G P Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals.  2011-2014 Microchip Technology Inc. DS70000652F-page 17

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 44-Pin TQFP = Pins are up to 5V tolerant 4 A R N24/RB6 N27/RB5 CK/CN0/ (1)SCL1/RP8/CN22/RB8 (1)INT0/RP7/CN23/RB7 (2)(1)FLTA1/ASCL1/RP6/C (2)(1)FLTB1/ASDA1/RP5/C VDD VSS (1)AN15/RP21/CN26/RC5 (1)AN12/RP20/CN25/RC4 (1)AN11/RP19/CN28/RC3 RA9 PGEC3/SOSCO/AN10/T1 44 43 42 41 40 39 38 37 36 35 34 SDA1/RP9(1)/CN21/RB9 1 33 PEGED3/SOSCI/AN9/RP4(1)/CN1/RB4 RP22(1)/CN18/RC6 2 32 RA8 RP23(1)/CN17/RC7 3 31 OSC2/CLK0/CN29/RA3 RP24(1)/CN20/RC8 4 30 OSC1/CLKI/CN30/RA2 RP25(1)/CN19/RC9 5 29 VSS VSS 6 dsPIC33FJ32MC104 28 VDD VCAP 7 27 AN8/RP18(1)/CN10/RC2 PWM1H3/RP10(1)/CN16/RB10 8 26 AN7/RP17(1)/CN9/RC1 PWM1L3/RP11(1)/CN15/RB11 9 25 AN6/RP16(1)/CN8/RC0 PWM1H2/RP12(1)/CN14/RB12 10 24 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 PWM1L2/RP13(1)/CN13/RB13 11 23 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 12 13 14 15 16 17 18 19 20 21 22 0 7 4 5 S D R 0 1 0 1 RA1 RA 2/RB1 1/RB1 AVS AVD MCL N2/RA N3/RA N4/RB N5/RB (1)PWM1H1/RTCC/RP14/CN1 (1)PWM1L1/RP15/CN1 PGED2/AN0/C3INB/C1INA/CTED1/C PGEC2/AN1/C3INA/C1INB/CTED2/C (1)PGED1/AN2/C2INA/C1INC/RP0/C (1)/CV/C2INB/C1IND/RP1/CFINREFOUT E R V C 3/ N A 1/ C E G P Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section15.2 “PWM Faults” for more information on the PWM Faults. DS70000652F-page 18  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 44-Pin QFN(2) = Pins are up to 5V tolerant 4 A R 0/ N C K/ C (1)SCL1/RP8/CN22/RB8 (1)INT0/RP7/CN23/RB7 (1)ASCL1/RP6/CN24/RB6 (1)ASDA1/RP5/CN27/RB5 VDD VSS (1)AN15/RP21/CN26/RC5 (1)AN12/RP20/CN25/RC4 (1)AN11/RP19/CN28/RC3 RA9 PGEC3/SOSCO/AN10/T1 44 43 42 41 40 39 38 37 36 35 34 SDA1/RP9(1)/CN21/RB9 1 33 PGED3/SOSCI/AN9/RP4(1)/CN1/RB4 RP22(1)/CN18/RC6 2 32 RA8 RP23(1)/CN17/RC7 3 31 OSC2/CLKO/CN29/RA3 RP24(1)/CN20/RC8 4 30 OSC1/CLKI/CN30/RA2 RP25(1)/CN19/RC9 5 29 VSS VSS 6 dsPIC33FJ32GP104 28 VDD VCAP 7 27 AN8/RP18(1)/CN10/RC2 RP10(1)/CN16/RB10 8 26 AN7/RP17(1)/CN9/RC1 RP11(1)/CN15/RB11 9 25 AN6/RP16(1)/CN8/RC0 RP12(1)/CN14/RB12 10 24 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 RP13(1)/CN13/RB13 11 23 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 12 13 14 15 16 17 18 19 20 21 22 0 7 4 5 S D R 0 1 0 1 RA1 RA 2/RB1 1/RB1 AVS AVD MCL N2/RA N3/RA N4/RB N5/RB (1)RTCC/RP14/CN1 (1)RP15/CN1 PGED2/AN0/C3INB/C1INA/CTED1/C PGEC2/AN1/C3INA/C1INB/CTED2/C (1)PGED1/AN2/C2INA/C1INC/RP0/C (1)/CV/C2INB/C1IND/RP1/CFINREFOUT E R V C 3/ N A 1/ C E G P Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.  2011-2014 Microchip Technology Inc. DS70000652F-page 19

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 44-Pin QFN(2) = Pins are up to 5V tolerant 4 A R N24/RB6 N27/RB5 CK/CN0/ (1)SCL1/RP8/CN22/RB8 (1)INT0/RP7/CN23/RB7 (3)(1)FLTA1/ASCL1/RP6/C (3)(1)FLTB1/ASDA1/RP5/C VDD VSS (1)AN15/RP21/CN26/RC5 (1)AN12/RP20/CN25/RC4 (1)AN11/RP19/CN28/RC3 RA9 PGEC3/SOSCO/AN10/T1 44 43 42 41 40 39 38 37 36 35 34 SDA1/RP9(1)/CN21/RB9 1 33 PGED3/SOSCI/AN9/RP4(1)/CN1/RB4 RP22(1)/CN18/RC6 2 32 RA8 RP23(1)/CN17/RC7 3 31 OSC2/CLKO/CN29/RA3 RP24(1)/CN20/RC8 4 30 OSC1/CLKI/CN30/RA2 RP25(1)/CN19/RC9 5 29 VSS VSS 6 dsPIC33FJ32MC104 28 VDD VCAP 7 27 AN8/RP18(1)/CN10/RC2 PWM1H3/RP10(1)/CN16/RB10 8 26 AN7/RP17(1)/CN9/RC1 PWM1L3/RP11(1)/CN15/RB11 9 25 AN6/RP16(1)/CN8/RC0 PWM1H2/RP12(1)/CN14/RB12 10 24 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 PWM1L2/RP13(1)/CN13/RB13 11 23 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 12 13 14 15 16 17 18 19 20 21 22 0 7 4 5 S D R 0 1 0 1 RA1 RA 2/RB1 1/RB1 AVS AVD MCL N2/RA N3/RA N4/RB N5/RB (1)PWM1H1/RTCC/RP14/CN1 (1)PWM1L1/RP15/CN1 PGED2/AN0/C3INB/C1INA/CTED1/C PGEC2/AN1/C3INA/C1INB/CTED2/C (1)PGED1/AN2/C2INA/C1INC/RP0/C (1)/CV/C2INB/C1IND/RP1/CFINREFOUT E R V C 3/ N A 1/ C E G P Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 3: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section15.2 “PWM Faults” for more information on the PWM Faults. DS70000652F-page 20  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 44-Pin TLA(2) = Pins are up to 5V tolerant 4 A R 0/ N C K/ C (1)SCL1/RP8/CN22/RB8 (1)INT0/RP7/CN23/RB7 (1)ASCL1/RP6/CN24/RB6 (1)ASDA1/RP5/CN27/RB5 VDD VSS (1)AN15/RP21/CN26/RC5 (1)AN12/RP20/CN25/RC4 (1)AN11/RP19/CN28/RC3 RA9 PGEC3/SOSCO/AN10/T1 44 43 42 41 40 39 38 37 36 35 34 33 PGED3/SOSCI/AN9/RP4(1)/CN1/RB4 SDA1/RP9(1)/CN21/RB9 1 32 RA8 RP22(1)/CN18/RC6 2 31 OSC2/CLKO/CN29/RA3 RP23(1)/CN17/RC7 3 30 OSC1/CLKI/CN30/RA2 RP24(1)/CN20/RC8 4 29 VSS RP25(1)/CN19/RC9 5 dsPIC33FJ32GP104 28 VDD VSS 6 27 AN8/RP18(1)/CN10/RC2 VCAP 7 26 AN7/RP17(1)/CN9/RC1 RP10(1)/CN16/RB10 8 25 AN6/RP16(1)/CN8/RC0 RP11(1)/CN15/RB11 9 24 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 RP12(1)/CN14/RB12 10 23 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 RP13(1)/CN13/RB13 11 12 13 14 15 16 17 18 19 20 21 22 0 7 4 5 S D R 0 1 0 1 RA1 RA 2/RB1 1/RB1 AVS AVD MCL N2/RA N3/RA N4/RB N5/RB (1)RTCC/RP14/CN1 (1)RP15/CN1 PGED2/AN0/C3INB/C1INA/CTED1/C PGEC2/AN1/C3INA/C1INB/CTED2/C (1)PGED1/AN2/C2INA/C1INC/RP0/C (1)/CV/C2INB/C1IND/RP1/CFINREFOUT E R V C 3/ N A 1/ C E G P Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.  2011-2014 Microchip Technology Inc. DS70000652F-page 21

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Pin Diagrams (Continued) 44-Pin TLA(2) = Pins are up to 5V tolerant 4 A R N24/RB6 N27/RB5 CK/CN0/ (1)SCL1/RP8/CN22/RB8 (1)INT0/RP7/CN23/RB7 (3)(1)FLTA1/ASCL1/RP6/C (3)(1)FLTB1/ASDA1/RP5/C VDD VSS (1)AN15/RP21/CN26/RC5 (1)AN12/RP20/CN25/RC4 (1)AN11/RP19/CN28/RC3 RA9 PGEC3/SOSCO/AN10/T1 44 43 42 41 40 39 38 37 36 35 34 33 PGED3/SOSCI/AN9/RP4(1)/CN1/RB4 SDA1/RP9(1)/CN21/RB9 1 32 RA8 RP22(1)/CN18/RC6 2 31 OSC2/CLKO/CN29/RA3 RP23(1)/CN17/RC7 3 30 OSC1/CLKI/CN30/RA2 RP24(1)/CN20/RC8 4 29 VSS RP25(1)/CN19/RC9 5 dsPIC33FJ32MC104 28 VDD VSS 6 27 AN8/RP18(1)/CN10/RC2 VCAP 7 26 AN7/RP17(1)/CN9/RC1 PWM1H3/RP10(1)/CN16/RB10 8 25 AN6/RP16(1)/CN8/RC0 PWM1L3/RP11(1)/CN15/RB11 9 24 AN5/C3IND/C2IND/RP3(1)/CN7/RB3 PWM1H2/RP12(1)/CN14/RB12 10 23 AN4/C3INC/C2INC/RP2(1)/CN6/RB2 PWM1L2/RP13(1)/CN13/RB13 11 12 13 14 15 16 17 18 19 20 21 22 0 7 4 5 S D R 0 1 0 1 RA1 RA 2/RB1 1/RB1 AVS AVD MCL N2/RA N3/RA N4/RB N5/RB (1)PWM1H1/RTCC/RP14/CN1 (1)PWM1L1/RP15/CN1 PGED2/AN0/C3INB/C1INA/CTED1/C PGEC2/AN1/C3INA/C1INB/CTED2/C (1)PGED1/AN2/C2INA/C1INC/RP0/C (1)/CV/C2INB/C1IND/RP1/CFINREFOUT E R V C 3/ N A 1/ C E G P Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 3: The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section15.2 “PWM Faults” for more information on the PWM Faults. DS70000652F-page 22  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Table of Contents 1.0 Device Overview........................................................................................................................................................................27 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers..........................................................................................33 3.0 CPU............................................................................................................................................................................................37 4.0 Memory Organization.................................................................................................................................................................49 5.0 Flash Program Memory..............................................................................................................................................................83 6.0 Resets .......................................................................................................................................................................................87 7.0 Interrupt Controller.....................................................................................................................................................................95 8.0 Oscillator Configuration............................................................................................................................................................125 9.0 Power-Saving Features............................................................................................................................................................133 10.0 I/O Ports...................................................................................................................................................................................139 11.0 Timer1......................................................................................................................................................................................165 12.0 Timer2/3 and Timer4/5.............................................................................................................................................................167 13.0 Input Capture............................................................................................................................................................................175 14.0 Output Compare.......................................................................................................................................................................177 15.0 Motor Control PWM Module.....................................................................................................................................................181 16.0 Serial Peripheral Interface (SPI)...............................................................................................................................................197 17.0 Inter-Integrated Circuit™ (I2C™)..............................................................................................................................................203 18.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................211 19.0 10-Bit Analog-to-Digital Converter (ADC).................................................................................................................................217 20.0 Comparator Module..................................................................................................................................................................231 21.0 Real-Time Clock and Calendar (RTCC) ..................................................................................................................................243 22.0 Charge Time Measurement Unit (CTMU) ...............................................................................................................................255 23.0 Special Features......................................................................................................................................................................261 24.0 Instruction Set Summary..........................................................................................................................................................269 25.0 Development Support...............................................................................................................................................................277 26.0 Electrical Characteristics..........................................................................................................................................................281 27.0 High-Temperature Electrical Characteristics............................................................................................................................339 28.0 Packaging Information..............................................................................................................................................................343 Appendix A: Revision History.............................................................................................................................................................373 Index................................................................................................................................................................................................. 381 The Microchip Web Site.....................................................................................................................................................................387 Customer Change Notification Service..............................................................................................................................................387 Customer Support..............................................................................................................................................................................387 Product Identification System............................................................................................................................................................389  2011-2014 Microchip Technology Inc. DS70000652F-page 23

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70000652F-page 24  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33/PIC24 Family Ref- erence Manual”. These documents should be considered as the primary reference for the operation of a particular module or device feature. Note1: To access the documents listed below, browse to the documentation section of the dsPIC33FJ16MC102 product page of the Microchip Web site (www.microchip.com). In addition to parameters, features and other documentation, the resulting page provides links to the related family reference manual sections. • “CPU” (DS70204) • “Data Memory” (DS70202) • “Program Memory” (DS70203) • “Flash Programming” (DS70191) • “Reset” (DS70192) • “Watchdog Timer and Power-Saving Modes” (DS70196) • “Timers” (DS70205) • “Input Capture” (DS70198) • “Output Compare” (DS70209) • “Motor Control PWM” (DS70187) • “Analog-to-Digital Converter (ADC)” (DS70183) • “UART” (DS70188) • “Serial Peripheral Interface (SPI)” (DS70206) • “Inter-Integrated Circuit™ (I2C™)” (DS70195) • “CodeGuard Security” (DS70199) • “Programming and Diagnostics” (DS70207) • “Device Configuration” (DS70194) • “I/O Ports with Peripheral Pin Select (PPS)” (DS70190) • “Real-Time Clock and Calendar (RTCC)” (DS70301) • “Introduction (Part VI)” (DS70655) • “Oscillator (Part VI)” (DS70644) • “Interrupts (Part VI)” (DS70633) • “Comparator with Blanking” (DS70647) • “Charge Time Measurement Unit (CTMU)” (DS70635)  2011-2014 Microchip Technology Inc. DS70000652F-page 25

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70000652F-page 26  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 1.0 DEVICE OVERVIEW This data sheet contains device-specific information for dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/ Note: This data sheet summarizes the features MC)101/102/104 Digital Signal Controller (DSC) of the dsPIC33FJ16(GP/MC)101/102 devices. These devices contain extensive Digital Signal and dsPIC33FJ32(GP/MC)101/102/104 Processor (DSP) functionality with a high-performance, devices. However, it is not intended to be 16-bit microcontroller (MCU) architecture. a comprehensive reference source. To Figure1-1 shows a general block diagram of the core complement the information in this data and peripheral modules in the dsPIC33FJ16(GP/ sheet, refer to the latest family reference MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 sections of the “dsPIC33/PIC24 Family family of devices. Table1-1 lists the functions of the Reference Manual”, which are available various pins shown in the pinout diagrams. from the Microchip web site (www.microchip.com).  2011-2014 Microchip Technology Inc. DS70000652F-page 27

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 1-1: dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus Interrupt X Data Bus PORTA Controller 16 16 8 16 16 Data Latch Data Latch 23 23 PCU PCH PCL X RAM Y RAM PORTB Program Counter Stack Loop Address Address Control Control Latch Latch Logic Logic 16 23 16 16 Remappable Address Generator Units Pins Address Latch Program Memory EA MUX Data Latch ROM Latch 24 16 16 a Instruction Dat Decode and al Control Instruction Reg er Lit 16 Control Signals to Various Blocks DSP Engine 16 x 16 OSC2/CLKO Timing Power-up W Register Array OSC1/CLKI Generation Timer Divide Support 16 Oscillator FRC/LPRC Start-up Timer Oscillators Power-on Reset 16-Bit ALU Precision Band Gap Watchdog Reference Timer 16 Brown-out Voltage Reset Regulator VCAP VDD, VSS MCLR External Timers OC/ CTMU Interrupts 1-5 UART1 ADC1 PWM1-2 RTCC 1-3 Comparators PWM SPI1 IC1-IC3 CNx I2C1 1-3 6-ch Note: Not all pins or features are implemented on all device pinout configurations. See the “Pin Diagrams” section for the specific pins and features present on each device. DS70000652F-page 28  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name PPS Description Type Type AN0-AN12, I Analog No Analog input channels. AN15(5) CLKI I ST/CMOS No External clock source input. Always associated with OSC1 pin function. CLKO O — No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. OSC1 I ST/CMOS No Oscillator crystal input. ST buffer when configured in RC mode; CMOS — otherwise. OSC2 I/O No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. SOSCI I ST/CMOS No 32.768 kHz low-power oscillator crystal input; CMOS otherwise. SOSCO O — No 32.768 kHz low-power oscillator crystal output. CN0-CN30(5) I ST No Change Notification inputs. Can be software programmable for internal weak pull-ups on all inputs. IC1-IC3 I ST Yes Capture Inputs 1/2/3. OCFA I ST Yes Compare Fault A input (for Compare Channels 1 and 2). OC1-OC2 O — Yes Compare Outputs 1/2. INT0 I ST No External Interrupt 0. INT1 I ST Yes External Interrupt 1. INT2 I ST Yes External Interrupt 2. RA0-RA4, I/O ST No PORTA is a bidirectional I/O port. RA7-RA10(5) RB0-RB15(5) I/O ST No PORTB is a bidirectional I/O port. RC0-RC9(5) I/O ST No PORTC is a bidirectional I/O port. T1CK I ST No Timer1 external clock input. T2CK I ST Yes Timer2 external clock input. T3CK I ST Yes Timer3 external clock input. T4CK(6) I ST Yes Timer4 external clock input. T5CK(6) I ST Yes Timer5 external clock input. U1CTS I ST Yes UART1 Clear-to-Send. U1RTS O — Yes UART1 Ready-to-Send. U1RX I ST Yes UART1 receive. U1TX O — Yes UART1 transmit. SCK1 I/O ST Yes Synchronous serial clock input/output for SPI1. SDI1 I ST Yes SPI1 data in. SDO1 O — Yes SPI1 data out. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select Note 1: An external pull-down resistor is required for the FLTA1 pin in dsPIC33FJXXMC101 (20-pin) devices. 2: The FLTA1 pin and the PWM1Lx/PWM1Hx pins are available in dsPIC(16/32)MC10X devices only. 3: The FLTB1 pin is available in dsPIC(16/32)MC102/104 devices only. 4: The PWM Fault pins are enabled during any Reset event. Refer to Section15.2 “PWM Faults” for more information on the PWM Faults. 5: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for availability. 6: These pins are available in dsPIC33FJ32(GP/MC)104 (44-pin) devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 29

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name PPS Description Type Type SCL1 I/O ST No Synchronous serial clock input/output for I2C1. SDA1 I/O ST No Synchronous serial data input/output for I2C1. ASCL1 I/O ST No Alternate synchronous serial clock input/output for I2C1. ASDA1 I/O ST No Alternate synchronous serial data input/output for I2C1. FLTA1(1,2,4) I ST No PWM1 Fault A input. FLTB1(3,4) I ST No PWM1 Fault B input. PWM1L1 O — No PWM1 Low Output 1. PWM1H1 O — No PWM1 High Output 1. PWM1L2 O — No PWM1 Low Output 2. PWM1H2 O — No PWM1 High Output 2. PWM1L3 O — No PWM1 Low Output 3. PWM1H3 O — No PWM1 High Output 3. RTCC O Digital No RTCC Alarm output. CTPLS O Digital Yes CTMU pulse output. CTED1 I Digital No CTMU External Edge Input 1. CTED2 I Digital No CTMU External Edge Input 2. CVREFIN I Analog No Comparator Voltage Positive Reference Input. CVREFOUT O Analog No Comparator Voltage Positive Reference Output. C1INA I Analog No Comparator 1 Positive Input A. C1INB I Analog No Comparator 1 Negative Input B. C1INC I Analog No Comparator 1 Negative Input C. C1IND I Analog No Comparator 1 Negative Input D. C1OUT O Digital Yes Comparator 1 Output. C2INA I Analog No Comparator 2 Positive Input A. C2INB I Analog No Comparator 2 Negative Input B. C2INC I Analog No Comparator 2 Negative Input C. C2IND I Analog No Comparator 2 Negative Input D. C2OUT O Digital Yes Comparator 2 Output. C3INA I Analog No Comparator 3 Positive Input A. C3INB I Analog No Comparator 3 Negative Input B. C3INC I Analog No Comparator 3 Negative Input C. C3IND I Analog No Comparator 3 Negative Input D. C3OUT O Digital Yes Comparator 3 Output. PGED1 I/O ST No Data I/O pin for Programming/Debugging Communication Channel 1. PGEC1 I ST No Clock input pin for Programming/Debugging Communication Channel 1. PGED2 I/O ST No Data I/O pin for Programming/Debugging Communication Channel 2. PGEC2 I ST No Clock input pin for Programming/Debugging Communication Channel 2. PGED3 I/O ST No Data I/O pin for Programming/Debugging Communication Channel 3. PGEC3 I ST No Clock input pin for Programming/Debugging Communication Channel 3. MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select Note 1: An external pull-down resistor is required for the FLTA1 pin in dsPIC33FJXXMC101 (20-pin) devices. 2: The FLTA1 pin and the PWM1Lx/PWM1Hx pins are available in dsPIC(16/32)MC10X devices only. 3: The FLTB1 pin is available in dsPIC(16/32)MC102/104 devices only. 4: The PWM Fault pins are enabled during any Reset event. Refer to Section15.2 “PWM Faults” for more information on the PWM Faults. 5: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for availability. 6: These pins are available in dsPIC33FJ32(GP/MC)104 (44-pin) devices only. DS70000652F-page 30  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name PPS Description Type Type AVDD P P No Positive supply for analog modules. This pin must be connected at all times. AVDD is connected to VDD in the 18-pin dsPIC33FJXXGP101 and 20-pin dsPIC33FJXXMC101 devices. In all other devices, AVDD is separated from VDD. AVSS P P No Ground reference for analog modules. AVSS is connected to VSS in the 18-pin dsPIC33FJXXGP101 and 20-pin dsPIC33FJXXMC101 devices. In all other devices, AVSS is separated from VSS. VDD P — No Positive supply for peripheral logic and I/O pins. VCAP P — No CPU logic filter capacitor connection. VSS P — No Ground reference for logic and I/O pins. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select Note 1: An external pull-down resistor is required for the FLTA1 pin in dsPIC33FJXXMC101 (20-pin) devices. 2: The FLTA1 pin and the PWM1Lx/PWM1Hx pins are available in dsPIC(16/32)MC10X devices only. 3: The FLTB1 pin is available in dsPIC(16/32)MC102/104 devices only. 4: The PWM Fault pins are enabled during any Reset event. Refer to Section15.2 “PWM Faults” for more information on the PWM Faults. 5: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for availability. 6: These pins are available in dsPIC33FJ32(GP/MC)104 (44-pin) devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 31

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70000652F-page 32  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors STARTED WITH 16-BIT The use of decoupling capacitors on every pair of DIGITAL SIGNAL power supply pins, such as VDD, VSS, AVDD and CONTROLLERS AVSS, is required. Consider the following criteria when using decoupling Note1: This data sheet summarizes the features capacitors: of the dsPIC33FJ16(GP/MC)101/102 • Value and type of capacitor: Recommendation and dsPIC33FJ32(GP/MC)101/102/104 of 0.1 µF (100 nF), 10V-20V. This capacitor family devices. It is not intended to be a should be a low-ESR and have resonance comprehensive reference source. To com- frequency in the range of 20MHz and higher. It is plement the information in this data sheet, recommended that ceramic capacitors be used. refer to the “dsPIC33/PIC24 Family Reference Manual”. Please see the • Placement on the printed circuit board: The Microchip web site (www.microchip.com) decoupling capacitors should be placed as close for the latest “dsPIC33/PIC24 Family to the pins as possible. It is recommended to Reference Manual” sections. place the capacitors on the same side of the board as the device. If space is constricted, the 2: Some registers and associated bits capacitor can be placed on another layer on the described in this section may not be PCB using a via; however, ensure that the trace available on all devices. Refer to length from the pin to the capacitor is within Section4.0 “Memory Organization” in one-quarter inch (6mm) in length. this data sheet for device-specific register • Handling high-frequency noise: If the board is and bit information. experiencing high-frequency noise, upward of tens of MHz, add a second ceramic-type capacitor 2.1 Basic Connection Requirements in parallel to the above described decoupling capacitor. The value of the second capacitor can Getting started with the dsPIC33FJ16(GP/MC)101/102 be in the range of 0.01µF to 0.001µF. Place this and dsPIC33FJ32(GP/MC)101/102/104 family of 16-bit second capacitor next to the primary decoupling Digital Signal Controllers (DSCs) requires attention to a capacitor. In high-speed circuit designs, consider minimal set of device pin connections before implementing a decade pair of capacitances as proceeding with development. The following is a list of close to the power and ground pins as possible. pin names, which must always be connected: For example, 0.1 µF in parallel with 0.001 µF. • All VDD and VSS pins • Maximizing performance: On the board layout (see Section2.2 “Decoupling Capacitors”) from the power supply circuit, run the power and • All AVDD and AVSS pins, if present on the device return traces to the decoupling capacitors first, (regardless if ADC module is not used) and then to the device pins. This ensures that the (see Section2.2 “Decoupling Capacitors”) decoupling capacitors are first in the power chain. • VCAP Equally important is to keep the trace length (see Section2.3 “CPU Logic Filter Capacitor between the capacitor and the power pins to a Connection (VCAP)”) minimum thereby reducing PCB track inductance. • MCLR pin (see Section2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section2.6 “External Oscillator Pins”)  2011-2014 Microchip Technology Inc. DS70000652F-page 33

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 2-1: RECOMMENDED The placement of this capacitor should be close to the MINIMUM CONNECTION VCAP. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section23.2 0.1 µF “On-Chip Voltage Regulator” for details. VDD Ta1n0t aµluFm Ceramic 2.4 Master Clear (MCLR) Pin R AP DD SS C V V The MCLR pin provides two specific device R1 V functions: MCLR • Device Reset C • Device programming and debugging dsPIC33F During device programming and debugging, the VSS VDD resistance and capacitance that can be added to the pin must be considered. Device programmers and 0.1 µF VDD D S VSS 0.1 µF debuggers drive the MCLR pin. Consequently, Ceramic VD VS DD SS Ceramic specific voltage levels (VIH and VIL) and fast signal A A V V transitions must not be adversely affected. Therefore, 0.1 µF 0.1 µF specific values of R and C will need to be adjusted Ceramic Ceramic based on the application and PCB requirements. L1(1) For example, as shown in Figure2-2, it is recommended that the capacitor C, be isolated from Note 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and the MCLR pin during programming and debugging AVDD to improve ADC noise rejection. The inductor operations. impedance should be less than 1 and the inductor capacity greater than 10 mA. Place the components shown in Figure2-2 within one-quarter inch (6mm) from the MCLR pin. Where: FCNV f = -------------- (i.e., ADC conversion rate/2) FIGURE 2-2: EXAMPLE OF MCLR PIN 2 CONNECTIONS 1 f = ----------------------- 2 LC VDD L = ----------1------------2 2f C R(1) R1(2) MCLR 2.2.1 TANK CAPACITORS JP dsPIC33F On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor C for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that con- Note 1: R 10k is recommended. A suggested nects the power supply source to the device and the starting value is 10k. Ensure that the maximum current drawn by the device in the applica- MCLR pin VIH and VIL specifications are met. tion. In other words, select the tank capacitor so that it 2: R1 470 will limit any current flowing into meets the acceptable voltage sag at the device. Typical MCLR from the external capacitor, C, in the values range from 4.7µF to 47µF. event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical 2.3 CPU Logic Filter Capacitor Overstress (EOS). Ensure that the MCLR Connection (VCAP) pin VIH and VIL specifications are met. A low-ESR (< 5 Ohms) capacitor is required on the VCAP pin, which is used to stabilize the voltage regulator output voltage. The VCAP pin must not be connected to VDD, and must have a capacitor between 4.7µF and 10 µF, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section26.0 “Electrical Characteristics” for additional information. DS70000652F-page 34  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 2.5 ICSP Pins 2.6 External Oscillator Pins The PGECx and PGEDx pins are used for In-Circuit Many DSCs have options for at least two oscillators: a Serial Programming™ (ICSP™) and debugging pur- high-frequency primary oscillator and a low-frequency poses. It is recommended to keep the trace length secondary oscillator (refer to Section8.0 “Oscillator between the ICSP connector and the ICSP pins on the Configuration” for details). device as short as possible. If the ICSP connector is The oscillator circuit should be placed on the same expected to experience an ESD event, a series resistor side of the board as the device. Also, place the is recommended, with the value in the range of a few oscillator circuit close to the respective oscillator pins, tens of Ohms, not to exceed 100 Ohms. not exceeding one-half inch (12mm) distance Pull-up resistors, series diodes, and capacitors on the between them. The load capacitors should be placed PGECx and PGEDx pins are not recommended as they next to the oscillator itself, on the same side of the will interfere with the programmer/debugger communi- board. Use a grounded copper pour around the cations to the device. If such discrete components are oscillator circuit to isolate them from surrounding an application requirement, they should be removed circuits. The grounded copper pour should be routed from the circuit during programming and debugging. directly to the MCU ground. Do not run any signal Alternately, refer to the AC/DC characteristics and traces or power traces inside the ground pour. Also, if timing requirements information in the “dsPIC33F using a two-sided board, avoid any traces on the Flash Programming Specification for Devices with Vol- other side of the board where the crystal is placed. A atile Configuration Bits” (DS70659) for information on suggested layout is shown in Figure2-3. capacitive loading limits and pin Voltage Input High (VIH) and Voltage Input Low (VIL) requirements. FIGURE 2-3: SUGGESTED PLACEMENT Ensure that the “Communication Channel Select” (i.e., OF THE OSCILLATOR PGECx/PGEDx pins) programmed into the device CIRCUIT matches the physical connections for the ICSP to MPLAB® ICD 3 or MPLAB REAL ICE™. Main Oscillator For more information on ICD 3 and REAL ICE 13 connection requirements, refer to the following Guard Ring 14 documents that are available on the Microchip web site. 15 Guard Trace • “Using MPLAB® ICD 3” (poster) (DS51765) 16 • “MPLAB® ICD 3 Design Advisory” (DS51764) Secondary 17 • “MPLAB® REAL ICE™ In-Circuit Debugger Oscillator 18 User’s Guide” (DS51616) 19 • “Using MPLAB® REAL ICE™” (poster) (DS51749) 20  2011-2014 Microchip Technology Inc. DS70000652F-page 35

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 2.7 Oscillator Value Conditions on If your application needs to use certain Device Start-up Analog-to-Digital pins as analog input pins during the debug session, the user application must clear the If the PLL of the target device is enabled and corresponding bits in the AD1PCFGL register during configured for the device start-up oscillator, the initialization of the ADC module. maximum oscillator source frequency must be limited When MPLAB ICD 3 or MPLAB REAL ICE in-circuit to 4 MHz < FIN < 8 MHz (for MSPLL mode) or 3 MHz < emulator is used as a programmer, the user application FIN < 8 MHz (for ECPLL mode) to comply with device firmware must correctly configure the AD1PCFGL PLL start-up conditions. HSPLL mode is not supported. register. Automatic initialization of this register is only This means that if the external oscillator frequency is done during debugger operation. Failure to correctly outside this range, the application must start-up in the configure the register(s) will result in all FRC mode first. The fixed PLL settings of 4x after a Analog-to-Digital pins being recognized as analog input POR with an oscillator frequency outside this range will pins, resulting in the port value being read as a logic ‘0’, violate the device operating speed. which may affect user application functionality. Once the device powers up, the application firmware can enable the PLL and then perform a clock switch to 2.9 Unused I/Os the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration Unused I/O pins should be configured as outputs and Word. driven to a logic-low state. Alternately, connect a 1k to 10k resistor between VSS 2.8 Configuration of Analog and and unused pins. Digital Pins During ICSP Operations If MPLAB ICD 3 or MPLAB REAL ICE in-circuit emulator is selected as a debugger, it automatically initializes all of the Analog-to-Digital input pins (ANx) as “digital” pins, by setting all bits in the AD1PCFGL register. The bits in the register that correspond to the Analog-to-Digital pins that are initialized by MPLAB ICD 3 or MPLAB REAL ICE in-circuit emulator, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. DS70000652F-page 36  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 3.0 CPU A block diagram of the CPU is shown in Figure3-1, and the programmer’s model for the dsPIC33FJ16(GP/ Note1: This data sheet summarizes the features MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 of the dsPIC33FJ16(GP/MC)101/102 is shown in Figure3-2. and dsPIC33FJ32(GP/MC)101/102/104 family devices. It is not intended to be a 3.1 Data Addressing Overview comprehensive reference source. To complement the information in this data The data space can be addressed as 32K words or sheet, refer to “CPU” (DS70204) in the 64Kbytes and is split into two blocks, referred to as X “dsPIC33/PIC24 Family Reference Man- and Y data memory. Each memory block has its own ual”, which is available from the Microchip independent Address Generation Unit (AGU). The web site (www.microchip.com). MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory 2: Some registers and associated bits map as one linear data space. Certain DSP instructions described in this section may not be operate through the X and Y AGUs to support dual available on all devices. Refer to operand reads, which splits the data address space Section4.0 “Memory Organization” in into two parts. The X and Y data space boundary is this data sheet for device-specific register device-specific. and bit information. Overhead-free circular buffers (Modulo Addressing The dsPIC33FJ16(GP/MC)101/102 and mode) are supported in both X and Y address spaces. dsPIC33FJ32(GP/MC)101/102/104 CPU module has a The Modulo Addressing removes the software 16-bit (data) modified Harvard architecture with an boundary checking overhead for DSP algorithms. enhanced instruction set, including significant support Furthermore, the X AGU circular addressing can be for DSP. The CPU has a 24-bit instruction word with a used with any of the MCU class of instructions. The X variable length opcode field. The Program Counter AGU also supports Bit-Reversed Addressing to greatly (PC) is 23 bits wide and addresses up to 4Mx24 bits simplify input or output data reordering for radix-2 FFT of user program memory space. The actual amount of algorithms. program memory implemented varies by device. A The upper 32 Kbytes of the data space memory map single-cycle instruction prefetch mechanism is used to can optionally be mapped into program space at any help maintain throughput and provides predictable 16K program word boundary defined by the 8-bit execution. All instructions execute in a single cycle, Program Space Visibility Page (PSVPAG) register. The with the exception of instructions that change the program-to-data-space mapping feature lets any program flow, the double-word move (MOV.D) instruction access program space as if it were data instruction and the table instructions. Overhead-free space. program loop constructs are supported using the DO and REPEAT instructions, both of which are 3.2 DSP Engine Overview interruptible at any point. The dsPIC33FJ16(GP/MC)101/102 and The DSP engine features a high-speed, 17-bit by 17-bit dsPIC33FJ32(GP/MC)101/102/104 devices have six- multiplier, a 40-bit ALU, two 40-bit saturating accumula- teen, 16-bit Working registers in the programmer’s tors and a 40-bit bidirectional barrel shifter. The barrel model. Each of the Working registers can serve as a shifter is capable of shifting a 40-bit value up to 16 bits data, address, or address offset register. The 16th right or left, in a single cycle. The DSP instructions oper- Working register (W15) operates as a Software Stack ate seamlessly with all other instructions and have been Pointer (SSP) for interrupts and calls. designed for optimal real-time performance. The MAC instruction and other associated instructions can concur- There are two classes of instruction in the rently fetch two data operands from memory, while dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/ multiplying two W registers and accumulating and option- MC)101/102/104 devices: MCU and DSP. These two ally saturating the result in the same cycle. This instruc- instruction classes are seamlessly integrated into a sin- tion functionality requires that the RAM data space be gle CPU. The instruction set includes many addressing split for these instructions and linear for all others. Data modes and is designed for optimum C compiler effi- space partitioning is achieved in a transparent and ciency. For most instructions, dsPIC33FJ16(GP/ flexible manner through dedicating certain Working MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 registers to each address space. devices are capable of executing a data (or program data) memory read, a Working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle.  2011-2014 Microchip Technology Inc. DS70000652F-page 37

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 3.3 Special MCU Features The dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 supports 16/16 The dsPIC33FJ16(GP/MC)101/102 and and 32/16 divide operations, both fractional and dsPIC33FJ32(GP/MC)101/102/104 features a 17-bit integer. All divide instructions are iterative operations. by 17-bit, single-cycle multiplier that is shared by both They must be executed within a REPEAT loop, resulting the MCU ALU and DSP engine. The multiplier can per- in a total execution time of 19 instruction cycles. The form signed, unsigned and mixed-sign multiplication. divide operation can be interrupted during any of those Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit 19cycles without loss of data. multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for A 40-bit barrel shifter is used to perform up to a 16-bit special operations, such as (-1.0) x (-1.0). left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions. FIGURE 3-1: dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus Interrupt X Data Bus Controller 8 16 16 16 16 Data Latch Data Latch 23 PCU PCH PCL X RAM Y RAM 16 23 Program Counter Stack Loop Address Address Control Control Latch Latch Logic Logic 23 16 16 Address Latch Address Generator Units Program Memory EA MUX Data Latch ROM Latch 24 16 16 a at Instruction D Decode and al Control Instruction Reg er Lit Control Signals to Various Blocks 16 DSP Engine 16 x 16 W Register Array Divide Support 16 16-Bit ALU 16 To Peripheral Modules DS70000652F-page 38  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 3-2: dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 DSP Operand W5 Registers W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register AD39 AD31 AD15 AD0 DSP ACCA Accumulators ACCB PC22 PC0 0 Program Counter 7 0 TBLPAG Data Table Page Address 7 0 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address 22 DOEND DO Loop End Address 15 0 CORCON Core Configuration Register OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRH SRL  2011-2014 Microchip Technology Inc. DS70000652F-page 39

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 3.4 CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0 OA OB SA(1) SB(1) OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OA: Accumulator A Overflow Status bit 1 = Accumulator A has overflowed 0 = Accumulator A has not overflowed bit 14 OB: Accumulator B Overflow Status bit 1 = Accumulator B has overflowed 0 = Accumulator B has not overflowed bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit 1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated This bit may be read or cleared (not set). Clearing this bit will clear SA and SB. bit 9 DA: DO Loop Active bit 1 = DO loop is in progress 0 = DO loop is not in progress bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred Note 1: This bit can be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). DS70000652F-page 40  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop is in progress 0 = REPEAT loop is not in progress bit 3 N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 1 Z: MCU ALU Zero bit 1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: This bit can be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).  2011-2014 Microchip Technology Inc. DS70000652F-page 41

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT(1) DL2 DL1 DL0 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 15-13 Unimplemented: Read as ‘0’ bit 12 US: DSP Multiply Unsigned/Signed Control bit 1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed bit 11 EDT: Early DO Loop Termination Control bit(1) 1 = Terminates executing DO loop at the end of current loop iteration 0 = No effect bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits 111 = 7 DO loops are active • • • 001 = 1 DO loop is active 000 = 0 DO loops are active bit 7 SATA: ACCA Saturation Enable bit 1 = Accumulator A saturation is enabled 0 = Accumulator A saturation is disabled bit 6 SATB: ACCB Saturation Enable bit 1 = Accumulator B saturation is enabled 0 = Accumulator B saturation is disabled bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation is enabled 0 = Data space write saturation is disabled bit 4 ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space is visible in data space 0 = Program space is not visible in data space bit 1 RND: Rounding Mode Select bit 1 = Biased (conventional) rounding is enabled 0 = Unbiased (convergent) rounding is enabled bit 0 IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode is enabled for DSP multiply operations 0 = Fractional mode is enabled for DSP multiply operations Note 1: This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS70000652F-page 42  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 3.5 Arithmetic Logic Unit (ALU) The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take The dsPIC33FJ16(GP/MC)101/102 and the same number of cycles to execute. dsPIC33FJ32(GP/MC)101/102/104 ALU is 16 bits wide, and is capable of addition, subtraction, bit shifts 3.6 DSP Engine and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. The DSP engine consists of a high-speed, Depending on the operation, the ALU can affect the 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit values of the Carry (C), Zero (Z), Negative (N), Over- adder/subtracter (with two target accumulators, round flow (OV) and Digit Carry (DC) Status bits in the SR and saturation logic). register. The C and DC Status bits operate as Borrow The dsPIC33FJ16(GP/MC)101/102 and and Digit Borrow bits, respectively, for subtraction dsPIC33FJ32(GP/MC)101/102/104 is a single-cycle operations. instruction flow architecture; therefore, concurrent The ALU can perform 8-bit or 16-bit operations, operation of the DSP engine with MCU instruction flow depending on the mode of the instruction that is used. is not possible. However, some MCU ALU and DSP Data for the ALU operation can come from the W engine resources can be used concurrently by the register array or data memory, depending on the same instruction (e.g., ED, EDAC). addressing mode of the instruction. Likewise, output The DSP engine can also perform inherent accumulator- data from the ALU can be written to the W register array to-accumulator operations that require no additional or a data memory location. data. These instructions are ADD, SUB and NEG. Refer to the “16-Bit MCU and DSC Programmer’s The DSP engine has options selected through bits in Reference Manual” (DS70157) for information on the the CPU Core Control register (CORCON), as listed SR bits affected by each instruction. below: The dsPIC33FJ16(GP/MC)101/102 and • Fractional or Integer DSP Multiply (IF) dsPIC33FJ32(GP/MC)101/102/104 CPU incorporates • Signed or Unsigned DSP Multiply (US) hardware support for both multiplication and division. • Conventional or Convergent Rounding (RND) This includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division. • Automatic Saturation On/Off for ACCA (SATA) • Automatic Saturation On/Off for ACCB (SATB) 3.5.1 MULTIPLIER • Automatic Saturation On/Off for Writes to Data Using the high-speed, 17-bit x 17-bit multiplier of the Memory (SATDW) DSP engine, the ALU supports unsigned, signed or • Accumulator Saturation mode Selection (ACCSAT) mixed-sign operation in several MCU multiplication A block diagram of the DSP engine is shown in modes: Figure3-3. • 16-bit x 16-bit signed • 16-bit x 16-bit unsigned TABLE 3-1: DSP INSTRUCTIONS • 16-bit signed x 5-bit (literal) unsigned SUMMARY • 16-bit unsigned x 16-bit unsigned Algebraic ACC Write Instruction • 16-bit unsigned x 5-bit (literal) unsigned Operation Back • 16-bit unsigned x 16-bit signed CLR A = 0 Yes • 8-bit unsigned x 8-bit unsigned ED A = (x – y)2 No 3.5.2 DIVIDER EDAC A = A + (x – y)2 No The divide block supports 32-bit/16-bit and 16-bit/16-bit MAC A = A + (x * y) Yes signed and unsigned integer divide operations with the MAC A = A + x2 No following data sizes: MOVSAC No change in A Yes • 32-bit signed/16-bit signed divide MPY A = x * y No • 32-bit unsigned/16-bit unsigned divide MPY A = x 2 No • 16-bit signed/16-bit signed divide MPY.N A = – x * y No • 16-bit unsigned/16-bit unsigned divide MSC A = A – x * y Yes The quotient for all divide instructions ends up in W0 and the remainder in W1. The 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend.  2011-2014 Microchip Technology Inc. DS70000652F-page 43

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM S a 40 40-Bit Accumulator A 40 Round t 16 40-Bit Accumulator B u Logic r a Carry/Borrow Out t Saturate e Adder Carry/Borrow In Negate 40 40 40 Barrel 16 Shifter 40 us B a at D Sign-Extend X s u B a 32 16 at Zero Backfill D Y 32 33 17-Bit Multiplier/Scaler 16 16 To/From W Array DS70000652F-page 44  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 3.6.1 MULTIPLIER 3.6.2.1 Adder/Subtracter, Overflow and Saturation The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a The adder/subtracter is a 40-bit adder with an optional scaler to support either 1.31 fractional (Q31) or 32-bit zero input into one side and either true or complement integer results. Unsigned operands are zero-extended data into the other input. into the 17th bit of the multiplier input value. Signed • In the case of addition, the Carry/Borrow input is operands are sign-extended into the 17th bit of the active-high and the other input is true data (not multiplier input value. The output of the 17-bit x 17-bit complemented). multiplier/scaler is a 33-bit value that is sign-extended • In the case of subtraction, the Carry/Borrow input to 40 bits. Integer data is inherently represented as a is active-low and the other input is complemented. signed 2’s complement value, where the Most Signifi- cant bit (MSb) is defined as a sign bit. The range of an The adder/subtracter generates Overflow Status bits, N-bit 2’s complement integer is -2N-1 to 2N-1 – 1. SA/SB and OA/OB, which are latched and reflected in the STATUS Register: • For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including 0. • Overflow from bit 39: this is a catastrophic • For a 32-bit integer, the data range is overflow in which the sign of the accumulator is -2,147,483,648 (0x80000000) to 2,147,483,647 destroyed. (0x7FFF FFFF). • Overflow into guard bits 32 through 39: this is a recoverable overflow. This bit is set whenever all When the multiplier is configured for fractional the guard bits are not identical to each other. multiplication, the data is represented as a 2’s complement fraction, where the MSb is defined as a sign The adder has an additional saturation block that controls bit and the radix point is implied to lie just after the sign bit accumulator data saturation, if selected. It uses the result (QX format). The range of an N-bit 2’s complement of the adder, the Overflow Status bits described fraction with this implied radix point is -1.0 to (1 – 21-N). previously, and the SAT<A:B> (CORCON<7:6>) and For a 16-bit fraction, the Q15 data range is -1.0 (0x8000) ACCSAT (CORCON<4>) mode control bits to determine to 0.999969482 (0x7FFF) including 0 and has a precision when and to what value, to saturate. of 3.01518x10-5. In Fractional mode, the 16 x 16 multiply Six STATUS Register bits support saturation and operation generates a 1.31product that has a precision overflow: of 4.65661 x 10-10. • OA: ACCA overflowed into guard bits The same multiplier is used to support the MCU • OB: ACCB overflowed into guard bits multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiply operations. • SA: ACCA saturated (bit 31 overflow and saturation) The MUL instruction can be directed to use byte or or word-sized operands. Byte operands will direct a 16-bit ACCA overflowed into guard bits and result and word operands will direct a 32-bit result to saturated (bit 39 overflow and saturation) the specified register(s) in the W array. • SB: ACCB saturated (bit 31 overflow and 3.6.2 DATA ACCUMULATORS AND saturation) ADDER/SUBTRACTER or ACCB overflowed into guard bits and The data accumulator consists of a 40-bit adder/ saturated (bit 39 overflow and saturation) subtracter with automatic sign extension logic. It • OAB: Logical OR of OA and OB can select one of two accumulators (A or B) as its pre-accumulation source and post-accumulation • SAB: Logical OR of SA and SB destination. For the ADD and LAC instructions, the data The OA and OB bits are modified each time data to be accumulated or loaded can be optionally scaled passes through the adder/subtracter. When set, they using the barrel shifter prior to accumulation. indicate that the most recent operation has overflowed into the accumulator guard bits(bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when OA and OB are set and the corresponding Overflow Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1 register are set (refer to Section7.0 “Interrupt Controller”). This allows the user application to take immediate action; for example, to correct system gain.  2011-2014 Microchip Technology Inc. DS70000652F-page 45

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 The SA and SB bits are modified each time data 3.6.3 ACCUMULATOR ‘WRITE BACK’ passes through the adder/subtracter, but can only be The MAC class of instructions (with the exception of cleared by the user application. When set, they indicate MPY, MPY.N, ED and EDAC) can optionally write a that the accumulator has overflowed its maximum rounded version of the high word (bits 31 through 16) range (bit 31 for 32-bit saturation or bit 39 for 40-bit of the accumulator which is not targeted by the instruc- saturation) and will be saturated (if saturation is tion into data space memory. The write is performed enabled). When saturation is not enabled, SA and SB across the X bus into combined X and Y address default to bit 39 overflow, and therefore, indicate that a space. The following addressing modes are supported: catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, the SA and SB bits will • W13, Register Direct: generate an arithmetic warning trap when saturation is The rounded contents of the non-target disabled. accumulator are written into W13 as a 1.15fraction. The Overflow and Saturation Status bits can optionally • [W13]+ = 2, Register Indirect with Post-Increment: be viewed in the STATUS Register (SR) as the logical The rounded contents of the non-target accumu- OR of OA and OB (in bit OAB) and the logical OR of SA lator are written into the address pointed to by and SB (in bit SAB). Programmers can check one bit in W13 as a 1.15 fraction. W13 is then incremented the STATUS Register to determine whether either by 2 (for a word write). accumulator has overflowed, or one bit to determine whether either accumulator has saturated. This is 3.6.3.1 Round Logic useful for complex number arithmetic, which typically uses both accumulators. The round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) The device supports three Saturation and Overflow round function during an accumulator write (store). The modes: Round mode is determined by the state of the RND bit • Bit 39 Overflow and Saturation: in the CORCON register. It generates a 16-bit, When bit 39 overflow and saturation occurs, the 1.15data value that is passed to the data space write saturation logic loads the maximally positive saturation logic. If rounding is not indicated by the 9.31 value (0x7FFFFFFFFF) or maximally negative instruction, a truncated 1.15 data value is stored and 9.31 value (0x8000000000) into the target the least significant word (lsw) is simply discarded. accumulator. The SA or SB bit is set and remains Conventional rounding will zero-extend bit 15 of the set until cleared by the user application. This condi- accumulator and will add it to the ACCxH word (bits 16 tion is referred to as ‘super saturation’ and provides through 31 of the accumulator). protection against erroneous data or unexpected algorithm problems (such as gain calculations). • If the ACCxL word (bits0 through 15 of the accu- mulator) is between 0x8000 and 0xFFFF (0x8000 • Bit 31 Overflow and Saturation: included), ACCxH is incremented. When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive • If ACCxL is between 0x0000 and 0x7FFF, ACCxH 1.31 value (0x007FFFFFFF) or maximally nega- is left unchanged. tive 1.31 value (0x0080000000) into the target A consequence of this algorithm is that over a succes- accumulator. The SA or SB bit is set and remains sion of random rounding operations, the value tends to set until cleared by the user application. When be biased slightly positive. this Saturation mode is in effect, the guard bits are Convergent (or unbiased) rounding operates in the not used, so the OA, OB or OAB bits are never same manner as conventional rounding, except when set. ACCxL equals 0x8000. In this case, the Least • Bit 39 Catastrophic Overflow: Significant bit (LSb), bit16 of the accumulator, of The bit 39 Overflow Status bit from the adder is ACCxH is examined: used to set the SA or SB bit, which remains set until cleared by the user application. No saturation • If it is ‘1’, ACCxH is incremented. operation is performed and the accumulator is • If it is ‘0’, ACCxH is not modified. allowed to overflow, destroying its sign. If the Assuming that bit 16 is effectively random in nature, COVTE bit in the INTCON1 register is set, a this scheme removes any rounding bias that may catastrophic overflow can initiate a trap exception. accumulate. DS70000652F-page 46  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 The SAC and SAC.R instructions store either a The MSb of the source (bit 39) is used to determine the truncated (SAC), or rounded (SAC.R) version of the sign of the operand being tested. contents of the target accumulator to data memory via If the SATDW bit in the CORCON register is not set, the the X bus, subject to data saturation (see input data is always passed through unmodified under Section3.6.3.2 “Data Space Write Saturation”). For all conditions. the MAC class of instructions, the accumulator write- back operation functions in the same manner, 3.6.4 BARREL SHIFTER addressing combined MCU (X and Y) data space The barrel shifter can perform up to 16-bit arithmetic or though the X bus. For this class of instructions, the data logic right shifts, or up to 16-bit left shifts, in a single is always subject to rounding. cycle. The source can be either of the two DSP 3.6.3.2 Data Space Write Saturation accumulators or the X bus (to support multi-bit shifts of register or memory data). In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the The shifter requires a signed binary value to determine contents of the source accumulator. The data space both the magnitude (number of bits) and direction of the write saturation logic block accepts a 16-bit, shift operation. A positive value shifts the operand right. 1.15fractional value from the round logic block as its A negative value shifts the operand left. A value of ‘0’ input, together with overflow status from the original does not modify the operand. source (accumulator) and the 16-bit round adder. The barrel shifter is 40 bits wide, thereby obtaining a These inputs are combined and used to select the 40-bit result for DSP shift operations and a 16-bit result appropriate 1.15 fractional value as output to write to for MCU shift operations. Data from the X bus is data space memory. presented to the barrel shifter between Bit Positions 16 If the SATDW bit in the CORCON register is set, data and 31 for right shifts, and between Bit Positions 0 and (after rounding or truncation) is tested for overflow and 16 for left shifts. adjusted accordingly: • For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. • For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15value, 0x8000.  2011-2014 Microchip Technology Inc. DS70000652F-page 47

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70000652F-page 48  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 4.0 MEMORY ORGANIZATION 4.1 Program Address Space The program address memory space of the Note: This data sheet summarizes the features dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/ of the dsPIC33FJ16(GP/MC)101/102 and MC)101/102/104 devices is 4M instructions. The space dsPIC33FJ32(GP/MC)101/102/104 family is addressable by a 24-bit value derived either from the devices. However, it is not intended to be 23-bit Program Counter (PC) during program execution, a comprehensive reference source. To or from table operation or data space remapping as complement the information in this data described in Section4.6 “Interfacing Program and sheet, refer to “Data Memory” (DS70202) Data Memory Spaces”. and “Program Memory” (DS70203) in the “dsPIC33/PIC24 Family Reference User application access to the program memory space Manual”, which are available from the is restricted to the lower half of the address range Microchip web site (www.microchip.com). (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to The device architecture features separate program and permit access to the Configuration bits and Device ID data memory spaces and buses. This architecture also sections of the configuration memory space. allows the direct access of program memory from the The memory maps for the dsPIC33FJ16(GP/MC)101/ data space during code execution. 102 and dsPIC33FJ32(GP/MC)101/102/104 family of devices are shown in Figure4-1 and Figure4-2. FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33FJ16(GP/MC)101/102 DEVICES GOTO Instruction 0x000000 Reset Address 0x000002 0x000004 Interrupt Vector Table 0x0000FE Reserved 0x000100 0x000104 Alternate Vector Table 0x0001FE e User Program 0x000200 ac Flash Memory ory Sp F(l5a.s6hK Cinosntrfiugcutrioantiso)n 00xx000022BBFFAC em Words(1) 0x002BFE M er 0x002COO s U Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved e c a p S y 0xF7FFFE or Device Configuration 0xF80000 m e Shadow Registers 0xF80017 M 0xF80018 n o ati ur g nfi Reserved o C 0xFEFFFE 0xFF0000 DEVID (2) 0xFFFFFE Note 1: On Reset, these bits are automatically copied into the device Configuration Shadow registers.  2011-2014 Microchip Technology Inc. DS70000652F-page 49

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 4-2: PROGRAM MEMORY MAP FOR dsPIC33FJ32(GP/MC)101/102/104 DEVICES GOTO Instruction 0x000000 Reset Address 0x000002 0x000004 Interrupt Vector Table 0x0000FE Reserved 0x000100 0x000104 Alternate Vector Table 0x0001FE e User Program 0x000200 ac Flash Memory ory Sp F(1la1s.2hK C inosntfriguuctriaotniosn) 00xx00005577FFAC Mem Words(1) 0x0057FE er 0x005800 s U Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved e c a p S y 0xF7FFFE or Device Configuration 0xF80000 m e Shadow Registers 0xF80020 M 0xF80022 n o ati ur g nfi Reserved o C 0xFEFFFE 0xFF0000 DEVID (2) 0xFFFFFE Note 1: On Reset, these bits are automatically copied into the device Configuration Shadow registers. DS70000652F-page 50  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 4.1.1 PROGRAM MEMORY 4.1.2 INTERRUPT AND TRAP VECTORS ORGANIZATION All of the dsPIC33FJ16(GP/MC)101/102 and The program memory space is organized in word- dsPIC33FJ32(GP/MC)101/102/104 devices reserve addressable blocks. Although it is treated as 24 bits the addresses between 0x00000 and 0x000200 for wide, it is more appropriate to think of each address of hard-coded program execution vectors. A hardware the program memory as a lower and upper word, with Reset vector is provided to redirect code execution the upper byte of the upper word being unimplemented. from the default value of the PC on device Reset to the The lower word always has an even address, while the actual start of code. A GOTO instruction is programmed upper word has an odd address (Figure4-3). by the user application at 0x000000, with the actual address for the start of code at 0x000002. Program memory addresses are always word-aligned on the lower word and addresses are incremented or dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/ decremented by two during code execution. This MC)101/102/104 devices also have two Interrupt Vec- arrangement provides compatibility with data memory tor Tables (IVTs), located from 0x000004 to 0x0000FF space addressing and makes data in the program and 0x000100 to 0x0001FF. These vector tables allow memory space accessible. each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the Interrupt Vector Tables is provided in Section7.1 “Interrupt Vector Table”. FIGURE 4-3: PROGRAM MEMORY ORGANIZATION msw most significant word (msw) least significant word (lsw) PC Address Address (lsw Address) 23 16 8 0 0x000001 00000000 0x000000 0x000003 00000000 0x000002 0x000005 00000000 0x000004 0x000007 00000000 0x000006 Program Memory Instruction Width ‘Phantom’ Byte (read as ‘0’)  2011-2014 Microchip Technology Inc. DS70000652F-page 51

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 4.2 Data Address Space All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so The dsPIC33FJ16(GP/MC)101/102 and care must be taken when mixing byte and word dsPIC33FJ32(GP/MC)101/102/104 family CPU has a operations, or translating from 8-bit MCU code. If a separate 16-bit-wide data memory space. The data misaligned read or write is attempted, an address error space is accessed using separate Address Generation trap is generated. If the error occurred on a read, the Units (AGUs) for read and write operations. The data instruction in progress is completed. If the error memory maps is shown in Figure4-4. occurred on a write, the instruction is executed but the All Effective Addresses (EAs) in the data memory space write does not occur. In either case, a trap is then exe- are 16 bits wide and point to bytes within the data space. cuted, allowing the system and/or user application to This arrangement gives a data space address range of examine the machine state prior to execution of the 64Kbytes or 32K words. The lower half of the data address Fault. memory space (that is, when EA<15> = 0) is used for All byte loads into any W register are loaded into the implemented memory addresses, while the upper half LSB. The MSB is not modified. (EA<15> = 1) is reserved for the Program Space A Sign-Extend (SE) instruction is provided to allow user Visibility area (see Section4.6.3 “Reading Data from applications to translate 8-bit signed data to 16-bit Program Memory Using Program Space Visibility”). signed values. Alternately, for 16-bit unsigned data, Microchip dsPIC33FJ16(GP/MC)101/102 and user applications can clear the MSB of any W register dsPIC33FJ32(GP/MC)101/102/104 devices implement by executing a Zero-Extend (ZE) instruction on the up to 2 Kbytes of data memory. Should an EA point to appropriate address. a location outside of this area, an all-zero word or byte will be returned. 4.2.3 SFR SPACE 4.2.1 DATA SPACE WIDTH The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function The data memory space is organized in byte- Registers (SFRs). These are used by the addressable, 16-bit wide blocks. Data is aligned in data dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/ memory and registers as 16-bit words, but all data MC)101/102/104 family core and peripheral modules space EAs resolve to bytes. The Least Significant for controlling the operation of the device. Bytes (LSBs) of each word have even addresses, while SFRs are distributed among the modules that they the Most Significant Bytes (MSBs) have odd control and are generally grouped together by module. addresses. Much of the SFR space contains unused addresses; 4.2.2 DATA MEMORY ORGANIZATION these are read as ‘0’. AND ALIGNMENT Note: The actual set of peripheral features and To maintain backward compatibility with PIC® MCU interrupts varies by the device. Refer to devices and improve data space memory usage the corresponding device tables and efficiency, the dsPIC33FJ16(GP/MC)101/102 and pinout diagrams for device-specific dsPIC33FJ32(GP/MC)101/102/104 family instruction information. set supports both word and byte operations. As a consequence of byte accessibility, all Effective Address 4.2.4 NEAR DATA SPACE calculations are internally scaled to step through word- The 8-Kbyte area, between 0x0000 and 0x1FFF, is aligned memory. For example, the core recognizes that referred to as the Near Data Space. Locations in this Post-Modified Register Indirect Addressing mode space are directly addressable via a 13-bit absolute [Ws++] will result in a value of Ws + 1 for byte address field within all memory direct instructions. operations and Ws + 2 for word operations. Additionally, the whole data space is addressable using Data byte reads will read the complete word that the MOV class of instructions, which support Memory contains the byte, using the LSB of any EA to Direct Addressing mode with a 16-bit address field or determine which byte to select. The selected byte is by using Indirect Addressing mode with a Working placed onto the LSB of the data path. That is, data register as an Address Pointer. memory and registers are organized as two parallel byte-wide entities with shared (word) address decoding but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address. DS70000652F-page 52  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJ16(GP/MC)101/102 DEVICES WITH 1-KBYTE RAM MSB LSB Address 16 Bits Address MSb LSb 0x0001 0x0000 2-Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 X Data RAM (X) 8-Kbyte 1-Kbyte 0x09FF 0x09FE Near Data 0x0A01 0x0A00 SRAM Space Space Y Data RAM (Y) 0x0BFF 0x0BFE 0x0C01 0x0C00 0x1FFF 0x1FFE 0x2001 0x2000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE  2011-2014 Microchip Technology Inc. DS70000652F-page 53

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJ32(GP/MC)101/102/104 DEVICES WITH 2-KBYTE RAM MSB LSB Address 16 Bits Address MSb LSb 0x0001 0x0000 2 Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 X Data RAM (X) 8 Kbyte 2 Kbyte 0x0BFF 0x0BFE Near Data 0x0C01 0x0C00 SRAM Space Y Data RAM (Y) Space 0x0FFF 0x0FFE 0x1001 0x1000 0x1FFF 0x1FFE 0x2001 0x2000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE DS70000652F-page 54  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 4.2.5 X AND Y DATA SPACES The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, The core has two data spaces, X and Y. These data EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide spaces can beconsidered either separate (for some two concurrent data read paths. DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are Both the X and Y data spaces support Modulo accessed using two Address Generation Units (AGUs) Addressing mode for all instructions, subject to and separate data paths. This feature allows certain addressing mode restrictions. Bit-Reversed Addressing instructions to concurrently fetch two words from RAM, mode is only supported for writes to X data space. thereby enabling efficient execution of DSP algorithms All data memory writes, including in DSP instructions, such as Finite Impulse Response (FIR) filtering and view data space as combined X and Y address space. Fast Fourier transform (FFT). The boundary between the X and Y data spaces is The X data space is used by all instructions and device-dependent and is not user-programmable. supports all addressing modes. X data space has All Effective Addresses are 16 bits wide and point to separate read and write data buses. The X read data bytes within the data space. Therefore, the data space bus is the read data path for all instructions that view address range is 64 Kbytes, or 32K words, although the data space as combined X and Y address space. It is implemented memory locations vary by device. also the X data prefetch path for the dual operand DSP instructions (MAC class).  2011-2014 Microchip Technology Inc. DS70000652F-page 55

D TABLE 4-1: CPU CORE REGISTER MAP d S7 s 0000 SFR Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 6 52 WREG0 0000 Working Register 0 xxxx 3 F 3 -p WREG1 0002 Working Register 1 xxxx F a ge WREG2 0004 Working Register 2 xxxx J 5 1 6 WREG3 0006 Working Register 3 xxxx 6 WREG4 0008 Working Register 4 xxxx (G WREG5 000A Working Register 5 xxxx P WREG6 000C Working Register 6 xxxx /M WREG7 000E Working Register 7 xxxx C WREG8 0010 Working Register 8 xxxx ) 1 WREG9 0012 Working Register 9 xxxx 0 1 WREG10 0014 Working Register 10 xxxx / 1 WREG11 0016 Working Register 11 xxxx 0 WREG12 0018 Working Register 12 xxxx 2 WREG13 001A Working Register 13 xxxx A N WREG14 001C Working Register 14 xxxx D WREG15 001E Working Register 15 0800 d SPLIM 0020 Stack Pointer Limit Register xxxx s ACCAL 0022 Accumulator A Low Word Register xxxx P ACCAH 0024 Accumulator A High Word Register xxxx IC ACCAU 0026 Accumulator A Upper Word Register xxxx 3 3 ACCBL 0028 Accumulator B Low Word Register xxxx F ACCBH 002A Accumulator B High Word Register xxxx J 3 ACCBU 002C Accumulator B Upper Word Register xxxx 2 PCL 002E Program Counter Low Word Register 0000 ( G  2 PCH 0030 — — — — — — — — Program Counter High Byte Register 0000 P 0 1 TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register 0000 / 1 M -2 PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register 0000 0 C 14 RCOUNT 0036 Repeat Loop Counter Register xxxx ) M 1 ic DCOUNT 0038 DCOUNT<15:0> xxxx 0 ro DOSTARTL 003A DOSTARTL<15:1> 0 xxxx 1 chip DOSTARTH 003C — — — — — — — — — — DOSTARTH<5:0> 00xx /1 Te DOENDL 003E DOENDL<15:1> 0 xxxx 02 c hn DOENDH 0040 — — — — — — — — — — DOENDH 00xx /1 olo SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0 g 4 y In Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-1: CPU CORE REGISTER MAP (CONTINUED) 2 011-2 SFR Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 0 P 14 CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0020 I M MODCON 0046 XMODEN YMODEN — — BWM3 BWM2 BWM1 BWM0 YWM3 YWM2 YWM1 YWM0 XWM3 XWM2 XWM1 XWM0 0000 C ic 3 ro XMODSRT 0048 XS<15:1> 0 xxxx 3 c h F ip Te XYMMOODDESNRTD 000044CA XYES<<1155::11>> 10 xxxxxxxx J1 chn YMODEND 004E YE<15:1> 1 xxxx 6( olo XBREV 0050 BREN XB<14:0> xxxx G g P y Inc DLeISgIeCnNdT: x = unk0n0o5w2n value —on Reset, —— = unimplemented, read as ‘0’. Reset values are shown in hexadeDciismaabll.e Interrupts Counter Register 0000 /M . C ) 1 0 1 / 1 0 2 A N D d s P I C 3 3 F J 3 2 ( G P / M C D ) S 1 70 0 00 1 0 / 6 1 5 2 0 F-pag 2/1 e 0 5 4 7

D TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXGP101 DEVICES d S7 s 0000 NSaFmRe ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 6 52 CNEN1 0060 — — — CN12IE CN11IE — — — — — CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 3 F 3 -p CNEN2 0062 — CN30IE CN29IE — — — — — CN23IE CN22IE CN21IE — — — — — 0000 F a ge CNPU1 0068 — — — CN12PUE CN11PUE — — — — — CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 J 58 CNPU2 006A — CN30PUE CN29PUE — — — — — CN23PUE CN22PUE CN21PUE — — — — — 0000 16 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. (G P TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXMC101 DEVICES /M SFR SFR All C Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets ) 1 CNEN1 0060 — CN14IE CN13IE CN12IE CN11IE — — — — — CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0 1 CNEN2 0062 — CN30IE CN29IE — — — — — CN23IE CN22IE CN21IE — — — — — 0000 / 1 CNPU1 0068 — CN14PUE CN13PUE CN12PUE CN11PUE — — — — — CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0 2 CNPU2 006A — CN30PUE CN29PUE — — — — — CN23PUE CN22PUE CN21PUE — — — — — 0000 A Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. N D TABLE 4-4: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXX(GP/MC)102 DEVICES d s SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All P Name Addr Resets I C CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE — — — CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 3 CNEN2 0062 — CN30IE CN29IE — CN27IE — — CN24IE CN23IE CN22IE CN21IE — — — — CN16IE 0000 3 F CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE — — — CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 J CNPU2 006A — CN30PUE CN29PUE — CN27PUE — — CN24PUE CN23PUE CN22PUE CN21PUE — — — — CN16PUE 0000 3 2 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ( G  2 P 01 TABLE 4-5: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES / 1 M -2 014 NSaFmRe ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts C) M 1 ic CNEN1 0060 CN15IE CN13IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0 rochip T CCNNEPNU21 00006628 CN1—5PUE CCNN133P0IUEE CCNN1239PIUEE CCNN1228PIUEE CCNN112P7IUEE CCNN120P6IUEE CCNN92P5UIEE CCNN82P4UIEE CCNN72P3UIEE CCNN62P2UIEE CCNN52P1UIEE CCNN42P0UIEE CCNN31P9UIEE CCNN21P8UIEE CCNN11P7UIEE CCNN01P6UIEE 00000000 1/10 e CNPU2 006A — CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 2 c hn Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /1 olo 0 g 4 y In c .

 TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP 2 0 1 SFR SFR All d 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Name Addr Resets s 0 P 1 4 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — 0000 I M C ic INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 3 roc IFS0 0084 — — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 3 h F ip T IFS1 0086 — — INT2IF T5IF(2) T4IF(2) — — — — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 J e IFS2 0088 — — — — — — — — — — IC3IF — — — — — 0000 1 chn IFS3 008A FLTA1IF(1) RTCIF — — — — PWM1IF(1) — — — — — — — — — 0000 6( olo IFS4 008C — — CTMUIF — — — — — — — — — — — U1EIF FLTB1IF(3) 0000 G g P y Inc. IIEECC01 00009946 —— —— IANDT12IIEE UT15TIEX(I2E) UT14RIEX(2IE) SP—I1IE SPI—1EIE T—3IE T—2IE OC—2IE IC—2IE INT—1IE CTN1IIEE OCCM1IIEE MIIC2C1I1EIE SINI2TC01IEIE 00000000 /M C IEC2 0098 — — — — — — — — — — IC3IE — — — — — 0000 ) IEC3 009A FLTA1IE(1) RTCIE — — — — PWM1IE(1) — — — — — — — — — 0000 1 0 IEC4 009C — — CTMUIE — — — — — — — — — — — U1EIE FLTB1IE(3) 0000 1 IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2:0> 4444 /1 IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4440 0 2 IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 4444 A IPC3 00AA — — — — — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044 N IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444 D IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 d IPC6 00B0 — T4IP2(2) T4IP1(2) T4IP0(2) — — — — — — — — — — — — 4000 s P IPC7 00B2 — — — — — — — — — INT2IP2 INT2IP1 INT2IP0 — T5IP2(2) T5IP1(2) T5IP0(2) 0044 I C IPC9 00B6 — — — — — — — — — IC3IP2 IC3IP1 IC3IP0 — — — — 0040 3 IPC14 00C0 — — — — — — — — — PWM1IP2(1) PWM1IP1(1) PWM1IP0(1) — — — — 0040 3 IPC15 00C2 — FLTA1IP2(1) FLTA1IP1(1) FLTA1IP0(1) — RTCIP2 RTCIP1 RTCIP0 — — — — — — — — 4400 F J IPC16 00C4 — — — — — — — — — U1EIP2 U1EIP1 U1EIP0 — FLTB1IP2(3) FLTB1IP1(3) FLTB1IP0(3) 0040 3 IPC19 00CA — — — — — — — — — CTMUIP2 CTMUIP1 CTMUIP0 — — — — 0040 2 ( INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 G Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P Note 1: These bits are available in dsPIC33FJXXMC10X devices only. /M 2: These bits are available in dsPIC33FJ32(GP/MC)10X devices only. C 3: These bits are available in dsPIC33FJ(16/32)MC102/104 devices only. D ) S 1 70 0 00 1 0 / 6 1 5 2 0 F-pag 2/1 e 0 5 4 9

D TABLE 4-7: TIMERS REGISTER MAP FOR dsPIC33FJ16(GP/MC)10X DEVICES d S7 s 0000 NSaFmRe ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 6 52 TMR1 0100 Timer1 Register 0000 3 F 3 -p PR1 0102 Period Register 1 FFFF F a ge T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 J 60 TMR2 0106 Timer2 Register 0000 16 TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx (G TMR3 010A Timer3 Register 0000 P PR2 010C Period Register 2 FFFF /M PR3 010E Period Register 3 FFFF C T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 ) 1 T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 0 1 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / 1 0 TABLE 4-8: TIMERS REGISTER MAP FOR DSPIC33FJ32(GP/MC)10X DEVICES 2 A SFR SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 N Name Addr Resets D TMR1 0100 Timer1 Register 0000 d PR1 0102 Period Register 1 FFFF s T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 P I TMR2 0106 Timer2 Register 0000 C TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx 3 3 TMR3 010A Timer3 Register 0000 F PR2 010C Period Register 2 FFFF J 3 PR3 010E Period Register 3 FFFF 2 ( T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 G  2 T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 P 0 11 TMR4 0114 Timer4 Register 0000 /M -20 TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) xxxx C 1 4 TMR5 0118 Timer5 Register 0000 ) M 1 ic PR4 011A Period Register 4 FFFF 0 rochip T PT4RC5ON 001111CE TON — TSIDL — — — — P—eriod Regist—er 5 TGATE TCKPS1 TCKPS0 T32 — TCS — F0F0F0F0 1/10 e T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 2 c hn Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. /1 olo 0 g 4 y In c .

 TABLE 4-9: INPUT CAPTURE REGISTER MAP 2 0 1 SFR d 1 SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets -2 Addr s 0 P 14 IC1BUF 0140 Input Capture 1 Register xxxx I M IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 C ic 3 ro IC2BUF 0144 Input Capture 2 Register xxxx 3 c h IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 F ip T IC3BUF 0148 Input Capture 3 Register xxxx J e 1 ch IC3CON 014A — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 6 no Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. (G lo g P y Inc TABLE 4-10: OUTPUT COMPARE REGISTER MAP /M . SFR All SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C Addr Resets ) 1 OC1RS 0180 Output Compare 1 Secondary Register xxxx 0 OC1R 0182 Output Compare 1 Register xxxx 1 OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 /1 OC2RS 0186 Output Compare 2 Secondary Register xxxx 0 2 OC2R 0188 Output Compare 2 Register xxxx A OC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 N Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. D TABLE 4-11: 6-OUTPUT PWM1 REGISTER MAP FOR dsPIC33FJXXMC10X DEVICES d s SFR P SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State IC P1TCON 01C0 PTEN — PTSIDL — — — — — PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 0000 0000 0000 0000 3 3 P1TMR 01C2 PTDIR PWM1 Timer Count Value Register 0000 0000 0000 0000 F P1TPER 01C4 — PWM1 Time Base Period Register 0111 1111 1111 1111 J P1SECMP 01C6 SEVTDIR PWM1 Special Event Compare Register 0000 0000 0000 0000 3 2 PWM1CON1 01C8 — — — — — PMOD3 PMOD2 PMOD1 — PEN3H PEN2H PEN1H — PEN3L PEN2L PEN1L 0000 0000 0000 0000 ( G PWM1CON2 01CA — — — — SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 — — — — — IUE OSYNC UDIS 0000 0000 0000 0000 P P1DTCON1 01CC DTBPS1 DTBPS0 DTB5 DTB4 DTB3 DTB2 DTB1 DTB0 DTAPS1 DTAPS0 DTA5 DTA4 DTA3 DTA2 DTA1 DTA0 0000 0000 0000 0000 / P1DTCON2 01CE — — — — — — — — — — DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I 0000 0000 0000 0000 M P1FLTACON 01D0 — — FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM — — — — FAEN3 FAEN2 FAEN1 0000 0000 0000 0111 C DS P1FLTBCON 01D2 — — FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L FLTBM — — — — FBEN3 FBEN2 FBEN1 0000 0000 0000 0111 )1 70 P1OVDCON 01D4 — — POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L — — POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 0011 1111 0000 0000 0 000 P1DC1 01D6 PWM1 Duty Cycle 1 Register 0000 0000 0000 0000 1/ 6 1 5 P1DC2 01D8 PWM1 Duty Cycle 2 Register 0000 0000 0000 0000 2 0 F-pag PP1WDMC13KEY 0011DDAE PWM1P DWuMtyK CEyYc<le1 53: 0R>egister 00000000 00000000 00000000 00000000 2/1 e 6 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 04 1

D d S7 TABLE 4-12: I2C1 REGISTER MAP s 0 P 0 SFR All 00 SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 52F I2C1RCV 0200 — — — — — — — — I2C1 Receive Register 0000 33 -pa I2C1TRN 0202 — — — — — — — — I2C1 Transmit Register 00FF F g J e I2C1BRG 0204 — — — — — — — Baud Rate Generator Register 0000 6 1 2 I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 6 ( I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 G I2C1ADD 020A — — — — — — I2C1 Address Register 0000 P / I2C1MSK 020C — — — — — — I2C1 Address Mask Register 0000 M Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. C ) 1 0 TABLE 4-13: UART1 REGISTER MAP 1 / SFR All 1 SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Addr Resets 2 U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000 A U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 N U1TXREG 0224 — — — — — — — UART1 Transmit Register xxxx D U1RXREG 0226 — — — — — — — UART1 Receive Register 0000 d s U1BRG 0228 Baud Rate Generator Prescaler 0000 P Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. I C 3 3 TABLE 4-14: SPI1 REGISTER MAP F J SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 3 Addr Resets 2 (  SPI1STAT 0240 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 G 20 SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 P 1 / 1 SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY — 0000 M -2 0 SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000 C 1 4 M Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. )1 ic 0 ro 1 chip /1 T 0 e 2 c hn /1 olo 0 g 4 y In c .

 TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJXX(GP/MC)101 DEVICES 2 0 1 SFR All d 1 File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Addr Resets s 0 P 1 4 ADC1BUF0 0300 ADC1 Data Buffer 0 xxxx I M C ic ADC1BUF1 0302 ADC1 Data Buffer 1 xxxx 3 roc ADC1BUF2 0304 ADC1 Data Buffer 2 xxxx 3 h F ip T ADC1BUF3 0306 ADC1 Data Buffer 3 xxxx J e ADC1BUF4 0308 ADC1 Data Buffer 4 xxxx 1 chn ADC1BUF5 030A ADC1 Data Buffer 5 xxxx 6( o G lo ADC1BUF6 030C ADC1 Data Buffer 6 xxxx g P y Inc. AADDCC11BBUUFF78 003301E0 AADDCC11 DDaattaa BBuuffffeerr 78 xxxxxxxx /M C ADC1BUF9 0312 ADC1 Data Buffer 9 xxxx ) ADC1BUFA 0314 ADC1 Data Buffer 10 xxxx 1 0 ADC1BUFB 0316 ADC1 Data Buffer 11 xxxx 1 ADC1BUFC 0318 ADC1 Data Buffer 12 xxxx /1 ADC1BUFD 031A ADC1 Data Buffer 13 xxxx 0 2 ADC1BUFE 031C ADC1 Data Buffer 14 xxxx A ADC1BUFF 031E ADC1 Data Buffer 15 xxxx N AD1CON1 0320 ADON — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 — SIMSAM ASAM SAMP DONE 0000 D AD1CON2 0322 VCFG2 VCFG1 VCFG0 — — CSCNA CHPS1 CHPS0 BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000 d AD1CON3 0324 ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000 s P AD1CHS123 0326 — — — — — CH123NB1 CH123NB0 CH123SB — — — — — CH123NA1 CH123NA0 CH123SA 0000 I C AD1CHS0 0328 CH0NB — — CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — — CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000 3 AD1PCFGL 032C — — — — — PCFG<10:9>(1) — — — — — PCFG<3:0> 0000 3 AD1CSSL 0330 — — — — — CSS<10:9>(1) — — — — — CSS<3:0> 0000 F J Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 Note1: The PCFG<10:9> and CSS<10:9> bits are available in dsPIC33FJ32(GP/MC)101/102 devices only. 2 ( G P / M C D ) S 1 70 0 00 1 0 / 6 1 5 2 0 F-pag 2/1 e 0 6 4 3

D d S7 TABLE 4-16: ADC1 REGISTER MAP FOR dsPIC33FJXX(GP/MC)102 DEVICES s 0 P 0006 File Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC 52 3 F ADC1BUF0 0300 ADC1 Data Buffer 0 xxxx 3 -pa ADC1BUF1 0302 ADC1 Data Buffer 1 xxxx F g J e 6 ADC1BUF2 0304 ADC1 Data Buffer 2 xxxx 1 4 ADC1BUF3 0306 ADC1 Data Buffer 3 xxxx 6 ( ADC1BUF4 0308 ADC1 Data Buffer 4 xxxx G ADC1BUF5 030A ADC1 Data Buffer 5 xxxx P / ADC1BUF6 030C ADC1 Data Buffer 6 xxxx M ADC1BUF7 030E ADC1 Data Buffer 7 xxxx C ) ADC1BUF8 0310 ADC1 Data Buffer 8 xxxx 1 0 ADC1BUF9 0312 ADC1 Data Buffer 9 xxxx 1 ADC1BUFA 0314 ADC1 Data Buffer 10 xxxx / 1 ADC1BUFB 0316 ADC1 Data Buffer 11 xxxx 0 2 ADC1BUFC 0318 ADC1 Data Buffer 12 xxxx A ADC1BUFD 031A ADC1 Data Buffer 13 xxxx N ADC1BUFE 031C ADC1 Data Buffer 14 xxxx D ADC1BUFF 031E ADC1 Data Buffer 15 xxxx d AD1CON1 0320 ADON — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 — SIMSAM ASAM SAMP DONE 0000 s AD1CON2 0322 VCFG2 VCFG1 VCFG0 — — CSCNA CHPS1 CHPS0 BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000 P I AD1CON3 0324 ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000 C AD1CHS123 0326 — — — — — CH123NB1 CH123NB0 CH123SB — — — — — CH123NA1 CH123NA0 CH123SA 0000 3 3 AD1CHS0 0328 CH0NB — — CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — — CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000 F AD1PCFGL 032C — — — — — PCFG<10:9>(1) — — — PCFG<5:0> 0000 J 3 AD1CSSL 0330 — — — — — CSS<10:9>(1) — — — CSS<5:0> 0000 2 ( Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G  2 Note1: The PCFG<10:9> and CSS<10:9> bits are available in dsPIC33FJ32(GP/MC)101/102 devices only. P 0 1 / 1 M -2 0 C 1 4 ) M 1 ic 0 ro 1 chip /1 T 0 e 2 c hn /1 olo 0 g 4 y In c .

 2 TABLE 4-17: ADC1 REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES 0 1 d 1-20 File Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts sP 1 4 I M ADC1BUF0 0300 ADC1 Data Buffer 0 xxxx C icro ADC1BUF1 0302 ADC1 Data Buffer 1 xxxx 33 ch ADC1BUF2 0304 ADC1 Data Buffer 2 xxxx F ip T ADC1BUF3 0306 ADC1 Data Buffer 3 xxxx J e 1 ch ADC1BUF4 0308 ADC1 Data Buffer 4 xxxx 6 no ADC1BUF5 030A ADC1 Data Buffer 5 xxxx (G lo g ADC1BUF6 030C ADC1 Data Buffer 6 xxxx P y Inc ADC1BUF7 030E ADC1 Data Buffer 7 xxxx /M . ADC1BUF8 0310 ADC1 Data Buffer 8 xxxx C ADC1BUF9 0312 ADC1 Data Buffer 9 xxxx ) 1 ADC1BUFA 0314 ADC1 Data Buffer 10 xxxx 0 1 ADC1BUFB 0316 ADC1 Data Buffer 11 xxxx / 1 ADC1BUFC 0318 ADC1 Data Buffer 12 xxxx 0 ADC1BUFD 031A ADC1 Data Buffer 13 xxxx 2 ADC1BUFE 031C ADC1 Data Buffer 14 xxxx A ADC1BUFF 031E ADC1 Data Buffer 15 xxxx N D AD1CON1 0320 ADON — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 — SIMSAM ASAM SAMP DONE 0000 AD1CON2 0322 VCFG2 VCFG1 VCFG0 — — CSCNA CHPS1 CHPS0 BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000 d s AD1CON3 0324 ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000 P AD1CHS123 0326 — — — — — CH123NB1 CH123NB0 CH123SB — — — — — CH123NA1 CH123NA0 CH123SA 0000 IC AD1CHS0 0328 CH0NB — — CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — — CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000 3 AD1PCFGL 032C PCFG15 — — PCFG<12:0>(1) 0000 3 F AD1CSSL 0330 CSS15 — — CSS12:0>(1) 0000 J 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 Note1: The PCFG<10:9> and CSS<10:9> bits are available in dsPIC33FJ32(GP/MC)104 devices only. ( G P / M C D ) S 1 70 0 00 1 0 / 6 1 5 2 0 F-pag 2/1 e 0 6 4 5

D d S7 TABLE 4-18: CTMU REGISTER MAP s 0 P 0 SFR All 00 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 52 CTMUCON1 033A CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG — — — — — — — — 0000 3 F 3 -p CTMUCON2 033C EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — 0000 F a ge CTMUICON 033E ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 — — — — — — — — 0000 J 6 1 6 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 ( G P TABLE 4-19: REAL-TIME CLOCK AND CALENDAR REGISTER MAP / M SFR All File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C Addr Resets ) 1 ALRMVAL 0620 Alarm Value Register Window based on ALRMPTR<1:0> xxxx 0 ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 1 / RTCVAL 0624 RTCC Value Register Window based on RTCPTR<1:0> xxxx 1 0 RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000 2 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. A N D TABLE 4-20: PAD CONFIGURATION REGISTER MAP d SFR All s File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Addr Resets P I PADCFG1 02FC — — — — — — — — — — — — — — RTSECSEL — 0000 C 3 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 F J 3 2 ( G  2 P 0 1 / 1 M -2 0 C 1 4 ) M 1 ic 0 ro 1 chip /1 T 0 e 2 c hn /1 olo 0 g 4 y In c .

 TABLE 4-21: COMPARATOR REGISTER MAP 2 0 11-2 File Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts ds 0 P 1 4 CMSTAT 0650 CMSIDL — — — — C3EVT C2EVT C1EVT — — — — — C3OUT C2OUT C1OUT 0000 I M C ic CVRCON 0652 — — — — — VREFSEL BGSEL1 BGSEL0 CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 0000 3 roc CM1CON 0654 CON COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 3 h F ip T CM1MSKSRC 0656 — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0 0000 J e CM1MSKCON 0658 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000 1 ch 6 n CM1FLTR 065A — — — — — — — — — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0 0000 ( o G lo CM2CON 065C CON COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 g P y Inc. CCMM22MMSSKKSCROCN 006656E0 HL—MS —— OC—EN OC—NEN SEOLSBRECNC3 SEOLBSNRECNC2 SEOLSARECNC1 SEOLASNRECNC0 SENLSARGCSB3 SEPLASGRCSB2 SEALCSRECNB1 SEALCSNRECNB0 SEALSBRECNA3 SEALBSNRECNA2 SEALSARECNA1 SEALASNRECNA0 00000000 /M C CM2FLTR 0662 — — — — — — — — — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0 0000 ) CM3CON 0664 CON COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 1 0 CM3MSKSRC 0666 — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0 0000 1 / CM3MSKCON 0668 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000 1 0 CM3FLTR 066A — — — — — — — — — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0 0000 2 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. A N D TABLE 4-22: PERIPHERAL PIN SELECT INPUT REGISTER MAP d File SFR All s Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets P I RPINR0 0680 — — — INT1R<4:0> — — — — — — — — 1F00 C 3 RPINR1 0682 — — — — — — — — — — — INT2R<4:0> 001F 3 RPINR3 0686 — — — T3CKR<4:0> — — — T2CKR<4:0> 1F1F F RPINR4 0688 — — — T5CKR<4:0>(1) — — — T4CKR<4:0>(1) 1F1F J 3 RPINR7 068E — — — IC2R<4:0> — — — IC1R<4:0> 1F1F 2 ( RPINR8 0690 — — — — — — — — — — — IC3R<4:0> 001F G RPINR11 0696 — — — — — — — — — — — OCFAR<4:0> 001F P / RPINR18 06A4 — — — U1CTSR<4:0> — — — U1RXR<4:0> 1F1F M RPINR20 06A8 — — — SCK1R<4:0>(1) — — — SDI1R<4:0>(1) 1F1F C DS RPINR21 06AA — — — — — — — — — — — SS1R<4:0> 001F )1 70 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 00 Note1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only. 1 0 / 6 1 5 2 0 F-pag 2/1 e 0 6 4 7

D TABLE 4-23: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJXXGP101 DEVICES d S7 s 0000 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts PIC 6 52 RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> 0000 3 F 3 -p RPOR2 06C4 — — — — — — — — — — — RP4R<4:0> 0000 F a ge RPOR3 06C6 — — — RP7R<4:0> — — — — — — — — 0000 J 68 RPOR4 06C8 — — — RP9R<4:0> — — — RP8R<4:0> 0000 16 RPOR7 06CE — — — RP15R<4:0> — — — RP14R<4:0> 0000 (G Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P / M TABLE 4-24: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJXXMC101 DEVICES C ) 1 File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Name Addr Resets 1 / RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> 0000 1 0 RPOR2 06C4 — — — — — — — — — — — RP4R<4:0> 0000 2 RPOR3 06C6 — — — RP7R<4:0> — — — — — — — — 0000 A RPOR4 06C8 — — — RP9R<4:0> — — — RP8R<4:0> 0000 N RPOR6 06CC — — — RP13R<4:0> — — — RP12R<4:0> 0000 D RPOR7 06CE — — — RP15R<4:0> — — — RP14R<4:0> 0000 d Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. s P I C TABLE 4-25: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJXX(GP/MC)102 DEVICES 3 3 File SFR All F Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets J 3 RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> 0000 2 ( RPOR1 06C2 — — — RP3R<4:0> — — — RP2R<4:0> 0000 G  2 RPOR2 06C4 — — — RP5R<4:0> — — — RP4R<4:0> 0000 P 0 11 RPOR3 06C6 — — — RP7R<4:0> — — — RP6R<4:0> 0000 /M -20 RPOR4 06C8 — — — RP9R<4:0> — — — RP8R<4:0> 0000 C 1 4 RPOR5 06CA — — — RP11R<4:0> — — — RP10R<4:0> 0000 ) M 1 ic RPOR6 06CC — — — RP13R<4:0> — — — RP12R<4:0> 0000 0 rochip T RLePgOeRn7d: —0 =6 CunEimplem—ented, read— as ‘0’. Re—set values are shown in hexadRePci1m5aRl.<4:0> — — — RP14R<4:0> 0000 1/10 e 2 c hn /1 olo 0 g 4 y In c .

 2 TABLE 4-26: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES 0 11-2 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 0 P 1 4 M RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> 0000 IC ic RPOR1 06C2 — — — RP3R<4:0> — — — RP2R<4:0> 0000 3 roc RPOR2 06C4 — — — RP5R<4:0> — — — RP4R<4:0> 0000 3 h F ip T RPOR3 06C6 — — — RP7R<4:0> — — — RP6R<4:0> 0000 J e RPOR4 06C8 — — — RP9R<4:0> — — — RP8R<4:0> 0000 1 ch 6 n RPOR5 06CA — — — RP11R<4:0> — — — RP10R<4:0> 0000 ( o G log RPOR6 06CC — — — RP13R<4:0> — — — RP12R<4:0> 0000 P y Inc RPOR7 06CE — — — RP15R<4:0> — — — RP14R<4:0> 0000 /M . RPOR8 06D0 — — — RP17R<4:0> — — — RP16R<4:0> 0000 C RPOR9 06D2 — — — RP19R<4:0> — — — RP18R<4:0> 0000 ) 1 RPOR10 06D4 — — — RP21R<4:0> — — — RP20R<4:0> 0000 0 RPOR11 06D6 — — — RP23R<4:0> — — — RP22R<4:0> 0000 1 / RPOR12 06D8 — — — RP25R<4:0> — — — RP24R<4:0> 0000 1 0 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 A N TABLE 4-27: PORTA REGISTER MAP FOR dsPIC33FJ16(GP/MC)101/102 DEVICES D File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 d Name Addr Resets s TRISA 02C0 — — — — — — — — — — — TRISA<4:0> 001F P I PORTA 02C2 — — — — — — — — — — — RA<4:0 xxxx C 3 LATA 02C4 — — — — — — — — — — — LATA<4:0 xxxx 3 ODCA 02C6 — — — — — — — — — — — ODCA<4:2> — — 0000 F J Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 2 ( G TABLE 4-28: PORTA REGISTER MAP FOR dsPIC33FJ32(GP/MC)101/102 DEVICES P File SFR All / Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M Name Addr Resets C D TRISA 02C0 — — — — — — — — — — — TRISA<4:0> 001F ) S 1 70 PORTA 02C2 — — — — — — — — — — — RA<4:0 xxxx 0 00 LATA 02C4 — — — — — — — — — — — LATA<4:0 xxxx 1 0 / 65 ODCA 02C6 — — — — — — — — — — — — ODCA<3:2> — — 0000 1 2 0 F-pag Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2/1 e 0 6 4 9

D d S7 TABLE 4-29: PORTA REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES s 0 P 0 File SFR All 00 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 52 TRISA 02C0 — — — — — TRISA<10:7> — — TRISA<4:0> 001F 3 F 3 -p PORTA 02C2 — — — — — RA<10:7> — — RA<4:0> xxxx F a g J e LATA 02C4 — — — — — LATA<10:7> — — LATA<4:0> xxxx 7 1 0 ODCA 02C6 — — — — — ODCA<10:7> — — — ODCA<3:2> — — 0000 6 ( Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G P / M TABLE 4-30: PORTB REGISTER MAP FOR dsPIC33FJ16GP101 DEVICES C File Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts )1 0 TRISB 02C8 TRISB<15:14> — — — — TRISB<9:7> — — TRISB4 — — TRISB<1:0> C393 1 / PORTB 02CA RB<15:14> — — — — RB<9:7> — — RB4 — — RB<1:0> xxxx 1 0 LATB 02CC LATB<15:14> — — — — LATB<9:7> — — LATB4 — — LATB<1:0> xxxx 2 ODCB 02CE ODCB<15:14> — — — — ODCB<9:7> — — ODCB4 — — — — 0000 A Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. N D d TABLE 4-31: PORTB REGISTER MAP FOR dsPIC33FJ16MC101 DEVICES s P SFR All File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I Addr Resets C 3 TRISB 02C8 TRISB<15:12> — — TRISB<9:7> — — TRISB4 — — TRISB<1:0> F393 3 PORTB 02CA RB<15:12> — — RB<9:7> — — RB4 — — RB<1:0> xxxx F J LATB 02CC LATB<15:12> — — LATB<9:7> — — LATB4 — — LATB<1:0> xxxx 3 ODCB 02CE ODCB<15:12> — — ODCB<9:7> — — ODCB4 — — — — 0000 2 (  Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G 2 P 0 1 / 1 M -2 TABLE 4-32: PORTB REGISTER MAP FOR dsPIC33FJ16(GP/MC)102 DEVICES 0 C 1 4 File SFR All ) M Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 1 ic 0 ro TRISB 02C8 TRISB<15:0> FFFF 1 chip PORTB 02CA RB<15:0> xxxx /1 T 0 e LATB 02CC LATB<15:0> xxxx 2 c hn ODCB 02CE ODCB<15:4> — — — — 0000 /1 olo Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 g 4 y In c .

 TABLE 4-33: PORTB REGISTER MAP FOR dsPIC33FJ32GP101 DEVICES 2 0 11-2 File Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 0 P 1 4 TRISB 02C8 TRISB<15:14> — — — — TRISB<9:7> — — TRISB4 — — TRISB<1:0> C393 I M C ic PORTB 02CA RB<15:14> — — — — RB<9:7> — — RB4 — — RB<1:0> xxxx 3 roc LATB 02CC LATB<15:14> — — — — LATB<9:7> — — LATB4 — — LATB<1:0> xxxx 3 h F ip T ODCB 02CE ODCB<15:14> — — — — ODCB<9:7> — — — — — — — 0000 J e Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 ch 6 n ( o G lo g TABLE 4-34: PORTB REGISTER MAP FOR dsPIC33FJ32MC101 DEVICES P y Inc. File Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts /MC TRISB 02C8 TRISB<15:12> — — TRISB<9:7> — — TRISB4 — — TRISB<1:0> F393 )1 PORTB 02CA RB<15:12> — — RB<9:7> — — RB4 — — RB<1:0> xxxx 0 1 LATB 02CC LATB<15:12> — — LATB<9:7> — — LATB4 — — LATB<1:0> xxxx / 1 ODCB 02CE ODCB<15:12> — — ODCB<9:7> — — — — — — — 0000 0 2 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. A N TABLE 4-35: PORTB REGISTER MAP FOR dsPIC33FJ32(GP/MC)102 AND dsPIC33FJ32(GP/MC)104 DEVICES D d File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 s Name Addr Resets P TRISB 02C8 TRISB<15:0> FFFF IC PORTB 02CA RB<15:0> xxxx 3 3 LATB 02CC LATB<15:0> xxxx F ODCB 02CE ODCB<15:5> — — — — — 0000 J 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 ( G TABLE 4-36: PORTC REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES P / File SFR All M Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets C D ) S TRISC 02D0 — — — — — — TRISC<9:0> FFFF 1 7000 PORTC 02D2 — — — — — — RC<9:0> xxxx 01 0 LATC 02D4 — — — — — — LATC<9:0> xxxx / 6 1 5 2 ODCC 02D6 — — — — — — ODCC<9:6> — — — — — — 0000 0 F-pag Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2/1 e 0 7 4 1

D d S7 TABLE 4-37: SYSTEM CONTROL REGISTER MAP s 0 P 0 SFR All 00 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets IC 6 52 RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1) 3 F 3 -p OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF — LPOSCEN OSWEN 0300(2) F a ge CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN FRCDIV2 FRCDIV1 FRCDIV0 — — — — — — — — 3040 J 7 1 2 OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000 6 ( Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G Note1: RCON register Reset values are dependent on the type of Reset. P 2: OSCCON register Reset values are dependent on the FOSC Configuration bits and by type of Reset. / M C TABLE 4-38: NVM REGISTER MAP ) 1 0 SFR All File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 Addr Resets / 1 NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) 0 2 NVMKEY 0766 — — — — — — — — NVMKEY<7:0> 0000 A Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. N D d TABLE 4-39: PMD REGISTER MAP s P File Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts IC 3 PMD1 0770 T5MD(2) T4MD(2) T3MD T2MD T1MD — PWM1MD(1) — I2C1MD — U1MD — SPI1MD — — AD1MD 0000 3 F PMD2 0772 — — — — — IC3MD IC2MD IC1MD — — — — — — OC2MD OC1MD 0000 J PMD3 0774 — — — — — CMPMD RTCCMD — — — — — — — — — 0000 3 2 PMD4 0776 — — — — — — — — — — — — — CTMUMD — — 0000 (  Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G 2 Note1: This bit is available in dsPIC33FJXXMC10X devices only. P 0 1 2: These bits are available in dsPIC33FJ32(GP/MC)10X devices only. / 1 M -2 0 C 1 4 ) M 1 ic 0 ro 1 chip /1 T 0 e 2 c hn /1 olo 0 g 4 y In c .

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 4.2.6 SOFTWARE STACK 4.2.7 DATA RAM PROTECTION FEATURE In addition to its use as a working register, the W15 The dsPIC33F product family supports data RAM register in the dsPIC33FJ16(GP/MC)101/102 and protection features that enable segments of RAM to be dsPIC33FJ32(GP/MC)101/102/104 devices is also protected when used in conjunction with Boot and used as a Software Stack Pointer. The Stack Pointer Secure Code Segment Security. BSRAM (Secure RAM always points to the first available free word and grows Segment for BS) is accessible only from the Boot from lower to higher addresses. It pre-decrements for Segment Flash code when enabled. SSRAM (Secure stack pops and post-increments for stack pushes, as RAM Segment for RAM) is accessible only from the shown in Figure4-6. For a PC push during any CALL Secure Segment Flash code when enabled. See instruction, the MSb of the PC is zero-extended before Table4-1 for an overview of the BSRAM and SSRAM the push, ensuring that the MSb is always clear. SFRs. Note: A PC push during exception processing 4.3 Instruction Addressing Modes concatenates the SRL register to the MSb of the PC prior to the push. The addressing modes shown in Table4-40 form the basis of the addressing modes that are optimized to The Stack Pointer Limit register (SPLIM) associated support the specific features of individual instructions. with the Stack Pointer sets an upper address boundary The addressing modes provided in the MAC class of for the stack. SPLIM is uninitialized at Reset. As is the instructions differ from those provided in other case for the Stack Pointer, SPLIM<0> is forced to ‘0’ instruction types. because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source 4.3.1 FILE REGISTER INSTRUCTIONS or destination pointer, the resulting address is Most file register instructions use a 13-bit address field compared with the value in SPLIM. If the contents of (f) to directly address data present in the first the Stack Pointer (W15) and the SPLIM register are 8192bytes of data memory (Near Data Space). Most equal and a push operation is performed, a stack error file register instructions employ a Working register, W0, trap will not occur. However, the stack error trap will which is denoted as WREG in these instructions. The occur on a subsequent push operation. For example, to destination is typically either the same file register or cause a stack error trap when the stack grows beyond WREG (with the exception of the MUL instruction), address 0x0C00 in RAM, initialize the SPLIM with the which writes the result to a register or register pair. The value 0x0BFE. MOV instruction allows additional flexibility and can Similarly, a Stack Pointer underflow (stack error) trap is access the entire data space. generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from 4.3.2 MCU INSTRUCTIONS interfering with the SFR space. The three-operand MCU instructions are of the form: A write to the SPLIM register should not be immediately Operand 3 = Operand 1 <function> Operand 2 followed by an indirect read operation using W15. where Operand 1 is always a Working register (that is, the addressing mode can only be Register Direct), FIGURE 4-6: CALL STACK FRAME which is referred to as Wb. Operand 2 can be a W reg- ister, fetched from data memory, or a 5-bit literal. The 0x0000 15 0 result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions: d waress • Register Direct Todr s Ad • Register Indirect ower PC<15:0> W15 (before CALL) • Register Indirect Post-Modified Grgh 000000000 PC<22:16> ck Hi <Free Word> W15 (after CALL) • Register Indirect Pre-Modified a St • 5-Bit or 10-Bit Literal POP : [--W15] Note: Not all instructions support all of the PUSH: [W15++] addressing modes given above. Individual instructions can support different subsets of these addressing modes.  2011-2014 Microchip Technology Inc. DS70000652F-page 73

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 4-40: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. 4.3.3 MOVE AND ACCUMULATOR 4.3.4 MAC INSTRUCTIONS INSTRUCTIONS The dual source operand DSP instructions (CLR, ED, Move instructions and the DSP accumulator class of EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also instructions provide a greater degree of addressing referred to as MAC instructions, use a simplified set of flexibility than other instructions. In addition to the addressing modes to allow the user application to addressing modes supported by most MCU effectively manipulate the Data Pointers through instructions, move and accumulator instructions also register indirect tables. support Register Indirect with Register Offset The two-source operand prefetch registers must be Addressing mode, also referred to as Register Indexed members of the set {W8, W9, W10, W11}. For data mode. reads, W8 and W9 are always directed to the X RAGU, Note: For the MOV instructions, the addressing and W10 and W11 are always directed to the Y AGU. mode specified in the instruction can differ The Effective Addresses generated (before and after for the source and destination EA. How- modification) must, therefore, be valid addresses within ever, the 4-bit Wb (Register Offset) field is X data space for W8 and W9 and Y data space for W10 shared by both source and destination and W11. (but typically only used by one). Note: Register Indirect with Register Offset In summary, the following addressing modes are Addressing mode is available only for W9 supported by move and accumulator instructions: (in X space) and W11 (in Y space). • Register Direct In summary, the following addressing modes are • Register Indirect supported by the MAC class of instructions: • Register Indirect Post-modified • Register Indirect • Register Indirect Pre-modified • Register Indirect Post-Modified by 2 • Register Indirect with Register Offset (Indexed) • Register Indirect Post-Modified by 4 • Register Indirect with Literal Offset • Register Indirect Post-Modified by 6 • 8-Bit Literal • Register Indirect with Register Offset (Indexed) • 16-Bit Literal 4.3.5 OTHER INSTRUCTIONS Note: Not all instructions support all the In addition to the addressing modes outlined previously, addressing modes given above. Individual some instructions use literal constants of various sizes. instructions may support different subsets For example, BRA (branch) instructions use 16-bit signed of these addressing modes. literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. DS70000652F-page 74  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 4.4 Modulo Addressing The length of a circular buffer is not directly specified. It is determined by the difference between the correspond- Modulo Addressing mode is a method of providing an ing start and end addresses. The maximum possible automated means to support circular data buffers using length of the circular buffer is 32K words (64Kbytes). hardware. The objective is to remove the need for software to perform data address boundary checks 4.4.2 W ADDRESS REGISTER when executing tightly looped code, as is typical in SELECTION many DSP algorithms. • The Modulo and Bit-Reversed Addressing Control Modulo Addressing can operate in either data or program register, MODCON<15:0>, contains enable flags as space (since the Data Pointer mechanism is essentially well as a W register field to specify the W Address the same for both). One circular buffer can be supported registers. The XWM and YWM fields select which in each of the X (which also provides the pointers into registers will operate with Modulo Addressing. program space) and Y data spaces. Modulo Addressing • If XWM = 15, X RAGU and X WAGU Modulo can operate on any W Register Pointer. However, it is not Addressing is disabled. advisable to use W14 or W15 for Modulo Addressing • If YWM = 15, Y AGU Modulo Addressing is disabled. since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively. The X Address Space Pointer W register (XWM), to which Modulo Addressing is to be applied, is stored in In general, any particular circular buffer can be config- MODCON<3:0> (see Table4-1). Modulo Addressing is ured to operate in only one direction as there are enabled for X data space when XWM is set to any value certain restrictions on the buffer start address (for incre- other than ‘15’ and the XMODEN bit is set at menting buffers), or end address (for decrementing MODCON<15>. buffers), based upon the direction of the circular buffer. The Y Address Space Pointer W register (YWM) to The only exception to the usage restrictions is for which Modulo Addressing is to be applied is stored in buffers that have a power-of-two length. As these MODCON<7:4>. Modulo Addressing is enabled for Y buffers satisfy the start and end address criteria, they data space when YWM is set to any value other than can operate in a bidirectional mode (that is, address ‘15’ and the YMODEN bit is set at MODCON<14>. boundary checks are performed on both the lower and upper address boundaries). 4.4.1 START AND END ADDRESS The Modulo Addressing scheme requires that a starting and ending address be specified, and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table4-1). Note: Y space Modulo Addressing EA calcula- tions assume word-sized data (LSb of every EA is always clear). FIGURE 4-7: MODULO ADDRESSING OPERATION EXAMPLE Byte MOV #0x1100, W0 Address MOV W0, XMODSRT ;set modulo start address MOV #0x1163, W0 MOV W0, MODEND ;set modulo end address 0x1100 MOV #0x8001, W0 MOV W0, MODCON ;enable W1, X AGU for modulo MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer 0x1163 DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 Words  2011-2014 Microchip Technology Inc. DS70000652F-page 75

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 4.4.3 MODULO ADDRESSING If the length of a bit-reversed buffer is M = 2N bytes, APPLICABILITY the last ‘N’ bits of the data buffer start address must be zeros. Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W XB<14:0> is the bit-reversed address modifier, or ‘pivot register. Address boundaries check for addresses point,’ which is typically a constant. In the case of an equal to: FFT computation, its value is equal to half of the FFT data buffer size. • The upper boundary addresses for incrementing buffers Note: All bit-reversed EA calculations assume • The lower boundary addresses for decrementing word-sized data (LSb of every EA is always buffers clear). The XB<14:0> value is scaled accordingly to generate compatible (byte) It is important to realize that the address boundaries addresses. check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing When enabled, Bit-Reversed Addressing is executed buffers) boundary addresses (not just equal to). only for Register Indirect with Pre-Increment or Post- Address changes can, therefore, jump beyond Increment Addressing and word-sized data writes. It boundaries and still be adjusted correctly. will not function for any other addressing mode or for byte-sized data and normal addresses are generated Note: The modulo corrected Effective Address instead. When Bit-Reversed Addressing is active, the is written back to the register only when W Address Pointer is always added to the address Pre-Modify or Post-Modify Addressing modifier (XB) and the offset associated with the mode is used to compute the Effective Register Indirect Addressing mode is ignored. In Address. When an address offset (such addition, as word-sized data is a requirement, the LSb as [W7 + W2]) is used, Modulo of the EA is ignored (and always clear). Addressing correction is performed, but the contents of the register remain Note: Modulo Addressing and Bit-Reversed unchanged. Addressing should not be enabled together. If an application attempts to do 4.5 Bit-Reversed Addressing so, Bit-Reversed Addressing will assume priority when active. For the X WAGU and Bit-Reversed Addressing mode is intended to simplify Y AGU, Modulo Addressing will be data reordering for radix-2 FFT algorithms. It is disabled. However, Modulo Addressing will supported by the X AGU for data writes only. continue to function in the X RAGU. The modifier, which can be a constant value or register If Bit-Reversed Addressing has already been enabled contents, is regarded as having its bit order reversed. The by setting the BREN (XBREV<15>) bit, a write to the address source and destination are kept in normal order. XBREV register should not be immediately followed by Thus, the only operand requiring reversal is the modifier. an indirect read operation using the W register that has been designated as the Bit-Reversed Pointer. 4.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION Bit-Reversed Addressing mode is enabled in any of these situations: • BWM<3:0> bits (W register selection) in the MODCON register are any value other than ‘15’ (the stack cannot be accessed using Bit-Reversed Addressing) • The BREN bit is set in the XBREV register • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment DS70000652F-page 76  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE Se que ntial Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB<14:0> = 0x0008 for a 16-Word, Bit-Reversed Buffer TABLE 4-41: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15  2011-2014 Microchip Technology Inc. DS70000652F-page 77

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 4.6 Interfacing Program and Data 4.6.1 ADDRESSING PROGRAM SPACE Memory Spaces Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is The dsPIC33FJ16(GP/MC)101/102 and needed to create a 23-bit or 24-bit program address dsPIC33FJ32(GP/MC)101/102/104 architecture uses from 16-bit data registers. The solution depends on the a 24-bit-wide program space and a 16-bit-wide data interface method to be used. space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the For table operations, the 8-bit Table Page (TBLPAG) program space. To use this data successfully, it must register is used to define a 32K word region within the be accessed in a way that preserves the alignment of program space. This is concatenated with a 16-bit EA to information in both spaces. arrive at a full 24-bit program space address. In this format, the MSb of TBLPAG is used to determine if the Aside from normal execution, the dsPIC33FJ16(GP/ operation occurs in the user memory (TBLPAG<7>=0) MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 or the configuration memory (TBLPAG<7> = 1). architecture provides two methods by which program space can be accessed during operation: For remapping operations, the 8-bit Program Space Visibility (PSVPAG) register is used to define a • Using table instructions to access individual 16Kword page in the program space. When the MSb bytes, or words, anywhere in the program space of the EA is ‘1’, PSVPAG is concatenated with the lower • Remapping a portion of the program space into 15 bits of the EA to form a 23-bit program space the data space (Program Space Visibility) address. Unlike table operations, this limits remapping Table instructions allow an application to read or write operations strictly to the user memory area. to small areas of the program memory. This capability Table4-42 and Figure4-9 show how the program EA is makes the method ideal for accessing data tables that created for table operations and remapping accesses need to be updated periodically. It also allows access from the data EA. to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for lookups from a large table of static data. The application can only access the lsw of the program word. TABLE 4-42: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 (Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0>(1) (Block Remap/Read) 0 xxxx xxxx xxx xxxx xxxx xxxx Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. DS70000652F-page 78  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 0 23 Bits EA 1/0 Table Operations(2) 1/0 TBLPAG 8 Bits 16 Bits 24 Bits Select 1 EA 0 Program Space Visibility(1) 0 PSVPAG (Remapping) 8 Bits 15 Bits 23 Bits User/Configuration Byte Select Space Select Note 1: The Least Significant bit of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space.  2011-2014 Microchip Technology Inc. DS70000652F-page 79

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 4.6.2 DATA ACCESS FROM PROGRAM • TBLRDH (Table Read High): MEMORY USING TABLE - In Word mode, this instruction maps the entire INSTRUCTIONS upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the The TBLRDL and TBLWTL instructions offer a direct ‘phantom byte’, will always be ‘0’. method of reading or writing the lower word of any address within the program space without going - In Byte mode, this instruction maps the upper through data space. The TBLRDH and TBLWTH or lower byte of the program word to D<7:0> instructions are the only method to read or write the of the data address, in the TBLRDL instruc- upper 8bits of a program space word as data. tion. The data is always ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1). The PC is incremented by two for each successive 24-bit program word. This allows program memory In a similar fashion, two table instructions, TBLWTH addresses to directly map to data space addresses. Pro- and TBLWTL, are used to write individual bytes or gram memory can thus be regarded as two 16-bit-wide words to a program space address. The details of word address spaces, residing side by side, each with their operation are explained in Section5.0 “Flash the same address range. TBLRDL and TBLWTL access Program Memory”. the space that contains the least significant data word. For all table operations, the area of program memory TBLRDH and TBLWTH access the space that contains the space to be accessed is determined by the Table Page upper data byte. register (TBLPAG). TBLPAG covers the entire program Two table instructions are provided to move byte or memory space of the device, including user and word-sized (16-bit) data to and from program space. configuration spaces. When TBLPAG<7> = 0, the table Both function as either byte or word operations. page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration • TBLRDL (Table Read Low): space. - In Word mode, this instruction maps the lower word of the program space location (P<15:0>) to a data address (D<15:0>). - In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’. FIGURE 4-10: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG 02 23 15 0 0x000000 23 16 8 0 00000000 00000000 0x020000 00000000 0x030000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 0x800000 Only read operations are shown; write operations are also valid in the user memory area. DS70000652F-page 80  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 4.6.3 READING DATA FROM PROGRAM 24-bit program word are used to contain the data. The MEMORY USING PROGRAM SPACE upper 8 bits of any program space location used as VISIBILITY data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible The upper 32 Kbytes of data space may optionally be issues should the area of code ever be accidentally mapped into any 16K word page of the program space. executed. This option provides transparent access to stored constant data from the data space without the need to Note: PSV access is temporarily disabled during use special instructions (such as TBLRDL and Table Reads/Writes. TBLRDH). For operations that use PSV and are executed outside a Program space access through the data space occurs REPEAT loop, the MOV and MOV.D instructions require if the MSb of the data space EA is ‘1’ and program one instruction cycle in addition to the specified execution space visibility is enabled by setting the PSV bit in the time. All other instructions require two instruction cycles Core Control register (CORCON<2>). The location of in addition to the specified execution time. the program memory space to be mapped into the data For operations that use PSV, and are executed inside space is determined by the Program Space Visibility a REPEAT loop, these instances require two instruction Page register (PSVPAG). This 8-bit register defines cycles in addition to the specified execution time of the any one of 256 possible pages of 16K words in program instruction: space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the • Execution in the first iteration EA functioning as the lower bits. By incrementing the • Execution in the last iteration PC by 2 for each program memory word, the lower 15 • Execution prior to exiting the loop due to an bits of data space addresses directly map to the lower interrupt 15 bits in the corresponding program space addresses. • Execution upon re-entering the loop after an Data reads to this area add a cycle to the instruction interrupt is serviced being executed, since two program memory fetches Any other iteration of the REPEAT loop will allow the are required. instruction using PSV to access data, to execute in a Although each data space address, 0x8000 and higher, single cycle. maps directly into a corresponding program memory address (see Figure4-11), only the lower 16 bits of the FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space Data Space PSVPAG 23 15 0 02 0x000000 0x0000 Data EA<14:0> 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory 0x8000 space... PSV Area ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 0x800000  2011-2014 Microchip Technology Inc. DS70000652F-page 81

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70000652F-page 82  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 5.0 FLASH PROGRAM MEMORY ICSP allows a device to be serially programmed while in the end application circuit. This is done with two lines Note 1: This data sheet summarizes the features for programming clock and programming data (one of of the dsPIC33FJ16(GP/MC)101/102 and the alternate programming pin pairs: PGECx/PGEDx), dsPIC33FJ32(GP/MC)101/102/104 family and three other lines for power (VDD), ground (VSS) and devices. It is not intended to be a Master Clear (MCLR). This allows users to manufac- comprehensive reference source. To ture boards with unprogrammed devices and then complement the information in this data program the Digital Signal Controller just before sheet, refer to “Flash Programming” shipping the product. This also allows the most recent (DS70191) in the “dsPIC33/PIC24 Family firmware or a custom firmware to be programmed. Reference Manual”, which is available RTSP is accomplished using TBLRD (Table Read) and from the Microchip web site TBLWT (Table Write) instructions. With RTSP, the user (www.microchip.com). application can write program memory data in a single 2: Some registers and associated bits program memory word and erase program memory in described in this section may not be blocks or ‘pages’ of 512 instructions (1536 bytes). available on all devices. Refer to Section4.0 “Memory Organization” in 5.1 Table Instructions and Flash this data sheet for device-specific register Programming and bit information. Regardless of the method used, all programming of The dsPIC33FJ16(GP/MC)101/102 and Flash memory is done with the Table Read and Table dsPIC33FJ32(GP/MC)101/102/104 devices contain Write instructions. These allow direct read and write internal Flash program memory for storing and access to the program memory space, from the data executing application code. The memory is readable, memory, while the device is in normal operating mode. writable and erasable during normal operation over the The 24-bit target address in the program memory is entire VDD range. formed using bits<7:0> of the TBLPAG register and the Flash memory can be programmed in two ways: Effective Address (EA) from a W register specified in the table instruction, as shown in Figure5-1. • In-Circuit Serial Programming™ (ICSP™) programming capability The TBLRDL and the TBLWTL instructions are used to • Run-Time Self-Programming (RTSP) read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 Bits Using 0 Program Counter 0 Program Counter Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 Bits 16 Bits User/Configuration Byte Space Select 24-Bit EA Select  2011-2014 Microchip Technology Inc. DS70000652F-page 83

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 5.2 RTSP Operation 5.3.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 Flash program Programmers can program one word (24 bits) of memory array is organized into rows of 64 instructions or program Flash memory at a time. To do this, it is 192 bytes. RTSP allows the user application to erase a necessary to erase the 8-row erase page that contains page of memory, which consists of eight rows the desired address of the location the user wants to (512instructions); and to program one word. Table26-12 change. shows typical erase and programming times. The 8-row For protection against accidental operations, the write erase pages are edge-aligned from the beginning of initiate sequence for NVMKEY must be used to allow program memory, on boundaries of 1536 bytes. any erase or program operation to proceed. After the programming command has been executed, the user 5.3 Programming Operations application must wait for the programming time until programming is complete. The two instructions A complete programming sequence is necessary for following the start of the programming sequence programming or erasing the internal Flash in RTSP should be NOPs. mode. The processor stalls (waits) until the operation is finished. Note: Performing a page erase operation on the last page of program memory will clear the The programming time depends on the FRC accuracy Flash Configuration Words, thereby (see Table26-18) and the value of the FRC Oscillator enabling code protection as a result. Tuning register (see Register8-3). Use the following Therefore, users should avoid performing formula to calculate the minimum and maximum values page erase operations on the last page of for the Word write time and page erase time (see program memory. Parameters D138a and D138b, and ParametersD137a and D137b in Table26-12, respectively). Refer to “Flash Programming” (DS70191) in the “dsPIC33/PIC24 Family Reference Manual” for details EQUATION 5-1: PROGRAMMING TIME and codes examples on programming using RTSP. T -------------------------------------------------------------------------------------------------------------------------- 5.4 Control Registers 7.37 MHzFRC Accuracy%FRC Tuning% Two SFRs are used to read and write the program For example, if the device is operating at +125°C, the Flash memory: NVMCON and NVMKEY. FRC accuracy will be ±2%. If the TUN<5:0> bits (see The NVMCON register (Register5-1) controls which Register8-3) are set to ‘b000000, the minimum row blocks are to be erased, which memory type is to be write time is equal to Equation5-2. programmed and the start of the programming cycle. NVMKEY is a write-only register that is used for write EQUATION 5-2: MINIMUM ROW WRITE protection. To start a programming or erase sequence, TIME the user application must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section5.3 355 Cycles “Programming Operations” for further details. T =----------------------------------------------------------------------------------------------= 47.4s RW 7.37 MHz1+0.021–0.00375 The maximum row write time is equal to Equation5-3. EQUATION 5-3: MAXIMUM ROW WRITE TIME 355 Cycles T =----------------------------------------------------------------------------------------------= 49.3s RW 7.37 MHz1–0.021–0.00375 Setting the WR bit (NVMCON<15>) starts the opera- tion and the WR bit is automatically cleared when the operation is finished. DS70000652F-page 84  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — ERASE — — NVMOP3(2) NVMOP2(2) NVMOP1(2) NVMOP0(2) bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit(1) 1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit(1) 1 = Enables Flash program/erase operations 0 = Inhibits Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit(1) 1 = Performs the erase operation specified by NVMOP<3:0> on the next WR command 0 = Performs the program operation specified by NVMOP<3:0> on the next WR command bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation Selection bits(1,2) If ERASE = 1: 1111 = No operation 1101 = Erase General Segment 1100 = No operation 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = No operation If ERASE = 0: 1111 = No operation 1101 = No operation 1100 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = No operation 0000 = No operation Note 1: These bits can only be reset on a POR. 2: All other combinations of NVMOP<3:0> are unimplemented. REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — —  2011-2014 Microchip Technology Inc. DS70000652F-page 85

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register bits (write-only) DS70000652F-page 86  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 6.0 RESETS A simplified block diagram of the Reset module is shown in Figure6-1. Note1: This data sheet summarizes the features Any active source of Reset will make the SYSRST sig- of the dsPIC33FJ16(GP/MC)101/102 nal active. On system Reset, some of the registers and dsPIC33FJ32(GP/MC)101/102/104 associated with the CPU and peripherals are forced to family devices. It is not intended to be a a known Reset state, and some are unaffected. comprehensive reference source. To complement the information in this data Note: Refer to the specific peripheral section or sheet, refer to “Reset” (DS70192) in the Section3.0 “CPU” of this data sheet for “dsPIC33/PIC24 Family Reference register Reset states. Manual”, which is available from the Microchip web site (www.microchip.com). All types of device Reset set a corresponding status bit in the RCON register to indicate the type of Reset (see 2: Some registers and associated bits Register6-1). described in this section may not be available on all devices. Refer to All bits that are set, with the exception of the POR bit Section4.0 “Memory Organization” in (RCON<0>), are cleared during a POR event. The user this data sheet for device-specific register application can set or clear any bit at any time during and bit information. code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software The Reset module combines all Reset sources and does not cause a device Reset to occur. controls the device Master Reset Signal, SYSRST. The The RCON register also has other bits associated with following is a list of device Reset sources: the Watchdog Timer and device power-saving states. • POR: Power-on Reset The function of these bits is discussed in other sections • BOR: Brown-out Reset of this data sheet. • MCLR: Master Clear Pin Reset Note: The status bits in the RCON register • SWR: RESET Instruction should be cleared after they are read so • WDTO: Watchdog Timer Reset that the next RCON register value after a • CM: Configuration Mismatch Reset device Reset is meaningful. • TRAPR: Trap Conflict Reset • IOPUWR: Illegal Condition Device Reset - Illegal Opcode Reset - Uninitialized W Register Reset - Security Reset FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle Internal BOR Regulator SYSRST VDD VDD Rise POR Detect Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch  2011-2014 Microchip Technology Inc. DS70000652F-page 87

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 6.1 Reset Control Register REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 TRAPR IOPUWR — — — — CM VREGS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or Uninitialized W register used as an Address Pointer caused a Reset 0 = An Illegal Opcode or Uninitialized W Reset has not occurred bit 13-10 Unimplemented: Read as ‘0’ bit 9 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has occurred 0 = A Configuration Mismatch Reset has not occurred bit 8 VREGS: Voltage Regulator Stand-by During Sleep bit 1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Stand-by mode during Sleep bit 7 EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is set to ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70000652F-page 88  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is set to ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.  2011-2014 Microchip Technology Inc. DS70000652F-page 89

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 6.2 System Reset A Warm Reset is the result of all other Reset sources, including the RESET instruction. On Warm Reset, the The dsPIC33FJ16(GP/MC)101/102 and device will continue to operate from the current clock dsPIC33FJ32(GP/MC)101/102/104 family of devices source as indicated by the Current Oscillator Selec- have two types of Reset: tion (COSC<2:0>) bits in the Oscillator Control • Cold Reset (OSCCON<14:12>) register. • Warm Reset The device is kept in a Reset state until the system A Cold Reset is the result of a POR or a BOR. On a power supplies have stabilized at appropriate levels Cold Reset, the FNOSC<2:0> Configuration bits in the and the oscillator clock is ready. The sequence in FOSCSEL Configuration register selects the device which this occurs is shown in Figure6-2. clock source. TABLE 6-1: OSCILLATOR DELAY Oscillator Oscillator Start-up Oscillator Mode PLL Lock Time Total Delay Start-up Delay Timer FRC, FRCDIV16, TOSCD(1) — — TOSCD FRCDIVN FRCPLL TOSCD(1) — TLOCK(3) TOSCD(1) + TLOCK(3) MS TOSCD(1) TOST(2) — TOSCD(1) + TOST(2) HS TOSCD(1) TOST(2) — TOSCD(1) + TOST(2) EC — — — — MSPLL TOSCD(1) TOST(2) TLOCK(3) TOSCD(1) + TOST(2) + TLOCK(3) ECPLL — — TLOCK(3) TLOCK(3) SOSC TOSCD(1) TOST(2) — TOSCD(1) + TOST(2) LPRC TOSCD(1) — — TOSCD(1) Note 1: TOSCD = Oscillator Start-up Delay (1.1s max. for FRC, 70s max. for LPRC). Crystal oscillator start-up times vary with crystal characteristics, load capacitance, etc. 2: TOST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4s for a 10MHz crystal and TOST=32ms for a 32kHz crystal. 3: TLOCK = PLL Lock time (1.5ms nominal) if PLL is enabled. DS70000652F-page 90  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 6-2: SYSTEM RESET TIMING VBOR VPOR VDD TPOR POR 1 TBOR 2 BOR 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 FSCM TFSCM 5 Device Status Reset Run Time 1. POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. 2. BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes stable. 3. PWRT Timer: The Power-up Timer continues to hold the processor in Reset for a specific period of time (TPWRT) after a BOR. The delay, TPWRT, ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay, TPWRT, has elapsed, the SYSRST becomes inactive, which in turn, enables the selected oscillator to start generating clock cycles. 4. Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in Table6-1. Refer to Section8.0 “Oscillator Configuration” for more information. 5. When the oscillator clock is ready, the processor begins execution from location, 0x000000. The user application programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. 6. The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay, TFSCM, has elapsed. TABLE 6-2: OSCILLATOR PARAMETERS Note: When the device exits the Reset condition Symbol Parameter Value (begins normal operation), the device operating parameters (voltage, frequency, VPOR POR Threshold 1.8V nominal temperature, etc.) must be within their TPOR POR Extension Time 30s maximum operating ranges; otherwise, the device VBOR BOR Threshold 2.5V nominal may not function correctly. The user appli- cation must ensure that the delay between TBOR BOR Extension Time 100s maximum the time power is first applied, and the time TPWRT Power-up Time 64ms nominal SYSRST becomes inactive, is long Delay enough to get all operating parameters TFSCM Fail-Safe Clock 900s maximum within specification. Monitor Delay  2011-2014 Microchip Technology Inc. DS70000652F-page 91

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 6.3 POR 6.4 BOR and PWRT A POR circuit ensures the device is reset from power- The on-chip regulator has a BOR circuit that resets the on. The POR circuit is active until VDD crosses the device when the VDD is too low (VDD < VBOR) for proper VPOR threshold and the delay, TPOR, has elapsed. The device operation. The BOR circuit keeps the device in delay, TPOR, ensures that the internal device bias Reset until VDD crosses the VBOR threshold and the circuits become stable. delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes stable. The device supply voltage characteristics must meet the specified starting voltage and rise rate require- The Brown-out Reset (BOR) status bit in the Reset ments to generate the POR. Refer to Section26.0 Control (RCON<1>) register is set to indicate the “Electrical Characteristics” for details. Brown-out Reset. The Power-on Reset (POR) status bit in the Reset Con- The device will not run at full speed after a BOR as the trol (RCON<0>) register is set to indicate the Power-on VDD should rise to acceptable levels for full-speed Reset. operation. The Power-up Timer (PWRT) provides power- up time delay (TPWRT) to ensure that the system power supplies have stabilized at the appropriate levels for full-speed operation before the SYSRST is released. Refer to Section23.0 “Special Features” for further details. Figure6-3 shows the typical brown-out scenarios. The Reset delay (TBOR + TPWRT) is initiated each time VDD rises above the VBOR trip point. FIGURE 6-3: BROWN-OUT RESET SITUATIONS VDD VBOR TBOR + TPWRT SYSRST VDD VBOR TBOR + TPWRT SYSRST VDD Dips Before PWRT Expires VDD VBOR TBOR + TPWRT SYSRST DS70000652F-page 92  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 6.5 External Reset (EXTR) 6.8 Trap Conflict Reset The External Reset is generated by driving the MCLR If a lower priority hard trap occurs while a higher priority pin low. The MCLR pin is a Schmitt trigger input with an trap is being processed, a hard Trap Conflict Reset additional glitch filter. Reset pulses that are longer than occurs. The hard traps include exceptions of Priority the minimum pulse width will generate a Reset. Refer Level 13 through Level 15, inclusive. The address error to Section26.0 “Electrical Characteristics” for (Level13) and oscillator error (Level 14) traps fall into minimum pulse-width specifications. The External this category. Reset pin (MCLR) bit (EXTR) in the Reset Control The Trap Reset Flag (TRAPR) bit in the Reset Control (RCON) register is set to indicate the MCLR Reset. (RCON<15>) register is set to indicate the Trap Conflict Reset. Refer to Section7.0 “Interrupt Controller” for 6.5.1 EXTERNAL SUPERVISORY more information on Trap Conflict Resets. CIRCUIT Many systems have external supervisory circuits that 6.9 Configuration Mismatch Reset generate Reset signals to reset multiple devices in the system. This External Reset signal can be directly To maintain the integrity of the Peripheral Pin Select connected to the MCLR pin to reset the device when Control registers, they are constantly monitored with the rest of the system is reset. shadow registers in hardware. If an unexpected change in any of the registers occurs (such as cell 6.5.2 INTERNAL SUPERVISORY CIRCUIT disturbances caused by ESD or other external events), a Configuration Mismatch Reset occurs. When using the internal power supervisory circuit to reset the device, the External Reset pin (MCLR) should The Configuration Mismatch Flag (CM) bit in the Reset be tied directly or resistively to VDD. In this case, the Control (RCON<9>) register is set to indicate the MCLR pin will not be used to generate a Reset. The Configuration Mismatch Reset. Refer to Section10.0 External Reset pin (MCLR) does not have an internal “I/O Ports” for more information on the Configuration pull-up and must not be left unconnected. Mismatch Reset. Note: The Configuration Mismatch feature and 6.6 Software RESET Instruction (SWR) associated Reset flag is not available on Whenever the RESET instruction is executed, the device all devices. will assert SYSRST, placing the device in a special Reset state. This Reset state will not re-initialize the 6.10 Illegal Condition Device Reset clock. The clock source in effect prior to the RESET instruction will remain as the source. SYSRST is An Illegal Condition Device Reset occurs due to the released at the next instruction cycle and the Reset following sources: vector fetch will commence. • Illegal Opcode Reset The Software RESET (Instruction) Flag (SWR) bit in the • Uninitialized W Register Reset Reset Control (RCON<6>) register is set to indicate the • Security Reset Software Reset. The Illegal Opcode or Uninitialized W Access Reset Flag (IOPUWR) bit in the Reset Control (RCON<14>) 6.7 Watchdog Timer Time-out Reset register is set to indicate the Illegal Condition Device (WDTO) Reset. Whenever a Watchdog Timer Time-out Reset occurs, 6.10.1 ILLEGAL OPCODE RESET the device will asynchronously assert SYSRST. The clock source will remain unchanged. A WDT time-out A device Reset is generated if the device attempts to during Sleep or Idle mode will wake-up the processor, execute an illegal opcode value that is fetched from but will not reset the processor. program memory. The Watchdog Timer Time-out Flag (WDTO) bit in the The Illegal Opcode Reset function can prevent the Reset Control (RCON<4>) register is set to indicate the device from executing program memory sections that Watchdog Timer Reset. Refer to Section23.4 are used to store constant data. To take advantage of “Watchdog Timer (WDT)” for more information on the the Illegal Opcode Reset, use only the lower 16 bits of Watchdog Timer Reset. each program memory section to store the data values. The upper 8 bits should be programmed with 0x3F, which is an illegal opcode value.  2011-2014 Microchip Technology Inc. DS70000652F-page 93

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 6.10.2 UNINITIALIZED W REGISTER 6.11 Using the RCON Status Bits RESET The user application can read the Reset Control Any attempts to use the Uninitialized W register as an (RCON) register after any device Reset to determine Address Pointer will reset the device. The W register the cause of the Reset. array (with the exception of W15) is cleared during all Resets and is considered uninitialized until written to. Note: The status bits in the RCON register should be cleared after they are read so 6.10.3 SECURITY RESET that the next RCON register value after a device Reset will be meaningful. If a Program Flow Change (PFC) or Vector Flow Change (VFC) targets a restricted location in a Table6-3 provides a summary of Reset flag bit protected segment (Boot and Secure Segment), that operation. operation will cause a Security Reset. The PFC occurs when the Program Counter is reloaded as a result of a Call, Jump, Computed Jump, Return, Return from Subroutine or other form of branch instruction. The VFC occurs when the Program Counter is reloaded with an interrupt or trap vector. TABLE 6-3: RESET FLAG BIT OPERATION Flag Bit Set by: Cleared by: TRAPR (RCON<15>) Trap conflict event POR, BOR IOPWR (RCON<14>) Illegal opcode or uninitialized POR, BOR W register access or Security Reset CM (RCON<9>) Configuration Mismatch POR, BOR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET instruction POR, BOR WDTO (RCON<4>) WDT Time-out PWRSAV instruction, CLRWDT instruction, POR, BOR SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR, BOR IDLE (RCON<2>) PWRSAV #IDLE instruction POR, BOR BOR (RCON<1>) POR, BOR — POR (RCON<0>) POR — Note: All Reset flag bits can be set or cleared by user software. DS70000652F-page 94  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 7.0 INTERRUPT CONTROLLER Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the Note 1: This data sheet summarizes the features of vector table. Lower addresses generally have a higher the dsPIC33FJ16(GP/MC)101/102 and natural priority. For example, the interrupt associated dsPIC33FJ32(GP/MC)101/102/104 family with Vector 0 will take priority over interrupts at any devices. It is not intended to be a compre- other vector address. hensive reference source. To complement dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/ the information in this data sheet, refer to MC)101/102/104 devices implement up to 26 unique “Interrupts (Part IV)” (DS70300) in the interrupts and 4 nonmaskable traps. These are “dsPIC33/PIC24 Family Reference Man- summarized in Table7-1 and Table7-2. ual”, which is available on the Microchip web site (www.microchip.com). 7.1.1 ALTERNATE INTERRUPT VECTOR 2: Some registers and associated bits TABLE described in this section may not be The Alternate Interrupt Vector Table (AIVT) is located available on all devices. Refer to after the IVT, as shown in Figure7-1. Access to the AIVT Section4.0 “Memory Organization” in is provided by the ALTIVT control bit (INTCON2<15>). If this data sheet for device-specific register the ALTIVT bit is set, all interrupt and exception and bit information. processes use the alternate vectors instead of the default vectors. The alternate vectors are organized in The interrupt controller reduces the numerous periph- the same manner as the default vectors. eral interrupt request signals to a single interrupt request signal to the dsPIC33FJ16(GP/MC)101/102 The AIVT supports debugging by providing a way to and dsPIC33FJ32(GP/MC)101/102/104 family CPU. It switch between an application and a support environ- has the following features: ment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching • Up to eight processor exceptions and software traps between applications to facilitate evaluation of different • Seven user-selectable priority levels software algorithms at run time. If the AIVT is not • Interrupt Vector Table (IVT) with up to 118 vectors needed, the AIVT should be programmed with the • A unique vector for each interrupt or exception same addresses used in the IVT. source • Fixed priority within a specified user priority level 7.2 Reset Sequence • Alternate Interrupt Vector Table (AIVT) for debug A device Reset is not a true exception because the inter- support rupt controller is not involved in the Reset process. The • Fixed interrupt entry and return latencies dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/ MC)101/102/104 devices clear their registers in 7.1 Interrupt Vector Table response to a Reset, forcing the PC to zero. The Digital Signal Controller then begins program execution at The Interrupt Vector Table (IVT) is shown in Figure7-1. location, 0x000000. A GOTO instruction at the Reset The IVT resides in program memory, starting at location, address can redirect program execution to the 000004h. The IVT contains 126 vectors consisting of appropriate start-up routine. eightnon-maskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own Note: Any unimplemented or unused vector vector. Each interrupt vector contains a 24-bit-wide locations in the IVT and AIVT should be address. The value programmed into each interrupt programmed with the address of a default vector location is the starting address of the associated interrupt handler routine that contains a Interrupt Service Routine (ISR). RESET instruction.  2011-2014 Microchip Technology Inc. DS70000652F-page 95

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 7-1: dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 INTERRUPT VECTOR TABLE Reset – GOTO Instruction 0x000000 Reset – GOTO Address 0x000002 Reserved 0x000004 Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 0x000014 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 0x00007C Interrupt Vector Table (IVT)(1) Interrupt Vector 53 0x00007E ority Interrupt ~Vector 54 0x000080 Pri ~ der ~ Or Interrupt Vector 116 0x0000FC al Interrupt Vector 117 0x0000FE atur Reserved 0x000100 N Reserved 0x000102 g n Reserved si a Oscillator Fail Trap Vector e cr Address Error Trap Vector e D Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 0x000114 Interrupt Vector 1 ~ ~ ~ Alternate Interrupt Vector Table (AIVT)(1) Interrupt Vector 52 0x00017C Interrupt Vector 53 0x00017E Interrupt Vector 54 0x000180 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 0x0001FE Start of Code 0x000200 Note 1: See Table7-1 for the list of implemented interrupt vectors. DS70000652F-page 96  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 7-1: INTERRUPT VECTORS Interrupt Vector Request (IRQ) IVT Address AIVT Address Interrupt Source Number Number 8 0 0x000014 0x000114 INT0 – External Interrupt 0 9 1 0x000016 0x000116 IC1 – Input Capture 1 10 2 0x000018 0x000118 OC1 – Output Compare 1 11 3 0x00001A 0x00011A T1 – Timer1 12 4 0x00001C 0x00011C Reserved 13 5 0x00001E 0x00011E IC2 – Input Capture 2 14 6 0x000020 0x000120 OC2 – Output Compare 2 15 7 0x000022 0x000122 T2 – Timer2 16 8 0x000024 0x000124 T3 – Timer3 17 9 0x000026 0x000126 SPI1E – SPI1 Error 18 10 0x000028 0x000128 SPI1 – SPI1 Transfer Done 19 11 0x00002A 0x00012A U1RX – UART1 Receiver 20 12 0x00002C 0x00012C U1TX – UART1 Transmitter 21 13 0x00002E 0x00012E ADC1 – ADC1 22-23 14-15 0x000030-0x000032 0x000130-0x000132 Reserved 24 16 0x000034 0x000134 SI2C1 – I2C1 Slave Events 25 17 0x000036 0x000136 MI2C1 – I2C1 Master Events 26 18 0x000038 0x000138 CMP – Comparator Interrupt 27 19 0x00003A 0x00013A Change Notification Interrupt 28 20 0x00003C 0x00013C INT1 – External Interrupt 1 29-34 21-26 0x00003E-0x000038 0x00013E-0x000138 Reserved 35 27 0x00004A 0x00014A T4 – Timer4(2) 36 28 0x00004C 0x00014C T5 – Timer5(2) 37 29 0x00004E 0x00014E INT2 – External Interrupt 2 38-44 30-36 0x000050-0x00005C 0x000150-0x00015C Reserved 45 37 0x00005E 0x00015E IC3 – Input Capture 3 46-64 38-56 0x000060-0x000084 0x000160-0x000184 Reserved 65 57 0x000086 0x000186 PWM1 – PWM1 Period Match(1) 66-69 58-61 0x000088-0x00008E 0x000188-0x00018E Reserved 70 62 0x000090 0x000190 RTCC – Real-Time Clock and Calendar 71 63 0x000092 0x000192 FLTA1 – PWM1 Fault A(1) 72 64 0x000094 0x000194 FLTB1 – PWM1 Fault B(3) 73 65 0x000096 0x000196 U1E – UART1 Error 74-84 66-76 0x000098-0x0000AC 0x000198-0x0001AC Reserved 85 77 0x0000AE 0x0001AE CTMU – Charge Time Measurement Unit 86-125 78-117 0x0000B0-0x0000FE 0x0001B0-0x0001FE Reserved Note 1: This interrupt vector is available in dsPIC33FJ(16/32)MC10X devices only. 2: This interrupt vector is available in dsPIC33FJ32(GP/MC)10X devices only. 3: This interrupt vector is available in dsPIC33FJ(16/32)MC102/104 devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 97

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 7-2: TRAP VECTORS Vector Number IVT Address AIVT Address Trap Source 0 0x000004 0x000104 Reserved 1 0x000006 0x000106 Oscillator Failure 2 0x000008 0x000108 Address Error 3 0x00000A 0x00010A Stack Error 4 0x00000C 0x00010C Math Error 5 0x00000E 0x00010E Reserved 6 0x000010 0x000110 Reserved 7 0x000012 0x000112 Reserved 7.3 Interrupt Control and Status 7.3.4 IPCx Registers Registers The IPCx registers are used to set the Interrupt Priority Level (IPL) for each source of interrupt. Each user The dsPIC33FJ16(GP/MC)101/102 and interrupt source can be assigned to one of eight priority dsPIC33FJ32(GP/MC)101/102/104 devices implement levels. a total of 26 registers for the interrupt controller: • INTCON1 7.3.5 INTTREG • INTCON2 The INTTREG register contains the associated • IFSx interrupt vector number and the new CPU Interrupt • IECx Priority Level, which are latched into Vector Number • IPCx (VECNUM<6:0>) and Interrupt Level (ILR<3:0>) bit fields in the INTTREG register. The new Interrupt • INTTREG Priority Level is the priority of the pending interrupt. 7.3.1 INTCON1 AND INTCON2 The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are Global interrupt functions are controlled from INTCON1 listed in Table7-1. For example, the INT0 (External and INTCON2. INTCON1 contains the Interrupt Nest- Interrupt 0) is shown as having Vector Number 8 and a ing Disable (NSTDIS) bit as well as the control and natural order priority of 0. Thus, the INT0IF bit is found status flags for the processor trap sources. The in IFS0<0>, the INT0IE bit in IEC0<0> and the INT0IPx INTCON2 register controls the external interrupt bits in the first positions of IPC0 (IPC0<2:0>). request signal behavior and the use of the Alternate Interrupt Vector Table. 7.3.6 STATUS/CONTROL REGISTERS 7.3.2 IFSx Registers Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers The IFSx registers maintain all of the interrupt request contain bits that control interrupt functionality. flags. Each source of interrupt has a status bit, which is set by the respective peripherals or external signal and • The CPU STATUS Register, SR, contains the is cleared via software. IPL<2:0> bits (SR<7:5>). These bits indicate the current CPU Interrupt Priority Level. The user 7.3.3 IECx Registers application can change the current CPU Interrupt The IECx registers maintain all of the interrupt enable Priority Level by writing to the IPLx bits. bits. These control bits are used to individually enable • The CORCON register contains the IPL3 bit interrupts from the peripherals or external signals. which, together with IPL<2:0>, also indicates the current CPU Interrupt Priority Level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All Interrupt registers are described in Register7-1 through Register7-28 on the following pages. DS70000652F-page 98  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-1: SR: CPU STATUS REGISTER(1) R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: For complete register details, see Register3-1. 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1. REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT DL2 DL1 DL0 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less Note 1: For complete register details, see Register3-2. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.  2011-2014 Microchip Technology Inc. DS70000652F-page 99

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14 OVAERR: Accumulator A Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A bit 13 OVBERR: Accumulator B Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B bit 10 OVATE: Accumulator A Overflow Trap Enable bit 1 = Trap overflow of Accumulator A 0 = Trap is disabled bit 9 OVBTE: Accumulator B Overflow Trap Enable bit 1 = Trap overflow of Accumulator B 0 = Trap is disabled bit 8 COVTE: Catastrophic Overflow Trap Enable bit 1 = Trap on catastrophic overflow of Accumulator A or B is enabled 0 = Trap is disabled bit 7 SFTACERR: Shift Accumulator Error Status bit 1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift bit 6 DIV0ERR: Arithmetic Error Status bit 1 = Math error trap was caused by a divide-by-zero 0 = Math error trap was not caused by a divide-by-zero bit 5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred DS70000652F-page 100  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’  2011-2014 Microchip Technology Inc. DS70000652F-page 101

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Uses Alternate Interrupt Vector Table 0 = Uses standard Interrupt Vector Table (default) bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-3 Unimplemented: Read as ‘0’ bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge DS70000652F-page 102  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 SPI1EIF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 Unimplemented: Read as ‘0’ bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2011-2014 Microchip Technology Inc. DS70000652F-page 103

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70000652F-page 104  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — — INT2IF T5IF(1) T4IF(1) — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 T5IF: Timer5 Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 T4IF: Timer4 Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10-5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 105

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — IC3IF — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-0 Unimplemented: Read as ‘0’ REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 U-0 FLTA1IF(1) RTCIF — — — — PWM1IF(1) — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTA1IF: PWM1 Fault A Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 RTCIF: RTCC Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-10 Unimplemented: Read as ‘0’ bit 9 PWM1IF: PWM1 Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’ Note 1: These bits are available in dsPIC(16/32)MC10X devices only. DS70000652F-page 106  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — CTMUIF — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — U1EIF FLTB1IF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-2 Unimplemented: Read as ‘0’ bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 FLTB1IF: PWM1 Fault B Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: This bit is available in dsPIC(16/32)MC102/104 devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 107

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 SPI1IE: SPI1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 SPI1EIE: SPI1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4 Unimplemented: Read as ‘0’ bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS70000652F-page 108  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — — INT2IE T5IE(1) T4IE(1) — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 T5IE: Timer5 Interrupt Enable bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 T4IE: Timer4 Interrupt Enable bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10-5 Unimplemented: Read as ‘0’ bit 4 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 CMIE: Comparator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 109

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — IC3IE — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4-0 Unimplemented: Read as ‘0’ REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 U-0 FLTA1IE(1) RTCIE — — — — PWM1IE(1) — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTA1IE: PWM1 Fault A Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 RTCIE: RTCC Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13-10 Unimplemented: Read as ‘0’ bit 9 PWM1IE: PWM1 Interrupt Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8-0 Unimplemented: Read as ‘0’ Note 1: These bits are available in dsPIC(16/32)MC10X devices only. DS70000652F-page 110  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — CTMUIE — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — U1EIE FLTB1IE(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 FLTB1IE: PWM1 Fault B Interrupt Enable bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: This bit is available in dsPIC(16/32)MC102/104 devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 111

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS70000652F-page 112  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC2IP2 IC2IP1 IC2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2011-2014 Microchip Technology Inc. DS70000652F-page 113

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS70000652F-page 114  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2011-2014 Microchip Technology Inc. DS70000652F-page 115

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 CMIP<2:0>: Comparator Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS70000652F-page 116  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled REGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — T4IP2(1) T4IP1(1) T4IP0(1) — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’ Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 117

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2(1) T5IP1(1) T5IP0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only. DS70000652F-page 118  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 7-23: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC3IP2 IC3IP1 IC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 IC3IP<2:0>: External Interrupt 3 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ REGISTER 7-24: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — PWM1IP2(1) PWM1IP1(1) PWM1IP0(1) — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PWM1IP<2:0>: PWM1 Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: These bits are available in dsPIC(16/32)MC10X devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 119

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 7-25: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — FLTA1IP2(1) FLTA1IP1(1) FLTA1IP0(1) — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 FLTA1IP<2:0>: PWM1 Fault A Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: RTCC Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ Note 1: These bits are available in dsPIC(16/32)MC10X devices only. DS70000652F-page 120  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 7-26: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — U1EIP2 U1EIP1 U1EIP0 — FLTB1IP2(1) FLTB1IP1(1) FLTB1IP0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 FLTB1IP<2:0>: PWM1 Fault B Interrupt Priority bits(1) 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Note 1: These bits are available in dsPIC(16/32)MC102/104 devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 121

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 7-27: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CTMUIP2 CTMUIP1 CTMUIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70000652F-page 122  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 7-28: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt vector pending is Number 135 • • • 0000001 = Interrupt vector pending is Number 9 0000000 = Interrupt vector pending is Number 8  2011-2014 Microchip Technology Inc. DS70000652F-page 123

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 7.4 Interrupt Setup Procedures 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, 7.4.1 INITIALIZATION except that the appropriate trap status flag in the To configure an interrupt source at initialization: INTCON1 register must be cleared to avoid re-entry into the TSR. 1. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. 7.4.4 INTERRUPT DISABLE 2. Select the user-assigned priority level for the interrupt source by writing the control bits into All user interrupts can be disabled using this the appropriate IPCx register. The priority level procedure: will depend on the specific application and type 1. Push the current SR value onto the software of interrupt source. If multiple priority levels are stack using the PUSH instruction. not desired, the IPCx register control bits for all 2. Force the CPU to Priority Level 7 by inclusive enabled interrupt sources can be programmed ORing the value OEh with SRL. to the same non-zero value. To enable user interrupts, the POP instruction can be Note: At a device Reset, the IPCx registers used to restore the previous SR value. are initialized such that all user Note: Only user interrupts with a priority level of interrupt sources are assigned to 7 or lower can be disabled. Trap sources Interrupt Priority Level 4. (Level 8-Level 15) cannot be disabled. 3. Clear the interrupt flag status bit associated with The DISI instruction provides a convenient way to the peripheral in the associated IFSx register. disable interrupts of Priority Levels 1-6 for a fixed 4. Enable the interrupt source by setting the inter- period of time. Level 7 interrupt sources are not rupt enable control bit associated with the disabled by the DISI instruction. source in the appropriate IECx register. 7.4.2 INTERRUPT SERVICE ROUTINE The method used to declare an ISR and initialize the IVT with the correct vector address depends on the programming language (C or assembler), and the language development toolsuite used to develop the application. In general, the user application must clear the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, the program will re-enter the ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. DS70000652F-page 124  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 8.0 OSCILLATOR The oscillator system for dsPIC33FJ16(GP/MC)101/ 102 and dsPIC33FJ32(GP/MC)101/102/104 devices CONFIGURATION provides: Note1: This data sheet summarizes the features • External and internal oscillator options as clock of the dsPIC33FJ16(GP/MC)101/102 sources and dsPIC33FJ32(GP/MC)101/102/104 • An on-chip, 4x Phase Lock Loop (PLL) to scale the family devices. It is not intended to be a internal operating frequency to the required system comprehensive reference source. To com- clock frequency plement the information in this data sheet, • An internal FRC oscillator that can also be used with refer to “Oscillator (Part VI)” (DS70644) the PLL, thereby allowing full-speed operation in the “dsPIC33/PIC24 Family Reference without any external clock generation hardware Manual”, which is available from the • Clock switching between various clock sources Microchip web site (www.microchip.com). • Programmable clock postscaler for system power 2: Some registers and associated bits savings described in this section may not be • A Fail-Safe Clock Monitor (FSCM) that detects clock available on all devices. Refer to failure and takes fail-safe measures Section4.0 “Memory Organization” in this data sheet for device-specific register • An Oscillator Control register (OSCCON) and bit information. • Nonvolatile Configuration bits for main oscillator selection A simplified diagram of the oscillator system is shown in Figure8-1. FIGURE 8-1: OSCILLATOR SYSTEM DIAGRAM Primary Oscillator (POSC) OSC1 MS, HS, EC S2 DOZE<2:0> R(1) S3 MSPLL, ECPLL, FRCPLL OSC2 S1 4x PLL S1/S3 ZE FCY(2) O POSCMD<1:0> D FP(2) (To Peripherals) V FRC DI FRCDIVN ÷ 2 Oscillator RC S7 F FOSC FRCDIV<2:0> TUN<5:0> FRCDIV16 ÷ 16 S6 FRC S0 LPRC LPRC S5 Oscillator Secondary Oscillator (SOSC) SOSC SOSCO S4 LPOSCEN SOSCI Clock Fail Clock Switch Reset S7 NOSC<2:0> FNOSC<2:0> WDT, PWRT, FSCM Timer 1 Note1: If the oscillator is used with MS or HS modes, an extended parallel resistor with the value of 1 M must be connected. 2: The term, FP, refers to the clock source for all peripherals, while FCY refers to the clock source for the CPU. Throughout this docu- ment, FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode is used with a Doze ratio of 1:2 or lower.  2011-2014 Microchip Technology Inc. DS70000652F-page 125

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 8.1 CPU Clocking System 8.1.1.4 Low-Power RC The dsPIC33FJ16(GP/MC)101/102 and The Low-Power RC (LPRC) internal oscillator runs at a dsPIC33FJ32(GP/MC)101/102/104 devices provide nominal frequency of 32.768 kHz. It is also used as a seven system clock options: reference clock by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). • Fast RC (FRC) Oscillator • FRC Oscillator with 4x PLL 8.1.1.5 PLL • Primary (MS, HS or EC) Oscillator The clock signals generated by the FRC and primary • Primary Oscillator with 4x PLL oscillators can be optionally applied to an on-chip, 4x • Secondary (LP) Oscillator Phase Lock Loop (PLL) to provide faster output frequencies for device operation. PLL configuration is • Low-Power RC (LPRC) Oscillator described in Section8.1.3 “PLL Configuration”. • FRC Oscillator with postscaler 8.1.2 SYSTEM CLOCK SELECTION 8.1.1 SYSTEM CLOCK SOURCES The oscillator source used at a device Power-on Reset 8.1.1.1 Fast RC event is selected using Configuration bit settings. The Oscillator Configuration bit settings are located in the The Fast RC (FRC) internal oscillator runs at a nominal Configuration registers in the program memory. (Refer frequency of 7.37 MHz. User software can tune the to Section23.1 “Configuration Bits” for further FRC frequency. User software can optionally specify a details.) The initial Oscillator Selection Configuration factor (ranging from 1:2 to 1:256) by which the FRC bits, FNOSC<2:0> (FOSCSEL<2:0>), and the Primary clock frequency is divided. This factor is selected using Oscillator Mode Select Configuration bits, the FRCDIV<2:0> (CLKDIV<10:8>) bits. POSCMD<1:0> (FOSC<1:0>), select the oscillator The FRC frequency depends on the FRC accuracy source that is used at a Power-on Reset. The FRC (see Table26-18) and the value of the FRC Oscillator primary oscillator is the default (unprogrammed) Tuning register (see Register8-3). selection. 8.1.1.2 Primary The Configuration bits allow users to choose among 12different clock modes, shown in Table8-1. The primary oscillator can use one of the following as its clock source: The output of the oscillator (or the output of the PLL if a PLL mode has been selected) FOSC is divided by 2 to • MS (Crystal): Crystals and ceramic resonators in generate the device instruction clock (FCY) and the the range of 4 MHz to 10 MHz. The crystal is peripheral clock time base (FP). FCY defines the connected to the OSC1 and OSC2 pins. operating speed of the device, and speeds up to • HS (High-Speed Crystal): Crystals in the range of 16MHz are supported by the dsPIC33FJ16(GP/ 10 MHz to 32 MHz. The crystal is connected to MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 the OSC1 and OSC2 pins. architecture. • EC (External Clock): The external clock signal is directly applied to the OSC1 pin. Instruction execution speed or device operating frequency, FCY, is given by: 8.1.1.3 Secondary EQUATION 8-1: DEVICE OPERATING The secondary (LP) oscillator is designed for low power FREQUENCY and uses a 32.768 kHz crystal or ceramic resonator. The LP oscillator uses the SOSCI and SOSCO pins. FOSC FCY = ------------- 2 DS70000652F-page 126  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 8.1.3 PLL CONFIGURATION EQUATION 8-2: MS WITH PLL MODE EXAMPLE The primary oscillator and internal FRC oscillator can optionally use an on-chip, 4x PLL to obtain higher FOSC 1 speeds of operation. FCY = = (8000000 • 4) = 16 MIPS 2 2 For example, suppose an 8 MHz crystal is being used with the selected oscillator mode of MS with PLL. This provides a FOSC of 8 MHz * 4 = 32 MHz. The resultant device operating speed is 32/2 = 16 MIPS. TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator See Oscillator Mode POSCMD<1:0> FNOSC<2:0> Source Note Fast RC Oscillator with Divide-by-n (FRCDIVN) Internal xx 111 1, 2 Fast RC Oscillator with Divide-by-16 (FRCDIV16) Internal xx 110 1 Low-Power RC Oscillator (LPRC) Internal xx 101 1 Secondary (Timer1) Oscillator (SOSC) Secondary xx 100 1 Primary Oscillator (MS) with PLL (MSPLL) Primary 01 011 Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1 Primary Oscillator (HS) Primary 10 010 Primary Oscillator (MS) Primary 01 010 Primary Oscillator (EC) Primary 00 010 1 Fast RC Oscillator (FRC) with Divide-by-n and Internal xx 001 1 PLL (FRCPLL) Fast RC Oscillator (FRC) Internal xx 000 1 Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device.  2011-2014 Microchip Technology Inc. DS70000652F-page 127

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 8.2 Oscillator Control Registers REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y — COSC2 COSC1 COSC0 — NOSC2(2) NOSC1(2) NOSC0(2) bit 15 bit 8 R/W-0 R/W-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0 CLKLOCK IOLOCK LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 Legend: C = Clearable bit y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only) 111 = Fast RC Oscillator (FRC) with Divide-by-n 110 = Fast RC Oscillator (FRC) with Divide-by-16 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (MS, EC) with PLL 010 = Primary Oscillator (MS, HS, EC) 001 = Fast RC Oscillator (FRC) with Divide-by-n and PLL (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2) 111 = Fast RC Oscillator (FRC) with Divide-by-n 110 = Fast RC Oscillator (FRC) with Divide-by-16 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (MS, EC) with PLL 010 = Primary Oscillator (MS, HS, EC) 001 = Fast RC Oscillator (FRC) with Divide-by-n and PLL (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 7 CLKLOCK: Clock Lock Enable bit If Clock Switching is Enabled and FSCM is Disabled (FCKSM<1:0> (FOSC<7:6>) = 0b01): 1 = Clock switching is disabled, system clock source is locked 0 = Clock switching is enabled, system clock source can be modified by clock switching bit 6 IOLOCK: Peripheral Pin Select Lock bit 1 = Peripheral Pin Select is locked, a write to Peripheral Pin Select registers is not allowed 0 = Peripheral Pin Select is not locked, a write to Peripheral Pin Select registers is allowed bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled bit 4 Unimplemented: Read as ‘0’ Note 1: Writes to this register require an unlock sequence. Refer to “Oscillator (Part VI)” (DS70644) in the “dsPIC33/PIC24 Family Reference Manual” for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transitional clock source between the two PLL modes. DS70000652F-page 128  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED) bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected a clock failure 0 = FSCM has not detected a clock failure bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enables secondary oscillator 0 = Disables secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Requests oscillator switch to selection specified by the NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Writes to this register require an unlock sequence. Refer to “Oscillator (Part VI)” (DS70644) in the “dsPIC33/PIC24 Family Reference Manual” for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transitional clock source between the two PLL modes.  2011-2014 Microchip Technology Inc. DS70000652F-page 129

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 ROI DOZE2(2,3) DOZE1(2,3) DOZE0(2,3) DOZEN(1,2,3) FRCDIV2 FRCDIV1 FRCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits(2,3) 111 = FCY/128 110 = FCY/64 101 = FCY/32 100 = FCY/16 011 = FCY/8 (default) 010 = FCY/4 001 = FCY/2 000 = FCY/1 bit 11 DOZEN: DOZE Mode Enable bit(1,2,3) 1 = DOZE<2:0> bits field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock/peripheral clock ratio is forced to 1:1 bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits 111 = FRC divide-by-256 110 = FRC divide-by-64 101 = FRC divide-by-32 100 = FRC divide-by-16 011 = FRC divide-by-8 010 = FRC divide-by-4 001 = FRC divide-by-2 000 = FRC divide-by-1 (default) bit 7-0 Unimplemented: Read as ‘0’ Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. 2: If DOZEN = 1, writes to DOZE<2:0> are ignored. 3: If DOZE<2:0> = 000, the DOZEN bit cannot be set by the user; writes are ignored. DS70000652F-page 130  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits 011111 = Maximum frequency deviation of 1.453% (7.477 MHz) 011110 = Center frequency + 1.406% (7.474 MHz) • • • 000001 = Center frequency + 0.047% (7.373 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency – 0.047% (7.367 MHz) • • • 100001 = Center frequency – 1.453% (7.263 MHz) 100000 = Minimum frequency deviation of -1.5% (7.259 MHz)  2011-2014 Microchip Technology Inc. DS70000652F-page 131

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 8.3 Clock Switching Operation Once the basic sequence is completed, the system clock hardware responds automatically as follows: Applications are free to switch among any of the four 1. The clock switching hardware compares the clock sources (Primary, LP, FRC and LPRC) under COSCx status bits with the new value of the software control at any time. To limit the possible side NOSCx control bits. If they are the same, the effects of this flexibility, dsPIC33FJ16(GP/MC)101/102 clock switch is a redundant operation. In this and dsPIC33FJ32(GP/MC)101/102/104 devices have case, the OSWEN bit is cleared automatically a safeguard lock built into the switch process. and the clock switch is aborted. Note: Primary Oscillator mode has three different 2. If a valid clock switch has been initiated, the LOCK submodes (MS, HS and EC), which are and CF (OSCCON<5,3>) status bits are cleared. determined by the POSCMD<1:0> Config- 3. The new oscillator is turned on by the hardware uration bits. While an application can if it is not currently running. If a crystal oscillator switch to and from Primary Oscillator must be turned on, the hardware waits until the mode in software, it cannot switch among Oscillator Start-up Timer (OST) expires. If the the different primary submodes without new source is using the PLL, the hardware waits reprogramming the device. until a PLL lock is detected (LOCK = 1). 4. The hardware waits for 10 clock cycles from the new 8.3.1 ENABLING CLOCK SWITCHING clock source and then performs the clock switch. To enable clock switching, the FCKSM1 Configuration bit 5. The hardware clears the OSWEN bit to indicate a in the FOSC Configuration register must be programmed successful clock transition. In addition, the NOSCx to ‘0’. (Refer to Section23.1 “Configuration Bits” for bit values are transferred to the COSCx status bits. further details.) If the FCKSM1 Configuration bit is unpro- 6. The old clock source is turned off at this time, grammed (‘1’), the clock switching function and Fail-Safe with the exception of LPRC (if WDT or FSCM is Clock Monitor function are disabled. This is the default enabled) or LP (if LPOSCEN remains set). setting. Note1: The processor continues to execute code The NOSCx control bits (OSCCON<10:8>) do not control throughout the clock switching sequence. the clock selection when clock switching is disabled. How- Timing-sensitive code should not be ever, the COSCx bits (OSCCON<14:12>) reflect the clock executed during this time. source selected by the FNOSCx Configuration bits. 2: Direct clock switches between any Pri- The OSWEN control bit (OSCCON<0>) has no effect mary Oscillator mode with PLL and when clock switching is disabled; it is held at ‘0’ at all FRCPLL mode are not permitted. This times. applies to clock switches in either direc- tion. In these instances, the application 8.3.2 OSCILLATOR SWITCHING SEQUENCE must switch to FRC mode as a transition clock source between the two PLL modes. Performing a clock switch requires this basic sequence: 3: Refer to “Oscillator (Part VI)” (DS70644) in the “dsPIC33/PIC24 Family 1. If desired, read the COSC bits Reference Manual” for details. (OSCCON<14:12>) to determine the current oscillator source. 8.4 Fail-Safe Clock Monitor (FSCM) 2. Perform the unlock sequence to allow a write to the OSCCON register high byte. The Fail-Safe Clock Monitor (FSCM) allows the device 3. Write the appropriate value to the NOSCx con- to continue to operate even in the event of an oscillator trol bits (OSCCON<10:8>) for the new oscillator failure. The FSCM function is enabled by programming. source. If the FSCM function is enabled, the LPRC internal 4. Perform the unlock sequence to allow a write to oscillator runs at all times (except during Sleep mode) the OSCCON register low byte. and is not subject to control by the Watchdog Timer. 5. Set the OSWEN bit (OSCCON<0>) to initiate In the event of an oscillator failure, the FSCM the oscillator switch. generates a clock failure trap event and switches the system clock over to the FRC oscillator. Then, the application program can either attempt to restart the oscillator or execute a controlled shutdown. The trap can be treated as a Warm Reset by simply loading the Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. DS70000652F-page 132  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 9.0 POWER-SAVING FEATURES 9.2 Instruction-Based Power-Saving Modes Note1: This data sheet summarizes the features of the dsPIC33FJ16(GP/MC)101/102 dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/ and dsPIC33FJ32(GP/MC)101/102/104 MC)101/102/104 devices have two special power- family devices. It is not intended to be a saving modes that are entered through the execution of comprehensive reference source. To a special PWRSAV instruction. Sleep mode stops clock complement the information in this data operation and halts all code execution. Idle mode halts sheet, refer to “Watchdog Timer and the CPU and code execution, but allows peripheral Power-Saving Modes” (DS70196) in the modules to continue operation. The assembler syntax “dsPIC33/PIC24 Family Reference Man- of the PWRSAV instruction is shown in Example9-1. ual”, which is available from the Microchip Note: SLEEP_MODE and IDLE_MODE are web site (www.microchip.com). constants defined in the assembler 2: Some registers and associated bits include file for the selected device. described in this section may not be Sleep and Idle modes can be exited as a result of an available on all devices. Refer to enabled interrupt, WDT time-out or a device Reset. When Section4.0 “Memory Organization” in the device exits these modes, it is said to wake-up. this data sheet for device-specific register and bit information. 9.2.1 SLEEP MODE The dsPIC33FJ16(GP/MC)101/102 and The following occurs in Sleep mode: dsPIC33FJ32(GP/MC)101/102/104 devices provide • The system clock source is shut down. If an the ability to manage power consumption by selectively on-chip oscillator is used, it is turned off. managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the • The device current consumption is reduced to a number of circuits being clocked constitutes lower minimum, provided that no I/O pin is sourcing consumed power. Devices can manage power current consumption in four different ways: • The Fail-Safe Clock Monitor does not operate, since the system clock source is disabled • Clock Frequency • The LPRC clock continues to run in Sleep mode if • Instruction-Based Sleep and Idle modes the WDT is enabled • Software-Controlled Doze mode • The WDT, if enabled, is automatically cleared • Selective Peripheral Control in Software prior to entering Sleep mode Combinations of these methods can be used to selec- • Some device features or peripherals may continue tively tailor an application’s power consumption while to operate. This includes items such as the Input still maintaining critical application features, such as Change Notification (ICN) on the I/O ports or timing-sensitive communications. peripherals that use an external clock input. • Any peripheral that requires the system clock 9.1 Clock Frequency and Clock source for its operation is disabled Switching The device will wake-up from Sleep mode on any of the dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/ these events: MC)101/102/104 devices allow a wide range of clock • Any interrupt source that is individually enabled frequencies to be selected under application control. If • Any form of device Reset the system clock configuration is not locked, users can • A WDT time-out choose low-power or high-precision oscillators by simply changing the NOSC<2:0> bits (OSCCON<10:8>). The On wake-up from Sleep mode, the processor restarts process of changing a system clock during operation, as with the same clock source that was active when Sleep well as limitations to the process, are discussed in more mode was entered. detail in Section8.0 “Oscillator Configuration”. EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode  2011-2014 Microchip Technology Inc. DS70000652F-page 133

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 9.2.2 IDLE MODE Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core The following occurs in Idle mode: clock speed is determined by the DOZE<2:0> bits • The CPU stops executing instructions. (CLKDIV<14:12>). There are eight possible • The WDT is automatically cleared. configurations, from 1:1 to 1:128, with 1:1 being the • The system clock source remains active. By default setting. default, all peripheral modules continue to operate Programs can use Doze mode to selectively reduce normally from the system clock source, but can power consumption in event-driven applications. This also be selectively disabled (see Section9.4 allows clock-sensitive functions, such as synchronous “Peripheral Module Disable”). communications, to continue without interruption while • If the WDT or FSCM is enabled, the LPRC also the CPU Idles, waiting for something to invoke an remains active. interrupt routine. An automatic return to full-speed CPU operation on interrupts can be enabled by setting the The device will wake from Idle mode on any of these ROI bit (CLKDIV<15>). By default, interrupt events events: have no effect on Doze mode operation. • Any interrupt that is individually enabled For example, suppose the device is operating at • Any device Reset 20MIPS and the UART module has been configured • A WDT time-out for 500 kbps based on this device operating speed. If On wake-up from Idle mode, the clock is reapplied to the device is placed in Doze mode with a clock the CPU and instruction execution will begin (2-4 clock frequency ratio of 1:4, the UART module continues to cycles later), starting with the instruction following the communicate at the required bit rate of 500 kbps, but PWRSAV instruction, or the first instruction in the ISR. the CPU now starts executing instructions at a frequency of 5 MIPS. 9.2.3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS 9.4 Peripheral Module Disable Any interrupt that coincides with the execution of a The Peripheral Module Disable (PMDx) registers PWRSAV instruction is held off until entry into Sleep or provide a method to disable a peripheral module by Idle mode has completed. The device then wakes up stopping all clock sources supplied to that module. from Sleep or Idle mode. When a peripheral is disabled using the appropriate PMDx control bit, the peripheral is in a minimum power 9.3 Doze Mode consumption state. The control and status registers associated with the peripheral are also disabled, so The preferred strategies for reducing power consumption writes to those registers will have no effect and read are changing clock speed and invoking one of the power- values will be invalid. saving modes. In some circumstances, this may not be practical. For example, it may be necessary for an A peripheral module is enabled only if both the application to maintain uninterrupted synchronous associated bit in the PMDx register is cleared and the communication, even while it is doing nothing else. peripheral is supported by the specific dsPIC® DSC Reducing system clock speed can introduce variant. If the peripheral is present in the device, it is communication errors, while using a power-saving mode enabled in the PMDx register by default. can stop communications completely. Note: If a PMDx bit is set, the corresponding Doze mode is a simple and effective alternative method module is disabled after a delay of one to reduce power consumption while the device is still instruction cycle. Similarly, if a PMDx bit is executing code. In this mode, the system clock cleared, the corresponding module is continues to operate from the same source and at the enabled after a delay of one instruction same speed. Peripheral modules continue to be cycle (assuming the module control regis- clocked at the same speed, while the CPU clock speed ters are already configured to enable is reduced. Synchronization between the two clock module operation). domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. DS70000652F-page 134  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 9.5 PMD Control Registers REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 T5MD(1) T4MD(1) T3MD T2MD T1MD — PWM1MD — bit 15 bit 8 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 I2C1MD — U1MD — SPI1MD — — AD1MD(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 T5MD: Timer5 Module Disable bit(1) 1 = Timer5 module is disabled 0 = Timer5 module is enabled bit 14 T4MD: Timer4 Module Disable bit(1) 1 = Timer4 module is disabled 0 = Timer4 module is enabled bit 13 T3MD: Timer3 Module Disable bit 1 = Timer3 module is disabled 0 = Timer3 module is enabled bit 12 T2MD: Timer2 Module Disable bit 1 = Timer2 module is disabled 0 = Timer2 module is enabled bit 11 T1MD: Timer1 Module Disable bit 1 = Timer1 module is disabled 0 = Timer1 module is enabled bit 10 Unimplemented: Read as ‘0’ bit 9 PWM1MD: PWM1 Module Disable bit 1 = PWM1 module is disabled 0 = PWM1 module is enabled bit 8 Unimplemented: Read as ‘0’ bit 7 I2C1MD: I2C1 Module Disable bit 1 = I2C1 module is disabled 0 = I2C1 module is enabled bit 6 Unimplemented: Read as ‘0’ bit 5 U1MD: UART1 Module Disable bit 1 = UART1 module is disabled 0 = UART1 module is enabled bit 4 Unimplemented: Read as ‘0’ Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only. 2: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode.  2011-2014 Microchip Technology Inc. DS70000652F-page 135

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED) bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2-1 Unimplemented: Read as ‘0’ bit 0 AD1MD: ADC1 Module Disable bit(2) 1 = ADC1 module is disabled 0 = ADC1 module is enabled Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only. 2: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode. REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — IC3MD IC2MD IC1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 IC3MD: Input Capture 3 Module Disable bit 1 = Input Capture 3 module is disabled 0 = Input Capture 3 module is enabled bit 9 IC2MD: Input Capture 2 Module Disable bit 1 = Input Capture 2 module is disabled 0 = Input Capture 2 module is enabled bit 8 IC1MD: Input Capture 1 Module Disable bit 1 = Input Capture 1 module is disabled 0 = Input Capture 1 module is enabled bit 7-2 Unimplemented: Read as ‘0’ bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled DS70000652F-page 136  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — CMPMD RTCCMD — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Comparator Module Disable bit 1 = Comparator module is disabled 0 = Comparator module is enabled bit 9 RTCCMD: RTCC Module Disable bit 1 = RTCC module is disabled 0 = RTCC module is enabled bit 8-0 Unimplemented: Read as ‘0’ REGISTER 9-4: PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 — — — — — CTMUMD — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2 CTMUMD: CTMU Module Disable bit 1 = CTMU module is disabled 0 = CTMU module is enabled bit 1-0 Unimplemented: Read as ‘0’  2011-2014 Microchip Technology Inc. DS70000652F-page 137

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70000652F-page 138  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 10.0 I/O PORTS When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as Note1: This data sheet summarizes the features a general purpose output pin is disabled. The I/O pin of the dsPIC33FJ16(GP/MC)101/102 can be read, but the output driver for the parallel port bit and dsPIC33FJ32(GP/MC)101/102/104 is disabled. If a peripheral is enabled, but the peripheral family devices. It is not intended to be a is not actively driving a pin, that pin can be driven by a comprehensive reference source. To com- port. plement the information in this data sheet, All port pins have three registers directly associated refer to “I/O Ports” (DS70193) in the with their operation as digital I/O. The Data Direction “dsPIC33/PIC24 Family Reference Man- register (TRISx) determines whether the pin is an input ual”, which is available from the Microchip or an output. If the data direction bit is a ‘1’, the pin is web site (www.microchip.com). an input. All port pins are defined as inputs after a 2: Some registers and associated bits Reset. Reads from the Output Latch (LATx) register described in this section may not be read the latch. Writes to the Output Latch register write available on all devices. Refer to the latch. Reads from the port (PORTx) read the port Section4.0 “Memory Organization” in pins, while writes to the port pins write the latch. this data sheet for device-specific register Any bit and its associated data and control registers and bit information. that is not valid for a particular device will be disabled. This means the corresponding LATx and TRISx All of the device pins (except VDD, VSS, MCLR and registers and the port pin will read as zeros. OSC1/CLKI) are shared among the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt When a pin is shared with another peripheral or Trigger inputs for improved noise immunity. function that is defined as an input only, it is nevertheless regarded as a dedicated port because 10.1 Parallel I/O (PIO) Ports there is no other competing source of outputs. Generally a parallel I/O port that shares a pin with a peripheral is subservient to the peripheral. The peripheral’s output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through,” in which a port’s digital output can drive the input of a peripheral that shares the same pin. Figure10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected.  2011-2014 Microchip Technology Inc. DS70000652F-page 139

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data Read TRIS 0 Data Bus D Q I/O Pin WR TRIS CK TRIS Latch D Q WR LAT + CK WR PORT Data Latch Read LAT Input Data Read PORT DS70000652F-page 140  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 10.1.1 OPEN-DRAIN CONFIGURATION 10.2.1 I/O PORT WRITE/READ TIMING In addition to the PORTx, LATx and TRISx registers One instruction cycle is required between a port for data control, some port pins can also be direction change or port write operation and a read individually configured for either digital or open-drain operation of the same port. Typically this instruction output. This is controlled by the Open-Drain Control would be a NOP. A demonstration is shown in register, ODCx, associated with each port. Setting any Example10-1. of the bits configures the corresponding pin to act as an open-drain output. 10.3 Input Change Notification (ICN) The open-drain feature allows the generation of The Input Change Notification function of the I/O outputs higher than VDD (e.g., 5V) on any desired 5V ports allows the dsPIC33FJ16(GP/MC)101/102 and tolerant pins by using external pull-up resistors. The dsPIC33FJ32(GP/MC)101/102/104 devices to gener- maximum open-drain voltage allowed is the same as ate interrupt requests to the processor in response to a the maximum VIH specification. Change-of-State (COS) on selected input pins. This See “Pin Diagrams” for the available pins and their feature can detect input Change-of-States, even in functionality. Sleep mode, when the clocks are disabled. Depending on the device pin count, up to 21 external signals (CNx 10.2 Configuring Analog Port Pins pin) can be selected (enabled) for generating an interrupt request on a Change-of-State. The AD1PCFGL and TRISx registers control the oper- Four control registers are associated with the CN ation of the Analog-to-Digital port pins. The port pins module. The CNEN1 and CNEN2 registers contain the that are to function as analog inputs must have their interrupt enable control bits for each of the CN input corresponding TRISx bit set (input). If the TRISx bit is pins. Setting any of these bits enables a CN interrupt cleared (output), the digital output level (VOH or VOL) for the corresponding pins. will be converted. Each CN pin also has a weak pull-up connected to it. The AD1PCFGL register has a default value of 0x0000; The pull-ups act as a current source connected to the therefore, all pins that share ANx functions are analog pin and eliminate the need for external resistors when (not digital) by default. push button or keypad devices are connected. The When the PORTx register is read, all pins configured as pull-ups are enabled separately using the CNPU1 and analog input channels will read as cleared (a low level). CNPU2 registers, which contain the control bits for Pins configured as digital inputs will not convert an each of the CN pins. Setting any of the control bits analog input. Analog levels on any pin defined as a enables the weak pull-ups for the corresponding pins. digital input (including the ANx pins) can cause the Note: Pull-ups on Input Change Notification pins input buffer to consume current that exceeds the should always be disabled when the port device specifications. pin is configured as a digital output. EXAMPLE 10-1: PORT WRITE/READ EXAMPLE MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs MOV W0, TRISBB ; and PORTB<7:0> as outputs NOP ; Delay 1 cycle btss PORTB, #13 ; Next Instruction  2011-2014 Microchip Technology Inc. DS70000652F-page 141

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 10.4 Peripheral Pin Select (PPS) 10.4.2.1 Input Mapping Peripheral Pin Select configuration enables peripheral The inputs of the Peripheral Pin Select options are set selection and placement on a wide range of I/O mapped on the basis of the peripheral. A control pins. By increasing the pinout options available on a register associated with a peripheral dictates the pin it particular device, programmers can better tailor the will be mapped to. The RPINRx registers are used to microcontroller to their entire application, rather than configure peripheral input mapping (see Register10-1 trimming the application to fit the device. through Register10-10). Each register contains sets of 5-bit fields, with each set associated with one of the The Peripheral Pin Select configuration feature remappable peripherals. Programming a given operates over a fixed subset of digital I/O pins. Pro- peripheral’s bit field with an appropriate 5-bit value grammers can independently map the input and/or maps the RPn pin with that value to that peripheral. output of most digital peripherals to any one of these For any given device, the valid range of values for any I/O pins. Peripheral Pin Select is performed in soft- bit field corresponds to the maximum number of ware and generally does not require the device to be Peripheral Pin Selections supported by the device. reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the Figure10-2 Illustrates remappable pin selection for peripheral mapping, once it has been established. U1RX input. Note: For input mapping only, the Peripheral Pin 10.4.1 AVAILABLE PINS Select (PPS) functionality does not have The Peripheral Pin Select feature is used with a range priority over the TRISx settings. There- of up to 16 pins. The number of available pins depends fore, when configuring the RPx pin for on the particular device and its pin count. Pins that input, the corresponding bit in the TRISx support the Peripheral Pin Select feature include the register must also be configured for input designation “RPn” in their full pin designation, where (i.e., set to ‘1’). “RP” designates a remappable peripheral and “n” is the remappable pin number. FIGURE 10-2: REMAPPABLE MUX INPUT FOR U1RX 10.4.2 CONTROLLING PERIPHERAL PIN SELECT U1RXR<4:0> Peripheral Pin Select features are controlled through two sets of Special Function Registers: one to map 0 peripheral inputs and one to map outputs. Because they are separately controlled, a particular peripheral’s RP0 input and output (if the peripheral has both) can be placed on any selectable function pin without 1 constraint. RP1 U1RX Input The association of a peripheral to a peripheral select- to Peripheral 2 able pin is handled in two different ways, depending on whether an input or output is being mapped. RP2 25 RP25 DS70000652F-page 142  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Configuration Input Name Function Name Register Bits External Interrupt 1 INT1 RPINR0 INT1R<4:0> External Interrupt 2 INT2 RPINR1 INT2R<4:0> Timer2 External Clock T2CK RPINR3 T2CKR<4:0> Timer3 External Clock T3CK RPINR3 T3CKR<4:0> Timer4 External Clock T4CK RPINR4 T4CKR<4:0>(2) Timer5 External Clock T5CK RPINR4 T5CKR<4:0>(2) Input Capture 1 IC1 RPINR7 IC1R<4:0> Input Capture 2 IC2 RPINR7 IC2R<4:0> Input Capture 3 IC3 RPINR8 IC3R<4:0> Output Compare Fault A OCFA RPINR11 OCFAR<4:0> UART1 Receive U1RX RPINR18 U1RXR<4:0> UART1 Clear-to-Send U1CTS RPINR18 U1CTSR<4:0> SDI1 SPI Data Input 1 SDI1 RPINR20 SDI1R<4:0>(2) SCK1 SPI Clock Input 1 SCK1 RPINR20 SCK1R<4:0>(2) SPI1 Slave Select Input SS1 RPINR21 SS1R<4:0>(2) Note 1: Unless otherwise noted, all inputs use the Schmitt input buffers. 2: These bits are available in dsPIC33FJ32(GP/MC)10X devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 143

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 10.4.2.2 Output Mapping FIGURE 10-3: MULTIPLEXING OF REMAPPABLE OUTPUT In contrast to the inputs, the outputs of the Peripheral FOR RPn Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a RPnR<4:0> particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control out- Default put mapping. Like the RPINRx registers, each register 0 contains sets of 5-bit fields, with each set associated U1TX Output Enable 3 with one RPn pin (see Register10-11 through U1RTS Output Enable 4 Register10-23). The value of the bit field corresponds Output Enable to one of the peripherals and that peripheral’s output is mapped to the pin (see Table10-2 and Figure10-3). The list of peripherals for output mapping also includes a null value of ‘00000’ because of the mapping OC2 Output Enable 19 technique. This permits any given pin to remain unconnected from the output of any of the pin selectable peripherals. Default 0 U1TX Output 3 U1RTS Output 4 Output Data RPn OC2 Output 19 TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn) Function RPnR<4:0> Output Name NULL 00000 RPn tied to Default Port Pin C1OUT 00001 RPn tied to Comparator 1 Output C2OUT 00010 RPn tied to Comparator 2 Output U1TX 00011 RPn tied to UART1 Transmit U1RTS 00100 RPn tied to UART1 Ready-to-Send SCK1 01000 RPn tied to SPI Clock(1) SDO1 00111 RPn tied to SPI Data Output(1) SS1 01001 RPn tied to SPI1 Slave Select Output(1) OC1 10010 RPn tied to Output Compare 1 OC2 10011 RPn tied to Output Compare 2 CTPLS 11101 RPn tied to CTMU Pulse Output C3OUT 11110 RPn tied to Comparator 3 Output Note 1: This function is available in dsPIC33FJ32(GP/MC)10X devices only. DS70000652F-page 144  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 10.4.3 CONTROLLING CONFIGURATION 10.4.3.2 Continuous State Monitoring CHANGES In addition to being protected from direct writes, the Because peripheral remapping can be changed during contents of the RPINRx and RPORx registers are run time, some restrictions on peripheral remapping are constantly monitored in hardware by shadow registers. needed to prevent accidental configuration changes. If an unexpected change in any of the registers occurs dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/ (such as cell disturbances caused by ESD or other MC)101/102/104 devices include three features to external events), a Configuration Mismatch Reset will prevent alterations to the peripheral map: be triggered. • Control register lock sequence 10.4.3.3 Configuration Bit Pin Select Lock • Continuous state monitoring As an additional level of safety, the device can be • Configuration bit pin select lock configured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY 10.4.3.1 Control Register Lock (FOSC<5>) Configuration bit blocks the IOLOCK bit Under normal operation, writes to the RPINRx and from being cleared after it has been set once. If RPORx registers are not allowed. Attempted writes IOLOCK remains set, the register unlock procedure will appear to execute normally, but the contents of the not execute and the Peripheral Pin Select Control registers remain unchanged. To change these regis- registers cannot be written to. The only way to clear the ters, they must be unlocked in hardware. The register bit and re-enable peripheral remapping is to perform a lock is controlled by the IOLOCK bit (OSCCON<6>). device Reset. Setting IOLOCK prevents writes to the control In the default (unprogrammed) state, IOL1WAY is set, registers; clearing IOLOCK allows writes. restricting users to one write session. Programming To set or clear IOLOCK, a specific command sequence IOL1WAY allows user applications unlimited access must be executed: (with the proper use of the unlock sequence) to the 1. Write 0x46 to OSCCON<7:0>. Peripheral Pin Select registers. 2. Write 0x57 to OSCCON<7:0>. 3. Clear (or set) IOLOCK as a single operation. Note: MPLAB® C30 provides built-in C language functions for unlocking the OSCCON register: __builtin_write_OSCCONL(value) __builtin_write_OSCCONH(value) See MPLAB IDE Help for more information. Unlike the similar sequence with the oscillator’s LOCK bit, IOLOCK remains in one state until changed. This allows all of the Peripheral Pin Selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence.  2011-2014 Microchip Technology Inc. DS70000652F-page 145

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 10.5 I/O Helpful Tips 4. Each CN pin has a configurable internal weak pull-up resistor. The pull-ups act as a current 1. In some cases, certain pins, as defined in source connected to the pin and eliminates the Section26.0 “Electrical Characteristics”, need for external resistors in certain applica- Table26-11 under “Injection Current”, have tions. The internal pull-up is to ~(VDD – 0.8), not internal protection diodes to VDD and VSS. The VDD. This is still above the minimum VIH of term, “Injection Current”, is also referred to as CMOS and TTL devices. “Clamp Current”. On designated pins, with suffi- 5. When driving LEDs directly, the I/O pin can cient external current limiting precautions by the source or sink more current than what is specified user, I/O pin input voltages are allowed to be in the VOH/IOH and VOL/IOL DC characteristic greater or less than the data sheet absolute specification. The respective IOH and IOL current maximum ratings with nominal VDD, with respect rating only applies to maintaining the correspond- to the VSS and VDD supplies. Note that when the ing output at or above the VOH and at or below the user application forward biases either of the high VOL levels. However, for LEDs unlike digital or low side internal input clamp diodes, that the inputs of an externally connected device, they are resulting current being injected into the device, not governed by the same minimum VIH/VIL that is clamped internally by the VDD and VSS levels. An I/O pin output can safely sink or source power rails, may affect the ADC accuracy by any current less than that listed in the absolute four to six counts. maximum rating section of the data sheet. For 2. I/O pins that are shared with any analog input pin, example: (i.e., ANx), are always analog pins by default after any Reset. Consequently, any pin(s) configured VOH = 2.4v @ IOH = -6 mA and VDD = 3.3V as an analog input pin, automatically disables the The maximum output current sourced by any 6mA digital input pin buffer. As such, any attempt to I/O pin = 15 mA. read a digital input pin will always return a ‘0’ LED source current < 15 mA is technically regardless of the digital logic level on the pin if the permitted. Refer to the VOH/IOH specifications in analog pin is configured. To use a pin as a digital Section26.0 “Electrical Characteristics” for I/O pin on a shared ANx pin, the user application additional information. needs to configure the ADC1 Port Configuration Low (AD1PCFGL) register in the ADC module, by 10.6 I/O Resources setting the appropriate bit that corresponds to that I/O port pin, to a ‘1’. On devices with more than Many useful resources are provided on the main one ADC, both analog pin configurations for both product page of the Microchip web site for the devices ADC modules must be configured as a digital I/O listed in this data sheet. This product page, which can pin for that pin to function as a digital I/O pin. be accessed using this link, contains the latest updates Note: Although it is not possible to use a digital and additional information. input pin when its analog function is Note: In the event you are not able to access the enabled, it is possible to use the digital I/O product page using the link above, enter output function, TRISx = 0x0, while the this URL in your browser: analog function is also enabled. However, http://www.microchip.com/wwwproducts/ this is not recommended, particularly if the Devices.aspx?dDocName=en554109 analog input is connected to an external analog voltage source, which would 10.6.1 KEY RESOURCES create signal contention between the analog signal and the output pin driver. • “I/O Ports” (DS70193) in the “dsPIC33/PIC24 Family Reference Manual” 3. Most I/O pins have multiple functions. Referring to • Code Samples the device pin diagrams in the data sheet, the priorities of the functions allocated to any pins are • Application Notes indicated by reading the pin name from left-to-right. • Software Libraries The left most function name takes precedence over • Webinars any function to its right in the naming convention. • All related “dsPIC33/PIC24 Family Reference For example: AN16/T2CK/T7CK/RC1. This indi- Manual” Sections cates that AN16 is the highest priority in this • Development Tools example and will supersede all other functions to its right in the list. Those other functions to its right, even if enabled, would not work as long as any other function to its left was enabled. This rule applies to all of the functions listed for a given pin. DS70000652F-page 146  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 10.7 Peripheral Pin Select Registers Note: Input and output register values can only be changed if IOLOCK (OSCCON<6>) = 0. The dsPIC33FJ16(GP/MC)101/102 and See Section10.4.3.1 “Control Register dsPIC33FJ32(GP/MC)101/102/104 family of devices Lock” for a specific command sequence. implements up to 23 registers for remappable peripheral configuration. REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the Corresponding RPn Pin bits 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’  2011-2014 Microchip Technology Inc. DS70000652F-page 147

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the Corresponding RPn Pin bits 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70000652F-page 148  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to the Corresponding RPn Pin bits 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn Pin bits 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0  2011-2014 Microchip Technology Inc. DS70000652F-page 149

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-4: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T5CKR4(1) T5CKR3(1) T5CKR2(1) T5CKR1(1) T5CKR0(1) bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — T4CKR4(1) T4CKR3(1) T4CKR2(1) T4CKR1(1) T4CKR0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T5CKR<4:0>: Assign Timer5 External Clock (T5CK) to the Corresponding RPn Pin bits(1) 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T4CKR<4:0>: Assign Timer4 External Clock (T4CK) to the Corresponding RPn Pin bits(1) 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only. DS70000652F-page 150  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC2R<4:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC1R<4:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0  2011-2014 Microchip Technology Inc. DS70000652F-page 151

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-6: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 IC3R<4:0>: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70000652F-page 152  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-7: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign Output Capture A (OCFA) to the Corresponding RPn Pin bits 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0  2011-2014 Microchip Technology Inc. DS70000652F-page 153

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-8: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 U1CTSR<4:0>: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn Pin bits 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 U1RXR<4:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70000652F-page 154  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-9: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SCK1R4(1) SCK1R3(1) SCK1R2(1) SCK1R1(1) SCK1R0(1) bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SDI1R4(1) SDI1R3(1) SDI1R2(1) SDI1R1(1) SDI1R0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 SCK1R<4:0>: Assign SPI1 Clock Input (SCK1IN) to the Corresponding RPn Pin bits(1) 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits(1) 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 155

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-10: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn Pin bits 11111 = Input tied to VSS 11110 = Reserved . . . 11010 = Reserved 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70000652F-page 156  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-11: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP1R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP0R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table10-2 for peripheral function numbers) REGISTER 10-12: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP3R<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP2R<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits(1) (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits(1) (see Table10-2 for peripheral function numbers) Note 1: These bits are not available in dsPIC33FJXX(GP/MC)101 devices.  2011-2014 Microchip Technology Inc. DS70000652F-page 157

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-13: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP5R<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP4R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits(1) (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table10-2 for peripheral function numbers) Note 1: These bits are not available in dsPIC33FJ(16/32)(GP/MC)101 devices. REGISTER 10-14: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP7R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP6R<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits(1) (see Table10-2 for peripheral function numbers) Note 1: These bits are not available in dsPIC33FJ(16/32)(GP/MC)101 devices. DS70000652F-page 158  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-15: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP9R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP8R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table10-2 for peripheral function numbers) REGISTER 10-16: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP11R<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP10R<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits(1) (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits(1) (see Table10-2 for peripheral function numbers) Note 1: These bits are not available in dsPIC33FJXX(GP/MC)101 devices.  2011-2014 Microchip Technology Inc. DS70000652F-page 159

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-17: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP13R<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP12R<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits(1) (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits(1) (see Table10-2 for peripheral function numbers) Note 1: These bits are not available in dsPIC33FJXXGP101 devices. REGISTER 10-18: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP15R<4:0> bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP14R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table10-2 for peripheral function numbers) DS70000652F-page 160  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-19: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP17R<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP16R<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits(1) (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP16R<4:0>: Peripheral Output Function is Assigned to RP16 Output Pin bits(1) (see Table10-2 for peripheral function numbers) Note 1: These bits are available in dsPIC33FJ32(GP/MC)104 devices only. REGISTER 10-20: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP19R<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP18R<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits(1) (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits(1) (see Table10-2 for peripheral function numbers) Note 1: These bits are available in dsPIC33FJ32(GP/MC)104 devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 161

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 10-21: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP21R<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP20R<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP21R<4:0>: Peripheral Output Function is Assigned to RP21 Output Pin bits(1) (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits(1) (see Table10-2 for peripheral function numbers) Note 1: These bits are available in dsPIC33FJ32(GP/MC)104 devices only. REGISTER 10-22: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP23R<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP22R<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits(1) (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits(1) (see Table10-2 for peripheral function numbers) Note 1: These bits are available in dsPIC33FJ32(GP/MC)104 devices only. DS70000652F-page 162  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 \REGISTER 10-23: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP25R<4:0>(1) bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RP24R<4:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP25R<4:0>: Peripheral Output Function is Assigned to RP25 Output Pin bits(1) (see Table10-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits(1) (see Table10-2 for peripheral function numbers) Note 1: These bits are available in dsPIC33FJ32(GP/MC)104 devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 163

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70000652F-page 164  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 11.0 TIMER1 Timer1 also supports these features: • Timer gate operation Note1: This data sheet summarizes the features • Selectable prescaler settings of the dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 • Timer operation during CPU Idle and Sleep modes family devices. It is not intended to be a • Interrupt on 16-bit Period register match or falling comprehensive reference source. To com- edge of external gate signal plement the information in this data sheet, Figure11-1 presents a block diagram of the 16-bit timer refer to “Timers” (DS70205) in the module. “dsPIC33/PIC24 Family Reference Man- To configure Timer1 for operation: ual”, which is available from the Microchip web site (www.microchip.com). 1. Load the timer value into the TMR1 register. 2: Some registers and associated bits 2. Load the timer period value into the PR1 described in this section may not be register. available on all devices. Refer to 3. Select the timer prescaler ratio using the Section4.0 “Memory Organization” in TCKPS<1:0> bits in the T1CON register. this data sheet for device-specific register 4. Set the Clock and Gating modes using the TCS and bit information. and TGATE bits in the T1CON register. 5. Set or clear the TSYNC bit in T1CON to select The Timer1 module is a 16-bit timer, which can serve synchronous or asynchronous operation. as the time counter for the Real-Time Clock (RTC) or operate as a free-running interval timer/counter. Timer1 6. If interrupts are required, set the Timer1 Inter- can operate in three modes: rupt Enable bit, T1IE. Use the Timer1 Interrupt Priority bits, T1IP<2:0>, to set the interrupt • 16-Bit Timer priority. • 16-Bit Synchronous Counter 7. Set the TON bit (= 1) in the T1CON register. • 16-Bit Asynchronous Counter FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM TCKPS<1:0> TON 2 SOSCO/ 1x T1CK Gate Prescaler SOSCEN Sync 01 1, 8, 64, 256 SOSCI TCY 00 TGATE TGATE TCS 1 Q D Set T1IF 0 Q CK 0 Reset TMR1 1 Sync Comparator TSYNC Equal PR1  2011-2014 Microchip Technology Inc. DS70000652F-page 165

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 11.1 Timer1 Control Register REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit(1) 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timer1 Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0> Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronizes external clock input 0 = Does not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit(1) 1 = External clock from pin, T1CK (on the rising edge) 0 = Internal clock (FCY) bit 0 Unimplemented: Read as ‘0’ Note 1: When TCS = 1 and TON = 1, writes to the TMR1 register are inhibited from the CPU. DS70000652F-page 166  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 12.0 TIMER2/3 AND TIMER4/5 For 32-bit timer/counter operation, Timer2/4 is the least significant word (lsw) and Timer3/5 is the most Note1: This data sheet summarizes the features significant word (msw) of the 32-bit timers. of the dsPIC33FJ16(GP/MC)101/102 Note: For 32-bit operation, T3CON and T5CON and dsPIC33FJ32(GP/MC)101/102/104 control bits are ignored. Only T2CON and family devices. It is not intended to be a T4CON control bits are used for setup and comprehensive reference source. To com- control. Timer2 and Timer4 clock and gate plement the information in this data sheet, inputs are used for the 32-bit timer refer to “Timers” (DS70205) in the modules, but an interrupt is generated “dsPIC33/PIC24 Family Reference Man- with the Timer3 and Timer5 interrupt flags. ual”, which is available from the Microchip web site (www.microchip.com). 12.1 32-Bit Operation 2: Some registers and associated bits described in this section may not be To configure Timer2/3 and Timer4/5 for 32-bit available on all devices. Refer to operation: Section4.0 “Memory Organization” in 1. Set the T32 control bit. this data sheet for device-specific register 2. Select the prescaler ratio for Timer2 or Timer4 and bit information. using the TCKPS<1:0> bits. Timer2/3 and Timer4/5 have three 2-bit timers that can 3. Set the Clock and Gating modes using the also be configured as two independent 16-bit timers corresponding TCS and TGATE bits. with selectable operating modes. 4. Load the timer period value. PR3/PR5 contains Note1: Timer4 and Timer5 are available in the msw of the value, while PR2/PR4 contains dsPIC33FJ32(GP/MC10X) devices only. the least significant word (lsw). 5. If interrupts are required, set the Timer3 (or As a 32-bit timer, Timer2/3 and Timer4/5 permit Timer5) Interrupt Enable bit, T3IE (or T5IE). Use operation in three modes: the priority bits, T3IP<2:0> or T5IP<2:0>, to set the • Two independent 16-bit timers (e.g., Timer2 and interrupt priority. While Timer2/Timer4 controls the Timer3 or Timer4 and Timer5) with all 16-bit timer, the interrupt appears as a Timer3/Timer5 operating modes (except Asynchronous Counter interrupt. mode) 6. Set the corresponding TON bit. • Single 32-bit timer (Timer2/3 and Timer4/5) The timer value at any point is stored in the register • Single 32-bit synchronous counter (Timer2/3 and pair, TMR3:TMR2 or TMR5:TMR4, which always Timer4/5) contains the msw of the count, while TMR2 or TMR4 Timer2/3 and Timer4/5 also support: contains the lsw. • Timer gate operation 12.2 16-Bit Operation • Selectable prescaler settings • Timer operation during Idle and Sleep modes To configure any of the timers for individual 16-bit • Interrupt on a 32-bit Period register match operation: • Time base for input capture and output compare 1. Clear the T32 bit corresponding to that timer. modules (Timer2 and Timer3 only) 2. Select the timer prescaler ratio using the • ADC1 event trigger (Timer2/3 only) TCKPS<1:0> bits. Individually, all eight of the 16-bit timers can function as 3. Set the Clock and Gating modes using the TCS synchronous timers or counters. They also offer the and TGATE bits. features listed above, except for the event trigger. The 4. Load the timer period value into the PRx operating modes and enabled features are determined register. by setting the appropriate bit(s) in the T2CON, T3CON, 5. If interrupts are required, set the Timerx Interrupt T4CON and T5CON registers (see Register12-1 Enable bit, TxIE. Use the priority bits, through Register12-4). TxIP<2:0>, to set the interrupt priority. 6. Set the TON bit.  2011-2014 Microchip Technology Inc. DS70000652F-page 167

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM(1,3,4) TCKPS<1:0> TON 2 TxCK 1x Gate Prescaler Sync 01 1, 8, 64, 256 TCY 00 TGATE TGATE TCS 1 Q D Set TxIF Q CK 0 PRx PRy ADC Event Trigger(2) Equal Comparator MSb LSb TMRx TMRy Sync Reset 16 Read TMRx/TMRy To CTMU Filter Write TMRx/TMRy 16 16 TMRxHLD 16 Data Bus<15:0> Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the TxCON register. 2: The ADC event trigger is available only on Timer2/3. 3: Timer4/5 is available in dsPIC33FJ32(GP/MC)10X devices only. 4: Where ‘x’ or ‘y’ is present, x = 2 or 4; y = 3 or 5. DS70000652F-page 168  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 12-2: TIMER2 AND TIMER4 (16-BIT) BLOCK DIAGRAM(1) TCKPS<1:0> TON 2 TxCK 1x Gate Prescaler Sync 01 1, 8, 64, 256 TGATE 00 TCY TCS 1 Q D TGATE Set TxIF 0 Q CK Reset TMRx Sync Comparator To CTMU Filter Equal PRx Note 1: Timer4 is available in dsPIC33FJ32(GP/MC)10X devices only. FIGURE 12-3: TIMER3 AND TIMER5 (16-BIT) BLOCK DIAGRAM(1) Gate Falling Edge 1 Sync Detect Set TxIF Flag Prescaler 10 FCY 0 (/n) Reset 00 TMRx TCKPS<1:0> TGATE Prescaler Sync x1 (/n) Equal ADC SOC Trigger TxCK Comparator TCKPS<1:0> TGATE TCS PRx To CTMU Filter Note 1: Timer5 is available in dsPIC33FJ32(GP/MC)10X devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 169

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 12.3 Timer2/3 and Timer4/5 Control Registers REGISTER 12-1: T2CON: TIMER2 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer2 On bit When T32 = 1: 1 = Starts 32-bit Timer2/3 0 = Stops 32-bit Timer2/3 When T32 = 0: 1 = Starts 16-bit Timer2 0 = Stops 16-bit Timer2 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timer2 Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer2 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timer2 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 T32: 32-Bit Timer Mode Select bit 1 = Timer2 and Timer3 form a single 32-bit timer 0 = Timer2 and Timer3 act as two 16-bit timers bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer2 Clock Source Select bit 1 = External clock from pin, T2CK (on the rising edge) 0 = Internal clock (FCY) bit 0 Unimplemented: Read as ‘0’ DS70000652F-page 170  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 12-2: T3CON: TIMER3 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(2) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(2) TCKPS1(2) TCKPS0(2) — — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer3 On bit(2) 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timer3 Stop in Idle Mode bit(1) 1 = Discontinues timer operation when device enters Idle mode 0 = Continues timer operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer3 Gated Time Accumulation Enable bit(2) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(2) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer3 Clock Source Select bit(2) 1 = External clock from T3CK pin 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer2 Control register (T2CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32=1) in the Timer2 Control register (T2CON<3>), these bits have no effect.  2011-2014 Microchip Technology Inc. DS70000652F-page 171

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 12-3: T4CON: TIMER4 CONTROL REGISTER(1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer4 On bit When T32 = 1: 1 = Starts 32-bit Timer4/5 0 = Stops 32-bit Timer4/5 When T32 = 0: 1 = Starts 16-bit Timer4 0 = Stops 16-bit Timer4 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timer4 Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer4 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timer4 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 T32: 32-Bit Timer Mode Select bit 1 = Timer4 and Timer5 form a single 32-bit timer 0 = Timer4 and Timer5 act as two 16-bit timers bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer4 Clock Source Select bit 1 = External clock from pin, T4CK (on the rising edge) 0 = Internal clock (FCY) bit 0 Unimplemented: Read as ‘0’ Note 1: This register is available in dsPIC33FJ32(GP/MC)10X devices only. DS70000652F-page 172  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 12-4: T5CON: TIMER5 CONTROL REGISTER(1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(3) — TSIDL(2) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(3) TCKPS1(3) TCKPS0(3) — — TCS(3) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer5 On bit(3) 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timer5 Stop in Idle Mode bit(2) 1 = Discontinues timer operation when device enters Idle mode 0 = Continues timer operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer5 Gated Time Accumulation Enable bit(3) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timer5 Input Clock Prescale Select bits(3) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer5 Clock Source Select bit(3) 1 = External clock from T5CK pin 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: This register is available in dsPIC33FJ32(GP/MC)10X devices only. 2: When 32-bit timer operation is enabled (T32 = 1) in the Timer4 Control register (T4CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 3: When the 32-bit timer operation is enabled (T32=1) in the Timer4 Control register (T4CON<3>), these bits have no effect.  2011-2014 Microchip Technology Inc. DS70000652F-page 173

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70000652F-page 174  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 13.0 INPUT CAPTURE The input capture module captures the 16-bit value of the selected Time Base register when an event occurs Note1: This data sheet summarizes the features on the ICx pin. The events that cause a capture event of the dsPIC33FJ16(GP/MC)101/102 are listed below in three categories: and dsPIC33FJ32(GP/MC)101/102/104 1. Simple Capture Event modes: family devices. It is not intended to be a • Capture timer value on every falling edge of comprehensive reference source. To input at ICx pin complement the information in this data • Capture timer value on every rising edge of sheet, refer to “Input Capture” input at ICx pin (DS70198) in the “dsPIC33/PIC24 Family 2. Capture timer value on every edge (rising and Reference Manual”, which is available falling). from the Microchip web site 3. Prescaler Capture Event modes: (www.microchip.com). • Capture timer value on every 4th rising edge 2: Some registers and associated bits of input at ICx pin described in this section may not be • Capture timer value on every 16th rising available on all devices. Refer to edge of input at ICx pin Section4.0 “Memory Organization” in this data sheet for device-specific register Each input capture channel can select one of two and bit information. 16-bit timers (Timer2 or Timer3) for the time base. The selected timer can use either an internal or The input capture module is useful in applications external clock. requiring frequency (period) and pulse measurement. Other operational features include: The dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 devices support • Device wake-up from capture pin during CPU up to three input capture channels. Sleep and Idle modes • Interrupt on input capture event • 4-word FIFO buffer for capture values: - Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled • Use of input capture to provide additional sources of external interrupts FIGURE 13-1: INPUT CAPTURE x BLOCK DIAGRAM From 16-Bit Timers TMR2 TMR3 16 16 ICTMR 1 0 (ICxCON<7>) Prescaler Edge Detection Logic FIFO Counter and (1, 4, 16) Clock Synchronizer R/W Logic ICx Pin ICM<2:0> (ICxCON<2:0>) 3 Mode Select O F ICOV, ICBNE (ICxCON<4:3>) FI ICxBUF ICI<1:0> Interrupt ICxCON Logic Set Flag ICxIF System Bus (in IFSn Register) Note: An ‘x’ in a signal, register or bit name denotes the number of the input capture channel.  2011-2014 Microchip Technology Inc. DS70000652F-page 175

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 13.1 Input Capture Control Register REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — ICSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0 ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture x Stop in Idle Control bit 1 = Input Capture x module will halt in CPU Idle mode 0 = Input Capture x module will continue to operate in CPU Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 ICTMR: Input Capture x Timer Select bits 1 = TMR2 contents are captured on a capture event 0 = TMR3 contents are captured on a capture event bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only) 1 = Input Capture x overflow occurred 0 = No Input Capture x overflow occurred bit 3 ICBNE: Input Capture x Buffer Empty Status bit (read-only) 1 = Input Capture x buffer is not empty, at least one more capture value can be read 0 = Input Capture x buffer is empty bit 2-0 ICM<2:0>: Input Capture x Mode Select bits 111 = Input Capture x functions as an interrupt pin only when device is in Sleep or Idle mode (rising edge detect only, all other control bits are not applicable) 110 = Unused (module is disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge, rising and falling (ICI<1:0> bits do not control interrupt generation for this mode) 000 = Input Capture x module is turned off DS70000652F-page 176  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 14.0 OUTPUT COMPARE The output compare module can select either Timer2 or Timer3 for its time base. The module compares the Note1: This data sheet summarizes the features value of the timer with the value of one or two compare of the dsPIC33FJ16(GP/MC)101/102 registers depending on the operating mode selected. and dsPIC33FJ32(GP/MC)101/102/104 The state of the output pin changes when the timer family devices. It is not intended to be a value matches the Output Compare Control register comprehensive reference source. To com- value. The output compare module generates either a plement the information in this data sheet, single output pulse, or a sequence of output pulses, by refer to “Output Compare” (DS70209) in changing the state of the output pin on the compare the “dsPIC33/PIC24 Family Reference match events. The output compare module can also Manual”, which is available from the generate interrupts on compare match events. Microchip web site (www.microchip.com). The output compare module has multiple operating 2: Some registers and associated bits modes: described in this section may not be • Active-Low One-Shot mode available on all devices. Refer to • Active-High One-Shot mode Section4.0 “Memory Organization” in • Toggle mode this data sheet for device-specific register and bit information. • Delayed One-Shot mode • Continuous Pulse mode • PWM mode without Fault Protection • PWM mode with Fault Protection FIGURE 14-1: OUTPUT COMPARE x MODULE BLOCK DIAGRAM Set Flag bit, OCxIF OCxRS Output S Q OCxR OCx Logic R 3 Output Output OCM<2:0> Enable Enable Mode Select Logic Comparator OCFA 0 1 OCTSEL 0 1 16 16 TMR2 TMR3 TMR2 TMR3 Rollover Rollover  2011-2014 Microchip Technology Inc. DS70000652F-page 177

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 14.1 Output Compare Modes application must disable the associated timer when writing to the Output Compare Control registers to Configure the Output Compare modes by setting the avoid malfunctions. appropriate Output Compare Mode bits (OCM<2:0>) in the Output Compare x Control (OCxCON<2:0>) Note: See “Output Compare” in the “dsPIC33/ register. Table14-1 lists the different bit settings for the PIC24 Family Reference Manual” Output Compare modes. Figure14-2 illustrates the (DS70209) for OCxR and OCxRS register output compare operation for various modes. The user restrictions. TABLE 14-1: OUTPUT COMPARE x MODES OCM<2:0> Mode OCx Pin Initial State OCx Interrupt Generation 000 Module Disabled Controlled by GPIO register — 001 Active-Low One-Shot 0 OCx Rising Edge 010 Active-High One-Shot 1 OCx Falling Edge 011 Toggle Current output is maintained OCx Rising and Falling Edge 100 Delayed One-Shot 0 OCx Falling Edge 101 Continuous Pulse 0 OCx Falling Edge 110 PWM without Fault Protection 0, if OCxR is zero No Interrupt 1, if OCxR is non-zero 111 PWM with Fault Protection 0, if OCxR is zero OCFA Falling Edge for OC1 to OC4 1, if OCxR is non-zero FIGURE 14-2: OUTPUT COMPARE x OPERATION Output Compare Timer is Reset on Mode Enabled Period Match OCxRS TMRy OCxR Active-Low One-Shot (OCM<2:0> = 001) Active-High One-Shot (OCM<2:0> = 010) Toggle Mode (OCM<2:0> = 011) Delayed One-Shot (OCM<2:0> = 100) Continuous Pulse Mode (OCM<2:0> = 101) PWM Mode (OCM<2:0> = 110 or 111) DS70000652F-page 178  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 14.2 Output Compare Control Register REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0 — — — OCFLT OCTSEL OCM2 OCM1 OCM0 bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Output Compare x Stop in Idle Mode Control bit 1 = Output Compare x will halt in CPU Idle mode 0 = Output Compare x will continue to operate in CPU Idle mode bit 12-5 Unimplemented: Read as ‘0’ bit 4 OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in hardware only) 0 = No PWM Fault condition has occurred (This bit is only used when OCM<2:0> = 111.) bit 3 OCTSEL: Output Compare x Timer Selection bit 1 = Timer3 is the clock source for Output Compare x 0 = Timer2 is the clock source for Output Compare x bit 2-0 OCM<2:0>: Output Compare x Mode Select bits 111 = PWM mode on OCx, Fault pin is enabled 110 = PWM mode on OCx, Fault pin is disabled 101 = Initializes OCx pin low, generates continuous output pulses on OCx pin 100 = Initializes OCx pin low, generates single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initializes OCx pin high, compare event forces OCx pin low 001 = Initializes OCx pin low, compare event forces OCx pin high 000 = Output Compare x channel is disabled  2011-2014 Microchip Technology Inc. DS70000652F-page 179

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70000652F-page 180  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 15.0 MOTOR CONTROL PWM 15.1 PWM1: 6-Channel PWM Module MODULE This module simplifies the task of generating multiple synchronized PWM outputs. The following power and Note1: This data sheet summarizes the features motion control applications are supported by the PWM of the dsPIC33FJ16(GP/MC)101/102 module: and dsPIC33FJ32(GP/MC)101/102/104 family devices. It is not intended to be a • 3-Phase AC Induction Motor comprehensive reference source. To • Switched Reluctance (SR) Motor complement the information in this data • Brushless DC (BLDC) Motor sheet, refer to “Motor Control PWM” • Uninterruptible Power Supply (UPS) (DS70187) in the “dsPIC33/PIC24 This module contains three duty cycle generators, Family Reference Manual”, which is numbered 1 through 3. The module has six PWM available on the Microchip web site output pins, numbered PWM1H1/PWM1L1 through (www.microchip.com). PWM1H3/PWM1L3. The six I/O pins are grouped into 2: Some registers and associated bits high/low numbered pairs, denoted by the suffix H or L, described in this section may not be respectively. For complementary loads, the low PWM available on all devices. Refer to pins are always the complement of the corresponding Section4.0 “Memory Organization” in high I/O pin. this data sheet for device-specific register and bit information. The dsPIC33FJ16MC10X devices have a 6-channel Pulse-Width Modulation (PWM) module. The PWM module has the following features: • Up to 16-bit resolution • On-the-fly PWM frequency changes • Edge-Aligned and Center-Aligned Output modes • Single Pulse Generation mode • Interrupt support for asymmetrical updates in Center-Aligned mode • Output override control for Electrically Commutative Motor (ECM) operation or BLDC • Special event comparator for scheduling other peripheral events • Fault pins to optionally drive each of the PWM output pins to a defined state • Duty cycle updates configurable to be immediate or synchronized to the PWM time base  2011-2014 Microchip Technology Inc. DS70000652F-page 181

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 15-1: 6-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM1) PWM1CON1 PWM Enable and Mode SFRs PWM1CON2 P1DTCON1 Dead-Time Control SFRs P1DTCON2 P1FLTACON Fault A Pin Control SFRs P1FLTBCON Fault B Pin Control SFRs P1OVDCON PWM Manual Control SFR PWM Generator 3 P1DC3 Buffer P1DC3 s u B a Comparator at D Bit Channel 3 Dead-Time PWM1H3 6- Generator and 1 Override Logic PWM1L3 PWM P1TMR Generator 2(1) Channel 2 Dead-Time PWM1H2 Generator and Override Logic Output PWM1L2 Comparator Driver PWM Generator 1(1) Channel 1 Dead-Time Block PWM1H1 Generator and P1TPER Override Logic PWM1L1 P1TPER Buffer FLTA1(2,3) P1TCON FLTB1(3) Comparator Special Event Special Event Trigger Postscaler SEVTDIR P1SECMP PTDIR PWM Time Base Note 1: The details of PWM Generator 1 and 2 are not shown for clarity. 2: On dsPIC33FJ16MC101 (20-pin) devices, the FLTA1 pin is supported, but requires an external pull-down resistor for correct functionality. 3: On dsPIC33FJ16MC102 (28-pin) devices, the FLTA1 and FLTB1 pins are supported and do not require an external pull-down resistor. DS70000652F-page 182  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 15.2 PWM Faults Refer to “Motor Control PWM” (DS70187) in the “dsPIC33/PIC24 Family Reference Manual” for more The Motor Control PWM module incorporates up to two information on the PWM Faults. Fault inputs, FLTA1 and FLTB1. These Fault inputs are implemented with Class B safety features. These Note: The number of PWM Faults mapped to features ensure that the PWM outputs enter a safe the device pins depend on the specific state when either of the Fault inputs is asserted. variant. Regardless of the variant, both Faults will be enabled during any Reset The FLTA1 and FLTB1 pins, when enabled and having event. The application must clear both ownership of a pin, also enable a soft internal pull-down FLTA1 and FLTB1 before enabling the resistor. The soft pull-down provides a safety feature by Motor Control PWM module. Refer to the automatically asserting the Fault should a break occur specific device pin diagrams to see which in the Fault signal connection. Fault pins are mapped to the device pins. The implementation of internal pull-down resistors is dependent on the device variant. Table15-1 describes 15.3 Write-Protected Registers which devices and pins implement the internal pull-down resistors. On dsPIC33FJ(16/32)MC10X devices, write protection is implemented for the PWMxCON1, PxFLTACON and TABLE 15-1: INTERNAL PULL-DOWN PxFLTBCON registers. The write protection feature RESISTORS ON PWM FAULT prevents any inadvertent writes to these registers. The PINS write protection feature can be controlled by the PWMLOCK Configuration bit in the FOSCSEL Config- Internal uration register. The default state of the write protection Device Fault Pin Pull-Down feature is enabled (PWMLOCK = 1). The write protec- Implemented? tion feature can be disabled by configuring PWMLOCK (FOSCSEL<6>) = 0. dsPIC33FJXXMC101 FLTA1 No The user application can gain access to these locked dsPIC33FJXXMC102 FLTA1 Yes registers either by configuring the PWMLOCK bit FLTB1 Yes (FOSCSEL<6>) = 0 or by performing the unlock dsPIC33FJ32MC104 FLTA1 Yes sequence. To perform the unlock sequence, the user application must write two consecutive values FLTB1 Yes (0xABCD and 0x4321) to the PWMxKEY register to On devices without internal pull-downs on the Fault pin, perform the unlock operation. The write access to the it is recommended to connect an external pull-down PWMxCON1, PxFLTACON or PxFLTBCON registers resistor for Class B safety features. must be the next SFR access following the unlock process. There can be no other SFR accesses during 15.2.1 PWM FAULTS AT RESET the unlock process and subsequent write access. During any Reset event, the PWM module maintains To write to all registers, the PWMxCON1, PxFLTACON ownership of both PWM Fault pins. At Reset, both and PxFLTBCON registers require three unlock Faults are enabled in latched mode to guarantee the operations. fail-safe power-up of the application. The application The correct unlocking sequence is described in software must clear both of the PWM Faults before Example15-1 and Example15-2. enabling the Motor Control PWM module. The Fault condition must be cleared by the external cir- cuitry driving the Fault input pin high and clearing the Fault interrupt flag. After the Fault pin condition has been cleared, the PWM module restores the PWM output signals on the next PWM period or half-period boundary.  2011-2014 Microchip Technology Inc. DS70000652F-page 183

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 EXAMPLE 15-1: ASSEMBLY CODE FOR WRITE-PROTECTED REGISTER UNLOCK AND FAULT CLEARING SEQUENCE ; FLTA1 pin must be pulled high externally in order to clear and disable the Fault ; Writing to P1FLTBCON register requires unlock sequence mov #0xabcd,w10 ; Load first unlock key to w10 register mov #0x4321,w11 ; Load second unlock key to w11 register mov #0x0000,w0 ; Load desired value of P1FLTACON register in w0 mov w10, PWM1KEY ; Write first unlock key to PWM1KEY register mov w11, PWM1KEY ; Write second unlock key to PWM1KEY register mov w0,P1FLTACON ; Write desired value to P1FLTACON register ; FLTB1 pin must be pulled high externally in order to clear and disable the Fault ; Writing to P1FLTBCON register requires unlock sequence mov #0xabcd,w10 ; Load first unlock key to w10 register mov #0x4321,w11 ; Load second unlock key to w11 register mov #0x0000,w0 ; Load desired value of P1FLTBCON register in w0 mov w10, PWM1KEY ; Write first unlock key to PWM1KEY register mov w11, PWM1KEY ; Write second unlock key to PWM1KEY register mov w0,P1FLTBCON ; Write desired value to P1FLTBCON register ; Enable all PWMs using PWM1CON1 register ; Writing to PWM1CON1 register requires unlock sequence mov #0xabcd,w10 ; Load first unlock key to w10 register mov #0x4321,w11 ; Load second unlock key to w11 register mov #0x0077,w0 ; Load desired value of PWM1CON1 register in w0 mov w10, PWM1KEY ; Write first unlock key to PWM1KEY register mov w11, PWM1KEY ; Write second unlock key to PWM1KEY register mov w0,PWM1CON1 ; Write desired value to PWM1CON1 register EXAMPLE 15-2: C CODE FOR WRITE-PROTECTED REGISTER UNLOCK AND FAULT CLEARING SEQUENCE // FLTA1 pin must be pulled high externally in order to clear and disable the Fault // Writing to P1FLTACON register requires unlock sequence // Use builtin function to write 0x0000 to P1FLTACON register __builtin_write_PWMSFR(&P1FLTACON, 0x0000, &PWM1KEY); // FLTB1 pin must be pulled high externally in order to clear and disable the Fault // Writing to P1FLTBCON register requires unlock sequence // Use builtin function to write 0x0000 to P1FLTBCON register __builtin_write_PWMSFR(&P1FLTBCON, 0x0000, &PWM1KEY); // Enable all PWMs using PWM1CON1 register // Writing to PWM1CON1 register requires unlock sequence // Use builtin function to write 0x0077 to PWM1CON1 register __builtin_write_PWMSFR(&PWM1CON1, 0x0077, &PWM1KEY); DS70000652F-page 184  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 15.4 PWM Control Registers REGISTER 15-1: PxTCON: PWMx TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 PTEN — PTSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTEN: PWMx Time Base Timer Enable bit 1 = PWMx time base is on 0 = PWMx time base is off bit 14 Unimplemented: Read as ‘0’ bit 13 PTSIDL: PWMx Time Base Stop in Idle Mode bit 1 = PWMx time base halts in CPU Idle mode 0 = PWMx time base runs in CPU Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7-4 PTOPS<3:0>: PWMx Time Base Output Postscale Select bits 1111 = 1:16 postscale • • • 0001 = 1:2 postscale 0000 = 1:1 postscale bit 3-2 PTCKPS<1:0>: PWMx Time Base Input Clock Prescale Select bits 11 = PWMx time base input clock period is 64 TCY (1:64 prescale) 10 = PWMx time base input clock period is 16 TCY (1:16 prescale) 01 = PWMx time base input clock period is 4 TCY (1:4 prescale) 00 = PWMx time base input clock period is TCY (1:1 prescale) bit 1-0 PTMOD<1:0>: PWMx Time Base Mode Select bits 11 = PWMx time base operates in a Continuous Up/Down Count mode with interrupts for double PWM updates 10 = PWMx time base operates in a Continuous Up/Down Count mode 01 = PWMx time base operates in Single Pulse mode 00 = PWMx time base operates in a Free-Running mode  2011-2014 Microchip Technology Inc. DS70000652F-page 185

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 15-2: PxTMR: PWMx TIMER COUNT VALUE REGISTER R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTDIR PTMR<14:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTMR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTDIR: PWMx Time Base Count Direction Status bit (read-only) 1 = PWMx time base is counting down 0 = PWMx time base is counting up bit 14-0 PTMR <14:0>: PWMx Time Base Register Count Value bits REGISTER 15-3: PxTPER: PWMx TIME BASE PERIOD REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — PTPER<14:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTPER<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-0 PTPER<14:0>: PWMx Time Base Period Value bits DS70000652F-page 186  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 15-4: PxSECMP: PWMx SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTDIR(1) SEVTCMP<14:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SEVTDIR: Special Event Trigger Time Base Direction bit(1) 1 = A Special Event Trigger will occur when the PWMx time base is counting down 0 = A Special Event Trigger will occur when the PWMx time base is counting up bit 14-0 SEVTCMP<14:0>: Special Event Compare Value bits(2) Note 1: SEVTDIR is compared with PTDIR (PxTMR<15>) to generate the Special Event Trigger. 2: PxSECMP<14:0> is compared with PxTMR<14:0> to generate the Special Event Trigger.  2011-2014 Microchip Technology Inc. DS70000652F-page 187

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 15-5: PWMxCON1: PWMx CONTROL REGISTER 1(1) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PMOD3 PMOD2 PMOD1 bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — PEN3H(2) PEN2H(2) PEN1H(2) — PEN3L(2) PEN2L(2) PEN1L(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 PMOD<3:1>: PWMx I/O Pair Mode bits 1 = PWMx I/O pin pair is in the Independent PWM Output mode 0 = PWMx I/O pin pair is in the Complementary Output mode bit 7 Unimplemented: Read as ‘0’ bit 6-4 PEN3H:PEN1H: PWMxH I/O Enable bits(2) 1 = PWMxH pin is enabled for PWMx output 0 = PWMxH pin is disabled, I/O pin becomes a general purpose I/O bit 3 Unimplemented: Read as ‘0’ bit 2-0 PEN3L:PEN1L: PWMxL I/O Enable bits(2) 1 = PWMxL pin is enabled for PWMx output 0 = PWMxL pin is disabled, I/O pin becomes a general purpose I/O Note 1: The PWMxCON1 register is a write-protected register. Refer to Section15.3 “Write-Protected Registers” for more information on the unlock sequence. 2: The Reset status for these bits depends on the setting of the PWMPIN Configuration bit (FPOR<7>): • If PWMPIN = 1 (default), the PWM pins are controlled by the PORT register at Reset, meaning they are initially programmed as inputs (i.e., tri-stated). • If PWMPIN = 0, the PWM pins are controlled by the PWM module at Reset and are therefore, initially programmed as output pins. DS70000652F-page 188  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 15-6: PWMxCON2: PWMx CONTROL REGISTER 2 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SEVOPS<3:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — IUE OSYNC UDIS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SEVOPS<3:0>: PWMx Special Event Trigger Output Postscale Select bits 1111 = 1:16 postscale • • • 0001 = 1:2 postscale 0000 = 1:1 postscale bit 7-3 Unimplemented: Read as ‘0’ bit 2 IUE: Immediate Update Enable bit 1 = Updates to the active PxDC registers are immediate 0 = Updates to the active PxDC registers are synchronized to the PWMx time base bit 1 OSYNC: Output Override Synchronization bit 1 = Output overrides via the PxOVDCON register are synchronized to the PWMx time base 0 = Output overrides via the PxOVDCON register occur on the next TCY boundary bit 0 UDIS: PWMx Update Disable bit 1 = Updates from Duty Cycle and Period Buffer registers are disabled 0 = Updates from Duty Cycle and Period Buffer registers are enabled  2011-2014 Microchip Technology Inc. DS70000652F-page 189

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 15-7: PxDTCON1: PWMx DEAD-TIME CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTBPS1 DTBPS0 DTB5 DTB4 DTB3 DTB2 DTB1 DTB0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTAPS1 DTAPS0 DTA5 DTA4 DTA3 DTA2 DTA1 DTA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 DTBPS<1:0>: Dead-Time Unit B Prescale Select bits 11 = Clock period for Dead-Time Unit B is 8 TCY 10 = Clock period for Dead-Time Unit B is 4 TCY 01 = Clock period for Dead-Time Unit B is 2 TCY 00 = Clock period for Dead-Time Unit B is TCY bit 13-8 DTB<5:0>: Unsigned 6-Bit Dead-Time Value for Dead-Time Unit B bits bit 7-6 DTAPS<1:0>: Dead-Time Unit A Prescale Select bits 11 = Clock period for Dead-Time Unit A is 8 TCY 10 = Clock period for Dead-Time Unit A is 4 TCY 01 = Clock period for Dead-Time Unit A is 2 TCY 00 = Clock period for Dead-Time Unit A is TCY bit 5-0 DTA<5:0>: Unsigned 6-Bit Dead-Time Value for Dead-Time Unit A bits DS70000652F-page 190  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 15-8: PxDTCON2: PWMx DEAD-TIME CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 DTS3A: Dead-Time Select for PWM3 Signal Going Active bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A bit 4 DTS3I: Dead-Time Select for PWM3 Signal Going Inactive bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A bit 3 DTS2A: Dead-Time Select for PWM2 Signal Going Active bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A bit 2 DTS2I: Dead-Time Select for PWM2 Signal Going Inactive bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A bit 1 DTS1A: Dead-Time Select for PWM1 Signal Going Active bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A bit 0 DTS1I: Dead-Time Select for PWM1 Signal Going Inactive bit 1 = Dead time provided from Unit B 0 = Dead time provided from Unit A  2011-2014 Microchip Technology Inc. DS70000652F-page 191

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 15-9: PxFLTACON: PWMx FAULT A CONTROL REGISTER(1,2,3,4) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 FLTAM — — — — FAEN3 FAEN2 FAEN1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FAOV<3:1>H:FAOV<3:1>L: Fault Input A PWMx Override Value bits 1 = The PWMx output pin is driven active on an external Fault input event 0 = The PWMx output pin is driven inactive on an external Fault input event bit 7 FLTAM: Fault A Mode bit 1 = The Fault A input pin functions in the Cycle-by-Cycle mode 0 = The Fault A input pin latches all control pins to the programmed states in PxFLTACON<13:8> bit 6-3 Unimplemented: Read as ‘0’ bit 2 FAEN3: Fault Input A Enable bit 1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input A 0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input A bit 1 FAEN2: Fault Input A Enable bit 1 = PWMxH2/PWMxL2 pin pair is controlled by Fault Input A 0 = PWMxH2/PWMxL2 pin pair is not controlled by Fault Input A bit 0 FAEN1: Fault Input A Enable bit 1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input A 0 = PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A Note 1: Comparator outputs are not internally connected to the PWM Fault control logic. If using the comparator modules for Fault generation, the user must externally connect the desired comparator output pin to the dedicated FLTA1 or FLTB1 input pin. 2: Refer to Table15-1 for FLTA1 implementation details. 3: The PxFLTACON register is a write-protected register. Refer to Section15.3 “Write-Protected Registers” for more information on the unlock sequence. 4: During any Reset event, FLTA1 is enabled by default and must be cleared as described in Section15.2 “PWM Faults”. DS70000652F-page 192  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 15-10: PxFLTBCON: PWMx FAULT B CONTROL REGISTER(1,2,3,4) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 FLTBM — — — — FBEN3 FBEN2 FBEN1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FBOV<3:1>H:FBOV<3:1>L: Fault Input B PWMx Override Value bits 1 = The PWMx output pin is driven active on an external Fault input event 0 = The PWMx output pin is driven inactive on an external Fault input event bit 7 FLTBM: Fault B Mode bit 1 = The Fault B input pin functions in the Cycle-by-Cycle mode 0 = The Fault B input pin latches all control pins to the programmed states in PxFLTBCON<13:8> bit 6-3 Unimplemented: Read as ‘0’ bit 2 FBEN3: Fault Input B Enable bit 1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input B 0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input B bit 1 FBEN2: Fault Input B Enable bit 1 = PWMxH2/PWMxL2 pin pair is controlled by Fault Input B 0 = PWMxH2/PWMxL2 pin pair is not controlled by Fault Input B bit 0 FBEN1: Fault Input B Enable bit 1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input B 0 = PWMxH1/PWMxL1 pin pair is not controlled by Fault Input B Note 1: Comparator outputs are not internally connected to the PWM Fault control logic. If using the comparator modules for Fault generation, the user must externally connect the desired comparator output pin to the dedicated FLTA1 or FLTB1 input pin. 2: Refer to Table15-1 for FLTB1 implementation details. 3: The PxFLTACON register is a write-protected register. Refer to Section15.3 “Write-Protected Registers” for more information on the unlock sequence. 4: During any Reset event, FLTB1 is enabled by default and must be cleared as described in Section15.2 “PWM Faults”.  2011-2014 Microchip Technology Inc. DS70000652F-page 193

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 15-11: PxOVDCON: PWMx OVERRIDE CONTROL REGISTER U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 POVD<3:1>H:POVD<3:1>L: PWMx Output Override bits 1 = Output on PWMx I/O pin is controlled by the PWMx generator 0 = Output on PWMx I/O pin is controlled by the value in the corresponding POUTxH:POUTxL bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 POUT<3:1>H:POUT<3:1>L: PWM Manual Output bits 1 = PWMx I/O pin is driven active when the corresponding POVDxH:POVDxL bits are cleared 0 = PWMx I/O pin is driven inactive when the corresponding POVDxH:POVDxL bits are cleared DS70000652F-page 194  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 15-12: PxDC1: PWMx DUTY CYCLE 1 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC1<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC1<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PDC1<15:0>: PWMx Duty Cycle 1 Value bits REGISTER 15-13: PxDC2: PWMx DUTY CYCLE 2 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC2<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC2<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PDC2<15:0>: PWMx Duty Cycle 2 Value bits REGISTER 15-14: PxDC3: PWMx DUTY CYCLE 3 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC3<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC3<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PDC3<15:0>: PWMx Duty Cycle 3 Value bits  2011-2014 Microchip Technology Inc. DS70000652F-page 195

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 15-15: PWMxKEY: PWMx UNLOCK REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWMKEY<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PWMKEY<15:0>: PWMx Unlock bits If the PWMLOCK Configuration bit is asserted (PWMLOCK = 1), the PWMxCON1, PxFLTACON and PxFLTBCON registers are writable only after the proper sequence is written to the PWMxKEY register. If the PWMLOCK Configuration bit is deasserted (PWMLOCK = 0), the PWMxCON1, PxFLTACON and PxFLTBCON registers are writable at all times. Refer to “Motor Control PWM” (DS70187) in the “dsPIC33/ PIC24 Family Reference Manual” for details on the unlock sequence. DS70000652F-page 196  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 16.0 SERIAL PERIPHERAL The Serial Peripheral Interface (SPI) module is a INTERFACE (SPI) synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These Note1: This data sheet summarizes the features peripheral devices can be serial EEPROMs, shift regis- of the dsPIC33FJ16(GP/MC)101/102 ters, display drivers, Analog-to-Digital Converters, etc. and dsPIC33FJ32(GP/MC)101/102/104 The SPI module is compatible with SPI and SIOP from family devices. It is not intended to be a Motorola®. comprehensive reference source. To Each SPI module consists of a 16-bit shift register, complement the information in this data SPIxSR (where x = 1 or 2), used for shifting data in and sheet, refer to “Serial Peripheral Inter- out, and a buffer register, SPIxBUF. A control register, face (SPI)” (DS70206) in the “dsPIC33/ SPIxCON, configures the module. Additionally, a status PIC24 Family Reference Manual”, which register, SPIxSTAT, indicates status conditions. is available from the Microchip web site The serial interface consists of four pins: (www.microchip.com). • SDIx (serial data input) 2: Some registers and associated bits • SDOx (serial data output) described in this section may not be • SCKx (shift clock input or output) available on all devices. Refer to • SSx (active-low slave select). Section4.0 “Memory Organization” in this data sheet for device-specific register In Master mode operation, SCKx is a clock output. In and bit information. Slave mode, it is a clock input. FIGURE 16-1: SPIx MODULE BLOCK DIAGRAM SCKx 1:1 to 1:8 1:1/4/16/64 Secondary Primary FCY Prescaler Prescaler SSx Sync Control Select Control Clock Edge SPIxCON1<1:0> Shift Control SPIxCON1<4:2> SDOx Enable SDIx bit 0 Master Clock SPIxSR Transfer Transfer SPIxRXB SPIxTXB SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus  2011-2014 Microchip Technology Inc. DS70000652F-page 197

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 16.1 SPI Helpful Tips 16.2 SPI Resources 1. In Frame mode, if there is a possibility that the Many useful resources are provided on the main prod- master may not be initialized before the slave: uct page of the Microchip web site for the devices listed a) If FRMPOL (SPIxCON2<13>) = 1, use a in this data sheet. This product page, which can be pull-down resistor on SSx. accessed using this link, contains the latest updates and additional information. b) If FRMPOL = 0, use a pull-up resistor on SSx. Note: This insures that the first frame transmission Note: In the event you are not able to access after initialization is not shifted or corrupted. the product page using the link above, enter this URL in your browser: 2. In Non-Framed 3-Wire mode (i.e., not using SSx http://www.microchip.com/wwwproducts/ from a master): Devices.aspx?dDocName=en554109 a) If CKP (SPIxCON1<6>) = 1, always place a pull-up resistor on SSx. 16.2.1 KEY RESOURCES b) If CKP = 0, always place a pull-down • “Serial Peripheral Interface (SPI)” (DS70206) in resistor on SSx. the “dsPIC33/PIC24 Family Reference Manual”. Note: This will insure that during power-up and • Code Samples initialization, the master/slave will not lose • Application Notes sync due to an errant SCK transition that • Software Libraries would cause the slave to accumulate data • Webinars shift errors for both transmit and receive, • All related “dsPIC33/PIC24 Family Reference appearing as corrupted data. Manual” sections 3. FRMEN (SPIxCON2<15>) = 1 and SSEN • Development Tools (SPIxCON1<7>) = 1 are exclusive and invalid. In Frame mode, SCKx is continuous and the Frame Sync pulse is active on the SSx pin, which indicates the start of a data frame. Note: Not all third-party devices support Frame mode timing. Refer to the SPI electrical characteristics for details. 4. In Master mode only, set the SMP bit (SPIxCON1<9>) to a ‘1’ for the fastest SPI data rate possible. The SMP bit can only be set at the same time or after the MSTEN bit (SPIxCON1<5>) is set. 5. To avoid invalid slave read data to the master, the user’s master software must ensure enough time for slave software to fill its write buffer before the user application initiates a master write/read cycle. It is always advisable to pre- load the SPIxBUF Transmit register in advance of the next master transaction cycle. SPIxBUF is transferred to the SPIx Shift register and is empty once the data transmission begins. 6. The SPI related pins (SDI1, SDO1, SCK1) are located at fixed positions in the dsPIC33FJ16(GP/ MC)10X devices. The same pins are remappable in the dsPIC33FJ32(GP/MC)10X devices. DS70000652F-page 198  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 16.3 SPI Control Registers REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 SPIEN — SPISIDL — — — — — bit 15 bit 8 U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0 — SPIROV — — — — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: SPIx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 SPIROV: SPIx Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded; the user software has not read the previous data in the SPIxBUF register 0 = No overflow has occurred. bit 5-2 Unimplemented: Read as ‘0’ bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit has not yet started, SPIxTXB is full 0 = Transmit has started, SPIxTXB is empty Automatically set in hardware when the CPU writes the SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.  2011-2014 Microchip Technology Inc. DS70000652F-page 199

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(2) CKP MSTEN SPRE2(3) SPRE1(3) SPRE0(3) PPRE1(3) PPRE0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled, pin functions as I/O 0 = Internal SPI clock is enabled bit 11 DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by the module; pin functions as I/O 0 = SDOx pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. bit 8 CKE: Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) bit 7 SSEN: SPIx Slave Select Enable bit (Slave mode)(2) 1 = SSx pin is used for Slave mode 0 = SSx pin is not used by the module, pin is controlled by port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = 1. 3: Do not set both primary and secondary prescalers to a value of 1:1. DS70000652F-page 200  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(3) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 . . . 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(3) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = 1. 3: Do not set both primary and secondary prescalers to a value of 1:1.  2011-2014 Microchip Technology Inc. DS70000652F-page 201

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enabled (SSx pin is used as Frame Sync pulse input/output) 0 = Framed SPIx support is disabled bit 14 SPIFSD: Frame Sync Pulse Direction Control bit 1 = Frame Sync pulse input (slave) 0 = Frame Sync pulse output (master) bit 13 FRMPOL: Frame Sync Pulse Polarity bit 1 = Frame Sync pulse is active-high 0 = Frame Sync pulse is active-low bit 12-2 Unimplemented: Read as ‘0’ bit 1 FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame Sync pulse coincides with first bit clock 0 = Frame Sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application DS70000652F-page 202  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 17.0 INTER-INTEGRATED CIRCUIT™ 17.1 Operating Modes (I2C™) The hardware fully implements all the master and slave functions of the I2C Standard and Fast mode Note 1: This data sheet summarizes the features specifications, as well as 7-Bit and 10-Bit Addressing. of the dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 family The I2C module can operate either as a slave or a devices. It is not intended to be a master on an I2C bus. comprehensive reference source. To com- The following types of I2C operation are supported: plement the information in this data sheet, • I2C slave operation with 7-Bit Addressing refer to “Inter-Integrated Circuit™ (I2C™)” (DS70195) in the “dsPIC33/ • I2C slave operation with 10-Bit Addressing PIC24 Family Reference Manual”, which • I2C master operation with 7-Bit or is available from the Microchip web site 10-Bit Addressing (www.microchip.com). For details about the communication sequence in each 2: Some registers and associated bits of these modes, refer to the Microchip web site described in this section may not be (www.microchip.com) for the latest “dsPIC33/PIC24 available on all devices. Refer to Family Reference Manual” sections. Section4.0 “Memory Organization” in this data sheet for device-specific register 17.2 I2C Registers and bit information. I2CxCON and I2CxSTAT are control and status The Inter-Integrated Circuit™ (I2C™) module provides registers, respectively. The I2CxCON register is complete hardware support for both Slave and Multi- readable and writable. The lower six bits of I2CxSTAT Master modes of the I2C serial communication are read-only. The remaining bits of the I2CxSTAT are standard, with a 16-bit interface. read/write. The I2C module has a 2-pin interface: • I2CxRSR is the shift register used for shifting data • The SCLx pin is clock • I2CxRCV is the receive buffer and the register to • The SDAx pin is data which data bytes are written or from which data bytes are read The I2C module offers the following key features: • I2CxTRN is the transmit register to which bytes • I2C interface supporting both Master and Slave are written during a transmit operation modes of operation • I2CxADD register holds the slave address • I2C Slave mode supports 7-bit and 10-bit addresses • ADD10 status bit indicates 10-Bit Addressing • I2C Master mode supports 7-bit and 10-bit addresses mode • I2C port allows bidirectional transfers between • I2CxBRG acts as the Baud Rate Generator (BRG) master and slaves reload value • Serial clock synchronization for I2C port can be In receive operations, I2CxRSR and I2CxRCV together used as a handshake mechanism to suspend and form a double-buffered receiver. When I2CxRSR resume serial transfer (SCLREL control) receives a complete byte, it is transferred to I2CxRCV • I2C supports multi-master operation, detects bus and an interrupt pulse is generated. collision and arbitrates accordingly  2011-2014 Microchip Technology Inc. DS70000652F-page 203

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 17-1: I2C™ BLOCK DIAGRAM (X = 1) Internal Data Bus I2CxRCV Read Shift SCLx Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation I2CxSTAT c gi Read o CDoelltiseicotn ol L Write ntr o C I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read Shift Clock Reload Control Write BRG Down Counter I2CxBRG Read TCY/2 DS70000652F-page 204  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 17.3 I2C Control Registers REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module, and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module; all I2C™ pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit 1 = Discontinues module operation when device enters an Idle mode 0 = Continues module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Releases SCLx clock 0 = Holds SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clears at beginning of every slave data byte transmission. Hardware clears at end of every slave address byte reception. Hardware clears at every slave data byte reception. If STREN = 0: Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clears at beginning of every slave data byte transmission. Hardware clears at end of every slave address byte reception. bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = IPMI mode is enabled; all addresses are Acknowledged 0 = IPMI mode is disabled bit 10 A10M: I2Cx 10-Bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control is disabled 0 = Slew rate control is enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with SMBus specification 0 = Disables SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address is disabled  2011-2014 Microchip Technology Inc. DS70000652F-page 205

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with the SCLREL bit. 1 = Enables software or receives clock stretching 0 = Disables software or receives clock stretching bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; hardware clears at end of master Acknowledge sequence 0 = Acknowledge sequence is not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C; hardware clears at end of eighth bit of the master receive data byte 0 = Receive sequence is not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on SDAx and SCLx pins; hardware clears at end of the master Stop sequence 0 = Stop condition not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiates Repeated Start condition on SDAx and SCLx pins; hardware clears at end of the master Repeated Start sequence 0 = Repeated Start condition is not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiates Start condition on SDAx and SCLx pins; hardware clears at end of master Start sequence 0 = Start condition is not in progress DS70000652F-page 206  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HS = Hardware Settable bit bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C™ master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware sets or clears at end of slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware sets at beginning of master transmission. Hardware clears at end of slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware sets at detection of bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware sets when address matches general call address. Hardware clears at Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware sets at match of 2nd byte of matched 10-bit address. Hardware clears at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware sets at occurrence of a write to I2CxTRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware sets at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was a device address Hardware clears at device address match. Hardware sets by reception of a slave byte.  2011-2014 Microchip Technology Inc. DS70000652F-page 207

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware sets or clears when Start, Repeated Start or Stop is detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware sets or clears when Start, Repeated Start or Stop is detected. bit 2 R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read – Indicates data transfer is output from slave 0 = Write – Indicates data transfer is input to slave Hardware sets or clears after reception of an I2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive is complete, I2CxRCV is full 0 = Receive is not complete, I2CxRCV is empty Hardware sets when I2CxRCV is written with received byte. Hardware clears when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware sets when software writes to I2CxTRN. Hardware clears at completion of data transmission. DS70000652F-page 208  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK<9:0>: Mask for Address Bit x Select bits 1 = Enables masking for Bit x of incoming message address; bit match not required in this position 0 = Disables masking for Bit x; bit match required in this position  2011-2014 Microchip Technology Inc. DS70000652F-page 209

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70000652F-page 210  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 18.0 UNIVERSAL ASYNCHRONOUS The primary features of the UART module are: RECEIVER TRANSMITTER • Full-Duplex, 8-Bit or 9-Bit Data Transmission (UART) through the UxTX and UxRX Pins • Even, Odd or No Parity options (for 8-bit data) Note1: This data sheet summarizes the features • One or Two Stop bits of the dsPIC33FJ16(GP/MC)101/102 • Hardware Flow Control Option with UxCTS and and dsPIC33FJ32(GP/MC)101/102/104 UxRTS Pins family devices. It is not intended to be a • Fully Integrated Baud Rate Generator with comprehensive reference source. To com- 16-Bit Prescaler plement the information in this data sheet, • Baud Rates Ranging from 1Mbps to 6bps at refer to “UART” (DS70188) in the 16x mode at 16 MIPS “dsPIC33/PIC24 Family Reference Manual”, which is available from the • Baud Rates Ranging from 4Mbps to 24.4bps at Microchip web site (www.microchip.com). 4x mode at 16 MIPS • 4-Deep First-In First-Out (FIFO) Transmit Data 2: Some registers and associated bits Buffer described in this section may not be available on all devices. Refer to • 4-Deep FIFO Receive Data Buffer Section4.0 “Memory Organization” in • Parity, Framing and Buffer Overrun Error Detection this data sheet for device-specific register • Support for 9-bit mode with Address Detect and bit information. (9th bit = 1) • Transmit and Receive Interrupts The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules • A Separate Interrupt for all UART Error Conditions available in the dsPIC33FJ16(GP/MC)101/102 and • Loopback mode for Diagnostic Support dsPIC33FJ32(GP/MC)101/102/104 device family. The • Support for Sync and Break Characters UART is a full-duplex asynchronous system that can • Support for Automatic Baud Rate Detection communicate with peripheral devices, such as • IrDA® Encoder and Decoder Logic personal computers, LIN/J2602, RS-232 and RS-485 interfaces. The module also supports a hardware flow • 16x Baud Clock Output for IrDA® Support control option with the UxCTS and UxRTS pins, and A simplified block diagram of the UART module is also includes an IrDA® encoder and decoder. shown in Figure18-1. The UART module consists of these key hardware elements: • Baud Rate Generator • Asynchronous Transmitter • Asynchronous Receiver FIGURE 18-1: UARTx SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® Hardware Flow Control UxRTS/BCLK UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX  2011-2014 Microchip Technology Inc. DS70000652F-page 211

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 18.1 UART Helpful Tips 18.2 UART Resources 1. In multi-node, direct connect UART networks, Many useful resources are provided on the main UART receive inputs react to the complementary product page of the Microchip web site for the devices logic level defined by the URXINV bit listed in this data sheet. This product page, which can (UxMODE<4>), which defines the Idle state, the be accessed using this link, contains the latest updates default of which is logic high (i.e., URXINV = 0). and additional information. Because remote devices do not initialize at the Note: In the event you are not able to access same time, it is likely that one of the devices, the product page using the link above, because the RX line is floating, will trigger a Start enter this URL in your browser: bit detection and will cause the first byte received http://www.microchip.com/wwwproducts/ after the device has been initialized to be invalid. Devices.aspx?dDocName=en554109 To avoid this situation, the user should use a pull-up or pull-down resistor on the RX pin 18.2.1 KEY RESOURCES depending on the value of the URXINV bit. a) If URXINV = 0, use a pull-up resistor on the • “UART” (DS70188) in the “dsPIC33/PIC24 RX pin. Family Reference Manual” b) If URXINV = 1, use a pull-down resistor on • Code Samples the RX pin. • Application Notes 2. The first character received on a wake-up from • Software Libraries Sleep mode caused by activity on the UxRX pin • Webinars of the UART module will be invalid. In Sleep • All related “dsPIC33/PIC24 Family Reference mode, peripheral clocks are disabled. By the Manual” sections time the oscillator system has restarted and • Development Tools stabilized from Sleep mode, the baud rate bit sampling clock, relative to the incoming UxRX bit timing, is no longer synchronized, resulting in the first character being invalid; this is to be expected. DS70000652F-page 212  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 18.3 UART Control Registers REGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UARTEN(1) — USIDL IREN(2) RTSMD — UEN1 UEN0 bit 15 bit 8 R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by the UEN<1:0> bits 0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption is minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: UARTx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder are enabled 0 = IrDA encoder and decoder are disabled bit 11 RTSMD: UARTx Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Pin Enable bits 11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin is controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins are controlled by port latches bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt is generated on falling edge, bit is cleared in hardware on following rising edge 0 = No wake-up is enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enables Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h) before other data; cleared in hardware upon completion 0 = Baud rate measurement is disabled or completed Note 1: Refer to “UART” (DS70188) in the “dsPIC33/PIC24 Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is available for 16x BRG mode (BRGH=0) only.  2011-2014 Microchip Technology Inc. DS70000652F-page 213

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 URXINV: UARTx Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: Refer to “UART” (DS70188) in the “dsPIC33/PIC24 Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is available for 16x BRG mode (BRGH=0) only. DS70000652F-page 214  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: UARTx Transmit Polarity Inversion bit If IREN = 0: 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ If IREN = 1: 1 = IrDA encoded, UxTX Idle state is ‘1’ 0 = IrDA encoded, UxTX Idle state is ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: UARTx Transmit Break bit 1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission is disabled or completed bit 10 UTXEN: UARTx Transmit Enable bit(1) 1 = Transmit is enabled, UxTX pin is controlled by UARTx 0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is controlled by port bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits 11 = Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive buffer; receive buffer has one or more characters Note 1: Refer to “UART” (DS70188) in the “dsPIC33/PIC24 Family Reference Manual” for information on enabling the UART module for transmit operation.  2011-2014 Microchip Technology Inc. DS70000652F-page 215

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (Bit 8 of received data=1) 1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (read-only/clear only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed; clearing a previously set OERR bit (1 0 transition) will reset the receiver buffer and the UxRSR to the empty state bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to “UART” (DS70188) in the “dsPIC33/PIC24 Family Reference Manual” for information on enabling the UART module for transmit operation. DS70000652F-page 216  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 19.0 10-BIT ANALOG-TO-DIGITAL Depending on the particular device pinout, the ADC CONVERTER (ADC) can have up to 14 analog input pins. Block diagrams of the ADC module are shown in Note 1: This data sheet summarizes the features Figure19-1 through Figure19-3. of the dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 family 19.2 ADC Initialization devices. It is not intended to be a compre- hensive reference source. To complement To configure the ADC module: the information in this data sheet, refer 1. Select port pins as analog inputs to “Analog-to-Digital Converter (AD1PCFGL<15:0>). (ADC)” (DS70183) in the “dsPIC33/ PIC24 Family Reference Manual”, which 2. Select the analog conversion clock to match the is available from the Microchip web site desired data rate with the processor clock (www.microchip.com). (ADxCON3<7:0>). 2: Some registers and associated bits 3. Determine how many Sample-and-Hold described in this section may not be channels will be used (ADxCON2<9:8>). available on all devices. Refer to 4. Select the appropriate sample and conver- Section4.0 “Memory Organization” in sion sequence (ADxCON1<7:5> and this data sheet for device-specific register ADxCON3<12:8>). and bit information. 5. Select the way conversion results are presented in the buffer (ADxCON1<9:8>). The dsPIC33FJ16(GP/MC)101/102 and 6. Turn on the ADC module (ADxCON1<15>). dsPIC33FJ32(GP/MC)101/102/104 devices have up to 14 ADC module input channels. 7. Configure the ADC interrupt (if required): a) Clear the ADxIF bit. 19.1 Key Features b) Select the ADC interrupt priority. The 10-bit ADC configuration has the following key features: • Successive Approximation (SAR) conversion • Conversion speeds of up to 1.1 Msps • Up to 14 analog input pins • Four Sample-and-Hold (S&H) circuits for simultaneous sampling of up to four analog input pins • Automatic Channel Scan mode • Selectable conversion trigger source • Selectable Buffer Fill modes • Four result alignment options (signed/unsigned, fractional/integer) • Operation during CPU Sleep and Idle modes • 16-word conversion result buffer  2011-2014 Microchip Technology Inc. DS70000652F-page 217

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 19-1: ADC1 BLOCK DIAGRAM FOR dsPIC33FJXX(GP/MC)101 DEVICES CTMU TEMP(1) CTMUI(1) Open(2) AN0-AN3 AN9(3) AN10(3) S&H0 Channel Scan + CH0SA<4:0> CH0SB<4:0> - CH0 CSCNA AN1 VREFL CH0NA CH0NB AN0 AVDD AVSS AN3 S&H1 + CH123SA CH123SB - CH1 AN9(3) VCFG<2:0> ADC1BUF0 VREFL ADC1BUF1 ADC1BUF2 VREFH VREFL CH123NA CH123NB SAR ADC AN1 S&H2 + ADC1BUFE ADC1BUFF CH123SA CH123SB - CH2 AN10(3) VREFL CH123NA CH123NB AN2 S&H3 + CH123SA CH123SB - CH3 VREFL CH123NA CH123NB Alternate Input Selection Note1: Internally connected to the CTMU module. 2: This selection is only used with CTMU capacitive and time measurement. 3: This pin is available in dsPIC33FJ32(GP/MC)101 devices only. DS70000652F-page 218  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 19-2: ADC1 BLOCK DIAGRAM FOR dsPIC33FJXX(GP/MC)102 DEVICES CTMU TEMP(1) CTMUI(1) Open(2) AN0-AN5 AN9(3) AN10(3) S&H0 Channel Scan + CH0SB<4:0> CH0SA<4:0> - CH0 CSCNA AN1 VREFL CH0NA CH0NB AN0 AVDD AVSS AN3 S&H1 + CH123SA CH123SB - CH1 AN9(3) VCFG<2:0> VREFL ADC1BUF0 ADC1BUF1 ADC1BUF2 VREFH VREFL CH123NA CH123NB SAR ADC AN1 AN4 S&H2 + ADC1BUFE CH123SA CH123SB - ADC1BUFF CH2 AN10(3) VREFL CH123NA CH123NB AN2 AN5 S&H3 + CH123SA CH123SB - CH3 VREFL CH123NA CH123NB Alternate Input Selection Note1: Internally connected to the CTMU module. 2: This selection is only used with CTMU capacitive and time measurement. 3: This pin is available in dsPIC33FJ32(GP/MC)101 devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 219

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 19-3: ADC1 BLOCK DIAGRAM FOR dsPIC33FJ32(GP/MC)104 DEVICES CTMU TEMP(1) CTMUI(1) Open(2) AN0-AN12 AN15 S&H0 Channel Scan + CH0SB<4:0> CH0SA<4:0> - CH0 CSCNA AN1 VREFL CH0NA CH0NB AN0 AN3 S&H1 AVDD AVSS + - CH123SA CH123SB CH1 AN6 VCFG<2:0> AN9 VREFL ADC1BUF0 ADC1BUF1 ADC1BUF2 VREFH VREFL CH123NA CH123NB SAR ADC AN1 AN4 S&H2 + ADC1BUFE CH123SA CH123SB - ADC1BUFF CH2 AN7 AN10 VREFL CH123NA CH123NB AN2 AN5 S&H3 + CH123SA CH123SB - CH3 AN8 AN11 VREFL CH123NA CH123NB Alternate Input Selection Note1: Internally connected to the CTMU module. 2: This selection is only used with CTMU capacitive and time measurement. DS70000652F-page 220  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 19-4: ADC1 CONVERSION CLOCK PERIOD BLOCK DIAGRAM AD1CON3<15> ADC1 Internal RC Clock(1) 1 TAD AD1CON3<5:0> 0 6 ADC1 Conversion TCY Clock Multiplier TOSC(1) X2 1, 2, 3, 4, 5,..., 64 Note 1: See the ADC specifications in Section26.0 “Electrical Characteristics” for the exact RC clock value. 19.3 ADC Helpful Tips 19.4 ADC Resources 1. The SMPI<3:0> (AD1CON2<5:2>) control bits: Many useful resources are provided on the main prod- a) Determine when the ADC interrupt flag is uct page of the Microchip web site for the devices listed set and an interrupt is generated if enabled. in this data sheet. This product page, which can be accessed using this link, contains the latest updates b) When the CSCNA bit (AD1CON2<10>) is and additional information. set to ‘1’, determine when the ADC analog scan channel list, defined in the AD1CSSL Note: In the event you are not able to access register, starts over from the beginning. the product page using the link above, 2. The ADC has 16 result buffers. ADC conversion enter this URL in your browser: http:// results are stored sequentially in ADC1BUF0- www.microchip.com/wwwproducts/ ADC1BUFF, regardless of which analog inputs Devices.aspx?dDocName=en554109 are being used, subject to the SMPI<3:0> bits (AD1CON2<5:2>). There is no relationship 19.4.1 KEY RESOURCES between the ANx input being measured and • “Analog-to-Digital Converter (ADC)” which ADC buffer (ADC1BUF0-ADC1BUFF) (DS70183) in the “dsPIC33/PIC24 Family that the conversion results will be placed in. Reference Manual” 3. The DONE bit (AD1CON1<0>) is only cleared at the start of each conversion and is set at the • Code Samples completion of the conversion, but remains set • Application Notes indefinitely, even through the next sample phase • Software Libraries until the next conversion begins. If application • Webinars code is monitoring the DONE bit in any kind of • All related “dsPIC33/PIC24 Family Reference software loop, the user must consider this Manual” sections behavior because the CPU code execution is • Development Tools faster than the ADC. As a result, in Manual Sample mode, particularly where the user’s code is setting the SAMP bit (AD1CON1<1>), the DONE bit should also be cleared by the user application just before setting the SAMP bit.  2011-2014 Microchip Technology Inc. DS70000652F-page 221

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 19.5 ADC Control Registers REGISTER 19-1: AD1CON1: ADC1 CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ADON — ADSIDL — — — FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0, HC, HS R/C-0, HC, HS SSRC2 SSRC1 SSRC0 — SIMSAM ASAM SAMP DONE bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: ADC1 Operating Mode bit 1 = ADC1 module is operating 0 = ADC1 is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: ADC1 Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 FORM<1:0>: Data Output Format bits 11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s =.NOT.d<9>) 10 = Fractional (DOUT = dddd dddd dd00 0000) 01 = Signed integer (DOUT = ssss sssd dddd dddd, where s =.NOT.d<9>) 00 = Integer (DOUT = 0000 00dd dddd dddd) bit 7-5 SSRC<2:0>: Sample Clock Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = CTMU 101 = Reserved 100 = Reserved 011 = Motor control PWM interval ends sampling and starts conversion(1) 010 = GP Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion bit 4 Unimplemented: Read as ‘0’ bit 3 SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> = 01 or 1x) 1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x) or samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01) 0 = Samples multiple channels individually in sequence bit 2 ASAM: ADC1 Sample Auto-Start bit 1 = Sampling begins immediately after last conversion; SAMP bit is auto-set 0 = Sampling begins when the SAMP bit is set Note 1: This feature is available in dsPIC33FJ(16/32)MC10X devices only. DS70000652F-page 222  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 19-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 1 SAMP: ADC1 Sample Enable bit 1 = ADC1 Sample-and-Hold amplifiers are sampling 0 = ADC1 Sample-and-Hold amplifiers are holding If ASAM = 0, software can write ‘1’ to begin sampling; automatically set by hardware if ASAM = 1. If SSRC<2:0> = 000, software can write ‘0’ to end sampling and start conversion. If SSRC<2:0> 000, automatically cleared by hardware to end sampling and start conversion. bit 0 DONE: ADC1 Conversion Status bit 1 = ADC1 conversion cycle is completed 0 = ADC1 conversion has not started or is in progress Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear the DONE bit status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion. Note 1: This feature is available in dsPIC33FJ(16/32)MC10X devices only.  2011-2014 Microchip Technology Inc. DS70000652F-page 223

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 19-2: AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 VCFG2 VCFG1 VCFG0 — — CSCNA CHPS1 CHPS0 bit 15 bit 8 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits ADREF+ ADREF- xxx AVDD AVSS bit 12-11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Scan Input Selections for CH0+ During Sample A bit 1 = Scans inputs 0 = Does not scan inputs bit 9-8 CHPS<1:0>: Select Channels Utilized bits 1x = Converts CH0, CH1, CH2 and CH3 01 = Converts CH0 and CH1 00 = Converts CH0 bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = ADC1 is currently filling second half of buffer, user should access data in the first half 0 = ADC1 is currently filling first half of buffer, user application should access data in the second half bit 6 Unimplemented: Read as ‘0’ bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence • • • 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence bit 1 BUFM: Buffer Fill Mode Select bit 1 = Starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt 0 = Always starts filling buffer from the beginning bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A DS70000652F-page 224  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 19-3: AD1CON3: ADC1 CONTROL REGISTER 3 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — — SAMC4(1) SAMC3(1) SAMC2(1) SAMC1(1) SAMC0(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7(2) ADCS6(2) ADCS5(2) ADCS4(2) ADCS3(2) ADCS2(2) ADCS1(2) ADCS0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADRC: ADC1 Conversion Clock Source bit 1 = ADC1 internal RC clock 0 = Clock derived from system clock bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 SAMC<4:0>: Auto-Sample Time bits(1) 11111 = 31 TAD • • • 00001 = 1 TAD 00000 = 0 TAD bit 7-0 ADCS<7:0>: ADC1 Conversion Clock Select bits(2) 11111111 = Reserved • • • • 01000000 = Reserved 00111111 = TCY • (ADCS<7:0> + 1) = 64 • TCY = TAD • • • 00000010 = TCY • (ADCS<7:0> + 1) = 3 • TCY = TAD 00000001 = TCY • (ADCS<7:0> + 1) = 2 • TCY = TAD 00000000 = TCY • (ADCS<7:0> + 1) = 1 • TCY = TAD Note 1: This bit is only used if SSRC<2:0> (AD1CON1<7:5>) = 1. 2: This bit is not used if ADRC (AD1CON3<15>) = 1.  2011-2014 Microchip Technology Inc. DS70000652F-page 225

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 19-4: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CH123NB1 CH123NB0 CH123SB bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CH123NA1 CH123NA0 CH123SA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits dsPIC33FJ16(GP/MC)101/102 Devices Only: 11 = Reserved 10 = Reserved 0x = CH1, CH2, CH3 negative inputs are AVSS dsPIC33FJ32(GP/MC)101/102 Devices Only: 11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is not connected 10 = Reserved 0x = CH1, CH2, CH3 negative inputs are AVSS dsPIC33FJ32(GP/MC)104 Devices Only: 11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8 0x = CH1, CH2, CH3 negative inputs are AVSS bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit dsPIC33FJXX(GP/MC)101 Devices Only: 1 = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 All Other Devices: 1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 bit 7-3 Unimplemented: Read as ‘0’ bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits Refer to bits<10-9> for the available settings. bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit Refer to bit 8 for the available settings. DS70000652F-page 226  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R EGISTER 19-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB — — CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is AVSS bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits 11111-10000 = Reserved; do not use 01111 = Channel 0 positive input is AN15(2) 01110 = No channels connected, all inputs are floating (used for CTMU) 01101 = Channel 0 positive input is connected to CTMU temperature sensor 01100 = Channel 0 positive input is AN12(2) 01011 = Channel 0 positive input is AN11(2) 01010 = Channel 0 positive input is AN10(3) 01001 = Channel 0 positive input is AN9(3) 01000 = Channel 0 positive input is AN8(2) 00111 = Channel 0 positive input is AN7(2) 00110 = Channel 0 positive input is AN6(2) 00101 = Channel 0 positive input is AN5(1) 00100 = Channel 0 positive input is AN4(1) 00011 = Channel 0 positive input is AN3 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is AVSS bit 6-5 Unimplemented: Read as ‘0’ bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits Refer to bits<12-8> for the available settings. Note 1: This setting is available in all devices, excluding the dsPIC33FJXX(GP/MC)101, where it is reserved. 2: This setting is available in the dsPIC33FJ32(GP/MC)104 devices only and is reserved in all other devices. 3: This setting is available in all devices, excluding the dsPIC33FJ16(GP/MC)101/102, where it is reserved.  2011-2014 Microchip Technology Inc. DS70000652F-page 227

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 R ,2EGISTER 19-6: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1,2,3) R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS15(4) — — CSS<12:8>(4,6) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS<7:0>(4,5) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CSS15: ADC1 Input Scan Selection bit(4) 1 = Selects ANx for input scan 0 = Skips ANx for input scan bit 14-13 Unimplemented: Read as ‘0’ bit 12-0 CSS<12:0>: ADC1 Input Scan Selection bits(4,5,6) 1 = Selects ANx for input scan 0 = Skips ANx for input scan Note 1: On devices without 14 analog inputs, all AD1CSSL bits can be selected by the user application. However, inputs selected for scan without a corresponding input on the device converts VREFL. 2: CSSx = ANx, where x = 0 through 12 and 15. 3: CTMU temperature sensor input cannot be scanned. 4: The CSS<15,12:11,8:6> bits are available in the dsPIC33FJ32(GP/MC)104 devices only and are reserved in all other devices. 5: The CSS<5:4> bits are available on all devices, excluding the dsPIC33FJXX(GP/MC)101 devices, where they are reserved. 6: The CSS<10:9> bits are available on all devices, excluding the dsPIC33FJ16(GP/MC)101/102 devices, where they are reserved. DS70000652F-page 228  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 19-7: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW(1,2,3) R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG15(4,5) — — PCFG<12:0>(4,5,7) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG<7:0>(4,5,6) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PCFG15: ADC1 Port Configuration Control bit(4,5) 1 = Port pin is in Digital mode, port read input is enabled, ADC1 input multiplexer is connected to AVSS 0 = Port pin is in Analog mode, port read input is disabled, ADC1 samples pin voltage bit 14-13 Unimplemented: Read as ‘0’ bit 12-0 PCFG<12:0>: ADC1 Port Configuration Control bits(4,5,6,7) 1 = Port pin is in Digital mode, port read input is enabled, ADC1 input multiplexer is connected to AVSS 0 = Port pin is in Analog mode, port read input is disabled, ADC1 samples pin voltage Note 1: On devices without 14 analog inputs, all PCFGx bits are R/W by user. However, PCFGx bits are ignored on ports without a corresponding input on the device. 2: PCFGx = ANx, where x = 0 through 12 and 15. 3: The PCFGx bits have no effect if the ADC module is disabled by setting the AD1MD bit in the PMD1 register. When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode. 4: Pins shared with analog functions (i.e., ANx) are analog by default and therefore, must be set by the user to enable any digital function on that pin. Reading any port pin with the analog function enabled will return a ‘0’, regardless of the signal input level. 5: The PCFG<15,12:11,8:6> bits are available in the dsPIC33FJ32(GP/MC)104 devices only and are reserved in all other devices. 6: The PCFG<5:4> bits are available on all devices, excluding the dsPIC33FJXX(GP/MC)101 devices, where they are reserved. 7: The PCFG<10:9> bits are available on all devices, excluding the dsPIC33FJ16(GP/MC)101/102 devices, where they are reserved.  2011-2014 Microchip Technology Inc. DS70000652F-page 229

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70000652F-page 230  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 20.0 COMPARATOR MODULE The comparator module provides three comparators that can be configured in different ways. As shown in Note1: This data sheet summarizes the features Figure20-1, individual comparator options are of the dsPIC33FJ16(GP/MC)101/102 specified by the comparator module’s Special Function and dsPIC33FJ32(GP/MC)101/102/104 Register (SFR) control bits. device families. It is not intended to be a These options allow users to: comprehensive reference source. To complement the information in this data • Select the edge for trigger and interrupt generation sheet, refer to “Comparator with Blank- • Select low-power control ing” (DS70647) in the “dsPIC33/PIC24 • Configure the comparator voltage reference and Family Reference Manual”, which is band gap available from the Microchip web site • Configure output blanking and masking (www.microchip.com). The comparator operating mode is determined by the 2: Some registers and associated bits input selections (i.e., whether the input voltage is described in this section may not be compared to a second input voltage) to an internal available on all devices. Refer to voltage reference. Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 20-1: COMPARATOR I/O OPERATING MODES EVPOL<1:0> INTREF Interrupt C1INB MUX Logic COE C1INC CPOL VIN- – Blanking Digital C1IND C1 Function Filter VIN+ + (Figure20-3) (Figure20-4) C1OUT CVREFIN COUT MUX C1INA EVPOL<1:0> INTREF Interrupt C2INB MUX Logic COE C2INC VIN- CPOL – Blanking Digital C2IND C2 Function Filter VIN+ + (Figure20-3) (Figure20-4) C2OUT CVREFIN COUT MUX C2INA EVPOL<1:0> INTREF Interrupt C3INB MUX Logic COE C3INC CPOL VIN- – Blanking Digital C3IND VIN+ C3 Function Filter + (Figure20-3) (Figure20-4) C3OUT CVREFIN COUT MUX C3INA Comparator Voltage Reference (Figure20-2) CVREF BGSEL<1:0> AVDD AVSS IVREF(1) Note 1: This reference voltage is generated internally on the device. Refer to Section26.0 “Electrical Characteristics” for the specified voltage range.  2011-2014 Microchip Technology Inc. DS70000652F-page 231

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 20-2: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSRC CVRCON<3:0> VREFSEL AVDD(1) R3R2R1R0 8R CVCVCVCV CVREFIN R CVREN R R R X U M 16 Steps 1 CVREF o- 6-t 1 R CVROE (CVRCON<6>) R R CVRR 8R AVSS(1) Note 1: This pin is VDD and VSS on devices that have no AVDD or AVSS pins. FIGURE 20-3: USER-PROGRAMMABLE BLANKING FUNCTION BLOCK DIAGRAM SELSRCA<3:0> (CMxMSKSRC<3:0>) Comparator Output To Digital Blanking UX A MAI “AND-OR” Function BlLaongkiicng Filter Signals M MAI MBI ANDI AND SELSRCB<3:0> MCI (CMxMSKSRC<7:4) MAI HLMS (CMxMSKCON<15>) BSlaignnkainlsg X B MBI MBI OR MASK U M MCI SELSRCC<3:0> (CMxMSKSRC<11:8) CMxMSKCON C Blanking X MCI Signals U M DS70000652F-page 232  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 20-4: DIGITAL FILTER INTERCONNECT BLOCK DIAGRAM Timer2 Timer3 PWM Special Event Trigger FOSC FCY CFDIV CFSEL<2:0> CFLTREN From Blanking Logic Digital Filter CXOUT  2011-2014 Microchip Technology Inc. DS70000652F-page 233

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 20.1 Comparator Control Registers REGISTER 20-1: CMSTAT: COMPARATOR STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 CMSIDL — — — — C3EVT C2EVT C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — C3OUT C2OUT C1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMSIDL: Comparator Stop in Idle Mode bit 1 = Discontinues operation of all comparators when device enters Idle mode 0 = Continues operation of all comparators in Idle mode bit 14-11 Unimplemented: Read as ‘0’ bit 10 C3EVT: Comparator 3 Event Status bit 1 = Comparator event occurred 0 = Comparator event did not occur bit 9 C2EVT: Comparator 2 Event Status bit 1 = Comparator event occurred 0 = Comparator event did not occur bit 8 C1EVT: Comparator 1 Event Status bit 1 = Comparator event occurred 0 = Comparator event did not occur bit 7-3 Unimplemented: Read as ‘0’ bit 2 C3OUT: Comparator 3 Output Status bit When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 1 C2OUT: Comparator 2 Output Status bit When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 0 C1OUT: Comparator 1 Output Status bit When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- DS70000652F-page 234  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 20-2: CMxCON: COMPARATOR x CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 CON COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CON: Comparator x Enable bit 1 = Comparator x is enabled 0 = Comparator x is disabled bit 14 COE: Comparator x Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 13 CPOL: Comparator x Output Polarity Select bit 1 = Comparator x output is inverted 0 = Comparator x output is not inverted bit 12-10 Unimplemented: Read as ‘0’ bit 9 CEVT: Comparator x Event bit 1 = Comparator x event according to EVPOL<1:0> settings occurred; disables future triggers and interrupts until the bit is cleared 0 = Comparator x event did not occur bit 8 COUT: Comparator x Output bit When CPOL = 0 (non-inverted polarity): 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1 (inverted polarity): 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT=0) 10 = Trigger/event/interrupt is generated only on high-to-low transition of the polarity selected comparator output (while CEVT=0) If CPOL = 1 (inverted polarity): Low-to-high transition of the comparator output. If CPOL = 0 (non-inverted polarity): High-to-low transition of the comparator output. 01 = Trigger/event/interrupt is generated only on low-to-high transition of the polarity selected comparator output (while CEVT=0) If CPOL = 1 (inverted polarity): High-to-low transition of the comparator output. If CPOL = 0 (non-inverted polarity): Low-to-high transition of the comparator output. 00 = Trigger/event/interrupt generation is disabled bit 5 Unimplemented: Read as ‘0’  2011-2014 Microchip Technology Inc. DS70000652F-page 235

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 20-2: CMxCON: COMPARATOR x CONTROL REGISTER (CONTINUED) bit 4 CREF: Comparator x Reference Select bit (VIN+ input) 1 = VIN+ input connects to internal CVREFIN voltage 0 = VIN+ input connects to CxINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator x Channel Select bits 11 = VIN- input of comparator connects to INTREF 10 = VIN- input of comparator connects to CXIND pin 01 = VIN- input of comparator connects to CXINC pin 00 = VIN- input of comparator connects to CXINB pin DS70000652F-page 236  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 20-3: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT REGISTER U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 RW-0 — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SELSRCC<3:0>: Mask C Input Select bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = PWM1H3 0100 = PWM1L3 0011 = PWM1H2 0010 = PWM1L2 0001 = PWM1H1 0000 = PWM1L1 bit 7-4 SELSRCB<3:0>: Mask B Input Select bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = PWM1H3 0100 = PWM1L3 0011 = PWM1H2 0010 = PWM1L2 0001 = PWM1H1 0000 = PWM1L1  2011-2014 Microchip Technology Inc. DS70000652F-page 237

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 20-3: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT REGISTER (CONTINUED) bit 3-0 SELSRCA<3:0>: Mask A Input Select bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = PWM1H3 0100 = PWM1L3 0011 = PWM1H2 0010 = PWM1L2 0001 = PWM1H1 0000 = PWM1L1 DS70000652F-page 238  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 20-4: CMxMSKCON: COMPARATOR x MASK GATING CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLMS: High or Low Level Masking Select bits 1 = The masking (blanking) function will prevent any asserted (‘0’) comparator signal from propagating 0 = The masking (blanking) function will prevent any asserted (‘1’) comparator signal from propagating bit 14 Unimplemented: Read as ‘0’ bit 13 OCEN: OR Gate C Input Inverted Enable bit 1 = MCI is connected to OR gate 0 = MCI is not connected to OR gate bit 12 OCNEN: OR Gate C Input Inverted Enable bit 1 = Inverted MCI is connected to OR gate 0 = Inverted MCI is not connected to OR gate bit 11 OBEN: OR Gate B Input Inverted Enable bit 1 = MBI is connected to OR gate 0 = MBI is not connected to OR gate bit 10 OBNEN: OR Gate B Input Inverted Enable bit 1 = Inverted MBI is connected to OR gate 0 = Inverted MBI is not connected to OR gate bit 9 OAEN: OR Gate A Input Enable bit 1 = MAI is connected to OR gate 0 = MAI is not connected to OR gate bit 8 OANEN: OR Gate A Input Inverted Enable bit 1 = Inverted MAI is connected to OR gate 0 = Inverted MAI is not connected to OR gate bit 7 NAGS: Negative AND Gate Output Select 1 = Inverted ANDI is connected to OR gate 0 = Inverted ANDI is not connected to OR gate bit 6 PAGS: Positive AND Gate Output Select 1 = ANDI is connected to OR gate 0 = ANDI is not connected to OR gate bit 5 ACEN: AND Gate A1 C Input Inverted Enable bit 1 = MCI is connected to AND gate 0 = MCI is not connected to AND gate bit 4 ACNEN: AND Gate A1 C Input Inverted Enable bit 1 = Inverted MCI is connected to AND gate 0 = Inverted MCI is not connected to AND gate  2011-2014 Microchip Technology Inc. DS70000652F-page 239

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 20-4: CMxMSKCON: COMPARATOR x MASK GATING CONTROL REGISTER (CONTINUED) bit 3 ABEN: AND Gate A1 B Input Inverted Enable bit 1 = MBI is connected to AND gate 0 = MBI is not connected to AND gate bit 2 ABNEN: AND Gate A1 B Input Inverted Enable bit 1 = Inverted MBI is connected to AND gate 0 = Inverted MBI is not connected to AND gate bit 1 AAEN: AND Gate A1 A Input Enable bit 1 = MAI is connected to AND gate 0 = MAI is not connected to AND gate bit 0 AANEN: AND Gate A1 A Input Inverted Enable bit 1 = Inverted MAI is connected to AND gate 0 = Inverted MAI is not connected to AND gate DS70000652F-page 240  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 20-5: CMxFLTR: COMPARATOR x FILTER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CFSEL<2:0>: Comparator Filter Input Clock Select bits 111 = Reserved 110 = Reserved 101 = Timer3 100 = Timer2 011 = Reserved 010 = PWM Special Event Trigger 001 = FOSC 000 = FCY bit 3 CFLTREN: Comparator Filter Enable bit 1 = Digital filter is enabled 0 = Digital filter is disabled bit 2-0 CFDIV<2:0>: Comparator Filter Clock Divide Select bits 111 = Clock Divide 1:128 110 = Clock Divide 1:64 101 = Clock Divide 1:32 100 = Clock Divide 1:16 011 = Clock Divide 1:8 010 = Clock Divide 1:4 001 = Clock Divide 1:2 000 = Clock Divide 1:1  2011-2014 Microchip Technology Inc. DS70000652F-page 241

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 20-6: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — VREFSEL BGSEL1 BGSEL0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR — CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 VREFSEL: Voltage Reference Select bit 1 = CVREFIN = CVREF pin 0 = CVREFIN is generated by the resistor network bit 9-8 BGSEL<1:0>: Band Gap Reference Source Select bits 11 = INTREF = CVREF pin 10 = INTREF = 1.2V (nominal)(2) 0x = Reserved bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = Comparator voltage reference circuit is powered on 0 = Comparator voltage reference circuit is powered down bit 6 CVROE: Comparator Voltage Reference Output Enable bit(1) 1 = Voltage level is output on CVREF pin 0 = Voltage level is disconnected from CVREF pin bit 5 CVRR: Comparator Voltage Reference Range Selection bit 1 = CVRSRC/24 step-size 0 = CVRSRC/32 step-size bit 4 Unimplemented: Read as ‘0’ bit 3-0 CVR<3:0>: Comparator Voltage Reference Value Selection 0  CVR<3:0>  15 bits When CVRR = 1: CVREFIN = (CVR<3:0>/24) • (CVRSRC) When CVRR = 0: CVREFIN = 1/4 • (CVRSRC) + (CVR<3:0>/32) • (CVRSRC) Note 1: CVROE overrides the TRISx bit setting. 2: This reference voltage is generated internally on the device. Refer to Section26.0 “Electrical Characteristics” for the specified voltage range. DS70000652F-page 242  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 21.0 REAL-TIME CLOCK AND Some of the key features of the RTCC module are: CALENDAR (RTCC) • Time: hours, minutes and seconds • 24-hour format (military time) Note1: This data sheet summarizes the features • Calendar: weekday, date, month and year of the dsPIC33FJ16(GP/MC)101/102 • Alarm configurable and dsPIC33FJ32(GP/MC)101/102/104 device families of devices. It is not • Year range: 2000 to 2099 intended to be a comprehensive reference • Leap year correction source. To complement the information in • BCD format for compact firmware this data sheet, refer to “Real-Time Clock • Optimized for low-power operation and Calendar (RTCC)” (DS70310) in the • User calibration with auto-adjust “dsPIC33/PIC24 Family Reference Man- • Calibration range: ±2.64 seconds error per month ual”, which is available on the Microchip web site (www.microchip.com). • Requirements: external 32.768 kHz clock crystal • Alarm pulse or seconds clock output on RTCC pin 2: Some registers and associated bits described in this section may not be The RTCC module is intended for applications where available on all devices. Refer to accurate time must be maintained for extended periods Section4.0 “Memory Organization” in of time with minimum to no intervention from the CPU. this data sheet for device-specific register The RTCC module is optimized for low-power usage to and bit information. provide extended battery lifetime while keeping track of time. This chapter discusses the Real-Time Clock and Calendar (RTCC) module, available The RTCC module is a 100-year clock and calendar on dsPIC33FJ16(GP/MC)101/102 and with automatic leap year detection. The range of the dsPIC33FJ32(GP/MC)101/102/104 devices, and its clock is from 00:00:00 (midnight) on January 1, 2000 to operation. 23:59:59 on December 31, 2099. The hours are available in 24-hour (military time) format. The clock provides a granularity of one second with half-second visibility to the user. FIGURE 21-1: RTCC BLOCK DIAGRAM RTCC Clock Domain CPU Clock Domain 32.768 kHz Input RCFGCAL from SOSC Oscillator RTCC Prescalers ALCFGRPT 0.5s RTCC Timer RTCVAL Alarm Event Comparator Compare Registers ALRMVAL with Masks Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE  2011-2014 Microchip Technology Inc. DS70000652F-page 243

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 21.1 RTCC Module Registers By writing the ALRMVALH byte, the Alarm Pointer value (ALRMPTR<1:0> bits) decrements by one until it The RTCC module registers are organized into three reaches ‘00’. Once it reaches ‘00’, the ALRMMIN and categories: ALRMSEC value will be accessible through • RTCC Control Registers ALRMVALH and ALRMVALL until the pointer value is • RTCC Value Registers manually changed. • Alarm Value Registers TABLE 21-2: ALRMVAL REGISTER 21.1.1 REGISTER MAPPING MAPPING To limit the register interface, the RTCC Timer and Alarm Value Register Window ALRMPTR Alarm Time registers are accessed through <1:0> ALRMVAL<15:8> ALRMVAL<7:0> corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the 00 ALRMMIN ALRMSEC RTCPTR bits (RCFGCAL<9:8>) to select the desired 01 ALRMWD ALRMHR Timer register pair (see Table21-1). 10 ALRMMNTH ALRMDAY By writing the RTCVALH byte, the RTCC Pointer value 11 — — (RTCPTR<1:0> bits) decrements by one until it reaches ‘00’. Once it reaches ‘00’, the MINUTES and Considering that the 16-bit core does not distinguish SECONDS value will be accessible through RTCVALH between 8-bit and 16-bit read operations, the user must and RTCVALL until the pointer value is manually be aware that when reading either the ALRMVALH or changed. ALRMVALL, bytes will decrement the ALRMPTR<1:0> value. The same applies to the RTCVALH or RTCVALL TABLE 21-1: RTCVAL REGISTER MAPPING bytes with the RTCPTR<1:0> being decremented. RTCC Value Register Window Note: This only applies to read operations and RTCPTR not write operations. <1:0> RTCVAL<15:8> RTCVAL<7:0> 00 MINUTES SECONDS 21.1.2 WRITE LOCK 01 WEEKDAY HOURS In order to perform a write to any of the RTCC Timer 10 MONTH DAY registers, the RTCWREN bit (RCFGCAL<13>) must be set (refer to Example21-1). 11 — YEAR Note: To avoid accidental writes to the timer, it is The Alarm Value register window (ALRMVALH and recommended that the RTCWREN bit ALRMVALL) uses the ALRMPTR bits (ALCFGRPT<9:8>) (RCFGCAL<13>) is kept clear at any to select the desired Alarm register pair (see Table21-2). other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed between the 55h/AA sequence and the setting of RTCWREN; therefore, it is recommended that code follow the procedure in Example21-1. EXAMPLE 21-1: SETTING THE RTCWREN BIT MOV #NVMKEY, W1 ;move the address of NVMKEY into W1 MOV #0x55, W2 MOV #0xAA, W3 MOV W2, [W1] ;start 55/AA sequence MOV W3, [W1] BSET RCFGCAL, #13 ;set the RTCWREN bit DS70000652F-page 244  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 21.2 RTCC Control Registers REGISTER 21-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 RTCEN(2) — RTCWREN RTCSYNC HALFSEC(3) RTCOE RTCPTR1 RTCPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading, due to a rollover ripple, resulting in an invalid data read. If the register is read twice and the results are the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple bit 11 HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second bit 10 RTCOE: RTCC Output Enable bit 1 = RTCC output is enabled 0 = RTCC output is disabled bit 9-8 RTCPTR<1:0>: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers; the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’. RTCVAL<15:8>: 00 = MINUTES 01 = WEEKDAY 10 = MONTH 11 = Reserved RTCVAL<7:0>: 00 = SECONDS 01 = HOURS 10 = DAY 11 = YEAR Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.  2011-2014 Microchip Technology Inc. DS70000652F-page 245

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 21-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) bit 7-0 CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute • • • 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute • • • 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register. DS70000652F-page 246  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 21-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — RTSECSEL(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 Unimplemented: Read as ‘0’ Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set.  2011-2014 Microchip Technology Inc. DS70000652F-page 247

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 21-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0>=0x00 and CHIME=0) 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit 1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 0x00 to 0xFF 0 = Chime is disabled; ARPT<7:0> bits stop once they reach 0x00 bit 13-10 AMASK<3:0>: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every 4 years) 101x = Reserved – do not use 11xx = Reserved – do not use bit 9-8 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers; the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVAL<15:8>: 00 = ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = Unimplemented ALRMVAL<7:0>: 00 = ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = Unimplemented bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times • • • 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 0x00 to 0xFF unless CHIME=1. DS70000652F-page 248  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 21-4: RTCVAL (WHEN RTCPTR<1:0> = 11): RTCC YEAR VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits Contains a value from 0 to 9. bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 21-5: RTCVAL (WHEN RTCPTR<1:0> = 10): RTCC MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R-x R-x R-x R-x R-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1.  2011-2014 Microchip Technology Inc. DS70000652F-page 249

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 21-6: RTCVAL (WHEN RTCPTR<1:0> = 01): RTCC WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. DS70000652F-page 250  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 21-7: RTCVAL (WHEN RTCPTR<1:0> = 00): RTCC MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2011-2014 Microchip Technology Inc. DS70000652F-page 251

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 21-8: ALRMVAL (WHEN ALRMPTR<1:0> = 10): ALARM MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. DS70000652F-page 252  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 21-9: ALRMVAL (WHEN ALRMPTR<1:0> = 01): ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1.  2011-2014 Microchip Technology Inc. DS70000652F-page 253

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 21-10: ALRMVAL (WHEN ALRMPTR<1:0> = 00): ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9. DS70000652F-page 254  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 22.0 CHARGE TIME Together with other on-chip analog modules, the CTMU MEASUREMENT UNIT (CTMU) can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses that are independent of the Note1: This data sheet summarizes the features system clock. of the dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 The CTMU module is ideal for interfacing with device families of devices. It is not capacitive-based sensors. The CTMU is controlled intended to be a comprehensive reference through three registers: CTMUCON1, CTMUCON2 source. To complement the information in and CTMUICON. CTMUCON1 enables the module, this data sheet, refer to “Charge Time the edge delay generation, sequencing of edges, and Measurement Unit (CTMU)” (DS70635) controls the current source and the output trigger. in the “dsPIC33/PIC24 Family Reference CTMUCON2 controls the edge source selection, edge Manual”, which is available on the source polarity selection and edge sampling mode. The Microchip web site (www.microchip.com). CTMUICON register controls the selection and trim of the current source. 2: Some registers and associated bits described in this section may not be Figure22-1 shows the CTMU block diagram. available on all devices. Refer to Section4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Charge Time Measurement Unit (CTMU) is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. Its key features include: • Four edge input trigger sources • Polarity control for each edge source • Control of edge sequence • Control of response to edges • Precise time measurement resolution of 200 ps • Accurate current source suitable for capacitive measurement • On-chip temperature measurement using a built-in diode  2011-2014 Microchip Technology Inc. DS70000652F-page 255

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 22-1: CTMU BLOCK DIAGRAM CTMUCON1 or CTMUCON2 CTMUICON ITRIM<5:0> IRNG<1:0> Current Source CTED1 Edge Control EDG1STAT CTMU Analog-to-Digital CTED2 Logic EDG2STAT Current TGEN CLoongtircol Trigger Control Timer1 OC1 Pulse IC1 CTMUP CTPLS Generator CMP2 CTMUI to ADC CTMU TEMP CTMU C2INA Temperature Sensor CDelay Comparator 2 External Capacitor for Pulse Generation Current Control Selection TGEN EDG1STAT, EDG2STAT CTMU TEMP 0 EDG1STAT = EDG2STAT CTMUI 0 EDG1STAT  EDG2STAT CTMUP 1 EDG1STAT  EDG2STAT No Connect 1 EDG1STAT = EDG2STAT DS70000652F-page 256  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 22.1 CTMU Control Registers REGISTER 22-1: CTMUCON1: CTMU CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN(1) EDGEN EDGSEQEN IDISSEN(2) CTTRIG bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CTMUSIDL: CTMU Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 TGEN: Time Generation Enable bit(1) 1 = Enables edge delay generation 0 = Disables edge delay generation bit 11 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 10 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 9 IDISSEN: Analog Current Source Control bit(2) 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 8 CTTRIG: CTMU Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled bit 7-0 Unimplemented: Read as ‘0’ Note 1: If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. For more information, see Section10.4 “Peripheral Pin Select (PPS)”. 2: The ADC module S&H capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitance measurement must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array.  2011-2014 Microchip Technology Inc. DS70000652F-page 257

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 22-2: CTMUCON2: CTMU CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 EDG1MOD: Edge 1 Edge Sampling Selection bit 1 = Edge 1 is edge-sensitive 0 = Edge 1 is level-sensitive bit 14 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 is programmed for a positive edge response 0 = Edge 1 is programmed for a negative edge response bit 13-10 EDG1SEL<3:0>: Edge 1 Source Select bits 1xxx = Reserved 01xx = Reserved 0011 = CTED1 pin 0010 = CTED2 pin 0001 = OC1 module 0000 = Timer1 module bit 9 EDG2STAT: Edge 2 Status bit Indicates the status of Edge 2 and can be written to control the edge source. 1 = Edge 2 has occurred 0 = Edge 2 has not occurred bit 8 EDG1STAT: Edge 1 Status bit Indicates the status of Edge 1 and can be written to control the edge source. 1 = Edge 1 has occurred 0 = Edge 1 has not occurred bit 7 EDG2MOD: Edge 2 Edge Sampling Selection bit 1 = Edge 2 is edge-sensitive 0 = Edge 2 is level-sensitive bit 6 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative edge response bit 5-2 EDG2SEL<3:0>: Edge 2 Source Select bits 1xxx = Reserved 01xx = Reserved 0011 = CTED2 pin 0010 = CTED1 pin 0001 = Comparator 2 module 0000 = IC1 module bit 1-0 Unimplemented: Read as ‘0’ DS70000652F-page 258  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 22-3: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 ITRIM<5:0>: Current Source Trim bits 011111 = Nominal current output specified by IRNG<1:0> + 62% 011110 = Nominal current output specified by IRNG<1:0> + 60% • • • 000001 = Nominal current output specified by IRNG<1:0> + 2% 000000 = Nominal current output specified by IRNG<1:0> 111111 = Nominal current output specified by IRNG<1:0> – 2% • • • 100010 = Nominal current output specified by IRNG<1:0> – 62% 100001 = Nominal current output specified by IRNG<1:0> – 64% bit 9-8 IRNG<1:0>: Current Source Range Select bits 11 = 100  Base Current(1) 10 = 10  Base Current 01 = Base current level (0.55A nominal) 00 = Reserved bit 7-0 Unimplemented: Read as ‘0’ Note 1: This setting must be used for the CTMU temperature sensor.  2011-2014 Microchip Technology Inc. DS70000652F-page 259

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70000652F-page 260  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 23.0 SPECIAL FEATURES In dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 devices, the Con- Note 1: This data sheet summarizes the figuration bytes are implemented as volatile memory. features of the dsPIC33FJ16(GP/ This means that configuration data must be programmed MC)101/102 and dsPIC33FJ32(GP/ each time the device is powered up. Configuration data MC)101/102/104 devices. It is not is stored in the two words at the top of the on-chip pro- intended to be a comprehensive reference gram memory space, known as the Flash Configuration source. To complement the information in Words. Their specific locations are shown in Table23-2. this data sheet, refer to “Programming These are packed representations of the actual device and Diagnostics” (DS70207) and Configuration bits, whose actual locations are distributed “Device Configuration” (DS70194) in among several locations in configuration space. The con- the “dsPIC33/PIC24 Family Reference figuration data is automatically loaded from the Flash Manual”, which are available from the Configuration Words to the proper Configuration Microchip web site (www.microchip.com). registers during device Resets. 2: Some registers and associated bits Note: Configuration data is reloaded on all types described in this section may not be of device Resets. available on all devices. Refer to When creating applications for these devices, users Section4.0 “Memory Organization” in should always specifically allocate the location of the this data sheet for device-specific register Flash Configuration Word for configuration data. This is and bit information. to make certain that program code is not stored in this dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/ address when the code is compiled. MC)101/102/104 devices include several features The upper byte of all Flash Configuration Words in pro- intended to maximize application flexibility and gram memory should always be ‘1111 1111’. This reliability, and minimize cost through elimination of makes them appear to be NOP instructions in the external components. These are: remote event that their locations are ever executed by • Flexible Configuration accident. Since Configuration bits are not implemented • Watchdog Timer (WDT) in the corresponding locations, writing ‘1’s to these locations has no effect on device operation. • Code Protection • In-Circuit Serial Programming™ (ICSP™) Note: Performing a page erase operation on the • In-Circuit Emulation last page of program memory clears the Flash Configuration Words, enabling code 23.1 Configuration Bits protection as a result. Therefore, users should avoid performing page erase The Configuration Shadow register bits can be config- operations on the last page of program ured (read as ‘0’) or left unprogrammed (read as ‘1’) to memory. select various device configurations. These read-only bits are mapped starting at program memory location, 0xF80000. A detailed explanation of the various bit functions is provided in Table23-4. Note that address, 0xF80000, is beyond the user pro- gram memory space and belongs to the configuration memory space (0x800000-0xFFFFFF), which can only be accessed using Table Reads.  2011-2014 Microchip Technology Inc. DS70000652F-page 261

D The Configuration Shadow register map is shown in Table23-1. d S7 s 00 TABLE 23-1: CONFIGURATION SHADOW REGISTER MAP P 0 I 0 C 652 File Name Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3 F 3 -p FGS F80004 — — — — — — GCP GWRP F ag FOSCSEL F80006 IESO PWMLOCK(1) — WDTWIN1 WDTWIN0 FNOSC2 FNOSC1 FNOSC0 J e 2 FOSC F80008 FCKSM1 FCKSM0 IOL1WAY — — OSCIOFNC POSCMD1 POSCMD0 1 6 6 2 FWDT F8000A FWDTEN WINDIS PLLKEN WDTPRE WDTPOST3 WDTPOST2 WDTPOST1 WDTPOST0 ( G FPOR F8000C PWMPIN(1) HPOL(1) LPOL(1) ALTI2C1 — — — — P FICD F8000E Reserved(2) — Reserved(3) Reserved(3) — — ICS1 ICS0 / M Legend: — = unimplemented, read as ‘1’. C Note 1: These bits are available in dsPIC33FJ(16/32)MC10X devices only. ) 2: This bit is reserved for use by development tools. 1 3: These bits are reserved, program as ‘0’. 0 1 / 1 The Configuration Flash Word maps are shown in Table23-2 and Table23-3. 0 2 TABLE 23-2: CONFIGURATION FLASH WORDS FOR dsPIC33FJ16(GP/MC)10X DEVICES(1) A N File Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D Name d CONFIG2 002BFC — IESO PWMLOCK(2) PWMPIN(2) WDTWIN1 WDTWIN0 FNOSC2 FNOSC1 FNOSC0 FCKSM1 FCKSM0 OSCIOFNC(5) IOL1WAY LPOL(2) ALTI2C1 POSCMD1 POSCMD0 s CONFIG1 002BFE — Reserved(3) Reserved(3) GCP GWRP Reserved(4) HPOL(2) ICS1 ICS0 FWDTEN WINDIS PLLKEN WDTPRE WDTPOST3 WDTPOST2 WDTPOST1 WDTPOST0 P I Legend: — = unimplemented, read as ‘1’. C Note 1: During a Power-on Reset (POR), the contents of these Flash locations are transferred to the Configuration Shadow registers. 3 2: These bits are reserved in dsPIC33FJ16GP10X devices and read as ‘1’. 3 3: These bits are reserved, program as ‘0’. F 4: This bit is reserved for use by development tools and must be programmed as ‘1’. J 5: This bit is programmed to ‘0’ during final tests in the factory. 3 2 ( G  2 TABLE 23-3: CONFIGURATION FLASH WORDS FOR dsPIC33FJ32(GP/MC)10X DEVICES(1) P 0 1 / 1-20 NFaimlee Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MC 1 4 M CONFIG2 0057FC — IESO PWMLOCK(2) PWMPIN(2) WDTWIN1 WDTWIN0 FNOSC2 FNOSC1 FNOSC0 FCKSM1 FCKSM0 OSCIOFNC(5) IOL1WAY LPOL(2) ALTI2C1 POSCMD1 POSCMD0 )1 icro CONFIG1 0057FE — Reserved(3) Reserved(3) GCP GWRP Reserved(4) HPOL(2) ICS1 ICS0 FWDTEN WINDIS PLLKEN WDTPRE WDTPOST3 WDTPOST2 WDTPOST1 WDTPOST0 01 chip T LNeogteend1:: —Du r=in ugn aim Ppolewmeer-notne dR, ereseatd ( aPsO ‘R1’)., the contents of these Flash locations are transferred to the Configuration Shadow registers. /10 e 2: These bits are reserved in dsPIC33FJ32GP10X devices and read as ‘1’. 2 c hn 3: These bits are reserved, program as ‘0’. /1 olog 45:: TThhiiss bbiitt iiss rpersoegrrvaemdm foerd u tsoe ‘ 0b’y d duerivnegl ofipnmale tnets ttos oinls tahned f amctuosrty .be programmed as ‘1’. 04 y In c .

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 23-4: dsPIC33F CONFIGURATION BITS DESCRIPTION Bit Field Description GCP General Segment Code-Protect bit 1 = User program memory is not code-protected 0 = Code protection is enabled for the entire program memory space GWRP General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected IESO Two-Speed Oscillator Start-up Enable bit 1 = Starts up device with FRC, then automatically switches to the user-selected oscillator source when ready 0 = Starts up device with user-selected oscillator source PWMLOCK PWM Lock Enable bit 1 = Certain PWM registers may only be written after a key sequence 0 = PWM registers may be written without a key sequence WDTWIN<1:0> Watchdog Timer Window Select bits 11 = WDT window is 24% of WDT period 10 = WDT window is 37.5% of WDT period 01 = WDT window is 50% of WDT period 00 = WDT window is 75% of WDT period FNOSC<2:0> Oscillator Selection bits 111 = Fast RC Oscillator with Divide-by-N (FRCDIVN) 110 = Reserved; do not use 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (MS + PLL, EC + PLL) 010 = Primary Oscillator (MS, HS, EC) 001 = Fast RC Oscillator with Divide-by-N and PLL module (FRCDIVN + PLL) 000 = Fast RC Oscillator (FRC) FCKSM<1:0> Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled IOL1WAY Peripheral Pin Select Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations OSCIOFNC OSC2 Pin Function bit (except in MS and HS modes) 1 = OSC2 is a clock output 0 = OSC2 is a general purpose digital I/O pin POSCMD<1:0> Primary Oscillator Mode Select bits 11 = Primary Oscillator is disabled 10 = HS Crystal Oscillator mode (10 MHz-32 MHz) 01 = MS Crystal Oscillator mode (3 MHz-10 MHz) 00 = EC (External Clock) mode (DC-32 MHz) FWDTEN Watchdog Timer Enable bit 1 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the SWDTEN bit in the RCON register will have no effect) 0 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) WINDIS Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode  2011-2014 Microchip Technology Inc. DS70000652F-page 263

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 23-4: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Description WDTPRE Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 WDTPOST<3:0> Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 PLLKEN PLL Lock Enable bit 1 = Clock switch to PLL will wait until the PLL lock signal is valid 0 = Clock switch will not wait for the PLL lock signal ALTI2C Alternate I2C™ Pins bit 1 = I2C is mapped to SDA1/SCL1 pins 0 = I2C is mapped to ASDA1/ASCL1 pins ICS<1:0> ICD Communication Channel Select bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use PWMPIN Motor Control PWM Module Pin Mode bit 1 = PWM module pins controlled by PORT register at device Reset (tri-stated) 0 = PWM module pins controlled by PWM module at device Reset (configured as output pins) HPOL Motor Control PWM High Side Polarity bit 1 = PWM module high side output pins have active-high output polarity 0 = PWM module high side output pins have active-low output polarity LPOL Motor Control PWM Low Side Polarity bit 1 = PWM module low side output pins have active-high output polarity 0 = PWM module low side output pins have active-low output polarity DS70000652F-page 264  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 REGISTER 23-1: DEVID: DEVICE ID REGISTER R R R R R R R R DEVID<23:16>(1) bit 23 bit 16 R R R R R R R R DEVID<15:8>(1) bit 15 bit 8 R R R R R R R R DEVID<7:0>(1) bit 7 bit 0 Legend: R = Read-Only bit U = Unimplemented bit bit 23-0 DEIDV<23:0>: Device Identifier bits(1) Note 1: Refer to the “dsPIC33F Flash Programming Specification for Devices with Volatile Configuration Bits” (DS70659) for the list of device ID values. REGISTER 23-2: DEVREV: DEVICE REVISION REGISTER R R R R R R R R DEVREV<23:16>(1) bit 23 bit 16 R R R R R R R R DEVREV<15:8>(1) bit 15 bit 8 R R R R R R R R DEVREV<7:0>(1) bit 7 bit 0 Legend: R = Read-only bit U = Unimplemented bit bit 23-0 DEVREV<23:0>: Device Revision bits(1) Note 1: Refer to the “dsPIC33F Flash Programming Specification for Devices with Volatile Configuration Bits” (DS70659) for the list of device revision values.  2011-2014 Microchip Technology Inc. DS70000652F-page 265

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 23.2 On-Chip Voltage Regulator 23.3 BOR: Brown-out Reset All of the dsPIC33FJ16(GP/MC)101/102 and The Brown-out Reset (BOR) module is based on an dsPIC33FJ32(GP/MC)101/102/104 devices power internal voltage reference circuit that monitors the their core digital logic at a nominal 2.5V. This can regulated supply voltage, VCAP. The main purpose of create a conflict for designs that are required to operate the BOR module is to generate a device Reset when a at a higher typical voltage, such as 3.3V. To simplify brown-out condition occurs. Brown-out conditions are system design, all devices in the dsPIC33FJ16(GP/ generally caused by glitches on the AC mains (for MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 example, missing portions of the AC cycle waveform family incorporate an on-chip regulator that allows the due to bad power transmission lines or voltage sags device to run its core logic from VDD. due to excessive current draw when a large inductive load is turned on). The regulator provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR A BOR generates a Reset pulse, which resets the (less than 5 ohms) capacitor (such as tantalum or device. The BOR selects the clock source, based on ceramic) must be connected to the VCAP pin the device Configuration bit values (FNOSC<2:0> and (Figure23-1). This helps to maintain the stability of the POSCMD<1:0>). regulator. The recommended value for the filter capac- If an Oscillator mode is selected, the BOR activates the itor is provided in Table26-14 located in Section26.1 Oscillator Start-up Timer (OST). The system clock is “DC Characteristics”. held until OST expires. If the PLL is used, the clock is Note: It is important for low-ESR capacitors to be held until the LOCK bit (OSCCON<5>) is ‘1’. placed as close as possible to the VCAP pin. Concurrently, the PWRT Time-out (TPWRT) is applied On a POR, it takes approximately 20s for the on-chip before the internal Reset is released. If TPWRT = 0 and a crystal oscillator is being used, then a nominal delay voltage regulator to generate an output voltage. During this time, designated as TSTARTUP, code execution is of TFSCM = 100 is applied. The total delay in this case disabled. TSTARTUP is applied every time the device is TFSCM. resumes operation after any power-down. The BOR status bit (RCON<1>) is set to indicate that a BOR has occurred. The BOR circuit continues to oper- FIGURE 23-1: CONNECTIONS FOR THE ate while in Sleep or Idle modes and resets the device ON-CHIP VOLTAGE should VDD fall below the BOR threshold voltage. REGULATOR(1,2,3) 3.3V dsPIC33F VDD CEFC VCAP 10 µF Tantalum VSS Note 1: These are typical operating voltages. Refer to Table26-14 located in Section26.1 “DC Characteristics” for the full operating ranges of VDD and VCAP. 2: It is important for low-ESR capacitors to be placed as close as possible to the VCAP pin. 3: Typical VCAP pin voltage = 2.5V when VDD  VDDMIN. DS70000652F-page 266  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 23.4 Watchdog Timer (WDT) 23.4.2 SLEEP AND IDLE MODES For dsPIC33FJ16(GP/MC)101/102 and If the WDT is enabled, it will continue to run during Sleep dsPIC33FJ32(GP/MC)101/102/104 devices, the WDT or Idle modes. When the WDT time-out occurs, the is driven by the LPRC oscillator. When the WDT is device will wake the device and code execution will enabled, the clock source is also enabled. continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits 23.4.1 PRESCALER/POSTSCALER (RCON<3:2>) will need to be cleared in software after the device wakes up. The nominal WDT clock source from LPRC is 32kHz. This feeds a prescaler than can be configured for either 23.4.3 ENABLING WDT 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit. The WDT is enabled or disabled by the FWDTEN Configuration bit in the FWDT Configuration register. With a 32kHz input, the prescaler yields a nominal WDT Time-out (TWDT) period of 1ms in 5-bit mode or When the FWDTEN Configuration bit is set, the WDT is 4ms in 7-bit mode. always enabled. A variable postscaler divides down the WDT prescaler The WDT can be optionally controlled in software when output and allows for a wide range of time-out periods. the FWDTEN Configuration bit has been programmed to The postscaler is controlled by the WDTPOST<3:0> ‘0’. The WDT is enabled in software by setting the Configuration bits (FWDT<3:0>), which allow the SWDTEN control bit (RCON<5>). The SWDTEN control selection of 16 settings, from 1:1 to 1:32,768. Using the bit is cleared on any device Reset. The software WDT prescaler and postscaler, time-out periods, ranging option allows the user application to enable the WDT for from 1ms to 131 seconds, can be achieved. critical code segments and disables the WDT during non-critical segments for maximum power savings. The WDT, prescaler and postscaler are reset: Note: If the WINDIS bit (FWDT<6>) is cleared, • On any device Reset the CLRWDT instruction should be executed • On the completion of a clock switch, whether by the application software only during the invoked by software (i.e., setting the OSWEN bit last 1/4 of the WDT period. This CLRWDT after changing the NOSCx bits) or by hardware window can be determined by using a timer. (i.e., Fail-Safe Clock Monitor) If a CLRWDT instruction is executed before • When a PWRSAV instruction is executed this window, a WDT Reset occurs. (i.e., Sleep or Idle mode is entered) The WDT flag bit, WDTO (RCON<4>), is not automatically • When the device exits Sleep or Idle mode to cleared following a WDT time-out. To detect subsequent resume normal operation WDT events, the flag must be cleared in software. • By a CLRWDT instruction during normal execution Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. FIGURE 23-2: WDT BLOCK DIAGRAM All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle WDTPRE WDTPOST<3:0> SWDTEN WDT FWDTEN Wake-up RS RS 1 Prescaler Postscaler LPRC Clock (divide-by-N1) (divide-by-N2) WDT 0 Reset WINDIS WDT Window Select CLRWDT Instruction  2011-2014 Microchip Technology Inc. DS70000652F-page 267

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 23.5 In-Circuit Serial Programming™ 23.6 In-Circuit Debugger (ICSP™) When MPLAB® ICD 3 is selected as a debugger, the in- Devices can be serially programmed while in the end circuit debugging functionality is enabled. This function application circuit. This is done with two lines for clock allows simple debugging functions when used with and data and three other lines for power, ground and MPLAB IDE. Debugging functionality is controlled the programming sequence. Serial programming through the PGECx (Emulation/Debug Clock) and allows customers to manufacture boards with PGEDx (Emulation/Debug Data) pin functions. unprogrammed devices and then program the Digital Any of the three pairs of debugging clock/data pins can Signal Controller just before shipping the product. be used: Serial programming also allows the most recent • PGEC1 and PGED1 firmware or a custom firmware to be programmed. Refer to the “dsPIC33F Flash Programming • PGEC2 and PGED2 Specification for Devices with Volatile Configuration • PGEC3 and PGED3 Bits” (DS70659) for details about In-Circuit Serial To use the in-circuit debugger function of the device, Programming (ICSP). the design must implement ICSP connections to Any of the three pairs of programming clock/data pins MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In can be used: addition, when the feature is enabled, some of the resources are not available for general use. These • PGEC1 and PGED1 resources include the first 80 bytes of data RAM and • PGEC2 and PGED2 two I/O pins. • PGEC3 and PGED3 DS70000652F-page 268  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 24.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: Note: This data sheet summarizes the • The W register (with or without an address features of the dsPIC33FJ16(GP/ modifier) or file register (specified by the value of MC)101/102 and dsPIC33FJ32(GP/ ‘Ws’ or ‘f’) MC)101/102/104 devices. However, it is • The bit in the W register or file register (specified not intended to be a comprehensive by a literal value or indirectly by the contents of reference source. To complement the register ‘Wb’) information in this data sheet, refer to the latest family reference sections of the The literal instructions that involve data movement can “dsPIC33/PIC24 Family Reference use some of the following operands: Manual”, which are available from the • A literal value to be loaded into a W register or file Microchip web site (www.microchip.com). register (specified by ‘k’) The dsPIC33F instruction set is identical to that of the • The W register or file register where the literal dsPIC30F. value is to be loaded (specified by ‘Wb’ or ‘f’) Most instructions are a single program memory word However, literal instructions that involve arithmetic or (24 bits). Only three instructions require two program logical operations use some of the following operands: memory locations. • The first source operand, which is a register ‘Wb’ Each single-word instruction is a 24-bit word, divided without any address modifier into an 8-bit opcode, which specifies the instruction • The second source operand, which is a literal type and one or more operands, which further specify value the operation of the instruction. • The destination of the result (only if not the same The instruction set is highly orthogonal and is grouped as the first source operand), which is typically a into five basic categories: register ‘Wd’ with or without an address modifier • Word or byte-oriented operations The MAC class of DSP instructions can use some of the following operands: • Bit-oriented operations • Literal operations • The accumulator (A or B) to be used (required operand) • DSP operations • The W registers to be used as the two operands • Control operations • The X and Y address space prefetch operations Table24-1 shows the general symbols used in • The X and Y address space prefetch destinations describing the instructions. • The accumulator write-back destination The dsPIC33F instruction set summary in Table24-2 lists all the instructions, along with the status flags The other DSP instructions do not involve any affected by each instruction. multiplication and can include: Most word or byte-oriented W register instructions • The accumulator to be used (required) (including barrel shift instructions) have three • The source or destination operand (designated as operands: Wso or Wdo, respectively) with or without an address modifier • The first source operand, which is typically a register ‘Wb’ without any address modifier • The amount of shift specified by a W register ‘Wn’ or a literal value • The second source operand, which is typically a register ‘Ws’ with or without an address modifier The control instructions can use some of the following • The destination of the result, which is typically a operands: register ‘Wd’ with or without an address modifier • A program memory address However, word or byte-oriented file register instructions • The mode of the Table Read and Table Write have two operands: instructions • The file register specified by the value ‘f’ • The destination, which could be either the file register ‘f’ or the W0 register, which is denoted as ‘WREG’  2011-2014 Microchip Technology Inc. DS70000652F-page 269

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Most instructions are a single word. Certain double- as a NOP. Notable exceptions are the BRA (uncondi- word instructions are designed to provide all the tional/computed branch), indirect CALL/GOTO, all Table required information in these 48 bits. In the second Reads and Writes and RETURN/RETFIE instructions, word, the 8MSbs are ‘0’s. If this second word is which are single-word instructions but take two or three executed as an instruction (by itself), it will execute as cycles. Certain instructions that involve skipping over the a NOP. subsequent instruction require either two or three cycles if the skip is performed, depending on whether the The double-word instructions execute in two instruction instruction being skipped is a single-word or two-word cycles. instruction. Moreover, double-word moves require two Most single-word instructions are executed in a single cycles. instruction cycle, unless a conditional test is true, or the Program Counter is changed as a result of the instruc- Note: For more details on the instruction set, refer tion. In these cases, the execution takes two instruction to the “16-Bit MCU and DSC Programmer’s cycles with the additional instruction cycle(s) executed Reference Manual” (DS70157). TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator write-back destination address register {W13, [W13]+ = 2} bit4 4-bit bit selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0x0000...0x1FFF} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; LSb must be ‘0’ None Field does not require an entry, can be blank OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm, Wn Dividend, Divisor Working register pair (direct addressing) DS70000652F-page 270  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier Working register pair for Square instructions  {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier Working register pair for DSP instructions  {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 Working registers {W0..W15} Wnd One of 16 destination Working registers {W0..W15} Wns One of 16 source Working registers {W0..W15} WREG W0 (Working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register  { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wx X data space prefetch address register for DSP instructions  {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none} Wxd X data space prefetch destination register for DSP instructions {W4..W7} Wy Y data space prefetch address register for DSP instructions  {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Wyd Y data space prefetch destination register for DSP instructions {W4..W7}  2011-2014 Microchip Technology Inc. DS70000652F-page 271

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 24-2: INSTRUCTION SET OVERVIEW Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB 2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z 3 AND AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z 4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z 5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None 6 BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if greater than or equal 1 1 (2) None BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None BRA GT,Expr Branch if greater than 1 1 (2) None BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None BRA LE,Expr Branch if less than or equal 1 1 (2) None BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None BRA LT,Expr Branch if less than 1 1 (2) None BRA LTU,Expr Branch if unsigned less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OA,Expr Branch if Accumulator A overflow 1 1 (2) None BRA OB,Expr Branch if Accumulator B overflow 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA SA,Expr Branch if Accumulator A saturated 1 1 (2) None BRA SB,Expr Branch if Accumulator B saturated 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None 7 BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None 8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None DS70000652F-page 272  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 9 BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None 10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3) 11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) 12 BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z 13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z 14 CALL CALL lit23 Call subroutine 2 2 None CALL Wn Call indirect subroutine 1 2 None 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB 16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep 17 COM COM f f = f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z 18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z 19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z 20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z (Wb – Ws – C) 21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1 None (2 or 3) 22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1 None (2 or 3) 23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1 None (2 or 3) 24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if  1 1 None (2 or 3) 25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C 26 DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z 27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z 28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None  2011-2014 Microchip Technology Inc. DS70000652F-page 273

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV 30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV 31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 None DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indirect 1 2 None 39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z 41 IOR IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 43 LNK LNK #lit14 Link Frame Pointer 1 1 None 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z 45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd, Multiply and Accumulate 1 1 OA,OB,OAB, AWB SA,SB,SAB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB 46 MOV MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 N,Z MOV f,WREG Move f to WREG 1 1 None MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 None MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None 47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store accumulator 1 1 None DS70000652F-page 274  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 48 MPY MPY Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, Wm*Wn,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB MPY Square Wm to Accumulator 1 1 OA,OB,OAB, Wm*Wm,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB 49 MPY.N MPY.N (Multiply Wm by Wn) to Accumulator 1 1 None Wm*Wn,Acc,Wx,Wxd,Wy,Wyd 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd, Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, AWB SA,SB,SAB 51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(Ws) MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(lit5) MUL f W3:W2 = f * WREG 1 1 None 52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f = f + 1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 53 NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None 54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None W(nd):W(nd + 1) POP.S Pop Shadow Registers 1 1 All 55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None 56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep 57 RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None 58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None 59 RESET RESET Software device Reset 1 1 None 60 RETFIE RETFIE Return from interrupt 1 3 (2) None 61 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None 62 RETURN RETURN Return from Subroutine 1 3 (2) None 63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z 64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z 65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z  2011-2014 Microchip Technology Inc. DS70000652F-page 275

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None 68 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z 69 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None 70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB 71 SL SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z 72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f – WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z 73 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z 74 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z 75 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z 76 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None SWAP Wn Wn = byte swap Wn 1 1 None 77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None 78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None 79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 81 ULNK ULNK Unlink Frame Pointer 1 1 None 82 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z 83 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N DS70000652F-page 276  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 25.0 DEVELOPMENT SUPPORT 25.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2011-2014 Microchip Technology Inc. DS70000652F-page 277

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 25.2 MPLAB XC Compilers 25.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 25.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 25.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS70000652F-page 278  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 25.6 MPLAB X SIM Software Simulator 25.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 25.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 25.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 25.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2011-2014 Microchip Technology Inc. DS70000652F-page 279

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 25.11 Demonstration/Development 25.12 Third-Party Development Tools Boards, Evaluation Kits and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS70000652F-page 280  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 26.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS.......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(3).....................................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD  3.0V(3)................................................... -0.3V to +5.6V Voltage on any 5V tolerant pin with respect to VSS when VDD  3.0V(3)........................................ -0.3V to (VDD + 0.3V) Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin(2)...........................................................................................................................250 mA Maximum output current sourced and sunk by any I/O pin excluding OSCO.........................................................15 mA Maximum output current sourced and sunk by OSCO............................................................................................25 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports(2)...............................................................................................................200 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those, or any other conditions above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of the device maximum power dissipation (see Table26-2). 3: See the “Pin Diagrams” section for 5V tolerant pins.  2011-2014 Microchip Technology Inc. DS70000652F-page 281

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 26.1 DC Characteristics TABLE 26-1: OPERATING MIPS vs. VOLTAGE Max MIPS VDD Range Temp Range Characteristic (in Volts) (in °C) dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 DC5 VBOR-3.6V(1) -40°C to +85°C 16 VBOR-3.6V(1) -40°C to +125°C 16 Note 1: Overall functional device operation at VBOR < VDD < VDDMIN is ensured but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. TABLE 26-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Industrial Temperature Devices Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Extended Temperature Devices Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PIO W I/O Pin Power Dissipation: I/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W TABLE 26-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes Package Thermal Resistance, 18-pin PDIP JA 50 — °C/W 1 Package Thermal Resistance, 20-pin PDIP JA 50 — °C/W 1 Package Thermal Resistance, 28-pin SPDIP JA 50 — °C/W 1 Package Thermal Resistance, 18-pin SOIC JA 63 — °C/W 1 Package Thermal Resistance, 20-pin SOIC JA 63 — °C/W 1 Package Thermal Resistance, 28-pin SOIC JA 55 — °C/W 1 Package Thermal Resistance, 20-pin SSOP JA 90 — °C/W 1 Package Thermal Resistance, 28-pin SSOP JA 71 — °C/W 1 Package Thermal Resistance, 28-pin QFN (6x6 mm) JA 37 — °C/W 1 Package Thermal Resistance, 36-pin VTLA (5x5 mm) JA 31.1 — °C/W 1 Package Thermal Resistance, 44-pin TQFP JA 45 — °C/W 1, 2 Package Thermal Resistance, 44-pin QFN JA 32 — °C/W 1, 2 Package Thermal Resistance, 44-pin VTLA JA 30 — °C/W 1, 2 Note 1: Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations. 2: This package is available in dsPIC33FJ32(GP/MC)104 devices only. DS70000652F-page 282  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Operating Voltage DC10 Supply Voltage(3) VDD — VBOR — 3.6 V Industrial and Extended DC12 VDR RAM Data Retention Voltage(2) 1.8 — — V DC16 VPOR VDD Start Voltage — 1.75 VSS V to Ensure Internal Power-on Reset Signal DC17 SVDD VDD Rise Rate 0.024 — — V/ms 0-2.4V in 0.1s to Ensure Internal Power-on Reset Signal Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: This is the limit to which VDD may be lowered without losing RAM data. 3: Overall functional device operation at VBOR < VDD < VDDMIN is ensured but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. TABLE 26-5: ELECTRICAL CHARACTERISTICS: BROWN-OUT RESET (BOR) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic Min(1) Typ Max Units Conditions No. BO10 VBOR BOR Event on VDD Transition 2.40 2.48 2.55 V See Note 2 High-to-Low Note 1: Parameters are for design guidance only and are not tested in manufacturing. 2: Overall functional device operation at VBOR < VDD < VDDMIN is ensured but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.  2011-2014 Microchip Technology Inc. DS70000652F-page 283

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Parameter Typical(1) Max Units Conditions No. Operating Current (IDD)(2) – dsPIC33FJ16(GP/MC)10X Devices DC20d 0.7 1.7 mA -40°C DC20a 0.7 1.7 mA +25°C LPRC 3.3V DC20b 1.0 1.7 mA +85°C (32.768 kHz)(3) DC20c 1.3 1.7 mA +125°C DC21d 1.9 2.6 mA -40°C DC21a 1.9 2.6 mA +25°C 3.3V 1 MIPS(3) DC21b 1.9 2.6 mA +85°C DC21c 2.0 2.6 mA +125°C DC22d 6.5 8.5 mA -40°C DC22a 6.5 8.5 mA +25°C 3.3V 4 MIPS(3) DC22b 6.5 8.5 mA +85°C DC22c 6.5 8.5 mA +125°C DC23d 12.2 16 mA -40°C DC23a 12.2 16 mA +25°C 3.3V 10 MIPS(3) DC23b 12.2 16 mA +85°C DC23c 12.2 16 mA +125°C DC24d 16 21 mA -40°C DC24a 16 21 mA +25°C 3.3V 16 MIPS DC24b 16 21 mA +85°C DC24c 16 21 mA +125°C Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 2: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all zeroed) • CPU executing while(1) statement 3: These parameters are characterized, but not tested in manufacturing. DS70000652F-page 284  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Parameter Typical(1) Max Units Conditions No. Operating Current (IDD)(2) – dsPIC33FJ32(GP/MC)10X Devices DC20d 1 2 mA -40°C DC20a 1 2 mA +25°C LPRC 3.3V DC20b 1.1 2 mA +85°C (32.768 kHz)(3) DC20c 1.3 2 mA +125°C DC21d 1.7 3 mA -40°C DC21a 2.3 3 mA +25°C 3.3V 1 MIPS(3) DC21b 2.3 3 mA +85°C DC21c 2.4 3 mA +125°C DC22d 7 8.5 mA -40°C DC22a 7 8.5 mA +25°C 3.3V 4 MIPS(3) DC22b 7 8.5 mA +85°C DC22c 7 8.5 mA +125°C DC23d 13.2 17 mA -40°C DC23a 13.2 17 mA +25°C 3.3V 10 MIPS(3) DC23b 13.2 17 mA +85°C DC23c 13.2 17 mA +125°C DC24d 17 22 mA -40°C DC24a 17 22 mA +25°C 3.3V 16 MIPS DC24b 17 22 mA +85°C DC24c 17 22 mA +125°C Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 2: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all zeroed) • CPU executing while(1) statement 3: These parameters are characterized, but not tested in manufacturing.  2011-2014 Microchip Technology Inc. DS70000652F-page 285

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Parameter Typical(1) Max Units Conditions No. Idle Current (IIDLE): Core Off, Clock On Base Current(2) – dsPIC33FJ16(GP/MC)10X Devices DC40d 0.4 1.0 mA -40°C DC40a 0.4 1.0 mA +25°C LPRC 3.3V DC40b 0.4 1.0 mA +85°C (32.768 kHz)(3) DC40c 0.5 1.0 mA +125°C DC41d 0.5 1.1 mA -40°C DC41a 0.5 1.1 mA +25°C 3.3V 1 MIPS(3) DC41b 0.5 1.1 mA +85°C DC41c 0.8 1.1 mA +125°C DC42d 0.9 1.6 mA -40°C DC42a 0.9 1.6 mA +25°C 3.3V 4 MIPS(3) DC42b 1.0 1.6 mA +85°C DC42c 1.2 1.6 mA +125°C DC43a 1.6 2.6 mA +25°C DC43d 1.6 2.6 mA -40°C 3.3V 10 MIPS(3) DC43b 1.7 2.6 mA +85°C DC43c 2 2.6 mA +125°C DC44d 2.4 3.8 mA -40°C DC44a 2.4 3.8 mA +25°C 3.3V 16 MIPS(3) DC44b 2.6 3.8 mA +85°C DC44c 2.9 3.8 mA +125°C Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 2: Base Idle current is measured as follows: • CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail • CLKO is configured as an I/O input pin in the Configuration Word • External Secondary Oscillator (SOSC) is disabled (i.e., SOSCO and SOSCI pins are configured as digital I/O inputs) • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all zeroed) 3: These parameters are characterized, but not tested in manufacturing. DS70000652F-page 286  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Parameter Typical(1) Max Units Conditions No. Idle Current (IIDLE): Core Off, Clock On Base Current(2) – dsPIC33FJ32(GP/MC)10X Devices DC40d 0.4 1.0 mA -40°C DC40a 0.4 1.0 mA +25°C LPRC 3.3V DC40b 0.4 1.0 mA +85°C (32.768 kHz)(3) DC40c 0.5 1.0 mA +125°C DC41d 0.5 1.1 mA -40°C DC41a 0.5 1.1 mA +25°C 3.3V 1 MIPS(3) DC41b 0.5 1.1 mA +85°C DC41c 0.8 1.1 mA +125°C DC42d 0.9 1.6 mA -40°C DC42a 0.9 1.6 mA +25°C 3.3V 4 MIPS(3) DC42b 1.0 1.6 mA +85°C DC42c 1.2 1.6 mA +125°C DC43a 1.6 2.6 mA +25°C DC43d 1.6 2.6 mA -40°C 3.3V 10 MIPS(3) DC43b 1.7 2.6 mA +85°C DC43c 2.0 2.6 mA +125°C DC44d 2.4 3.8 mA -40°C DC44a 2.4 3.8 mA +25°C 3.3V 16 MIPS(3) DC44b 2.6 3.8 mA +85°C DC44c 2.9 3.8 mA +125°C Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 2: Base Idle current is measured as follows: • CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail • CLKO is configured as an I/O input pin in the Configuration Word • External Secondary Oscillator (SOSC) is disabled (i.e., SOSCO and SOSCI pins are configured as digital I/O inputs) • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all zeroed) 3: These parameters are characterized, but not tested in manufacturing.  2011-2014 Microchip Technology Inc. DS70000652F-page 287

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Parameter Typical(1) Max Units Conditions No. Power-Down Current (IPD)(2) – dsPIC33FJ16(GP/MC)10X Devices DC60d 27 250 µA -40°C DC60a 32 250 µA +25°C 3.3V Base Power-Down Current(3,4) DC60b 43 250 µA +85°C DC60c 150 500 µA +125°C DC61d 420 600 µA -40°C DC61a 420 600 µA +25°C 3.3V Watchdog Timer Current: IWDT(3,5) DC61b 530 750 µA +85°C DC61c 620 900 µA +125°C Power-Down Current (IPD)(2) – dsPIC33FJ32(GP/MC)10X Devices DC60d 27 250 µA -40°C DC60a 32 250 µA +25°C 3.3V Base Power-Down Current(3,4) DC60b 43 250 µA +85°C DC60c 150 500 µA +125°C DC61d 420 600 µA -40°C DC61a 420 600 µA +25°C 3.3V Watchdog Timer Current: IWDT(3,5) DC61b 530 750 µA +85°C DC61c 620 900 µA +125°C Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. 2: IPD (Sleep) current is measured as follows: • CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail • CLKO is configured as an I/O input pin in the Configuration Word • External Secondary Oscillator (SOSC) is disabled (i.e., SOSCO and SOSCI pins are configured as digital I/O inputs) • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • All peripheral modules are disabled (PMDx bits are all ones) • VREGS bit (RCON<8>) = 1 (i.e., core regulator is set to stand-by while the device is in Sleep mode) • On applicable devices, RTCC is disabled, plus the VREGS bit (RCON<8>) = 1 3: The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: These currents are measured on the device containing the most memory in this family. 5: These parameters are characterized, but not tested in manufacturing. DS70000652F-page 288  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-9: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Doze Parameter No. Typical(1) Max Units Conditions Ratio(2) Doze Current (IDOZE)(2) – dsPIC33FJ16(GP/MC)10X Devices DC73a 13.2 17.2 1:2 mA DC73f 4.7 6.2 1:64 mA -40°C 3.3V 16 MIPS DC73g 4.7 6.2 1:128 mA DC70a 13.2 17.2 1:2 mA DC70f 4.7 6.2 1:64 mA +25°C 3.3V 16 MIPS DC70g 4.7 6.2 1:128 mA DC71a 13.2 17.2 1:2 mA DC71f 4.7 6.2 1:64 mA +85°C 3.3V 16 MIPS DC71g 4.7 6.2 1:128 mA DC72a 13.2 17.2 1:2 mA DC72f 4.7 6.2 1:64 mA +125°C 3.3V 16 MIPS DC72g 4.7 6.2 1:128 mA Doze Current (IDOZE)(2) – dsPIC33FJ32(GP/MC)10X Devices DC73a 13.2 17.2 1:2 mA DC73f 4.7 6.2 1:64 mA -40°C 3.3V 16 MIPS DC73g 4.7 6.2 1:128 mA DC70a 13.2 17.2 1:2 mA DC70f 4.7 6.2 1:64 mA +25°C 3.3V 16 MIPS DC70g 4.7 6.2 1:128 mA DC71a 13.2 17.2 1:2 mA DC71f 4.7 6.2 1:64 mA +85°C 3.3V 16 MIPS DC71g 4.7 6.2 1:128 mA DC72a 13.2 17.2 1:2 mA DC72f 4.7 6.2 1:64 mA +125°C 3.3V 16 MIPS DC72g 4.7 6.2 1:128 mA Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. 2: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDOZE measurements are as follows: • Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all zeros) • CPU executing while(1) statement  2011-2014 Microchip Technology Inc. DS70000652F-page 289

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VIL Input Low Voltage DI10 I/O Pins VSS — 0.2VDD V DI15 MCLR VSS — 0.2VDD V DI18 I/O Pins with SDAx, SCLx VSS — 0.3 VDD V SMBus disabled DI19 I/O Pins with SDAx, SCLx VSS — 0.8 V SMBus enabled VIH Input High Voltage DI20 I/O Pins Not 5V Tolerant(4) 0.7VDD — VDD V I/O Pins 5V Tolerant(4) 0.7VDD — 5.5 V DI28 SDAx, SCLx 0.7 VDD — 5.5 V SMBus disabled DI29 SDAx, SCLx 2.1 — 5.5 V SMBus enabled ICNPU CNx Pull-up Current DI30 50 250 450 A VDD = 3.3V, VPIN = VSS IIL Input Leakage Current(2,3) DI50 I/O Pins 5V Tolerant(4) — — ±2 A VSS  VPIN  VDD, Pin at high-impedance DI51 I/O Pins Not 5V Tolerant(4) — — ±1 A VSS  VPIN  VDD, Pin at high-impedance, -40°CTA +85°C DI51a I/O Pins Not 5V Tolerant(4) — — ±2 A Shared with external reference pins, -40°CTA  +85°C DI51b I/O Pins Not 5V Tolerant(4) — — ±3.5 A VSS  VPIN  VDD, Pin at high-impedance, -40°CTA +125°C DI51c I/O Pins Not 5V Tolerant(4) — — ±8 A Analog pins shared with external reference pins, -40°CTA +125°C DI55 MCLR — — ±2 A VSS VPIN VDD DI56 OSC1 — — ±2 A VSS VPIN VDD, XT and HS modes Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See the “Pin Diagrams” section for the 5V tolerant I/O pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: Non-5V tolerant pins, VIH source > (VDD + 0.3), 5V tolerant pins, VIH source > 5.5V. Characterized but not tested. 7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. DS70000652F-page 290  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. IICL Input Low Injection Current DI60a 0 -5(5,8) — mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO and RB14 IICH Input High Injection Current DI60b 0 — +5(6,7,8) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO, RB14 and digital 5V tolerant designated pins IICT Total Input Injection Current DI60c (sum of all I/O and control -20(9) — +20(9) mA Absolute instantaneous pins) sum of all ± input injection currents from all I/O pins (| IICL + | IICH |)  IICT Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See the “Pin Diagrams” section for the 5V tolerant I/O pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: Non-5V tolerant pins, VIH source > (VDD + 0.3), 5V tolerant pins, VIH source > 5.5V. Characterized but not tested. 7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested.  2011-2014 Microchip Technology Inc. DS70000652F-page 291

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA+125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Output Low Voltage I/O Pins: IOL  6 mA, VDD = 3.3V, — — 0.4 V 4x Sink Driver Pins – All Pins See Note 1 DO10 VOL excluding OSCO Output Low Voltage IOL  10 mA, VDD = 3.3V, I/O Pins: — — 0.4 V See Note 1 8x Sink Driver Pins – OSCO Output High Voltage I/O Pins: IOL-6 mA, VDD = 3.3V, 2.4 — — V 4x Source Driver Pins – All See Note 1 DO20 VOH Pins excluding OSCO Output High Voltage IOL-10 mA, VDD = 3.3V, I/O Pins: 2.4 — — V See Note 1 8x Source Driver Pins – OSCO Output High Voltage IOH-12 mA, VDD = 3.3V, 1.5 — — I/O Pins: See Note 1 4x Source Driver Pins – All IOH-11 mA, VDD = 3.3V, Pins excluding OSCO 2.0 — — V See Note 1 IOH-3 mA, VDD = 3.3V, 3.0 — — See Note 1 DO20A VOH1 Output High Voltage IOH-16 mA, VDD = 3.3V, 1.5 — — I/O Pins: See Note 1 8x Source Driver Pins – OSCO IOH-12 mA, VDD = 3.3V, 2.0 — — V See Note 1 IOH-4 mA, VDD = 3.3V, 3.0 — — See Note 1 Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. DS70000652F-page 292  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(3) Min Typ(1) Max Units Conditions No. Program Flash Memory D130a EP Cell Endurance 10,000 — — E/W -40C to +125C D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132b VPEW VDD for Self-Timed Write VMIN — 3.6 V VMIN = Minimum operating voltage D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated D135 IDDP Supply Current during — 10 — mA Programming D137a TPE Page Erase Time 20.1 — 26.5 ms TPE = 168517 FRC cycles, TA = +85°C, See Note 2 D137b TPE Page Erase Time 19.5 — 27.3 ms TPE = 168517 FRC cycles, TA = +125°C, See Note 2 D138a TWW Word Write Cycle Time 47.4 — 49.3 µs TWW = 355 FRC cycles, TA = +85°C, See Note 2 D138b TWW Word Write Cycle Time 47.4 — 49.3 µs TWW = 355 FRC cycles, TA = +125°C, See Note 2 Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max). This parameter depends on the FRC accuracy (see Table26-18) and the value of the FRC Oscillator Tuning register (see Register8-3). For complete details on calculating the Minimum and Maximum time, see Section5.3 “Programming Operations”. 3: These parameters are ensured by design, but are not characterized or tested in manufacturing. TABLE 26-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA+125°C for Extended Param Symbol Characteristics Min Typ Max Units Comments No. — CEFC External Filter Capacitor 4.7 10 — µF Capacitor must be low Value(1) series resistance (< 5 ohms) Note 1: Typical VCAP voltage = 2.5V when VDD  VDDMIN.  2011-2014 Microchip Technology Inc. DS70000652F-page 293

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 26.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 family AC characteristics and timing parameters. TABLE 26-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°CTA +85°C for Industrial AC CHARACTERISTICS -40°CTA +125°C for Extended Operating voltage VDD range as described in Section26.1 “DC Characteristics”. FIGURE 26-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSC2 VSS 15 pF for OSC2 output TABLE 26-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol Characteristic Min Typ Max Units Conditions No. DO50 COSC2 OSC2/SOSC2 Pin — — 15 pF In MS and HS modes when external clock is used to drive OSC1 DO56 CIO All I/O Pins and OSC2 — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode DS70000652F-page 294  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 26-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symb Characteristic Min Typ(1) Max Units Conditions No. OS10 FIN External CLKI Frequency DC — 32 MHz EC (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency 3.0 — 10 MHz MS 10 — 32 MHz HS 31 — 33 kHz SOSC OS20 TOSC TOSC = 1/FOSC 31.25 — DC ns OS25 TCY Instruction Cycle Time(2,4) 62.5 — DC ns OS30 TosL, External Clock in (OSC1)(5) 0.45 x TOSC — — ns EC TosH High or Low Time OS31 TosR, External Clock in (OSC1)(5) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(3,5) — 6 10 ns OS41 TckF CLKO Fall Time(3,5) — 6 10 ns OS42 GM External Oscillator 14 16 18 mA/V VDD = 3.3V, Transconductance(4) TA = +25°C Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. 4: These parameters are characterized by similarity, but are tested in manufacturing at FIN = 32 MHz only. 5: These parameters are characterized by similarity, but are not tested in manufacturing.  2011-2014 Microchip Technology Inc. DS70000652F-page 295

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-17: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS50 FPLLI PLL Voltage Controlled Oscillator 3.0 — 8 MHz ECPLL and MSPLL modes (VCO) Input Frequency Range(2) OS51 FSYS On-Chip VCO System 12 — 32 MHz Frequency(3) OS52 TLOCK PLL Start-up Time (Lock Time)(3) — — 2 mS OS53 DCLK CLKO Stability (Jitter)(3) -2 1 +2 % Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized by similarity, but are tested in manufacturing at 7.7 MHz input only. 3: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is based on clock cycle by clock cycle measurements. The effective jitter for individual time bases, or communi- cation clocks used by the user application, are derived from dividing the CLKO stability specification by the square root of “N” (where “N” is equal to FOSC, divided by the peripheral data rate clock). For example, if FOSC = 32 MHz and the SPI bit rate is 5 MHz, the effective jitter of the SPI clock is equal to: DCLK 2% -------------- = ---------- = 0.79% 32 2.53 ------ 5 TABLE 26-18: AC CHARACTERISTICS: INTERNAL FAST RC (FRC) ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. Internal FRC Accuracy @ 7.37 MHz(1) F20a FRC -2 ±0.25 +2 % -40°C  TA -10°C VDD 3.0-3.6V F20b FRC -1 ±0.25 +1 % -10°C  TA +85°C VDD 3.0-3.6V F20c FRC -5 ±0.25 +5 % +85°C  TA +125°C VDD 3.0-3.6V Note 1: Frequency is calibrated at +25°C and 3.3V. TUNx bits may be used to compensate for temperature drift. TABLE 26-19: INTERNAL LOW-POWER RC (LPRC) ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. LPRC @ 32.768 kHz(1,2) F21a LPRC -30 ±10 +20 % -40°C  TA -10°C VDD 3.0-3.6V F21b LPRC -20 ±10 +30 % -10°C  TA +85°C VDD 3.0-3.6V F21c LPRC -35 ±10 +35 % +85°C  TA +125°C VDD 3.0-3.6V Note 1: Change of LPRC frequency as VDD changes. 2: LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT1). See Section23.4 “Watchdog Timer (WDT)” for more information. DS70000652F-page 296  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-3: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure26-1 for load conditions. TABLE 26-20: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(2) Min Typ(1) Max Units Conditions No. DO31 TIOR Port Output Rise Time — 10 25 ns DO32 TIOF Port Output Fall Time — 10 25 ns DI35 TINP INTx Pin High or Low Time (input) 25 — — ns DI40 TRBP CNx High or Low Time (input) 2 — — TCY Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: These parameters are characterized, but are not tested in manufacturing.  2011-2014 Microchip Technology Inc. DS70000652F-page 297

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD SY12 MCLR Internal SY10 POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure26-1 for load conditions. TABLE 26-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symb Characteristic(1) Min Typ(2) Max Units Conditions No. SY10 TMCL MCLR Pulse Width (low) 2 — — s SY11 TPWRT Power-up Timer Period — 64 — ms SY12 TPOR Power-on Reset Delay 3 10 30 s SY13 TIOZ I/O High-Impedance from MCLR — — 1.2 s Low or Watchdog Timer Reset SY20 TWDT1 Watchdog Timer Time-out — — — ms See Section23.4 “Watchdog Period Timer (WDT)” and LPRC Parameter F21a (Table26-19). SY30 TOST Oscillator Start-up Time — 1024 * TOSC — — TOSC = OSC1 period SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 900 s Note 1: These parameters are characterized but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. DS70000652F-page 298  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-5: TIMER1/2/3 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRx Note: Refer to Figure26-1 for load conditions. TABLE 26-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(2) Min Typ Max Units Conditions No. TA10 TTXH T1CK High Synchronous Greater of: — — ns Must also meet Time mode 20 or Parameter TA15, (TCY + 20)/N N = prescale value Asynchronous 35 — — ns (1, 8, 64, 256) TA11 TTXL T1CK Low Synchronous Greater of: — — ns Must also meet Time mode 20 ns or Parameter TA15, (TCY + 20)/N N = prescale value Asynchronous 10 — — ns (1, 8, 64, 256) TA15 TTXP T1CK Input Synchronous Greater of: — — ns N = prescale value Period mode 40 or (1, 8, 64, 256) (2 TCY + 40)/N OS60 Ft1 SOSC1/T1CK Oscillator DC — 50 kHz Input Frequency Range (oscillator enabled by setting the TCS (T1CON<1>) bit) TA20 TCKEXTMRL Delay from External T1CK 0.75 TCY + 40 — 1.75 TCY + 40 ns Clock Edge to Timer Increment Note 1: Timer1 is a Type A. 2: These parameters are characterized by similarity, but are not tested in manufacturing.  2011-2014 Microchip Technology Inc. DS70000652F-page 299

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 T ABLE 26-23: TIMER2/4 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. TB10 TtxH TxCK High Synchronous Greater of: — — ns Must also meet Time mode 20 or Parameter TB15, (TCY + 20)/N N = prescale value (1, 8, 64, 256) TB11 TtxL TxCK Low Synchronous Greater of: — — ns Must also meet Time mode 20 or Parameter TB15, (TCY + 20)/N N = prescale value (1, 8, 64, 256) TB15 TtxP TxCK Input Synchronous Greater of: — — ns N = prescale value Period mode 40 or (1, 8, 64, 256) (2 TCY + 40)/N TB20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns Clock Edge to Timer Increment Note 1: These parameters are characterized, but are not tested in manufacturing. TABLE 26-24: TIMER3/5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. TC10 TtxH TxCK High Synchronous TCY + 20 — — ns Must also meet Time Parameter TC15 TC11 TtxL TxCK Low Synchronous TCY + 20 — — ns Must also meet Time Parameter TC15 TC15 TtxP TxCK Input Synchronous, 2 TCY + 40 — — ns N = prescale value Period with Prescaler (1, 8, 64, 256) TC20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns Clock Edge to Timer Increment Note 1: These parameters are characterized, but are not tested in manufacturing. DS70000652F-page 300  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-6: INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure26-1 for load conditions. TABLE 26-25: INPUT CAPTURE x (ICx) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Max Units Conditions No. IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns With Prescaler 10 — ns IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns With Prescaler 10 — ns IC15 TccP ICx Input Period (TCY + 40)/N — ns N = prescale value (1, 4, 16) Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.  2011-2014 Microchip Technology Inc. DS70000652F-page 301

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-7: OUTPUT COMPARE x (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure26-1 for load conditions. TABLE 26-26: OUTPUT COMPARE x (OCx) MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. OC10 TccF OCx Output Fall Time — — — ns See Parameter DO32 OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31 Note 1: These parameters are characterized by similarity, but are not tested in manufacturing. FIGURE 26-8: OCx/PWMx MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 OCx Active Tri-State TABLE 26-27: SIMPLE OCx/PWMx MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. OC15 TFD Fault Input to PWMx I/O — — TCY + 20 ns ns Change OC20 TFLT Fault Input Pulse Width TCY + 20 ns — — ns Note 1: These parameters are characterized by similarity, but are not tested in manufacturing. DS70000652F-page 302  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-9: MOTOR CONTROL PWMx MODULE FAULT TIMING CHARACTERISTICS MP30 FLTA1 MP20 PWMx See Note 1 Note 1: For the logic state after a Fault, refer to the FAOVxH:FAOVxL bits in the PxFLTACON register. FIGURE 26-10: MOTOR CONTROL PWMx MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure26-1 for load conditions. TABLE 26-28: MOTOR CONTROL PWMx MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. MP10 TFPWM PWM Output Fall Time — — — ns See Parameter DO32 MP11 TRPWM PWM Output Rise Time — — — ns See Parameter DO31 MP20 TFD Fault Input  to PWM — — 50 ns I/O Change MP30 TFH Minimum Pulse Width 50 — — ns Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.  2011-2014 Microchip Technology Inc. DS70000652F-page 303

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-29: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY FOR dsPIC33FJ16(GP/MC)10X Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Master Master Slave Maximum Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP Data Rate (Half-Duplex) (Full-Duplex) (Full-Duplex) 15 MHz Table26-30 — — 0,1 0,1 0,1 10 MHz — Table26-31 — 1 0,1 1 10 MHz — Table26-32 — 0 0,1 1 15 MHz — — Table26-33 1 0 0 11 MHz — — Table26-34 1 1 0 15 MHz — — Table26-35 0 1 0 11 MHz — — Table26-36 0 0 0 FIGURE 26-11: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 Note: Refer to Figure26-1 for load conditions. DS70000652F-page 304  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-12: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 Note: Refer to Figure26-1 for load conditions. TABLE 26-30: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCKx Frequency — — 15 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdiV2scH, SDOx Data Output Setup to 30 — — ns TdiV2scL First SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2011-2014 Microchip Technology Inc. DS70000652F-page 305

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-13: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP40 SDIx MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure26-1 for load conditions. TABLE 26-31: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCKx Frequency — — 10 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2sc, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70000652F-page 306  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-14: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure26-1 for load conditions. TABLE 26-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCKx Frequency — — 10 MHz -40°C to +125°C, see Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2011-2014 Microchip Technology Inc. DS70000652F-page 307

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-15: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X SP60 SSx SP50 SP52 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure26-1 for load conditions. DS70000652F-page 308  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input Frequency — — 15 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2011-2014 Microchip Technology Inc. DS70000652F-page 309

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-16: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X SP60 SSx SP50 SP52 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SP52 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure26-1 for load conditions. DS70000652F-page 310  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input Frequency — — 11 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2011-2014 Microchip Technology Inc. DS70000652F-page 311

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-17: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure26-1 for load conditions. DS70000652F-page 312  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input Frequency — — 15 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2011-2014 Microchip Technology Inc. DS70000652F-page 313

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-18: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP35 SP72 SP73 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure26-1 for load conditions. DS70000652F-page 314  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input Frequency — — 11 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2011-2014 Microchip Technology Inc. DS70000652F-page 315

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-37: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY FOR dsPIC33FJ32(GP/MC)10X Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Master Master Slave Maximum Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP Data Rate (Half-Duplex) (Full-Duplex) (Full-Duplex) 15 MHz Table26-30 — — 0,1 0,1 0,1 9 MHz — Table26-31 — 1 0,1 1 9 MHz — Table26-32 — 0 0,1 1 15 MHz — — Table26-33 1 0 0 11 Mhz — — Table26-34 1 1 0 15 MHz — — Table26-35 0 1 0 11 MHz — — Table26-36 0 0 0 FIGURE 26-19: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 Note: Refer to Figure26-1 for load conditions. DS70000652F-page 316  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-20: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 Note: Refer to Figure26-1 for load conditions. TABLE 26-38: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCKx Frequency — — 15 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdiV2scH, SDOx Data Output Setup to 30 — — ns TdiV2scL First SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2011-2014 Microchip Technology Inc. DS70000652F-page 317

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-21: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP40 SDIx MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure26-1 for load conditions. TABLE 26-39: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCKx Frequency — — 9 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2sc, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70000652F-page 318  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-22: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure26-1 for load conditions. TABLE 26-40: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCKx Frequency — — 9 MHz -40°C to +125°C, see Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2011-2014 Microchip Technology Inc. DS70000652F-page 319

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-23: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure26-1 for load conditions. DS70000652F-page 320  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-41: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input Frequency — — 15 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2011-2014 Microchip Technology Inc. DS70000652F-page 321

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-24: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SP52 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure26-1 for load conditions. DS70000652F-page 322  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-42: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input Frequency — — 11 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2011-2014 Microchip Technology Inc. DS70000652F-page 323

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-25: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP35 SP72 SP73 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure26-1 for load conditions. DS70000652F-page 324  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-43: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input Frequency — — 15 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — —w ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2011-2014 Microchip Technology Inc. DS70000652F-page 325

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-26: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP35 SP72 SP73 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure26-1 for load conditions. DS70000652F-page 326  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-44: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input Frequency — — 11 MHz See Note 3 SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2011-2014 Microchip Technology Inc. DS70000652F-page 327

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-27: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Start Stop Condition Condition Note: Refer to Figure26-1 for load conditions. FIGURE 26-28: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM21 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure26-1 for load conditions. DS70000652F-page 328  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 T ABLE 26-45: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol Characteristic Min(1) Max Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 100 ns IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) 40 — ns IM26 THD:DAT Data Input 100 kHz mode 0 — s Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(2) 0.2 — s IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — s Only relevant for Setup Time 400 kHz mode TCY/2 (BRG + 1) — s Repeated Start 1 MHz mode(2) TCY/2 (BRG + 1) — s condition IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — s After this period the first Hold Time 400 kHz mode TCY/2 (BRG + 1) — s clock pulse is generated 1 MHz mode(2) TCY/2 (BRG + 1) — s IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — s Setup Time 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns 1 MHz mode(2) TCY/2 (BRG + 1) — ns IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns from Clock 400 kHz mode — 1000 ns 1 MHz mode(2) — 400 ns IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be 400 kHz mode 1.3 — s free before a new 1 MHz mode(2) 0.5 — s transmission can start IM50 CB Bus Capacitive Loading — 400 pF IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 3 Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to “Inter-Integrated Circuit (I2C™)” (DS70195) in the “dsPIC33/PIC24 Family Reference Manual”. Please see the Microchip web site for the latest “dsPIC33/ PIC24 Family Reference Manual” sections. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: Typical value for this parameter is 130 ns.  2011-2014 Microchip Technology Inc. DS70000652F-page 329

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-29: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS34 IS30 IS33 SDAx Start Stop Condition Condition FIGURE 26-30: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS70000652F-page 330  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-46: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param. Symbol Characteristic Min Max Units Conditions IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — s Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(1) 0 0.3 s IS30 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated Setup Time 400 kHz mode 0.6 — s Start condition 1 MHz mode(1) 0.25 — s IS31 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first Hold Time 400 kHz mode 0.6 — s clock pulse is generated 1 MHz mode(1) 0.25 — s IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — s Setup Time 400 kHz mode 0.6 — s 1 MHz mode(1) 0.6 — s IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — ns 1 MHz mode(1) 250 ns IS40 TAA:SCL Output Valid 100 kHz mode 0 3500 ns from Clock 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start 1 MHz mode(1) 0.5 — s IS50 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).  2011-2014 Microchip Technology Inc. DS70000652F-page 331

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 T ABLE 26-47: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V(6) (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply(2,4) Greater of: — Lesser of: V VDD – 0.3 VDD + 0.3 or 2.9 or 3.6 AD02 AVSS Module VSS Supply(2,5) VSS – 0.3 — VSS + 0.3 V AD09 IAD Operating Current — 7.0 9.0 mA See Note 1 Analog Input AD12 VINH Input Voltage Range VINL — AVDD V This voltage reflects S&H VINH(2) Channels 0, 1, 2 and 3 (CH0-CH3), positive input AD13 VINL Input Voltage Range AVSS — AVSS + 1V V This voltage reflects S&H VINL(2) Channels 0, 1, 2 and 3 (CH0-CH3), negative input AD17 RIN Recommended — — 200  Impedance of Analog Voltage Source(3) Note 1: These parameters are not characterized or tested in manufacturing. 2: These parameters are characterized, but are not tested in manufacturing. 3: These parameters are assured by design, but are not characterized or tested in manufacturing. 4: This pin may not be available on all devices; in which case, this pin will be connected to VDD internally. See the “Pin Diagrams” section for availability. 5: This pin may not be available on all devices; in which case, this pin will be connected to VSS internally. See the “Pin Diagrams” section for availability. 6: Overall functional device operation at VBOR < VDD < VDDMIN is ensured but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. DS70000652F-page 332  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-48: 10-BIT ADC MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V(4) (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. 10-Bit ADC Accuracy – Measurements with AVDD/AVSS(3) AD20b Nr Resolution 10 Data Bits bits AD21b INL Integral Nonlinearity -1 — +1 LSb VINL = AVSS = 0V, AVDD = 3.6V AD22b DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = 0V, AVDD = 3.6V AD23b GERR Gain Error 3 7 15 LSb VINL = AVSS = 0V, AVDD = 3.6V AD24b EOFF Offset Error 1.5 3 7 LSb VINL = AVSS = 0V, AVDD = 3.6V AD25b — Monotonicity — — — — Guaranteed(1) Dynamic Performance (10-Bit Mode)(2) AD30b THD Total Harmonic Distortion — — -64 dB AD31b SINAD Signal to Noise and 57 58.5 — dB Distortion AD32b SFDR Spurious Free Dynamic 72 — — dB Range AD33b FNYQ Input Signal Bandwidth — — 550 kHz AD34b ENOB Effective Number of Bits 9.16 9.4 — bits Note 1: The Analog-to-Digital conversion result never decreases with an increase in the input voltage and has no missing codes. 2: These parameters are characterized by similarity, but are not tested in manufacturing. 3: These parameters are characterized, but are tested at 20 ksps only. 4: Overall functional device operation at VBOR < VDD < VDDMIN is guaranteed but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN  2011-2014 Microchip Technology Inc. DS70000652F-page 333

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-31: ADC CONVERSION TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP AD61 AD60 TSAMP AD55 AD55 DONE ADxIF 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33/PIC24 Family Reference Manual”. 3 – Software clears ADxCON. SAMP to start conversion. 4 – Sampling ends, conversion sequence starts. 5 –– CCoonnvveerrtt bbiitt 99.. 6 – Convert bit 8. 7 – Convert bit 0. 8 – One TAD for end of conversion. FIGURE 26-32: ADC CONVERSION TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP TSAMP AD55 AD55 TSAMP AD55 ADxIF DONE 1 2 3 4 5 6 7 3 4 5 6 8 1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. TSAMP is described in 6 – One TAD for end of conversion. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33/PIC24 Family Reference Manual”. 7 – Begin conversion of next channel. 3 – Convert bit 9. 8 – Sample for time specified by SAMC<4:0>. 4 – Convert bit 8. DS70000652F-page 334  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-49: 10-BIT ADC CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min. Typ(1) Max. Units Conditions No. Clock Parameters(2) AD50 TAD ADC Clock Period 76 — — ns AD51 tRC ADC Internal RC Oscillator Period — 250 — ns Conversion Rates AD55 tCONV Conversion Time — 12 TAD — — AD56 FCNV Throughput Rate — — 1.1 Msps AD57 TSAMP Sample Time 2.0 TAD — — — Timing Parameters AD60 tPCS Conversion Start from Sample 2.0 TAD — 3.0 TAD — Auto-Convert Trigger Trigger(1) (SSRC<2:0> = 111) not selected AD61 tPSS Sample Start from Setting 2.0 TAD — 3.0 TAD — Sample (SAMP) bit(1) AD62 tCSS Conversion Completion to — 0.5 TAD — — Sample Start (ASAM = 1)(1) AD63 tDPU Time to Stabilize Analog Stage — — 20 s from ADC Off to ADC On(1) Note 1: These parameters are characterized but not tested in manufacturing. 2: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures.  2011-2014 Microchip Technology Inc. DS70000652F-page 335

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-50: COMPARATOR TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. 300 TRESP Response Time(1,2) — 150 400 ns 301 TMC2OV Comparator Mode Change — — 10 s to Output Valid(1) 302 TON2OV Comparator Enabled to — — 10 µs Output Valid(1) Note 1: Parameters are characterized but not tested. 2: Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 26-51: COMPARATOR MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°CTA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. D300 VIOFF Input Offset Voltage(1) -20 ±10 20 mV D301 VICM Input Common-Mode Voltage(1) 0 — AVDD – 1.5V V D302 CMRR Common-Mode Rejection Ratio(1) -54 — — dB D305 IVREF Internal Voltage Reference(1) 1.116 1.24 1.364 V Note 1: Parameters are characterized but not tested. TABLE 26-52: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. VR310 TSET Settling Time(1) — — 10 s Note 1: Settling time measured while CVRR = 1 and the CVR<3:0> bits transition from ‘0000’ to ‘1111’. DS70000652F-page 336  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 26-53: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions:3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. VRD310 CVRES Resolution CVRSRC/24 — CVRSRC/32 LSb VRD311 CVRAA Absolute Accuracy — — 0.5 LSb VRD312 CVRUR Unit Resistor Value (R) — 2k —  TABLE 26-54: CTMU CURRENT SOURCE SPECIFICATIONS Standard Operating Conditions:3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. CTMU Current Source CTMUI1 IOUT1 Base Range(1) 320 550 980 na IRNG<1:0> bits (CTMUICON<9:8>) = 0b01 CTMUI2 IOUT2 10x Range(1) 3.2 5.5 9.8 µA IRNG<1:0> bits (CTMUICON<9:8>) = 0b10 CTMUI3 IOUT3 100x Range(1) 32 55 98 µA IRNG<1:0> bits (CTMUICON<9:8>) = 0b11 Internal Diode CTMUFV1 VF Forward Voltage(2) — 0.77 — V IRNG<1:0> bits (CTMUICON<9:8>) = 0b11 @ +25°C CTMUFV2 VFVR Forward Voltage — -1.38 — mV/ºC IRNG<1:0> bits (CTMUICON<9:8>) = 0b11 Rate(2) Note 1: Nominal value at center point of current trim range (ITRIM<5:0> bits (CTMUICON<15:10>) = 0b000000). 2: ADC module configured for conversion speed of 500 ksps. Parameters are characterized but not tested in manufacturing.  2011-2014 Microchip Technology Inc. DS70000652F-page 337

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 FIGURE 26-33: FORWARD VOLTAGE VERSUS TEMPERATURE 0.900 00..885500 VF @ IOUT = 55 µA 00..880000 V) Forward Voltage @ +25°C e ( 00..775500 VF= 0.77 g Forward Voltage Rate a olt VFVR = -1.38 mV/°C V 00..770000 d r a w r Fo 0.650 0.600 0.550 0.500 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 4 3 3 2 2 1 1 - 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 0 0 1 1 2 2 - - - - - - - 1 1 1 1 1 1 Temperature (°C) Note: This graph is a statistical summary based on a limited number of samples and this data is characterized but not tested in manufacturing. DS70000652F-page 338  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 27.0 HIGH-TEMPERATURE ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 family electrical characteristics for devices operating in an ambient temperature range of -40°C to +150°C. The specifications between -40°C to +150°C are identical to those shown in Section26.0 “Electrical Characteristics” for operation between -40°C to +125°C, with the exception of the parameters listed in this section. Parameters in this section begin with an H, which denotes: High temperature. For example, Parameter DC10 in Section26.0 “Electrical Characteristics” is the Industrial and Extended temperature equivalent of HDC10. Absolute maximum ratings for the dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 high- temperature devices are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias(3).........................................................................................................-40°C to +150°C Storage temperature.............................................................................................................................. -65°C to +160°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(4) ....................................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(4) ....................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD  3.0V(4) .................................................... -0.3V to 5.6V Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin(2)...........................................................................................................................250 mA Maximum junction temperature.............................................................................................................................+155°C Maximum current sourced/sunk by any 4x I/O pin....................................................................................................4 mA Maximum current sourced/sunk by any 8x I/O pin....................................................................................................8 mA Maximum current sunk by all ports combined ........................................................................................................80 mA Maximum current sourced by all ports combined(2)................................................................................................80 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress rating only and functional operation of the device at those, or any other conditions above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods can affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table27-2). 3: AEC-Q100 reliability testing for devices intended to operate at +150°C is 1,000 hours. Any design in which the total operating time from +125°C to +150°C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc. 4: Refer to the “Pin Diagrams” section for 5V tolerant pins. Preliminary  2011-2014 Microchip Technology Inc. DS70000652F-page 339

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 27.1 High-Temperature DC Characteristics TABLE 27-1: OPERATING MIPS VS. VOLTAGE Max MIPS VDD Range Temperature Range Characteristic (in Volts) (in °C) dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 HDC5 VBOR – 3.6V(1) -40°C to +150°C 5 Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc., may have degraded performances below VDDMIN. TABLE 27-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit High Temperature Devices Operating Junction Temperature Range TJ -40 — +155 °C Operating Ambient Temperature Range TA -40 — +150 °C Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W I/O Pin Power Dissipation: I/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W TABLE 27-3: DC CHARACTERISTICS: OPERATING CURRENT (IDD)) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C for High Temperature Parameter Typical Max Units Conditions No. Operating Current (IDD) – dsPIC33FJ16(GP/MC)10X Devices DC20e 1.3 1.7 mA 3.3V LPRC (32.768 kHz) DC22e 7.0 8.5 mA 3.3V 5 MIPS Preliminary DS70000652F-page 340  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 27-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD)) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C for High Temperature Parameter Typical Max Units Conditions No. Operating Current (IDD) – dsPIC33FJ32(GP/MC)10X Devices DC20e 1.3 2.0 mA 3.3V LPRC (32.768 kHz) DC22e 7.25 8.5 mA 3.3V 5 MIPS TABLE 27-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C for High Temperature Parameter Typical Max Units Conditions No. Idle Current (IIDLE) – dsPIC33FJ16(GP/MC)10X Devices DC40e 0.5 1.0 mA 3.3V LPRC (32.768 kHz) DC22e 1.2 1.6 mA 3.3V 5 MIPS Idle Current (IIDLE) – dsPIC33FJ32(GP/MC)10X Devices DC40e 0.5 1.0 mA 3.3V LPRC (32.768 kHz) DC22e 1.4 1.8 mA 3.3V 5 MIPS TABLE 27-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C for High Temperature Parameter Typical(1) Max Units Conditions No. Power-Down Current (IPD) – dsPIC33FJXX(GP/MC)10X DC60e 500 1000 A 3.3V Base Power-Down Current DC61e 650 1000 A 3.3V Watchdog Timer Current: IWDT Note 1: Data in the Typical column is 3.3V unless otherwise stated. Preliminary  2011-2014 Microchip Technology Inc. DS70000652F-page 341

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE 27-7: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +150°C for High Temperature Parameter Typical(1) Max Doze Ratio Units Conditions No. Doze Current (IDOZE) – dsPIC33FJ16(GP/MC)10X Devices DC74a 4.3 7.2 1:2 mA 3.3V 5 MIPS DC74f 1.6 6.2 1:64 mA 3.3V 5 MIPS DC74g 1.5 6.2 1:128 mA 3.3V 5 MIPS Doze Current (IDOZE) – dsPIC33FJ32(GP/MC)10X Devices DC74a 4.7 7.2 1:2 mA 3.3V 5 MIPS DC74f 1.9 6.2 1:64 mA 3.3V 5 MIPS DC74g 1.4 6.2 1:128 mA 3.3V 5 MIPS Note 1: Data in the Typical column is 3.3V unless otherwise stated. TABLE 27-8: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. Program Flash Memory HD130 EP Cell Endurance 10,000 — — E/W -40C to +150C(2) HD134 TRETD Characteristic Retention 20 — — Year 1000 E/W cycles or less and no other specifications are violated Note 1: These parameters are assured by design, but are not characterized or tested in manufacturing. 2: Programming of the Flash memory is allowed up to +150°C. TABLE 27-9: AC CHARACTERISTICS: INTERNAL FAST RC (FRC) ACCURACY AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Param Characteristic Min Typ Max Units Conditions No. Internal FRC Accuracy @ 7.37 MHz(1) F20d FRC -8 ±0.25 +8 % -40°C  TA +150°C VDD 3.0-3.6V Note 1: Frequency is calibrated at +25°C and 3.3V. TUNx bits may be used to compensate for temperature drift. TABLE 27-10: INTERNAL LOW-POWER RC (LPRC) ACCURACY AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Param Characteristic Min Typ Max Units Conditions No. LPRC @ 32.768 kHz(1,2) F21c LPRC -40 ±10 +40 % -40°C  TA +150°C VDD 3.0-3.6V Note 1: Change of LPRC frequency as VDD changes. 2: LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT1). See Section23.4 “Watchdog Timer (WDT)” for more information. Preliminary DS70000652F-page 342  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX dsPIC33FJ16GP XXXXXXXXXXXXXXXXX 101-E/P e3 YYWWNNN 1330235 18-Lead SOIC Example XXXXXXXXXXXX dsPIC33FJ16 XXXXXXXXXXXX GP101-E/SOe3 XXXXXXXXXXXX YYWWNNN 1310017 20-Lead PDIP Example XXXXXXXXXXXXXXXXX dsPIC33FJ16MC XXXXXXXXXXXXXXXXX 101-E/Pe3 YYWWNNN 1330235 20-Lead SSOP Example XXXXXXXXXXX dsPIC33FJ16 XXXXXXXXXXX MC101-I/SSe3 YYWWNNN 1330235 20-Lead SOIC Example XXXXXXXXXXXXXX dsPIC33FJ16 XXXXXXXXXXXXXX MC101-I/SOe3 XXXXXXXXXXXXXX 1310017 YYWWNNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information.  2011-2014 Microchip Technology Inc. DS70000652F-page 343

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 28.1 Package Marking Information (Continued) 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX dsPIC33FJ16MC XXXXXXXXXXXXXXXXX 102-E/SPe3 YYWWNNN 1330235 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX dsPIC33FJ16MC XXXXXXXXXXXXXXXXXXXX 102-E/SOe3 XXXXXXXXXXXXXXXXXXXX 1330235 YYWWNNN 28-Lead SSOP Example XXXXXXXXXXXX 33FJ16MC XXXXXXXXXXXX 102-E/SSe3 YYWWNNN 1330235 28-Lead QFN Example XXXXXXXX 33FJ16MC XXXXXXXX 102/MLe3 YYWWNNN 1330235 36-Lead VTLA Example XXXXXXXX 33FJ16MC XXXXXXXX 102/TLe3 YYWWNNN 1330235 DS70000652F-page 344  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 28.1 Package Marking Information (Continued) 44-Lead QFN Example XXXXXXXXXX dsPIC33FJ XXXXXXXXXX 32MC104 XXXXXXXXXX -E/ML e3 YYWWNNN 1330235 44-Lead TQFP Example XXXXXXXXXX dsPIC33FJ XXXXXXXXXX 32MC104 XXXXXXXXXX -E/PTe3 YYWWNNN 1330235 44-Lead VTLA Example XXXXXXXX 33FJ32MC XXXXXXXX 104/TLe3 YYWWNNN 1330235  2011-2014 Microchip Technology Inc. DS70000652F-page 345

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 28.2 Package Details (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:11)(cid:9)(cid:18)(cid:19)(cid:4)(cid:5)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)(cid:10)(cid:21)(cid:9)(cid:22)(cid:9)(cid:23)(cid:24)(cid:24)(cid:9)(cid:25)(cid:14)(cid:11)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)(cid:10)(cid:16)(cid:18)(cid:10)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) (cid:2) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:30)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)-(cid:4)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)-(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) (cid:20)(cid:3)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:20)<<(cid:4) (cid:20)(cid:24)(cid:4)(cid:4) (cid:20)(cid:24)(cid:3)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:23) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:29) (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:4)(cid:5)1 DS70000652F-page 346  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2014 Microchip Technology Inc. DS70000652F-page 347

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000652F-page 348  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2014 Microchip Technology Inc. DS70000652F-page 349

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 !(cid:24)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:11)(cid:9)(cid:18)(cid:19)(cid:4)(cid:5)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)(cid:10)(cid:21)(cid:9)(cid:22)(cid:9)(cid:23)(cid:24)(cid:24)(cid:9)(cid:25)(cid:14)(cid:11)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)(cid:10)(cid:16)(cid:18)(cid:10)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) (cid:2) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)(cid:4) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)-(cid:4)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)-(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) (cid:20)(cid:3)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:20)(cid:24)<(cid:4) (cid:30)(cid:20)(cid:4)-(cid:4) (cid:30)(cid:20)(cid:4)?(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:29) (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)(cid:24)1 DS70000652F-page 350  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2014 Microchip Technology Inc. DS70000652F-page 351

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000652F-page 352  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2014 Microchip Technology Inc. DS70000652F-page 353

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 !(cid:24)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)"#$(cid:14)(cid:19)%(cid:9)"(cid:25)(cid:7)(cid:11)(cid:11)(cid:9)&(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)""(cid:21)(cid:9)(cid:22)(cid:9)’((cid:23)(cid:24)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)""&(cid:10)(cid:30)(cid:9) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 NOTE1 1 2 e b c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)(cid:4) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)?(cid:29) (cid:30)(cid:20)(cid:5)(cid:29) (cid:30)(cid:20)<(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = = : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)?(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) ?(cid:20)(cid:24)(cid:4) (cid:5)(cid:20)(cid:3)(cid:4) (cid:5)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:3)(cid:29)(cid:2)(cid:26).3 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:29) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ (cid:23)@ <@ 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)-< (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:3)1 DS70000652F-page 354  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2014 Microchip Technology Inc. DS70000652F-page 355

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L c A1 b1 b e eB Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e .100 BSC Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .335 Molded Package Width E1 .240 .285 .295 Overall Length D 1.345 1.365 1.400 Tip to Seating Plane L .110 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .050 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-070B DS70000652F-page 356  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 !(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)"#$(cid:14)(cid:19)%(cid:9)"(cid:25)(cid:7)(cid:11)(cid:11)(cid:9)&(cid:17)(cid:13)(cid:11)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)""(cid:21)(cid:9)(cid:22)(cid:9)’((cid:23)(cid:24)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29)""&(cid:10)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)?(cid:29) (cid:30)(cid:20)(cid:5)(cid:29) (cid:30)(cid:20)<(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = = : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20)<(cid:4) <(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:29)(cid:20)(cid:4)(cid:4) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)?(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4) (cid:30)(cid:4)(cid:20)(cid:3)(cid:4) (cid:30)(cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:29) (cid:4)(cid:20)(cid:5)(cid:29) (cid:4)(cid:20)(cid:24)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:3)(cid:29)(cid:2)(cid:26).3 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:29) 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ (cid:23)@ <@ 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:3) = (cid:4)(cid:20)-< (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)-1  2011-2014 Microchip Technology Inc. DS70000652F-page 357

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000652F-page 358  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2014 Microchip Technology Inc. DS70000652F-page 359

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000652F-page 360  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2014 Microchip Technology Inc. DS70000652F-page 361

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 DS70000652F-page 362  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104  2011-2014 Microchip Technology Inc. DS70000652F-page 363

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 !(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9))(cid:17)(cid:7)(cid:8)(cid:9)*(cid:11)(cid:7)(cid:13)+(cid:9)(cid:31)(cid:27)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)%(cid:7),(cid:6)(cid:9)(cid:20)-(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)./.(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29))*(cid:31)(cid:30) 0(cid:14)(cid:13)#(cid:9)(cid:24)(’’(cid:9)(cid:25)(cid:25)(cid:9)1(cid:27)(cid:19)(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)(cid:19),(cid:13)# (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS70000652F-page 364  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104  2011-2014 Microchip Technology Inc. DS70000652F-page 365

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 DS70000652F-page 366  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 22(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9))(cid:17)(cid:7)(cid:8)(cid:9)*(cid:11)(cid:7)(cid:13)+(cid:9)(cid:31)(cid:27)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)%(cid:7),(cid:6)(cid:9)(cid:20)-(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)(cid:3)/(cid:3)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29))*(cid:31)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E E2 b 2 2 1 1 N NOTE1 N L K TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:23)(cid:23) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . <(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) ?(cid:20)-(cid:4) ?(cid:20)(cid:23)(cid:29) ?(cid:20)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) <(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) ?(cid:20)-(cid:4) ?(cid:20)(cid:23)(cid:29) ?(cid:20)<(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)(cid:29) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-< ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)(cid:29)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# A (cid:4)(cid:20)(cid:3)(cid:4) = = (cid:31)(cid:27)(cid:13)(cid:6)(cid:12) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)-1  2011-2014 Microchip Technology Inc. DS70000652F-page 367

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 22(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9))(cid:17)(cid:7)(cid:8)(cid:9)*(cid:11)(cid:7)(cid:13)+(cid:9)(cid:31)(cid:27)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)%(cid:7),(cid:6)(cid:9)(cid:20)-(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)(cid:3)/(cid:3)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)(cid:9)(cid:29))*(cid:31)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS70000652F-page 368  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 22(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)3#(cid:14)(cid:19)(cid:9))(cid:17)(cid:7)(cid:8)(cid:9)*(cid:11)(cid:7)(cid:13)4(cid:7)(cid:15)%(cid:9)(cid:20)(cid:10)3(cid:21)(cid:9)(cid:22)(cid:9)(cid:2)(cid:24)/(cid:2)(cid:24)/(cid:2)(cid:9)(cid:25)(cid:25)(cid:9)(cid:26)(cid:27)(cid:8)(cid:28)+(cid:9)!((cid:24)(cid:24)(cid:9)(cid:25)(cid:25)(cid:9)(cid:29)3)*(cid:10)(cid:30) (cid:31)(cid:27)(cid:13)(cid:6) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D1 E e E1 N b NOTE1 1 2 3 NOTE2 α A c φ β A1 A2 L L1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)9(cid:14)(cid:28)#! 7 (cid:23)(cid:23) 9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)<(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)(cid:24)(cid:29) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)@ -(cid:20)(cid:29)@ (cid:5)@ : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! 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DS70000652F-page 369

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000652F-page 370  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104  2011-2014 Microchip Technology Inc. DS70000652F-page 371

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 DS70000652F-page 372  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 APPENDIX A: REVISION HISTORY Revision A (January 2011) This is the initial released version of the document. Revision B (February 2011) All major changes are referenced by their respective section in TableA-1. In addition, minor text and formatting changes were incorporated throughout the document. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description High-Performance, Ultra Low Cost 16-bit Pin diagram updates (see “Pin Diagrams”): Digital Signal Controllers • 20-pin PDIP/SOIC/SSOP (dsPIC33FJ16MC101): Removed the FLTB1 pin from pin 10 • 28-pin SPDIP/SOIC/SSOP (dsPIC33FJ16MC102): Relocated the FLTB1 pin from pin 12 to pin 14; relocated the FLTA1 pin from pin 16 to pin 15 • 28-pin QFN (dsPIC33FJ16MC102): Relocated the FLTA1 pin from pin 13 to pin 12; relocated the FLTB1 pin from pin 9 to pin 11 • 36-pin TLA (dsPIC33FJ16MC102): Relocated the FLTA1 pin from pin 17 to pin 16; relocated the FLTB1 pin from pin 10 to pin 15 Section1.0 “Device Overview” Added Notes 1, 2, and 3 regarding the FLTA1 and FLTB1 pins to the Pinout I/O Descriptions (see Table1-1). Added Section “”. Section4.0 “Memory Organization” Updated All Resets value for PxFLTACON and PxFLTABCON to the 6-Output PWM1 Register Map (see Table4-9). Added Note 1 to the PMD Register Map (see Table4-29). Section6.0 “Resets” Removed Reset timing sequence information from Section6.2 “System Reset”, as this information is provided in Figure6-2. Section15.0 “Motor Control PWM Module” Added Note 2 and Note 3 regarding the FLTA1 and FLTB1 pins to the 6-channel PWM Module Block Diagram (see Figure15-1). Added Section15.2 “PWM Faults” and Section15.3 “Write- protected Registers”. Added Note 2 and Note 3 regarding the FLTA1 and FLTB1 pins to the note boxes located below the PxFLTACON and PxFLTBCON registers (see Register15-9 and Register15-10). Section17.0 “Inter-Integrated Circuit™ Updated the descriptions for the conditional If STREN = 1 and If (I2C™)” STREN = 0 statements for the SCLREL bit in the I2Cx Control Register (see Register17-1). Section23.0 “Special Features” Added the RTSP Effect column to the dsPIC33F Configuration Bits Description (see Table23-3). Section26.0 “Electrical Characteristics” Added Parameters 300 and D305 (see Table26-42 and Table26-43). Section27.0 “Packaging Information” Modified the pending TLA packaging page.  2011-2014 Microchip Technology Inc. DS70000652F-page 373

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Revision C (June 2011) This revision includes the following global update: • All JTAG references have been removed All other major changes are referenced by their respective section in TableA-2. In addition, minor text and formatting changes were incorporated throughout the document. TABLE A-2: MAJOR SECTION UPDATES Section Name Update Description High-Performance, Ultra Low Cost The TMS, TDI, TDO, and TCK pin names were removed from these pin 16-bit Digital Signal Controllers diagrams: • 28-pin SPDIP/SOIC/SSOP • 28-pin QFN • 36-pin TLA Section1.0 “Device Overview” Updated the Buffer Type to Digital for the CTED1 and CTED2 pins (see Table1-1). Section4.0 “Memory Organization” Updated the SFR Address for IC2CON, IC3BUF, and IC3CON in the Input Capture Register Map (see Table4-7). Added the VREGS bit to the RCON register in the System Control Register Map (see Table4-27). Section6.0 “Resets” Added the VREGS bit to the RCON register (see Register6-1). Section8.0 “Oscillator Configuration” Updated the definition for COSC<2:0> = 001 and NOSC<2:0> = 001 in the OSCCON register (see Register8-1). Section15.0 “Motor Control PWM Updated the title for Example15-1 to include a reference to the Assembly Module” language. Added Example15-2, which provides a C code version of the write- protected register unlock and Fault clearing sequence. Section19.0 “10-bit Analog-to-Digital Updated the CH0 section and added Note 2 in both ADC block diagrams Converter (ADC)” (see Figure19-1 and Figure19-2). Updated the multiplexer values in the ADC Conversion Clock Period Block Diagram (see Figure19-3. Added the 01110 bit definitions and updated the 01101 bit definitions for the CH0SB<4:0> and CH0SA<4:0> bits in the AD1CHS0 register (see Register19-5). Section22.0 “Charge Time Removed Section 22.1 “Measuring Capacitance”, Section 22.2 “Measuring Measurement Unit (CTMU)” Time”, and Section 22.3 “Pulse Generation and Delay” Updated the key features. Added the CTMU Block Diagram (see Figure22-1). Updated the ITRIM<5:0> bit definitions and added Note 1 to the CTMU Current Control register (see Register22-3). DS70000652F-page 374  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section23.0 “Special Features” Updated bits 5 and 4 of FPOR, modified Note 2, and removed Note 3 from the Configuration Shadow Register Map (see Table23-1). Updated bit 14 of CONFIG1 and removed Note 5 from the Configuration Flash Words (see Table23-2). Updated the PLLKEN Configuration bit description (see Table23-3). Added Note 3 to Connections for the On-Chip Voltage Regulator (see Figure23-1). Section26.0 “Electrical Updated the Standard Operating Conditions to: 3.0V to 3.6V in all tables. Characteristics” Removed the Voltage on VCAP with respect to VSS entry in Absolute Maximum Ratings(1). Updated the VDD Range (in Volts) in Operating MIPS vs. Voltage (see Table26-1). Removed Parameter DC18 and updated the minimum value for Parameter DC 10 in the DC Temperature and Voltage Specifications (see Table26-4). Updated the Characteristic definition and the Typical value for Parameter BO10 in Electrical Characteristics: BOR (see Table26-5). Updated Note 2 in the DC Characteristics: Operating Current (IDD) (see Table26-6). Updated Note 2 in the DC Characteristics: Idle Current (IIDLE) (see Table26-7). Updated Note 2 and Parameters DC60C and DC61a-DC61d in the DC Characteristics: Power-Down Current (IPD) (see Table26-8). Updated Note 2 in the DC Characteristics: Doze Current (IDOZE) (see Table26-9). Added Note 1 to the Internal Voltage Regulator Specifications (see Table26-13). Updated the Minimum and Maximum values for Parameter F20a and the Typical value for Parameter F20b in AC Characteristics: Internal Fast RC (FRC) Accuracy (see Table26-18). Updated the Minimum, Typical, and Maximum values for Parameter F21a and F21b in Internal Low-Power RC (LPRC) Accuracy (see Table26-19). Updated the Minimum, Typical, and Maximum values for Parameter D305 in the Comparator Module Specifications (see Table26-43). Added Parameters CTMUFV1 and CTMUFV2 and updated Note 1 and the Conditions for all parameters in the CTMU Current Source Specifications (see Table26-46). Added Forward Voltage Versus Temperature (see Figure26-25).  2011-2014 Microchip Technology Inc. DS70000652F-page 375

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Revision D (April 2012) Also, where applicable, new sections were added to peripheral chapters that provide information and links This revision includes updates in support of the to the related resources, as well as helpful tips. For following new devices: examples, see Section18.1 “UART Helpful Tips” • dsPIC33FJ32GP101 and Section18.2 “UART Resources”. • dsPIC33FJ32GP102 This revision includes text and formatting changes that • dsPIC33FJ32GP104 were incorporated throughout the document. • dsPIC33FJ32MC101 All other major changes are referenced by their • dsPIC33FJ32MC102 respective section in TableA-3. • dsPIC33FJ32MC104 TABLE A-3: MAJOR SECTION UPDATES Section Name Update Description “16-Bit Digital Signal The content on the first page of this section was extensively reworked to provide the Controllers (up to 32- reader with the key features and functionality of this device family in an “at-a-glance” Kbyte Flash and 2-Kbyte format. SRAM)” TABLE 2: “dsPIC33FJ32(GP/MC)101/102/104 Device Features” was added, which provides a feature overview of the new devices. All pin diagrams were updated (see “Pin Diagrams”). Section1.0 “Device Updated the notes in the device family block diagram (see Figure1-1). Overview” Updated the following pinout I/O descriptions (Table1-1): • ANx • CNx • RAx • RCx • CVREFIN (formerly CVREF) Relocated 1.1 “Referenced Sources” to the previous chapter (see “Referenced Sources”). Section2.0 “Guidelines Updated the Recommended Minimum Connection diagram (see Figure2-1). for Getting Started with 16-bit Digital Signal Controllers” Section4.0 “Memory Updated the existing Program Memory Map (see Figure4-1) and added the Program Organization” Memory Map for dsPIC33FJ16(GP/MC)101/102 Devices (see Figure4-1). Updated the existing Data Memory Map (see Figure4-4) and added the Data Memory Map for dsPIC33FJ32(GP/MC)101/102/104 Devices with 2-Kbyte RAM (see Figure4-5). The following Special Function Register maps were updated or added: • TABLE 4-5: Change Notification Register Map for dsPIC33FJ32(GP/MC)104 Devices • TABLE 4-6: Interrupt Controller Register Map • TABLE 4-8: Timers Register Map for dsPIC33FJ32(GP/MC)10X Devices • TABLE 4-15: ADC1 Register Map for dsPIC33FJXX(GP/MC)101 Devices • TABLE 4-17: ADC1 Register Map for dsPIC33FJ32(GP/MC)104 Devices • TABLE 4-22: Peripheral Pin Select Input Register Map • TABLE 4-26: Peripheral Pin Select Output Register Map for dsPIC33FJ32(GP/ MC)104 Devices • TABLE 4-28: PORTA Register Map for dsPIC33FJ32(GP/MC)101/102 Devices • TABLE 4-29: PORTA Register Map for dsPIC33FJ32(GP/MC)104 Devices • TABLE 4-36: PORTC Register Map for dsPIC33FJ32(GP/MC)104 Devices • TABLE 4-39: PMD Register Map DS70000652F-page 376  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE A-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section7.0 “Interrupt Updated the Interrupt Vectors (see Table7-1). Controller” The following registers were updated or added: • Register 7-5: IFS0: Interrupt Flag Status Register 0 • Register 7-11: IEC1: Interrupt Enable Control Register 1 • Register 7-21: IPC6: Interrupt Priority Control Register 6 Section9.0 “Power- Updated 9.5 PMD Control Registers. Saving Features” Section10.0 “I/O Ports” Updated TABLE 10-1: Selectable Input Sources (Maps Input to Function)(1). Updated TABLE 10-2: Output Selection for Remappable Pin (RPn) The following registers were updated or added: • Register 10-4: RPINR4: Peripheral Pin Select Input Register 4 • Register 10-6: RPINR8: Peripheral Pin Select Input Register 8 • Register 10-19: RPOR8: Peripheral Pin Select Output Register 8 • Register 10-20: RPOR9: Peripheral Pin Select Output Register 9 • Register 10-21: RPOR10: Peripheral Pin Select Output Register 10 • Register 10-22: RPOR11: Peripheral Pin Select Output Register 11 • Register 10-23: RPOR12: Peripheral Pin Select Output Register 12 Section12.0 “Timer2/3 The features and operation information was extensively updated in support of Timer4/5 and Timer4/5” (see Section12.1 “32-Bit Operation” and Section12.2 “16-Bit Operation”). The block diagrams were updated in support of the new timers (see Figure12-1, Figure12-2, and Figure12-3). The following registers were added: • Register 12-3: T4CON: Timer4 Control Register(1) • Register 12-4: T5CON: Timer5 Control Register(1) Section15.0 “Motor Updated TABLE 15-1: Internal Pull-down resistors on PWM Fault pins. Control PWM Module” Note 2 was added to Register 15-5: PWMXCON1: PWMx Control Register 1(1). Section19.0 “10-Bit The number of available input pins and channels were updated from six to 14. Analog-to-Digital Updated FIGURE 19-1: ADC1 Block Diagram for dsPIC33FJXX(GP/MC)101 Devices. Converter (ADC)” Updated FIGURE 19-2: ADC1 Block Diagram for dsPIC33FJXX(GP/MC)102 Devices. Added FIGURE 19-3: ADC1 Block Diagram for dsPIC33FJ32(GP/MC)104 Devices. The following registers were updated: • Register 19-4: AD1CHS123: ADC1 Input Channel 1, 2, 3 Select Register • Register 19-5: AD1CHS0: ADC1 INPUT Channel 0 select Register • Register 19-6: AD1CSSL: ADC1 Input Scan Select Register Low(1,2,3) • Register 19-7: AD1PCFGL: ADC1 Port Configuration Register Low(1,2,3)  2011-2014 Microchip Technology Inc. DS70000652F-page 377

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 TABLE A-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section26.0 “Electrical Updated the Absolute Maximum Ratings. Characteristics” Updated TABLE 26-3: Thermal Packaging Characteristics. Updated TABLE 26-6: DC Characteristics: Operating Current (Idd). Updated TABLE 26-7: DC Characteristics: Idle Current (Iidle). Updated TABLE 26-8: DC Characteristics: Power-Down Current (Ipd). Updated TABLE 26-9: DC Characteristics: Doze Current (Idoze). Updated TABLE 26-10: DC Characteristics: I/O Pin Input Specifications. Replaced all SPI specifications and figures (see Table26-29 through Table26-44 and Figure26-11 through Figure26-26). Section28.0 “Packaging Added the following Package Marking Information and Package Drawings: Information” • 44-Lead TQFP • 44-Lead QFN • 44-Lead VTLA (referred to as TLA in the package drawings) DS70000652F-page 378  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Revision E (September 2012) This revision includes updates to the values in Section26.0 “Electrical Characteristics” and updated packaging diagrams in Section28.0 “Packaging Information”. There are minor text edits throughout the document. Revision F (January 2014) This revision adds the High-Temperature Electrical Characteristics chapter and updated packaging diagrams in Section28.0 “Packaging Information”. There are minor text edits throughout the document.  2011-2014 Microchip Technology Inc. DS70000652F-page 379

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70000652F-page 380  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 INDEX A C Absolute Maximum Ratings..............................................281 Charge Time Measurement Unit. See CTMU. AC Characteristics............................................................294 Clock Switching................................................................132 10-Bit ADC Specifications.........................................333 Enabling....................................................................132 ADC Specifications...................................................332 Sequence.................................................................132 Internal Fast RC (FRC) Accuracy.....................296, 342 Code Examples Internal Low-Power RC (LPRC) Accuracy........296, 342 Assembly Code for Write-Protected Register Load Conditions........................................................294 Unlock, Fault Clearing Sequence.....................184 PLL Clock..................................................................296 C Code for Write-Protected Register Unlock, Temperature and Voltage Specifications..................294 Fault Clearing Sequence..................................184 ADC Port Write/Read........................................................141 Control Registers......................................................222 PWRSAV Instruction Syntax....................................133 Helpful Tips...............................................................221 Setting the RTCWREN Bit........................................244 Initialization...............................................................217 Comparator.......................................................................231 Key Features.............................................................217 Control Registers......................................................234 Resources.................................................................221 Configuration Bits.............................................................261 Alternate Interrupt Vector Table (AIVT)..............................95 Description................................................................263 Analog-to-Digital Converter (ADC)....................................217 CPU Arithmetic Logic Unit (ALU).................................................43 Control Registers........................................................40 Data Addressing B Overview.............................................................37 Bit-Reversed Addressing....................................................76 DSP Engine................................................................43 Example......................................................................77 Adder/Subtracter Implementation...........................................................76 Overflow and Saturation.............................45 Sequence Table (16-Entry).........................................77 Barrel Shifter.......................................................47 Block Diagrams Data Accumulators 16-Bit Timer1 Module................................................165 Write Back..................................................46 6-Channel PWM1 Module.........................................182 Data Accumulators and Adder/Subtracter..........45 ADC1 Conversion Clock Period................................221 Multiplier.............................................................45 ADC1 for dsPIC33FJ32(GP/MC)104 Devices..........220 Overview.............................................................37 ADC1 for dsPIC33FJXX(GP/MC)101 Devices..........218 Special MCU Features...............................................38 ADC1 for dsPIC33FJXX(GP/MC)102 Devices..........219 CPU Clocking System......................................................126 Comparator I/O Operating Modes.............................231 Clock Selection.........................................................126 Comparator Voltage Reference................................232 Clock Sources..........................................................126 Connections for On-Chip Voltage Regulator.............266 Configuration Bit Values for Clock Selection............127 CTMU Module...........................................................256 PLL Configuration.....................................................127 Digital Filter Interconnect..........................................233 CTMU DSP Engine................................................................44 Control Registers......................................................257 dsPIC33FJXX(GP/MC)10X CPU Core.......................38 Customer Change Notification Service.............................387 dsPIC33FJXX(GP/MC)10X Devices...........................28 Customer Notification Service..........................................387 I2C Module................................................................204 Customer Support.............................................................387 Input Capture x Module.............................................175 D MCLR Pin Connections...............................................34 Multiplexing of Remappable Output for RPn.............144 Data Address Space...........................................................52 Oscillator System......................................................125 Memory Map for dsPIC33FJ16(GP/MC)101/102 Output Compare x Module........................................177 Devices, 1-Kbyte RAM.......................................53 Real-Time Clock and Calendar (RTCC) Module.......243 Memory Map for dsPIC33FJ32(GP/MC)101/102/104 Recommended Minimum Connection.........................34 Devices, 2-Kbyte RAM............................................54 Remappable MUX Input for U1RX............................142 Near Data Space........................................................52 Reset System..............................................................87 Organization and Alignment.......................................52 Shared Port Structure...............................................140 SFR Space.................................................................52 SPIx Module..............................................................197 Software Stack...........................................................73 Timer2 and Timer4 (16-Bit).......................................169 Width..........................................................................52 Timer2/3 and Timer4/5 (32-Bit).................................168 X and Y Spaces..........................................................55 Timer3 and Timer5 (16-Bit).......................................169 UARTx Simplified......................................................211 User-Programmable Blanking Function....................232 Watchdog Timer (WDT)............................................267 Brown-out Reset (BOR)....................................................266  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dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 DC Characteristics............................................................282 H Brown-out Reset (BOR)............................................283 High-Temperature Electrical Characteristics....................339 Doze Current (IDOZE)........................................289, 342 High Temperature.....................................................340 I I/O Pin Input Specifications.......................................290 I/O Ports............................................................................139 I/O Pin Output Specifications....................................292 Configuring Analog Port Pins....................................141 Idle Current (IIDLE)............................................286, 341 Open-Drain Configuration.........................................141 Operating Current (IDD).............................284, 340, 341 Parallel I/O (PIO)......................................................139 Operating MIPS vs. Voltage..............................282, 340 Write/Read Timing....................................................141 Power-Down Current (IPD)................................288, 341 I2C Program Memory......................................................293 Control Registers......................................................205 Temperature and Voltage Specifications..................283 Operating Modes......................................................203 Thermal Operating Conditions..........................282, 340 Registers..................................................................203 Thermal Packaging...................................................282 In-Circuit Debugger...........................................................268 Development Support.......................................................277 In-Circuit Serial Programming (ICSP)...............................268 Assembler Input Capture....................................................................175 MPASM Assembler...........................................278 Control Register........................................................176 C Compilers Input Change Notification (ICN)........................................141 MPLAB XC........................................................278 Instruction Addressing Modes............................................73 Demonstration/Development Boards........................280 File Register Instructions............................................73 Evaluation and Starter Kits.......................................280 Fundamental Modes Supported.................................74 MPLAB Assembler, Linker, Librarian........................278 MAC Instructions........................................................74 MPLAB ICD 3 In-Circuit Debugger System..............279 MCU Instructions........................................................73 MPLAB PM3 Device Programmer............................279 Move and Accumulator Instructions............................74 MPLAB REAL ICE In-Circuit Emulator System.........279 Other Instructions.......................................................74 MPLAB X Integrated Development Instruction Set Environment Software.......................................277 MPLINK Object Linker/MPLIB Object Librarian........278 Summary..........................................................269 PICkit 3 In-Circuit Debugger/Programmer................279 Overview...................................................................272 Software Simulator (MPLAB X SIM).........................279 Symbols Used in Opcode Descriptions....................270 Third-Party Development Tools................................280 Instruction-Based Power-Saving Modes...........................133 Doze Mode........................................................................134 Idle............................................................................134 dsPIC33FJ16(GP/MC)101/102 Sleep........................................................................133 Device Features............................................................2 Internet Address...............................................................387 dsPIC33FJ32(GP/MC)101/102/104 Interrupt Controller..............................................................95 Device Features............................................................3 Interrupt Registers E IECx....................................................................98 IFSx....................................................................98 Electrical Characteristics...................................................281 INTCON1............................................................98 Equations INTCON2............................................................98 Device Operating Frequency....................................126 INTTREG............................................................98 Flash Programming Time............................................84 IPCx....................................................................98 Maximum Row Write Time..........................................84 Interrupt Setup Procedures.......................................124 Minimum Row Write Time...........................................84 Initialization.......................................................124 MS with PLL Mode....................................................127 Interrupt Disable...............................................124 Errata..................................................................................24 Interrupt Service Routine (ISR)........................124 F Trap Service Routine (TSR).............................124 Interrupt Vectors.........................................................97 Flash Program Memory.......................................................83 Reset Sequence.........................................................95 Control Registers........................................................85 Interrupt Vector Table (IVT)................................................95 Operations..................................................................84 Interrupts Coincident with Power Save Instructions.........134 Programming Algorithm..............................................84 RTSP Operation..........................................................84 L Table Instructions........................................................83 LPRC Oscillator G Use with WDT...........................................................267 Getting Started with 16-Bit DSCs........................................33 M Analog and Digital Pins Configuration Memory Organization.........................................................49 During ICSP........................................................36 Microchip Internet Web Site..............................................387 Connection Requirements..........................................33 Modulo Addressing.............................................................75 Decoupling Capacitors................................................33 Applicability.................................................................76 External Oscillator Pins...............................................35 Operation Example.....................................................75 ICSP Pins....................................................................35 Start and End Address...............................................75 Master Clear (MCLR) Pin............................................34 W Address Register Selection....................................75 Oscillator Value Conditions on Start-up......................36 Unused I/Os................................................................36 DS70000652F-page 382  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Motor Control PWM..........................................................181 R 6-Channel PWM1 Module.........................................181 Real-Time Clock and Calendar (RTCC)...........................243 Control Registers......................................................185 Register Maps Faults........................................................................183 6-Output PWM1, dsPIC33FJXXMC10X Devices.......61 At Reset............................................................183 ADC1, dsPIC33FJ32(GP/MC)104 Devices................65 Write-Protected Registers.........................................183 ADC1, dsPIC33FJXX(GP/MC)101 Devices...............63 O ADC1, dsPIC33FJXX(GP/MC)102 Devices...............64 Change Notification, dsPIC33FJ32(GP/MC)104 Oscillator Configuration Devices...............................................................58 Control Registers......................................................128 Change Notification, dsPIC33FJXX(GP/MC)102 Output Compare...............................................................177 Devices...............................................................58 Control Register........................................................179 Change Notification, dsPIC33FJXXGP101 Modes.......................................................................178 Devices...............................................................58 Active-High One-Shot.......................................178 Change Notification, dsPIC33FJXXMC101 Active-Low One-Shot........................................178 Devices...............................................................58 Continuous Pulse..............................................178 Comparator.................................................................67 Delayed One-Shot............................................178 Configuration Flash Words Module Disabled...............................................178 dsPIC33FJ16(GP/MC)10X Devices.................262 PWM with Fault Protection...............................178 dsPIC33FJ32(GP/MC)10X Devices.................262 PWM without Fault Protection..........................178 Configuration Shadow Registers..............................262 Toggle...............................................................178 CPU Core...................................................................56 P CTMU.........................................................................66 I2C1............................................................................62 Packaging.........................................................................343 Input Capture..............................................................61 Details.......................................................................346 Interrupt Controller......................................................59 Marking.....................................................343, 344, 345 NVM............................................................................72 Peripheral Module Disable (PMD)....................................134 Output Compare.........................................................61 Peripheral Pin Select (PPS)..............................................142 PAD Configuration......................................................66 Available Pins...........................................................142 PMD............................................................................72 Controlling.................................................................142 PORTA, dsPIC33FJ16(GP/MC)101/102 Controlling Configuration Changes...........................145 Devices...............................................................69 Helpful Tips...............................................................146 PORTA, dsPIC33FJ32(GP/MC)101/102 I/O Resources...........................................................146 Devices...............................................................69 Input Mapping...........................................................142 PORTA, dsPIC33FJ32(GP/MC)104 Devices.............70 Input Selection Sources for Remappable PORTB, dsPIC33FJ16GP101 Devices......................70 Pin (RPn)..........................................................143 PORTB, dsPIC33FJ16MC101 Devices......................70 Output Mapping........................................................144 PORTB, dsPIC33FJ32(GP/MC)102 and Output Selection Sources for Remappable dsPIC33FJ32(GP/MC)104 Devices....................71 Pin (RPn)..........................................................144 PORTB, dsPIC33FJ32GP101 Devices......................71 Registers...................................................................147 PORTB, dsPIC33FJ32MC101 Devices......................71 Pin Diagrams........................................................................4 PORTB, dsPIC33FJXX(GP/MC)102 and Pinout I/O Descriptions (table)............................................29 dsPIC33FJ16(GP/MC)102 Devices....................70 PORTA PORTC, dsPIC33FJ32(GP/MC)104 Devices.............71 Register Map...............................................................70 PPS Input...................................................................67 Power-Saving Features....................................................133 PPS Output, dsPIC33FJ32(GP/MC)104 Devices.......69 Clock Frequency and Switching................................133 PPS Output, dsPIC33FJXX(GP/MC)102 Devices......68 Program Address Space.....................................................49 PPS Output, dsPIC33FJXXGP101 Devices...............68 Construction................................................................78 PPS Output, dsPIC33FJXXMC101 Devices...............68 Data Access from Program Memory Using Real-Time Clock and Calendar..................................66 Table Instructions...............................................80 SPI1............................................................................62 Data Access from, Address Generation......................79 System Control...........................................................72 Memory Map Timers, dsPIC33FJ16(GP/MC)10X Devices..............60 dsPIC33FJ16(GP/MC)101/102 Devices.............49 Timers, dsPIC33FJ32(GP/MC)10X Devices..............60 dsPIC33FJ32(GP/MC)101/102/104 Devices......50 UART1........................................................................62 PSV Operation............................................................81 Registers Reading Data Using Program Space Visibility............81 AD1CHS0 (ADC1 Input Channel 0 Select)...............227 Table Read Instructions AD1CHS123 (ADC1 Input TBLRDH.............................................................80 Channel 1, 2, 3 Select).....................................226 TBLRDL..............................................................80 AD1CON1 (ADC1 Control 1)....................................222 Program Memory AD1CON2 (ADC1 Control 2)....................................224 Interrupt Vector...........................................................51 AD1CON3 (ADC1 Control 3)....................................225 Organization................................................................51 AD1CSSL (ADC1 Input Scan Select Low)...............228 Reset Vector...............................................................51 AD1PCFGL (ADC1 Port Configuration Low)............229 Programmer’s Model...........................................................39  2011-2014 Microchip Technology Inc. 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dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 ALCFGRPT (Alarm Configuration)............................248 PMD3 (Peripheral Module Disable Control 3)...........137 ALRMVAL (Alarm Minutes and Seconds Value, PMD4 (Peripheral Module Disable Control 4)...........137 ALRMPTR Bits = 00)........................................254 PWMxCON1 (PWMx Control 1)................................188 ALRMVAL (Alarm Month and Day Value, PWMxCON2 (PWMx Control 2)................................189 ALRMPTR Bits = 10)........................................252 PWMxKEY (PWMx Unlock)......................................196 ALRMVAL (Alarm Weekday and Hours Value, PxDC1 (PWMx Duty Cycle 1)...................................195 ALRMPTR Bits = 01)........................................253 PxDC2 (PWMx Duty Cycle 2)...................................195 CLKDIV (Clock Divisor).............................................130 PxDC3 (PWMx Duty Cycle 3)...................................195 CMSTAT (Comparator Status)..................................234 PxDTCON1 (PWMx Dead-Time Control 1)..............190 CMxCON (Comparator x Control).............................235 PxDTCON2 (PWMx Dead-Time Control 2)..............191 CMxFLTR (Comparator x Filter Control)...................241 PxFLTACON (PWMx Fault A Control)......................192 CMxMSKCON (Comparator x Mask PxFLTBCON (PWMx Fault B Control)......................193 Gating Control)..................................................239 PxOVDCON (PWMx Override Control)....................194 CMxMSKSRC (Comparator x Mask PxSECMP (PWMx Special Event Compare)............187 Source Select)..................................................237 PxTCON (PWMx Time Base Control).......................185 CORCON (Core Control)......................................42, 99 PxTMR (PWMx Timer Count Value).........................186 CTMUCON1 (CTMU Control 1)................................257 PxTPER (PWMx Time Base Period)........................186 CTMUCON2 (CTMU Control 2)................................258 RCFGCAL (RTCC Calibration CTMUICON (CTMU Current Control).......................259 and Configuration)............................................245 CVRCON (Comparator Voltage RCON (Reset Control)................................................88 Reference Control)............................................242 RPINR0 (Peripheral Pin Select Input 0)....................147 DEVID (Device ID)....................................................265 RPINR1 (Peripheral Pin Select Input 1)....................148 DEVREV (Device Revision)......................................265 RPINR11 (Peripheral Pin Select Input 11)................153 I2CxCON (I2Cx Control)...........................................205 RPINR18 (Peripheral Pin Select Input 18)................154 I2CxMSK (I2Cx Slave Mode Address Mask)............209 RPINR20 (Peripheral Pin Select Input 20)................155 I2CxSTAT (I2Cx Status)...........................................207 RPINR21 (Peripheral Pin Select Input 21)................156 ICxCON (Input Capture x Control)............................176 RPINR3 (Peripheral Pin Select Input 3)....................149 IEC0 (Interrupt Enable Control 0).............................108 RPINR4 (Peripheral Pin Select Input 4)....................150 IEC1 (Interrupt Enable Control 1).............................109 RPINR7 (Peripheral Pin Select Input 7)....................151 IEC2 (Interrupt Enable Control 2).............................110 RPINR8 (Peripheral Pin Select Input 8)....................152 IEC3 (Interrupt Enable Control 3).............................110 RPOR0 (Peripheral Pin Select Output 0)..................157 IEC4 (Interrupt Enable Control 4).............................111 RPOR1 (Peripheral Pin Select Output 1)..................157 IFS0 (Interrupt Flag Status 0)...................................103 RPOR10 (Peripheral Pin Select Output 10)..............162 IFS1 (Interrupt Flag Status 1)...................................105 RPOR11 (Peripheral Pin Select Output 11)..............162 IFS2 (Interrupt Flag Status 2)...................................106 RPOR12 (Peripheral Pin Select Output 12)..............163 IFS3 (Interrupt Flag Status 3)...................................106 RPOR2 (Peripheral Pin Select Output 2)..................158 IFS4 (Interrupt Flag Status 4)...................................107 RPOR3 (Peripheral Pin Select Output 3)..................158 INTCON1 (Interrupt Control 1)..................................100 RPOR4 (Peripheral Pin Select Output 4)..................159 INTCON2 (Interrupt Control 2)..................................102 RPOR5 (Peripheral Pin Select Output 5)..................159 INTTREG (Interrupt Control and Status)...................123 RPOR6 (Peripheral Pin Select Output 6)..................160 IPC0 (Interrupt Priority Control 0).............................112 RPOR7 (Peripheral Pin Select Output 7)..................160 IPC1 (Interrupt Priority Control 1).............................113 RPOR8 (Peripheral Pin Select Output 8)..................161 IPC14 (Interrupt Priority Control 14).........................119 RPOR9 (Peripheral Pin Select Output 9)..................161 IPC15 (Interrupt Priority Control 15).........................120 RTCVAL (RTCC Minutes and Seconds Value, IPC16 (Interrupt Priority Control 16).........................121 RTCPTR Bits = 00)...........................................251 IPC19 (Interrupt Priority Control 19).........................122 RTCVAL (RTCC Month and Day Value, IPC2 (Interrupt Priority Control 2).............................114 RTCPTR Bits = 10)...........................................249 IPC3 (Interrupt Priority Control 3).............................115 RTCVAL (RTCC Weekdays and Hours Value, IPC4 (Interrupt Priority Control 4).............................116 RTCPTR Bits = 01)...........................................250 IPC5 (Interrupt Priority Control 5).............................117 RTCVAL (RTCC Year Value, IPC6 (Interrupt Priority Control 6).............................117 RTCPTR Bits = 11)...........................................249 IPC7 (Interrupt Priority Control 7).............................118 SPIxCON1 (SPIx Control 1)......................................200 IPC9 (Interrupt Priority Control 9).............................119 SPIxCON2 (SPIx Control 2)......................................202 NVMCON (Flash Memory Control).............................85 SPIxSTAT (SPIx Status and Control).......................199 NVMKEY (Nonvolatile Memory Key)..........................85 SR (CPU STATUS)...............................................40, 99 OCxCON (Output Compare x Control).....................179 T1CON (Timer1 Control)..........................................166 OSCCON (Oscillator Control)...................................128 T2CON (Timer2 Control)..........................................170 OSCTUN (FRC Oscillator Tuning)............................131 T3CON (Timer3 Control)..........................................171 PADCFG1 (Pad Configuration Control)....................247 T4CON (Timer4 Control)..........................................172 PMD1 (Peripheral Module Disable Control 1)...........135 T5CON (Timer5 Control)..........................................173 PMD2 (Peripheral Module Disable Control 2)...........136 UxMODE (UARTx Mode)..........................................213 UxSTA (UARTx Status and Control).........................215 DS70000652F-page 384  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 Resets.................................................................................87 I2Cx Bus Start/Stop Bits (Master Mode)...................328 BOR (Brown-out Reset)..............................................87 I2Cx Bus Start/Stop Bits (Slave Mode).....................330 BOR and Power-up Timer (PWRT).............................92 Input Capture x (ICx)................................................301 CM (Configuration Mismatch Reset)...........................87 Motor Control PWMx................................................303 Configuration Mismatch (CM).....................................93 Motor Control PWMx Fault.......................................303 External (EXTR)..........................................................93 OCx/PWMx...............................................................302 Illegal Condition..........................................................93 Output Compare x (OCx)..........................................302 Illegal Opcode.....................................................93 Output Compare x Operation...................................178 Security.........................................................93, 94 Reset, Watchdog Timer, Oscillator Start-up Timer Uninitialized W Register................................93, 94 and Power-up Timer.........................................298 IOPUWR (Illegal Condition Reset)..............................87 SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, Illegal Opcode.....................................................87 SMP = 1) for dsPIC33FJ16(GP/MC)10X..........307 Security...............................................................87 SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, Uninitialized W Register......................................87 SMP = 1) for dsPIC33FJ32(GP/MC)10X..........319 MCLR (Master Clear Pin)............................................87 SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, Oscillator Delays.........................................................90 SMP = 1) for dsPIC33FJ16(GP/MC)10X..........306 POR (Power-on Reset)...............................................87 SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, Power-on Reset (POR)...............................................92 SMP = 1) for dsPIC33FJ32(GP/MC)10X..........318 Software RESET Instruction (SWR)...........................93 SPIx Master Transmit Mode (Half-Duplex, CKE = 0) SWR (RESET Instruction)...........................................87 for dsPIC33FJ16(GP/MC)10X..........................304 System SPIx Master Transmit Mode (Half-Duplex, CKE = 0) Cold Reset..........................................................90 for dsPIC33FJ32(GP/MC)10X..........................316 Warm Reset........................................................90 SPIx Master Transmit Mode (Half-Duplex, CKE = 1) Trap Conflict................................................................93 for dsPIC33FJ16(GP/MC)10X..........................305 TRAPR (Trap Conflict Reset)......................................87 SPIx Master Transmit Mode (Half-Duplex, CKE = 1) Watchdog Timer Time-out (WDTO)............................93 for dsPIC33FJ32(GP/MC)10X..........................317 WDTO (Watchdog Timer Reset).................................87 SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, Revision History................................................................373 SMP = 0) for dsPIC33FJ16(GP/MC)10X..........314 RTCC SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, Control Registers......................................................245 SMP = 0) for dsPIC33FJ32(GP/MC)10X..........326 Module Registers......................................................244 SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, Register Mapping......................................................244 SMP = 0) for dsPIC33FJ16(GP/MC)10X..........312 SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, S SMP = 0) for dsPIC33FJ32(GP/MC)10X..........324 Serial Peripheral Interface (SPI).......................................197 SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, Control Registers......................................................199 SMP = 0) for dsPIC33FJ16(GP/MC)10X..........308 Helpful Tips...............................................................198 SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, Resources.................................................................198 SMP = 0) for dsPIC33FJ32(GP/MC)10X..........320 Software Stack Pointer, Frame Pointer SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, CALL Stack Frame......................................................73 SMP = 0) for dsPIC33FJ16(GP/MC)10X..........310 Special Features...............................................................261 SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, Code Protection........................................................261 SMP = 0) for dsPIC33FJ32(GP/MC)10X..........322 Flexible Configuration...............................................261 System Reset.............................................................91 In-Circuit Emulation...................................................261 Timer1/2/3 External Clock........................................299 In-Circuit Serial Programming (ICSP).......................261 Timing Requirements Watchdog Timer (WDT)............................................261 10-Bit ADC Conversion............................................335 Capacitive Loading on Output Pins..........................294 T CLKO and I/O...........................................................297 Timer1...............................................................................165 External Clock..........................................................295 Control Register........................................................166 I2Cx Bus Data (Master Mode)..................................329 Timer2/3 and Timer4/5......................................................167 I2Cx Bus Data (Slave Mode)....................................331 16-Bit Operation........................................................167 Input Capture x (ICx)................................................301 32-Bit Operation........................................................167 Motor Control PWMx................................................303 Control Registers......................................................170 Output Compare x (OCx)..........................................302 Timing Diagrams Reset, Watchdog Timer, Oscillator Start-up Timer, ADC Conversion Characteristics (CHPS<1:0> = 01, Power-up Timer and Brown-out Reset.............298 SIMSAM = 0, ASAM = 0, Simple OCx/PWMx Mode.........................................302 SSRC<2:0> = 000)...........................................334 SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, ADC Conversion Characteristics (CHPS<1:0> = 01, SMP = 1) for dsPIC33FJ16(GP/MC)10X..........307 SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SAMC<4:0> = 00001).......................................334 SMP = 1) for dsPIC33FJ32(GP/MC)10X..........319 Brown-out Reset Situations........................................92 SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, CLKO and I/O...........................................................297 SMP = 1) for dsPIC33FJ16(GP/MC)10X..........306 External Clock...........................................................295 SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, I2Cx Bus Data (Master Mode)..................................328 SMP = 1) for dsPIC33FJ32(GP/MC)10X..........318 I2Cx Bus Data (Slave Mode)....................................330  2011-2014 Microchip Technology Inc. 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dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 SPIx Master Transmit Mode (Half-Duplex) U for dsPIC33FJ16(GP/MC)10X..........................305 UART SPIx Master Transmit Mode (Half-Duplex) Control Registers......................................................213 for dsPIC33FJ32(GP/MC)10X..........................317 Helpful Tips...............................................................212 SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, Resources................................................................212 SMP = 0) for dsPIC33FJ16(GP/MC)10X..........315 Universal Asynchronous Receiver SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, Transmitter (UART)..................................................211 SMP = 0) for dsPIC33FJ32(GP/MC)10X..........327 Using the RCON Status Bits...............................................94 SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) for dsPIC33FJ16(GP/MC)10X..........313 V SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, Voltage Regulator (On-Chip)............................................266 SMP = 0) for dsPIC33FJ32(GP/MC)10X..........325 SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, W SMP = 0) for dsPIC33FJ16(GP/MC)10X..........309 Watchdog Timer (WDT)....................................................267 SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, Programming Considerations...................................267 SMP = 0) for dsPIC33FJ32(GP/MC)10X..........321 WWW Address.................................................................387 SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, WWW, On-Line Support.....................................................24 SMP = 0) for dsPIC33FJ16(GP/MC)10X..........311 SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) for dsPIC33FJ32(GP/MC)10X..........323 Timer1 External Clock...............................................299 Timer2/4 External Clock............................................300 Timer3/5 External Clock............................................300 Timing Specifications Comparator Module..................................................336 Comparator Timing...................................................336 Comparator Voltage Reference................................337 Comparator Voltage Reference Settling Time..........336 CTMU Current Source..............................................337 DS70000652F-page 386  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2011-2014 Microchip Technology Inc. DS70000652F-page 387

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70000652F-page 388  2011-2014 Microchip Technology Inc.

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 16 MC1 02 T E / SP - XXX Examples: a) dsPIC33FJ16MC102-E/SP: Microchip Trademark Motor Control dsPIC33, 16-Kbyte Program Memory, Architecture 28-Pin, Extended Temperature, Flash Memory Family SPDIP package. Program Memory Size (Kbyte) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture: 33 = 16-bit Digital Signal Controller Flash Memory Family: FJ = Flash program memory, 3.3V Product Group: GP1 = General Purpose family MC1 = Motor Control family Pin Count: 01 = 18-pin and 20-pin 02 = 28-pin and 32-pin Temperature Range: I = -40C to +85C (Industrial) E = -40C to +125C (Extended) Package: P = Plastic Dual In-Line - 300 mil body (PDIP) SS = Plastic Shrink Small Outline - 5.3 mm body (SSOP) SP = Skinny Plastic Dual In-Line - 300 mil body (SPDIP) SO = Plastic Small Outline - Wide - 7.50 mil body (SOIC) ML = Plastic Quad, No Lead - (28-pin) 6x6 mm body (QFN) PT = Plastic Thin Quad Flatpack - (44-pin) 10x10 mm body (TQFP) TL = Very Thin Leadless Array - (36-pin) 5x5 mm body (VTLA)  2011-2014 Microchip Technology Inc. DS70000652F-page 389

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 NOTES: DS70000652F-page 390  2011-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2011-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62077-845-6 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2011-2014 Microchip Technology Inc. DS70000652F-page 391

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: DSPIC33FJ16GP101-E/P DSPIC33FJ16GP101-E/SO DSPIC33FJ16GP101-E/SS DSPIC33FJ16GP101-I/P DSPIC33FJ16GP101-I/SO DSPIC33FJ16GP101-I/SS DSPIC33FJ16GP101T-I/SO DSPIC33FJ16GP101T-I/SS DSPIC33FJ16GP102-E/ML DSPIC33FJ16GP102-E/SO DSPIC33FJ16GP102-E/SP DSPIC33FJ16GP102-E/SS DSPIC33FJ16GP102-I/ML DSPIC33FJ16GP102-I/SO DSPIC33FJ16GP102-I/SP DSPIC33FJ16GP102-I/SS DSPIC33FJ16GP102T-I/ML DSPIC33FJ16GP102T-I/SO DSPIC33FJ16GP102T-I/SS DSPIC33FJ32GP102-I/SO DSPIC33FJ32MC102-I/SO DSPIC33FJ32GP104-I/PT DSPIC33FJ32MC104-I/PT DSPIC33FJ32MC101T-I/SS DSPIC33FJ32MC104T-I/PT DSPIC33FJ32MC102-I/ML DSPIC33FJ32GP101-H/P DSPIC33FJ16MC101-I/SO DSPIC33FJ32MC102-H/SS DSPIC33FJ16MC102-I/SP DSPIC33FJ32GP102-E/SO DSPIC33FJ32MC104-E/PT DSPIC33FJ16MC101-E/SO DSPIC33FJ32GP102T-I/ML DSPIC33FJ32MC102-I/SS DSPIC33FJ32GP102-H/SS DSPIC33FJ32GP101T-I/SS DSPIC33FJ16MC101T-I/SS DSPIC33FJ32GP102T-E/SS DSPIC33FJ16MC102T-I/SO DSPIC33FJ32MC101T-I/SO DSPIC33FJ32GP102-E/ML DSPIC33FJ32GP104-H/TL DSPIC33FJ32MC104T-I/ML DSPIC33FJ32GP102T-I/SS DSPIC33FJ32MC102-I/SP DSPIC33FJ32MC102T-E/SO DSPIC33FJ32MC104-I/TL DSPIC33FJ32GP102-H/SO DSPIC33FJ32GP101-I/SO DSPIC33FJ16MC102T-I/SS DSPIC33FJ32GP102-I/SP DSPIC33FJ32MC101-I/SS DSPIC33FJ32MC102T-I/SO DSPIC33FJ16MC101-I/SS DSPIC33FJ32GP101-H/SO DSPIC33FJ32GP104-H/PT DSPIC33FJ32MC102-E/TL DSPIC33FJ32MC101-I/SO DSPIC33FJ32GP102-H/TL DSPIC33FJ32MC101-H/SO DSPIC33FJ32MC104-I/ML DSPIC33FJ16MC102-E/SO DSPIC33FJ32MC102T-I/TL DSPIC33FJ32GP104-H/ML DSPIC33FJ32GP101-E/SS DSPIC33FJ32MC101-H/P DSPIC33FJ16MC102-I/SS DSPIC33FJ32GP101-I/P DSPIC33FJ32MC101-E/SO DSPIC33FJ32MC104T-E/ML DSPIC33FJ32MC102-E/SS DSPIC33FJ32MC104-E/TL DSPIC33FJ32MC102-E/SP DSPIC33FJ32GP101T-E/SO DSPIC33FJ16MC102T-I/ML DSPIC33FJ16MC101-I/P DSPIC33FJ16MC102-E/SS DSPIC33FJ32GP102-H/SP DSPIC33FJ32GP104T-I/ML DSPIC33FJ32GP101T-I/SO DSPIC33FJ32MC101-E/SS DSPIC33FJ32GP101-E/SO DSPIC33FJ32MC102T-I/ML DSPIC33FJ32GP104-I/ML DSPIC33FJ32GP102-I/ML DSPIC33FJ32MC102-H/TL DSPIC33FJ32GP104-E/ML DSPIC33FJ32MC102-H/SP DSPIC33FJ32MC104-H/ML DSPIC33FJ32GP104T-I/PT DSPIC33FJ32MC101T-E/SO DSPIC33FJ32GP104T-E/ML DSPIC33FJ32MC102T-E/SS DSPIC33FJ32GP102-I/TL DSPIC33FJ32MC102-H/SO DSPIC33FJ32MC104T-I/TL DSPIC33FJ32GP102T-I/SO DSPIC33FJ32MC101-E/P DSPIC33FJ32MC102-E/SO