dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 16-Bit Digital Signal Controllers (up to 16-Kbyte Flash and up to 2-Kbyte SRAM) with High-Speed PWM, ADC and Comparators Operating Conditions Advanced Analog Features (Continued) • 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS • Up to Four High-Speed Comparators with Direct • 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS Connection to the PWM module: • 3.0V to 3.6V, -40ºC to +85ºC, DC to 50 MIPS - Programmable references with 1024 voltage points Core: 16-Bit dsPIC33F CPU Timers/Output Compare/Input Capture • Code-Efficient (C and Assembly) Architecture • Three General Purpose Timers: • Two 40-Bit Wide Accumulators - Three 16-bit and one 32-bit timer/counter • Single-Cycle (MAC/MPY) with Dual Data Fetch • Two Output Compare (OC) modules • Single-Cycle Mixed-Sign MUL plus Hardware Divide • Two Input Capture (IC) modules • 32-Bit Multiply Support • Peripheral Pin Select (PPS) to allow Function Remap Communication Interfaces Clock Management • UART module (12.5 Mbps): • ±2.0% Internal Oscillator - With support for LIN/J2602 protocols and IrDA® • Programmable PLLs and Oscillator Clock Sources • 4-Wire SPI module • Fail-Safe Clock Monitor (FSCM) • I2C™ module (up to 1 Mbaud) with SMBus Support • Independent Watchdog Timer (WDT) • PPS to allow Function Remap • Fast Wake-up and Start-up Input/Output Power Management • Sink/Source 18 mA on 8 Pins, 10 mA on 10 Pins • Low-Power Management modes (Sleep, Idle, Doze) and 6 mA on 17 Pins • Integrated Power-on Reset and Brown-out Reset • 5V Tolerant Pins • Selectable Open-Drain and Pull-ups High-Speed PWM • External Interrupts on up to 30 I/O Pins • Up to Four PWM Pairs with Independent Timing Qualification and Class B Support • Dead Time for Rising and Falling Edges • 1.04 ns PWM Resolution • AEC-Q100 REVG (Grade 1, -40ºC to +125ºC) • PWM Support for: • AEC-Q100 REVG (Grade 0, -40ºC to +150ºC) - DC/DC, AC/DC, Inverters, PFC and Lighting • Class B Safety Library, IEC 60730, VDE Certified • Programmable Fault Inputs • 6x6x0.5 mm UQFN Package Designed and • Flexible Trigger Configurations for ADC Conversions Optimized to ease IPC9592A 2nd Level Temperature Cycle Qualification Advanced Analog Features Debugger Development Support • ADC module: - 10-bit resolution with up to 2 Successive Approximation • In-Circuit and In-Application Programming Register (SAR) converters (4 Msps) and up to • Two Breakpoints six Sample-and-Hold (S&H) circuits • IEEE 1149.2-Compatible (JTAG) Boundary Scan - Up to 12 input channels grouped into six conversion • Trace and Run-Time Watch pairs, plus two voltage reference monitoring inputs - Dedicated result buffer for each analog channel • Flexible and Independent ADC Trigger Sources  2008-2014 Microchip Technology Inc. DS70000318G-page 1

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 dsPIC33FJ06GS101/X02 AND dsPIC33FJ16GSX02/X04 PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CONTROLLER FAMILIES s) Remappable Peripherals ADC e Kbyt rcuit s Device Pins rogram Flash Memory ( RAM (Bytes) Remappable Pins 16-Bit Timer Input Capture Output Compare UART SPI (2)PWM Analog Comparator (3)External Interrupts DAC Output 2IC™ SARs mple-and-Hold (S&H) Ci Analog-to-Digital Input I/O Pins Packages P a S dsPIC33FJ06GS101 18 6 256 8 2 0 1 1 1 2x2(1) 0 3 0 1 1 3 6 13 SOIC dsPIC33FJ06GS102 28 6 256 16 2 0 1 1 1 2x2 0 3 0 1 1 3 6 21 SPDIP, SOIC, QFN-S dsPIC33FJ06GS202 28 6 1K 16 2 1 1 1 1 2x2 2 3 1 1 1 3 6 21 SPDIP, SOIC, QFN-S dsPIC33FJ16GS402 28 16 2K 16 3 2 2 1 1 3x2 0 3 0 1 1 4 8 21 SPDIP, SOIC, QFN-S dsPIC33FJ16GS404 44 16 2K 30 3 2 2 1 1 3x2 0 3 0 1 1 4 8 35 QFN, TQFP, VTLA dsPIC33FJ16GS502 28 16 2K 16 3 2 2 1 1 4x2(1) 4 3 1 1 2 6 8 21 SPDIP, SOIC, QFN-S, UQFN dsPIC33FJ16GS504 44 16 2K 30 3 2 2 1 1 4x2(1) 4 3 1 1 2 6 12 35 QFN, TQFP, VTLA Note 1: The PWM4H:PWM4L pins are remappable. 2: The PWM Fault pins and PWM synchronization pins are remappable. 3: Only two out of three interrupts are remappable. DS70000318G-page 2  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams 18-Pin SOIC = Pins are up to 5V tolerant MCLR 1 18 VDD AN0/RA0 2 d 17 VSS s AN1/RA1 3 P 16 PWM1L/RA3 IC AN2/RA2 4 3 15 PWM1H/RA4 3 AN3/RP0(1)/CN0/RB0 5 FJ 14 VCAP OSC1/CLKI/AN6/RP1(1)/CN1/RB1 6 06 13 VSS OSC2/CLKO/AN7/RP2(1)/CN2/RB2 7 GS 12 PGEC1/SDA1/RP7(1)/CN7/RB7 TCK/PGED2/INT0/RP3(1)/CN3/RB3 8 10 11 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 1 TMS/PGEC2/RP4(1)/CN4/RB4 9 10 TDO/RP5(1)/CN5/RB5 28-Pin SOIC, SPDIP = Pins are up to 5V tolerant MCLR 1 28 AVDD AN0/RA0 2 27 AVSS AN1/RA1 3 d 26 PWM1L/RA3 AN2/RA2 4 sP 25 PWM1H/RA4 AN3/RP0(1)/CN0/RB0 5 IC 24 PWM2L/RP14(1)/CN14/RB14 AN4/RP9(1)/CN9/RB9 6 33 23 PWM2H/RP13(1)/CN13/RB13 AN5/RP10(1)/CN10/RB10 7 FJ 22 RP12(1)/CN12/RB12 VSS 8 06 21 RP11(1)/CN11/RB11 OOSSCC12//CCLLKKION//RRPP21((11))//CCNN21//RRBB21 910 GS1 2109 VVCSASP TCK/PGED2/INT0/RP3(1)/CN3/RB3 11 02 18 PGEC1/SDA/RP7(1)/CN7/RB7 TMS/PGEC2/RP4(1)/CN4/RB4 12 17 PGED1/TDI/SCL/RP6(1)/CN6/RB6 VDD 13 16 TDO/RP5(1)/CN5/RB5 PGED3/RP8(1)/CN8/RB8 14 15 PGEC3/RP15(1)/CN15/RB15 28-Pin SPDIP, SOIC = Pins are up to 5V tolerant MCLR 1 28 AVDD AN0/CMP1A/RA0 2 27 AVSS AN1/CMP1B/RA1 3 d 26 PWM1L/RA3 AN2/CMP1C/CMP2A/RA2 4 sP 25 PWM1H/RA4 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 5 IC 24 PWM2L/RP14(1)/CN14/RB14 AN4/CMP2C/RP9(1)/CN9/RB9 6 33 23 PWM2H/RP13(1)/CN13/RB13 AN5/CMP2D/RP10(1)/CN10/RB10 7 FJ 22 TCK/RP12(1)/CN12/RB12 VSS 8 06 21 TMS/RP11(1)/CN11/RB11 OSC1/CLKIN/RP1(1)/CN1/RB1 9 G 20 VCAP OSC2/CLKO/RP2(1)/CN2/RB2 10 S2 19 VSS PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 11 02 18 PGEC1/SDA/RP7(1)/CN7/RB7 PGEC2/EXTREF/RP4(1)/CN4/RB4 12 17 PGED1/TDI/SCL/RP6(1)/CN6/RB6 VDD 13 16 TDO/RP5(1)/CN5/RB5 PGED3/RP8(1)/CN8/RB8 14 15 PGEC3/RP15(1)/CN15/RB15 Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals.  2008-2014 Microchip Technology Inc. DS70000318G-page 3

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 28-Pin SPDIP, SOIC = Pins are up to 5V tolerant MCLR 1 28 AVDD AN0/RA0 2 27 AVSS AN1/RA1 3 d 26 PWM1L/RA3 AN2/RA2 4 sP 25 PWM1H/RA4 AN3/RP0(1)/CN0/RB0 5 IC 24 PWM2L/RP14(1)/CN14/RB14 AN4/RP9(1)/CN9/RB9 6 33 23 PWM2H/RP13(1)/CN13/RB13 AN5/RP10(1)/CN10/RB10 7 FJ 22 TCK/PWM3L/RP12(1)/CN12/RB12 VSS 8 16 21 TMS/PWM3H/RP11(1)/CN11/RB11 OSC1/CLKIN/AN6/RP1(1)/CN1/RB1 9 G 20 VCAP OSC2/CLKO/AN7/RP2(1)/CN2/RB2 10 S4 19 VSS PGED2/INT0/RP3(1)/CN3/RB3 11 02 18 PGEC1/SDA/RP7(1)/CN7/RB7 PGEC2/RP4(1)/CN4/RB4 12 17 PGED1/TDI/SCL/RP6(1)/CN6/RB6 VDD 13 16 TDO/RP5(1)/CN5/RB5 PGED3/RP8(1)/CN8/RB8 14 15 PGEC3/RP15/CN15/RB15 28-Pin SPDIP, SOIC = Pins are up to 5V tolerant MCLR 1 28 AVDD AN0/CMP1A/RA0 2 27 AVSS AN1/CMP1B/RA1 3 d 26 PWM1L/RA3 AN2/CMP1C/CMP2A/RA2 4 sP 25 PWM1H/RA4 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 5 IC 24 PWM2L/RP14(1)/CN14/RB14 AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9 6 33 23 PWM2H/RP13(1)/CN13/RB13 AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10 7 FJ 22 TCK/PWM3L/RP12(1)/CN12/RB12 VSS 8 16 21 TMS/PWM3H/RP11(1)/CN11/RB11 OSC1/CLKIN/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1 9 G 20 VCAP OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2 10 S5 19 VSS PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 11 02 18 PGEC1/SDA/RP7(1)/CN7/RB7 PGEC2/EXTREF/RP4(1)/CN4/RB4 12 17 PGED1/TDI/SCL/RP6(1)/CN6/RB6 VDD 13 16 TDO/RP5(1)/CN5/RB5 CN8/RB8/PGED3/RP8(1)/CN8/RB8 14 15 PGEC3/RP15(1)/CN15/RB15 Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. DS70000318G-page 4  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 28-Pin QFN-S(2) = Pins are up to 5V tolerant A3A4 A1A0 L/RH/R N1/RN0/RCLRVDDVSSWM1WM1 AAMAAPP 28272625242322 AN2/RA2 1 21 PWM2L/RP14(1)/CN14/RB14 AN3/RP0(1)/CN0/RB0 2 20 PWM2H/RP13(1)/CN13/RB13 AN4/RP9(1)/CN9/RB9 3 19 TCK/RP12(1)/CN12/RB12 AN5/RP10(1)/CN10/RB10 4 dsPIC33FJ06GS10218 TMS/RP11(1)/CN11/RB11 VSS 5 17 VCAP OSC1/CLKIN/RP1(1)/CN1/RB1 6 16 VSS OSC2/CLKO/RP2(1)/CN2/RB2 7 15 PGEC1/SDA/RP7(1)/CN7/RB7 8 91011121314 34D8556 BBDB1BB RRVRBRR N3/N4/ N8/5/RN5/N6/ 1)/C1)/C 1)/CCN11)/C1)/C (RP3(RP4 (RP8(1)5/(RP5(RP6 0/2/ 3/P1O/L/ GED2/INTPGEC PGEDPGEC3/RTDD1/TDI/SC P E G P 28-Pin QFN-S = Pins are up to 5V tolerant 10 AA RR P1B/P1A/ RA3RA4 MM L/H/ N1/CN0/CCLRVDDVSSWM1WM1 AAMAAPP 28272625242322 AN2/CMP1C/CMP2A/RA2 1 21 PWM2L/RP14(1)/CN14/RB14 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 2 20 PWM2H/RP13(1)/CN13/RB13 AN4/CMP2C/RP9(1)/CN9/RB9 3 19 TCK/RP12(1)/CN12/RB12 AN5/CMP2D/RP10(1)/CN10/RB10 4 dsPIC33FJ06GS20218 TMS/RP11(1)/CN11/RB11 VSS 5 17 VCAP OSC1/CLKIN/RP1(1)/CN1/RB1 6 16 VSS OSC2/CLKO/RP2(1)/CN2/RB2 7 15 PGEC1/SDA/RP7(1)/CN7/RB7 8 91011121314 34D8556 BBDB1BB RRVRBRR N3/N4/ N8/5/RN5/N6/ 1)/C1)/C 1)/CCN11)/C1)/C (RP3(RP4 (RP8(1)5/(RP5(RP6 0/F/ 3/P1O/L/ COUT/INTC2/EXTRE PGEDPGEC3/RTDD1/TDI/SC AE E DG G 2/P P D E G P Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.  2008-2014 Microchip Technology Inc. DS70000318G-page 5

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 28-Pin QFN-S(2) A3A4 = Pins are up to 5V tolerant A1A0 L/RH/R N1/RN0/RCLRVDDVSSWM1WM1 AAMAAPP 28272625242322 AN2/RA2 1 21 PWM2L/RP14(1)/CN14/RB14 AN3/RP0(1)/CN0/RB0 2 20 PWM2H/RP13(1)/CN13/RB13 AN4/RP9(1)/CN9/RB9 3 19 TCK/PWM3L/RP12(1)/CN12/RB12 AN5/RP10(1)/CN10/RB10 4 dsPIC33FJ16GS40218 TMS/PWM3H/RP11(1)/CN11/RB11 VSS 5 17 VCAP OSC1/CLKIN/AN6/RP1(1)/CN1/RB1 6 16 VSS OSC2/CLKO/AN7/RP2(1)/CN2/RB2 7 15 PGEC1/SDA/RP7(1)/CN7/RB7 8 91011121314 34D8556 BBDB1BB RRVRBRR N3/N4/ N8/5/RN5/N6/ 1)/C1)/C 1)/CCN11)/C1)/C (RP3(RP4 (RP8(1)5/(RP5(RP6 0/2/ 3/P1O/L/ GED2/INTPGEC PGEDPGEC3/RTDD1/TDI/SC P E G P 28-Pin QFN-S, UQFN(2,3) = Pins are up to 5V tolerant 10 AA RR P1B/P1A/ RA3RA4 MM L/H/ N1/CN0/CCLRVDDVSSWM1WM1 AAMAAPP 28272625242322 AN2/CMP1C/CMP2A/RA2 1 21 PWM2L/RP14(1)/CN14/RB14 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 2 20 PWM2H/RP13(1)/CN13/RB13 AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9 3 19 TCK/PWM3L/RP12(1)/CN12/RB12 AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10 4 dsPIC33FJ16GS50218 TMS/PWM3H/RP11(1)/CN11/RB11 VSS 5 17 VCAP OSC1/CLKIN/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1 6 16 VSS OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2 7 15 PGEC1/SDA/RP7(1)/CN7/RB7 8 91011121314 34D8556 BBDB1BB RRVRBRR N3/N4/ N8/5/RN5/N6/ (1)RP3/C(1)RP4/C (1)RP8/C(1)5/CN1(1)RP5/C(1)RP6/C NT0/EF/ D3/RP1DO/CL/ ACOUT/IC2/EXTR PGEPGEC3/TD1/TDI/S DE E 2/G G DP P E G P Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 3: This package is available only in Extended temperature and not Industrial temperature (applies to dsPIC33FJ16GS502 UQFN package only). DS70000318G-page 6  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin VTLA(2) = Pins are up to 5V tolerant 6 B R N6/ 15 RB3 (1)GED1/TDI/SCL/RP6/C (1)DO/RP5/CN5/RB5 (1)GEC3/RP15/CN15/RB (1)GED3/RP8/CN8/RB8 DD SS (1)P24/CN24/RC8 (1)P23/CN23/RC7 (1)P18/CN18/RC2 (1)GEC2/RP4/CN4/RB4 (1)GED2/INT0/RP3/CN3/ P T P P V V R R R P P 44 43 42 41 40 39 38 37 36 35 34 33 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 PGEC1/SDA/RP7(1)/CN7/RB7 1 32 OSC1/CLKI/AN6/RP1(1)/CN1/RB1 RP20(1)/CN20/RC4 2 31 RP17(1)/CN17/RC1 RP21(1)/CN21/RC5 3 30 VSS RP22(1)/CN22/RC6 4 29 VDD RP19(1)/CN19/RC3 5 dsPIC33FJ16GS404 28 RP26(1)/CN26/RC10 VSS 6 27 RP25(1)/CN25/RC9 VCAP 7 26 AN5/RP10(1)/CN10/RB10 TMS/PWM3H/RP11(1)/CN11/RB11 8 25 AN4/RP9(1)/CN9/RB9 TCK/PWM3L/RP12(1)/CN12/RB12 9 24 AN3/RP0(1)/CN0/RB0 PWM2H/RP13(1)/CN13/RB13 10 23 AN2/RA2 PWM2L/RP14(1)/CN14/RB14 11 12 13 14 15 16 17 18 19 20 21 22 4 3 0 3 S D R 1 2 0 1 PWM1H/RA PWM1L/RA (1)16/CN16/RC (1)9/CN29/RC1 AVS AVD MCL (1)7/CN27/RC1 (1)8/CN28/RC1 AN0/RA AN1/RA P 2 2 2 R P P P R R R Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.  2008-2014 Microchip Technology Inc. DS70000318G-page 7

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin VTLA(2) = Pins are up to 5V tolerant 2 C 3 R B 8/ R 6 N1 N3/ B C C (1)GED1/TDI/SCL/RP6/CN6/R (1)DO/RP5/CN5/RB5 (1)GEC3/RP15/CN15/RB15 (1)GED3/RP8/CN8/RB8 DD SS (1)P24/CN24/RC8 (1)P23/CN23/RC7 (1)N9/EXTREF/CMP4D/RP18/ (1)GEC2/RP4/CN4/RB4 (1)GED2/DACOUT/INT0/RP3/ P T P P V V R R A P P 44 43 42 41 40 39 38 37 36 35 34 33 OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2 PGEC1/SDA/RP7(1)/CN7/RB7 1 32 OSC1/CLKI/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1 RP20(1)/CN20/RC4 2 31 AN8/CMP4C/RP17(1)/CN17/RC1 RP21(1)/CN21/RC5 3 30 VSS RP22(1)/RN22/RC6 4 29 VDD RP19(1)/CN19/RC3 5 dsPIC33FJ16GS504 28 AN10/RP26(1)/CN26/RC10 VSS 6 27 AN11/RP25(1)/CN25/RC9 VCAP 7 26 AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10 TMS/PWM3H/RP11(1)/CN11/RB11 8 25 AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9 TCK/PWM3L/RP12(1)/CN12/RB12 9 24 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 PWM2H/RP13(1)/CN13/RB13 10 23 AN2/CMP1C/CMP2A/RA2 PWM2L/RP14(1)/CN14/RB14 11 12 13 14 15 16 17 18 19 20 21 22 4 3 0 3 S D R 1 2 0 1 PWM1H/RA PWM1L/RA (1)16/CN16/RC (1)9/CN29/RC1 AVS AVD MCL (1)7/CN27/RC1 (1)8/CN28/RC1 N0/CMP1A/RA N1/CMP1B/RA P 2 2 2 A A R P P P R R R Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70000318G-page 8  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) = Pins are up to 5V tolerant 6 B R N6/ 15 RB3 (1)GED1/TDI/SCL/RP6/C(1)DO/RP5/CN5/RB5 (1)GEC3/RP15/CN15/RB(1)GED3/RP8/CN8/RB8 DD SS(1)P24/CN24/RC8(1)P23/CN23/RC7 (1)P18/CN18/RC2(1)GEC2/RP4/CN4/RB4(1)GED2/INT0/RP3/CN3/ PT P P VVR R R P P 44 43 42 41 40 39 38 3736 35 34 PGEC1/SDA/RP7(1)/CN7/RB7 1 33 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 RP20(1)/CN20/RC4 2 32 OSC1/CLKI/AN6/RP1(1)/CN1/RB1 RP21(1)/CN21/RC5 3 31 RP17(1)/CN17/RC1 RP22(1)/CN22/RC6 4 30 VSS RP19(1)/CN19/RC3 5 29 VDD VSS 6 dsPIC33FJ16GS404 28 RP26(1)/CN26/RC10 VCAP 7 27 RP25(1)/CN25/RC9 TMS/PWM3H/RP11(1)/CN11/RB11 8 26 AN5/RP10(1)/CN10/RB10 TCK/PWM3L/RP12(1)/CN12/RB12 9 25 AN4/RP9(1)/CN9/RB9 PWM2H/RP13(1)/CN13/RB13 10 24 AN3/RP0(1)/CN0/RB0 PWM2L/RP14(1)/CN14/RB14 11 23 AN2/RA2 12 13 1415 16 1718 19 20 21 22 4 3 03 S D R 1 20 1 PWM1H/RA PWM1L/RA(1)16/CN16/RC(1)9/CN29/RC1 AVS AVD MCL(1)7/CN27/RC1(1)8/CN28/RC1AN0/RA AN1/RA P2 2 2 RP P P R R R Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.  2008-2014 Microchip Technology Inc. DS70000318G-page 9

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) = Pins are up to 5V tolerant 2 C 3 R B 8/ R 6 N1 N3/ B C C (1)GED1/TDI/SCL/RP6/CN6/R(1)DO/RP5/CN5/RB5 (1)GEC3/RP15/CN15/RB15(1)GED3/RP8/CN8/RB8 DD SS(1)P24/CN24/RC8(1)P23/CN23/RC7 (1)N9/EXTREF/CMP4D/RP18/(1)GEC2/RP4/CN4/RB4(1)GED2/DACOUT/INT0/RP3/ P T P P VVR R A P P 44 4342 41 4039 38 37 36 35 34 PGEC1/SDA/RP7(1)/CN7/RB7 1 33 OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2 RP20(1)/CN20/RC4 2 32 OSC1/CLKI/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1 RP21(1)/CN21/RC5 3 31 AN8/CMP4C/RP17(1)/CN17/RC1 RP22(1)/RN22/RC6 4 30 VSS RP19(1)/CN19/RC3 5 29 VDD VSS 6 dsPIC33FJ16GS504 28 AN10/RP26(1)/CN26/RC10 VCAP 7 27 AN11/RP25(1)/CN25/RC9 TMS/PWM3H/RP11(1)/CN11/RB11 8 26 AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10 TCK/PWM3L/RP12(1)/CN12/RB12 9 25 AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9 PWM2H/RP13(1)/CN13/RB13 10 24 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 PWM2L/RP14(1)/CN14/RB14 11 23 AN2/CMP1C/CMP2A/RA2 12 1314 15 1617 18 19 20 21 22 4 3 03 S D R 1 20 1 PWM1H/RA PWM1L/RA(1)16/CN16/RC(1)9/CN29/RC1 AVS AVD MCL(1)7/CN27/RC1(1)8/CN28/RC1N0/CMP1A/RA N1/CMP1B/RA P2 2 2A A RP P P R R R Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70000318G-page 10  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin TQFP = Pins are up to 5V tolerant 6 B R N6/ 15 RB3 (1)GED1/TDI/SCL/RP6/C(1)DO/RP5/CN5/RB5(1)GEC3/RP15/CN15/RB(1)GED3/RP8/CN8/RB8 DD SS(1)P24/CN24/RC8(1)P23/CN23/RC7(1)P18/CN18/RC2 (1)GEC2/RP4/CN4/RB4(1)GED2/INT0/RP3/CN3/ PTP P V VR RR PP 4 3 21 0 9 8 76 5 4 PGEC1/SDA/RP7(1)/CN7/RB7 1 4 4 44 4 3 3 33 3 333 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 RP20(1)/CN20/RC4 2 32 OSC1/CLKI/AN6/RP1(1)/CN1/RB1 RP21(1)/CN21/RC5 3 31 RP17(1)/CN17/RC1 RP22(1)/CN22/RC6 4 30 VSS RP19(1)/CN19/RC3 5 dsPIC33FJ16GS404 29 VDD VSS 6 28 RP26(1)/CN26/RC10 VCAP 7 27 RP25(1)/CN25/RC9 TMS/PWM3H/RP11(1)/CN11/RB11 8 26 AN5/RP10(1)/CN10/RB10 TCK/PWM3L/RP12(1)/CN12/RB12 9 25 AN4/RP9(1)/CN9/RB9 PWM2H/RP13(1)/CN13/RB13 10 24 AN3/RP0(1)/CN0/RB0 PWM2L/RP14(1)/CN14/RB14 11 23 AN2/RA2 11 1 11 1 1 1 2 22 23 4 56 7 8 9 0 12 4 3 0 3 S D R1 2 01 PWM1H/RA PWM1L/RA(1)16/CN16/RC(1)9/CN29/RC1AVS AVD MCL(1)7/CN27/RC1(1)8/CN28/RC1 AN0/RAAN1/RA P 2 2 2 R P P P R R R Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals.  2008-2014 Microchip Technology Inc. DS70000318G-page 11

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin TQFP = Pins are up to 5V tolerant 2 C 3 R B 8/ R 6 N1 N3/ B C C (1)GED1/TDI/SCL/RP6/CN6/R(1)DO/RP5/CN5/RB5(1)GEC3/RP15/CN15/RB15(1)GED3/RP8/CN8/RB8 DD SS(1)P24/CN24/RC8(1)P23/CN23/RC7(1)N9/EXTREF/CMP4D/RP18/ (1)GEC2/RP4/CN4/RB4(1)GED2/DACOUT/INT0/RP3/ PTP P V VR RA PP 4 3 21 0 9 8 76 5 4 4 4 44 4 3 3 33 3 3 PGEC1/SDA/RP7(1)/CN7/RB7 1 33 OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2 RP20(1)/CN20/RC4 2 32 OSC1/CLKI/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1 RP21(1)/CN21/RC5 3 31 AN8/CMP4C/RP17(1)/CN17/RC1 RP22(1)/CN22/RC6 4 30 VSS RP19(1)/CN19/RC3 5 dsPIC33FJ16GS504 29 VDD VSS 6 28 AN10/RP26(1)/CN26/RC10 VCAP 7 27 AN11/RP25(1)/CN25/RC9 TMS/PWM3H/RP11(1)/CN11/RB11 8 26 AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10 TCK/PWM3L/RP12(1)/CN12/RB12 9 25 AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9 PWM2H/RP13(1)/CN13/RB13 10 24 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 PWM2L/RP14(1)/CN14/RB14 11 23 AN2/CMP1C/CMP2A/RA2 11 1 11 1 1 1 2 22 23 4 56 7 8 9 0 12 4 3 0 3 S D R1 2 01 PWM1H/RA PWM1L/RA(1)16/CN16/RC(1)9/CN29/RC1AVS AVD MCL(1)7/CN27/RC1(1)8/CN28/RC1 N0/CMP1A/RAN1/CMP1B/RA P 2 2 2 AA R P P P R R R Note 1: The RPn pins can be used by any remappable peripheral. See Table1 for the list of available peripherals. DS70000318G-page 12  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Table of Contents dsPIC33FJ06GS101/X02 AND dsPIC33FJ16GSX02/X04 Product Families.........................................................................................2 1.0 Device Overview........................................................................................................................................................................17 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers..........................................................................................21 3.0 CPU............................................................................................................................................................................................31 4.0 Memory Organization.................................................................................................................................................................43 5.0 Flash Program Memory..............................................................................................................................................................83 6.0 Resets .......................................................................................................................................................................................89 7.0 Interrupt Controller.....................................................................................................................................................................97 8.0 Oscillator Configuration .........................................................................................................................................................135 9.0 Power-Saving Features............................................................................................................................................................147 10.0 I/O Ports...................................................................................................................................................................................155 11.0 Timer1......................................................................................................................................................................................183 12.0 Timer2/3 Features ...................................................................................................................................................................185 13.0 Input Capture............................................................................................................................................................................191 14.0 Output Compare.......................................................................................................................................................................193 15.0 High-Speed PWM.....................................................................................................................................................................197 16.0 Serial Peripheral Interface (SPI)...............................................................................................................................................219 17.0 Inter-Integrated Circuit (I2C™).................................................................................................................................................225 18.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................233 19.0 High-Speed 10-bit Analog-to-Digital Converter (ADC).............................................................................................................239 20.0 High-Speed Analog Comparator..............................................................................................................................................263 21.0 Special Features......................................................................................................................................................................267 22.0 Instruction Set Summary..........................................................................................................................................................275 23.0 Development Support...............................................................................................................................................................283 24.0 Electrical Characteristics..........................................................................................................................................................287 25.0 High-Temperature Electrical Characteristics............................................................................................................................333 26.0 50 MIPS Electrical Characteristics...........................................................................................................................................341 27.0 DC and AC Device Characteristics Graphs..............................................................................................................................347 28.0 Packaging Information..............................................................................................................................................................351 The Microchip Web Site.....................................................................................................................................................................393 Customer Change Notification Service..............................................................................................................................................393 Customer Support..............................................................................................................................................................................393 Product Identification System............................................................................................................................................................395  2008-2014 Microchip Technology Inc. DS70000318G-page 13

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70000318G-page 14  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33/PIC24 Family Ref- erence Manual”. These documents should be considered as the primary reference for the operation of a particular module or device feature. Note: To access the documents listed below, browse to the documentation section of the dsPIC33FJ16GS504 product page of the Microchip web site (www.microchip.com). In addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections. • “Introduction” (DS70197) • “CPU” (DS70204) • “Data Memory” (DS70202) • “Program Memory” (DS70203) • “Flash Programming” (DS70191) • “Reset” (DS70192) • “Watchdog Timer (WDT) and Power-Saving Modes” (DS70196) • “I/O Ports” (DS70193) • “Timers” (DS70205) • “Input Capture” (DS70198) • “Output Compare” (DS70005157) • “Analog-to-Digital Converter (ADC)” (DS70621) • “UART” (DS70188) • “Serial Peripheral Interface (SPI)” (DS70206) • “Inter-Integrated Circuit™ (I2C™)” (DS70000195) • “CodeGuard™ Security (DS70199) • “Programming and Diagnostics” (DS70207) • “Device Configuration” (DS70194) • “Interrupts (Part IV)” (DS70300) • “Oscillator (Part IV)” (DS70307) • “High-Speed PWM Module” (DS70000323) • “High-Speed 10-Bit ADC” (DS70000321) • “High-Speed Analog Comparator” (DS70296) • “Oscillator (Part VI)” (DS70644)  2008-2014 Microchip Technology Inc. DS70000318G-page 15

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 16  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 1.0 DEVICE OVERVIEW This document contains device-specific information for the following dsPIC33F Digital Signal Controller (DSC) Note 1: This data sheet summarizes the features devices: of the dsPIC33FJ06GS101/X02 and • dsPIC33FJ06GS101 dsPIC33FJ16GSX02/X04 families of • dsPIC33FJ06GS102 devices. It is not intended to be a compre- • dsPIC33FJ06GS202 hensive reference source. To complement the information in this data sheet, refer to • dsPIC33FJ16GS402 the “dsPIC33F/PIC24H Family Reference • dsPIC33FJ16GS404 Manual”. Please see the Microchip web • dsPIC33FJ16GS502 site (www.microchip.com) for the latest • dsPIC33FJ16GS504 “dsPIC33F/PIC24H Family Reference Manual” sections. dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices contain extensive Digital Signal Processor 2: Some registers and associated bits (DSP) functionality with a high-performance, 16-bit described in this section may not be microcontroller (MCU) architecture. available on all devices. Refer to Section4.0 “Memory Organization” in Figure1-1 shows a general block diagram of the core and this data sheet for device-specific register peripheral modules in the dsPIC33FJ06GS101/X02 and and bit information. dsPIC33FJ16GSX02/X04 devices. Table1-1 lists the functions of the various pins shown in the pinout diagrams.  2008-2014 Microchip Technology Inc. DS70000318G-page 17

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 1-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 BLOCK DIAGRAM PSV & Table Data Access Control Block Y Data Bus Interrupt X Data Bus PORTA Controller 16 8 16 16 16 Data Latch Data Latch 23 23 PCU PCH PCL X RAM Y RAM PORTB Program Counter Stack Loop Address Address Control Control Latch Latch Logic Logic 16 23 16 16 PORTC Address Generator Units Address Latch Program Memory EA MUX Remappable Data Latch ROM Latch Pins 24 16 16 a at Instruction D Decode & al Control Instruction Reg er Lit 16 Control Signals to Various Blocks DSP Engine 16 x 16 Power-up W Register Array Timer Divide Support OSC2/CLKO Timing 16 OSC1/CLKI Generation Oscillator Start-up Timer FRC/LPRC Power-on Oscillators Reset 16-Bit ALU Watchdog Timer 16 Brown-out Voltage Reset Regulator VCAP VDD, VSS MCLR Tim1-e3rs UART1 ADC1 OOCC12 P4W x M2 Analog IC1 CNx I2C1 SPI1 Comparators 1-4 IC2 Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. DS70000318G-page 18  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer PPS Pin Name Description Type Type Capable AN0-AN11 I Analog No Analog input channels CLKI I ST/CMOS No External clock source input. Always associated with OSC1 pin function. CLKO O — No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. OSC1 I ST/CMOS No Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. OSC2 I/O — No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. CN0-CN29 I ST No Change Notification inputs. Can be software programmed for internal weak pull-ups on all inputs. IC1-IC2 I ST Yes Capture Inputs 1/2. OCFA I ST Yes Compare Fault A input (for Compare Channels 1 and 2) OC1-OC2 O — Yes Compare Outputs 1 through 2. INT0 I ST No External Interrupt 0. INT1 I ST Yes External Interrupt 1. INT2 I ST Yes External Interrupt 2. RA0-RA4 I/O ST No PORTA is a bidirectional I/O port. RB0-RB15 I/O ST No PORTB is a bidirectional I/O port. RC0-RC13 I/O ST No PORTC is a bidirectional I/O port. RP0-RP29 I/O ST No Remappable I/O pins. T1CK I ST Yes Timer1 external clock input. T2CK I ST Yes Timer2 external clock input. T3CK I ST Yes Timer3 external clock input. U1CTS I ST Yes UART1 Clear-To-Send. U1RTS O — Yes UART1 Ready-To-Send. U1RX I ST Yes UART1 receive. U1TX O — Yes UART1 transmit. SCK1 I/O ST Yes Synchronous serial clock input/output for SPI1. SDI1 I ST Yes SPI1 data in. SDO1 O — Yes SPI1 data out. SS1 I/O ST Yes SPI1 slave synchronization or frame pulse I/O. SCL1 I/O ST No Synchronous serial clock input/output for I2C1. SDA1 I/O ST No Synchronous serial data input/output for I2C1. TMS I TTL No JTAG Test mode select pin. TCK I TTL No JTAG test clock input pin. TDI I TTL No JTAG test data input pin. TDO O — No JTAG test data output pin. Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input ST = Schmitt Trigger input with CMOS levels P = Power O = Output TTL = Transistor-Transistor Logic PPS = Peripheral Pin Select  2008-2014 Microchip Technology Inc. DS70000318G-page 19

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer PPS Pin Name Description Type Type Capable CMP1A I Analog No Comparator 1 Channel A. CMP1B I Analog No Comparator 1 Channel B. CMP1C I Analog No Comparator 1 Channel C. CMP1D I Analog No Comparator 1 Channel D. CMP2A I Analog No Comparator 2 Channel A. CMP2B I Analog No Comparator 2 Channel B. CMP2C I Analog No Comparator 2 Channel C. CMP2D I Analog No Comparator 2 Channel D. CMP3A I Analog No Comparator 3 Channel A. CMP3B I Analog No Comparator 3 Channel B. CMP3C I Analog No Comparator 3 Channel C. CMP3D I Analog No Comparator 3 Channel D. CMP4A I Analog No Comparator 4 Channel A. CMP4B I Analog No Comparator 4 Channel B. CMP4C I Analog No Comparator 4 Channel C. CMP4D I Analog No Comparator 4 Channel D. DACOUT O — No DAC output voltage. ACMP1-ACMP4 O — Yes DAC trigger to PWM module. EXTREF I Analog No External voltage reference input for the reference DACs. REFCLKO O — Yes REFCLKO output signal is a postscaled derivative of the system clock. FLT1-FLT8 I ST Yes Fault Inputs to PWM module. SYNCI1-SYNCI2 I ST Yes External synchronization signal to PWM master time base. SYNCO1 O — Yes PWM master time base for external device synchronization. PWM1L O — No PWM1 low output. PWM1H O — No PWM1 high output. PWM2L O — No PWM2 low output. PWM2H O — No PWM2 high output. PWM3L O — No PWM3 low output. PWM3H O — No PWM3 high output. PWM4L O — Yes PWM4 low output. PWM4H O — Yes PWM4 high output. PGED1 I/O ST No Data I/O pin for programming/debugging Communication Channel 1. PGEC1 I ST No Clock input pin for programming/debugging Communication Channel 1. PGED2 I/O ST No Data I/O pin for programming/debugging Communication Channel 2. PGEC2 I ST No Clock input pin for programming/debugging Communication Channel 2. PGED3 I/O ST No Data I/O pin for programming/debugging Communication Channel 3. PGEC3 I ST No Clock input pin for programming/debugging Communication Channel 3. MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device. AVDD P P No Positive supply for analog modules. This pin must be connected at all times. AVDD is connected to VDD. AVSS P P No Ground reference for analog modules. AVSS is connected to VSS. VDD P — No Positive supply for peripheral logic and I/O pins. VCAP P — No CPU logic filter capacitor connection. VSS P — No Ground reference for logic and I/O pins. Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input ST = Schmitt Trigger input with CMOS levels P = Power O = Output TTL = Transistor-Transistor Logic PPS = Peripheral Pin Select DS70000318G-page 20  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors STARTED WITH 16-BIT The use of decoupling capacitors on every pair of DIGITAL SIGNAL power supply pins, such as VDD, VSS, AVDD and CONTROLLERS AVSS is required. Consider the following criteria when using decoupling Note1: This data sheet summarizes the features capacitors: of the dsPIC33FJ06GS101/X02 and • Value and type of capacitor: Recommendation dsPIC33FJ16GSX02/X04 family of of 0.1 µF (100 nF), 10-20V. This capacitor should devices. It is not intended to be a be a low-ESR and have resonance frequency in comprehensive reference source. To the range of 20MHz and higher. It is complement the information in this data recommended that ceramic capacitors be used. sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”, which is • Placement on the printed circuit board: The available from the Microchip web site decoupling capacitors should be placed as close (www.microchip.com). to the pins as possible. It is recommended to place the capacitors on the same side of the 2: Some registers and associated bits board as the device. If space is constricted, the described in this section may not be capacitor can be placed on another layer on the available on all devices. Refer to PCB using a via; however, ensure that the trace Section4.0 “Memory Organization” in length from the pin to the capacitor is within this data sheet for device-specific register one-quarter inch (6mm) in length. and bit information. • Handling high frequency noise: If the board is experiencing high frequency noise, upward of 2.1 Basic Connection Requirements tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling Getting started with the dsPIC33FJ06GS101/X02 and capacitor. The value of the second capacitor can dsPIC33FJ16GSX02/X04 family of 16-bit Digital Signal be in the range of 0.01µF to 0.001µF. Place this Controllers (DSC) requires attention to a minimal set of second capacitor next to the primary decoupling device pin connections before proceeding with capacitor. In high-speed circuit designs, consider development. The following is a list of pin names, which implementing a decade pair of capacitances as must always be connected: close to the power and ground pins as possible. • All VDD and VSS pins For example, 0.1 µF in parallel with 0.001 µF. (see Section2.2 “Decoupling Capacitors”) • Maximizing performance: On the board layout • All AVDD and AVSS pins (regardless if ADC module from the power supply circuit, run the power and is not used) return traces to the decoupling capacitors first, (see Section2.2 “Decoupling Capacitors”) and then to the device pins. This ensures that the • VCAP decoupling capacitors are first in the power chain. (see Section2.3 “Capacitor on Internal Voltage Equally important is to keep the trace length Regulator (VCAP)”) between the capacitor and the power pins to a • MCLR pin minimum thereby reducing PCB track inductance. (see Section2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section2.5 “ICSP™ Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section2.6 “External Oscillator Pins”)  2008-2014 Microchip Technology Inc. DS70000318G-page 21

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-1: RECOMMENDED The placement of this capacitor should be close to the MINIMUM CONNECTION VCAP. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section21.2 0.1 µF “On-Chip Voltage Regulator” for details. 10 µF Ceramic VDD Tantalum 2.4 Master Clear (MCLR) Pin R AP DD SS C V V The MCLR pin provides two specific device R1 V functions: MCLR • Device Reset C • Device programming and debugging. dsPIC33F During device programming and debugging, the VSS VDD resistance and capacitance that can be added to the pin must be considered. Device programmers and VDD VSS debuggers drive the MCLR pin. Consequently, 0.1 µF D S 0.1 µF Ceramic VD VS DD SS Ceramic specific voltage levels (VIH and VIL) and fast signal A A V V transitions must not be adversely affected. Therefore, 0.1 µF 0.1 µF specific values of R and C will need to be adjusted Ceramic Ceramic based on the application and PCB requirements. L1(1) For example, as shown in Figure2-2, it is recommended that the capacitor C, be isolated from Note 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and the MCLR pin during programming and debugging AVDD to improve ADC noise rejection. The inductor operations. impedance should be less than 1 and the inductor capacity greater than 10 mA. Place the components shown in Figure2-2 within one-quarter inch (6mm) from the MCLR pin. Where: FCNV f = -------------- (i.e., ADC conversion rate/2) FIGURE 2-2: EXAMPLE OF MCLR PIN 2 CONNECTIONS 1 f = ----------------------- 2 LC VDD L = ----------1------------2   R 2f C R1 MCLR 2.2.1 TANK CAPACITORS JP dsPIC33F On boards with power traces running longer than six C inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that con- Note 1: R  10 k is recommended. A suggested nects the power supply source to the device, and the starting value is 10 k. Ensure that the MCLR maximum current drawn by the device in the applica- pin VIH and VIL specifications are met. tion. In other words, select the tank capacitor so that it 2: R1  470 will limit any current flowing into meets the acceptable voltage sag at the device. Typical MCLR from the external capacitor, C, in the values range from 4.7µF to 47µF. event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin 2.3 Capacitor on Internal Voltage VIH and VIL specifications are met. Regulator (VCAP) A low-ESR (<5 Ohms) capacitor is required on the VCAP pin, which is used to stabilize the voltage regulator output voltage. The VCAP pin must not be connected to VDD, and must have a capacitor between 4.7µF and 10 µF, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section24.0 “Electrical Characteristics” for additional information. DS70000318G-page 22  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 2.5 ICSP™ Pins FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR The PGECx and PGEDx pins are used for In-Circuit CIRCUIT Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the Main Oscillator device as short as possible. If the ICSP connector is 13 expected to experience an ESD event, a series resistor Guard Ring 14 is recommended, with the value in the range of a few 15 tens of Ohms, not to exceed 100 Ohms. Guard Trace 16 Pull-up resistors, series diodes, and capacitors on the PGECx and PGEDx pins are not recommended as they Secondary 17 will interfere with the programmer/debugger Oscillator 18 communications to the device. If such discrete 19 components are an application requirement, they should be removed from the circuit during program- 20 ming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification 2.7 Oscillator Value Conditions on for information on capacitive loading limits and pin input Device Start-up voltage high (VIH) and input low (VIL) requirements. If the PLL of the target device is enabled and Ensure that the “Communication Channel Select” configured for the device start-up oscillator, the (i.e.,PGECx/PGEDx pins) programmed into the device maximum oscillator source frequency must be limited matches the physical connections for the ICSP to MPLAB® ICD 3 or MPLAB® REAL ICE™. to 4 MHz < FIN < 8 MHz to comply with device PLL start-up conditions. This means that if the external For more information on ICD 3 and REAL ICE oscillator frequency is outside this range, the connection requirements, refer to the following application must start up in the FRC mode first. The documents that are available on the Microchip web site. default PLL settings after a POR with an oscillator • “Using MPLAB® ICD 3” (poster) DS51765 frequency outside this range will violate the device • “MPLAB® ICD 3 Design Advisory” DS51764 operating speed. • “MPLAB® REAL ICE™ In-Circuit Debugger Once the device powers up, the application firmware User’s Guide” DS51616 can initialize the PLL SFRs, CLKDIV, and PLLFBD to a • “Using MPLAB® REAL ICE™” (poster) DS51749 suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration Word. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure2-3.  2008-2014 Microchip Technology Inc. DS70000318G-page 23

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 2.8 Configuration of Analog and 2.9 Unused I/Os Digital Pins During ICSP Unused I/O pins should be configured as outputs and Operations driven to a logic-low state. If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a Alternatively, connect a 1k to 10k resistor between VSS debugger, it automatically initializes all of the A/D input and unused pins and drive the output to logic low. pins (ANx) as “digital” pins, by setting all bits in the ADPCFG register. 2.10 Typical Application Connection The bits in the registers that correspond to the A/D pins Examples that are initialized by MPLAB ICD 2, ICD 3, or REAL Examples of typical application connections are shown ICE, must not be cleared by the user application firm- in Figure2-4 through Figure2-11. ware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG register during initialization of the ADC module. When MPLAB ICD 2, ICD 3, or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of these registers is only done during debugger opera- tion. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. DS70000318G-page 24  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-4: DIGITAL PFC IPFC VHV_BUS |VAC| k1 k3 VAC k FET 2 Driver ADC Channel ADC Channel PWM Output ADC Channel dsPIC33FJ06GS101 FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION IPFC VINPUT VOUTPUT k1 k3 k FET 2 Driver ADC Channel ADC PWM ADC Channel Channel Output dsPIC33FJ06GS101  2008-2014 Microchip Technology Inc. DS70000318G-page 25

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input 5V Output I 5V k7 DFrEivTer k1 k2 ADC M M Analog ADC Channel W W Comp. Channel P P dsPIC33FJ06GS202 FIGURE 2-7: MULTI-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input 3.3V Output k 6 k FET FET 7 Driver Driver ADC MM MM Channel WW WW PWM FET PP PP PWM Driver Analog Comparator k3 dsPIC33FJ06GS502 Analog Comparator k4 Analog Comparator k5 ADC Channel DS70000318G-page 26  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-8: OFF-LINE UPS VDC Push-Pull Converter Full-Bridge Inverter VOUT+ VBAT + VOUT- GND GND FET FET FET FET FET FET Driver Driver k2 k1 Driver Driver Driver Driver k4 k5 PWM PWM ADC ADC PWM PWM PWM PWM or Analog Comp. k3 ADC dsPIC33FJ16GS504 ADC ADC ADC PWM FET k Driver 6 + Battery Charger  2008-2014 Microchip Technology Inc. DS70000318G-page 27

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-9: INTERLEAVED PFC VOUT+ |VAC| k4 VAC k3 k k 1 2 VOUT- FET FET Driver Driver ADC Channel PWM ADC PWM ADC ADC Channel Channel Channel dsPIC33FJ06GS202 ADC Channel DS70000318G-page 28  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-10: PHASE-SHIFTED FULL-BRIDGE CONVERTER VIN+ Gate 6 Gate 3 Gate 1 VOUT+ S1 S3 VOUT- Gate 2 Gate 4 Gate 5 VIN- Gate 5 6 e at G FET k Driver 2 k 1 Analog Gate 1 Ground FET PWM ADC PWM ADC S1 Driver Channel Channel Gate 3 dsPIC33FJ06GS202 FET Driver S3 PWM Gate 2 Gate 4  2008-2014 Microchip Technology Inc. DS70000318G-page 29

D FIGURE 2-11: AC-TO-DC POWER SUPPLY WITH PFC AND THREE OUTPUTS (12V, 5V AND 3.3V) d S 7 s 0 0 ZVT with Current Doubler Synchronous Rectifier P 0 0318 VHV_BUS IsBoalarrtiieorn VOUT IC G -p IZVT 3 a 3 g e 3 3.3V Multi-Phase Buck Stage F 0 3.3V Output J 12V Input 0 I3.3V_1 6 G FET FET S Driver Driver k4 DFrEivTer 5V Buck Stage 5V Output 1 I5V I3.3V_2 01 PWM PWM PWM PWM ChAaDnCnel ChAaDnCnel DFriEveTr DFriEveTr /X0 PWM dPsrPimICa3r3yF CJo1n6GtroSl5le0r4 PWM k5 DFrEivTer k6 k7 I3.3V_3 k11 2 a n ADC ADC PWM ADC UART Ch. Ch. Output Ch. RX d ChAaDnCnel PWM PWM ACnoamlopg. ChAaDnCnel PWMPWM PWMPWM PPWWMM DFrEivTer d Analog Comparator k8 s Secondary Controller P dsPIC33FJ16GS504 Analog Comparator k9 I C PFC Stage k2 FET Driver UATRXT Analog Comparator k10 3 3 ADC Channel F  J 20 VAC 1 0 8-2 k3 6 0 G 1 4 M S icro X chip T k1 02 e / ch |VAC| X no VHV_BUS 0 log IPFC 4 y In c .

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.0 CPU 3.1 Data Addressing Overview The data space can be addressed as 32K words or Note1: This data sheet summarizes the features 64Kbytes and is split into two blocks, referred to as X of the dsPIC33FJ06GS101/X02 and and Y data memory. Each memory block has its own dsPIC33FJ16GSX02/X04 families of independent Address Generation Unit (AGU). The devices. It is not intended to be a MCU class of instructions operates solely through the comprehensive reference source. To X memory AGU, which accesses the entire memory complement the information in this data map as one linear data space. Certain DSP instructions sheet, refer to “CPU” (DS70204) in the operate through the X and Y AGUs to support dual “dsPIC33F/PIC24H Family Reference operand reads, which splits the data address space Manual”, which is available from the into two parts. The X and Y data space boundary is Microchip web site (www.microchip.com). device-specific. 2: Some registers and associated bits Overhead-free circular buffers (Modulo Addressing described in this section may not be mode) are supported in both X and Y address spaces. available on all devices. Refer to The Modulo Addressing removes the software Section4.0 “Memory Organization” in boundary checking overhead for DSP algorithms. this data sheet for device-specific register Furthermore, the X AGU circular addressing can be and bit information. used with any of the MCU class of instructions. The X The CPU module has a 16-bit (data) modified Harvard AGU also supports Bit-Reversed Addressing to greatly architecture with an enhanced instruction set, including simplify input or output data reordering for radix-2 FFT significant support for DSP. The CPU has a 24-bit algorithms. instruction word with a variable length opcode field. The upper 32 Kbytes of the data space memory map The Program Counter (PC) is 23 bits wide and can optionally be mapped into program space at any addresses up to 4M x 24 bits of user program memory 16K program word boundary defined by the 8-bit space. The actual amount of program memory Program Space Visibility Page (PSVPAG) register. The implemented varies from device to device. A single- program-to-data space mapping feature allows any cycle instruction prefetch mechanism is used to help instruction access program space as if it were data maintain throughput and provides predictable space. execution. All instructions execute in a single cycle, with the exception of instructions that change the 3.2 DSP Engine Overview program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free The DSP engine features a high-speed, 17-bit by 17-bit program loop constructs are supported using the DO multiplier, a 40-bit ALU, two 40-bit saturating and REPEAT instructions, both of which are accumulators and a 40-bit bidirectional barrel shifter. interruptible at any point. The barrel shifter is capable of shifting a 40-bit value up dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ to 16 bits, right or left, in a single cycle. The DSP X04 devices have sixteen, 16-bit Working registers in instructions operate seamlessly with all other the programmer’s model. Each of the Working registers instructions and have been designed for optimal real- can serve as a data, address or address offset register. time performance. The MAC instruction and other The sixteenth Working register (W15) operates as a associated instructions can concurrently fetch two data software Stack Pointer (SP) for interrupts and calls. operands from memory while multiplying two W registers and accumulating and optionally saturating There are two classes of instruction in the the result in the same cycle. This instruction dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ functionality requires that the RAM data space be split X04 devices: MCU and DSP. These two instruction for these instructions and linear for all others. Data classes are seamlessly integrated into a single CPU. space partitioning is achieved in a transparent and The instruction set includes many addressing modes flexible manner through dedicating certain Working and is designed for optimum C compiler efficiency. For registers to each address space. most instructions, the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 is capable of executing a data (or program data) memory read, a Working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure3-1, and the programmer’s model is shown in Figure3-2.  2008-2014 Microchip Technology Inc. DS70000318G-page 31

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.3 Special MCU Features The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices support 16/16 and 32/16 divide operations, dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 both fractional and integer. All divide instructions are iter- devices feature a 17-bit by 17-bit single-cycle multi- ative operations. They must be executed within a REPEAT plier that is shared by both the MCU ALU and DSP loop, resulting in a total execution time of 19instruction engine. The multiplier can perform signed, unsigned cycles. The divide operation can be interrupted during any and mixed sign multiplication. Using a 17-bit by 17-bit of those 19cycles without loss of data. multiplier for 16-bit by 16-bit multiplication not only A 40-bit barrel shifter is used to perform up to a 16-bit allows you to perform mixed sign multiplication, it left or right shift in a single cycle. The barrel shifter can also achieves accurate results for special operations, be used by both MCU and DSP instructions. such as (-1.0)x(1.0). FIGURE 3-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Y Data Bus Interrupt X Data Bus Controller 8 16 16 16 16 Data Latch Data Latch 23 PCU PCH PCL X RAM Y RAM 16 23 Program Counter Stack Loop Address Address Control Control Latch Latch Logic Logic 23 16 16 Address Latch Address Generator Units Program Memory EA MUX Data Latch ROM Latch 24 16 16 a at Instruction D Decode & al Control Instruction Reg er Lit 16 Control Signals to Various Blocks DSP Engine 16 x 16 W Register Array Divide Support 16 16-Bit ALU 16 To Peripheral Modules DS70000318G-page 32  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 3-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.SShadow W1 DOShadow W2 W3 Legend W4 DSP Operand W5 Registers W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register AD39 AD31 AD15 AD0 DSP ACCA Accumulators ACCB PC22 PC0 0 Program Counter 7 0 TBLPAG Data Table Page Address 7 0 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address 22 DOEND DO Loop End Address 15 0 CORCON Core Configuration Register OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRH SRL  2008-2014 Microchip Technology Inc. DS70000318G-page 33

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.4 CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0 OA OB SA(1) SB(1) OAB SAB(1,4) DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 15 OA: Accumulator A Overflow Status bit 1 = Accumulator A has overflowed 0 = Accumulator A has not overflowed bit 14 OB: Accumulator B Overflow Status bit 1 = Accumulator B has overflowed 0 = Accumulator B has not overflowed bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit 1 = Accumulator A or B has overflowed 0 = Neither Accumulator A or B has overflowed bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit(1,4) 1 = Accumulator A or B is saturated or has been saturated at some time in the past 0 = Neither Accumulator A or B is saturated bit 9 DA: DO Loop Active bit 1 = DO loop in progress 0 = DO loop not in progress bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred Note 1: This bit can be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). 4: Clearing this bit will clear SA and SB. DS70000318G-page 34  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 1 Z: MCU ALU Zero bit 1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit (MSb) of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: This bit can be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). 4: Clearing this bit will clear SA and SB.  2008-2014 Microchip Technology Inc. DS70000318G-page 35

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT(1) DL2 DL1 DL0 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 15-13 Unimplemented: Read as ‘0’ bit 12 US: DSP Multiply Unsigned/Signed Control bit 1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed bit 11 EDT: Early DO Loop Termination Control bit(1) 1 = Terminate executing DO loop at end of current loop iteration 0 = No effect bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits 111 = 7 DO loops are active • • • 001 = 1 DO loop is active 000 = 0 DO loops are active bit 7 SATA: ACCA Saturation Enable bit 1 = Accumulator A saturation is enabled 0 = Accumulator A saturation is disabled bit 6 SATB: ACCB Saturation Enable bit 1 = Accumulator B saturation is enabled 0 = Accumulator B saturation is disabled bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation is enabled 0 = Data space write saturation is disabled bit 4 ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space is visible in data space 0 = Program space is not visible in data space Note 1: This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS70000318G-page 36  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 3-2: CORCON: CORE CONTROL REGISTER (CONTINUED) bit 1 RND: Rounding Mode Select bit 1 = Biased (conventional) rounding is enabled 0 = Unbiased (convergent) rounding is enabled bit 0 IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode is enabled for DSP multiply ops 0 = Fractional mode is enabled for DSP multiply ops Note 1: This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.  2008-2014 Microchip Technology Inc. DS70000318G-page 37

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.5 Arithmetic Logic Unit (ALU) 3.6 DSP Engine The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ The DSP engine consists of a high-speed, 17-bit x 17-bit X04 ALU is 16 bits wide and is capable of addition, multiplier, a barrel shifter and a 40-bit adder/subtracter subtraction, bit shifts and logic operations. Unless (with two target accumulators, round and saturation otherwise mentioned, arithmetic operations are 2’s com- logic). plement in nature. Depending on the operation, the ALU The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ can affect the values of the Carry (C), Zero (Z), X04 is a single-cycle instruction flow architecture; Negative(N), Overflow (OV) and Digit Carry (DC) Status therefore, concurrent operation of the DSP engine with bits in the SR register. The C and DC Status bits operate MCU instruction flow is not possible. However, some as Borrow and Digit Borrow bits, respectively, for MCU ALU and DSP engine resources can be used subtraction operations. concurrently by the same instruction (for example, ED, The ALU can perform 8-bit or 16-bit operations, EDAC). depending on the mode of the instruction that is used. The DSP engine can also perform inherent Data for the ALU operation can come from the W accumulator-to-accumulator operations that require no register array or data memory, depending on the additional data. These instructions are ADD, SUB and addressing mode of the instruction. Likewise, output NEG. data from the ALU can be written to the W register array or a data memory location. The DSP engine has options selected through bits in the CPU Core Control register (CORCON), as listed Refer to the “16-bit MCU and DSC Programmer’s below: Reference Manual” (DS70157) for information on the SR bits affected by each instruction. • Fractional or Integer DSP Multiply (IF) • Signed or Unsigned DSP Multiply (US) The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 CPU incorporates hardware support for both multipli- • Conventional or Convergent Rounding (RND) cation and division. This includes a dedicated hardware • Automatic Saturation On/Off for ACCA (SATA) multiplier and support hardware for 16-bit-divisor division. • Automatic Saturation On/Off for ACCB (SATB) • Automatic Saturation On/Off for Writes to Data 3.5.1 MULTIPLIER Memory (SATDW) Using the high-speed, 17-bit x 17-bit multiplier of the • Accumulator Saturation mode Selection DSP engine, the ALU supports unsigned, signed or (ACCSAT) mixed sign operation in several MCU multiplication A block diagram of the DSP engine is shown in modes: Figure3-3. • 16-bit x 16-bit signed • 16-bit x 16-bit unsigned TABLE 3-1: DSP INSTRUCTIONS • 16-bit signed x 5-bit (literal) unsigned SUMMARY • 16-bit unsigned x 16-bit unsigned Algebraic ACC • 16-bit unsigned x 5-bit (literal) unsigned Instruction Operation Write Back • 16-bit unsigned x 16-bit signed CLR A = 0 Yes • 8-bit unsigned x 8-bit unsigned ED A = (x – y)2 No 3.5.2 DIVIDER EDAC A = A + (x – y)2 No The divide block supports 32-bit/16-bit and 16-bit/16-bit MAC A = A + (x * y) Yes signed and unsigned integer divide operations with the MAC A = A + x2 No following data sizes: MOVSAC No change in A Yes • 32-bit signed/16-bit signed divide MPY A = x * y No • 32-bit unsigned/16-bit unsigned divide MPY A = x 2 No • 16-bit signed/16-bit signed divide MPY.N A = – x * y No • 16-bit unsigned/16-bit unsigned divide MSC A = A – x * y Yes The quotient for all divide instructions ends up in W0 and the remainder in W1. The 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m+1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/ 16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. DS70000318G-page 38  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM S 40 40-Bit Accumulator A a 40 Round t 16 40-Bit Accumulator B u Logic r Carry/Borrow Out a Saturate t e Carry/Borrow In Adder Negate 40 40 40 Barrel 16 Shifter 40 us B a Sign-Extend at D X s u B a 32 16 at Zero Backfill D Y 32 33 17-Bit Multiplier/Scaler 16 16 To/From W Array  2008-2014 Microchip Technology Inc. DS70000318G-page 39

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.6.1 MULTIPLIER 3.6.2.1 Adder/Subtracter, Overflow and Saturation The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a The adder/subtracter is a 40-bit adder with an optional scaler to support either 1.31 fractional (Q31) or 32-bit zero input into one side, and either true or complement integer results. Unsigned operands are zero-extended data into the other input. into the 17th bit of the multiplier input value. Signed • In the case of addition, the Carry/Borrow input is operands are sign-extended into the 17th bit of the active-high and the other input is true data (not multiplier input value. The output of the 17-bit x 17-bit complemented). multiplier/scaler is a 33-bit value that is sign-extended • In the case of subtraction, the Carry/Borrow input to 40 bits. Integer data is inherently represented as a is active-low and the other input is complemented. signed 2’s complement value, where the Most Significant bit (MSb) is defined as a sign bit. The range The adder/subtracter generates Overflow Status bits, of an N-bit 2’s complement integer is -2N-1 to 2N-1 – 1. SA/SB and OA/OB, which are latched and reflected in the STATUS Register: • For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF), including 0. • Overflow from bit 39: this is a catastrophic • For a 32-bit integer, the data range is overflow in which the sign of the accumulator is -2,147,483,648 (0x80000000) to 2,147,483,647 destroyed. (0x7FFF FFFF). • Overflow into guard bits, 32 through 39: this is a recoverable overflow. This bit is set whenever all When the multiplier is configured for fractional the guard bits are not identical to each other. multiplication, the data is represented as a 2’s complement fraction, where the MSb is defined as a The adder has an additional saturation block that sign bit and the radix point is implied to lie just after the controls accumulator data saturation, if selected. It sign bit (QX format). The range of an N-bit uses the result of the adder, the Overflow Status bits 2’scomplement fraction with this implied radix point is described previously and the SAT<A:B> -1.0 to (1 – 21-N). For a 16-bit fraction, the Q15 data (CORCON<7:6>) and ACCSAT (CORCON<4>) mode range is -1.0 (0x8000) to 0.999969482 (0x7FFF) control bits to determine when and to what value to including 0 and has a precision of 3.01518x10-5. In saturate. Fractional mode, the 16 x 16 multiply operation Six STATUS Register bits support saturation and generates a 1.31product that has a precision of overflow: 4.65661 x 10-10. • OA: ACCA overflowed into guard bits The same multiplier is used to support the MCU • OB: ACCB overflowed into guard bits multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiply operations. • SA: ACCA saturated (bit 31 overflow and saturation) The MUL instruction can be directed to use byte or or word-sized operands. Byte operands will direct a 16-bit ACCA overflowed into guard bits and saturated result, and word operands will direct a 32-bit result to (bit 39 overflow and saturation) the specified register(s) in the W array. • SB: ACCB saturated (bit 31 overflow and 3.6.2 DATA ACCUMULATORS AND saturation) or ADDER/SUBTRACTER ACCB overflowed into guard bits and saturated The data accumulator consists of a 40-bit adder/ (bit 39 overflow and saturation) subtracter with automatic sign extension logic. It can • OAB: Logical OR of OA and OB select one of two accumulators (A or B) as its pre- • SAB: Logical OR of SA and SB accumulation source and post-accumulation destination. For the ADD and LAC instructions, the data The OA and OB bits are modified each time data to be accumulated or loaded can be optionally scaled passes through the adder/subtracter. When set, they using the barrel shifter prior to accumulation. indicate that the most recent operation has overflowed into the accumulator guard bits(bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the correspond- ing Overflow Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1 register are set (refer to Section7.0 “Interrupt Controller”). This allows the user applica- tion to take immediate action, for example, to correct system gain. DS70000318G-page 40  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 The SA and SB bits are modified each time data 3.6.3 ACCUMULATOR ‘WRITE BACK’ passes through the adder/subtracter, but can only be The MAC class of instructions (with the exception of cleared by the user application. When set, they indicate MPY, MPY.N, ED and EDAC) can optionally write a that the accumulator has overflowed its maximum rounded version of the high word (bits 31 through 16) range (bit 31 for 32-bit saturation or bit 39 for 40-bit of the accumulator that is not targeted by the instruction saturation) and will be saturated (if saturation is into data space memory. The write is performed across enabled). When saturation is not enabled, SA and SB the X bus into combined X and Y address space. The default to bit 39 overflow and thus, indicate that a cata- following addressing modes are supported: strophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate • W13, Register Direct: an arithmetic warning trap when saturation is disabled. The rounded contents of the non-target accumulator are written into W13 as a 1.15fraction. The Overflow and Saturation Status bits can optionally be viewed in the STATUS Register (SR) as the logical • [W13] + = 2, Register Indirect with Post-Increment: OR of OA and OB (in bit OAB) and the logical OR of SA The rounded contents of the non-target and SB (in bit SAB). Programmers can check one bit accumulator are written into the address pointed in the STATUS Register to determine if either to by W13 as a 1.15 fraction. W13 is then accumulator has overflowed, or one bit to determine if incremented by 2 (for a word write). either accumulator has saturated. This is useful for 3.6.3.1 Round Logic complex number arithmetic, which typically uses both accumulators. The round logic is a combinational block that performs The device supports three Saturation and Overflow a conventional (biased) or convergent (unbiased) modes: round function during an accumulator write (store). The Round mode is determined by the state of the RND bit • Bit 39 Overflow and Saturation: in the CORCON register. It generates a 16-bit, When bit 39 overflow and saturation occurs, the 1.15data value that is passed to the data space write saturation logic loads the maximally positive saturation logic. If rounding is not indicated by the 9.31 (0x7FFFFFFFFF) or maximally negative instruction, a truncated 1.15 data value is stored and 9.31 value (0x8000000000) into the target accumu- the least significant word is simply discarded. lator. The SA or SB bit is set and remains set until cleared by the user application. This condition is Conventional rounding zero-extends bit 15 of the accu- referred to as ‘super saturation’ and provides mulator and adds it to the ACCxH word (bits 16 through protection against erroneous data or unexpected 31 of the accumulator). algorithm problems (such as gain calculations). • If the ACCxL word (bits0 through 15 of the • Bit 31 Overflow and Saturation: accumulator) is between 0x8000 and 0xFFFF When bit 31 overflow and saturation occurs, the (0x8000 included), ACCxH is incremented. saturation logic then loads the maximally positive • If ACCxL is between 0x0000 and 0x7FFF, ACCxH 1.31 value (0x007FFFFFFF) or maximally nega- is left unchanged. tive 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains A consequence of this algorithm is that over a set until cleared by the user application. When succession of random rounding operations, the value this Saturation mode is in effect, the guard bits are tends to be biased slightly positive. not used, so the OA, OB or OAB bits are never Convergent (or unbiased) rounding operates in the same set. manner as conventional rounding, except when ACCxL • Bit 39 Catastrophic Overflow: equals 0x8000. In this case, the Least Significant bit The bit 39 Overflow Status bit from the adder is (bit16 of the accumulator) of ACCxH is examined: used to set the SA or SB bit, which remains set until cleared by the user application. No saturation • If it is ‘1’, ACCxH is incremented. operation is performed, and the accumulator is • If it is ‘0’, ACCxH is not modified. allowed to overflow, destroying its sign. If the Assuming that bit 16 is effectively random in nature, COVTE bit in the INTCON1 register is set, a this scheme removes any rounding bias that may catastrophic overflow can initiate a trap exception. accumulate.  2008-2014 Microchip Technology Inc. DS70000318G-page 41

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 The SAC and SAC.R instructions store either a 3.6.4 BARREL SHIFTER truncated (SAC), or rounded (SAC.R) version of the The barrel shifter can perform up to 16-bit arithmetic or contents of the target accumulator to data memory via logic right shifts, or up to 16-bit left shifts in a single the X bus, subject to data saturation (see cycle. The source can be either of the two DSP Section3.6.3.2 “Data Space Write Saturation”). For accumulators or the X bus (to support multi-bit shifts of the MAC class of instructions, the accumulator write- register or memory data). back operation functions in the same manner, addressing combined MCU (X and Y) data space The shifter requires a signed binary value to determine though the X bus. For this class of instructions, the data both the magnitude (number of bits) and direction of the is always subject to rounding. shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ 3.6.3.2 Data Space Write Saturation does not modify the operand. In addition to adder/subtracter saturation, writes to data The barrel shifter is 40 bits wide, thereby obtaining a space can also be saturated, but without affecting the 40-bit result for DSP shift operations and a 16-bit result contents of the source accumulator. The data space write for MCU shift operations. Data from the X bus is saturation logic block accepts a 16-bit, 1.15 fractional presented to the barrel shifter between bit positions 16 value from the round logic block as its input, together with and 31 for right shifts, and between bit positions 0 and overflow status from the original source (accumulator) 16 for left shifts. and the 16-bit round adder. These inputs are combined and used to select the appropriate 1.15fractional value as output to write to data space memory. If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly: • For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. • For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. DS70000318G-page 42  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.0 MEMORY ORGANIZATION 4.1 Program Address Space Note: This data sheet summarizes the features The program address memory space of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 of the dsPIC33FJ06GS101/X02 and devices is 4M instructions. The space is addressable by a dsPIC33FJ16GSX02/X04 families of 24-bit value derived either from the 23-bit Program devices. It is not intended to be a compre- Counter (PC) during program execution, or from table hensive reference source. To complement operation or data space remapping, as described in the information in this data sheet, refer to Section4.6 “Interfacing Program and Data Memory “Program Memory” (DS70202) in the Spaces”. “dsPIC33F/PIC24H Family Reference Man- User application access to the program memory space ual”, which is available from the Microchip is restricted to the lower half of the address range web site (www.microchip.com). (0x000000 to 0x7FFFFF). The exception is the use of The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ TBLRD/TBLWT operations, which use TBLPAG<7> to X04 architecture features separate program and data permit access to the Configuration bits and Device ID memory spaces and buses. This architecture also allows sections of the configuration memory space. the direct access to program memory from the data The memory maps for the dsPIC33FJ06GS101/X02 and space during code execution. dsPIC33FJ16GSX02/X04 devices are shown in Figure4-1. FIGURE 4-1: PROGRAM MEMORY MAPS FOR dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 DEVICES dsPIC33FJ06GS101/102/202 dsPIC33FJ16GS402/404/502/504 GOTO Instruction 0x000000 GOTO Instruction 0x000000 0x000002 0x000002 Reset Address Reset Address 0x000004 0x000004 Interrupt Vector Table Interrupt Vector Table 0x0000FE 0x0000FE Reserved 0x000100 Reserved 0x000100 0x000104 0x000104 Alternate Vector Table Alternate Vector Table e 0x0001FE e 0x0001FE c c a 0x000200 a 0x000200 Sp User Program Sp User Program y Flash Memory y Flash Memory or (1792 instructions) or (5376 instructions) m 0x000FFE m 0x002BFE e e M 0x001000 M 0x002C00 er er s s U U Unimplemented Unimplemented (Read ‘0’s) (Read ‘0’s) 0x7FFFFE 0x7FFFFE 0x800000 0x800000 Reserved Reserved e e c c a a p p S 0xF7FFFE S 0xF7FFFE ory Device Configuration 0xF80000 ory Device Configuration 0xF80000 m Registers 0xF80017 m Registers 0xF80017 e e M 0xF80018 M 0xF80018 n n o o ati ati ur ur g Reserved g Reserved nfi nfi o o C C 0xFEFFFE 0xFEFFFE DEVID (2) 0xFF0000 DEVID (2) 0xFF0000 0xFF0002 0xFF0002 Reserved 0xFFFFFE Reserved 0xFFFFFE  2008-2014 Microchip Technology Inc. DS70000318G-page 43

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.1.1 PROGRAM MEMORY 4.1.2 INTERRUPT AND TRAP VECTORS ORGANIZATION All dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ The program memory space is organized in word- X04 devices reserve the addresses between 0x00000 addressable blocks. Although it is treated as 24 bits and 0x000200 for hard-coded program execution vectors. wide, it is more appropriate consider each address of A hardware Reset vector is provided to redirect code the program memory as a lower and upper word, with execution from the default value of the PC on device the upper byte of the upper word being unimplemented. Reset to the actual start of code. A GOTO instruction is The lower word always has an even address, while the programmed by the user application at 0x000000, with upper word has an odd address (see Figure4-2). the actual address for the start of code at 0x000002. Program memory addresses are always word-aligned The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ on the lower word, and addresses are incremented or X04 devices also have two interrupt vector tables, located decremented by two during the code execution. This from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. arrangement provides compatibility with data memory These vector tables allow each of the device interrupt space addressing and makes data in the program sources to be handled by separate Interrupt Service memory space accessible. Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section7.1 “Interrupt Vector Table”. FIGURE 4-2: PROGRAM MEMORY ORGANIZATION msw most significant word least significant word PC Address Address (lsw Address) 23 16 8 0 0x000001 00000000 0x000000 0x000003 00000000 0x000002 0x000005 00000000 0x000004 0x000007 00000000 0x000006 Program Memory Instruction Width ‘Phantom’ Byte (read as ‘0’) DS70000318G-page 44  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.2 Data Address Space All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ care must be taken when mixing byte and word X04 CPU has a separate, 16-bit-wide data memory operations, or translating from 8-bit MCU code. If a space. The data space is accessed using separate misaligned read or write is attempted, an address error Address Generation Units (AGUs) for read and write trap is generated. If the error occurred on a read, the operations. The data memory maps is shown in instruction underway is completed. If the error occurred Figure4-3. on a write, the instruction is executed but the write does All Effective Addresses (EAs) in the data memory space not occur. In either case, a trap is then executed, are 16 bits wide and point to bytes within the data space. allowing the system and/or user application to examine This arrangement gives a data space address range of the machine state prior to execution of the address 64Kbytes or 32K words. The lower half of the data Fault. memory space (that is, when EA<15> = 0) is used for All byte loads into any W register are loaded into the implemented memory addresses, while the upper half Least Significant Byte. The Most Significant Byte is not (EA<15> = 1) is reserved for the Program Space modified. Visibility area (see Section4.6.3 “Reading Data from A sign-extend (SE) instruction is provided to allow user Program Memory Using Program Space Visibility”). applications to translate 8-bit signed data to 16-bit dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ signed values. Alternatively, for 16-bit unsigned data, X04 devices implement up to 2 Kbytes of data memory. user applications can clear the MSB of any W register Should an EA point to a location outside of this area, an by executing a zero-extend (ZE) instruction on the all zero word or byte will be returned. appropriate address. 4.2.1 DATA SPACE WIDTH 4.2.3 SFR SPACE The data memory space is organized in byte The first 2 Kbytes of the Near Data Space, from 0x0000 addressable, 16-bit wide blocks. Data is aligned in data to 0x07FF, is primarily occupied by Special Function memory and registers as 16-bit words, but all data Registers (SFRs). These are used by the space EAs resolve to bytes. The Least Significant dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ Bytes (LSBs) of each word have even addresses, while X04 core and peripheral modules for controlling the the Most Significant Bytes (MSBs) have odd operation of the device. addresses. SFRs are distributed among the modules that they 4.2.2 DATA MEMORY ORGANIZATION control, and are generally grouped together by module. AND ALIGNMENT Much of the SFR space contains unused addresses; these are read as ‘0’. To maintain backward compatibility with PIC® MCU devices and improve data space memory usage Note: The actual set of peripheral features and efficiency, the dsPIC33FJ06GS101/X02 and interrupts varies by the device. Refer to dsPIC33FJ16GSX02/X04 instruction set supports both the corresponding device tables and word and byte operations. As a consequence of byte pinout diagrams for device-specific accessibility, all Effective Address calculations are information. internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified 4.2.4 NEAR DATA SPACE Register Indirect Addressing mode [Ws++] that results The 8-Kbyte area, between 0x0000 and 0x1FFF, is in a value of Ws + 1 for byte operations and Ws + 2 for referred to as the Near Data Space. Locations in this word operations. space are directly addressable via a 13-bit absolute Data byte reads will read the complete word that address field within all memory direct instructions. contains the byte, using the LSB of any EA to Additionally, the whole data space is addressable using determine which byte to select. The selected byte is MOV instructions, which support Memory Direct placed onto the LSB of the data path. That is, data Addressing mode with a 16-bit address field or by using memory and registers are organized as two parallel Indirect Addressing mode using a Working register as byte-wide entities with shared (word) address decode an Address Pointer. but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address.  2008-2014 Microchip Technology Inc. DS70000318G-page 45

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ06GS101/102 DEVICES WITH 256 BYTES OF RAM MSB LSB Address 16 Bits Address MSb LSb 0x0001 0x0000 2-Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 X Data RAM (X) 8-Kbyte 256 Bytes 0x087F 0x087E Near Data 0x0881 0x0880 SRAM Space Y Data RAM (Y) Space 0x08FF 0x08FE 0x0901 0x0900 0x1FFF 0x1FFE 0x2001 0x2000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE DS70000318G-page 46  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJ06GS202 DEVICE WITH 1-KBYTE RAM MSB LSB Address 16 Bits Address MSb LSb 0x0001 0x0000 2-Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 X Data RAM (X) 8-Kbyte 1-Kbyte 0x09FF 0x09FE Near Data SRAM Space 0x0A01 Y Data RAM (Y) 0x0A00 Space 0x0BFF 0x0BFE 0x0C01 0x0C00 0x1FFF 0x1FFE 0x2001 0x2000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE  2008-2014 Microchip Technology Inc. DS70000318G-page 47

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJ16GS402/404/502/504 DEVICES WITH 2-KBYTE RAM MSB LSB Address 16 Bits Address MSb LSb 0x0001 0x0000 2-Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 X Data RAM (X) 8-Kbyte 2-Kbyte 0x0BFF 0x0BFE Near Data 0x0C01 0x0C00 SRAM Space Space Y Data RAM (Y) 0x0FFF 0x0FFE 0x1001 0x1000 0x1FFF 0x1FFE 0x2001 0x2000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE DS70000318G-page 48  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.2.5 X AND Y DATA SPACES The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, The core has two data spaces, X and Y. These data EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide spaces can beconsidered either separate (for some two concurrent data read paths. DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are Both the X and Y data spaces support Modulo accessed using two Address Generation Units (AGUs) Addressing mode for all instructions, subject to and separate data paths. This feature allows certain addressing mode restrictions. Bit-Reversed Addressing instructions to concurrently fetch two words from RAM, mode is only supported for writes to X data space. thereby enabling efficient execution of DSP algorithms, All data memory writes, including in DSP instructions, such as Finite Impulse Response (FIR) filtering and view data space as combined X and Y address space. Fast Fourier Transform (FFT). The boundary between the X and Y data spaces is The X data space is used by all instructions and device-dependent and is not user-programmable. supports all addressing modes. X data space has All Effective Addresses are 16 bits wide and point to separate read and write data buses. The X read data bytes within the data space. Therefore, the data space bus is the read data path for all instructions that view address range is 64 Kbytes, or 32K words, though the data space as combined X and Y address space. It is implemented memory locations vary by device. also the X data prefetch path for the dual operand DSP instructions (MAC class).  2008-2014 Microchip Technology Inc. DS70000318G-page 49

D TABLE 4-1: CPU CORE REGISTER MAP d S 7 s 000 File Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts P 0 3 I 18 WREG0 0000 Working Register 0 0000 C G -p WREG1 0002 Working Register 1 0000 3 ag WREG2 0004 Working Register 2 0000 3 e 5 WREG3 0006 Working Register 3 0000 F 0 J WREG4 0008 Working Register 4 0000 0 WREG5 000A Working Register 5 0000 6 WREG6 000C Working Register 6 0000 G WREG7 000E Working Register 7 0000 S WREG8 0010 Working Register 8 0000 1 WREG9 0012 Working Register 9 0000 0 WREG10 0014 Working Register 10 0000 1 WREG11 0016 Working Register 11 0000 / X WREG12 0018 Working Register 12 0000 0 WREG13 001A Working Register 13 0000 2 WREG14 001C Working Register 14 0000 WREG15 001E Working Register 15 0800 a SPLIM 0020 Stack Pointer Limit Register xxxx n d ACCAL 0022 ACCAL xxxx ACCAH 0024 ACCAH xxxx d ACCAU 0026 ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCAU xxxx s ACCBL 0028 ACCBL xxxx P ACCBH 002A ACCBH xxxx I C ACCBU 002C ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCBU xxxx 3 PCL 002E Program Counter Low Word Register 0000 3 PCH 0030 — — — — — — — — Program Counter High Byte Register 0000 F  TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register 0000 J 20 PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register 0000 1 0 8 RCOUNT 0036 REPEAT Loop Counter Register xxxx 6 -2 0 DCOUNT 0038 DCOUNT<15:0> xxxx G 1 4 M DOSTARTL 003A DOSTARTL<15:1> 0 xxxx S icro DOSTARTH 003C — — — — — — — — — — DOSTARTH<5:0> 00xx X ch DOENDL 003E DOENDL<15:1> 0 xxxx 0 ip T DOENDH 0040 — — — — — — — — — — DOENDH 00xx 2 e SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 / chn CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0020 X o 0 lo MODCON 0046 XMODEN YMODEN — — BWM3 BWM2 BWM1 BWM0 YWM3 YWM2 YWM1 YWM0 XWM3 XWM2 XWM1 XWM0 0000 g 4 y In Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-1: CPU CORE REGISTER MAP (CONTINUED) 2 008-2 File Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 01 XMODSRT 0048 XS<15:1> 0 xxxx P 4 M XMODEND 004A XE<15:1> 1 xxxx IC icro YMODSRT 004C YS<15:1> 0 xxxx 3 chip YMODEND 004E YE<15:1> 1 xxxx 3 T XBREV 0050 BREN XB14 XB13 XB12 XB11 XB10 XB9 XB8 XB7 XB6 XB5 XB4 XB3 XB2 XB1 XB0 xxxx F e ch DISICNT 0052 — — Disable Interrupts Counter Register xxxx J no Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 log 6 y In TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ06GS101 G c . S File SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 1 Name Addr Resets 0 CNEN1 0060 — — — — — — — — CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 1 CNPU1 0068 — — — — — — — — CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 /X Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 2 TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402 AND a dsPIC33FJ16GS502 n File SFR All d Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets d CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 s CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 P Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. I C 3 TABLE 4-4: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ16GS404 AND dsPIC33FJ16GS504 3 File SFR All F Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets J 1 CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 6 CNEN2 0062 — — CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 G D CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 S S 7 CNPU2 006A — — CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 0 X 00 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 0 3 1 2 8 G / -p X a g 0 e 5 4 1

D TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS101 DEVICES ONLY d S 7 s 0 000 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts P 3 I 1 C 8 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — 0000 G -p INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 3 a 3 ge 52 IIFFSS01 00008846 —— —— INATD2IFIF U1—TXIF U1—RXIF SP—I1IF SP—I1EIF —— T—2IF —— —— INT—1IF CTN1IIFF OC—1IF MI2—C1IF SINI2TC01IFIF 00000000 FJ IFS3 008A — — — — — — PSEMIF — — — — — — — — — 0000 0 IFS4 008C — — — — — — — — — — — — — — U1EIF — 0000 6 IFS5 008E — PWM1IF — — — — — — — — — — — — — — 0000 G IFS6 0090 ADCP1IF ADCP0IF — — — — — — — — — — — — PWM4IF — 0000 S IFS7 0092 — — — — — — — — — — — — — — ADCP3IF — 0000 1 IEC0 0094 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE — T2IE — — — T1IE OC1IE — INT0IE 0000 0 1 IEC1 0096 — — INT2IE — — — — — — — — INT1IE CNIE — MI2C1IE SI2C1IE 0000 / IEC2 0098 — — — — — — — — — — — — — — — — 0000 X IEC3 009A — — — — — — PSEMIE — — — — — — — — — 0000 0 2 IEC4 009C — — — — — — — — — — — — — — U1EIE — 0000 IEC5 009E — PWM1IE — — — — — — — — — — — — — — 0000 a IEC6 00A0 ADCP1IE ADCP0IE — — — — — — — — — — — — PWM4IE — 0000 n d IEC7 00A2 — — — — — — — — — — — — — — ADCP3IE — 0000 IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — — — — — INT0IP2 INT0IP1 INT0IP2 4404 d IPC1 00A6 — T2IP2 T2IP1 T2IP0 — — — — — — — — — — — — 4000 s IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — — — — 4440 P IPC3 00AA — — — — — — — — -— ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044 IC IPC4 00AC — CNIP2 CNIP1 CNIP0 — — — — — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4044 3 IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP21 INT1IP0 0004 3 IPC7 00B2 — — — — — — — — — INT2IP2 INT2IP1 INT2IP0 — — — — 0040 F  2 IPC14 00C0 — — — — — — — — — PSEMIP2 PSEMIP1 PSEMIP0 — — — — 0040 J 0 1 0 IPC16 00C4 — — — — — — — — — U1EIP2 U1EIP1 U1EIP0 — — — — 0400 8 6 -2 IPC23 00D2 — — — — — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — — 0040 0 G 14 IPC24 00D4 — — — — — — — — — PWM4IP2 PWM4IP1 PWM4IP0 — — — — 4400 M S IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — — 0040 icro IPC28 00DC — — — — — — — — — ADCP3IP2 ADCP3IP1 ADCP3IP0 — — — — 0000 X ch 0 ip Te ILNeTgTeRndE:G 00Ex0 = unkn—own value o—n Reset, —— = unimplem—ented, readI LaRs 3‘0’. ReseItL vRa2lues are sILhRo1wn in hexILaRde0cimal. — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 2/ ch X n o 0 lo g 4 y In c .

 TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS102 DEVICES ONLY 2 0 d 08-2 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts s 01 P 4 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — 0000 M I ic INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 C roc IFS0 0084 — — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF — T2IF — — — T1IF OC1IF — INT0IF 0000 3 hip IFS1 0086 — — INT2IF — — — — — — — — INT1IF CNIF — MI2C1IF SI2C1IF 0000 3 T F e IFS3 008A — — — — — — PSEMIF — — — — — — — — — 0000 ch J no IFS4 008C — — — — — — — — — — — — — — U1EIF — 0000 0 log IFS5 008E PWM2IF PWM1IF — — — — — — — — — — — — — — 0000 6 y In IFS6 0090 ADCP1IF ADCP0IF — — — — — — — — — — — — — — 0000 G c. IFS7 0092 — — — — — — — — — — — — — — — ADCP2IF 0000 S IEC0 0094 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE — T2IE — — — T1IE OC1IE — INT0IE 0000 1 IEC1 0096 — — INT2IE — — — — — — — — INT1IE CNIE — MI2C1IE SI2C1IE 0000 0 IEC3 009A — — — — — — PSEMIE — — — — — — — — — 0000 1 / IEC4 009C — — — — — — — — — — — — — — U1EIE — 0000 X IEC5 009E PWM2IE PWM1IE — — — — — — — — — — — — — — 0000 0 IEC6 00A0 ADCP1IE ADCP0IE — — — — — — — — — — — — — — 0000 2 IEC7 00A2 — — — — — — — — — — — — — — — ADCP2IE 0000 a IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — — — — — INT0IP2 INT0IP1 INT0IP0 4404 n IPC1 00A6 — T2IP2 T2IP1 T2IP0 — — — — — — — — — — — — 4000 d IPC2 00A8 — U1RXIP2 U1RXIP2 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — — — — 4440 d IPC3 00AA — — — — — — — — -— ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044 s IPC4 00AC — CNIP2 CNIP1 CNIP0 — — — — — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4044 P IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 I C IPC7 00B2 — — — — — — — — — INT2IP2 INT2IP1 INT2IP0 — — — — 0040 3 IPC14 00C0 — — — — — — — — — PSEMIP2 PSEMIP1 PSEMIP0 — — — — 0040 3 IPC16 00C4 — — — — — — — — — U1EIP2 U1EIP1 U1EIP0 — — — — 0040 F IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — — 4400 J IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — — 4400 1 6 IPC28 00DC — — — — — — — — — — — — — ADCP2IP2 ADCP2IP1 ADCP2IP0 0004 G INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 D S Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. S 7 0 X 0 0 0 0 3 1 2 8 G / -p X a g 0 e 5 4 3

D TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06G202 DEVICES ONLY d S 7 s 0 000 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts P 3 I 1 C 8 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — 0000 G -p INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 3 a 3 ge 54 IIFFSS01 00008846 —— —— INATD2IFIF U1—TXIF U1—RXIF SP—I1IF SPI—1EIF —— T—2IF —— —— INT—1IF CTN1IIFF OACC11IIFF MIIC2C1I1FIF SINI2TC01IFIF 00000000 FJ IFS3 008A — — — — — — PSEMIF — — — — — — — — — 0000 0 IFS4 008C — — — — — — — — — — — — — — U1EIF — 0000 6 IFS5 008E PWM2IF PWM1IF — — — — — — — — — — — — — — 0000 G IFS6 0090 ADCP1IF ADCP0IF — — — — — — AC2IF — — — — — — — 0000 S IFS7 0092 — — — — — — — — — — — ADCP6IF — — — ADCP2IF 0000 1 IEC0 0094 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE — T2IE — — — T1IE OC1IE IC1IE INT0IE 0000 0 1 IEC1 0096 — — INT2IE — — — — — — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE 0000 / IEC3 009A — — — — — — PSEMIE — — — — — — — — — 0000 X IEC4 009C — — — — — — — — — — — — — — U1EIE — 0000 0 2 IEC5 009E PWM2IE PWM1IE — — — — — — — — — — — — — — 0000 IEC6 00A0 ADCP1IE ADCP0IE — — — — — — AC2IE — — — — — — — 0000 a IEC7 00A2 — — — — — — — — — — — ADCP6IE — — — ADCP2IE 0000 n d IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444 IPC1 00A6 — T2IP2 T2IP1 T2IP0 — — — — — — — — — — — — 4000 d IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — — — — 4440 s IPC3 00AA — — — — — — — — -— ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044 P IPC4 00AC — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444 IC IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 3 IPC7 00B2 — — — — — — — — — INT2IP2 INT2IP1 INT2IP0 — — — — 0040 3 IPC14 00C0 — — — — — — — — — PSEMIP2 PSEMIP1 PSEMIP0 — — — — 0040 F  2 IPC16 00C4 — — — — — — — — — U1EIP2 U1EIP1 U1EIP0 — — — — 0040 J 0 1 0 IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — — 4400 8 6 -2 IPC25 00D6 — AC2IP2 AC2IP1 AC2IP0 — — — — — — — — — — — — 4000 0 G 14 IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — — 4400 M S IPC28 00DC — — — — — — — — — — — — — ADCP2IP2 ADCP2IP1 ADCP2IP0 0004 icro IPC29 00DE — — — — — — — — — — — — — ADCP6IP2 ADCP6IP1 ADCP6IP0 0004 X ch 0 ip Te ILNeTgTeRndE:G 00Ex 0= unkn—own value o—n Reset, — —= unimpleme—nted, read aILsR ‘03’. Reset IvLaRlu2es are sIhLoRw1n in hexIaLdRe0cimal. — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 2/ ch X n o 0 lo g 4 y In c .

 TABLE 4-8: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS402/404 DEVICES ONLY 2 0 d 08-2 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts s 01 P 4 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — 0000 M I ic INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 C roc IFS0 0084 — — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 3 hip IFS1 0086 — — INT2IF — — — — — — — — INT1IF CNIF — MI2C1IF SI2C1IF 0000 3 T F e IFS3 008A — — — — — — PSEMIF — — — — — — — — — 0000 ch J no IFS4 008C — — — — — — — — — — — — — — U1EIF — 0000 0 log IFS5 008E PWM2IF PWM1IF — — — — — — — — — — — — — — 0000 6 y In IFS6 0090 ADCP1IF ADCP0IF — — — — — — — — — — — — — PWM3IF 0000 G c. IFS7 0092 — — — — — — — — — — — — — — ADCP3IF ADCP2IF 0000 S IEC0 0094 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000 1 IEC1 0096 — — INT2IE — — — — — — — — INT1IE CNIE — MI2C1IE SI2C1IE 0000 0 IEC3 009A — — — — — — PSEMIE — — — — — — — — — 0000 1 / IEC4 009C — — — — — — — — — — — — — — U1EIE — 0000 X IEC5 009E PWM2IE PWM1IE — — — — — — — — — — — — — — 0000 0 IEC6 00A0 ADCP1IE ADCP0IE — — — — — — — — — — — — — PWM3IE 0000 2 IEC7 00A2 — — — — — — — — — — — — — — ADCP3IE ADCP2IE 0000 a IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP2 4444 n IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4440 d IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 4444 d IPC3 00AA — — — — — — — — -— ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044 s IPC4 00AC — CNIP2 CNIP1 CNIP0 — — — — — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4044 P IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 I C IPC7 00B2 — — — — — — — — — INT2IP2 INT2IP1 INT2IP0 — — — — 0040 3 IPC14 00C0 — — — — — — — — — PSEMIP2 PSEMIP1 PSEMIP0 — — — — 0040 3 IPC16 00C4 — — — — — — — — — U1EIP2 U1EIP1 U1EIP0 — — — — 0040 F IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 -— — — — — — 4400 J IPC24 00D4 — — — — — — — — — — — — — PWM3IP2 PWM3IP1 PWM3IP0 0004 1 6 IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 -— — — — — — 4400 G IPC28 00DC — — — — — — — — — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1 ADCP2IP0 0044 D S INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 S 7 0 X 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 0 0 3 1 2 8 G / -p X a g 0 e 5 4 5

D TABLE 4-9: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS502 DEVICES ONLY d S 7 s 000 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts P 0 3 I 18 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERRCOVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERRADDRERR STKERR OSCFAIL — 0000 C G -p INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 3 a 3 g IFS0 0084 — — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 e 5 IFS1 0086 — — INT2IF — — — — — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000 F 6 J IFS3 008A — — — — — — PSEMIF — — — — — — — — — 0000 0 IFS4 008C — — — — — — — — — — — — — — U1EIF — 0000 6 IFS5 008E PWM2IF PWM1IF — — — — — — — — — — — — — — 0000 G IFS6 0090 ADCP1IF ADCP0IF — — — — AC4IF AC3IF AC2IF — — — — — PWM4IF PWM3IF 0000 S IFS7 0092 — — — — — — — — — — — ADCP6IF — — ADCP3IF ADCP2IF 0000 1 IEC0 0094 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000 0 IEC1 0096 — — INT2IE — — — — — — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE 0000 1 / IEC3 009A — — — — — — PSEMIE — — — — — — — — — 0000 X IEC4 009C — — — — — — — — — — — — — — U1EIE — 0000 0 IEC5 009E PWM2IE PWM1IE — — — — — — — — — — — — — — 0000 2 IEC6 00A0 ADCP1IE ADCP0IE — — — — AC4IE AC3IE AC2IE — — — — — PWM4IE PWM3IE 0000 a IEC7 00A2 — — — — — — — — — — — ADCP6IE — — ADCP3IE ADCP2IE 0000 n IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP2 4444 d IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 -— — — — 4440 d IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 4444 s IPC3 00AA — — — — -— — — — -— ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044 P IPC4 00AC — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444 I C IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 3 IPC7 00B2 — — — — — — — — — INT2IP2 INT2IP1 INT2IP0 — — — — 0040 3 IPC14 00C0 — — — — — — — — — PSEMIP2 PSEMIP1 PSEMIP0 — — — — 0040 F  IPC16 00C4 — — — — — — — — — U1EIP2 U1EIP1 U1EIP0 — — — — 0040 J 2 00 IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — — 4400 1 8 6 -2 IPC24 00D4 — — — — — — — — — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0 0044 0 G 1 IPC25 00D6 — AC2IP2 AC2IP1 AC2IP0 — — — — — — — — — — — — 4000 4 M IPC26 00D8 — — — — — — — — — AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0 0044 S icro IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 -— — — — — — — — 4400 X chip T IIPPCC2289 0000DDCE —— —— —— —— —— —— —— —— —— ADC—P3IP2 ADC—P3IP1 ADC—P3IP0 —— AADDCCPP26IIPP22 AADDCCPP26IIPP11 AADDCCPP26IIPP00 00004044 02 e / ch INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 X n olo Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 g 4 y In c .

 TABLE 4-10: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS504 DEVICES ONLY 2 00 File SFR All d 8-2 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets s 014 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — 0000 P M INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 IC ic ro IFS0 0084 — — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 3 c hip IFS1 0086 — — INT2IF — — — — — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000 3 Te IFS3 008A — — — — — — PSEMIF — — — — — — — — — 0000 F chno IFS4 008C — — — — — — — — — — — — — — U1EIF — 0000 J0 log IFS5 008E PWM2IF PWM1IF — — — — — — — — — — — — — — 0000 6 y In IFS6 0090 ADCP1IF ADCP0IF — — — — AC4IF AC3IF AC2IF — — — — — PWM4IF PWM3IF 0000 G c IFS7 0092 — — — — — — — — — — — ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF 0000 . S IEC0 0094 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000 1 IEC1 0096 — — INT2IE — — — — — — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE 0000 0 IEC3 009A — — — — — — PSEMIE — — — — — — — — — 0000 1 IEC4 009C — — — — — — — — — — — — — — U1EIE — 0000 /X IEC5 009E PWM2IE PWM1IE — — — — — — — — — — — — — — 0000 0 IEC6 00A0 ADCP1IE ADCP0IE — — — — AC4IE AC3IE AC2IE — — — — — PWM4IE PWM3IE 0000 2 IEC7 00A2 — — — — — — — — — — — ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE 0000 a IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP2 4444 n IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4440 d IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 4444 d IPC3 00AA — — — — — — — — -— ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044 s IPC4 00AC — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444 P IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 I C IPC7 00B2 — — — — — — — — — INT2IP2 INT2IP1 INT2IP0 — — — — 0040 3 IPC14 00C0 — — — — — — — — — PSEMIP2 PSEMIP1 PSEMIP0 — — — — 0040 3 IPC16 00C4 — — — — — — — — — U1EIP2 U1EIP1 U1EIP0 — — — — 0040 F IPC23 00D2 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — — 4400 J IPC24 00D4 — — — — — — — — — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0 0044 1 IPC25 00D6 — AC2IP2 AC2IP1 AC2IP0 — — — — — — — — — — — — 4000 6 IPC26 00D8 — — — — — — — — — AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0 0440 G D S IPC27 00DA — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 — — — — — — — — 4400 S 7 00 IPC28 00DC — ADCP5IP2 ADCP5IP1 ADCP5IP0 — ADCP4IP2 ADCP4IP1 ADCP4IP0 — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1 ADCP2IP0 4444 X 0 0 IPC29 00DE — — — — — — — — — — — — — ADCP6IP2 ADCP6IP1 ADCP6IP0 0004 0 3 18 INTTREG 00E0 — — — — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 2 G / -p Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X a g 0 e 5 4 7

D TABLE 4-11: TIMER REGISTER MAP FOR dsPIC33FJ06GS101 AND dsPIC33FJ06GSX02 d S 7 s 0 File SFR All 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P 0 Name Addr Resets 0 3 I 18 TMR1 0100 Timer1 Register 0000 C G -p PR1 0102 Period Register 1 FFFF 3 ag T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 3 e 5 TMR2 0106 Timer2 Register 0000 F 8 J PR2 010C Period Register 2 FFFF 0 T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G S TABLE 4-12: TIMER REGISTER MAP FOR dsPIC33FJ16GSX02 AND dsPIC33FJ16GSX04 1 0 File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 Name Addr Resets / X TMR1 0100 Timer1 Register 0000 0 PR1 0102 Period Register 1 FFFF 2 T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 a TMR2 0106 Timer2 Register 0000 n TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx d TMR3 010A Timer3 Register 0000 PR2 010C Period Register 2 FFFF d s PR3 010E Period Register 3 FFFF P T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 I T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 C Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 3 F  TABLE 4-13: INPUT CAPTURE REGISTER MAP FOR dsPIC33FJ06GS202 J 2 0 1 08 File SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 6 -2 Name Addr Resets 0 G 1 4 IC1BUF 0140 Input Capture 1 Register xxxx M S icroch ILCe1gCeOndN: x0 =14 u2nknown —value on R—eset, — =IC uSnIiDmLplemente—d, read as ‘0—’. Reset valu—es are sho—wn in hex—adecimaICl.TMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 X0 ip T 2 e / ch X n o 0 lo g 4 y In c .

 TABLE 4-14: INPUT CAPTURE REGISTER MAP FOR dsPIC33FJ16GSX02 AND dsPIC33FJ16GSX04 2 008-2 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 014 IC1BUF 0140 Input Capture 1 Register xxxx P M IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 IC ic ro IC2BUF 0144 Input Capture 2 Register xxxx 3 c hip IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 3 Te Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. F ch J no 0 log TABLE 4-15: OUTPUT COMPARE REGISTER MAP FOR dsPIC33FJ06GS101 AND dsPIC33FJ06GSX02 6 y Inc. NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts GS OC1RS 0180 Output Compare 1 Secondary Register xxxx 1 OC1R 0182 Output Compare 1 Register xxxx 0 1 OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 / Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X 0 TABLE 4-16: OUTPUT COMPARE REGISTER MAP FOR dsPIC33FJ16GSX02 AND dsPIC33FJ06GSX04 2 a File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n Name Addr Resets d OC1RS 0180 Output Compare 1 Secondary Register xxxx d OC1R 0182 Output Compare 1 Register xxxx s OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 P OC2RS 0186 Output Compare 2 Secondary Register xxxx I OC2R 0188 Output Compare 2 Register xxxxx C OC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 F J TABLE 4-17: HIGH-SPEED PWM REGISTER MAP 1 6 File SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All G Name Addr Resets D S S 7 PTCON 0400 PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN — SYNCSRC1 SYNCSRC0 SEVTPS3 SEVTPS2 SEVTPS1 SEVTPS0 0000 0 X 00 PTCON2 0402 — — — — — — — — — — — — — PCLKDIV2 PCLKDIV1 PCLKDIV0 0000 0 0 31 PTPER 0404 PTPER<15:0> FFF8 2 8 G SEVTCMP 0406 SEVTCMP<15:3> — — — 0000 / -pa MDC 040A MDC<15:0> 0000 X g 0 e 5 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 9

D d S TABLE 4-18: HIGH-SPEED PWM GENERATOR 1 REGISTER MAP 7 s 0 0 P 0 File SFR All 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3 Name Addr Resets I 1 C 8 G-p PWMCON1 0420 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 — — — CAM XPRES IUE 0000 3 a IOCON1 0422 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000 3 g e 6 FCLCON1 0424 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000 F 0 PDC1 0426 PDC1<15:0> 0000 J 0 PHASE1 0428 PHASE1<15:0> 0000 6 DTR1 042A — — DTR1<13:0> 0000 G ALTDTR1 042C — — ALTDTR1<13:0> 0000 S SDC1 042E SDC1<15:0> 0000 1 SPHASE1 0430 SPHASE1<15:0> 0000 0 TRIG1 0432 TRGCMP<15:3> — — — 0000 1 TRGCON1 0434 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000 / X STRIG1 0436 STRGCMP<15:3> — — — 0000 0 PWMCAP1 0438 PWMCAP1<15:3> — — — 0000 2 LEBCON1 043A PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB6 LEB5 LEB4 LEB3 LEB2 LEB1 LEB0 — — — 0000 a Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. n d TABLE 4-19: HIGH-SPEED PWM GENERATOR 2 REGISTER MAP FOR dsPIC33FJ06GS102/202 AND dsPIC33FJ16GSX02/X04 DEVICES ONLY d s File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P Name Addr Resets I PWMCON2 0440 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 — — — CAM XPRES IUE 0000 C IOCON2 0442 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000 3 FCLCON2 0444 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000 3 F PDC2 0446 PDC2<15:0> 0000  J 2 PHASE2 0448 PHASE2<15:0> 0000 0 1 08 DTR2 044A — — DTR2<13:0> 0000 6 -2 0 ALTDTR2 044C — — ALTDTR2<13:0> 0000 G 1 4 M SDC2 044E SDC2<15:0> 0000 S icro SPHASE2 0450 SPHASE2<15:0> 0000 X ch TRIG2 0452 TRGCMP<15:3> — — — 0000 0 ip T TRGCON2 0454 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000 2 ech STRIG2 0456 STRGCMP<15:3> — — — 0000 /X no PWMCAP2 0458 PWMCAP2<15:3> — — — 0000 0 log LEBCON2 045A PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB6 LEB5 LEB4 LEB3 LEB2 LEB1 LEB0 — — — 0000 4 y In Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-20: HIGH-SPEED PWM GENERATOR 3 REGISTER MAP FOR dsPIC33FJ16GSX02/X04 DEVICES ONLY 2 0 d 08-2 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts s 01 P 4 PWMCON3 0460 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 — — — CAM XPRES IUE 0000 M I ic IOCON3 0462 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000 C roc FCLCON3 0464 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000 3 hip PDC3 0466 PDC3<15:0> 0000 3 T F e PHASE3 0468 PHASE3<15:0> 0000 ch J no DTR3 046C — — DTR3<13:0> 0000 0 log ALTDTR3 046C — — ALTDTR3<13:0> 0000 6 y In SDC3 046E SDC3<15:0> 0000 G c. SPHASE3 0470 SPHASE3<15:0> 0000 S TRIG3 0472 TRGCMP<15:3> — — — 0000 1 TRGCON3 0474 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000 0 STRIG3 0476 STRGCMP<15:3> — — — 0000 1 / PWMCAP3 0478 PWMCAP3<15:3> — — — 0000 X LEBCON3 047A PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB6 LEB5 LEB4 LEB3 LEB2 LEB1 LEB0 — — — 0000 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 a TABLE 4-21: HIGH-SPEED PWM GENERATOR 4 REGISTER MAP FOR dsPIC33FJ06GS101 AND dsPIC33FJ16GS50X DEVICES ONLY n d File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets d s PWMCON4 0480 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 — — — CAM XPRES IUE 0000 P IOCON4 0482 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC 0000 I FCLCON4 0484 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 0000 C PDC4 0486 PDC4<15:0> 0000 3 PHASE4 0488 PHASE4<15:0> 0000 3 F DTR4 048A — — DTR4<13:0> 0000 J ALTDTR4 048A — — ALTDTR4<13:0> 0000 1 SDC4 048E SDC4<15:0> 0000 6 SPHASE4 0490 SPHASE4<15:0> 0000 G D TRIG4 0492 TRGCMP<15:3> — — — 0000 S S 70 TRGCON4 0494 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000 X 0 0 STRIG4 0496 STRGCMP<15:3> — — — 0000 0 0 31 PWMCAP4 0498 PWMCAP4<15:3> — — — 0000 2 8 G LEBCON4 049A PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB6 LEB5 LEB4 LEB3 LEB2 LEB1 LEB0 — — — 0000 / -p X a Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. g 0 e 6 4 1

D TABLE 4-22: I2C1 REGISTER MAP d S 7 s 0 000 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts P 3 I 1 C 8 I2C1RCV 0200 — — — — — — — — I2C1 Receive Register 0000 G -p I2C1TRN 0202 — — — — — — — — I2C1 Transmit Register 00FF 3 a 3 ge 62 II22CC11BCROGN 00220046 I2C—EN —— I2C—SIDL SCL—REL IPM—IEN A1—0M DIS—SLW SMEN GCEN STREN BAaCuKdD RTate GAeCnKeEraNtor ReRgCisEteNr PEN RSEN SEN 01000000 FJ I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 0 I2C1ADD 020A — — — — — — I2C1 Address Register 0000 6 I2C1MSK 020C — — — — — — AMSK<9:0> 0000 G Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. S 1 TABLE 4-23: UART1 REGISTER MAP 0 1 File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 / Name Addr Resets X U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000 0 2 U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 U1TXREG 0224 — — — — — — — UART1 Transmit Register xxxx a n U1RXREG 0226 — — — — — — — UART1 Receive Register 0000 d U1BRG 0228 Baud Rate Generator Prescaler 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d s TABLE 4-24: SPI1 REGISTER MAP P I File SFR All C Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets 3 SPI1STAT 0240 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 3 SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 F  J 2 SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY — 0000 0 1 08 SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000 6 -20 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G 1 4 M S icro X ch 0 ip T 2 e / ch X n o 0 lo g 4 y In c .

 TABLE 4-25: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS101 DEVICES ONLY 2 008-2 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 014 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0 0003 P M ADPCFG 0302 — — — — — — — — PCFG7 PCFG6 — — PCFG3 PCFG2 PCFG1 PCFG0 0000 IC ic ro ADSTAT 0306 — — — — — — — — — — — — P3RDY — P1RDY P0RDY 0000 3 c hip ADBASE 0308 ADBASE<15:1> — 0000 3 Te ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00 0000 F ch ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 — — — — — — — — 0000 J no 0 log ADCBUF0 0320 ADC Data Buffer 0 xxxx 6 y In ADCBUF1 0322 ADC Data Buffer 1 xxxx G c ADCBUF2 0324 ADC Data Buffer 2 xxxx . S ADCBUF3 0326 ADC Data Buffer 3 xxxx 1 ADCBUF6 032C ADC Data Buffer 6 xxxx 0 ADCBUF7 032E ADC Data Buffer 7 xxxx 1 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / X 0 TABLE 4-26: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS102 DEVICES ONLY 2 File SFR All a Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets n d ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0 0003 ADPCFG 0302 — — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 d ADSTAT 0306 — — — — — — — — — — — — — P2RDY P1RDY P0RDY 0000 s P ADBASE 0308 ADBASE<15:1> — 0000 I ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00 0000 C ADCPC1 030C — — — — — — — — IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20 0000 3 ADCBUF0 0320 ADC Data Buffer 0 xxxx 3 ADCBUF1 0322 ADC Data Buffer 1 xxxx F ADCBUF2 0324 ADC Data Buffer 2 xxxx J 1 ADCBUF3 0326 ADC Data Buffer 3 xxxx 6 ADCBUF4 0328 ADC Data Buffer 4 xxxx G D ADCBUF5 032A ADC Data Buffer 5 xxxx S S 7 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 X 0 0 0 0 3 1 2 8 G / -p X a g 0 e 6 4 3

D TABLE 4-27: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY d S 7 s 000 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts P 0 3 I 18 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0 0003 C G -p ADPCFG 0302 — — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 3 a 3 g ADSTAT 0306 — — — — — — — — — P6RDY — — — P2RDY P1RDY P0RDY 0000 e 6 ADBASE 0308 ADBASE<15:1> — 0000 F 4 J ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00 0000 0 ADCPC1 030C — — — — — — — — IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20 0000 6 ADCPC3 0310 — — — — — — — — IRQEN6 PEND6 SWTRG6 TRGSRC64 TRGSRC63 TRGSRC62 TRGSRC61 TRGSRC60 0000 G ADCBUF0 0320 ADC Data Buffer 0 xxxx S ADCBUF1 0322 ADC Data Buffer 1 xxxx 1 ADCBUF2 0324 ADC Data Buffer 2 xxxx 0 ADCBUF3 0326 ADC Data Buffer 3 xxxx 1 / ADCBUF4 0328 ADC Data Buffer 4 xxxx X ADCBUF5 032A ADC Data Buffer 5 xxxx 0 ADCBUF12 0338 ADC Data Buffer 12 xxxx 2 ADCBUF13 033A ADC Data Buffer13 xxxx a Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. n d TABLE 4-28: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS402/404 DEVICES ONLY d File SFR All s Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets P ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0 0003 IC ADPCFG 0302 — — — — — — — — PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 3 ADSTAT 0306 — — — — — — — — — — — — P3RDY P2RDY P1RDY P0RDY 0000 3 ADBASE 0308 ADBASE<15:1> — 0000 F  2 ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00 0000 J 0 1 0 ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20 0000 8 6 -2 ADCBUF0 0320 ADC Data Buffer 0 xxxx 0 G 14 ADCBUF1 0322 ADC Data Buffer 1 xxxx M S icro AADDCCBBUUFF23 00332246 AADDCC DDaattaa BBuuffffeerr 23 xxxxxxxx X ch 0 ip T ADCBUF4 0328 ADC Data Buffer 4 xxxx 2 e ADCBUF5 032A ADC Data Buffer 5 xxxx / chn ADCBUF6 032C ADC Data Buffer 6 xxxx X o 0 lo ADCBUF7 032E ADC Data Buffer 7 xxxx g 4 y In Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

 TABLE 4-29: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS502 DEVICES ONLY 2 0 d 0 File SFR All 8-2 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets s 01 P 4 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0 0003 M I ic ADPCFG 0302 — — — — — — — — PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 C roc ADSTAT 0306 — — — — — — — — — P6RDY — — P3RDY P2RDY P1RDY P0RDY 0000 3 hip ADBASE 0308 ADBASE<15:1> — 0000 3 T F e ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00 0000 chno ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20 0000 J0 log ADCPC3 0310 — — — — — — — — IRQEN6 PEND6 SWTRG6 TRGSRC64 TRGSRC63 TRGSRC62 TRGSRC61 TRGSRC60 0000 6 y In ADCBUF0 0320 ADC Data Buffer 0 xxxx G c. ADCBUF1 0322 ADC Data Buffer 1 xxxx S ADCBUF2 0324 ADC Data Buffer 2 xxxx 1 ADCBUF3 0326 ADC Data Buffer 3 xxxx 0 ADCBUF4 0328 ADC Data Buffer 4 xxxx 1 / ADCBUF5 032A ADC Data Buffer 5 xxxx X ADCBUF6 032C ADC Data Buffer 6 xxxx 0 ADCBUF7 032E ADC Data Buffer 7 xxxx 2 ADCBUF12 0338 ADC Data Buffer 12 xxxx a ADCBUF13 033A ADC Data Buffer 13 xxxx n Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. d d s P I C 3 3 F J 1 6 G D S S 7 0 X 0 0 0 0 3 1 2 8 G / -p X a g 0 e 6 4 5

D TABLE 4-30: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS504 DEVICES ONLY d S 7 s 000 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts P 0 3 I 18 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS2 ADCS1 ADCS0 0003 C G -p ADPCFG 0302 — — — — PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 3 a 3 g ADSTAT 0306 — — — — — — — — — P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY P0RDY 0000 e 6 ADBASE 0308 ADBASE<15:1> — 0000 F 6 J ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00 0000 0 ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2 PEND2 SWTRG2 TRGSRC24 TRGSRC23 TRGSRC22 TRGSRC21 TRGSRC20 0000 6 ADCPC2 030E IRQEN5 PEND5 SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50 IRQEN4 PEND4 SWTRG4 TRGSRC44 TRGSRC43 TRGSRC42 TRGSRC41 TRGSRC40 0000 G ADCPC3 0310 — — — — — — — — IRQEN6 PEND6 SWTRG6 TRGSRC64 TRGSRC63 TRGSRC62 TRGSRC61 TRGSRC60 0000 S ADCBUF0 0320 ADC Data Buffer 0 xxxx 1 ADCBUF1 0322 ADC Data Buffer 1 xxxx 0 ADCBUF2 0324 ADC Data Buffer 2 xxxx 1 / ADCBUF3 0326 ADC Data Buffer 3 xxxx X ADCBUF4 0328 ADC Data Buffer 4 xxxx 0 ADCBUF5 032A ADC Data Buffer 5 xxxx 2 ADCBUF6 032C ADC Data Buffer 6 xxxx a ADCBUF7 032E ADC Data Buffer 7 xxxx n ADCBUF8 0330 ADC Data Buffer 8 xxxx d ADCBUF9 0332 ADC Data Buffer 9 xxxx d ADCBUF10 0334 ADC Data Buffer 10 xxxx s ADCBUF11 0336 ADC Data Buffer 11 xxxx P ADCBUF12 0338 ADC Data Buffer 12 xxxx I C ADCBUF13 033A ADC Data Buffer 13 xxxx 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 3 F  J 2 0 1 0 8 6 -2 0 G 1 4 M S icro X ch 0 ip T 2 e / ch X n o 0 lo g 4 y In c .

 TABLE 4-31: ANALOG COMPARATOR CONTROL REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY 2 0 d 08-2 NFaimlee ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts s 01 P 4 CMPCON1 0540 CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000 M I ic CMPDAC1 0542 — — — — — — CMREF<9:0> 0000 C roc CMPCON2 0544 CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000 3 hip CMPDAC2 0546 — — — — — — CMREF<9:0> 0000 3 T F e ch J no 0 log TABLE 4-32: ANALOG COMPARATOR CONTROL REGISTER MAP dsPIC33FJ16GS502/504 DEVICES ONLY 6 y Inc. NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts GS CMPCON1 0540 CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000 1 CMPDAC1 0542 — — — — — — CMREF<9:0> 0000 0 1 CMPCON2 0544 CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000 / CMPDAC2 0546 — — — — — — CMREF<9:0> 0000 X CMPCON3 0548 CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000 0 CMPDAC3 054A — — — — — — CMREF<9:0> 0000 2 CMPCON4 054C CMPON — CMPSIDL — — — — DACOE INSEL1 INSEL0 EXTREF — CMPSTAT — CMPPOL RANGE 0000 a CMPDAC4 054E — — — — — — CMREF<9:0> 0000 n d d s P I C 3 3 F J 1 6 G D S S 7 0 X 0 0 0 0 3 1 2 8 G / -p X a g 0 e 6 4 7

D TABLE 4-33: PERIPHERAL PIN SELECT INPUT REGISTER MAP d S 7 s 000 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts P 0 3 I 18 RPINR0 0680 — — INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 — — — — — — — — 3F00 C G -p RPINR1 0682 — — — — — — — — — — INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 003F 3 a 3 g RPINR2 0684 — — T1CKR5 T1CKR4 T1CKR3 T1CKR2 T1CKR1 T1CKR0 — — — — — — — — 0000 e 6 RPINR3 0686 — — T3CKR5 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 — — T2CKR5 T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 3F3F F 8 J RPINR7 068E — — IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 — — IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 3F3F 0 RPINR11 0696 — — — — — — — — — — OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 3F3F 6 RPINR18 06A4 — — U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 — — U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 003F G RPINR20 06A8 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 — — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 3F3F S RPINR21 06AA — — — — — — — — — — SS1R5 SS1R54 SS1R3 SS1R2 SS1R1 SS1R0 0000 1 RPINR29 06BA — — FLT1R5 FLT1R4 FLT1R3 FLT1R2 FLT1R1 FLT1R0 — — — — — — — — 3F00 0 RPINR30 06BC — — FLT3R5 FLT3R4 FLT3R3 FLT3R2 FLT3R1 FLT3R0 — — FLT2R5 FLT2R4 FLT2R3 FLT2R2 FLT2R1 FLT2R0 3F3F 1 / RPINR31 06BE — — FLT5R5 FLT5R4 FLT5R3 FLT5R2 FLT5R1 FLT5R0 — — FLT4R5 FLT4R4 FLT4R3 FLT4R2 FLT4R1 FLT4R0 3F3F X RPINR32 06C0 — — FLT7R5 FLT7R4 FLT7R3 FLT7R2 FLT7R1 FLT7R0 — — FLT6R5 FLT6R4 FLT6R3 FLT6R2 FLT6R1 FLT6R0 3F3F 0 RPINR33 06C2 — — SYNCI1R5 SYNCI1R4 SYNCI1R3 SYNCI1R2 SYNCI1R1 SYNCI1R0 — — FLT8R5 FLT8R4 FLT8R3 FLT8R2 FLT8R1 FLT8R0 3F3F 2 RPINR34 06C4 — — — — — — — — — — SYNCI2R5 SYNCI2R4 SYNCI2R3 SYNCI2R2 SYNCI2R1 SYNCI2R0 3F3F a Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. n d TABLE 4-34: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ06GS101 d s File SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P Name Addr Resets I RPOR0 06D0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000 C RPOR1 06D2 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 0000 3 RPOR2 06D4 — — RP5R5 RP5R4 RP5R3 RP5R2 RP5R1 RP5R0 — — RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 0000 3 F  RPOR3 06D6 — — RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 — — RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 0000 J 2 RPOR16 06F0 — — RP33R5 RP33R4 RP33R3 RP33R2 RP33R1 RP33R0 — — RP32R5 RP32R4 RP32R3 RP32R2 RP32R1 RP32R0 0000 0 1 0 8 RPOR17 06F2 — — RP35R5 RP35R4 RP35R3 RP35R2 RP35R1 RP35R0 — — RP34R5 RP34R4 RP34R3 RP34R2 RP34R1 RP34R0 0000 6 -2 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G 1 4 M S icro X ch 0 ip T 2 e / ch X n o 0 lo g 4 y In c .

 TABLE 4-35: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402 2 0 AND dsPIC33FJ16GS502 d 0 8 -201 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts sP 4 M I ic RPOR0 06D0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000 C roc RPOR1 06D2 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 0000 3 hip RPOR2 06D4 — — RP5R5 RP5R4 RP5R3 RP5R2 RP5R1 RP5R0 — — RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 0000 3 T F e RPOR3 06D6 — — RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 — — RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 0000 ch J no RPOR4 06D8 — — RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 — — RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 0000 0 log RPOR5 06DA — — RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 — — RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 0000 6 y In RPOR6 06DC — — RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 — — RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 0000 G c. RPOR7 06DE — — RP15R5 RP15R4 RP15R3 RP15R2 RP15R1 RP15R0 — — RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 0000 S RPOR16 06F0 — — RP33R5 RP33R4 RP33R3 RP33R2 RP33R1 RP33R0 — — RP32R5 RP32R4 RP32R3 RP32R2 RP32R1 RP32R0 0000 1 RPOR17 06F2 — — RP35R5 RP35R4 RP35R3 RP35R2 RP35R1 RP35R0 — — RP34R5 RP34R4 RP34R3 RP34R2 RP34R1 RP34R0 0000 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 / X TABLE 4-36: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ16GS404 AND dsPIC33FJ16GS504 0 2 File SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Name Addr Resets a n RPOR0 06D0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000 d RPOR1 06D2 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 0000 RPOR2 06D4 — — RP5R5 RP5R4 RP5R3 RP5R2 RP5R1 RP5R0 — — RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 0000 d s RPOR3 06D6 — — RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 — — RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 0000 P RPOR4 06D8 — — RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 — — RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 0000 I RPOR5 06DA — — RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 — — RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 0000 C RPOR6 06DC — — RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 — — RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 0000 3 RPOR7 06DE — — RP15R5 RP15R4 RP15R3 RP15R2 RP15R1 RP15R0 — — RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 0000 3 F RPOR8 06E0 — — RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 — — RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 0000 J RPOR9 06E2 — — RP19R5 RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 — — RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 0000 1 RPOR10 06E4 — — RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 0000 6 RPOR11 06E6 — — RP23R5 RP23R4 RP23R3 RP23R2 RP23R1 RP23R0 — — RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0 0000 G DS RPOR12 06E8 — — RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 — — RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 0000 S 70 RPOR13 06EA — — RP27R5 RP27R4 RP27R3 RP27R2 RP27R1 RP27R0 — — RP26R5 RP26R4 RP26R3 RP26R2 RP26R1 RP26R0 0000 X 0 00 RPOR14 06EC — — RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0 — — RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0 0000 0 3 1 RPOR16 06F0 — — RP33R5 RP33R4 RP33R3 RP33R2 RP33R1 RP33R0 — — RP32R5 RP32R4 RP32R3 RP32R2 RP32R1 RP32R0 0000 2 8 G RPOR17 06F2 — — RP35R5 RP35R4 RP35R3 RP35R2 RP35R1 RP35R0 — — RP34R5 RP34R4 RP34R3 RP34R2 RP34R1 RP34R0 0000 / -p X ag Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 e 6 4 9

D TABLE 4-37: PORTA REGISTER MAP d S 7 s 0 File SFR All 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P 0 Name Addr Resets 0 3 I 18 TRISA 02C0 — — — — — — — — — — — TRISA<4:0> 001F C G -p PORTA 02C2 — — — — — — — — — — — RA<4:0> xxxx 3 ag LATA 02C4 — — — — — — — — — — — LATA<4:0> 0000 3 e 7 ODCA 02C6 — — — — — — — — — — — ODCA<4:3> — — — 0000 F 0 J Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 6 TABLE 4-38: PORTB REGISTER MAP FOR dsPIC33FJ06GS101 G File SFR All S Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets 1 TRISB 02C8 — — — — — — — — TRISB<7:0> 00FF 0 1 PORTB 02CA — — — — — — — — RB<7:0> xxxx / LATB 02CC — — — — — — — — LATB<7:0> 0000 X ODCB 02CE — — — — — — — — ODCB<7:6> — ODCB4 — — — — 0000 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 a TABLE 4-39: PORTB REGISTER MAP FOR dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402, dsPIC33FJ16GS404, n dsPIC33FJ16GS502 AND dsPIC33FJ16GS504 d File SFR All d Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets s P TRISB 02C8 TRISB<15:0> FFFF I PORTB 02CA RB<15:0> xxxx C LATB 02CC LATB<15:0> 0000 3 ODCB 02CE ODCB<15:11> — — ODCB<8:6> — ODCB4(1) — — — — 0000 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. F  Note 1: This bit is not available on dsPIC33FJ06GS202/502 devices. J 2 0 1 0 8-2 TABLE 4-40: PORTC REGISTER MAP FOR dsPIC33FJ16GS404 AND dsPIC33FJ16GS504 6 0 G 1 4 M NSaFmRe ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts S icro TRISC 02D0 — — TRISC<13:0> 3FFF X ch 0 ip Te PLAOTRCTC 0022DD24 —— —— LRATCC<<1133:0:0>> x0x00x0x 2/ chn ODCC 02D6 — — ODCC<13:11> — — ODCC<8:3> — — ODCC0 0000 X o 0 lo Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. g 4 y In c .

 TABLE 4-41: SYSTEM CONTROL REGISTER MAP 2 008-2 NFaimlee ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ds 01 RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1) P 4 M OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF — — OSWEN 0300(2) IC ic ro CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN FRCDIV2 FRCDIV1 FRCDIV0 PLLPOST1 PLLPOST0 — PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0 3040 3 c hip PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0030 3 T REFOCON 074E ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000 F e ch OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000 J no ACLKCON 0750 ENAPLL APLLCK SELACLK — — APSTSCLR2 APSTSCLR1 APSTSCLR0 ASRCSEL FRCSEL — — — — — — 2300 0 log Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 y In Note 1: The RCON register Reset values are dependent on the type of Reset. G c. 2: The OSCCON register Reset values are dependent on the FOSCx Configuration bits and on type of Reset. S TABLE 4-42: NVM REGISTER MAP 1 0 File SFR All 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets / X NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) 0 NVMKEY 0766 — — — — — — — — NVMKEY<7:0> 0000 2 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: Reset value shown is for POR only. The value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. a n TABLE 4-43: PMD REGISTER MAP FOR dsPIC33FJ06GS101 DEVICES ONLY d File SFR All d Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets s PMD1 0770 — — — T2MD T1MD — PWMMD — I2C1MD — U1MD — SPI1MD — — ADCMD 0000 P PMD2 0772 — — — — — — IC2MD IC1MD — — — — — — OC2MD OC1MD 0000 I C PMD3 0774 — — — — — CMPMD — — — — — — — — — — 0000 3 PMD4 0776 — — — — — — — — — — — — REFOMD — — — 0000 3 PMD6 077A — — — — PWM4MD — — PWM1MD — — — — — — — — 0000 F Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. J 1 TABLE 4-44: PMD REGISTER MAP FOR dsPIC33FJ06GS102 DEVICES ONLY 6 File SFR All G Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D Name Addr Resets S S 7 0 PMD1 0770 — — — T2MD T1MD — PWMMD — I2C1MD — U1MD — SPI1MD — — ADCMD 0000 X 0 00 PMD2 0772 — — — — — — IC2MD IC1MD — — — — — — OC2MD OC1MD 0000 0 3 1 PMD3 0774 — — — — — CMPMD — — — — — — — — — — 0000 2 8 G PMD4 0776 — — — — — — — — — — — — REFOMD — — — 0000 / -p X a PMD6 077A — — — — — — PWM2MD PWM1MD — — — — — — — — 0000 g 0 e 7 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 1

D TABLE 4-45: PMD REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY d S 7 s 0 SFR SFR All 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P 0 Name Addr Resets 0 3 I 18 PMD1 0770 — — — T2MD T1MD — PWMMD — I2C1MD — U1MD — SPI1MD — — ADCMD 0000 C G -p PMD2 0772 — — — — — — — IC1MD — — — — — — — OC1MD 0000 3 ag PMD3 0774 — — — — — CMPMD — — — — — — — — — — 0000 3 e 7 PMD4 0776 — — — — — — — — — — — — REFOMD — — — 0000 F 2 J PMD6 077A — — — — — — PWM2MD PWM1MD — — — — — — — — 0000 0 PMD7 077C — — — — — — CMP2MD CMP1MD — — — — — — — — 0000 6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G S TABLE 4-46: PMD REGISTER MAP FOR dsPIC33FJ16GS402 AND dsPIC33FJ16GS404 DEVICES ONLY 1 0 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 1 Name Addr Resets / X PMD1 0770 — — T3MD T2MD T1MD — PWMMD — I2C1MD — U1MD — SPI1MD — — ADCMD 0000 0 PMD2 0772 — — — — — — IC2MD IC1MD — — — — — — OC2MD OC1MD 0000 2 PMD3 0774 — — — — — — — — — — — — — — — — 0000 a PMD4 0776 — — — — — — — — — — — — REFOMD — — — 0000 n PMD6 077A — — — — — PWM3MD PWM2MD PWM1MD — — — — — — — — 0000 d PMD7 077C — — — — — — — — — — — — — — — — 0000 d Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. s P TABLE 4-47: PMD REGISTER MAP FOR dsPIC33FJ16GS502 AND dsPIC33FJ16GS504 DEVICES ONLY I C SFR SFR All 3 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Addr Resets 3 F PMD1 0770 — — T3MD T2MD T1MD — PWMMD — I2C1MD — U1MD — SPI1MD — — ADCMD 0000  J 2 PMD2 0772 — — — — — — IC2MD IC1MD — — — — — — OC2MD OC1MD 0000 0 1 08 PMD3 0774 — — — — — CMPMD — — — — — — — — — — 0000 6 -20 PMD4 0776 — — — — — — — — — — — — REFOMD — — — 0000 G 1 4 PMD6 077A — — — — PWM4MD PWM3MD PWM2MD PWM1MD — — — — — — — — 0000 M S icroch PLeMgDe7nd: 07x7 C= unkno—wn value o—n Reset, — =— unimpleme—nted, reaCdM asP 4‘0M’.D ReseCt MvaPlu3eMsD are sChMowPn2 MinD hexaCdeMcPim1aMl.D — — — — — — — — 0000 X0 ip T 2 e / ch X n o 0 lo g 4 y In c .

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.2.6 SOFTWARE STACK 4.3 Instruction Addressing Modes In addition to its use as a Working register, the W15 The addressing modes shown in Table4-48 form the register in the dsPIC33FJ06GS101/X02 and basis of the addressing modes optimized to support the dsPIC33FJ16GSX02/X04 devices is also used as a specific features of individual instructions. The software Stack Pointer. The Stack Pointer always addressing modes provided in the MAC class of points to the first available free word and grows from instructions differ from those in the other instruction lower to higher addresses. It predecrements for stack types. pops and post-increments for stack pushes, as shown in Figure4-6. For a PC push during any CALL instruc- 4.3.1 FILE REGISTER INSTRUCTIONS tion, the MSb of the PC is zero-extended before the Most file register instructions use a 13-bit address field push, ensuring that the MSb is always clear. (f) to directly address data present in the first Note: A PC push during exception processing 8192bytes of data memory (Near Data Space). Most concatenates the SRL register to the MSb file register instructions employ a Working register, W0, of the PC prior to the push. which is denoted as WREG in these instructions. The destination is typically either the same file register or The Stack Pointer Limit register (SPLIM) associated WREG (with the exception of the MUL instruction), with the Stack Pointer sets an upper address boundary which writes the result to a register or register pair. The for the stack. SPLIM is uninitialized at Reset. As is the MOV instruction allows additional flexibility and can case for the Stack Pointer, SPLIM<0> is forced to ‘0’ access the entire data space. because all stack operations must be word-aligned. 4.3.2 MCU INSTRUCTIONS Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is The three-operand MCU instructions are of the form: compared with the value in SPLIM. If the contents of Operand 3 = Operand 1 <function> Operand 2 the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error where, Operand 1 is always a Working register (that is, trap will not occur. The stack error trap will occur on a the addressing mode can only be register direct), which subsequent push operation. For example, to cause a is referred to as Wb. Operand 2 can be a W register, stack error trap when the stack grows beyond address fetched from data memory, or a 5-bit literal. The result 0x1000 in RAM, initialize the SPLIM with the value location can be either a W register or a data memory 0x0FFE. location. The following addressing modes are supported by MCU instructions: Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to • Register Direct be less than 0x0800. This prevents the stack from • Register Indirect interfering with the Special Function Register (SFR) • Register Indirect Post-Modified space. • Register Indirect Pre-Modified • 5-bit or 10-bit Literal A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. Note: Not all instructions support all the addressing modes given above. Individ- FIGURE 4-6: CALL STACK FRAME ual instructions can support different subsets of these addressing modes. 0x0000 15 0 d waress Todr s Ad ower PC<15:0> W15 (before CALL) Grgh 000000000 PC<22:16> ck Hi <Free Word> W15 (after CALL) a St POP : [--W15] PUSH: [W15++]  2008-2014 Microchip Technology Inc. DS70000318G-page 73

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 4-48: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. 4.3.3 MOVE AND ACCUMULATOR 4.3.4 MAC INSTRUCTIONS INSTRUCTIONS The dual source operand DSP instructions (CLR, ED, Move instructions and the DSP accumulator class of EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred instructions to provide a greater addressing flexibility to as MAC instructions, use a simplified set of addressing than other instructions. In addition to the addressing modes to allow the user application to effectively modes supported by most MCU instructions, move and manipulate the Data Pointers through register indirect accumulator instructions also support Register Indirect tables. with Register Offset Addressing mode, also referred to The two-source operand prefetch registers must be as Register Indexed mode. members of the set {W8, W9, W10, W11}. For data Note: For the MOV instructions, the addressing reads, W8 and W9 are always directed to the X RAGU, mode specified in the instruction can differ and W10 and W11 are always directed to the Y AGU. for the source and destination EA. How- The Effective Addresses generated (before and after ever, the 4-bit Wb (register offset) field is modification) must, therefore, be valid addresses within shared by both source and destination X data space for W8 and W9 and Y data space for W10 (but typically only used by one). and W11. Note: Register Indirect with Register Offset In summary, the following addressing modes are Addressing mode is available only for W9 supported by move and accumulator instructions: (in X space) and W11 (in Y space). • Register Direct • Register Indirect In summary, the following addressing modes are • Register Indirect Post-modified supported by the MAC class of instructions: • Register Indirect Pre-modified • Register Indirect • Register Indirect with Register Offset (Indexed) • Register Indirect Post-Modified by 2 • Register Indirect with Literal Offset • Register Indirect Post-Modified by 4 • 8-bit Literal • Register Indirect Post-Modified by 6 • 16-bit Literal • Register Indirect with Register Offset (Indexed) Note: Not all instructions support all the addressing modes given above. Individual 4.3.5 OTHER INSTRUCTIONS instructions may support different subsets Besides the addressing modes outlined previously, some of these addressing modes. instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. DS70000318G-page 74  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.4 Modulo Addressing Note: Y space Modulo Addressing EA calcula- Modulo Addressing mode is a method used to provide tions assume word-sized data (LSb of an automated means to support circular data buffers every EA is always clear). using hardware. The objective is to remove the need The length of a circular buffer is not directly specified. It for software to perform data address boundary checks is determined by the difference between the when executing tightly looped code, as is typical in corresponding start and end addresses. The maximum many DSP algorithms. possible length of the circular buffer is 32K words Modulo Addressing can operate in either data or program (64Kbytes). space (since the Data Pointer mechanism is essentially 4.4.2 W ADDRESS REGISTER the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into SELECTION program space) and Y data spaces. Modulo Addressing The Modulo and Bit-Reversed Addressing Control can operate on any W register Pointer. However, it is not register, MODCON<15:0>, contains enable flags as advisable to use W14 or W15 for Modulo Addressing well as a W register field to specify the W Address since these two registers are used as the Stack Frame registers. The XWM and YWM fields select the Pointer and Stack Pointer, respectively. registers that will operate with Modulo Addressing: In general, any particular circular buffer can be • If XWM = 15, XRAGU and X WAGU Modulo configured to operate in only one direction as there are Addressing is disabled. certain restrictions on the buffer start address (for incre- • If YWM = 15, Y AGU Modulo Addressing is menting buffers), or end address (for decrementing disabled. buffers), based upon the direction of the buffer. The X Address Space Pointer W register (XWM), to The only exception to the usage restrictions is for which Modulo Addressing is to be applied, is stored in buffers that have a power-of-two length. As these MODCON<3:0> (see Table4-1). Modulo Addressing is buffers satisfy the start and end address criteria, they enabled for X data space when XWM is set to any value can operate in a bidirectional mode (that is, address other than ‘15’ and the XMODEN bit is set at boundary checks are performed on both the lower and MODCON<15>. upper address boundaries). The Y Address Space Pointer W register (YWM) to 4.4.1 START AND END ADDRESS which Modulo Addressing is to be applied is stored in MODCON<7:4>. Modulo Addressing is enabled for Y The Modulo Addressing scheme requires that a data space when YWM is set to any value other than starting and ending address be specified and loaded ‘15’ and the YMODEN bit is set at MODCON<14>. into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table4-1). FIGURE 4-7: MODULO ADDRESSING OPERATION EXAMPLE Byte MOV #0x1100, W0 Address MOV W0, XMODSRT ;set modulo start address MOV #0x1163, W0 MOV W0, MODEND ;set modulo end address 0x1100 MOV #0x8001, W0 MOV W0, MODCON ;enable W1, X AGU for modulo MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer 0x1163 DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words  2008-2014 Microchip Technology Inc. DS70000318G-page 75

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.4.3 MODULO ADDRESSING If the length of a bit-reversed buffer is M = 2N bytes, APPLICABILITY the last ‘N’ bits of the data buffer start address must be zeros. Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W XB<14:0> is the Bit-Reversed Address modifier, or register. Address boundaries check for addresses ‘pivot point,’ which is typically a constant. In the case of equal to: an FFT computation, its value is equal to half of the FFT data buffer size. • The upper boundary addresses for incrementing buffers Note: All bit-reversed EA calculations assume • The lower boundary addresses for decrementing word-sized data (LSb of every EA is buffers always clear). The XB value is scaled accordingly to generate compatible (byte) The address boundaries check for addresses less than addresses. or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses When enabled, Bit-Reversed Addressing is executed (not just equal to). Address changes can, therefore, only for Register Indirect with Pre-Increment or Post- jump beyond boundaries and still be adjusted correctly. Increment Addressing and word-sized data writes. It will not function for any other addressing mode or for Note: The modulo corrected Effective Address is byte-sized data, and normal addresses are generated written back to the register only when Pre- instead. When Bit-Reversed Addressing is active, the Modify or Post-Modify Addressing mode is W Address Pointer is always added to the address used to compute the Effective Address. modifier (XB), and the offset associated with the Regis- When an address offset (such as ter Indirect Addressing mode is ignored. In addition, as [W7+W2]) is used, Modulo Addressing word-sized data is a requirement, the LSb of the EA is correction is performed but the contents of ignored (and always clear). the register remain unchanged. Note: Modulo Addressing and Bit-Reversed 4.5 Bit-Reversed Addressing Addressing should not be enabled together. If an application attempts to do Bit-Reversed Addressing mode is intended to simplify so, Bit-Reversed Addressing will assume data re-ordering for radix-2 FFT algorithms. It is priority when active for the X WAGU and X supported by the X AGU for data writes only. WAGU; Modulo Addressing will be dis- abled. However, Modulo Addressing will The modifier, which can be a constant value or register continue to function in the X RAGU. contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. If Bit-Reversed Addressing has already been enabled Thus, the only operand requiring reversal is the modifier. by setting the BREN (XBREV<15>) bit, a write to the XBREV register should not be immediately followed by 4.5.1 BIT-REVERSED ADDRESSING an indirect read operation using the W register that has IMPLEMENTATION been designated as the Bit-Reversed Pointer. Bit-Reversed Addressing mode is enabled in any of these situations: • BWM bits (W register selection) in the MODCON register are any value other than 15 (the stack cannot be accessed using Bit-Reversed Addressing) • The BREN bit is set in the XBREV register • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment DS70000318G-page 76  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-49: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15  2008-2014 Microchip Technology Inc. DS70000318G-page 77

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.6 Interfacing Program and Data 4.6.1 ADDRESSING PROGRAM SPACE Memory Spaces Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ needed to create a 23-bit or 24-bit program address X04 architecture uses a 24-bit-wide program space and a from 16-bit data registers. The solution depends on the 16-bit-wide data space. The architecture is also a interface method to be used. modified Harvard scheme, meaning that data can also be present in the program space. To use this data For table operations, the 8-bit Table Page register successfully, it must be accessed in a way that preserves (TBLPAG) is used to define a 32K word region within the alignment of information in both spaces. the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In Aside from normal execution, the dsPIC33FJ06GS101/ this format, the Most Significant bit of TBLPAG is used X02 and dsPIC33FJ16GSX02/X04 architecture to determine if the operation occurs in the user memory provides two methods by which program space can be (TBLPAG<7> = 0) or the configuration memory accessed during operation: (TBLPAG<7> = 1). • Using table instructions to access individual bytes For remapping operations, the 8-bit Program Space or words anywhere in the program space Visibility register (PSVPAG) is used to define a • Remapping a portion of the program space into 16Kword page in the program space. When the Most the data space (Program Space Visibility) Significant bit of the EA is ‘1’, PSVPAG is concatenated Table instructions allow an application to read or write with the lower 15 bits of the EA to form a 23-bit program to small areas of the program memory. This capability space address. Unlike table operations, this limits makes the method ideal for accessing data tables that remapping operations strictly to the user memory area. need to be updated periodically. It also allows access Table4-50 and Figure4-9 show how the program EA is to all bytes of the program word. The remapping created for table operations and remapping accesses method allows an application to access a large block of from the data EA. Here, P<23:0> refers to a program data on a read-only basis, which is ideal for look ups space word, and D<15:0> refers to a data space word. from a large table of static data. The application can only access the least significant word of the program word. TABLE 4-50: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 (Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0>(1) (Block Remap/Read) 0 xxxx xxxx xxx xxxx xxxx xxxx Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. DS70000318G-page 78  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 0 23 Bits EA 1/0 Table Operations(2) 1/0 TBLPAG 8 Bits 16 Bits 24 Bits Select 1 EA 0 Program Space Visibility(1) 0 PSVPAG (Remapping) 8 Bits 15 Bits 23 Bits User/Configuration Byte Select Space Select Note1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table Read operations are permitted in the configuration memory space.  2008-2014 Microchip Technology Inc. DS70000318G-page 79

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.6.2 DATA ACCESS FROM PROGRAM - In Byte mode, either the upper or lower byte MEMORY USING TABLE of the lower program word is mapped to the INSTRUCTIONS lower byte of a data address. The upper byte is selected when byte select is ‘1’; the lower The TBLRDL and TBLWTL instructions offer a direct byte is selected when it is ‘0’. method of reading or writing the lower word of any • TBLRDH (Table Read High): address within the program space without going through data space. The TBLRDH and TBLWTH - In Word mode, this instruction maps the entire instructions are the only method to read or write the upper word of a program address (P<23:16>) upper 8bits of a program space word as data. to a data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’. The PC is incremented by two for each successive - In Byte mode, this instruction maps the upper 24-bit program word. This allows program memory or lower byte of the program word to D<7:0> of addresses to directly map to data space addresses. the data address, in the TBLRDL instruction. Program memory can thus be regarded as two 16-bit The data is always ‘0’ when the upper wide word address spaces, residing side by side, each ‘phantom’ byte is selected (Byte Select= 1). with the same address range. TBLRDL and TBLWTL access the space that contains the least significant Similarly, two table instructions, TBLWTH and TBLWTL, data word. TBLRDH and TBLWTH access the space that are used to write individual bytes or words to a program contains the upper data byte. space address. The details of their operation are explained in Section5.0 “Flash Program Memory”. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. For all table operations, the area of program memory Both function as either byte or word operations. space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program • TBLRDL (Table Read Low): memory space of the device, including user and con- - In Word mode, this instruction maps the figuration spaces. When TBLPAG<7> = 0, the table lower word of the program space location page is located in the user memory space. When (P<15:0>) to a data address (D<15:0>). TBLPAG<7>=1, the page is located in configuration space. FIGURE 4-10: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG 02 23 15 0 0x000000 23 16 8 0 00000000 00000000 0x020000 00000000 0x030000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 0x800000 Only read operations are shown; write operations are also valid in the user memory area. DS70000318G-page 80  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.6.3 READING DATA FROM PROGRAM 24-bit program word are used to contain the data. The MEMORY USING PROGRAM SPACE upper 8 bits of any program space location used as VISIBILITY data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible The upper 32 Kbytes of data space may optionally be issues should the area of code ever be accidentally mapped into any 16K word page of the program space. executed. This option provides transparent access to stored constant data from the data space without the need to Note: PSV access is temporarily disabled during use special instructions (such as TBLRDL/H). Table Reads/Writes. Program space access through the data space occurs For operations that use PSV and are executed outside if the Most Significant bit of the data space EA is ‘1’ and a REPEAT loop, the MOV and MOV.D instructions require Program Space Visibility (PSV) is enabled by setting one instruction cycle in addition to the specified the PSV bit in the Core Control register execution time. All other instructions require two (CORCON<2>). The location of the program memory instruction cycles in addition to the specified execution space to be mapped into the data space is determined time. by the Program Space Visibility Page register For operations that use PSV, and are executed inside (PSVPAG). This 8-bit register defines any one of 256 a REPEAT loop, these instances require two instruction possible pages of 16Kwords in program space. In cycles in addition to the specified execution time of the effect, PSVPAG functions as the upper 8 bits of the instruction: program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC • Execution in the first iteration by 2 for each program memory word, the lower 15 bits • Execution in the last iteration of data space addresses directly map to the lower • Execution prior to exiting the loop due to an 15bits in the corresponding program space addresses. interrupt Data reads to this area add a cycle to the instruction • Execution upon re-entering the loop after an being executed, since two program memory fetches interrupt is serviced are required. Any other iteration of the REPEAT loop will allow the Although each data space address 8000h and higher instruction using PSV to access data, to execute in a maps directly into a corresponding program memory single cycle. address (see Figure4-11), only the lower 16 bits of the FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space Data Space PSVPAG 23 15 0 02 0x000000 0x0000 Data EA<14:0> 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory 0x8000 space... PSV Area ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 0x800000  2008-2014 Microchip Technology Inc. DS70000318G-page 81

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 82  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 5.0 FLASH PROGRAM MEMORY power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with Note 1: This data sheet summarizes the features unprogrammed devices and then program the Digital of the dsPIC33FJ06GS101/X02 and Signal Controller just before shipping the product. This dsPIC33FJ16GSX02/X04 families of also allows the most recent firmware or a custom devices. It is not intended to be a firmware to be programmed. comprehensive reference source. To RTSP is accomplished using TBLRD (Table Read) and complement the information in this data TBLWT (Table Write) instructions. With RTSP, the user sheet, refer to “Flash Programming” application can write program memory data, either in (DS70191) in the “dsPIC33F/PIC24H blocks or ‘rows’ of 64 instructions (192 bytes) at a time, Family Reference Manual”, which is avail- or a single program memory word, and erase program able from the Microchip web site memory in blocks or ‘pages’ of 512 instructions (www.microchip.com). (1536bytes) at a time. 2: Some registers and associated bits described in this section may not be 5.1 Table Instructions and Flash available on all devices. Refer to Programming Section4.0 “Memory Organization” in this data sheet for device-specific register Regardless of the method used, all programming of and bit information. Flash memory is done with the Table Read and Table Write instructions. These allow direct read and write The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ access to the program memory space from the data X04 devices contain internal Flash program memory for memory while the device is in normal operating mode. storing and executing application code. The memory is The 24-bit target address in the program memory is readable, writable and erasable during normal operation formed using bits<7:0> of the TBLPAG register and the over the entire VDD range. Effective Address (EA) from a W register specified in Flash memory can be programmed in two ways: the table instruction, as shown in Figure5-1. • In-Circuit Serial Programming™ (ICSP™) The TBLRDL and the TBLWTL instructions are used to programming capability read or write to bits<15:0> of program memory. • Run-Time Self-Programming (RTSP) TBLRDL and TBLWTL can access program memory in both Word and Byte modes. ICSP allows a dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 device to be serially The TBLRDH and TBLWTH instructions are used to read programmed while in the end application circuit. This is or write to bits<23:16> of program memory. TBLRDH done with two lines for programming clock and and TBLWTH can also access program memory in Word programming data (one of the alternate programming or Byte mode. pin pairs: PGECx/PGEDx, and three other lines for FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 Bits Using 0 Program Counter 0 Program Counter Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 Bits 16 Bits User/Configuration Byte Space Select 24-Bit EA Select  2008-2014 Microchip Technology Inc. DS70000318G-page 83

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 5.2 RTSP Operation For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN<5:0> bits (see The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ Register8-4) are set to ‘b111111, the minimum row X04 Flash program memory array is organized into rows write time is equal to Equation5-2. of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of EQUATION 5-2: MINIMUM ROW WRITE eight rows (512 instructions) at a time, and to program TIME one row or one word at a time. Table24-12 shows typical erase and programming times. The 8-row erase pages 11064 Cycles and single row write rows are edge-aligned from the TRW =7---.--3---7--- --M-----H----z-----------1-----+-----0---.-0---5--------------1-----–----0---.--0---0---3---7---5----=1.435ms beginning of program memory, on boundaries of 1536bytes and 192 bytes, respectively. The program memory implements holding buffers that The maximum row write time is equal to Equation5-3. can contain 64 instructions of programming data. Prior to the actual programming operation, the write data EQUATION 5-3: MAXIMUM ROW WRITE must be loaded into the buffers sequentially. The TIME instruction words loaded must always be from a group of 64 boundary. 11064 Cycles T =----------------------------------------------------------------------------------------------=1.586ms The basic sequence for RTSP programming is to set up RW 7.37 MHz1–0.051–0.00375 a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total Setting the WR bit (NVMCON<15>) starts the opera- of 64 TBLWTL and TBLWTH instructions are required tion, and the WR bit is automatically cleared when the to load the instructions. operation is finished. All of the Table Write operations are single-word writes 5.4 Control Registers (two instruction cycles) because only the buffers are written. A programming cycle is required for Two SFRs are used to read and write the program programming each row. Flash memory: NVMCON and NVMKEY. The NVMCON register (Register5-1) controls which 5.3 Programming Operations blocks are to be erased, which memory type is to be A complete programming sequence is necessary for programmed and the start of the programming cycle. programming or erasing the internal Flash in RTSP NVMKEY is a write-only register that is used for write mode. The processor stalls (waits) until the protection. To start a programming or erase sequence, programming operation is finished. the user application must consecutively write 0x55 and The programming time depends on the FRC accuracy 0xAA to the NVMKEY register. Refer to Section5.3 (see Table24-20) and the value of the FRC Oscillator “Programming Operations” for further details. Tuning register (see Register8-4). Use the following formula to calculate the minimum and maximum values for the Row Write Time, Page Erase Time, and Word Write Cycle Time parameters (see Table24-12). EQUATION 5-1: PROGRAMMING TIME T -------------------------------------------------------------------------------------------------------------------------- 7.37 MHzFRC Accuracy%FRC Tuning% DS70000318G-page 84  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — ERASE — — NVMOP3(2) NVMOP2(2) NVMOP1(2) NVMOP0(2) bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit(1) 1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once the operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit(1) 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt, or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit(1) 1 = Performs the erase operation specified by NVMOP<3:0> on the next WR command 0 = Performs the program operation specified by NVMOP<3:0> on the next WR command bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,2) If ERASE = 1: 1111 = Memory bulk erase operation 1101 = Erase general segment 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte If ERASE = 0: 1111 = No operation 1101 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be Reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented.  2008-2014 Microchip Technology Inc. DS70000318G-page 85

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Nonvolatile Memory Key bits (write-only) DS70000318G-page 86  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 5.4.1 PROGRAMMING ALGORITHM FOR 4. Write the first 64 instructions from data RAM into FLASH PROGRAM MEMORY the program memory buffers (see Example5-2). 5. Write the program block to Flash memory: One row of program Flash memory can be programmed at a time. To achieve this, it is necessary a) Set the NVMOP<3:0> bits to ‘0001’ to to erase the 8-row erase page that contains the desired configure for row programming. Clear the row. The general process is: ERASE bit and set the WREN bit. b) Write 0x55 to the NVMKEY register. 1. Read eight rows of program memory (512instructions) and store in data RAM. c) Write 0xAA to the NVMKEY register. 2. Update the program data in RAM with the desired d) Set the WR bit. The programming cycle begins new data. and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, 3. Erase the block (see Example5-1): the WR bit is cleared automatically. a) Set the NVMOP<3:0> bits (NVMCON<3:0>) to 6. Repeat Steps 4 and 5, using the next available ‘0010’ to configure for block erase. Set 64instructions from the block in data RAM by incre- the ERASE (NVMCON<6>) and WREN menting the value in the TBLPAG register, until all (NVMCON<14>) bits. 512instructions are written back to Flash memory. b) Write the starting address of the page to be erased into the TBLPAG and W registers. For protection against accidental operations, the write initiate sequence for the NVMKEY register must be c) Write 0x55 to NVMKEY. used to allow any erase or program operation to d) Write 0xAA to NVMKEY. proceed. After the programming command has been e) Set the WR bit (NVMCON<15>). The erase executed, the user application must wait for the pro- cycle begins and the CPU stalls for the duration gramming time until programming is complete. The two of the erase cycle. When the erase is done, the instructions following the start of the programming WR bit is cleared automatically. sequence should be NOPs, as shown in Example5-3. EXAMPLE 5-1: ERASING A PROGRAM MEMORY PAGE ; Set up NVMCON for block erase operation MOV #0x4042, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted  2008-2014 Microchip Technology Inc. DS70000318G-page 87

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch • • • ; 63rd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch EXAMPLE 5-3: INITIATING A PROGRAMMING SEQUENCE DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the NOP ; erase command is asserted DS70000318G-page 88  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.0 RESETS A simplified block diagram of the Reset module is shown in Figure6-1. Note1: This data sheet summarizes the features Any active source of Reset will make the SYSRST of the dsPIC33FJ06GS101/X02 and signal active. On system Reset, some of the registers dsPIC33FJ16GSX02/X04 families of associated with the CPU and peripherals are forced to devices. It is not intended to be a a known Reset state and some are unaffected. comprehensive reference source. To complement the information in this data Note: Refer to the specific peripheral section or sheet, refer to “Reset” (DS70192) in the Section3.0 “CPU” of this data sheet for “dsPIC33F/PIC24H Family Reference register Reset states. Manual”, which is available from the All types of device Reset set a corresponding status bit Microchip web site (www.microchip.com). in the RCON register to indicate the type of Reset (see 2: Some registers and associated bits Register6-1). described in this section may not be A POR clears all the bits, except for the POR bit available on all devices. Refer to (RCON<0>), which is set. The user application can set Section4.0 “Memory Organization” in or clear any bit at any time during code execution. The this data sheet for device-specific register RCON bits only serve as status bits. Setting a particular and bit information. Reset status bit in software does not cause a device The Reset module combines all Reset sources and Reset to occur. controls the device Master Reset Signal, SYSRST. The The RCON register also has other bits associated with following is a list of device Reset sources: the Watchdog Timer and device power-saving states. • POR: Power-on Reset The function of these bits is discussed in other sections of this manual. • BOR: Brown-out Reset • MCLR: Master Clear Pin Reset Note: The status bits in the RCON register • SWR: Software RESET Instruction should be cleared after they are read so that the next RCON register value after a • WDTO: Watchdog Timer Reset device Reset is meaningful. • CM: Configuration Mismatch Reset • TRAPR: Trap Conflict Reset • IOPUWR: Illegal Condition Device Reset - Illegal Opcode Reset - Uninitialized W Register Reset - Security Reset FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle BOR Internal Regulator SYSRST VDD VDD Rise POR Detect Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch  2008-2014 Microchip Technology Inc. DS70000318G-page 89

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R E GISTER 6-1: RCON: RESET CONTROL REGISTER(1) R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 TRAPR IOPUWR — — — — CM VREGS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or Uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or Uninitialized W register Reset has not occurred bit 13-10 Unimplemented: Read as ‘0’ bit 9 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has occurred 0 = A Configuration Mismatch Reset has NOT occurred bit 8 VREGS: Voltage Regulator Standby During Sleep bit 1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Standby mode during Sleep bit 7 EXTR: External Reset Pin (MCLR) bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset Flag (Instruction) bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70000318G-page 90  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.  2008-2014 Microchip Technology Inc. DS70000318G-page 91

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.1 System Reset A Warm Reset is the result of all the other Reset sources, including the RESET instruction. On Warm The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ Reset, the device will continue to operate from the X04 families of devices have two types of Reset: current clock source as indicated by the Current • Cold Reset Oscillator Selection (COSC<2:0>) bits in the Oscillator • Warm Reset Control (OSCCON<14:12>) register. A Cold Reset is the result of a Power-on Reset (POR) The device is kept in a Reset state until the system or a Brown-out Reset (BOR). On a Cold Reset, the power supplies have stabilized at appropriate levels FNOSCx Configuration bits in the FOSC Configuration and the oscillator clock is ready. The sequence in register select the device clock source. which this occurs is detailed in Figure6-2. TABLE 6-1: OSCILLATOR DELAY Oscillator Oscillator Oscillator Mode PLL Lock Time Total Delay Startup Delay Startup Timer FRC, FRCDIV16, TOSCD(1) — — TOSCD(1) FRCDIVN FRCPLL TOSCD(1) — TLOCK(3) TOSCD + TLOCK(1,3) XT TOSCD(1) TOST(2) — TOSCD + TOST(1,2) HS TOSCD(1) TOST(2) — TOSCD + TOST(1,2) EC — — — — XTPLL TOSCD(1) TOST(2) TLOCK(3) TOSCD + TOST + TLOCK(1,2,3) HSPLL TOSCD(1) TOST(2) TLOCK(3) TOSCD + TOST + TLOCK(1,2,3) ECPLL — — TLOCK(3) TLOCK(3) LPRC TOSCD(1) — — TOSCD(1) Note 1: TOSCD = Oscillator start-up delay (1.1s max for FRC, 70s max for LPRC). Crystal oscillator start-up times vary with crystal characteristics, load capacitance, etc. 2: TOST = Oscillator Start-up Timer delay (1024 oscillator clock period). For example, TOST = 102.4s for a 10MHz crystal and TOST=32ms for a 32kHz crystal. 3: TLOCK = PLL lock time (1.5ms nominal) if PLL is enabled. DS70000318G-page 92  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 6-2: SYSTEM RESET TIMING VBOR VPOR VDD TPOR 1 POR Reset TBOR 2 BOR Reset 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 TFSCM FSCM 5 Device Status Reset Run Time Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. 2: BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes stable. 3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (TPWRT) after a BOR. The delay, TPWRT, ensures that the system power supplies have stabilized at the appro- priate level for full-speed operation. After the delay, TPWRT has elapsed and the SYSRST becomes inactive, which in turn, enables the selected oscillator to start generating clock cycles. 4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in Table6-1. Refer to Section8.0 “Oscillator Configuration” for more information. 5: When the oscillator clock is ready, the processor begins execution from location, 0x000000. The user application programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. 6: If the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is ready and the delay, TFSCM, has elapsed. TABLE 6-2: OSCILLATOR DELAY Note: When the device exits the Reset Symbol Parameter Value condition (begins normal operation), the device operating parameters (voltage, VPOR POR Threshold 1.8V nominal frequency, temperature, etc.) must be TPOR POR Extension Time 30s maximum within their operating ranges; otherwise, VBOR BOR Threshold 2.5V nominal the device may not function correctly. TBOR BOR Extension Time 100s maximum The user application must ensure that the delay between the time power is first TPWRT Programmable 0-128ms nominal applied, and the time SYSRST becomes Power-up Time Delay inactive, is long enough to get all TFSCM Fail-Safe Clock Monitor 900s maximum operating parameters within specification. Delay  2008-2014 Microchip Technology Inc. DS70000318G-page 93

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.2 Power-on Reset (POR) VBOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output A Power-on Reset (POR) circuit ensures the device is becomes stable. reset from power-on. The POR circuit is active until The BOR status (BOR) bit in the Reset Control VDD crosses the VPOR threshold and the delay, TPOR, (RCON<1>) register is set to indicate the Brown-out has elapsed. The delay, TPOR, ensures the internal Reset. device bias circuits become stable. The device will not run at full speed after a BOR as the The device supply voltage characteristics must meet the specified starting voltage and rise rate VDD should rise to acceptable levels for full-speed operation. The PWRT provides power-up time delay requirements to generate the POR. Refer to Section24.0 “Electrical Characteristics” for details. (TPWRT) to ensure that the system power supplies have stabilized at the appropriate levels for full-speed The POR status (POR) bit in the Reset Control operation before the SYSRST is released. (RCON<0>) register is set to indicate the Power-on Reset. The Power-up Timer Delay (TPWRT) is programmed by the Power-on Reset Timer Value Select 6.2.1 Brown-out Reset (BOR) and (FPWRT<2:0>) bits in the FPOR Configuration Power-up Timer (PWRT) (FPOR<2:0>) register, which provides eight settings (from 0ms to 128ms). Refer to Section21.0 “Special The on-chip regulator has a Brown-out Reset (BOR) Features” for further details. circuit that resets the device when the VDD is too low Figure6-3 shows the typical brown-out scenarios. The (VDD < VBOR) for proper device operation. The BOR Reset delay (TBOR + TPWRT) is initiated each time VDD circuit keeps the device in Reset until VDD crosses the rises above the VBOR trip point. FIGURE 6-3: BROWN-OUT SITUATIONS VDD VBOR TBOR + TPWRT SYSRST VDD VBOR TBOR + TPWRT SYSRST VDD Dips before PWRT Expires VDD VBOR TBOR + TPWRT SYSRST DS70000318G-page 94  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.3 External Reset (EXTR) 6.6 Trap Conflict Reset The External Reset is generated by driving the MCLR If a lower priority hard trap occurs while a higher pin low. The MCLR pin is a Schmitt trigger input with an priority trap is being processed, a hard Trap Conflict additional glitch filter. Reset pulses that are longer than Reset occurs. The hard traps include exceptions of the minimum pulse width will generate a Reset. Refer Priority Levels 13 through 15, inclusive. The address to Section24.0 “Electrical Characteristics” for error (Level13) and oscillator error (Level 14) traps fall minimum pulse width specifications. The External into this category. Reset (MCLR) pin (EXTR) bit in the Reset Control The Trap Reset (TRAPR) flag in the Reset Control (RCON) register is set to indicate the MCLR Reset. (RCON<15>) register is set to indicate the Trap Conflict Reset. Refer to Section7.0 “Interrupt Controller” for 6.3.0.1 EXTERNAL SUPERVISORY more information on Trap Conflict Resets. CIRCUIT Many systems have external supervisory circuits that 6.7 Configuration Mismatch Reset generate Reset signals to reset multiple devices in the system. This External Reset signal can be directly To maintain the integrity of the Peripheral Pin Select connected to the MCLR pin to reset the device when Control registers, they are constantly monitored with the rest of the system is reset. shadow registers in hardware. If an unexpected change in any of the registers occur (such as cell 6.3.0.2 INTERNAL SUPERVISORY CIRCUIT disturbances caused by ESD or other external events), a Configuration Mismatch Reset occurs. When using the internal power supervisory circuit to reset the device, the External Reset pin (MCLR) should The Configuration Mismatch (CM) flag in the Reset be tied directly or resistively to VDD. In this case, the Control (RCON<9>) register is set to indicate the MCLR pin will not be used to generate a Reset. The Configuration Mismatch Reset. Refer to Section10.0 External Reset pin (MCLR) does not have an internal “I/O Ports” for more information on the pull-up and must not be left unconnected. Configuration Mismatch Reset. Note: The Configuration Mismatch Reset 6.4 Software RESET Instruction (SWR) feature and associated Reset flag are not available on all devices. Whenever the RESET instruction is executed, the device will assert SYSRST, placing the device in a 6.8 Illegal Condition Device Reset special Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to An illegal condition device Reset occurs due to the the RESET instruction will remain. SYSRST is released following sources: at the next instruction cycle and the Reset vector fetch • Illegal Opcode Reset will commence. • Uninitialized W Register Reset The Software Reset (SWR) flag (instruction) in the • Security Reset Reset Control (RCON<6>) register is set to indicate The Illegal Opcode or Uninitialized W Access Reset the Software Reset. (IOPUWR) flag in the Reset Control (RCON<14>) register is set to indicate the illegal condition device 6.5 Watchdog Timer Time-out Reset Reset. (WDTO) 6.8.1 ILLEGAL OPCODE RESET Whenever a Watchdog time-out occurs, the device will asynchronously assert SYSRST. The clock source will A device Reset is generated if the device attempts to remain unchanged. A WDT time-out during Sleep or execute an illegal opcode value that is fetched from Idle mode will wake-up the processor, but will not reset program memory. the processor. The Illegal Opcode Reset function can prevent the The Watchdog Timer Time-out (WDTO) flag in the device from executing program memory sections that Reset Control (RCON<4>) register is set to indicate are used to store constant data. To take advantage of the Watchdog Timer Reset. Refer to Section21.4 the Illegal Opcode Reset, use only the lower 16 bits of “Watchdog Timer (WDT)” for more information on each program memory section to store the data values. the Watchdog Timer Reset. The upper 8 bits should be programmed with 3Fh, which is an illegal opcode value.  2008-2014 Microchip Technology Inc. DS70000318G-page 95

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.8.2 UNINITIALIZED W REGISTER The VFC occurs when the Program Counter is RESET reloaded with an interrupt or trap vector. Any attempt to use the Uninitialized W register as an Refer to Section21.8 “Code Protection and Address Pointer will reset the device. The W register CodeGuard™ Security” for more information on array (with the exception of W15) is cleared during all Security Reset. Resets and is considered uninitialized until written to. 6.9 Using the RCON Status Bits 6.8.3 SECURITY RESET The user application can read the Reset Control If a Program Flow Change (PFC) or Vector Flow (RCON) register after any device Reset to determine Change (VFC) targets a restricted location in a the cause of the Reset. protected segment (boot and secure segment), that operation will cause a Security Reset. Note: The status bits in the RCON register should be cleared after they are read so The PFC occurs when the Program Counter is that the next RCON register value after a reloaded as a result of a call, jump, computed jump, device Reset will be meaningful. return, return from subroutine or other form of branch instruction. Table6-3 provides a summary of the Reset flag bit operation. TABLE 6-3: RESET FLAG BIT OPERATION Flag Bit Set by: Cleared by: TRAPR (RCON<15>) Trap conflict event POR, BOR IOPWR (RCON<14>) Illegal opcode or Uninitialized W register POR, BOR access or Security Reset CM (RCON<9>) Configuration Mismatch POR, BOR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET instruction POR, BOR WDTO (RCON<4>) WDT time-out PWRSAV instruction, CLRWDT instruction, POR, BOR SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR, BOR IDLE (RCON<2>) PWRSAV #IDLE instruction POR, BOR BOR (RCON<1>) POR, BOR — POR (RCON<0>) POR — Note: All Reset flag bits can be set or cleared by user software. DS70000318G-page 96  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 7.0 INTERRUPT CONTROLLER Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the Note1: This data sheet summarizes the features vector table. Lower addresses generally have a higher of the dsPIC33FJ06GS101/X02 and natural priority. For example, the interrupt associated dsPIC33FJ16GSX02/X04 families of with Vector 0 will take priority over interrupts at any devices. It is not intended to be a other vector address. comprehensive reference source. To The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ complement the information in this data X04 devices implement up to 35 unique interrupts and sheet, refer to “Interrupts (Part IV)” 4non-maskable traps. These are summarized in (DS70300) in the “dsPIC33F/PIC24H Table7-1. Family Reference Manual”, which is available on the Microchip web site 7.1.1 ALTERNATE INTERRUPT VECTOR (www.microchip.com). TABLE 2: Some registers and associated bits The Alternate Interrupt Vector Table (AIVT) is located described in this section may not be after the IVT, as shown in Figure7-1. Access to the available on all devices. Refer to AIVT is provided by the ALTIVT control bit Section4.0 “Memory Organization” in (INTCON2<15>). If the ALTIVT bit is set, all interrupt this data sheet for device-specific register and exception processes use the alternate vectors and bit information. instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 interrupt controller reduces the numerous The AIVT supports debugging by providing a means to peripheral interrupt request signals to a single interrupt switch between an application and a support environ- request signal to the dsPIC33FJ06GS101/X02 and ment without requiring the interrupt vectors to be dsPIC33FJ16GSX02/X04 CPU. It has the following reprogrammed. This feature also enables switching features: between applications for evaluation of different software algorithms at run time. If the AIVT is not • Up to eight processor exceptions and software needed, the AIVT should be programmed with the traps same addresses used in the IVT. • Seven user-selectable priority levels • Interrupt Vector Table (IVT) with up to 118 vectors 7.2 Reset Sequence • A unique vector for each interrupt or exception source A device Reset is not a true exception because the • Fixed priority within a specified user priority level interrupt controller is not involved in the Reset process. The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ • Alternate Interrupt Vector Table (AIVT) for debug X04 devices clear their registers in response to a Reset, support which forces the PC to zero. The Digital Signal Controller • Fixed interrupt entry and return latencies then begins program execution at location, 0x000000. A GOTO instruction at the Reset address can redirect 7.1 Interrupt Vector Table program execution to the appropriate start-up routine. The Interrupt Vector Table (IVT) is shown in Figure7-1. Note: Any unimplemented or unused vector The IVT resides in program memory, starting at location locations in the IVT and AIVT should be 000004h. The IVT contains 126 vectors, consisting of programmed with the address of a default eight nonmaskable trap vectors, plus up to 118 sources interrupt handler routine that contains a of interrupt. In general, each interrupt source has its own RESET instruction. vector. Each interrupt vector contains a 24-bit-wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR).  2008-2014 Microchip Technology Inc. DS70000318G-page 97

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 7-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 INTERRUPT VECTOR TABLE Reset – GOTO Instruction 0x000000 Reset – GOTO Address 0x000002 Reserved 0x000004 Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 0x000014 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 0x00007C Interrupt Vector Table (IVT)(1) Interrupt Vector 53 0x00007E ority Interrupt ~Vector 54 0x000080 Pri ~ der ~ Or Interrupt Vector 116 0x0000FC al Interrupt Vector 117 0x0000FE atur Reserved 0x000100 N Reserved 0x000102 g n Reserved si a Oscillator Fail Trap Vector e cr Address Error Trap Vector e D Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 0x000114 Interrupt Vector 1 ~ ~ ~ Alternate Interrupt Vector Table (AIVT)(1) Interrupt Vector 52 0x00017C Interrupt Vector 53 0x00017E Interrupt Vector 54 0x000180 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 0x0001FE Start of Code 0x000200 Note 1: See Table7-1 for the list of implemented interrupt vectors. DS70000318G-page 98  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 7-1: INTERRUPT VECTORS Interrupt Vector Request IVT Address AIVT Address Interrupt Source Number (IQR) Highest Natural Order Priority 8 0 0x000014 0x000114 INT0 – External Interrupt 0 9 1 0x000016 0x000116 IC1 – Input Capture 1 10 2 0x000018 0x000118 OC1 – Output Compare 1 11 3 0x00001A 0x00011A T1 – Timer1 12 4 0x00001C 0x00011C Reserved 13 5 0x00001E 0x00011E IC2 – Input Capture 2 14 6 0x000020 0x000120 OC2 – Output Compare 2 15 7 0x000022 0x000122 T2 – Timer2 16 8 0x000024 0x000124 T3 – Timer3 17 9 0x000026 0x000126 SPI1E – SPI1 Fault 18 10 0x000028 0x000128 SPI1 – SPI1 Transfer Done 19 11 0x00002A 0x00012A U1RX – UART1 Receiver 20 12 0x00002C 0x00012C U1TX – UART1 Transmitter 21 13 0x00002E 0x00012E ADC–ADC Group Convert Done 22-23 14-15 0x000030-0x000032 0x000130-0x000132 Reserved 24 16 0x000034 0x000134 SI2C1 – I2C1 Slave Event 25 17 0x000036 0x000136 MI2C1 – I2C1 Master Event 26 18 0x000038 0x000138 CMP1 – Analog Comparator 1 Interrupt 27 19 0x00003A 0x00013A CN – Input Change Notification Interrupt 28 20 0x00003C 0x00013C INT1 – External Interrupt 1 29-36 21-28 0x00003E-0x00004C 0x00013E-0x00014C Reserved 37 29 0x00004E 0x00014E INT2 – External Interrupt 2 38-64 30-56 0x000050-0x000084 0x000150-0x000184 Reserved 65 57 0x000086 0x000186 PWM PSEM Special Event Match 66-72 58-64 0x000088-0x000094 0x000188-0x000194 Reserved 73 65 0x000096 0x000196 U1E – UART1 Error Interrupt 74-101 66-93 0x000098-0x0000CE 0x000198-0x0001CE Reserved 102 94 0x0000D0 0x0001D0 PWM1 – PWM1 Interrupt 103 95 0x0000D2 0x0001D2 PWM2 – PWM2 Interrupt 104 96 0x0000D4 0x0001D4 PWM3 – PWM3 Interrupt 105 97 0x0000D6 0x0001D6 PWM4 – PWM4 Interrupt 106-110 98-102 0x0000D8-0x0000E0 0x0001D8-0x0001E0 Reserved 111 103 0x0000E2 0x00001E2 CMP2 – Analog Comparator 2 112 104 0x0000E4 0x0001E4 CMP3 – Analog Comparator 3 113 105 0x0000E6 0x0001E6 CMP4 – Analog Comparator 4 114-117 106-109 0x0000E8-0x0000EE 0x0001E8-0x0001EE Reserved 118 110 0x0000F0 0x0001F0 ADC Pair 0 Convert Done 119 111 0x0000F2 0x0001F2 ADC Pair 1 Convert Done 120 112 0x0000F4 0x0001F4 ADC Pair 2 Convert Done 121 113 0x0000F6 0x0001F6 ADC Pair 3 Convert Done 122 114 0x0000F8 0x0001F8 ADC Pair 4 Convert Done 123 115 0x0000FA 0x0001FA ADC Pair 5 Convert Done 124 116 0x0000FC 0x0001FC ADC Pair 6 Convert Done 125 117 0x0000FE 0x0001FE Reserved Lowest Natural Order Priority  2008-2014 Microchip Technology Inc. DS70000318G-page 99

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 7.3 Interrupt Control and Status 7.3.5 INTTREG Registers The INTTREG register contains the associated interrupt vector number and the new CPU Interrupt Pri- The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ ority Level, which are latched into the Vector Number X04 devices implement 27 registers for the interrupt (VECNUM<6:0>) and Interrupt Level (ILR<3:0>) bit controller: fields in the INTTREG register. The new Interrupt • INTCON1 Priority Level is the priority of the pending interrupt. • INTCON2 The interrupt sources are assigned to the IFSx, IECx • IFSx and IPCx registers in the same sequence that they are • IECx listed in Table7-1. For example, the INT0 (External • IPCx Interrupt 0) is shown as having Vector Number 8 and a • INTTREG natural order priority of 0. Thus, the INT0IF bit is found 7.3.1 INTCON1 AND INTCON2 in IFS0<0>, the INT0IE bit is found in IEC0<0> and the INT0IP bits are found in the first position of IPC0 Global interrupt control functions are controlled from (IPC0<2:0>). INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the 7.3.6 STATUS/CONTROL REGISTERS control and status flags for the processor trap sources. Although they are not specifically part of the interrupt The INTCON2 register controls the external interrupt control hardware, two of the CPU Control registers request signal behavior and the use of the Alternate contain bits that control interrupt functionality. Interrupt Vector Table. • The CPU STATUS Register, SR, contains the 7.3.2 IFSx IPL<2:0> bits (SR<7:5>). These bits indicate the current CPU Interrupt Priority Level. The user can The IFSx registers maintain all of the interrupt request change the current CPU priority level by writing to flags. Each source of interrupt has a status bit, which is the IPL bits. set by the respective peripherals or external signal and is cleared via software. • The CORCON register contains the IPL3 bit, which together with IPL<2:0>, indicates the 7.3.3 IECx current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user The IECx registers maintain all of the interrupt enable software. bits. These control bits are used to individually enable interrupts from the peripherals or external signals. All Interrupt registers are described in Register7-1 through Register7-35 in the following pages. 7.3.4 IPCx The IPCx registers are used to set the Interrupt Priority Level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. DS70000318G-page 100  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-1: SR: CPU STATUS REGISTER(1) R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: For complete register details, see Register3-1. 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> status bits are read-only when NSTDIS (INTCON1<15>) = 1. REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT DL2 DL1 DL0 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less Note 1: For complete register details, see Register3-2. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.  2008-2014 Microchip Technology Inc. DS70000318G-page 101

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14 OVAERR: Accumulator A Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A bit 13 OVBERR: Accumulator B Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B bit 10 OVATE: Accumulator A Overflow Trap Enable bit 1 = Trap overflow of Accumulator A 0 = Trap is disabled bit 9 OVBTE: Accumulator B Overflow Trap Enable bit 1 = Trap overflow of Accumulator B 0 = Trap is disabled bit 8 COVTE: Catastrophic Overflow Trap Enable bit 1 = Trap on catastrophic overflow of Accumulator A or B enabled 0 = Trap is disabled bit 7 SFTACERR: Shift Accumulator Error Status bit 1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift bit 6 DIV0ERR: Arithmetic Error Status bit 1 = Math error trap was caused by a divide-by-zero 0 = Math error trap was not caused by a divide-by-zero bit 5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred DS70000318G-page 102  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’  2008-2014 Microchip Technology Inc. DS70000318G-page 103

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table 0 = Use standard (default) vector table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-3 Unimplemented: Read as ‘0’ bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge DS70000318G-page 104  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 7-5: IFS0: INTERRUPT FLAG STATUS R EGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ADIF: ADC Group Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 SPI1EIF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 Unimplemented: Read as ‘0’ bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2008-2014 Microchip Technology Inc. DS70000318G-page 105

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70000318G-page 106  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — INT2IF — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 AC1IF: Analog Comparator 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2008-2014 Microchip Technology Inc. DS70000318G-page 107

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-7: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — PSEMIF — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9 PSEMIF: PWM Special Event Match Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’ REGISTER 7-8: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — U1EIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ DS70000318G-page 108  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-9: IFS5: INTERRUPT FLAG STATUS REGISTER 5 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 PWM2IF PWM1IF — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWM2IF: PWM2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 PWM1IF: PWM1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-0 Unimplemented: Read as ‘0’  2008-2014 Microchip Technology Inc. DS70000318G-page 109

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-10: IFS6: INTERRUPT FLAG STATUS REGISTER 6 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 ADCP1IF ADCP0IF — — — — AC4IF AC3IF bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 AC2IF — — — — — PWM4IF PWM3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 ADCP0IF: ADC Pair 0 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-10 Unimplemented: Read as ‘0’ bit 9 AC4IF: Analog Comparator 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 AC3IF: Analog Comparator 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 AC2IF: Analog Comparator 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6-2 Unimplemented: Read as ‘0’ bit 1 PWM4IF: PWM4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 PWM3IF: PWM3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70000318G-page 110  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-11: IFS7: INTERRUPT FLAG STATUS REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 ADCP6IF: ADC Pair 6 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 ADCP5IF: ADC Pair 5 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 ADCP4IF: ADC Pair 4 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 ADCP3IF: ADC Pair 3 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 ADCP2IF: ADC Pair 2 Conversion Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2008-2014 Microchip Technology Inc. DS70000318G-page 111

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 7-12: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ADIE: ADC1 Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 SPI1IE: SPI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 SPI1EIE: SPI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 Unimplemented: Read as ‘0’ bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70000318G-page 112  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-12: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled  2008-2014 Microchip Technology Inc. DS70000318G-page 113

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-13: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — INT2IE — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12-5 Unimplemented: Read as ‘0’ bit 4 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 AC1IE: Analog Comparator 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70000318G-page 114  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — PSEMIE — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9 PSEMIE: PWM Special Event Match Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8-0 Unimplemented: Read as ‘0’ REGISTER 7-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — U1EIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’  2008-2014 Microchip Technology Inc. DS70000318G-page 115

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 PWM2IE PWM1IE — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWM2IE: PWM2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 PWM1IE: PWM1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13-0 Unimplemented: Read as ‘0’ DS70000318G-page 116  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-17: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 ADCP1IE ADCP0IE — — — — AC4IE AC3IE bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 AC2IE — — — — — PWM4IE PWM3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADCP1IE: ADC Pair 1 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 ADCP0IE: ADC Pair 0 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13-10 Unimplemented: Read as ‘0 bit 9 AC4IE: Analog Comparator 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 AC3IE: Analog Comparator 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 AC2IE: Analog Comparator 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6-2 Unimplemented: Read as ‘0’ bit 1 PWM4IE: PWM4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 PWM3IE: PWM3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2008-2014 Microchip Technology Inc. DS70000318G-page 117

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-18: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 ADCP6IE: ADC Pair 6 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 ADCP5IE: ADC Pair 5 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 ADCP4IE: ADC Pair 4 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 ADCP3IE: ADC Pair 3 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 ADCP2IE: ADC Pair 2 Conversion Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS70000318G-page 118  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-19: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2008-2014 Microchip Technology Inc. DS70000318G-page 119

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-20: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC2IP2 IC2IP1 IC2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70000318G-page 120  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-21: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2008-2014 Microchip Technology Inc. DS70000318G-page 121

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-22: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADIP2 ADIP1 ADIP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ADIP<2:0>: ADC1 Conversion Complete Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS70000318G-page 122  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-23: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 AC1IP<2:0>: Analog Comparator 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2008-2014 Microchip Technology Inc. DS70000318G-page 123

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-24: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled REGISTER 7-25: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT2IP2 INT2IP1 INT2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70000318G-page 124  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-26: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — PSEMIP2 PSEMIP1 PSEMIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PSEMIP<2:0>: PWM Special Event Match Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ REGISTER 7-27: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1EIP2 U1EIP1 U1EIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2008-2014 Microchip Technology Inc. DS70000318G-page 125

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-28: IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 PWM2IP<2:0>: PWM2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ DS70000318G-page 126  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-29: IPC24: INTERRUPT PRIORITY CONTROL REGISTER 24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PWM4IP<2:0>: PWM4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 PWM3IP<2:0>: PWM3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2008-2014 Microchip Technology Inc. DS70000318G-page 127

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-30: IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — AC2IP2 AC2IP1 AC2IP0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 AC2IP<2:0>: Analog Comparator 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-01 Unimplemented: Read as ‘0’ DS70000318G-page 128  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-31: IPC26: INTERRUPT PRIORITY CONTROL REGISTER 26 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AC4IP<2:0>: Analog Comparator 4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 AC3IP<2:0>: Analog Comparator 3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2008-2014 Microchip Technology Inc. DS70000318G-page 129

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-32: IPC27: INTERRUPT PRIORITY CONTROL REGISTER 27 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADCP1IP2 ADCP1IP1 ADCP1IP0 — ADCP0IP2 ADCP0IP1 ADCP0IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP1IP<2:0>: ADC Pair 1 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 ADCP0IP<2:0>: ADC Pair 0 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ DS70000318G-page 130  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-33: IPC28: INTERRUPT PRIORITY CONTROL REGISTER 28 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADCP5IP2 ADCP5IP1 ADCP5IP0 — ADCP4IP2 ADCP4IP1 ADCP4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — ADCP3IP2 ADCP3IP1 ADCP3IP0 — ADCP2IP2 ADCP2IP1 ADCP2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP5IP<2:0>: ADC Pair 5 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 ADCP4IP<2:0>: ADC Pair 4 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCP3IP<2:0>: ADC Pair 3 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 ADCP2IP<2:0>: ADC Pair 2 Conversion Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2008-2014 Microchip Technology Inc. DS70000318G-page 131

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-34: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — ADCP6IP2 ADCP6IP1 ADCP6IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 ADCP6IP<2:0>: ADC Pair 6 Conversion Done Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS70000318G-page 132  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-35: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt vector pending is Number 135 • • • 0000001 = Interrupt vector pending is Number 9 0000000 = Interrupt vector pending is Number 8  2008-2014 Microchip Technology Inc. DS70000318G-page 133

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 7.4 Interrupt Setup Procedures 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, 7.4.1 INITIALIZATION except that the appropriate trap status flag in the Complete the following steps to configure an interrupt INTCON1 register must be cleared to avoid re-entry source at initialization: into the TSR. 1. Set the NSTDIS bit (INTCON1<15>) if nested 7.4.4 INTERRUPT DISABLE interrupts are not desired. 2. Select the user-assigned priority level for the The following steps outline the procedure to disable all user interrupts: interrupt source by writing the control bits in the appropriate IPCx register. The priority level will 1. Push the current SR value onto the software depend on the specific application and type of stack using the PUSH instruction. interrupt source. If multiple priority levels are not 2. Force the CPU to Priority Level 7 by inclusive desired, the IPCx register control bits for all ORing the value 0xE0 with SRL. enabled interrupt sources can be programmed To enable user interrupts, the POP instruction can be to the same non-zero value. used to restore the previous SR value. Note: At a device Reset, the IPCx registers are initialized such that all user interrupt Note: Only user interrupts with a priority level of7 sources are assigned to Priority Level 4. or lower can be disabled. Trap sources (level 8-level 15) cannot be disabled. 3. Clear the interrupt flag status bit associated with The DISI instruction provides a convenient way to the peripheral in the associated IFSx register. disable interrupts of Priority Levels 1-6 for a fixed 4. Enable the interrupt source by setting the period of time. Level 7 interrupt sources are not interrupt enable control bit associated with the disabled by the DISI instruction. source in the appropriate IECx register. 7.4.2 INTERRUPT SERVICE ROUTINE The method used to declare an ISR and initialize the IVT with the correct vector address depends on the programming language (C or assembler) and the language development toolsuite used to develop the application. In general, the user application must clear the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, program will re-enter the ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. DS70000318G-page 134  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.0 OSCILLATOR CONFIGURATION The oscillator system provides: • External and internal oscillator options as Note 1: This data sheet summarizes the features clock sources of the dsPIC33FJ06GS101/X02 and • An on-chip Phase-Locked Loop (PLL) to scale the dsPIC33FJ16GSX02/X04 families of internal operating frequency to the required system devices. It is not intended to be a compre- clock frequency hensive reference source. To complement • An internal FRC oscillator that can also be used with the information in this data sheet, refer to the PLL, thereby allowing full-speed operation “Oscillator (Part IV)” (DS70307) in the without any external clock generation hardware “dsPIC33F/PIC24H Family Reference • Clock switching between various clock sources Manual”, which is available from the • Programmable clock postscaler for system power Microchip web site (www.microchip.com). savings 2: Some registers and associated bits • A Fail-Safe Clock Monitor (FSCM) that detects clock described in this section may not be failure and takes fail-safe measures available on all devices. Refer to • A Clock Control register (OSCCON) Section4.0 “Memory Organization” in • Nonvolatile Configuration bits for main oscillator this data sheet for device-specific register selection and bit information. • Auxiliary PLL for ADC and PWM A simplified diagram of the oscillator system is shown in Figure8-1. FIGURE 8-1: OSCILLATOR SYSTEM DIAGRAM Primary Oscillator DOZE<2:0> OSC1 POSCCLK XT, HS, EC S2 S3 XTPLL, HSPLL, R(2) S1 PLL(1) FEVCCPOL(1L), FRCPLL S1/S3 OZE FCY(3) D OSC2 POSCMD<1:0> FP(3) V FRC FRCCLK DI FRCDIVN Oscillator C S7 ÷ 2 R F FOSC FRCDIV<2:0> TUN<5:0> FRCDIV16 ÷ 16 S6 FRC S0 LPRC LPRC S5 Oscillator Reference Clock Generation POSCCLK Clock Fail Clock Switch Reset REFCLKO ÷ N FOSC RPx S7 NOSC<2:0> FNOSC<2:0> ROSEL RODIV<3:0> WDT, PWRT, FSCM Auxiliary Clock Generation POSCCLK FRCCLK APLL(1) FVCO(1) ACLK To PWM/ADC(1) x16 ÷ N ASRCSEL FRCSEL ENAPLL SELACLK APSTSCLR<2:0> Note 1: See Section8.1.3 “PLL Configuration” and Section8.2 “Auxiliary Clock Generation” for configuration restrictions. 2: If the oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 M must be connected. 3: The term, FP, refers to the clock source for all the peripherals, while FCY refers to the clock source for the CPU. Throughout this doc- ument, FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode is used in any ratio other than 1:1, which is the default.  2008-2014 Microchip Technology Inc. DS70000318G-page 135

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.1 CPU Clocking System output frequencies for device operation. PLL configuration is described in Section8.1.3 “PLL The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ Configuration”. X04 devices provide six system clock options: The FRC frequency depends on the FRC accuracy • Fast RC (FRC) Oscillator (see Table24-20) and the value of the FRC Oscillator • FRC Oscillator with PLL Tuning register (see Register8-4). • Primary (XT, HS or EC) Oscillator • Primary Oscillator with PLL 8.1.2 SYSTEM CLOCK SELECTION • Low-Power RC (LPRC) Oscillator The oscillator source used at a device Power-on • FRC Oscillator with Postscaler Reset event is selected using Configuration bit 8.1.1 SYSTEM CLOCK SOURCES settings. The Oscillator Configuration bit settings are located in the Configuration registers in the program The Fast RC (FRC) internal oscillator runs at a nominal memory. (Refer to Section21.1 “Configuration Bits” frequency of 7.37 MHz. User software can tune the for further details.) The Initial Oscillator Selection Con- FRC frequency. User software can optionally specify a figuration bits, FNOSC<2:0> (FOSCSEL<2:0>), and the factor (ranging from 1:2 to 1:256) by which the FRC Primary Oscillator Mode Select Configuration bits, clock frequency is divided. This factor is selected using POSCMD<1:0> (FOSC<1:0>), select the oscillator the FRCDIV<2:0> (CLKDIV<10:8>) bits. source that is used at a Power-on Reset. The FRC The primary oscillator can use one of the following as primary oscillator is the default (unprogrammed) its clock source: selection. • XT (Crystal): Crystals and ceramic resonators in The Configuration bits allow users to choose among the range of 3 MHz to 10 MHz. The crystal is 12different clock modes, shown in Table8-1. connected to the OSC1 and OSC2 pins. The output of the oscillator (or the output of the PLL if • HS (High-Speed Crystal): Crystals in the range of a PLL mode has been selected), FOSC, is divided by 2 10 MHz to 40 MHz. The crystal is connected to to generate the device instruction clock (FCY) and the the OSC1 and OSC2 pins. peripheral clock time base (FP). FCY defines the • EC (External Clock): The external clock signal is operating speed of the device and speeds up to directly applied to the OSC1 pin. 40MHz are supported by the dsPIC33FJ06GS101/ X02 and dsPIC33FJ16GSX02/X04 architecture. The LPRC internal oscIllator runs at a nominal frequency of 32.768 kHz. It is also used as a reference Instruction execution speed or device operating clock by the Watchdog Timer (WDT) and Fail-Safe frequency, FCY, is given by Equation8-1. Clock Monitor (FSCM). EQUATION 8-1: DEVICE OPERATING The clock signals generated by the FRC and primary FREQUENCY oscillators can be optionally applied to an on-chip Phase-Locked Loop (PLL) to provide a wide range of FCY = FOSC/2 TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> See Notes Fast RC Oscillator with Divide-by-N (FRCDIVN) Internal xx 111 1, 2 Fast RC Oscillator with Divide-by-16 (FRCDIV16) Internal xx 110 1 Low-Power RC Oscillator (LPRC) Internal xx 101 1 Reserved Reserved xx 100 — Primary Oscillator (HS) with PLL (HSPLL) Primary 10 011 — Primary Oscillator (XT) with PLL (XTPLL) Primary 01 011 — Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1 Primary Oscillator (HS) Primary 10 010 — Primary Oscillator (XT) Primary 01 010 — Primary Oscillator (EC) Primary 00 010 1 Fast RC Oscillator with PLL (FRCPLL) Internal xx 001 1 Fast RC Oscillator (FRC) Internal xx 000 1 Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. DS70000318G-page 136  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.1.3 PLL CONFIGURATION For a primary oscillator or FRC oscillator, output ‘FIN’, the PLL output ‘FOSC’ is given by Equation8-2. The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in EQUATION 8-2: FOSC CALCULATION selecting the device operating speed. A block diagram ( M ) of the PLL is shown in Figure8-2. FOSC = FIN * N1*N2 The output of the primary oscillator or FRC, denoted For example, suppose a 10 MHz crystal is being used as ‘FIN’, is divided down by a prescale factor (N1) of 2, with the selected oscillator mode of XT with PLL (see 3, ... or 33 before being provided to the PLL’s Voltage Equation8-3). Controlled Oscillator (VCO). The input to the VCO must be selected in the range of 0.8 MHz to 8 MHz. • If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO input of 10/2 = 5 MHz, which is within the The prescale factor ‘N1’ is selected using the acceptable range of 0.8-8 MHz. PLLPRE<4:0> bits (CLKDIV<4:0>). • If PLLDIV<8:0> = 0x1E, then M = 32. This yields a The PLL Feedback Divisor, selected using the VCO output of 5 x 32 = 160 MHz, which is within PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor, ‘M’, the 100-200 MHz ranged needed. by which the input to the VCO is multiplied. This factor must be selected such that the resulting VCO output • If PLLPOST<1:0> = 0, then N2 = 2. This provides a Fosc of 160/2 = 80 MHz. The resultant device frequency is in the range of 100 MHz to 200 MHz. operating speed is 80/2 = 40 MIPS. The VCO output is further divided by a postscale factor, ‘N2’. This factor is selected using the PLLPOST<1:0> EQUATION 8-3: XT WITH PLL MODE bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4, or 8, and EXAMPLE must be selected such that the PLL output frequency (FOSC) is in the range of 12.5 MHz to 80 MHz, which FCY = FOSC = 1 (10000000 * 32)= 40 MIPS generates device operating speeds of 6.25-40 MIPS. 2 2 2 * 2 FIGURE 8-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PLL BLOCK DIAGRAM FVCO 0.8-8.0 MHz 100-200 MHz 12.5-80 MHz Here(1) Here(1) Here(1) Source (Crystal, External Clock or Internal RC) PLLPRE X VCO PLLPOST FOSC PLLDIV N2 N1 Divide-by- Divide-by- 2, 4, 8 2-33 M Divide-by- 2-513 Note1: This frequency range must be satisfied at all times.  2008-2014 Microchip Technology Inc. DS70000318G-page 137

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.2 Auxiliary Clock Generation 8.3 Reference Clock Generation The auxiliary clock generation is used for a peripherals The reference clock output logic provides the user with that need to operate at a frequency unrelated to the the ability to output a clock signal based on the system system clock such as a PWM or ADC. clock or the crystal oscillator on a device pin. The user application can specify a wide range of clock scaling The primary oscillator and internal FRC oscillator prior to outputting the reference clock. sources can be used with an auxiliary PLL to obtain the auxiliary clock. The auxiliary PLL has a fixed 16x multiplication factor. The auxiliary clock has the following configuration restrictions: • For proper PWM operation, auxiliary clock genera- tion must be configured for 120 MHz (see Parameter OS56 in Table24-18 in Section24.0 “Electrical Characteristics”). If a slower frequency is desired, the PWM Input Clock Prescaler (Divider) Select bits (PCLKDIV<2:0>) should be used. • To achieve 1.04 ns PWM resolution, the auxiliary clock must use the 16x auxiliary PLL (APLL). All other clock sources will have a minimum PWM resolution of 8 ns. • If the primary PLL is used as a source for the auxiliary clock, the primary PLL should be config- ured up to a maximum operation of 30 MIPS or less DS70000318G-page 138  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.4 Oscillator Control Registers REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,2) U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y — COSC2 COSC1 COSC0 — NOSC2(3) NOSC1(3) NOSC0(3) bit 15 bit 8 R/W-0 R/W-0 R-0 U-0 R/C-0 U-0 U-0 R/W-0 CLKLOCK IOLOCK LOCK — CF — — OSWEN bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only) 111 = Fast RC oscillator (FRC) with divide-by-n 110 = Fast RC oscillator (FRC) with divide-by-16 101 = Low-Power RC oscillator (LPRC) 100 = Reserved 011 = Primary oscillator (XT, HS, EC) with PLL 010 = Primary oscillator (XT, HS, EC) 001 = Fast RC oscillator (FRC) with PLL 000 = Fast RC oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits(3) 111 = Fast RC oscillator (FRC) with divide-by-n 110 = Fast RC oscillator (FRC) with divide-by-16 101 = Low-Power RC oscillator (LPRC) 100 = Reserved 011 = Primary oscillator (XT, HS, EC) with PLL 010 = Primary oscillator (XT, HS, EC) 001 = Fast RC oscillator (FRC) with PLL 000 = Fast RC oscillator (FRC) bit 7 CLKLOCK: Clock Lock Enable bit If Clock Switching is Enabled and FSCM is Disabled, (FOSC<FCKSM> = 0b01): 1 = Clock switching is disabled, system clock source is locked 0 = Clock switching is enabled, system clock source can be modified by clock switching bit 6 IOLOCK: Peripheral Pin Select Lock bit 1 = Peripheral Pin Select is locked, write to Peripheral Pin Select registers not allowed 0 = Peripheral Pin Select is not locked, write to Peripheral Pin Select registers allowed bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled bit 4 Unimplemented: Read as ‘0’ Note 1: Writes to this register require an unlock sequence. Refer to “Oscillator (Part IV)” (DS70307) in the “dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip web site) for details. 2: This register is reset only on a Power-on Reset (POR). 3: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.  2008-2014 Microchip Technology Inc. DS70000318G-page 139

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,2) (CONTINUED) bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2-1 Unimplemented: Read as ‘0’ bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Writes to this register require an unlock sequence. Refer to “Oscillator (Part IV)” (DS70307) in the “dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip web site) for details. 2: This register is reset only on a Power-on Reset (POR). 3: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. DS70000318G-page 140  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER(1) R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 ROI DOZE2 DOZE1 DOZE0 DOZEN(2) FRCDIV2 FRCDIV1 FRCDIV0 bit 15 bit 8 R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PLLPOST1 PLLPOST0 — PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits 111 = FCY/128 110 = FCY/64 101 = FCY/32 100 = FCY/16 011 = FCY/8 (default) 010 = FCY/4 001 = FCY/2 000 = FCY/1 bit 11 DOZEN: Doze Mode Enable bit(2) 1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock/peripheral clock ratio forced to 1:1 bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits 111 = FRC divide-by-256 110 = FRC divide-by-64 101 = FRC divide-by-32 100 = FRC divide-by-16 011 = FRC divide-by-8 010 = FRC divide-by-4 001 = FRC divide-by-2 000 = FRC divide-by-1 (default) bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler) 11 = Output/8 10 = Reserved 01 = Output/4 (default) 00 = Output/2 bit 5 Unimplemented: Read as ‘0’ bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 11111 = Input/33 • • • 00001 = Input/3 00000 = Input/2 (default) Note 1: This register is reset only on a Power-on Reset (POR). 2: This bit is cleared when the ROI bit is set and an interrupt occurs.  2008-2014 Microchip Technology Inc. DS70000318G-page 141

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV<8> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 111111111 = 513 • • • 000110000 = 50 (default) • • • 000000010 = 4 000000001 = 3 000000000 = 2 Note 1: This register is reset only on a Power-on Reset (POR). DS70000318G-page 142  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN<5:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(2) 011111 = Center frequency + 11.6% (8.2268 MHz) 011110 = Center frequency + 11.2% (8.1992 MHz) • • • 000001 = Center frequency + 0.375% (7.3976 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency – 0.375% (7.2594 MHz) • • • 100001 = Center frequency – 11.6% (6.5132 MHz) 000000 = Center frequency – 12% (6.4856 MHz) Note 1: This register is reset only on a Power-on Reset (POR). 2: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step-size is an approximation and is neither characterized nor tested.  2008-2014 Microchip Technology Inc. DS70000318G-page 143

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-5: ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER(1) R/W-0 R-0 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 ENAPLL APLLCK SELACLK — — APSTSCLR2 APSTSCLR1 APSTSCLR0 bit 15 bit 0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ASRCSEL FRCSEL — — — — — — bit 7 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ENAPLL: Auxiliary PLL Enable bit 1 = APLL is enabled 0 = APLL is disabled bit 14 APLLCK: APLL Locked Status bit (read-only) 1 = Indicates that auxiliary PLL is in lock 0 = Indicates that auxiliary PLL is not in lock bit 13 SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit 1 = Auxiliary oscillators provides the source clock for auxiliary clock divider 0 = Primary PLL (FVCO) provides the source clock for auxiliary clock divider bit 12-11 Unimplemented: Read as ‘0’ bit 10-8 APSTSCLR<2:0>: Auxiliary Clock Output Divider bits 111 = Divided by 1 110 = Divided by 2 101 = Divided by 4 100 = Divided by 8 011 = Divided by 16 010 = Divided by 32 001 = Divided by 64 000 = Divided by 256 bit 7 ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit 1 = Primary oscillator is the clock source 0 = No clock input is selected bit 6 FRCSEL: Select Reference Clock Source for Auxiliary PLL bit 1 = Select FRC clock for auxiliary PLL 0 = Input clock source is determined by ASRCSEL bit setting bit 5-0 Unimplemented: Read as ‘0’ Note 1: This register is reset only on a Power-on Reset (POR). DS70000318G-page 144  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-6: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROON — ROSSLP ROSEL RODIV3(1) RODIV2(1) RODIV1(1) RODIV0(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator output is enabled on the REFCLK0 pin(2) 0 = Reference oscillator output is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ROSSLP: Reference Oscillator Run in Sleep bit 1 = Reference oscillator output continues to run in Sleep 0 = Reference oscillator output is disabled in Sleep bit 12 ROSEL: Reference Oscillator Source Select bit 1 = Oscillator crystal is used as the reference clock 0 = System clock is used as the reference clock bit 11-8 RODIV<3:0>: Reference Oscillator Divider bits(1) 1111 = Reference clock divided by 32,768 1110 = Reference clock divided by 16,384 1101 = Reference clock divided by 8,192 1100 = Reference clock divided by 4,096 1011 = Reference clock divided by 2,048 1010 = Reference clock divided by 1,024 1001 = Reference clock divided by 512 1000 = Reference clock divided by 256 0111 = Reference clock divided by 128 0110 = Reference clock divided by 64 0101 = Reference clock divided by 32 0100 = Reference clock divided by 16 0011 = Reference clock divided by 8 0010 = Reference clock divided by 4 0001 = Reference clock divided by 2 0000 = Reference clock bit 7-0 Unimplemented: Read as ‘0’ Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits. 2: This pin is remappable. Refer to Section10.6 “Peripheral Pin Select” for more information.  2008-2014 Microchip Technology Inc. DS70000318G-page 145

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.5 Clock Switching Operation 2. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and the CF (OSCCON<3>) status Users can switch applications among any of the four bits are cleared. clock sources (primary, LP, FRC and LPRC) under 3. The new oscillator is turned on by the hardware if software control at any time. To limit the possible side it is not currently running. If a crystal oscillator effects of this flexibility, dsPIC33FJ06GS101/X02 and must be turned on, the hardware waits until the dsPIC33FJ16GSX02/X04 devices have a safeguard Oscillator Start-up Timer (OST) expires. If the new lock built into the switch process. source is using the PLL, the hardware waits until a Note: Primary oscillator mode has three different PLL lock is detected (LOCK = 1). submodes (XT, HS and EC), which are 4. The hardware waits for 10 clock cycles from the determined by the POSCMD<1:0> new clock source and then performs the clock Configuration bits. While an application switch. can switch to and from primary oscillator 5. The hardware clears the OSWEN bit to indicate a mode in software, it cannot switch among successful clock transition. In addition, the the different primary submodes without NOSC<2:0> bit values are transferred to the reprogramming the device. COSC<2:0> status bits. 6. The old clock source is turned off at this time, with 8.5.1 ENABLING CLOCK SWITCHING the exception of LPRC (if WDT or FSCM are To enable clock switching, the FCKSM1 Configuration enabled). bit in the Configuration register must be programmed to Note1: The processor continues to execute code ‘0’. (Refer to Section21.1 “Configuration Bits” for throughout the clock switching sequence. further details.) If the FCKSM1 Configuration bit is Timing-sensitive code should not be unprogrammed (‘1’), the clock switching function and executed during this time. Fail-Safe Clock Monitor function are disabled. This is the default setting. 2: Direct clock switches between any pri- mary oscillator mode with PLL and The NOSC<2:0> control bits (OSCCON<10:8>) do FRCPLL mode are not permitted. This not control the clock selection when clock switching applies to clock switches in either direc- is disabled. However, the COSC<2:0> bits tion. In these instances, the application (OSCCON<14:12>) reflect the clock source selected by must switch to FRC mode as a transition the FNOSCx Configuration bits. clock source between the two PLL modes. The OSWEN control bit (OSCCON<0>) has no effect 3: Refer to “Oscillator (Part IV)” when clock switching is disabled. It is held at ‘0’ at all (DS70307) in the “dsPIC33F/PIC24H times. Family Reference Manual” for details. 8.5.2 OSCILLATOR SWITCHING SEQUENCE 8.6 Fail-Safe Clock Monitor (FSCM) To perform a clock switch, the following basic sequence is required: The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator 1. If required, read the COSC<2:0> bits to determine failure. The FSCM function is enabled by programming. the current oscillator source. If the FSCM function is enabled, the LPRC internal 2. Perform the unlock sequence to allow a write to oscillator runs at all times (except during Sleep mode) the OSCCON register high byte. and is not subject to control by the Watchdog Timer. 3. Write the appropriate value to the NOSC<2:0> During an oscillator failure, the FSCM generates a control bits for the new oscillator source. clock failure trap event and switches the system clock 4. Perform the unlock sequence to allow a write to over to the FRC oscillator. Then, the application the OSCCON register low byte. program can either attempt to restart the oscillator or 5. Set the OSWEN bit to initiate the oscillator switch. execute a controlled shutdown. The trap can be treated as a Warm Reset by simply loading the Reset address After the basic sequence is completed, the system into the oscillator fail trap vector. clock hardware responds as follows: If the PLL multiplier is used to scale the system clock, 1. The clock switching hardware compares the the internal FRC is also multiplied by the same factor COSC<2:0> status bits with the new value of the on clock failure. Essentially, the device switches to NOSC<2:0> control bits. If they are the same, FRC with PLL on a clock failure. the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. DS70000318G-page 146  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 9.0 POWER-SAVING FEATURES 9.2 Instruction-Based Power-Saving Modes Note1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ dsPIC33FJ16GSX02/X04 families of X04 devices have two special power-saving modes that devices. It is not intended to be a are entered through the execution of a special PWRSAV comprehensive reference source. To instruction. Sleep mode stops clock operation and halts all complement the information in this data code execution. Idle mode halts the CPU and code sheet, refer to “Watchdog Timer and execution, but allows peripheral modules to continue Power-Saving Modes” (DS70196) in operation. The assembler syntax of the PWRSAV the “dsPIC33F/PIC24H Family Reference instruction is shown in Example9-1. Manual”, which is available from the Note: SLEEP_MODE and IDLE_MODE are Microchip web site (www.microchip.com). constants defined in the assembler 2: Some registers and associated bits include file for the selected device. described in this section may not be Sleep and Idle modes can be exited as a result of an available on all devices. Refer to enabled interrupt, WDT time-out or a device Reset. When Section4.0 “Memory Organization” in the device exits these modes, it is said to wake-up. this data sheet for device-specific register and bit information. 9.2.1 SLEEP MODE The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ The following occur in Sleep mode: X04 devices provide the ability to manage power • The system clock source is shut down. If an consumption by selectively managing clocking to the on-chip oscillator is used, it is turned off CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits • The device current consumption is reduced to a being clocked constitutes lower consumed power. minimum, provided that no I/O pin is sourcing dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ current X04 devices can manage power consumption in four • The Fail-Safe Clock Monitor does not operate, different ways: since the system clock source is disabled • Clock Frequency • The LPRC clock continues to run in Sleep mode if • Instruction-Based Sleep and Idle modes the WDT is enabled • Software-Controlled Doze mode • The WDT, if enabled, is automatically cleared • Selective Peripheral Control in Software prior to entering Sleep mode Combinations of these methods can be used to • Some device features or peripherals may continue selectively tailor an application’s power consumption to operate. This includes the items such as the while still maintaining critical application features, such Input Change Notification on the I/O ports or as timing-sensitive communications. peripherals that use an external clock input. • Any peripheral that requires the system clock 9.1 Clock Frequency and Clock source for its operation is disabled Switching The device will wake-up from Sleep mode on any of these events: The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ • Any interrupt source that is individually enabled X04 devices allow a wide range of clock frequencies to • Any form of device Reset be selected under application control. If the system • A WDT time-out clock configuration is not locked, users can choose low-power or high-precision oscillators by simply On wake-up from Sleep mode, the processor restarts changing the NOSC<2:0> bits (OSCCON<10:8>). with the same clock source that was active when Sleep The process of changing a system clock during mode was entered. operation, as well as limitations to the process, are discussed in more detail in Section8.0 “Oscillator Configuration”. EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode  2008-2014 Microchip Technology Inc. DS70000318G-page 147

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 9.2.2 IDLE MODE Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core The following occur in Idle mode: clock speed is determined by the DOZE<2:0> bits • The CPU stops executing instructions (CLKDIV<14:12>). There are eight possible configura- • The WDT is automatically cleared tions, from 1:1 to 1:128, with 1:1 being the default • The system clock source remains active. By setting. default, all peripheral modules continue to operate Programs can use Doze mode to selectively reduce normally from the system clock source, but can power consumption in event-driven applications. This also be selectively disabled (see Section9.4 allows clock-sensitive functions, such as synchronous “Peripheral Module Disable”). communications, to continue without interruption while • If the WDT or FSCM is enabled, the LPRC also the CPU idles, waiting for something to invoke an remains active interrupt routine. An automatic return to full-speed CPU operation on interrupts can be enabled by setting the The device will wake-up from Idle mode on any of these ROI bit (CLKDIV<15>). By default, interrupt events events: have no effect on Doze mode operation. • Any interrupt that is individually enabled For example, suppose the device is operating at • Any device Reset 20MIPS and the CAN module has been configured for • A WDT time-out 500 kbps based on this device operating speed. If the On wake-up from Idle mode, the clock is reapplied to device is placed in Doze mode with a clock frequency the CPU and instruction execution will begin (2-4 clock ratio of 1:4, the CAN module continues to communicate cycles later), starting with the instruction following the at the required bit rate of 500 kbps, but the CPU now PWRSAV instruction, or the first instruction in the ISR. starts executing instructions at a frequency of 5 MIPS. 9.2.3 INTERRUPTS COINCIDENT WITH 9.4 Peripheral Module Disable POWER SAVE INSTRUCTIONS Any interrupt that coincides with the execution of a The Peripheral Module Disable (PMD) registers PWRSAV instruction is held off until entry into Sleep or provide a method to disable a peripheral module by Idle mode has completed. The device then wakes up stopping all clock sources supplied to that module. from Sleep or Idle mode. When a peripheral is disabled using the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers 9.3 Doze Mode associated with the peripheral are also disabled, so The preferred strategies for reducing power writes to those registers will have no effect and read consumption are changing clock speed and invoking values will be invalid. one of the power-saving modes. In some A peripheral module is enabled only if both the circumstances, this may not be practical. For example, associated bit in the PMD register is cleared and the it may be necessary for an application to maintain peripheral is supported by the specific dsPIC® DSC uninterrupted synchronous communication, even while variant. If the peripheral is present in the device, it is it is doing nothing else. Reducing system clock speed enabled in the PMD register by default. can introduce communication errors, while using a power-saving mode can stop communications Note: If a PMD bit is set, the corresponding completely. module is disabled after a delay of one instruction cycle. Similarly, if a PMD bit is Doze mode is a simple and effective alternative method cleared, the corresponding module is to reduce power consumption while the device is still enabled after a delay of one instruction executing code. In this mode, the system clock cycle (assuming the module control regis- continues to operate from the same source and at the ters are already configured to enable same speed. Peripheral modules continue to be module operation). clocked at the same speed, while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. DS70000318G-page 148  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — — T3MD T2MD T1MD — PWMMD(1) — bit 15 bit 8 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 I2C1MD — U1MD — SPI1MD — — ADCMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 T3MD: Timer3 Module Disable bit 1 = Timer3 module is disabled 0 = Timer3 module is enabled bit 12 T2MD: Timer2 Module Disable bit 1 = Timer2 module is disabled 0 = Timer2 module is enabled bit 11 T1MD: Timer1 Module Disable bit 1 = Timer1 module is disabled 0 = Timer1 module is enabled bit 10 Unimplemented: Read as ‘0’ bit 9 PWMMD: PWM Module Disable bit(1) 1 = PWM module is disabled 0 = PWM module is enabled bit 8 Unimplemented: Read as ‘0’ bit 7 I2C1MD: I2C1 Module Disable bit 1 = I2C1 module is disabled 0 = I2C1 module is enabled bit 6 Unimplemented: Read as ‘0’ bit 5 U1MD: UART1 Module Disable bit 1 = UART1 module is disabled 0 = UART1 module is enabled bit 4 Unimplemented: Read as ‘0’ bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2-1 Unimplemented: Read as ‘0’ bit 0 ADCMD: ADC Module Disable bit 1 = ADC module is disabled 0 = ADC module is enabled Note 1: Once the PWM module is re-enabled (PWMMD is set to ‘1’ and then set to ‘0’), all PWM registers must be reinitialized.  2008-2014 Microchip Technology Inc. DS70000318G-page 149

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — IC2MD IC1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9 IC2MD: Input Capture 2 Module Disable bit 1 = Input Capture 2 module is disabled 0 = Input Capture 2 module is enabled bit 8 IC1MD: Input Capture 1 Module Disable bit 1 = Input Capture 1 module is disabled 0 = Input Capture 1 module is enabled bit 7-2 Unimplemented: Read as ‘0’ bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled DS70000318G-page 150  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 — — — — — CMPMD — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Analog Comparator Module Disable bit 1 = Analog comparator module is disabled 0 = Analog comparator module is enabled bit 9-0 Unimplemented: Read as ‘0’ REGISTER 9-4: PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 — — — — REFOMD — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 REFOMD: Reference Clock Generator Module Disable bit 1 = Reference clock generator module is disabled 0 = Reference clock generator module is enabled bit 2-0 Unimplemented: Read as ‘0’  2008-2014 Microchip Technology Inc. DS70000318G-page 151

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-5: PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — PWM4MD PWM3MD PWM2MD PWM1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11 PWM4MD: PWM Generator 4 Module Disable bit 1 = PWM Generator 4 module is disabled 0 = PWM Generator 4 module is enabled bit 10 PWM3MD: PWM Generator 3 Module Disable bit 1 = PWM Generator 3 module is disabled 0 = PWM Generator 3 module is enabled bit 9 PWM2MD: PWM Generator 2 Module Disable bit 1 = PWM Generator 2 module is disabled 0 = PWM Generator 2 module is enabled bit 8 PWM1MD: PWM Generator 1 Module Disable bit 1 = PWM Generator 1 module is disabled 0 = PWM Generator 1 module is enabled bit 7-0 Unimplemented: Read as ‘0’ DS70000318G-page 152  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-6: PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CMP4MD CMP3MD CMP2MD CMP1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11 CMP4MD: Analog Comparator 4 Module Disable bit 1 = Analog Comparator 4 module is disabled 0 = Analog Comparator 4 module is enabled bit 10 CMP3MD: Analog Comparator 3 Module Disable bit 1 = Analog Comparator 3 module is disabled 0 = Analog Comparator 3 module is enabled bit 9 CMP2MD: Analog Comparator 2 Module Disable bit 1 = Analog Comparator 2 module is disabled 0 = Analog Comparator 2 module is enabled bit 8 CMP1MD: Analog Comparator 1 Module Disable bit 1 = Analog Comparator 1 module is disabled 0 = Analog Comparator 1 module is enabled bit 7-0 Unimplemented: Read as ‘0’  2008-2014 Microchip Technology Inc. DS70000318G-page 153

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 154  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.0 I/O PORTS has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through”, in Note 1: This data sheet summarizes the features which a port’s digital output can drive the input of a of the dsPIC33FJ06GS101/X02 and peripheral that shares the same pin. Figure10-1 shows dsPIC33FJ16GSX02/X04 families of how ports are shared with other peripherals and the devices. It is not intended to be a compre- associated I/O pin to which they are connected. hensive reference source. To complement When a peripheral is enabled and the peripheral is the information in this data sheet, refer actively driving an associated pin, the use of the pin as a to “I/O Ports” (DS70193) in the general purpose output pin is disabled. The I/O pin can “dsPIC33F/PIC24H Family Reference be read, but the output driver for the parallel port bit is Manual”, which is available on Microchip disabled. If a peripheral is enabled, but the peripheral is web site (www.microchip.com). not actively driving a pin, that pin can be driven by a port. 2: Some registers and associated bits All port pins have three registers directly associated with described in this section may not be their operation as digital I/O. The data direction register available on all devices. Refer to (TRISx) determines whether the pin is an input or an out- Section4.0 “Memory Organization” in put. If the data direction bit is ‘1’, then the pin is an input. this data sheet for device-specific register All port pins are defined as inputs after a Reset. Reads and bit information. from the latch (LATx) read the latch. Writes to the latch write the latch. Reads from the port (PORTx) read the All of the device pins (except VDD, VSS, MCLR and port pins, while writes to the port pins write the latch. OSC1/CLKI) are shared among the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Any bit and its associated data and control registers Trigger inputs for improved noise immunity. that are not valid for a particular device will be disabled. That means the corresponding LATx and 10.1 Parallel I/O (PIO) Ports TRISx registers and the port pin will read as zeros. When a pin is shared with another peripheral or Generally a parallel I/O port that shares a pin with a function that is defined as an input only, it is peripheral is subservient to the peripheral. The nevertheless regarded as a dedicated port because peripheral’s output buffer data and control signals are there is no other competing source of outputs. provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data Read TRIS 0 Data Bus D Q I/O Pin WR TRIS CK TRIS Latch D Q WR LAT + WR PORT CK Data Latch Read LAT Input Data Read PORT  2008-2014 Microchip Technology Inc. DS70000318G-page 155

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.2 Open-Drain Configuration 10.4 I/O Port Write/Read Timing In addition to the PORTx, LATx and TRISx registers for One instruction cycle is required between a port direction data control, some digital-only port pins can also be change or port write operation and a read operation of individually configured for either digital or open-drain the same port. Typically, this instruction would be a NOP. output. This is controlled by the Open-Drain Control An example is shown in Example10-1. register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an 10.5 Input Change Notification open-drain output. The Input Change Notification (ICN) function of the The open-drain feature allows the generation of I/O ports allows the dsPIC33FJ06GS101/X02 and outputs higher than VDD (for example, 5V) on any dsPIC33FJ16GSX02/X04 devices to generate interrupt desired 5V tolerant pins by using external pull-up requests to the processor in response to a resistors. The maximum open-drain voltage allowed is Change-of-State (COS) on selected input pins. This the same as the maximum VIH specification. feature can detect input Change-of-States even in Refer to “Pin Diagrams” for the available pins and Sleep mode, when the clocks are disabled. Depending their functionality. on the device pin count, up to 30 external signals (CNx pin) can be selected (enabled) for generating an 10.3 Configuring Analog Port Pins interrupt request on a Change-of-State. Four control registers are associated with the CN The ADPCFG and TRISx registers control the opera- module. The CNEN1 and CNEN2 registers contain the tion of the Analog-to-Digital (A/D) port pins. The port interrupt enable control bits for each of the CN input pins that are to function as analog inputs must have pins. Setting any of these bits enables a CN interrupt their corresponding TRISx bit set (input). If the TRISx for the corresponding pins. bit is cleared (output), the digital output level (VOH or VOL) will be converted. Each CN pin also has a weak pull-up connected to it. The pull-ups act as a current source connected to the The ADPCFG register has a default value of 0x0000; pin, and eliminate the need for external resistors when therefore, all pins that share ANx functions are analog the push button or keypad devices are connected. The (not digital) by default. pull-ups are enabled separately using the CNPU1 and When the PORTx register is read, all pins configured as CNPU2 registers, which contain the control bits for analog input channels will read as cleared (a low level). each of the CN pins. Setting any of the control bits Pins configured as digital inputs will not convert an enables the weak pull-ups for the corresponding pins. analog input. Analog levels on any pin defined as a Note: Pull-ups on Change Notification pins digital input (including the ANx pins) can cause the should always be disabled when the port input buffer to consume current that exceeds the pin is configured as a digital output. device specifications. EQUATION 10-1: PORT WRITE/READ EXAMPLE MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs MOV W0, TRISBB ; and PORTB<7:0> as outputs NOP ; Delay 1 cycle BTSS PORTB, #13 ; Next Instruction DS70000318G-page 156  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.6 Peripheral Pin Select 10.6.2.1 Input Mapping Peripheral Pin Select configuration enables peripheral The inputs of the Peripheral Pin Select options are set selection and placement on a wide range of I/O mapped on the basis of the peripheral. A control pins. By increasing the pinout options available on a register associated with a peripheral dictates the pin it particular device, programmers can better tailor the will be mapped to. The RPINRx registers are used to microcontroller to their entire application, rather than configure peripheral input mapping (see Register10-1 trimming the application to fit the device. through Register10-14). Each register contains sets of 6-bit fields, with each set associated with one of the The Peripheral Pin Select configuration feature operates remappable peripherals. Programming a given over a fixed subset of digital I/O pins. Programmers can peripheral’s bit field with an appropriate 6-bit value independently map the input and/or output of most maps the RPn pin with that value to that peripheral. For digital peripherals to any one of these I/O pins. any given device, the valid range of values for any bit Peripheral Pin Select is performed in software, and gen- field corresponds to the maximum number of erally does not require the device to be reprogrammed. Peripheral Pin Selections supported by the device. Hardware safeguards are included that prevent acciden- tal or spurious changes to the peripheral mapping, once Figure10-2 Illustrates remappable pin selection for it has been established. U1RX input. Note: For input mapping only, the Peripheral Pin 10.6.1 AVAILABLE PINS Select (PPS) functionality does not have The Peripheral Pin Select feature is used with a range priority over the TRISx settings. There- of up to 30 pins. The number of available pins depends fore, when configuring the RPx pin for on the particular device and its pin count. Pins that input, the corresponding bit in the TRISx support the Peripheral Pin Select feature include the register must also be configured for input designation “RPn” in their full pin designation, where (i.e., set to ‘1’). “RP” designates a remappable peripheral and “n” is the remappable pin number. FIGURE 10-2: REMAPPABLE MUX INPUT FOR U1RX 10.6.2 CONTROLLING PERIPHERAL PIN SELECT U1RXR<5:0> Peripheral Pin Select features are controlled through two sets of Special Function Registers: one to map 0 peripheral inputs and another one to map outputs. RP0 Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) 1 RP1 can be placed on any selectable function pin without U1RX Input constraint. to Peripheral 2 The association of a peripheral to a peripheral select- RP2 able pin is handled in two different ways, depending on whether an input or output is being mapped. 33 RP33  2008-2014 Microchip Technology Inc. DS70000318G-page 157

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Configuration Input Name Function Name Register Bits External Interrupt 1 INT1 RPINR0 INT1R<5:0> External Interrupt 2 INT2 RPINR1 INT2R<5:0> Timer1 External Clock T1CK RPINR2 T1CKR<5:0> Timer2 External Clock T2CK RPINR3 T2CKR<5:0> Timer3 External Clock T3CK RPINR3 T3CKR<5:0> Input Capture 1 IC1 RPINR7 IC1R<5:0> Input Capture 2 IC2 RPINR7 IC2R<5:0> Output Compare Fault A OCFA RPINR11 OCFAR<5:0> UART1 Receive U1RX RPINR18 U1RXR<5:0> UART1 Clear-to-Send U1CTS RPINR18 U1CTSR<5:0> SPI Data Input 1 SDI1 RPINR20 SDI1R<5:0> SPI Clock Input 1 SCK1 RPINR20 SCK1R<5:0> SPI Slave Select Input 1 SS1 RPINR21 SS1R<5:0> PWM Fault Input PWM1 FLT1 RPINR29 FLT1R<5:0> PWM Fault Input PWM2 FLT2 RPINR30 FLT2R<5:0> PWM Fault Input PWM3 FLT3 RPINR30 FLT3R<5:0> PWM Fault Input PWM4 FLT4 RPINR31 FLT4R<5:0> PWM Fault Input PWM5 FLT5 RPINR31 FLT5R<5:0> PWM Fault Input PWM6 FLT6 RPINR32 FLT6R<5:0> PWM Fault Input PWM7 FLT7 RPINR32 FLT7R<5:0> PWM Fault Input PWM8 FLT8 RPINR33 FLT8R<5:0> External Synchronization signal to PWM Master Time Base SYNCI1 RPINR33 SYNCI1R<5:0> External Synchronization signal to PWM Master Time Base SYNCI2 RPINR34 SYNCI2R<5:0> DS70000318G-page 158  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.6.2.2 Output Mapping FIGURE 10-3: MULTIPLEXING OF REMAPPABLE OUTPUT In contrast to inputs, the outputs of the Peripheral Pin FOR RPn Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORn<5:0> RPORx registers are used to control output mapping. Like the RPINRx registers, each register contains sets Default 0 of 6-bit fields, with each set associated with one RPn U1TX Output Enable 3 pin (see Register10-15 through Register10-31). The value of the bit field corresponds to one of the U1RTS Output Enable 4 peripherals, and that peripheral’s output is mapped to Output Enable the pin (see Table10-2 and Figure10-3). The list of peripherals for output mapping also includes a null value of ‘00000’ because of the mapping OC2 Output Enable 19 technique. This permits any given pin to remain unconnected from the output of any of the pin PWM4L Output Enable 45 selectable peripherals. Default 0 U1TX Output 3 U1RTS Output 4 RPn Output Data OC2 Output 19 PWM4L Output 45 TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn) Function RPORn<5:0> Output Name NULL 000000 RPn tied to default port pin U1TX 000011 RPn tied to UART1 transmit U1RTS 000100 RPn tied to UART1 Ready-to-Send SDO1 000111 RPn tied to SPI1 data output SCK1 001000 RPn tied to SPI1 clock output SS1 001001 RPn tied to SPI1 slave select output OC1 010010 RPn tied to Output Compare 1 OC2 010011 RPn tied to Output Compare 2 SYNCO1 100101 RPn tied to external device synchronization signal via PWM master time base REFCLKO 100110 REFCLK output signal ACMP1 100111 RPn tied to Analog Comparator Output 1 ACMP2 101000 RPn tied to Analog Comparator Output 2 ACMP3 101001 RPn tied to Analog Comparator Output 3 ACMP4 101010 RPn tied to Analog Comparator Output 4 PWM4H 101100 RPn tied to PWM output pins associated with PWM Generator 4 PWM4L 101101 RPn tied to PWM output pins associated with PWM Generator 4  2008-2014 Microchip Technology Inc. DS70000318G-page 159

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.6.2.3 Virtual Pins Unlike the similar sequence with the oscillator’s LOCK bit, IOLOCK remains in one state until changed. This dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 allows all of the Peripheral Pin Selects to be configured devices support four virtual RPn pins (RP32, RP33, with a single unlock sequence followed by an update to RP34 and RP35), which are identical in functionality to all control registers, then locked with a second lock all other RPn pins, with the exception of pinouts. These sequence. four pins are internal to the devices and are not connected to a physical device pin. 10.6.3.2 Continuous State Monitoring These pins provide a simple way for inter-peripheral In addition to being protected from direct writes, the connection without utilizing a physical pin. For example, contents of the RPINRx and RPORx registers are the output of the analog comparator can be connected to constantly monitored in hardware by shadow registers. RP32 and the PWM Fault input can be configured for If an unexpected change in any of the registers occurs RP32 as well. This configuration allows the analog (such as cell disturbances caused by ESD or other comparator to trigger PWM Faults without the use of an external events), a Configuration Mismatch Reset will actual physical pin on the device. be triggered. 10.6.3 CONTROLLING CONFIGURATION 10.6.3.3 Configuration Bit Pin Select Lock CHANGES As an additional level of safety, the device can be Because peripheral remapping can be changed during configured to prevent many write session to the run time, some restrictions on peripheral remapping RPINRx and RPORx registers. The IOL1WAY are needed to prevent accidental configuration (FOSC<5>) Configuration bit blocks the IOLOCK bit changes. dsPIC33F devices include three features to from being cleared after it has been set once. If prevent alterations to the peripheral map: IOLOCK remains set, the register unlock procedure will • Control register lock sequence not execute and the Peripheral Pin Select Control • Continuous state monitoring registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a • Configuration bit pin select lock device Reset. 10.6.3.1 Control Register Lock In the default (unprogrammed) state, IOL1WAY is set, Under normal operation, writes to the RPINRx and restricting users to one write session. Programming RPORx registers are not allowed. Attempted writes IOL1WAY allows user applications unlimited access appear to execute normally, but the contents of the (with the proper use of the unlock sequence) to the registers remain unchanged. To change these Peripheral Pin Select registers. registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON<6>). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear IOLOCK, a specific command sequence must be executed: 1. Write 0x46 to OSCCON<7:0>. 2. Write 0x57 to OSCCON<7:0>. 3. Clear (or set) IOLOCK as a single operation. Note: MPLAB® C30 provides built-in C language functions for unlocking the OSCCON register: __builtin_write_OSCCONL(value) __builtin_write_OSCCONH(value) See the MPLAB C30 Help files for more information. DS70000318G-page 160  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.7 Peripheral Pin Select Registers Not all output remappable peripheral registers are implemented on all devices. See the specific register dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 description for further details. families of devices implement 34 registers for remappable peripheral configuration: • 15 Input Remappable Peripheral Registers • 17 Output Remappable Peripheral Registers Note: Input and output register values can only be changed if OSCCON<IOLOCK> = 0. See Section10.6.3.1 “Control Register Lock” for a specific command sequence. REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 INT1R<5:0>: Assign External Interrupt 1 (INTR1) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’  2008-2014 Microchip Technology Inc. DS70000318G-page 161

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 INT2R<5:0>: Assign External Interrupt 2 (INTR2) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 DS70000318G-page 162  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T3CKR5 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T2CKR5 T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 T3CKR<5:0>: Assign Timer3 External Clock (T3CK) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 T2CKR<5:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0  2008-2014 Microchip Technology Inc. DS70000318G-page 163

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC2R<5:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC1R<5:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 DS70000318G-page 164  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-5: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 OCFAR<5:0>: Assign Output Capture A (OCFA) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0  2008-2014 Microchip Technology Inc. DS70000318G-page 165

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-6: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U1CTSR<5:0>: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U1RXR<5:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 DS70000318G-page 166  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-7: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK1R<5:0>: Assign SPI1 Clock Input (SCK1IN) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI1R<5:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0  2008-2014 Microchip Technology Inc. DS70000318G-page 167

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-8: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS1R<5:0>: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 DS70000318G-page 168  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-9: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT1R5 FLT1R4 FLT1R3 FLT1R2 FLT1R1 FLT1R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT1R<5:0>: Assign PWM Fault Input 1 (FLT1) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’  2008-2014 Microchip Technology Inc. DS70000318G-page 169

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-10: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT3R5 FLT3R4 FLT3R3 FLT3R2 FLT3R1 FLT3R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT2R5 FLT2R4 FLT2R3 FLT2R2 FLT2R1 FLT2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT3R<5:0>: Assign PWM Fault Input 3 (FLT3) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 FLT2R<5:0>: Assign PWM Fault Input 2 (FLT2) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 DS70000318G-page 170  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-11: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT5R5 FLT5R4 FLT5R3 FLT5R2 FLT5R1 FLT5R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT4R5 FLT4R4 FLT4R3 FLT4R2 FLT4R1 FLT4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT5R<5:0>: Assign PWM Fault Input 5 (FLT5) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 FLT4R<5:0>: Assign PWM Fault Input 4 (FLT4) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0  2008-2014 Microchip Technology Inc. DS70000318G-page 171

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-12: RPINR32: PERIPHERAL PIN SELECT INPUT REGISTER 32 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT7R5 FLT7R4 FLT7R3 FLT7R2 FLT7R1 FLT7R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT6R5 FLT6R4 FLT6R3 FLT6R2 FLT6R1 FLT6R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT7R<5:0>: Assign PWM Fault Input 7 (FLT7) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 FLT6R<5:0>: Assign PWM Fault Input 6 (FLT6) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 DS70000318G-page 172  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-13: RPINR33: PERIPHERAL PIN SELECT INPUT REGISTER 33 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SYNCI1R5 SYNCI1R4 SYNCI1R3 SYNCI1R2 SYNCI1R1 SYNCI1R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — FLT8R5 FLT8R4 FLT8R3 FLT8R2 FLT8R1 FLT8R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SYNCI1R<5:0>: Assign PWM Master Time Base External Synchronization Signal to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 FLT8R<5:0>: Assign PWM Fault Input 8 (FLT8) to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0  2008-2014 Microchip Technology Inc. DS70000318G-page 173

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-14: RPINR34: PERIPHERAL PIN SELECT INPUT REGISTER 34 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SYNCI2R5 SYNCI2R4 SYNCI2R3 SYNCI2R2 SYNCI2R1 SYNCI2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SYNCI2R<5:0>: Assign PWM Master Time Base External Synchronization Signal to the Corresponding RPn Pin bits 111111 = Input tied to VSS 100011 = Input tied to RP35 100010 = Input tied to RP34 100001 = Input tied to RP33 100000 = Input tied to RP32 • • • 00000 = Input tied to RP0 REGISTER 10-15: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP1R<5:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP0R<5:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table10-2 for peripheral function numbers) DS70000318G-page 174  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-16: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP3R<5:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP2R<5:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table10-2 for peripheral function numbers) REGISTER 10-17: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP5R5 RP5R4 RP5R3 RP5R2 RP5R1 RP5R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP5R<5:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP4R<5:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table10-2 for peripheral function numbers)  2008-2014 Microchip Technology Inc. DS70000318G-page 175

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-18: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP7R<5:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP6R<5:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table10-2 for peripheral function numbers) REGISTER 10-19: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP9R<5:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP8R<5:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table10-2 for peripheral function numbers) Note 1: This register is not implemented in the dsPIC33FJ06GS101 device. DS70000318G-page 176  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-20: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP11R<5:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP10R<5:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table10-2 for peripheral function numbers) Note 1: This register is not implemented in the dsPIC33FJ06GS101 device. REGISTER 10-21: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP13R<5:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP12R<5:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table10-2 for peripheral function numbers) Note 1: This register is not implemented in the dsPIC33FJ06GS101 device.  2008-2014 Microchip Technology Inc. DS70000318G-page 177

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-22: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP15R5 RP15R4 RP15R3 RP15R2 RP15R1 RP15R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP15R<5:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP14R<5:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table10-2 for peripheral function numbers) Note 1: This register is not implemented in the dsPIC33FJ06GS101 device. REGISTER 10-23: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP17R<5:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP16R<5:0>: Peripheral Output Function is Assigned to RP16 Output Pin bits (see Table10-2 for peripheral function numbers) Note 1: This register is implemented in the dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only. DS70000318G-page 178  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-24: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP19R5 RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP19R<5:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP18R<5:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits (see Table10-2 for peripheral function numbers) Note 1: This register is implemented in the dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only. REGISTER 10-25: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP21R<5:0>: Peripheral Output Function is Assigned to RP21 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP20R<5:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table10-2 for peripheral function numbers) Note 1: This register is implemented in the dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only.  2008-2014 Microchip Technology Inc. DS70000318G-page 179

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-26: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP23R5 RP23R4 RP23R3 RP23R2 RP23R1 RP23R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP23R<5:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP22R<5:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table10-2 for peripheral function numbers) Note 1: This register is implemented in the dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only. REGISTER 10-27: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP25R<5:0>: Peripheral Output Function is Assigned to RP25 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP24R<5:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table10-2 for peripheral function numbers) Note 1: This register is implemented in the dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only. DS70000318G-page 180  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-28: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP27R5 RP27R4 RP27R3 RP27R2 RP27R1 RP27R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP26R5 RP26R4 RP26R3 RP26R2 RP26R1 RP26R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP27R<5:0>: Peripheral Output Function is Assigned to RP27 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP26R<5:0>: Peripheral Output Function is Assigned to RP26 Output Pin bits (see Table10-2 for peripheral function numbers) Note 1: This register is implemented in the dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only. REGISTER 10-29: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP29R<5:0>: Peripheral Output Function is Assigned to RP29 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP28R<5:0>: Peripheral Output Function is Assigned to RP28 Output Pin bits (see Table10-2 for peripheral function numbers) Note 1: This register is implemented in the dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices only.  2008-2014 Microchip Technology Inc. DS70000318G-page 181

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-30: RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP33R5 RP33R4 RP33R3 RP33R2 RP33R1 RP33R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP32R5 RP32R4 RP32R3 RP32R2 RP32R1 RP32R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP33R<5:0>: Peripheral Output Function is Assigned to RP33 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP32R<5:0>: Peripheral Output Function is Assigned to RP32 Output Pin bits (see Table10-2 for peripheral function numbers) REGISTER 10-31: RPOR17: PERIPHERAL PIN SELECT OUTPUT REGISTER 17 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP35R5 RP35R4 RP35R3 RP35R2 RP35R1 RP35R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP34R5 RP34R4 RP34R3 RP34R2 RP34R1 RP34R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP35R<5:0>: Peripheral Output Function is Assigned to RP35 Output Pin bits (see Table10-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP34R<5:0>: Peripheral Output Function is Assigned to RP34 Output Pin bits (see Table10-2 for peripheral function numbers) DS70000318G-page 182  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 11.0 TIMER1 The unique features of Timer1 allow it to be used for Real-Time Clock (RTC) applications. A block diagram Note1: This data sheet summarizes the features of Timer1 is shown in Figure11-1. of the dsPIC33FJ06GS101/X02 and The Timer1 module can operate in one of the following dsPIC33FJ16GSX02/X04 families of modes: devices. It is not intended to be a comprehensive reference source. To • Timer mode complement the information in this data • Gated Timer mode sheet, refer to “Timers” (DS70205) in • Synchronous Counter mode the “dsPIC33F/PIC24H Family Reference • Asynchronous Counter mode Manual”, which is available from the In Timer and Gated Timer modes, the input clock is Microchip web site (www.microchip.com). derived from the internal instruction cycle clock (FCY). In Synchronous and Asynchronous Counter modes, 2: Some registers and associated bits the input clock is derived from the external clock input described in this section may not be at the T1CK pin. available on all devices. Refer to Section4.0 “Memory Organization” in The Timer modes are determined by the following bits: this data sheet for device-specific register • Timer Clock Source Control bit (TCS): T1CON<1> and bit information. • Timer Synchronization Control bit (TSYNC): The Timer1 module is a 16-bit timer, which can serve T1CON<2> as a time counter for the Real-Time Clock (RTC), or • Timer Gate Control bit (TGATE): T1CON<6> operate as a free-running interval timer/counter. The timer control bit settings for different operating The Timer1 module has the following unique features modes are given in the Table11-1. over other timers: • Can be operated from the low-power 32 kHz TABLE 11-1: TIMER MODE SETTINGS crystal oscillator available on the device Mode TCS TGATE TSYNC • Can be operated in Asynchronous Counter mode from an external clock source Timer 0 0 x • Optionally, the external clock input (T1CK) can be Gated Timer 0 1 x synchronized to the internal device clock and the Synchronous 1 x 1 clock synchronization is performed after the Counter prescaler Asynchronous 1 x 0 Counter FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM Gate Falling Edge 1 Sync Detect Set T1IF Flag 0 FCY Prescaler 10 (/n) Reset TGATE TMR1 00 TCKPS<1:0> 0 T1CK x1 Equal Prescaler Sync 1 Comparator (/n) TGATE TSYNC TCKPS<1:0> TCS PR1  2008-2014 Microchip Technology Inc. DS70000318G-page 183

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timer1 Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0> Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronizes external clock input 0 = Does not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = External clock from T1CK pin (on the rising edge) 0 = Internal clock (FCY) bit 0 Unimplemented: Read as ‘0’ DS70000318G-page 184  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 12.0 TIMER2/3 FEATURES Timer2 is a Type B timer that offers the following major features: Note1: This data sheet summarizes the features • A Type B timer can be concatenated with a of the dsPIC33FJ06GS101/X02 and TypeC timer to form a 32-bit timer dsPIC33FJ16GSX02/X04 families of • External clock input (TxCK) is always synchronized devices. It is not intended to be a to the internal device clock and the clock comprehensive reference source. To synchronization is performed after the prescaler. complement the information in this data sheet, refer to “Timers” (DS70205) in Figure12-1 shows a block diagram of the Type B timer. the “dsPIC33F/PIC24H Family Reference Timer3 is a Type C timer that offers the following major Manual”, which is available on the features: Microchip web site (www.microchip.com). • A Type C timer can be concatenated with a 2: Some registers and associated bits TypeB timer to form a 32-bit timer described in this section may not be • The external clock input (TxCK) is always available on all devices. Refer to synchronized to the internal device clock and the clock Section4.0 “Memory Organization” in synchronization is performed before the prescaler this data sheet for device-specific register A block diagram of the Type C timer is shown in and bit information. Figure12-2. Note: Timer3 is not available on all devices. FIGURE 12-1: TYPE B TIMER BLOCK DIAGRAM (x = 2) Gate Falling Edge Sync Detect 1 Set TxIF Flag FCY Prescaler 10 0 (/n) Reset 00 TMRx TCKPS<1:0> TGATE Prescaler Sync x1 (/n) Equal TxCK Comparator TCKPS<1:0> TGATE TCS PRx FIGURE 12-2: TYPE C TIMER BLOCK DIAGRAM (x = 3) Gate Falling Edge Sync Detect 1 Set TxIF Flag FCY Prescaler 10 0 (/n) Reset TMRx 00 TGATE TCKPS<1:0> Prescaler Sync x1 (/n) Equal TxCK Comparator TCKPS<1:0> TGATE TCS PRx  2008-2014 Microchip Technology Inc. DS70000318G-page 185

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 The Timer2/3 module can operate in one of the When configured for 32-bit operation, only the Type B following modes: Timer Control (TxCON) register bits are required for setup and control while the Type C Timer Control • Timer mode register bits are ignored (except the TSIDL bit). • Gated Timer mode • Synchronous Counter mode For interrupt control, the combined 32-bit timer uses the interrupt enable, interrupt flag and interrupt priority In Timer and Gated Timer modes, the input clock is control bits of the Type C timer. The interrupt control derived from the internal instruction cycle clock (FCY). and status bits for the TypeB timer are ignored In Synchronous Counter mode, the input clock is during32-bit timer operation. derived from the external clock input at the TxCK pin. The Timer2 and Timer 3 that can be combined to form a The timer modes are determined by the following bits: 32-bit timer are listed in Table12-2. • TCS (TxCON<1>): Timer Clock Source Control bit • TGATE (TxCON<6>): Timer Gate Control bit TABLE 12-2: 32-BIT TIMER Timer control bit settings for different operating modes Type B Timer (lsw) Type C Timer (msw) are given in the Table12-1. Timer2 Timer3 TABLE 12-1: TIMER MODE SETTINGS A block diagram representation of the 32-bit timer Mode TCS TGATE module is shown in Figure12-3. The 32-timer module can operate in one of the following modes: Timer 0 0 • Timer mode Gated Timer 0 1 • Gated Timer mode Synchronous Counter 1 x • Synchronous Counter mode To configure the features of Timer2/3 for 32-bit 12.1 16-Bit Operation operation: To configure any of the timers for individual 16-bit 1. Set the T32 control bit. operation: 2. Select the prescaler ratio for Timer2 using the TCKPS<1:0> bits. 1. Clear the T32 bit corresponding to that timer. 3. Set the Clock and Gating modes using the 2. Select the timer prescaler ratio using the corresponding TCS and TGATE bits. TCKPS<1:0> bits. 4. Load the timer period value. PR3 contains the 3. Set the Clock and Gating modes using the TCS most significant word of the value, while PR2 and TGATE bits. contains the least significant word. 4. Load the timer period value into the PRx 5. If interrupts are required, set the interrupt enable register. bit, T3IE. Use the priority bits, T3IP<2:0>, to set 5. If interrupts are required, set the interrupt enable the interrupt priority. While Timer2 controls the bit, TxIE. Use the priority bits, TxIP<2:0>, to set timer, the interrupt appears as a Timer3 the interrupt priority. interrupt. 6. Set the TON bit. 6. Set the corresponding TON bit. 12.2 32-Bit Operation The timer value at any point is stored in the register pair, TMR3:TMR2, which always contains the most A 32-bit timer module can be formed by combining a significant word of the count, while TMR2 contains the Type B and a Type C 16-bit timer module. For 32-bit least significant word. timer operation, the T32 control bit in the Type B Timer Control (TxCON<3>) register must be set. The Type C timer holds the most significant word (msw) and the Type B timer holds the least significant word (lsw) for32-bit operation. DS70000318G-page 186  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 12-3: 32-BIT TIMER BLOCK DIAGRAM Gate Falling Edge Sync Detect 1 Set TyIF Flag PRx PRy 0 Equal Comparator TGATE Prescaler 10 FCY (/n) lsw msw Reset 00 TMRx(1) TMRy(2) TCKPS<1:0> Prescaler Sync x1 (/n) TxCK TMRyHLD TCKPS<1:0> TGATE TCS Data Bus <15:0> Note 1: Timerx is a Type B Timer (x = 2). 2: Timery is a Type C Timer (y = 3).  2008-2014 Microchip Technology Inc. DS70000318G-page 187

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 12-1: TxCON: TIMERx CONTROL REGISTER (x = 2) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timerx On bit When T32 = 1 (in 32-Bit Timer mode): 1 = Starts 32-bit TMRx:TMRy timer pair 0 = Stops 32-bit TMRx:TMRy timer pair When T32 = 0 (in 16-Bit Timer mode): 1 = Starts 16-bit timer 0 = Stops 16-bit timer bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timerx Stop in Idle Mode bit 1 = Discontinues timer operation when device enters Idle mode 0 = Continues timer operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 T32: 32-Bit Timerx Mode Select bit 1 = TMRx and TMRy form a 32-bit timer 0 = TMRx and TMRy form a separate 16-bit timer bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit 1 = External clock from TxCK pin 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ DS70000318G-page 188  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 12-2: TyCON: TIMERy CONTROL REGISTER (y = 3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(2) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(2) TCKPS1(2) TCKPS0(2) — — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timery On bit(2) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timery Stop in Idle Mode bit(1) 1 = Discontinues timer operation when device enters Idle mode 0 = Continues timer operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timery Gated Time Accumulation Enable bit(2) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timery Input Clock Prescale Select bits(2) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timery Clock Source Select bit(2) 1 = External clock from TxCK pin 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32=1) in the Timerx Control (TxCON<3>) register, these bits have no effect.  2008-2014 Microchip Technology Inc. DS70000318G-page 189

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 190  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 13.0 INPUT CAPTURE The input capture module captures the 16-bit value of the selected Time Base register when an event occurs Note1: This data sheet summarizes the features at the ICx pin. The events that cause a capture event of the dsPIC33FJ06GS101/X02 and are listed below in three categories: dsPIC33FJ16GSX02/X04 families of • Simple Capture Event modes: devices. It is not intended to be a - Capture timer value on every falling edge of comprehensive reference source. To input at ICx pin complement the information in this data - Capture timer value on every rising edge of sheet, refer to “Input Capture” input at ICx pin (DS70198) in the “dsPIC33F/PIC24H • Capture timer value on every edge (rising and Family Reference Manual”, which is falling) available on the Microchip web site • Prescaler Capture Event modes: (www.microchip.com). - Capture timer value on every 4th rising edge 2: Some registers and associated bits of input at ICx pin described in this section may not be - Capture timer value on every 16th rising available on all devices. Refer to edge of input at ICx pin Section4.0 “Memory Organization” in this data sheet for device-specific register Each input capture channel can select one of the and bit information. two 16-bit timers (Timer2 or Timer3) for the time base. The selected timer can use either an internal The input capture module is useful in applications or external clock. requiring frequency (period) and pulse measurement. Other operational features include: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices support up to two input capture channels. • Device wake-up from capture pin during CPU Sleep and Idle modes • Interrupt on input capture event • 4-word FIFO buffer for capture values - Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled • Use of input capture to provide additional sources of external interrupts FIGURE 13-1: INPUT CAPTURE x BLOCK DIAGRAM From 16-Bit Timers TMR2 TMR3 16 16 ICTMR 1 0 (ICxCON<7>) Prescaler Edge Detection Logic FIFO Counter and R/W (1, 4, 16) Clock Synchronizer Logic ICx Pin ICM<2:0> (ICxCON<2:0>) 3 Mode Select O F ICOV, ICBNE (ICxCON<4:3>) FI ICxBUF ICxI<1:0> Interrupt ICxCON Logic System Bus Set Flag ICxIF (in IFSx Register) Note 1: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.  2008-2014 Microchip Technology Inc. DS70000318G-page 191

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 13.1 Input Capture Register REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER (x = 1, 2) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — ICSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0 ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 ICTMR: Input Capture Timer Select bits 1 = TMR2 contents are captured on a capture event 0 = TMR3 contents are captured on a capture event bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM<2:0>: Input Capture Mode Select bits 111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode; rising edge detect only, all other control bits are not applicable 110 = Unused (module disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge (rising and falling); ICI<1:0> bits do not control interrupt generation for this mode 000 = Input capture module turned off DS70000318G-page 192  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 14.0 OUTPUT COMPARE The output compare module can select either Timer2 or Timer3 for its time base. The module compares the Note1: This data sheet summarizes the features value of the timer with the value of one or two Compare of the dsPIC33FJ06GS101/X02 and registers depending on the operating mode selected. dsPIC33FJ16GSX02/X04 families of The state of the output pin changes when the timer devices. It is not intended to be a value matches the Compare register value. The output comprehensive reference source. To compare module generates either a single output complement the information in this data pulse, or a sequence of output pulses, by changing the sheet, refer to “Output Compare” state of the output pin on the compare match events. (DS70005157) in the “dsPIC33F/PIC24H The output compare module can also generate Family Reference Manual”, which is interrupts on compare match events. available on the Microchip web site The output compare module has multiple operating (www.microchip.com). modes: 2: Some registers and associated bits • Active-Low One-Shot mode described in this section may not be • Active-High One-Shot mode available on all devices. Refer to Section4.0 “Memory Organization” in • Toggle mode this data sheet for device-specific register • Delayed One-Shot mode and bit information. • Continuous Pulse mode • PWM mode without Fault Protection • PWM mode with Fault Protection FIGURE 14-1: OUTPUT COMPARE x MODULE BLOCK DIAGRAM Set Flag bit OCxIF OCxRS Output S Q OCxR OCx Logic R Output Enable 3 OCM<2:0> Mode Select OCFA Comparator 0 1 OCTSEL 0 1 16 16 TMR2 TMR3 TMR2 TMR3 Rollover Rollover Note: An ‘x’ in a signal, register or bit name denotes the number of the output compare channels.  2008-2014 Microchip Technology Inc. DS70000318G-page 193

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 14.1 Output Compare Modes application must disable the associated timer when writing to the Output Compare Control registers to Configure the Output Compare modes by setting the avoid malfunctions. appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register. Note: Refer to “Output Compare” (DS70209) Table14-1 lists the different bit settings for the Output in the “dsPIC33F/PIC24H Family Compare modes. Figure14-2 illustrates the output Reference Manual” for OCxR and OCxRS compare operation for various modes. The user register restrictions. TABLE 14-1: OUTPUT COMPARE MODES OCM<2:0> Mode OCx Pin Initial State OCx Interrupt Generation 111 PWM with Fault Protection ‘0’, if OCxR is zero OCFA falling edge for OC1 to OC4 ‘1’, if OCxR is non-zero 110 PWM without Fault Protection ‘0’, if OCxR is zero No interrupt ‘1’, if OCxR is non-zero 101 Continuous Pulse 0 OCx falling edge 100 Delayed One-Shot 0 OCx falling edge 011 Toggle Current output is maintained OCx rising and falling edge 010 Active-High One-Shot 1 OCx falling edge 001 Active-Low One-Shot 0 OCx rising edge 000 Module Disabled Controlled by GPIO register — FIGURE 14-2: OUTPUT COMPARE OPERATION Output Compare Timer is Reset on Mode Enabled Period Match OCxRS TMRy OCxR Active-Low One-Shot (OCM<2:0> = 001) Active-High One-Shot (OCM<2:0> = 010) Toggle (OCM<2:0> = 011) Delayed One-Shot (OCM<2:0> = 100) Continuous Pulse (OCM<2:0> = 101) PWM (OCM<2:0> = 110 or 111) DS70000318G-page 194  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0 — — — OCFLT OCTSEL OCM2 OCM1 OCM0 bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Stop Output Compare in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode bit 12-5 Unimplemented: Read as ‘0’ bit 4 OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in hardware only) 0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111) bit 3 OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for Output Compare x 0 = Timer2 is the clock source for Output Compare x bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx, Fault pin is enabled 110 = PWM mode on OCx, Fault pin is disabled 101 = Initializes OCx pin low, generates continuous output pulses on OCx pin 100 = Initializes OCx pin low, generates single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initializes OCx pin high, compare event forces OCx pin low 001 = Initializes OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled  2008-2014 Microchip Technology Inc. DS70000318G-page 195

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 196  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 15.0 HIGH-SPEED PWM • Independent Fault/Current-Limit inputs for each of the eight PWM outputs Note1: This data sheet summarizes the fea- • Output override control tures of the dsPIC33FJ06GS101/X02 • Special Event Trigger and dsPIC33FJ16GSX02/X04 families • PWM capture feature of devices. It is not intended to be a • Prescaler for input clock comprehensive reference source. To complement the information in this data • Dual trigger from PWM to ADC sheet, refer to “High-Speed PWM” • PWMxH, PWMxL output pin swapping (DS70323) in the “dsPIC33F/PIC24H • PWM4H, PWM4L pins remappable Family Reference Manual”, which is • On-the-fly PWM frequency, duty cycle and available on the Microchip web site phase-shift changes (www.microchip.com). • Disabling of Individual PWM generators to reduce 2: Some registers and associated bits power consumption described in this section may not be • Leading-Edge Blanking (LEB) functionality available on all devices. Refer to Section4.0 “Memory Organization” in Note: Duty cycle, dead time, phase shift and this data sheet for device-specific register frequency resolution is 8.32 ns in and bit information. Center-Aligned PWM mode. The high-speed PWM module on the Figure15-1 conceptualizes the PWM module in a dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ simplified block diagram. Figure15-2 illustrates how X04 devices supports a wide variety of PWM modes the module hardware is partitioned for each PWM and output formats. This PWM module is ideal for output pair for the Complementary PWM mode. Each power conversion applications, such as: functional unit of the PWM module is discussed in subsequent sections. • AC/DC Converters • DC/DC Converters The PWM module contains four PWM generators. The module has up to eight PWM output pins: PWM1H, • Power Factor Correction (PFC) PWM1L, PWM2H, PWM2L, PWM3H, PWM3L, • Uninterruptible Power Supply (UPS) PWM4H and PWM4L. For complementary outputs, • Inverters these eight I/O pins are grouped into H/L pairs. • Battery Chargers • Digital Lighting 15.1 Features Overview The high-speed PWM module incorporates the following features: • 2-4 PWM generators with 4-8 outputs • Individual time base and duty cycle for each of the eight PWM outputs • Dead time for rising and falling edges: • Duty cycle resolution of 1.04 ns • Dead-time resolution of 1.04 ns • Phase-shift resolution of 1.04 ns • Frequency resolution of 1.04 ns • PWM modes supported: - Standard Edge-Aligned - True Independent Output - Complementary - Center-Aligned - Push-Pull - Multiphase - Variable Phase - Fixed Off-Time - Current Reset - Current-Limit  2008-2014 Microchip Technology Inc. DS70000318G-page 197

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 15.2 Feature Description Multiphase PWM is often used to improve DC/DC Converter load transient response, and reduce the size The PWM module is designed for applications that of output filter capacitors and inductors. Multiple DC/ require: DC Converters are often operated in parallel, but • High-resolution at high PWM frequencies phase-shifted in time. A single PWM output operating • The ability to drive Standard, Edge-Aligned, at 250kHz has a period of 4 s, but an array of four Center-Aligned Complementary mode, and PWM channels, staggered by 1 s each, yields an Push-Pull mode outputs effective switching frequency of 1 MHz. Multiphase • The ability to create multiphase PWM outputs PWM applications typically use a fixed-phase relationship. For Center-Aligned mode, the duty cycle, period phase and dead-time resolutions will be 8.32 ns. Variable phase PWM is useful in Zero Voltage Transition (ZVT) power converters. Here, the PWM Two common, medium power converter topologies are duty cycle is always 50%, and the power flow is push-pull and half-bridge. These designs require the controlled by varying the relative phase shift between PWM output signal to be switched between alternate the two PWM generators. pins, as provided by the Push-Pull PWM mode. Phase-shifted PWM describes the situation where each PWM generator provides outputs, but the phase relationship between the generator outputs is specifiable and changeable. DS70000318G-page 198  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 15-1: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF HIGH-SPEED PWM PWMCONx Pin and Mode Control LEBCONx Control for Blanking External Input Signals TRGCONx ADC Trigger Control ALTDTRx, DTRx Dead-Time Control PTCON PWM Enable and Mode Control MDC PDC1 Master Duty Cycle Register MUX Latch PWM GEN 1 Comparator Channel 1 PWM1H Dead-Time Generator PWM1L Timer 1 Phase PDC2 c gi MUX o L Latch PWM GEN 2 outing Channel 2 PWM2H Comparator d R Dead-Time Generator PWM2L n a Timer e c Phase Overrid de Logi PDC3 Fault Overri MUX mit and CLMT ComLaptacrhator PWM GEN 3 Current-Li Dead-CThimaen nGeel n3erator Fault PPWWMM33LH Timer er, s U Phase M W P PDC4 MUX PWM GEN 4 Latch Channel 4 PWM4H(1) Comparator Dead-Time Generator PWM4L(1) Timer Phase Timer Period PTPER Master Time Base FLTX(1) External Time Base SYNCO(1) PTMR Synchronization SYNCIX(1) Comparator Special Event Special Event Postscaler Trigger Special Event SEVTCMP Comparison Value IOCONx Pin Override Control Fault Mode and Pin Control FCLCONx Note 1: These pins are remappable.  2008-2014 Microchip Technology Inc. DS70000318G-page 199

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 15-2: PARTITIONED OUTPUT PAIR, COMPLEMENTARY PWM MODE Phase Offset TMR < PDC PWM M Timer/Counter Dead-Time U PWMXH Override X Logic Logic Duty Cycle Comparator M U PWMXL X PWM Duty Cycle Register Channel Override Values Fault Override Values Fault Active Fault Pin Fault Pin Assignment Logic 15.3 Control Registers • SDCx: PWMx Secondary Duty Cycle Register(1,2) The following registers control the operation of the • SPHASEx: PWMx Secondary Phase-Shift high-speed PWM module. Register(1,2) (provides the local time base period • PTCON: PWM Time Base Control Register for PWMxL) • PTCON2: PWM Clock Divider Select Register • TRGCONx: PWMx Trigger Control Register • PTPER: PWM Master Time Base Register(1) • IOCONx: PWMx I/O Control Register • SEVTCMP: PWM Special Event Compare • FCLCONx: PWMx Fault Current-Limit Control Register Register • MDC: PWM Master Duty Cycle Register(1,2) • TRIGx: PWMx Primary Trigger Compare Value • PWMCONx: PWMx Control Register Register • PDCx: PWMx Generator Duty Cycle Register(1,2) • STRIGx: PWMx Secondary Trigger Compare • PHASEx: PWMx Primary Phase-Shift Value Register Register(1,2) (provides the local time base period • LEBCONx: Leading-Edge Blanking Control for PWMxH) Register(1) • DTRx: PWMx Dead-Time Register • PWMCAPx: Primary PWMx Time Base Capture • ALTDTRx: PWMx Alternate Dead-Time Register Register DS70000318G-page 200  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 15-1: PTCON: PWM TIME BASE CONTROL REGISTER R/W-0 U-0 R/W-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN — PTSIDL SESTAT SEIEN EIPU(1) SYNCPOL(1) SYNCOEN(1) bit 15 bit 8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SYNCEN(1) — SYNCSRC1(1) SYNCSRC0(1) SEVTPS3(1) SEVTPS2(1) SEVTPS1(1) SEVTPS0(1) bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTEN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit 1 = PWM time base halts in CPU Idle mode 0 = PWM time base runs in CPU Idle mode bit 12 SESTAT: Special Event Interrupt Status bit 1 = Special event interrupt is pending 0 = Special event interrupt is not pending bit 11 SEIEN: Special Event Interrupt Enable bit 1 = Special event interrupt is enabled 0 = Special event interrupt is disabled bit 10 EIPU: Enable Immediate Period Updates bit(1) 1 = Active Period register is updated immediately 0 = Active Period register updates occur on PWM cycle boundaries bit 9 SYNCPOL: Synchronization Input/Output Polarity bit(1) 1 = SYNCIx and SYNCO polarity is inverted (active-low) 0 = SYNCIx and SYNCO are active-high bit 8 SYNCOEN: Primary Time Base Sync Enable bit(1) 1 = SYNCO output is enabled 0 = SYNCO output is disabled bit 7 SYNCEN: External Time Base Synchronization Enable bit(1) 1 = External synchronization of primary time base is enabled 0 = External synchronization of primary time base is disabled bit 6 Unimplemented: Read as ‘0’ bit 5-4 SYNCSRC<1:0>: Synchronous Source Selection bits(1) 11 = Reserved 10 = Reserved 01 = SYNCI2 00 = SYNCI1 Note 1: These bits should be changed only when PTEN=0. In addition, when using the SYNCIx feature, the user application must program the Period register with a value that is slightly larger than the expected period of the external synchronization input signal.  2008-2014 Microchip Technology Inc. DS70000318G-page 201

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-1: PTCON: PWM TIME BASE CONTROL REGISTER (CONTINUED) bit 3-0 SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits(1) 1111 = 1:16 Postscaler generates a Special Event Trigger trigger on every sixteenth compare match event • • • 0001 = 1:2 Postscaler generates a Special Event Trigger on every second compare match event 0000 = 1:1 Postscaler generates a Special Event Trigger on every compare match event Note 1: These bits should be changed only when PTEN=0. In addition, when using the SYNCIx feature, the user application must program the Period register with a value that is slightly larger than the expected period of the external synchronization input signal. DS70000318G-page 202  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-2: PTCON2: PWM CLOCK DIVIDER SELECT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCLKDIV<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1) 111 = Reserved 110 = Divide-by-64, maximum PWM timing resolution 101 = Divide-by-32, maximum PWM timing resolution 100 = Divide-by-16, maximum PWM timing resolution 011 = Divide-by-8, maximum PWM timing resolution 010 = Divide-by-4, maximum PWM timing resolution 001 = Divide-by-2, maximum PWM timing resolution 000 = Divide-by-1, maximum PWM timing resolution (power-on default) Note 1: These bits should be changed only when PTEN=0. Changing the clock selection during operation will yield unpredictable results. REGISTER 15-3: PTPER: PWM MASTER TIME BASE REGISTER(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PTPER <15:8> bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 PTPER <7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PTPER<15:0>: PWM Master Time Base (PMTMR) Period Value bits Note 1: The minimum value that can be loaded into the PTPER register is 0x0010 and the maximum value is 0xFFF8.  2008-2014 Microchip Technology Inc. DS70000318G-page 203

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-4: SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP <15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 SEVTCMP <7:3> — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 SEVTCMP<12:0>: Special Event Compare Count Value bits bit 2-0 Unimplemented: Read as ‘0’ REGISTER 15-5: MDC: PWM MASTER DUTY CYCLE REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MDC<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MDC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 MDC<15:0>: Master PWM Duty Cycle Value bits Note 1: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of Period – 0x0008. 2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of operation), the PWM duty cycle resolution will degrade from 1 LSB to 3 LSBs. DS70000318G-page 204  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER HS/HC-0 HS/HC-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTSTAT(1) CLSTAT(1) TRGSTAT FLTIEN CLIEN TRGIEN ITB(3) MDCS(3) bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 DTC1 DTC0 — — — CAM(2,3) XPRES(4) IUE bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTSTAT: Fault Interrupt Status bit(1) 1 = Fault interrupt is pending 0 = No Fault interrupt is pending; this bit is cleared by setting FLTIEN = 0 bit 14 CLSTAT: Current-Limit Interrupt Status bit(1) 1 = Current-limit interrupt is pending 0 = No current-limit interrupt is pending; this bit is cleared by setting CLIEN = 0 bit 13 TRGSTAT: Trigger Interrupt Status bit 1 = Trigger interrupt is pending 0 = No trigger interrupt is pending; this bit is cleared by setting TRGIEN = 0 bit 12 FLTIEN: Fault Interrupt Enable bit 1 = Fault interrupt is enabled 0 = Fault interrupt is disabled and the FLTSTAT bit is cleared bit 11 CLIEN: Current-Limit Interrupt Enable bit 1 = Current-limit interrupt is enabled 0 = Current-limit interrupt is disabled and the CLSTAT bit is cleared bit 10 TRGIEN: Trigger Interrupt Enable bit 1 = A trigger event generates an interrupt request 0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared bit 9 ITB: Independent Time Base Mode bit(3) 1 = PHASEx/SPHASEx register provides time base period for this PWM generator 0 = PTPER register provides timing for this PWM generator bit 8 MDCS: Master Duty Cycle Register Select bit(3) 1 = MDC register provides duty cycle information for this PWM generator 0 = PDCx/SDCx register provides duty cycle information for this PWM generator bit 7-6 DTC<1:0>: Dead-Time Control bits 11 = Reserved 10 = Dead-time function is disabled 01 = Negative dead time is actively applied for all output modes 00 = Positive dead time is actively applied for all output modes bit 5-3 Unimplemented: Read as ‘0’ Note 1: Software must clear the interrupt status here and the corresponding IFSx bit in the interrupt controller. 2: The Independent Time Base mode (ITB=1) must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. 3: These bits should be changed only when PTEN=0. Changing the clock selection during operation will yield unpredictable results. 4: To operate in External Period Reset mode, configure FCLCONx<CLMOD> = 0 and PWMCONx<ITB> = 1.  2008-2014 Microchip Technology Inc. DS70000318G-page 205

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER (CONTINUED) bit 2 CAM: Center-Aligned Mode Enable bit(2,3) 1 = Center-Aligned mode is enabled 0 = Center-Aligned mode is disabled bit 1 XPRES: External PWM Reset Control bit(4) 1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time Base (ITB) mode 0 = External pins do not affect PWM time base bit 0 IUE: Immediate Update Enable bit 1 = Updates to the active MDC/PDCx/SDCx registers are immediate 0 = Updates to the active MDC/PDCx/SDCx registers are synchronized to the PWM time base Note 1: Software must clear the interrupt status here and the corresponding IFSx bit in the interrupt controller. 2: The Independent Time Base mode (ITB=1) must be enabled to use Center-Aligned mode. If ITB = 0, the CAM bit is ignored. 3: These bits should be changed only when PTEN=0. Changing the clock selection during operation will yield unpredictable results. 4: To operate in External Period Reset mode, configure FCLCONx<CLMOD> = 0 and PWMCONx<ITB> = 1. DS70000318G-page 206  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-7: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PDCx<15:0>: PWM Generator # Duty Cycle Value bits Note 1: In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In Complementary, Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of both the PWMxH and PWMxL. The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of Period-0x0008. 2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of operation), the PWM duty cycle resolution will degrade from 1 LSB to 3 LSBs. REGISTER 15-8: SDCx: PWMx SECONDARY DUTY CYCLE REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SDCx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SDCx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 SDCx<15:0>: Secondary Duty Cycle for PWMxL Output Pin bits Note 1: The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the SDCx register controls the PWMxL duty cycle. The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009, while the maximum pulse width generated corresponds to a value of Period-0x0008. 2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of operation), the PWM duty cycle resolution will degrade from 1 LSB to 3 LSBs.  2008-2014 Microchip Technology Inc. DS70000318G-page 207

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-9: PHASEx: PWMx PRIMARY PHASE-SHIFT REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PHASEx<15:0>: PWM Phase-Shift Value or Independent Time Base Period for this PWM Generator bits Note 1: If PWMCONx<ITB> = 0, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or 10); PHASEx<15:0> = Phase-shift value for PWMxH and PWMxL outputs • True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11); PHASEx<15:0> = Phase-shift value for PWMxL only 2: If PWMCONx<ITB> = 1, the following applies based on the mode of operation: • Complementary, Redundant, and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or 10); PHASEx<15:0> = Independent Time Base period value for PWMxH and PWMxL • True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11); PHASEx<15:0> = Independent Time Base period value for PWMxL only • The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008, while the maximum pulse width generated corresponds to a value of Period – 0x0008. DS70000318G-page 208  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 15-10: SPHASEx: PWMx SECONDARY PHASE-SHIFT REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 SPHASEx<15:0>: Secondary Phase Offset for PWMxL Output Pin bits (used in Independent PWM mode only) Note 1: If PWMCONx<ITB> = 0, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01 or 10); SPHASEx<15:0> = Not used • True Independent Output mode (IOCONx<PMOD> = 11); PHASEx<15:0> = Phase-shift value for PWMxL only 2: If PWMCONx<ITB> = 1, the following applies based on the mode of operation: • Complementary, Redundant and Push-Pull Output mode (IOCONx<PMOD> = 00, 01, or 10); SPHASEx<15:0> = Not used • True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11); PHASEx<15:0> = Independent Time Base period value for PWMxL only  2008-2014 Microchip Technology Inc. DS70000318G-page 209

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 .REGISTER 15-11: DTRx: PWMx DEAD-TIME REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DTRx<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTRx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits REGISTER 15-12: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ALTDTRx<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALTDTR <7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 ALTDTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits DS70000318G-page 210  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-13: TRGCONx: PWMx TRIGGER CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — bit 15 bit 8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTM(1) — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 TRGDIV<3:0>: Trigger # Output Divider bits 1111 = Trigger output for every 16th trigger event 1110 = Trigger output for every 15th trigger event 1101 = Trigger output for every 14th trigger event 1100 = Trigger output for every 13th trigger event 1011 = Trigger output for every 12th trigger event 1010 = Trigger output for every 11th trigger event 1001 = Trigger output for every 10th trigger event 1000 = Trigger output for every 9th trigger event 0111 = Trigger output for every 8th trigger event 0110 = Trigger output for every 7th trigger event 0101 = Trigger output for every 6th trigger event 0100 = Trigger output for every 5th trigger event 0011 = Trigger output for every 4th trigger event 0010 = Trigger output for every 3rd trigger event 0001 = Trigger output for every 2nd trigger event 0000 = Trigger output for every trigger event bit 11-8 Unimplemented: Read as ‘0’ bit 7 DTM: Dual Trigger Mode bit(1) 1 = Secondary trigger event is combined with the primary trigger event to create the PWM trigger. 0 = Secondary trigger event is not combined with the primary trigger event to create the PWM trigger; two separate PWM triggers are generated bit 6 Unimplemented: Read as ‘0’ bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits 111111 = Wait 63 PWM cycles before generating the first trigger event after the module is enabled • • • 000010 = Wait 1 PWM cycles before generating the first trigger event after the module is enabled 000001 = Wait 1 PWM cycle before generating the first trigger event after the module is enabled 000000 = Wait 0 PWM cycles before generating the first trigger event after the module is enabled Note 1: The secondary generator cannot generate PWM trigger interrupts.  2008-2014 Microchip Technology Inc. DS70000318G-page 211

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R E GISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PENH PENL POLH POLL PMOD1(1) PMOD0(1) OVRENH OVRENL bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OVRDAT1 OVRDAT0 FLTDAT1(2) FLTDAT0(2) CLDAT1(2) CLDAT0(2) SWAP OSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PENH: PWMH Output Pin Ownership bit 1 = PWM module controls the PWMxH pin 0 = GPIO module controls the PWMxH pin bit 14 PENL: PWML Output Pin Ownership bit 1 = PWM module controls the PWMxL pin 0 = GPIO module controls the PWMxL pin bit 13 POLH: PWMH Output Pin Polarity bit 1 = PWMxH pin is active-low 0 = PWMxH pin is active-high bit 12 POLL: PWML Output Pin Polarity bit 1 = PWMxL pin is active-low 0 = PWMxL pin is active-high bit 11-10 PMOD<1:0>: PWM # I/O Pin Mode bits(1) 11 = PWM I/O pin pair is in the True Independent Output mode 10 = PWM I/O pin pair is in the Push-Pull Output mode 01 = PWM I/O pin pair is in the Redundant Output mode 00 = PWM I/O pin pair is in the Complementary Output mode bit 9 OVRENH: Override Enable for PWMxH Pin bit 1 = OVRDAT<1> provides data for output on the PWMxH pin 0 = PWM generator provides data for the PWMxH pin bit 8 OVRENL: Override Enable for PWMxL Pin bit 1 = OVRDAT<0> provides data for output on the PWMxL pin 0 = PWM generator provides data for the PWMxL pin bit 7-6 OVRDAT<1:0>: Data for PWMxH and PWMxL Pins if Override is Enabled bits If OVERENH = 1, then OVRDAT<1> provides data for PWMxH If OVERENL = 1, then OVRDAT<0> provides data for PWMxL bit 5-4 FLTDAT<1:0>: State for PWMxH and PWMxL Pins if FLTMOD is Enabled bits(2) FCLCONx<IFLTMOD> = 0: Normal Fault mode: If Fault is active, then FLTDAT<1> provides the state for PWMxH If Fault is active, then FLTDAT<0> provides the state for PWMxL FCLCONx<IFLTMOD> = 1: Independent Fault mode: If current-limit is active, then FLTDAT<1> provides data for PWMxH If Fault is active, then FLTDAT<0> provides the state for PWMxL Note 1: These bits should be changed only when PTEN=0. Changing the clock selection during operation will yield unpredictable results. 2: The state represents the active/inactive state of the PWM module depending on the POLH and POLL bit settings. DS70000318G-page 212  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER (CONTINUED) bit 3-2 CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMODE is Enabled bits(2) FCLCONx<IFLTMOD> = 0: Normal Fault mode: If current-limit is active, then CLDAT<1> provides the state for PWMxH If current-limit is active, then CLDAT<0> provides the state for PWMxL FCLCONx<IFLTMOD> = 1: Independent Fault mode: CLDAT<1:0> bits are ignored. bit 1 SWAP<1:0>: Swap PWMxH and PWMxL pins 1 = PWMxH output signal is connected to the PWMxL pin and the PWMxL signal is connected to the PWMxH pins 0 = PWMxH and PWMxL pins are mapped to their respective pins bit 0 OSYNC: Output Override Synchronization bit 1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base 0 = Output overrides via the OVDDAT<1:0> bits occur on the next CPU clock boundary Note 1: These bits should be changed only when PTEN=0. Changing the clock selection during operation will yield unpredictable results. 2: The state represents the active/inactive state of the PWM module depending on the POLH and POLL bit settings.  2008-2014 Microchip Technology Inc. DS70000318G-page 213

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFLTMOD CLSRC4(2,3) CLSRC3(2,3) CLSRC2(2,3) CLSRC1(2,3) CLSRC0(2,3) CLPOL(1) CLMOD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTSRC4(2,3) FLTSRC3(2,3) FLTSRC2(2,3) FLTSRC1(2,3) FLTSRC0(2,3) FLTPOL(1) FLTMOD1 FLTMOD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IFLTMOD: Independent Fault Mode Enable bit 1 = Independent Fault mode: Current-limit input maps FLTDAT1 to PWMxH output and the Fault input maps FLTDAT0 to the PWMxL output. The CLDAT<1:0> bits are not used for override functions. 0 = Normal Fault mode: Current-limit feature maps CLDAT<1:0> bits to the PWMxH and PWMxL outputs. The PWM Fault feature maps FLTDAT<1:0> to the PWMxH and PWMxL outputs. bit 14-10 CLSRC<4:0>: Current-Limit Control Signal Source Select for PWM # Generator bits(2,3) 11111 = Reserved • • • 01000 = Reserved 00111 = Fault 8 00110 = Fault 7 00101 = Fault 6 00100 = Fault 5 00011 = Fault 4 00010 = Fault 3 00001 = Fault 2 00000 = Fault 1 bit 9 CLPOL: Current-Limit Polarity for PWM Generator # bit(1) 1 = The selected current-limit source is active-low 0 = The selected current-limit source is active-high bit 8 CLMOD: Current-Limit Mode Enable bit for PWM Generator # bit 1 = Current-limit function is enabled 0 = Current-limit function is disabled Note 1: These bits should be changed only when PTEN=0. Changing the clock selection during operation will yield unpredictable results. 2: When Independent Fault mode is enabled (IFLTMOD = 1), and Fault 1 is used for Current-Limit mode (CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs. 3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode (FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs. DS70000318G-page 214  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED) bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select for PWM Generator # bits(2,3) 11111 = Reserved • • • 01000 = Reserved 00111 = Fault 8 00110 = Fault 7 00101 = Fault 6 00100 = Fault 5 00011 = Fault 4 00010 = Fault 3 00001 = Fault 2 00000 = Fault 1 bit 2 FLTPOL: Fault Polarity for PWM Generator # bit(1) 1 = The selected Fault source is active-low 0 = The selected Fault source is active-high bit 1-0 FLTMOD<1:0>: Fault Mode for PWM Generator # bits 11 = Fault input is disabled 10 = Reserved 01 = The selected Fault source forces the PWMxH and PWMxL pins to FLTDAT values (cycle) 00 = The selected Fault source forces the PWMxH and PWMxL pins to FLTDAT values (latched condition) Note 1: These bits should be changed only when PTEN=0. Changing the clock selection during operation will yield unpredictable results. 2: When Independent Fault mode is enabled (IFLTMOD = 1), and Fault 1 is used for Current-Limit mode (CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused Fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs. 3: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode (FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an unused current-limit source to prevent the current-limit source from disabling both the PWMxH and PWMxL outputs.  2008-2014 Microchip Technology Inc. DS70000318G-page 215

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R E GISTER 15-16: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 TRGCMP<7:3> — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 TRGCMP<15:3>: Trigger Control Value bits When primary PWM functions in the local time base, this register contains the compare values that can trigger the ADC module. bit 2-0 Unimplemented: Read as ‘0’ REGISTER 15-17: STRIGx: PWMx SECONDARY TRIGGER COMPARE VALUE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STRGCMP<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 STRGCMP<7:3> — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 STRGCMP<15:3>: Secondary Trigger Control Value bits When secondary PWM functions in the local time base, this register contains the compare values that can trigger the ADC module. bit 2-0 Unimplemented: Read as ‘0’ DS70000318G-page 216  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-18: LEBCONx: LEADING-EDGE BLANKING CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB6 LEB5 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 LEB4 LEB3 LEB2 LEB1 LEB0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PHR: PWMxH Rising Edge Trigger Enable bit 1 = Rising edge of PWMxH will trigger the LEB counter 0 = LEB ignores the rising edge of PWMxH bit 14 PHF: PWMH Falling Edge Trigger Enable bit 1 = Falling edge of PWMxH will trigger the LEB counter 0 = LEB ignores the falling edge of PWMxH bit 13 PLR: PWML Rising Edge Trigger Enable bit 1 = Rising edge of PWMxL will trigger the LEB counter 0 = LEB ignores the rising edge of PWMxL bit 12 PLF: PWML Falling Edge Trigger Enable bit 1 = Falling edge of PWMxL will trigger the LEB counter 0 = LEB ignores the falling edge of PWMxL bit 11 FLTLEBEN: Fault Input LEB Enable bit 1 = Leading-Edge Blanking is applied to selected Fault input 0 = Leading-Edge Blanking is not applied to selected Fault input bit 10 CLLEBEN: Current-Limit LEB Enable bit 1 = Leading-Edge Blanking is applied to selected current-limit input 0 = Leading-Edge Blanking is not applied to selected current-limit input bit 9-3 LEB<6:0>: Leading-Edge Blanking for Current-Limit and Fault Inputs bits The value is 8.32 nsec increments. bit 2-0 Unimplemented: Read as ‘0’ Note 1: Configure this register in word format.  2008-2014 Microchip Technology Inc. DS70000318G-page 217

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-19: PWMCAPx: PRIMARY PWMx TIME BASE CAPTURE REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PWMCAP<15:8>(1,2) bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 U-0 U-0 U-0 PWMCAP<7:3>(1,2) — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 PWMCAP<15:3>: Captured PWM Time Base Value bits(1,2) The value in this register represents the captured PWM time base value when a leading edge is detected on the current-limit input. bit 2-0 Unimplemented: Read as ‘0’ Note 1: The capture feature is only available on the primary output (PWMxH). 2: This feature is active only after LEB processing on the current-limit input signal is complete. DS70000318G-page 218  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 16.0 SERIAL PERIPHERAL The Serial Peripheral Interface (SPI) module is a INTERFACE (SPI) synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These Note 1: This data sheet summarizes the features peripheral devices can be serial EEPROMs, shift of the dsPIC33FJ06GS101/X02 and registers, display drivers, Analog-to-Digital Converters dsPIC33FJ16GSX02/X04 families of and so on. The SPI module is compatible with SPI and devices. It is not intended to be a SIOP from Motorola®. comprehensive reference source. To The SPI module consists of a 16-bit shift register, complement the information in this data SPIxSR (where x = 1), used for shifting data in and out, sheet, refer to “Serial Peripheral and a buffer register, SPIxBUF. A control register, Interface (SPI)” (DS70206) in the SPIxCON, configures the module. Additionally, a status “dsPIC33F/PIC24H Family Reference register, SPIxSTAT, indicates status conditions. Manual”, which is available on the The serial interface consists of the following four pins: Microchip website (www.microchip.com). • SDIx (Serial Data Input) 2: Some registers and associated bits • SDOx (Serial Data Output) described in this section may not be available on all devices. Refer to • SCKx (Shift Clock Input Or Output) Section4.0 “Memory Organization” in • SSx (Active-Low Slave Select). this data sheet for device-specific register In Master mode operation, SCK is a clock output; in and bit information. Slave mode, it is a clock input. FIGURE 16-1: SPIx MODULE BLOCK DIAGRAM SCKx 1:1 to 1:8 1:1/4/16/64 Secondary Primary FCY Prescaler Prescaler SSx Sync Control Select Control Clock Edge SPIxCON1<1:0> Shift Control SPIxCON1<4:2> SDOx Enable SDIx bit 0 Master Clock SPIxSR Transfer Transfer SPIxRXB SPIxTXB SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus  2008-2014 Microchip Technology Inc. DS70000318G-page 219

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 SPIEN — SPISIDL — — — — — bit 15 bit 8 U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0 — SPIROV — — — — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: SPIx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 SPIROV: SPIx Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred bit 5-2 Unimplemented: Read as ‘0’ bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty. Automatically set in hardware when CPU writes the SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty. Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads the SPIxBUF location, reading SPIxRXB. DS70000318G-page 220  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(3) CKP MSTEN SPRE2(2) SPRE1(2) SPRE0(2) PPRE1(2) PPRE0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCKx Pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled; pin functions as I/O 0 = Internal SPI clock is enabled bit 11 DISSDO: Disable SDOx Pin bit 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. bit 8 CKE: SPIx Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) bit 7 SSEN: Slave Select Enable bit (Slave mode)(3) 1 = SSx pin is used for Slave mode 0 = SSx pin is not used by module; pin controlled by port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: Do not set both primary and secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1.  2008-2014 Microchip Technology Inc. DS70000318G-page 221

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(2) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(2) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: Do not set both primary and secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. DS70000318G-page 222  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enabled (SSx pin used as frame sync pulse input/output) 0 = Framed SPIx support is disabled bit 14 SPIFSD: SPIx Frame Sync Pulse Direction Control bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) bit 13 FRMPOL: Frame Sync Pulse Polarity bit 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low bit 12-2 Unimplemented: Read as ‘0’ bit 1 FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application  2008-2014 Microchip Technology Inc. DS70000318G-page 223

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 224  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 17.0 INTER-INTEGRATED CIRCUIT The I2C module has a 2-pin interface, where: (I2C™) • The SCLx pin is clock • The SDAx pin is data Note1: This data sheet summarizes the features The I2C module offers the following key features: of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of • I2C interface supporting both Master and Slave devices. It is not intended to be a modes of operation comprehensive reference source. To • I2C Slave mode supports 7-bit and 10-bit addressing complement the information in this • I2C Master mode supports 7-bit and 10-bit data sheet, refer to “Inter-Integrated addressing Circuit (I2C™)” (DS70000195) in the • I2C port allows bidirectional transfers between “dsPIC33/PIC24 Family Reference Man- master and slaves ual”, which is available on the Microchip • Serial clock synchronization for I2C port can be used web site (www.microchip.com). as a handshake mechanism to suspend and resume 2: Some registers and associated bits serial transfer (SCLREL control) described in this section may not be • I2C supports multi-master operation, detects bus available on all devices. Refer to collision and arbitrates accordingly Section4.0 “Memory Organization” in this data sheet for device-specific register 17.1 Operating Modes and bit information. The hardware fully implements all the master and slave The Inter-Integrated Circuit (I2C) module provides functions of the I2C Standard and Fast mode complete hardware support for both Slave and specifications, as well as 7-bit and 10-bit addressing. Multi-Master modes of the I2C serial communication standard with a 16-bit interface. The I2C module can operate either as a slave or a master on an I2C bus. The following types of I2C operation are supported: • I2C slave operation with 7-bit addressing • I2C slave operation with 10-bit addressing • I2C master operation with 7-bit or 10-bit addressing  2008-2014 Microchip Technology Inc. DS70000318G-page 225

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 17-1: I2Cx BLOCK DIAGRAM (X = 1) Internal Data Bus I2CxRCV Read Shift SCLx Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation I2CxSTAT c gi Read o CDoellitseicotn ntrol L Write o C I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read ShiftClock Reload Control Write BRG Down Counter I2CxBRG Read TCY/2 DS70000318G-page 226  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 17.2 I2C Registers I2CxCON and I2CxSTAT are control and status registers. The I2CxCON register is readable and writable. The lower six bits of I2CxSTAT are read-only. The remaining bits of the I2CxSTAT are read/write: • I2CxRSR is the shift register used for shifting data internal to the module and the user application has no access to it • I2CxRCV is the receive buffer and the register to which data bytes are written, or from which data bytes are read • I2CxTRN is the transmit register to which bytes are written during a transmit operation • The I2CxADD register holds the slave address • A status bit, ADD10, indicates 10-Bit Addressing mode • The I2CxBRG acts as the Baud Rate Generator (BRG) reload value In receive operations, I2CxRSR and I2CxRCV together form a double-buffered receiver. When I2CxRSR receives a complete byte, it is transferred to I2CxRCV, and an interrupt pulse is generated.  2008-2014 Microchip Technology Inc. DS70000318G-page 227

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module, and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module; all I2C™ pins are controlled by port functions. bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit 1 = Discontinues module operation when device enters an Idle mode 0 = Continues module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Releases SCLx clock 0 = Holds SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave transmission. bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = IPMI mode is enabled; all addresses are Acknowledged 0 = IPMI mode is disabled bit 10 A10M: 10-Bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control is disabled 0 = Slew rate control is enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with SMBus specification 0 = Disables SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address is disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with the SCLREL bit. 1 = Enables software or receive clock stretching 0 = Disables software or receive clock stretching DS70000318G-page 228  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit. Hardware is clear at end of master Acknowledge sequence. 0 = Acknowledge sequence is not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware is clear at end of eighth bit of master receive data byte. 0 = Receive sequence is not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on SDAx and SCLx pins. Hardware is clear at end of master Stop sequence. 0 = Stop condition is not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware is clear at end of master Repeated Start sequence. 0 = Repeated Start condition is not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at end of master Start sequence. 0 = Start condition is not in progress  2008-2014 Microchip Technology Inc. DS70000318G-page 229

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HSC R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HS = Hardware Settable bit bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C™ master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware is set or clear at end of slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware is set at beginning of master transmission. Hardware is clear at end of slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware is set at detection of bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware is set when address matches general call address. Hardware is clear at Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware is set at match of 2nd byte of matched 10-bit address. Hardware is clear at Stop detection. bit 7 IWCOL: I2Cx Write Collision Detect bit 1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware is set at occurrence of write to I2CxTRN while busy (cleared by software). bit 6 I2COV: I2Cx Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware is set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was a device address Hardware is clear at device address match. Hardware is set by reception of slave byte. DS70000318G-page 230  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. bit 2 R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read – indicates data transfer is output from slave 0 = Write – indicates data transfer is input to slave Hardware is set or clear after reception of an I2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive is complete, I2CxRCV is full 0 = Receive is not complete, I2CxRCV is empty Hardware is set when I2CxRCV is written with a received byte. Hardware is clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit is in progress, I2CxTRN is full 0 = Transmit is complete, I2CxTRN is empty Hardware is set when software writes to I2CxTRN. Hardware is clear at completion of data transmission.  2008-2014 Microchip Technology Inc. DS70000318G-page 231

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK<9:0>: Mask for Address bit x Select bits 1 = Enables masking for bit x of incoming message address; bit match is not required in this position 0 = Disables masking for bit x; bit match is required in this position DS70000318G-page 232  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 18.0 UNIVERSAL ASYNCHRONOUS The primary features of the UART module are: RECEIVER TRANSMITTER • Full-Duplex, 8-Bit or 9-Bit Data Transmission (UART) through the UxTX and UxRX Pins • Even, Odd or No Parity Options (for 8-bit data) Note1: This data sheet summarizes the features • One or Two Stop bits of the dsPIC33FJ06GS101/X02 and • Hardware Flow Control Option with UxCTS and dsPIC33FJ16GSX02/X04 family of UxRTS Pins devices. It is not intended to be a • Fully Integrated Baud Rate Generator with 16-Bit comprehensive reference source. To Prescaler complement the information in this data • Baud Rates Ranging from 12.5Mbps to 38bps at sheet, refer to “UART” (DS70188) in the 50MIPS “dsPIC33F/PIC24H Family Reference Manual”, which is available on the • 4-Deep First-In First-Out (FIFO) Transmit Data Microchip web site (www.microchip.com). Buffer • 4-Deep FIFO Receive Data Buffer 2: Some registers and associated bits described in this section may not be • Parity, Framing and Buffer Overrun Error Detection available on all devices. Refer to • Support for 9-Bit mode with Address Detect Section4.0 “Memory Organization” in (9thbit =1) this data sheet for device-specific register • Transmit and Receive Interrupts and bit information. • A Separate Interrupt for all UART Error Conditions The Universal Asynchronous Receiver Transmitter • Loopback mode for Diagnostic Support (UART) module is one of the serial I/O modules • Support for Sync and Break Characters available in the dsPIC33FJ06GS101/X02 and • Support for Automatic Baud Rate Detection dsPIC33FJ16GSX02/X04 device families. The UART • IrDA Encoder and Decoder Logic is a full-duplex, asynchronous system that can commu- • 16x Baud Clock Output for IrDA® Support nicate with peripheral devices, such as personal computers, LIN/J2602, RS-232 and RS-485 interfaces. A simplified block diagram of the UART module is The module also supports a hardware flow control shown in Figure1. The UART module consists of these option with the UxCTS and UxRTS pins and also key hardware elements: includes an IrDA® encoder and decoder. • Baud Rate Generator • Asynchronous Transmitter • Asynchronous Receiver FIGURE 1: UART1 SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® Hardware Flow Control U1RTS/BCLK1 U1CTS UART Receiver U1RX UART Transmitter U1TX  2008-2014 Microchip Technology Inc. DS70000318G-page 233

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UARTEN(1) — USIDL IREN(2) RTSMD — UEN1 UEN0 bit 15 bit 8 R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches, UARTx power consumption isminimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: UARTx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder are enabled 0 = IrDA encoder and decoder are disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin is controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins are controlled by port latches bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt is generated on falling edge, bit is cleared in hardware on the following rising edge 0 = No wake-up is enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enables Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h) before other data; cleared in hardware upon completion 0 = Baud rate measurement is disabled or has completed Note 1: Refer to “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH=0). DS70000318G-page 234  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 URXINV: UARTx Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: Refer to “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH=0).  2008-2014 Microchip Technology Inc. DS70000318G-page 235

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware Clearable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: UARTx Transmit Polarity Inversion bit If IREN = 0: 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ If IREN = 1: 1 = IrDA® encoded UxTX Idle state is ‘1’ 0 = IrDA encoded UxTX Idle state is ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: UARTx Transmit Break bit 1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission is disabled or has completed bit 10 UTXEN: UARTx Transmit Enable bit(1) 1 = Transmit is enabled, UxTX pin is controlled by UARTx 0 = Transmit is disabled, any pending transmission is aborted and buffer is reset; UxTX pin is controlled by port bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full; at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits 11 = Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive buffer; receive buffer has one or more characters Note 1: Refer to “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. DS70000318G-page 236  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data=1) 1 = Address Detect mode is enable; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed; clearing a previously set OERR bit (10 transition) will reset the receiver buffer and the UxRSR to the empty state bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation.  2008-2014 Microchip Technology Inc. DS70000318G-page 237

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 238  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 19.0 HIGH-SPEED 10-BIT This ADC works with the high-speed PWM module in ANALOG-TO-DIGITAL power control applications that require high-frequency control loops. This module can sample and convert two CONVERTER (ADC) analog inputs in a 0.5 microsecond when two SARs are used. This small conversion delay reduces the “phase Note1: This data sheet summarizes the features lag” between measurement and control system of the dsPIC33FJ06GS101/X02 and response. dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a compre- Up to five inputs may be sampled at a time (four inputs hensive reference source. To complement from the dedicated Sample-and-Hold circuits and one the information in this data sheet, refer to from the shared Sample-and-Hold circuit). If multiple “High-Speed 10-Bit Analog-to-Digital inputs request conversion, the ADC will convert them in Converter (ADC)” (DS70000321) in the a sequential manner, starting with the lowest order “dsPIC33/PIC24 Family Reference Man- input. ual”, which is available on the Microchip This ADC design provides each pair of analog inputs web site (www.microchip.com). (AN1, AN0), (AN3, AN2),..., the ability to specify its own 2: Some registers and associated bits trigger source out of a maximum of sixteen different described in this section may not be trigger sources. This capability allows this ADC to available on all devices. Refer to sample and convert analog inputs that are associated with PWM generators operating on Independent Time Section4.0 “Memory Organization” in Bases (ITBs). this data sheet for device-specific register and bit information. The user application typically requires synchronization between analog data sampling and PWM output to the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 application circuit. The very high-speed operation of devices provide high-speed, successive approximation this ADC module allows “data on demand”. Analog-to-Digital conversions to support applications, In addition, several hardware features have been such as AC/DC and DC/DC power converters. added to the peripheral interface to improve real-time performance in a typical DSP-based application. 19.1 Features Overview • Result alignment options The ADC module comprises the following features: • Automated sampling • 10-bit resolution • External conversion start control • Unipolar inputs • Two internal inputs to monitor the INTREF internal • Up to two Successive Approximation Registers reference and the EXTREF input signal (SARs) 19.3 Module Functionality • Up to 12 external input channels • Up to two internal analog inputs The high-speed, 10-bit ADC module is designed to • Dedicated result register for each analog input support power conversion applications when used with the high-speed PWM module. The ADC may have one • ±1 LSB accuracy at 3.3V or two SAR modules, depending on the device variant. • Single supply operation If two SARs are present on a device, two conversions • 4 Msps conversion rate at 3.3V (devices with can be processed at a time, yielding 4 Msps conversion two SARs) rate. If only one SAR is present on a device, only one • 2 Msps conversion rate at 3.3V (devices with conversion can be processed at a time, yielding 2 Msps one SAR) conversion rate. The high-speed 10-bit ADC produces • Low-power CMOS technology two 10-bit conversion results in a 0.5 microsecond. The ADC module supports up to 12 external analog 19.2 Module Description inputs and two internal analog inputs. To monitor reference voltage, two internal inputs, AN12 and AN13, This ADC module is designed for applications that require are connected to the EXTREF and INTREF voltages, low latency between the request for conversion and the respectively. resultant output data. Typical applications include: The analog reference voltage is defined as the device • AC/DC power supplies supply voltage (AVDD/AVSS). • DC/DC Converters • Power Factor Correction (PFC) Block diagrams of the ADC module are shown in Figure19-1 through Figure19-6.  2008-2014 Microchip Technology Inc. DS70000318G-page 239

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-1: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS101 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 AN2 e c CSoArRe DataFormat Re1g6Si-siBxteitrs s Interfa u B AN1 Shared Sample-and-Hold AN3 AN6 AN7 DS70000318G-page 240  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-2: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS102 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 AN2 e c CSoArRe DataFormat Re1g6Si-siBxteitrs s Interfa u B AN1 Shared Sample-and-Hold AN3 AN4 AN5  2008-2014 Microchip Technology Inc. DS70000318G-page 241

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-3: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS202 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 AN2 e c AN12(1) CSoArRe DataFormat Re1Eg6iig-sBhteittrs s Interfa u (EXTREF) B AN1 Shared Sample-and-Hold AN3 AN4 AN5 AN13(2) (INTREF) Note1: AN12 (EXTREF) is an internal analog input. To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. 2: AN13 (INTREF) is an internal analog input and is not available on a pin. DS70000318G-page 242  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-4: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS402/404 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 AN2 AN4 e c CSoArRe DataFormat Re1Eg6igi-sbhtiettrs s Interfa u B AN1 AN3 Shared Sample-and-Hold AN5 AN6 AN7  2008-2014 Microchip Technology Inc. DS70000318G-page 243

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-5: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS502 DEVICES WITH TWO SARS Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 AN2 CSoArRe DataFormat Re1Fg6ii-vsBeteitrs AN4 AN6 Even Numbered Inputs with Shared S&H e c a AN12(1) erf (EXTREF) nt s I u B AN1 Odd Numbered Inputs with Shared S&H AN3 AANN57 CSoArRe DataFormat Re1Fg6ii-vsBeteitrs AN13(2) (INTREF) Note1: AN12 (EXTREF) is an internal analog input. To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. 2: AN13 (INTREF) is an internal analog input and is not available on a pin. DS70000318G-page 244  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-6: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS504 DEVICES WITH TWO SARS Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 AN2 CSAorRe Dataormat RSe1g6ei-vsBeteintrs F AN4 AN6 AN8 Even Numbered Inputs e with Shared S&H ac erf nt s I AN10 Bu AN12(1) (EXTREF) AN1 Odd Numbered Inputs with Shared S&H AN3 CSoArRe DataFormat RSe1g6ei-vsBeteintrs AN5 AN7 AN9 AN11 AN13(2) (INTREF) Note1: AN12 (EXTREF) is an internal analog input. To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference. 2: AN13 (INTREF) is an internal analog input and is not available on a pin.  2008-2014 Microchip Technology Inc. DS70000318G-page 245

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 19.4 ADC Control Registers The ADCON register controls the operation of the ADC module. The ADSTAT register displays the The ADC module uses the following control and status status of the conversion processes. The ADPCFG registers: registers configure the port pins as analog inputs or • ADCON: Analog-to-Digital Control Register as digital I/O. The ADCPCx registers control the • ADSTAT: Analog-to-Digital Status Register triggering of the ADC conversions. See Register19-1 through Register19-8 for detailed bit configurations. • ADBASE: Analog-to-Digital Base Register(1,2) • ADPCFG: Analog-to-Digital Port Configuration Note: A unique feature of the ADC module is its Register ability to sample inputs in an asynchronous • ADCPC0: Analog-to-Digital Convert Pair Control manner. Individual Sample-and-Hold Register 0 circuits can be triggered independently of each other. • ADCPC1: Analog-to-Digital Convert Pair Control Register 1 • ADCPC2: Analog-to-Digital Convert Pair Control Register 2(1) • ADCPC3: Analog-to-Digital Convert Pair Control Register 3(1) DS70000318G-page 246  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-1: ADCON: ANALOG-TO-DIGITAL CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 ADON — ADSIDL SLOWCLK(1) — GSWTRG — FORM(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-1 R/W-1 EIE(1) ORDER(1,2) SEQSAMP(1,2) ASYNCSAMP(1) — ADCS2(1) ADCS1(1) ADCS0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: Analog-to-Digital Operating Mode bit 1 = Analog-to-Digital Converter (ADC) module is operating 0 = ADC Converter is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: ADC Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 SLOWCLK: Enable The Slow Clock Divider bit(1) 1 = ADC is clocked by the auxiliary PLL (ACLK) 0 = ADC is clock by the primary PLL (FVCO) bit 11 Unimplemented: Read as ‘0’ bit 10 GSWTRG: Global Software Trigger bit When this bit is set by the user, it will trigger conversions if selected by the TRGSRC<4:0> bits in the ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e., this bit is not auto-clearing). bit 9 Unimplemented: Read as ‘0’ bit 8 FORM: Data Output Format bit(1) 1 = Fractional (DOUT = dddd dddd dd00 0000) 0 = Integer (DOUT = 0000 00dd dddd dddd) bit 7 EIE: Early Interrupt Enable bit(1) 1 = Interrupt is generated after first conversion is completed 0 = Interrupt is generated after second conversion is completed bit 6 ORDER: Conversion Order bit(1,2) 1 = Odd numbered analog input is converted first, followed by conversion of even numbered input 0 = Even numbered analog input is converted first, followed by conversion of odd numbered input bit 5 SEQSAMP: Sequential Sample Enable bit(1,2) 1 = Shared Sample-and-Hold (S&H) circuit is sampled at the start of the second conversion if ORDER=0. If ORDER = 1, then the shared S&H is sampled at the start of the first conversion. 0 = Shared S&H is sampled at the same time the dedicated S&H is sampled if the shared S&H is not currently busy with an existing conversion process. If the shared S&H is busy at the time the dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion cycle. Note 1: These control bits can only be changed while ADC is disabled (ADON = 0). 2: These bits are only available on devices with one SAR.  2008-2014 Microchip Technology Inc. DS70000318G-page 247

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-1: ADCON: ANALOG-TO-DIGITAL CONTROL REGISTER (CONTINUED) bit 4 ASYNCSAMP: Asynchronous Dedicated S&H Sampling Enable bit(1) 1 = The dedicated S&H is constantly sampling and then terminates sampling as soon as the trigger pulse is detected 0 = The dedicated S&H starts sampling when the trigger event is detected and completes the sampling process in two ADC clock cycles bit 3 Unimplemented: Read as ‘0’ bit 2-0 ADCS<2:0>: Analog-to-Digital Conversion Clock Divider Select bits(1) 111 = FADC/8 110 = FADC/7 101 = FADC/6 100 = FADC/5 011 = FADC/4 (default) 010 = FADC/3 001 = FADC/2 000 = FADC/1 Note 1: These control bits can only be changed while ADC is disabled (ADON = 0). 2: These bits are only available on devices with one SAR. DS70000318G-page 248  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R E GISTER 19-2: ADSTAT: ANALOG-TO-DIGITAL STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS — P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY P0RDY bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6 P6RDY: Conversion Data for Pair 6 Ready bit Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 5 P5RDY: Conversion Data for Pair 5 Ready bit Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 4 P4RDY: Conversion Data for Pair 4 Ready bit Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 3 P3RDY: Conversion Data for Pair 3 Ready bit Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 2 P2RDY: Conversion Data for Pair 2 Ready bit Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 1 P1RDY: Conversion Data for Pair 1 Ready bit Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 0 P0RDY: Conversion Data for Pair 0 Ready bit Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.  2008-2014 Microchip Technology Inc. DS70000318G-page 249

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-3: ADBASE: ANALOG-TO-DIGITAL BASE REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADBASE<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 ADBASE<7:1> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 ADBASE<15:1>: Analog-to-Digital Base bits This register contains the base address of the user’s ADC Interrupt Service Routine jump table. This register, when read, contains the sum of the ADBASE register contents and the encoded value of the PxRDY status bits. The encoder logic provides the bit number of the highest priority PxRDY bits, where P0RDY is the highest priority and P6RDY is the lowest priority. bit 0 Unimplemented: Read as ‘0’ Note 1: The encoding results are shifted left two bits, so bits 1-0 of the result are always zero. 2: As an alternative to using the ADBASE register, the ADCP0-6 ADC Pair Conversion Complete interrupts can be used to invoke A to D conversion completion routines for individual ADC input pairs. REGISTER 19-4: ADPCFG: ANALOG-TO-DIGITAL PORT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — PCFG<11:8>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG<7:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 PCFG<11:0>: Analog-to-Digital Port Configuration Control bits(1) 1 = Port pin in Digital mode; port read input is enabled, Analog-to-Digital input multiplexer is connected to AVSS 0 = Port pin in Analog mode; port read input is disabled, Analog-to-Digital samples the pin voltage Note 1: Not all PCFGx bits are available on all devices. See Figure19-1 through Figure19-6 for the available analog pins (PCFGx = ANx, where x = 0-11). DS70000318G-page 250  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 19-5: ADCPC0: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN1 PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN0 PEND0 SWTRG0 TRGSRC04 TRGSRC03 TRGSRC02 TRGSRC01 TRGSRC00 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN1: Interrupt Request Enable 1 bit 1 = Enables IRQ generation when requested conversion of Channels AN3 and AN2 is completed 0 = IRQ is not generated bit 14 PEND1: Pending Conversion Status 1 bit 1 = Conversion of Channels AN3 and AN2 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 13 SWTRG1: Software Trigger 1 bit 1 = Starts conversion of AN3 and AN2 (if selected by the TRGSRCx bits)(1) This bit is automatically cleared by hardware when the PEND1 bit is set. 0 = Conversion has not started Note 1: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, then the conversion will be performed when the conversion resources are available.  2008-2014 Microchip Technology Inc. DS70000318G-page 251

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-5: ADCPC0: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 0 (CONTINUED) bit 12-8 TRGSRC1<4:0>: Trigger 1 Source Selection bits Selects trigger source for conversion of Analog Channels AN3 and AN2. 11111 = Timer2 period match • • • 11011 = Reserved 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = Reserved • • • 10010 = Reserved 10001 = PWM Generator 4 secondary trigger is selected 10000 = PWM Generator 3 secondary trigger is selected 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = Reserved 01100 = Timer1 period match • • • 01000 = Reserved 00111 = PWM Generator 4 primary trigger is selected 00110 = PWM Generator 3 primary trigger is selected 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled bit 7 IRQEN0: Interrupt Request Enable 0 bit 1 = Enables IRQ generation when requested conversion of Channels AN1 and AN0 is completed 0 = IRQ is not generated bit 6 PEND0: Pending Conversion Status 0 bit 1 = Conversion of Channels AN1 and AN0 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 5 SWTRG0: Software Trigger 0 bit 1 = Starts conversion of AN1 and AN0 (if selected by the TRGSRCx bits)(1) This bit is automatically cleared by hardware when the PEND0 bit is set. 0 = Conversion has not started Note 1: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, then the conversion will be performed when the conversion resources are available. DS70000318G-page 252  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-5: ADCPC0: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 0 (CONTINUED) bit 4-0 TRGSRC0<4:0>: Trigger 0 Source Selection bits Selects trigger source for conversion of Analog Channels AN1 and AN0. 11111 = Timer2 period match • • • 11011 = Reserved 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = Reserved • • • 10010 = Reserved 10001 = PWM Generator 4 secondary trigger is selected 10000 = PWM Generator 3 secondary trigger is selected 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = Reserved 01100 = Timer1 period match • • • 01000 = Reserved 00111 = PWM Generator 4 primary trigger is selected 00110 = PWM Generator 3 primary trigger is selected 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled Note 1: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, then the conversion will be performed when the conversion resources are available.  2008-2014 Microchip Technology Inc. DS70000318G-page 253

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-6: ADCPC1: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN3(1) PEND3(1) SWTRG3(1) TRGSRC34(1) TRGSRC33(1) TRGSRC32(1) TRGSRC31(1) TRGSRC30(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN2(2) PEND2(2) SWTRG2(2) TRGSRC24(2) TRGSRC23(2) TRGSRC22(2) TRGSRC21(2) TRGSRC20(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN3: Interrupt Request Enable 3 bit(1) 1 = Enables IRQ generation when requested conversion of Channels AN7 and AN6 is completed 0 = IRQ is not generated bit 14 PEND3: Pending Conversion Status 3 bit(1) 1 = Conversion of Channels AN7 and AN6 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 13 SWTRG3: Software Trigger 3 bit(1) 1 = Starts conversion of AN7 and AN6 (if selected by the TRGSRCx bits)(3) This bit is automatically cleared by hardware when the PEND3 bit is set. 0 = Conversion has not started Note 1: These bits are available in the dsPIC33FJ16GS402/404, dsPIC33FJ16GS504, dsPIC33FJ16GS502 and dsPIC33FJ06GS101 devices only. 2: These bits are available in the dsPIC33FJ16GS502, dsPIC33FJ16GS504, dsPIC33FJ06GS102, dsPIC33FJ06GS202 and dsPIC33FJ16GS402/404 devices only. 3: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, then the conversion will be performed when the conversion resources are available. DS70000318G-page 254  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-6: ADCPC1: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) bit 12-8 TRGSRC3<4:0>: Trigger 3 Source Selection bits(1) Selects trigger source for conversion of Analog Channels AN7 and AN6. 11111 = Timer2 period match • • • 11011 = Reserved 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = Reserved • • • 10010 = Reserved 10001 = PWM Generator 4 secondary trigger is selected 10000 = PWM Generator 3 secondary trigger is selected 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = Reserved 01100 = Timer1 period match • • • 01000 = Reserved 00111 = PWM Generator 4 primary trigger is selected 00110 = PWM Generator 3 primary trigger is selected 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled bit 7 IRQEN2: Interrupt Request Enable 2 bit((2)) 1 = Enables IRQ generation when requested conversion of Channels AN5 and AN4 is completed 0 = IRQ is not generated bit 6 PEND2: Pending Conversion Status 2 bit((2)) 1 = Conversion of Channels AN5 and AN4 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 5 SWTRG2: Software Trigger 2 bit((2)) 1 = Starts conversion of AN5 and AN4 (if selected by the TRGSRCx bits)(3) This bit is automatically cleared by hardware when the PEND2 bit is set. 0 = Conversion has not started Note 1: These bits are available in the dsPIC33FJ16GS402/404, dsPIC33FJ16GS504, dsPIC33FJ16GS502 and dsPIC33FJ06GS101 devices only. 2: These bits are available in the dsPIC33FJ16GS502, dsPIC33FJ16GS504, dsPIC33FJ06GS102, dsPIC33FJ06GS202 and dsPIC33FJ16GS402/404 devices only. 3: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, then the conversion will be performed when the conversion resources are available.  2008-2014 Microchip Technology Inc. DS70000318G-page 255

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-6: ADCPC1: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) bit 4-0 TRGSRC2<4:0>: Trigger 2 Source Selection bits(2) Selects trigger source for conversion of Analog Channels AN5 and AN4. 11111 = Timer2 period match • • • 11011 = Reserved 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = Reserved • • • 10010 = Reserved 10001 = PWM Generator 4 secondary trigger is selected 10000 = PWM Generator 3 secondary trigger is selected 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = Reserved 01100 = Timer1 period match • • • 01000 = Reserved 00111 = PWM Generator 4 primary trigger is selected 00110 = PWM Generator 3 primary trigger is selected 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled Note 1: These bits are available in the dsPIC33FJ16GS402/404, dsPIC33FJ16GS504, dsPIC33FJ16GS502 and dsPIC33FJ06GS101 devices only. 2: These bits are available in the dsPIC33FJ16GS502, dsPIC33FJ16GS504, dsPIC33FJ06GS102, dsPIC33FJ06GS202 and dsPIC33FJ16GS402/404 devices only. 3: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, then the conversion will be performed when the conversion resources are available. DS70000318G-page 256  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-7: ADCPC2: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 2(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN5 PEND5 SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN4 PEND4 SWTRG4 TRGSRC44 TRGSRC43 TRGSRC42 TRGSRC41 TRGSRC40 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN5: Interrupt Request Enable 5 bit 1 = Enables IRQ generation when requested conversion of Channels AN11 and AN10 is completed 0 = IRQ is not generated bit 14 PEND5: Pending Conversion Status 5 bit 1 = Conversion of Channels AN11 and AN10 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 13 SWTRG5: Software Trigger 5 bit 1 = Starts conversion of AN11 and AN10 (if selected by the TRGSRCx bits)(2) This bit is automatically cleared by hardware when the PEND5 bit is set. 0 = Conversion has not started Note 1: This register is only implemented in the dsPIC33FJ16GS504 devices. 2: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, then the conversion will be performed when the conversion resources are available.  2008-2014 Microchip Technology Inc. DS70000318G-page 257

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-7: ADCPC2: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 2(1) (CONTINUED) bit 12-8 TRGSRC5<4:0>: Trigger 5 Source Selection bits Selects trigger source for conversion of Analog Channels AN11 and AN10. 11111 = Timer2 period match • • • 11011 = Reserved 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = Reserved • • • 10010 = Reserved 10001 = PWM Generator 4 secondary trigger is selected 10000 = PWM Generator 3 secondary trigger is selected 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = Reserved 01100 = Timer1 period match • • • 01000 = Reserved 00111 = PWM Generator 4 primary trigger is selected 00110 = PWM Generator 3 primary trigger is selected 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled bit 7 IRQEN4: Interrupt Request Enable 4 bit 1 = Enables IRQ generation when requested conversion of Channels AN9 and AN8 is completed 0 = IRQ is not generated bit 6 PEND4: Pending Conversion Status 4 bit 1 = Conversion of Channels AN9 and AN8 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 5 SWTRG4: Software Trigger 4 bit 1 = Starts conversion of AN9 and AN8 (if selected by the TRGSRCx bits)(2) This bit is automatically cleared by hardware when the PEND4 bit is set. 0 = Conversion has not started Note 1: This register is only implemented in the dsPIC33FJ16GS504 devices. 2: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, then the conversion will be performed when the conversion resources are available. DS70000318G-page 258  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-7: ADCPC2: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 2(1) (CONTINUED) bit 4-0 TRGSRC4<4:0>: Trigger 4 Source Selection bits Selects trigger source for conversion of Analog Channels AN9 and AN8. 11111 = Timer2 period match • • • 11011 = Reserved 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = Reserved • • • 10010 = Reserved 10001 = PWM Generator 4 secondary trigger is selected 10000 = PWM Generator 3 secondary trigger is selected 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = Reserved 01100 = Timer1 period match • • • 01000 = Reserved 00111 = PWM Generator 4 primary trigger is selected 00110 = PWM Generator 3 primary trigger is selected 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled Note 1: This register is only implemented in the dsPIC33FJ16GS504 devices. 2: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, then the conversion will be performed when the conversion resources are available.  2008-2014 Microchip Technology Inc. DS70000318G-page 259

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-8: ADCPC3: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 3(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQEN6 PEND6 SWTRG6 TRGSRC6<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IRQEN6: Interrupt Request Enable 6 bit 1 = Enables IRQ generation when requested conversion of Channels AN13 and AN12 is completed 0 = IRQ is not generated bit 6 PEND6: Pending Conversion Status 6 bit 1 = Conversion of Channels AN13 and AN 12 is pending; set when selected trigger is asserted 0 = Conversion is complete bit 5 SWTRG6: Software Trigger 6 bit 1 = Starts conversion of AN13 (INTREF) and AN12 (EXTREF) (if selected by the TRGSRCx bits)(2) This bit is automatically cleared by hardware when the PEND6 bit is set. 0 = Conversion has not started Note 1: This register is only implemented on the dsPIC33FJ16GS502 and dsPIC33FJ16GS504 devices. 2: The trigger source must be set as global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, conversion will be performed when the conversion resources are available. DS70000318G-page 260  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-8: ADCPC3: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 3(1) bit 4-0 TRGSRC6<4:0>: Trigger 6 Source Selection bits Selects trigger source for conversion of Analog Channels AN13 and AN12. 11111 = Timer2 period match • • • 11011 = Reserved 11010 = PWM Generator 4 current-limit ADC trigger 11001 = PWM Generator 3 current-limit ADC trigger 11000 = PWM Generator 2 current-limit ADC trigger 10111 = PWM Generator 1 current-limit ADC trigger 10110 = Reserved • • • 10010 = Reserved 10001 = PWM Generator 4 secondary trigger is selected 10000 = PWM Generator 3 secondary trigger is selected 01111 = PWM Generator 2 secondary trigger is selected 01110 = PWM Generator 1 secondary trigger is selected 01101 = Reserved 01100 = Timer1 period match • • • 01000 = Reserved 00111 = PWM Generator 4 primary trigger is selected 00110 = PWM Generator 3 primary trigger is selected 00101 = PWM Generator 2 primary trigger is selected 00100 = PWM Generator 1 primary trigger is selected 00011 = PWM Special Event Trigger is selected 00010 = Global software trigger is selected 00001 = Individual software trigger is selected 00000 = No conversion is enabled Note 1: This register is only implemented on the dsPIC33FJ16GS502 and dsPIC33FJ16GS504 devices. 2: The trigger source must be set as global software trigger prior to setting this bit to ‘1’. If other conversions are in progress, conversion will be performed when the conversion resources are available.  2008-2014 Microchip Technology Inc. DS70000318G-page 261

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 262  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 20.0 HIGH-SPEED ANALOG • Programmable output polarity COMPARATOR • Interrupt generation capability • DACOUT pin to provide DAC output Note1: This data sheet summarizes the • DAC has three ranges of operation: features of the dsPIC33FJ06GS101/X02 - AVDD/2 and dsPIC33FJ16GSX02/X04 families of - Internal Reference (INTREF) devices. It is not intended to be a comprehensive reference source. To - External Reference (EXTREF) complement the information in this data • ADC sample and convert trigger capability sheet, refer to “High-Speed Analog • Disable capability reduces power consumption Comparator” (DS70296) in the • Functional support for PWM module: “dsPIC33F/PIC24H Family Reference - PWM duty cycle control Manual”, which is available on the - PWM period control Microchip web site (www.microchip.com). - PWM Fault detect 2: Some registers and associated bits described in this section may not be 20.2 Module Description available on all devices. Refer to Section4.0 “Memory Organization” in Figure20-1 shows a functional block diagram of one this data sheet for device-specific register analog comparator from the SMPS comparator and bit information. module. The analog comparator provides high-speed operation with a typical delay of 20 ns. The comparator The dsPIC33F SMPS comparator module monitors has a typical offset voltage of ±5 mV. The negative current and/or voltage transients that may be too fast input of the comparator is always connected to the for the CPU and ADC to capture. DAC circuit. The positive input of the comparator is 20.1 Features Overview connected to an analog multiplexer that selects the desired source pin. The SMPS comparator module contains the following The analog comparator input pins are typically shared major features: with pins used by the Analog-to-Digital Converter (ADC) • 16 selectable comparator inputs module. Both the comparator and the ADC can use the same pins at the same time. This capability enables a • Up to four analog comparators user to measure an input voltage with the ADC and • 10-bit DAC for each analog comparator detect voltage transients with the comparator. FIGURE 20-1: HIGH-SPEED ANALOG COMPARATOR MODULE BLOCK DIAGRAM INSEL<1:0> ACMPx (Trigger to PWM)(1) CMPxA(1) Status CMPxB(1) M U CMPxC(1) X CMPx(1) 0 Pulse Glitch Filter Generator CMPxD(1) 1 RANGE CMPPOL AVDD/2 M INTREF(2) U DAC DACOUT Interrupt Request X 10 AVSS EXTREF(2) CMREF DACOE Note 1: x = 1, 2, 3 and 4. 2: For the INTREF and EXTREF values, refer to the DAC Module Specifications (Table24-43) in Section24.0 “Electrical Characteristics”.  2008-2014 Microchip Technology Inc. DS70000318G-page 263

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 20.3 Module Applications 20.5 Interaction with I/O Buffers This module provides a means for the SMPS dsPIC® If the comparator module is enabled and a pin has DSC devices to monitor voltage and currents in a been selected as the source for the comparator, then power conversion application. The ability to detect the chosen I/O pad must disable the digital input buffer transient conditions and stimulate the dsPIC DSC associated with the pad to prevent excessive currents processor and/or peripherals, without requiring the in the digital buffer due to analog input voltages. processor and ADC to constantly monitor voltages or 20.6 Digital Logic currents, frees the dsPIC DSC to perform other tasks. The comparator module has a high-speed comparator The CMPCONx register (see Register20-1) provides and an associated 10-bit DAC that provides a the control logic that configures the comparator programmable reference voltage to the inverting input module. The digital logic provides a glitch filter for the of the comparator. The polarity of the comparator out- comparator output to mask transient signals in less put is user-programmable. The output of the module than two instruction cycles. In Sleep or Idle mode, the can be used in the following modes: glitch filter is bypassed to enable an asynchronous • Generate an Interrupt path from the comparator to the interrupt controller. • Trigger an ADC Sample and Convert Process This asynchronous path can be used to wake-up the processor from Sleep or Idle mode. • Truncate the PWM Signal (current limit) • Truncate the PWM Period (current minimum) The comparator can be disabled while in Idle mode if the CMPSIDL bit is set. If a device has multiple • Disable the PWM Outputs (Fault latch) comparators, if any CMPSIDL bit is set, then the entire The output of the comparator module may be used in group of comparators will be disabled while in Idle multiple modes at the same time, such as: 1) generate mode. This behavior reduces complexity in the design an interrupt, 2) have the ADC take a sample and con- of the clock control logic for this module. vert it, and 3) truncate the PWM output in response to The digital logic also provides a one TCY width pulse a voltage being detected beyond its expected value. generator for triggering the ADC and generating The comparator module can also be used to wake-up interrupt requests. the system from Sleep or Idle mode when the analog The CMPDACx (see Register20-2) register provides input voltage exceeds the programmed threshold the digital input value to the reference DAC. voltage. If the module is disabled, the DAC and comparator are 20.4 DAC disabled to reduce power consumption. The range of the DAC is controlled through an analog 20.7 Comparator Input Range multiplexer that selects either AVDD/2, an internal ref- erence source, INTREF, or an external reference The comparator has a limitation for the input source, EXTREF. The full range of the DAC (AVDD/2) Common-Mode Range (CMR) of (AVDD – 1.5V), typical. will typically be used when the chosen input source pin This means that both inputs should not exceed this is shared with the ADC. The reduced range option range. As long as one of the inputs is within the (INTREF) will likely be used when monitoring current Common-Mode Range, the comparator output will be levels using a current sense resistor. Usually, the correct. However, any input exceeding the CMR measured voltages in such applications are small limitation will cause the comparator input to be saturated. (<1.25V); therefore the option of using a reduced ref- If both inputs exceed the CMR, the comparator output erence range for the comparator extends the available will be indeterminate. DAC resolution in these applications. The use of an external reference enables the user to connect to a 20.8 DAC Output Range reference that better suits their application. The DAC has a limitation for the maximum reference DACOUT, shown in Figure20-1, can only be voltage input of (AVDD – 1.6) volts. An external associated with a single comparator at a given time. reference voltage input should not exceed this value or Note: It should be ensured in software that the reference DAC output will become indeterminate. multiple DACOE bits are not set. The 20.9 Comparator Registers output on the DACOUT pin will be indeter- minate if multiple comparators enable the The comparator module is controlled by the following DAC output. registers: • CMPCONx: Comparator Control x Register • CMPDACx: Comparator DAC x Control Register DS70000318G-page 264  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R E GISTER 20-1: CMPCONx: COMPARATOR CONTROL x REGISTER R/W-0 U-0 R/W-0 r-0 r-0 r-0 r-0 R/W-0 CMPON — CMPSIDL r r r r DACOE bit 15 bit 8 R/W-0 R/W-0 R/W-0 r-0 R/W-0 r-0 R/W-0 R/W-0 INSEL1 INSEL0 EXTREF r CMPSTAT r CMPPOL RANGE bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMPON: Comparator Operating Mode bit 1 = Comparator module is enabled 0 = Comparator module is disabled (reduces power consumption) bit 14 Unimplemented: Read as ‘0’ bit 13 CMPSIDL: Comparator Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode. 0 = Continues module operation in Idle mode If a device has multiple comparators, any CMPSIDL bit set to ‘1’ disables ALL comparators while in Idle mode. bit 12-9 Reserved: Read as ‘0’ bit 8 DACOE: DAC Output Enable 1 = DAC analog voltage is output to the DACOUT pin(1) 0 = DAC analog voltage is not connected to the DACOUT pin bit 7-6 INSEL<1:0>: Input Source Select for Comparator bits 00 = Selects CMPxA input pin 01 = Selects CMPxB input pin 10 = Selects CMPxC input pin 11 = Selects CMPxD input pin bit 5 EXTREF: Enable External Reference bit 1 = External source provides reference to the DAC (maximum DAC voltage determined by the external voltage source) 0 = Internal reference sources provide reference to the DAC (maximum DAC voltage determined by the RANGE bit setting) bit 4 Reserved: Read as ‘0’ bit 3 CMPSTAT: Current State of Comparator Output Including CMPPOL Selection bit bit 2 Reserved: Read as ‘0’ bit 1 CMPPOL: Comparator Output Polarity Control bit 1 = Output is inverted 0 = Output is non-inverted bit 0 RANGE: Selects DAC Output Voltage Range bit 1 = High Range: Max DAC Value = AVDD/2, 1.65V at 3.3V AVDD 0 = Low Range: Max DAC Value = INTREF(2) Note 1: DACOUT can be associated only with a single comparator at any given time. The software must ensure that multiple comparators do not enable the DAC output by setting their respective DACOE bit. 2: Refer to the DAC Module Specifications (Table24-43) in Section24.0 “Electrical Characteristics” for the INTREF value.  2008-2014 Microchip Technology Inc. DS70000318G-page 265

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 R EGISTER 20-2: CMPDACx: COMPARATOR DAC x CONTROL REGISTER r-0 r-0 r-0 r-0 r-0 r-0 R/W-0 R/W-0 r r r r r r CMREF<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMREF<7:0> bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Reserved: Read as ‘0’ bit 9-0 CMREF<9:0>: Comparator Reference Voltage Select bits 1111111111 = (CMREF<9:0> * INTREF/1024) or (CMREF<9:0> * (AVDD/2)/1024) volts depending on the RANGE bit or (CMREF<9:0> * EXTREF/1024) if EXTREF is set • • • 0000000000 = 0.0 volts DS70000318G-page 266  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.0 SPECIAL FEATURES 21.1 Configuration Bits Note1: This data sheet summarizes the features dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 of the dsPIC33FJ06GS101/X02 and devices provide nonvolatile memory implementations dsPIC33FJ16GSX02/X04 devices. It is for device Configuration bits. Refer to “Device Config- not intended to be a comprehensive uration” (DS70194) in the “dsPIC33F/PIC24H Family reference source. To complement the Reference Manual” for more information on this information in this data sheet, refer to the implementation. “dsPIC33F/PIC24H Family Reference The Configuration bits can be programmed (read Manual”. Please see the Microchip web as‘0’), or left unprogrammed (read as ‘1’), to select site (www.microchip.com) for the latest various device configurations. These bits are mapped “dsPIC33F/PIC24H Family Reference starting at program memory location 0xF80000. Manual” sections. The individual Configuration bit descriptions for the 2: Some registers and associated bits Configuration registers are shown in Table21-2. described in this section may not be Note that address, 0xF80000, is beyond the user pro- available on all devices. Refer to gram memory space. It belongs to the configuration Section4.0 “Memory Organization” in memory space (0x800000-0xFFFFFF), which can only this data sheet for device-specific register be accessed using Table Reads and Table Writes. and bit information. The device Configuration register map is shown in dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Table21-1. devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • Flexible Configuration • Watchdog Timer (WDT) • Code Protection and CodeGuard™ Security • JTAG Boundary Scan Interface • In-Circuit Serial Programming™ (ICSP™) • In-Circuit Emulation • Brown-out Reset (BOR) TABLE 21-1: DEVICE CONFIGURATION REGISTER MAP Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0xF80000 FBS — — — — BSS2 BSS1 BSS0 BWRP 0xF80002 Reserved — — — — — — — — 0xF80004 FGS — — — — — GSS1 GSS0 GWRP 0xF80006 FOSCSEL IESO — — — FNOSC2 FNOSC1 FNOSC0 0xF80008 FOSC FCKSM1 FCKSM0 IOL1WAY — — OSCIOFNC POSCMD1 POSCMD0 0xF8000A FWDT FWDTEN WINDIS — WDTPRE WDTPOST3 WDTPOST2 WDTPOST1 WDTPOST0 0xF8000C FPOR — — — — Reserved(2) FPWRT2 FPWRT1 FPWRT0 0xF8000E FICD Reserved(1) JTAGEN — — — ICS1 ICS0 0xF80010 FUID0 User Unit ID Byte 0 0xF80012 FUID1 User Unit ID Byte 1 Legend: — = unimplemented bit, read as ‘0’. Note 1: These bits are reserved for use by development tools and must be programmed to ‘1’. 2: This bit reads the current programmed value.  2008-2014 Microchip Technology Inc. DS70000318G-page 267

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 21-2: dsPIC33F CONFIGURATION BITS DESCRIPTION Bit Field Register RTSP Effect Description BWRP FBS Immediate Boot Segment Program Flash Write Protection bit 1 = Boot segment can be written 0 = Boot segment is write-protected BSS<2:0> FBS Immediate Boot Segment Program Flash Code Protection Size bits x11 = No boot program Flash segment Boot Space is 256 Instruction Words (except interrupt vectors): 110 = Standard security; boot program Flash segment ends at 0x0003FE 010 = High security; boot program Flash segment ends at 0x0003FE Boot Space is 768 Instruction Words (except interrupt vectors): 101 = Standard security; boot program Flash segment ends at 0x0007FE 001 = High security; boot program Flash segment ends at 0x0007FE Boot Space is 1792 Instruction Words (except interrupt vectors): 100 = Standard security; boot program Flash segment ends at 0x000FFE 000 = High security; boot program Flash segment ends at 0x000FFE GSS<1:0> FGS Immediate General Segment Code-Protect bits 11 = User program memory is not code-protected 10 = Standard security 0x = High security GWRP FGS Immediate General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected IESO FOSCSEL Immediate Two-speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start-up device with user-selected oscillator source FNOSC<2:0> FOSCSEL If clock switch Initial Oscillator Source Selection bits is enabled, 111 = Internal Fast RC (FRC) Oscillator with Postscaler RTSP effect 110 = Internal Fast RC (FRC) Oscillator with Divide-by-16 is on any 101 = LPRC Oscillator device Reset; 100 = Reserved otherwise, 011 = Primary (XT, HS, EC) Oscillator with PLL Immediate 010 = Primary (XT, HS, EC) Oscillator 001 = Internal Fast RC (FRC) Oscillator with PLL 000 = FRC Oscillator FCKSM<1:0> FOSC Immediate Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled IOL1WAY FOSC Immediate Peripheral Pin Select Configuration bit 1 = Allows only one reconfiguration 0 = Allows multiple reconfigurations OSCIOFNC FOSC Immediate OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is the clock output 0 = OSC2 is the general purpose digital I/O pin DS70000318G-page 268  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 21-2: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register RTSP Effect Description POSCMD<1:0> FOSC Immediate Primary Oscillator Mode Select bits 11 = Primary Oscillator is disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode FWDTEN FWDT Immediate Watchdog Timer Enable bit 1 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the SWDTEN bit in the RCON register will have no effect) 0 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) WINDIS FWDT Immediate Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode WDTPRE FWDT Immediate Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 WDTPOST<3:0> FWDT Immediate Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 FPWRT<2:0> FPOR Immediate Power-on Reset Timer Value Select bits 111 = PWRT = 128 ms 110 = PWRT = 64 ms 101 = PWRT = 32 ms 100 = PWRT = 16 ms 011 = PWRT = 8 ms 010 = PWRT = 4 ms 001 = PWRT = 2 ms 000 = PWRT = Disabled JTAGEN FICD Immediate JTAG Enable bit 1 = JTAG is enabled 0 = JTAG is disabled ICS<1:0> FICD Immediate ICD Communication Channel Select Enable bits 11 = Communicates on PGEC1 and PGED1 10 = Communicates on PGEC2 and PGED2 01 = Communicates on PGEC3 and PGED3 00 = Reserved, do not use.  2008-2014 Microchip Technology Inc. DS70000318G-page 269

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.2 On-Chip Voltage Regulator 21.3 BOR: Brown-out Reset The dsPIC33FJ06GS101/X02 and The Brown-out Reset (BOR) module is based on an dsPIC33FJ16GSX02/X04 devices power their core internal voltage reference circuit. The main purpose of digital logic at a nominal2.5V. This can create a conflict the BOR module is to generate a device Reset when a for designs that are required to operate at a higher typical brown-out condition occurs. Brown-out conditions are voltage, such as3.3V. To simplify system design, all generally caused by glitches on the AC mains (for devices in the dsPIC33FJ06GS101/X02 and example, missing portions of the AC cycle waveform dsPIC33FJ16GSX02/X04 families incorporate an on-chip due to bad power transmission lines, or voltage sags regulator that allows the device to run its core logic from due to excessive current draw when a large inductive VDD. load is turned on). The regulator provides power to the core from the other A BOR generates a Reset pulse, which resets the VDD pins. When the regulator is enabled, a low-ESR device. The BOR selects the clock source, based on (less than 5 ohms) capacitor (such as tantalum or the device Configuration bit values (FNOSC<2:0> and ceramic) must be connected to the VCAP pin POSCMD<1:0>). (Figure21-1). This helps to maintain the stability of the If an oscillator mode is selected, the BOR activates the regulator. The recommended value for the filter Oscillator Start-up Timer (OST). The system clock is capacitor is provided in Table24-13 located in held until OST expires. If the PLL is used, the clock is Section24.1 “DC Characteristics”. held until the LOCK bit (OSCCON<5>) is ‘1’. Note: It is important for the low-ESR capacitor to Concurrently, the PWRT time-out (TPWRT) is applied be placed as close as possible to the VCAP before the internal Reset is released. If TPWRT = 0 and pin. a crystal oscillator is being used, then a nominal delay On a POR, it takes approximately 20s for the on-chip of TFSCM = 100 is applied. The total delay in this case voltage regulator to generate an output voltage. During is TFSCM. this time, designated as TSTARTUP, code execution is The BOR Status bit (RCON<1>) is set to indicate that a disabled. TSTARTUP is applied every time the device BOR has occurred. The BOR circuit continues to resumes operation after any power-down. operate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold FIGURE 21-1: CONNECTIONS FOR THE voltage. ON-CHIP VOLTAGE REGULATOR(1,2,3) 3.3V dsPIC33F VDD VCAP CEFC 10 µF VSS Tantalum Note 1: These are typical operating voltages. Refer to Table24-13 located in Section24.1 “DC Characteristics” for the full operating ranges of VDD. 2: It is important for the low-ESR capacitor to be placed as close as possible to the VCAP pin. 3: Typical VCAP pin voltage = 2.5V when VDD  VDDMIN. DS70000318G-page 270  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.4 Watchdog Timer (WDT) 21.4.2 SLEEP AND IDLE MODES For the dsPIC33FJ06GS101/X02 and If the WDT is enabled, it will continue to run during dsPIC33FJ16GSX02/X04 devices, the WDT is driven Sleep or Idle modes. When the WDT time-out occurs, by the LPRC oscillator. When the WDT is enabled, the the device will wake the device and code execution will clock source is also enabled. continue from where the PWRSAV instruction was executed. The corresponding SLEEP bit (RCON<3>) 21.4.1 PRESCALER/POSTSCALER or IDLE bit (RCON<2>) will need to be cleared in software after the device wakes up. The nominal WDT clock source from LPRC is 32kHz. This feeds a prescaler that can be configured for either 21.4.3 ENABLING WDT 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit. The WDT is enabled or disabled by the FWDTEN Configuration bit in the FWDT Configuration register. With a 32kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1ms in 5-bit mode, or When the FWDTEN Configuration bit is set, the WDT is 4ms in 7-bit mode. always enabled. A variable postscaler divides down the WDT prescaler The WDT can be optionally controlled in software when output and allows for a wide range of time-out periods. the FWDTEN Configuration bit has been programmed The postscaler is controlled by the WDTPOST<3:0> to ‘0’. The WDT is enabled in software by setting the Configuration bits (FWDT<3:0>) which allow the SWDTEN control bit (RCON<5>). The SWDTEN selection of 16 settings, from 1:1 to 1:32,768. Using the control bit is cleared on any device Reset. The software prescaler and postscaler, time-out periods ranging from WDT option allows the user application to enable the 1ms to 131 seconds can be achieved. WDT for critical code segments and disable the WDT during non-critical segments for maximum power The WDT, prescaler and postscaler are reset: savings. • On any device Reset Note: If the WINDIS bit (FWDT<6>) is cleared, • On the completion of a clock switch, whether the CLRWDT instruction should be executed invoked by software (i.e., setting the OSWEN bit by the application software only during the after changing the NOSC<2:0> bits) or by last 1/4 of the WDT period. This CLRWDT hardware (i.e., Fail-Safe Clock Monitor) window can be determined by using a timer. • When a PWRSAV instruction is executed If a CLRWDT instruction is executed before (i.e., Sleep or Idle mode is entered) this window, a WDT Reset occurs. • When the device exits Sleep or Idle mode to resume normal operation The WDT flag bit, WDTO (RCON<4>), is not automatically • By a CLRWDT instruction during normal execution cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. FIGURE 21-2: WDT BLOCK DIAGRAM All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle WDTPRE WDTPOST<3:0> SWDTEN WDT FWDTEN Wake-up RS RS 1 Prescaler Postscaler LPRC Clock (Divide-by-N1) (Divide-by-N2) WDT Reset 0 WINDIS WDT Window Select CLRWDT Instruction  2008-2014 Microchip Technology Inc. DS70000318G-page 271

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.5 JTAG Interface 21.7 In-Circuit Debugger The dsPIC33FJ06GS101/X02 and The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices implement a JTAG dsPIC33FJ16GSX02/X04 devices provide simple interface, which supports boundary scan device debugging functionality through the PGECx (Emula- testing. Detailed information on this interface will be tion/Debug Clock) and PGEDx (Emulation/Debug provided in future revisions of the document. Data) pin functions. Any of the three pairs of debugging clock/data pins can 21.6 In-Circuit Serial Programming be used: The dsPIC33FJ06GS101/X02 and • PGEC1 and PGED1 dsPIC33FJ16GSX02/X04 family of Digital Signal • PGEC2 and PGED2 Controllers can be serially programmed while in the • PGEC3 and PGED3 end application circuit. This is done with two lines for To use the in-circuit debugger function of the device, clock and data and three other lines for power, ground the design must implement ICSP connections to and the programming sequence. Serial programming allows customers to manufacture boards with MCLR, VDD, VSS, and the PGECx/PGEDx pin pair. In addition, when the feature is enabled, some of the unprogrammed devices and then program the Digital resources are not available for general use. These Signal Controller just before shipping the product. resources include the first 80 bytes of data RAM and Serial programming also allows the most recent two I/O pins. firmware or a custom firmware to be programmed. Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for details about In-Circuit Serial Programming (ICSP). Any of the three pairs of programming clock/data pins can be used: • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 DS70000318G-page 272  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.8 Code Protection and The code protection features are controlled by the CodeGuard™ Security Configuration registers: FBS and FGS. Secure segment and RAM protection is not implemented The dsPIC33FJ06GS101/X02 and in dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices offer the intermediate dsPIC33FJ16GSX02/X04 devices. implementation of CodeGuard™ Security. CodeGuard Security enables multiple parties to securely share Note: Refer to “CodeGuard™ Security” resources (memory, interrupts and peripherals) on a (DS70199) for further information on single chip. This feature helps protect individual CodeGuard Security usage, configuration Intellectual Property (IP) in collaborative system designs. and operation. When coupled with software encryption libraries, Code- Guard™ Security can be used to securely update Flash even when multiple IPs reside on a single chip. TABLE 21-3: CODE FLASH SECURITY TABLE 21-4: CODE FLASH SECURITY SEGMENT SIZES FOR SEGMENT SIZES FOR 6-Kbyte DEVICES 16-Kbyte DEVICES Configuration Bits Configuration Bits 000000h 000000h VS = 256 IW 0001FEh VS = 256 IW 0001FEh 000200h 000200h 0003FEh 0003FEh BSS<2:0> = x11 000400h BSS<2:0> = x11 000400h 0007FEh 0007FEh GS = 1792 IW 000800h 000800h 0K 000001F00F0Ehh 0K GS = 5376 IW 000001F00F0Ehh 002BFEh 002BFEh 000000h 000000h VS = 256 IW 0001FEh VS = 256 IW 0001FEh 000200h 000200h BS = 256 IW 0003FEh BS = 256 IW 0003FEh BSS<2:0> = x10 000400h BSS<2:0> = x10 000400h GS = 1536 IW 00000078F00Ehh 00000078F00Ehh 256 000FFEh 256 000FFEh 001000h 001000h GS = 5120 IW 002BFEh 002BFEh 000000h 000000h VS = 256 IW 0001FEh VS = 256 IW 0001FEh 000200h 000200h BSS<2:0> = x01 BS = 768 IW 00000034F00Ehh BSS<2:0> = x01 BS = 768 IW 00000034F00Ehh 0007FEh 0007FEh 768 GS = 1024 IW 0000008F0F0Ehh 768 0000008F0F0Ehh 001000h 001000h GS = 4608 IW 002BFEh 002BFEh 000000h 000000h VS = 256 IW 0001FEh VS = 256 IW 0001FEh 000200h 000200h BSS<2:0> = x00 BS = 1792 IW 00000034F00Ehh BSS<2:0> = x00 BS = 1792 IW 00000034F00Ehh 0007FEh 0007FEh 000800h 000800h 1792 000FFEh 1792 000FFEh 001000h 001000h GS = 3584 IW 002BFEh 002BFEh  2008-2014 Microchip Technology Inc. DS70000318G-page 273

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 274  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 22.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/shift instructions) have two operands: Note: This data sheet summarizes the features • The W register (with or without an address of the dsPIC33FJ06GS101/X02 and modifier) or file register (specified by the value of dsPIC33FJ16GSX02/X04 devices. It is ‘Ws’ or ‘f’) not intended to be a comprehensive • The bit in the W register or file register reference source. To complement the (specified by a literal value or indirectly by the information in this data sheet, refer to the contents of register ‘Wb’) latest sections in the “dsPIC33F/PIC24H Family Reference Manual”, which are The literal instructions that involve data movement can available on the Microchip web site use some of the following operands: (www.microchip.com). • A literal value to be loaded into a W register or file register (specified by ‘k’) The dsPIC33F instruction set is identical to that of the dsPIC30F. • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) Most instructions are a single program memory word (24 bits). Only three instructions require two program However, literal instructions that involve arithmetic or memory locations. logical operations use some of the following operands: Each single-word instruction is a 24-bit word, divided • The first source operand, which is a register ‘Wb’ into an 8-bit opcode, which specifies the instruction without any address modifier type and one or more operands, which further specify • The second source operand, which is a literal the operation of the instruction. value The instruction set is highly orthogonal and is grouped • The destination of the result (only if not the same into five basic categories: as the first source operand), which is typically a register ‘Wd’ with or without an address modifier • Word or byte-oriented operations The MAC class of DSP instructions can use some of the • Bit-oriented operations following operands: • Literal operations • The accumulator (A or B) to be used (required • DSP operations operand) • Control operations • The W registers to be used as the two operands Table22-1 shows the general symbols used in • The X and Y address space prefetch operations describing the instructions. • The X and Y address space prefetch destinations The dsPIC33F instruction set summary in Table22-2 • The accumulator write-back destination lists all the instructions, along with the status flags affected by each instruction. The other DSP instructions do not involve any multiplication and can include: Most word or byte-oriented W register instructions (including barrel shift instructions) have three • The accumulator to be used (required) operands: • The source or destination operand (designated as Wso or Wdo, respectively) with or without an • The first source operand, which is typically a address modifier register ‘Wb’ without any address modifier • The amount of shift specified by a W register, • The second source operand, which is typically a ‘Wn’, or a literal value register ‘Ws’ with or without an address modifier • The destination of the result, which is typically a The control instructions can use some of the following register ‘Wd’ with or without an address modifier operands: However, word or byte-oriented file register instructions • A program memory address have two operands: • The mode of the Table Read and Table Write instructions • The file register specified by the value, ‘f’ • The destination, which could be either the file register, ‘f’, or the W0 register, which is denoted as ‘WREG’  2008-2014 Microchip Technology Inc. DS70000318G-page 275

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Most instructions are a single word. Certain (unconditional/computed branch), indirect CALL/GOTO, double-word instructions are designed to provide all the all Table Reads and Table Writes and RETURN/RETFIE required information in these 48 bits. In the second instructions, which are single-word instructions but take word, the 8MSbs are ‘0’s. If this second word is two or three cycles. Certain instructions that involve executed as an instruction (by itself), it will execute as skipping over the subsequent instruction require either a NOP. two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word The double-word instructions execute in two instruction or two-word instruction. Moreover, double-word moves cycles. require two cycles. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the Note: For more details on the instruction set, Program Counter is changed as a result of the refer to the “16-bit MCU and DSC instruction. In these cases, the execution takes two Programmer’s Reference Manual” instruction cycles with the additional instruction cycle(s) (DS70157). executed as a NOP. Notable exceptions are the BRA TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator Write-Back Destination Address register {W13, [W13]+ = 2} bit4 4-bitbit selection field (used in word-addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0x0000...0x1FFF} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; LSb must be ‘0’ None Field does not require an entry, can be blank OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor Working register pair (Direct Addressing) DS70000318G-page 276  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier Working register pair for Square instructions  {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier Working register pair for DSP instructions  {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 Working registers {W0..W15} Wnd One of 16 Destination Working registers {W0...W15} Wns One of 16 Source Working registers {W0...W15} WREG W0 (Working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register  { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wx X Data Space Prefetch Address register for DSP instructions  {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none} Wxd X Data Space Prefetch Destination register for DSP instructions {W4...W7} Wy Y Data Space Prefetch Address register for DSP instructions  {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Wyd Y Data Space Prefetch Destination register for DSP instructions {W4...W7}  2008-2014 Microchip Technology Inc. DS70000318G-page 277

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: INSTRUCTION SET OVERVIEW Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB 2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z 3 AND AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z 4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z 5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None 6 BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater Than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater Than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater Than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater Than 1 1 (2) None BRA LE,Expr Branch if Less Than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less Than or Equal 1 1 (2) None BRA LT,Expr Branch if Less Than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less Than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OA,Expr Branch if Accumulator A Overflow 1 1 (2) None BRA OB,Expr Branch if Accumulator B Overflow 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA SA,Expr Branch if Accumulator A Saturated 1 1 (2) None BRA SB,Expr Branch if Accumulator B Saturated 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None 7 BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None 8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None 9 BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None DS70000318G-page 278  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3) 11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) 12 BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z 13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z 14 CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB 16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep 17 COM COM f f = f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z 18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z 19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z 20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z (Wb – Ws – C) 21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, Skip if = 1 1 None (2 or 3) 22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, Skip if > 1 1 None (2 or 3) 23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, Skip if < 1 1 None (2 or 3) 24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, Skip if  1 1 None (2 or 3) 25 DAW DAW Wn Wn = Decimal Adjust Wn 1 1 C 26 DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z 27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z 28 DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None  2008-2014 Microchip Technology Inc. DS70000318G-page 279

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV 30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV 31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 None DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None 39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z 41 IOR IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 43 LNK LNK #lit14 Link Frame Pointer 1 1 None 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z 45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply and Accumulate 1 1 OA,OB,OAB, , SA,SB,SAB AWB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB 46 MOV MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 N,Z MOV f,WREG Move f to WREG 1 1 None MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 None MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None 47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and Store Accumulator 1 1 None DS70000318G-page 280  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 48 MPY MPY Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, Wm*Wn,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB MPY Square Wm to Accumulator 1 1 OA,OB,OAB, Wm*Wm,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB 49 MPY.N MPY.N -(Multiply Wm by Wn) to Accumulator 1 1 None Wm*Wn,Acc,Wx,Wxd,Wy,Wyd 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, , SA,SB,SAB AWB 51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(Ws) MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(lit5) MUL f W3:W2 = f * WREG 1 1 None 52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f = f + 1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 53 NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None 54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None W(nd):W(nd + 1) POP.S Pop Shadow Registers 1 1 All 55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None 56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep 57 RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None 58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None 59 RESET RESET Software Device Reset 1 1 None 60 RETFIE RETFIE Return from interrupt 1 3 (2) None 61 RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None 62 RETURN RETURN Return from Subroutine 1 3 (2) None 63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z 64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z 65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z  2008-2014 Microchip Technology Inc. DS70000318G-page 281

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None 68 SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C,N,Z 69 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None 70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB 71 SL SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z 72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f – WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z 73 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z 74 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z 75 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z 76 SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None 77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None 78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None 79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 81 ULNK ULNK Unlink Frame Pointer 1 1 None 82 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z 83 ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C,Z,N DS70000318G-page 282  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.0 DEVELOPMENT SUPPORT 23.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® Digital Signal Controllers (DSC) are supported with a full The MPLAB X IDE is a single, unified graphical user range of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2008-2014 Microchip Technology Inc. DS70000318G-page 283

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.2 MPLAB XC Compilers 23.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16 and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other related modules together relocatable object files and archives to create an exe- • Flexible creation of libraries with easy module cutable file. MPLAB XC Compiler uses the assembler listing, replacement, deletion and extraction to produce its object file. Notable features of the assembler include: 23.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 23.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS70000318G-page 284  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.6 MPLAB X SIM Software Simulator 23.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 23.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 23.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the programs all 8, 16 and 32-bit MCU, and DSC devices target via a Microchip debug (RJ-11) connector (com- with the easy-to-use, powerful graphical user interface of patible with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 23.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2008-2014 Microchip Technology Inc. DS70000318G-page 285

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.11 Demonstration/Development 23.12 Third-Party Development Tools Boards, Evaluation Kits and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS70000318G-page 286  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 24.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS(3) ...................................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS, when VDD  3.0V(3) ................................................. -0.3V to +5.6V Voltage on any 5V tolerant pin with respect to Vss, when VDD < 3.0V(3)........................................-0.3V to (VDD + 0.3V) Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin(2)...........................................................................................................................250 mA Maximum current sourced/sunk by any 4x I/O pin..................................................................................................15 mA Maximum current sourced/sunk by any 8x I/O pin..................................................................................................25 mA Maximum current sourced/sunk by any 16x I/O pin................................................................................................45 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports(2)...............................................................................................................200 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table24-2). 3: See the “Pin Diagrams” section for 5V tolerant pins.  2008-2014 Microchip Technology Inc. DS70000318G-page 287

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 24.1 DC Characteristics TABLE 24-1: OPERATING MIPS VS. VOLTAGE Max MIPS VDD Range Temp Range Characteristic (in Volts) (in °C) dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 — 3.0-3.6V(1) -40°C to +85°C 40 — 3.0-3.6V(1) -40°C to +125°C 40 Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer to Parameter BO10 in Table24-11 for BOR values. TABLE 24-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Industrial Temperature Devices Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Extended Temperature Devices Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W I/O Pin Power Dissipation: I/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W TABLE 24-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes Package Thermal Resistance, 44-Pin QFN JA 28 — °C/W 1 Package Thermal Resistance, 44-Pin TFQP JA 39 — °C/W 1 Package Thermal Resistance, 28-Pin SPDIP JA 42 — °C/W 1 Package Thermal Resistance, 28-Pin SOIC JA 47 — °C/W 1 Package Thermal Resistance, 28-Pin QFN-S JA 34 — °C/W 1 Package Thermal Resistance, 18-Pin SOIC JA 57 — °C/W 1 Package Thermal Resistance, 44-Pin VTLA JA 25 — °C/W 1 Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS70000318G-page 288  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Operating Voltage DC10 VDD Supply Voltage(4) 3.0 — 3.6 V Industrial and Extended DC12 VDR RAM Data Retention Voltage(2) 1.8 — — V DC16 VPOR VDD Start Voltage — — VSS V to Ensure Internal Power-on Reset Signal DC17 SVDD VDD Rise Rate(3) 0.03 — — V/ms 0V-3.0V in 0.1 seconds to Ensure Internal Power-on Reset Signal Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: This is the limit to which VDD may be lowered without losing RAM data. 3: These parameters are characterized but not tested in manufacturing. 4: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer to Parameter BO10 in Table24-11 for BOR values.  2008-2014 Microchip Technology Inc. DS70000318G-page 289

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Typical(1) Max Units Conditions No. Operating Current (IDD)(2) DC20d 55 70 mA -40°C DC20a 55 70 mA +25°C 10 MIPS 3.3V DC20b 55 70 mA +85°C See Note 2 DC20c 55 70 mA +125°C DC21d 68 85 mA -40°C DC21a 68 85 mA +25°C 16 MIPS 3.3V DC21b 68 85 mA +85°C See Note 2 and Note 3 DC21c 68 85 mA +125°C DC22d 78 95 mA -40°C DC22a 78 95 mA +25°C 20 MIPS 3.3V DC22b 78 95 mA +85°C See Note 2 and Note 3 DC22c 78 95 mA +125°C DC23d 88 110 mA -40°C DC23a 88 110 mA +25°C 30 MIPS 3.3V DC23b 88 110 mA +85°C See Note 2 and Note 3 DC23c 88 110 mA +125°C DC24d 98 120 mA -40°C DC24a 98 120 mA +25°C 40 MIPS 3.3V DC24b 98 120 mA +85°C See Note 2 DC24c 98 120 mA +125°C DC25d 128 160 mA -40°C 40 MIPS DC25a 125 150 mA +25°C See Note 2, except PWM is 3.3V DC25b 121 150 mA +85°C operating at maximum speed DC25c 119 150 mA +125°C (PTCON2 = 0x0000) DC26d 115 140 mA -40°C 40 MIPS DC26a 112 140 mA +25°C See Note 2, except PWM is 3.3V DC26b 110 140 mA +85°C operating at 1/2 speed DC26c 108 140 mA +125°C (PTCON2 = 0x0001) Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 2: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are zeroed) • CPU executing while(1) statement • JTAG disabled 3: These parameters are characterized but not tested in manufacturing. DS70000318G-page 290  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Typical(1) Max Units Conditions No. Operating Current (IDD)(2) DC27d 111 140 mA -40°C 40 MIPS DC27a 108 130 mA +25°C See Note 2, except PWM is 3.3V DC27b 105 130 mA +85°C operating at 1/4 speed DC27c 103 130 mA +125°C (PTCON2 = 0x0002) DC28d 102 130 mA -40°C 40 MIPS DC28a 100 120 mA +25°C See Note 2, except PWM is 3.3V DC28b 100 120 mA +85°C operating at 1/8 speed DC28c 100 120 mA +125°C (PTCON2 = 0x0003) Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 2: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are zeroed) • CPU executing while(1) statement • JTAG disabled 3: These parameters are characterized but not tested in manufacturing.  2008-2014 Microchip Technology Inc. DS70000318G-page 291

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Typical(1) Max Units Conditions No. Idle Current (IIDLE): Core Off Clock On Base Current(2) DC40d 48 — mA -40°C DC40a 48 — mA +25°C 3.3V 10 MIPS DC40b 48 — mA +85°C DC40c 48 — mA +125°C DC41d 60 — mA -40°C DC41a 60 — mA +25°C 3.3V 16 MIPS(3) DC41b 60 — mA +85°C DC41c 60 — mA +125°C DC42d 68 — mA -40°C DC42a 68 — mA +25°C 3.3V 20 MIPS(3) DC42b 68 — mA +85°C DC42c 68 — mA +125°C DC43d 77 — mA -40°C DC43a 77 — mA +25°C 3.3V 30 MIPS(3) DC43b 77 — mA +85°C DC43c 77 — mA +125°C DC44d 86 — mA -40°C DC44a 86 — mA +25°C 3.3V 40 MIPS DC44b 86 — mA +85°C DC44c 86 — mA +125°C Note 1: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. 2: Base Idle current (IIDLE) is measured as follows: • CPU core is off, oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are zeroed) • JTAG is disabled 3: These parameters are characterized but not tested in manufacturing. DS70000318G-page 292  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Typical(1) Max Units Conditions No. Power-Down Current (IPD)(2,4) DC60d 125 500 A -40°C DC60a 135 500 A +25°C 3.3V Base Power-Down Current DC60b 235 500 A +85°C DC60c 565 950 A +125°C DC61d 40 50 A -40°C DC61a 40 50 A +25°C 3.3V Watchdog Timer Current: IWDT(3) DC61b 40 50 A +85°C DC61c 80 90 A +125°C Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. 2: IPD (Sleep) current is measured as follows: • CPU core is off, oscillator is configured in EC mode and external clock active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • All peripheral modules are disabled (PMDx bits are all ones) • The VREGS bit (RCON<8>) = 0 (i.e., core regulator is set to stand-by while the device is in Sleep mode) • JTAG disabled 3: The  current is the additional current consumed when the WDT module is enabled. This current should be added to the base IPD current. 4: These currents are measured on the device containing the most memory in this family.  2008-2014 Microchip Technology Inc. DS70000318G-page 293

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Doze Parameter No. Typical(1) Max Units Conditions Ratio Doze Current (IDOZE)(2) DC73a 75 105 1:2 mA DC73f 60 105 1:64 mA -40°C 3.3V 40 MIPS DC73g 60 105 1:128 mA DC70a 75 105 1:2 mA DC70f 60 105 1:64 mA +25°C 3.3V 40 MIPS DC70g 60 105 1:128 mA DC71a 75 105 1:2 mA DC71f 60 105 1:64 mA +85°C 3.3V 40 MIPS DC71g 60 105 1:128 mA DC72a 75 105 1:2 mA DC72f 60 105 1:64 mA +125°C 3.3V 40 MIPS DC72g 60 105 1:128 mA Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. 2: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDOZE measurements are as follows: • Oscillator is configured in EC mode and external clock active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are zeroed) • CPU executing while(1) statement • JTAG disabled DS70000318G-page 294  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VIL Input Low Voltage DI10 I/O Pins VSS — 0.2VDD V DI15 MCLR VSS — 0.2VDD V DI16 I/O Pins with OSC1 VSS — 0.2VDD V DI18 I/O Pins with SDAx, SCLx VSS — 0.3 VDD V SMBus disabled DI19 I/O Pins with SDAx, SCLx VSS — 0.8 V SMBus enabled VIH Input High Voltage DI20 I/O Pins Not 5V Tolerant(4) 0.7VDD — VDD V DI21 I/O Pins 5V Tolerant(4) 0.7VDD — 5.5 V DI28 SDA1, SCL1 0.7VDD — 5.5 V SMBus disabled DI29 SDA1, SCL1 2.1 — 5.5 V SMBus enabled ICNPU CNx Pull-up Current DI30 — 250 — A VDD = 3.3V, VPIN = VSS IIL Input Leakage Current(2,3,4) DI50 I/O Pins with: 4x Driver Pins - RA0-RA2, — — ±2 A VSS  VPIN  VDD, RB0-RB2, RB5-RB10, RB15, Pin at high-impedance RC1, RC2, RC9, RC10 8x Driver Pins - RC0, RC3-RC8, — — ±4 A VSS  VPIN  VDD, RC11-RC13 Pin at high-impedance 16x Driver Pins - RA3, RA4, RB3, — — ±8 A VSS  VPIN  VDD, RB4, RB11-RB14 Pin at high-impedance DI55 MCLR — — ±2 A VSS VPIN VDD DI56 OSC1 — — ±2 A VSS VPIN VDD, XT and HS modes Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See “Pin Diagrams” for the list of 5V tolerant I/O pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro- vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested.  2008-2014 Microchip Technology Inc. DS70000318G-page 295

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. IICL Input Low Injection Current DI60a 0 — -5(5,8) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP and RB5 IICH Input High Injection Current DI60b 0 — +5(6,7,8) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, RB5 and digital 5V-tolerant designated pins IICT Total Input Injection Current DI60c (sum of all I/O and control pins) -20(9) — +20(9) mA Absolute instantaneous sum of all ± input injection currents from all I/O pins (| IICL + | IICH |)  IICT Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See “Pin Diagrams” for the list of 5V tolerant I/O pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro- vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. DS70000318G-page 296  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min. Typ. Max. Units Conditions Output Low Voltage I/O Pins: IOL  6 mA, VDD = 3.3V 4x Sink Driver Pins – RA0-RA2, — — 0.4 V See Note 1 RB0-RB2, RB5-RB10, RB15, RC1, RC2, RC9, RC10 Output Low Voltage DO10 VOL I/O Pins: IOL  10 mA, VDD = 3.3V — — 0.4 V 8x Sink Driver Pins – RC0, See Note 1 RC3-RC8, RC11-RC13 Output Low Voltage I/O Pins: IOL  18 mA, VDD = 3.3V — — 0.4 V 16x Sink Driver Pins – RA3, See Note 1 RA4, RB3, RB4, RB11-RB14 Output High Voltage I/O Pins: 4x Source Driver Pins – IOH-6 mA, VDD = 3.3V 2.4 — — V RA0-RA2, RB0-RB2, RB5- See Note 1 RB10, RB15, RC1, RC2, RC9, RC10 Output High Voltage DO20 VOH I/O Pins: IOH-10 mA, VDD = 3.3V 2.4 — — V 8x Source Driver Pins – RC0, See Note 1 RC3-RC8, RC11-RC13 Output High Voltage I/O Pins: IOH-18 mA, VDD = 3.3V 2.4 — — V 16x Source Driver Pins – RA3, See Note 1 RA4, RB3, RB4, RB11-RB14 Output High Voltage IOH-12 mA, VDD = 3.3V 1.5 — — I/O Pins: See Note 1 4x Source Driver Pins – IOH-11 mA, VDD = 3.3V RA0-RA2, RB0-RB2, 2.0 — — V See Note 1 RB5-RB10, RB15, RC1, RC2, IOH-3 mA, VDD = 3.3V RC9, RC10 3.0 — — See Note 1 Output High Voltage IOH-16 mA, VDD = 3.3V 1.5 — — 8x Source Driver Pins – RC0, See Note 1 RC3-RC8, RC11-RC13 IOH-12 mA, VDD = 3.3V DO20A VOH1 2.0 — — V See Note 1 IOH-4 mA, VDD = 3.3V 3.0 — — See Note 1 Output High Voltage IOH-30 mA, VDD = 3.3V 1.5 — — I/O Pins: See Note 1 16x Source Driver Pins – RA3, IOH-25 mA, VDD = 3.3V RA4, RB3, RB4, RB11-RB14 2.0 — — V See Note 1 IOH-8 mA, VDD = 3.3V 3.0 — — See Note 1 Note 1: Parameters are characterized, but not tested.  2008-2014 Microchip Technology Inc. DS70000318G-page 297

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions (see Note 3): 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min(1) Typ Max Units Conditions No. BO10 VBOR BOR Event on VDD Transition 2.55 — 2.79 V See Note 2 High-to-Low BOR Event is Tied to VDD Core Voltage Decrease Note 1: Parameters are for design guidance only and are not tested in manufacturing. 2: The device will operate as normal until the VDDMIN threshold is reached. 3: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN. DS70000318G-page 298  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Program Flash Memory D130 EP Cell Endurance 10,000 — — E/W -40C to +125C D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132B VPEW VDD for Self-Timed Write VMIN — 3.6 V VMIN = Minimum operating voltage D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated, -40C to +125C D135 IDDP Supply Current during — 10 — mA Programming D136a TRW Row Write Time 1.477 — 1.538 ms TRW = 11064 FRC cycles, TA = +85°C, See Note 2 D136b TRW Row Write Time 1.435 — 1.586 ms TRW = 11064 FRC cycles, TA = +125°C, See Note 2 D137a TPE Page Erase Time 22.5 — 23.4 ms TPE = 168517 FRC cycles, TA = +85°C, See Note 2 D137b TPE Page Erase Time 21.9 — 24.2 ms TPE = 168517 FRC cycles, TA = +125°C, See Note 2 D138a TWW Word Write Cycle Time 47.4 — 49.3 µs TWW = 355 FRC cycles, TA = +85°C, See Note 2 D138b TWW Word Write Cycle Time 46 — 50.9 µs TWW = 355 FRC cycles, TA = +125°C, See Note 2 Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max). This parameter depends on the FRC accuracy (see Table24-20) and the value of the FRC Oscillator Tun- ing register (see Register9-4). For complete details on calculating the Minimum and Maximum time see Section5.3 “Programming Operations”. TABLE 24-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristics Min Typ Max Units Comments No. — CEFC External Filter Capacitor 4.7 10 — F Capacitor must be low Value(1) series resistance (< 5 ohms) Note 1: Typical VCAP voltage = 2.5 volts when VDD  VDDMIN.  2008-2014 Microchip Technology Inc. DS70000318G-page 299

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 24.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 AC characteristics and timing parameters. TABLE 24-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Operating voltage VDD range as described in Table24-1. FIGURE 24-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSC2 VSS 15 pF for OSC2 output TABLE 24-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol Characteristic Min Typ Max Units Conditions No. DO50 COSCO OSC2 Pin — — 15 pF In XT and HS modes when external clock is used to drive OSC1 DO56 CIO All I/O Pins and OSC2 — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode DS70000318G-page 300  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 24-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symb Characteristic Min Typ(1) Max Units Conditions No. OS10 FIN External CLKI Frequency DC — 40 MHz EC (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency 3.5 — 10 MHz XT 10 — 40 MHz HS OS20 TOSC TOSC = 1/FOSC 12.5 — DC ns OS25 TCY Instruction Cycle Time(2) 25 — DC ns OS30 TosL, External Clock in (OSC1) 0.375 x TOSC — 0.625 x TOSC ns EC TosH High or Low Time OS31 TosR, External Clock in (OSC1) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(3) — 5.2 — ns OS41 TckF CLKO Fall Time(3) — 5.2 — ns OS42 GM External Oscillator 14 16 18 mA/V VDD = 3.3V, Transconductance(4) TA = +25ºC Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. 4: Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing.  2008-2014 Microchip Technology Inc. DS70000318G-page 301

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS50 FPLLI PLL Voltage Controlled 0.8 — 8 MHz ECPLL, XTPLL modes Oscillator (VCO) Input Frequency Range OS51 FSYS On-Chip VCO System 100 — 200 MHz Frequency OS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 mS OS53 DCLK CLKO Stability (Jitter)(2) -3 0.5 3 % Measured over 100 ms period Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested in manufacturing. 2: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases or communication clocks use this formula: DCLK Peripheral Clock Jitter = ------------------------------------------------------------------------ -------------------------F----O----S---C-------------------------- Peripheral Bit Rate Clock For example: FOSC = 32 MHz, DCLK = 3%, SPI bit rate clock (i.e., SCKx) is 2 MHz. DCLK 3% 3% SPI SCK Jitter = ------------------------------ = ---------- = -------- = 0.75% 3---2---- --M-----H-----z- 16 4  2 MHz TABLE 24-18: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS56 FHPOUT On-Chip 16x PLL CCO 112 118 120 MHz Frequency OS57 FHPIN On-Chip 16x PLL Phase 7.0 7.37 7.5 MHz Detector Input Frequency OS58 TSU Frequency Generator Lock — — 10 µs Time Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested in manufacturing. DS70000318G-page 302  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-19: AC CHARACTERISTICS: INTERNAL FRC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA +85°C for industrial -40°C  TA  +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1) F20a FRC -2 — +2 % -40°C  TA +85°C VDD = 3.0-3.6V F20b FRC -5 — +5 % -40°C  TA +125°C VDD = 3.0-3.6V Note 1: Frequency calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift. TABLE 24-20: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. LPRC @ 32.768 kHz(1) F21a LPRC -20 ±6 +20 % -40°C  TA +85°C VDD = 3.0-3.6V F21b LPRC -70 — +70 % -40°C  TA +125°C VDD = 3.0-3.6V Note 1: Change of LPRC frequency as VDD changes.  2008-2014 Microchip Technology Inc. DS70000318G-page 303

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure24-1 for load conditions. TABLE 24-21: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V(unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. DO31 TIOR Port Output Rise Time: 4x Source Driver Pins – RA0-RA2, — 10 25 ns Refer to Figure24-1 RB0-RB2, RB5-RB10, RB15, RC1, for test conditions RC2, RC9, RC10 8x Source Driver Pins – RC0, — 8 20 ns RC3-RC8, RC11-RC13 16x Source Driver Pins – RA3, — 6 15 ns RA4, RB3, RB4, RB11-RB14 DO32 TIOF Port Output Fall Time: 4x Source Driver Pins – RA0-RA2, Refer to Figure24-1 RB0-RB2, RB5-RB10, RB15, RC1, — 10 25 ns for test conditions RC2, RC9, RC10 8x Source Driver Pins – RC0, — 8 20 ns RC3-RC8, RC11-RC13 16x Source Driver Pins – RA3, — 6 15 ns RA4, RB3, RB4, RB11-RB14 DI35 TINP INTx Pin High or Low Time (input) 20 — — ns DI40 TRBP CNx High or Low Time (input) 2 — — TCY Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. DS70000318G-page 304  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD SY12 MCLR Internal SY10 POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure24-1 for load conditions.  2008-2014 Microchip Technology Inc. DS70000318G-page 305

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SY10 TMCL MCLR Pulse Width (low) 2 — — s -40°C to +85°C SY11 TPWRT Power-up Timer Period — 2 — ms -40°C to +85°C, 4 User programmable 8 16 32 64 128 SY12 TPOR Power-on Reset Delay 3 10 30 s -40°C to +85°C SY13 TIOZ I/O High-Impedance from MCLR 0.68 0.72 1.2 s Low or Watchdog Timer Reset SY20 TWDT1 Watchdog Timer Time-out Period — — — ms See Section21.4 “Watch- dog Timer (WDT)” and LPRC Parameter F21a (Table24-20) SY30 TOST Oscillator Start-up Time — 1024TOSC — — TOSC = OSC1 period Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. DS70000318G-page 306  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-5: TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRx Note: Refer to Figure24-1 for load conditions. TABLE 24-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min. Typ. Max. Units Conditions No. TA10 TTXH T1CK High Synchronous, TCY + 20 — — ns Must also meet Time no prescaler Parameter TA15, Synchronous, (TCY + 20)/N — — ns N = Prescale value (1, 8, 64, 256) with prescaler Asynchronous 20 — — ns TA11 TTXL T1CK Low Synchronous, TCY + 20 — — ns Must also meet Time no prescaler Parameter TA15, Synchronous, (TCY + 20)/N — — ns N = Prescale value (1, 8, 64, 256) with prescaler Asynchronous 20 — — ns TA15 TTXP T1CK Input Synchronous, 2 TCY + 40 — — ns Period no prescaler Synchronous, Greater of: — — — N = Prescale value with prescaler 40 ns or (1, 8, 64, 256) (2 TCY + 40)/N Asynchronous 40 — — ns OS60 FT1 T1CK Oscillator Input DC — 50 kHz Frequency Range (oscillator enabled by setting bit, TCS (T1CON<1>)) TA20 TCKEXTMRL Delay from External T1CK 0.75 TCY + 40 — 1.75 TCY + 40 — Clock Edge to Timer Increment Note 1: Timer1 is a Type A timer.  2008-2014 Microchip Technology Inc. DS70000318G-page 307

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 T ABLE 24-24: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min. Typ. Max. Units Conditions No. TB10 TTXH T2CK High Synchronous Greater of: — — ns Must also meet Time 20 ns or Parameter TB15, (TCY + 20)/N N = Prescale value (1, 8, 64, 256) TB11 TTXL T2CK Low Synchronous Greater of: — — ns Must also meet Time 20 ns or Parameter TB15, (TCY + 20)/N N = Prescale value (1, 8, 64, 256) TB15 TTXP T2CK Input Synchronous Greater of: — — ns N = Prescale value Period 40 ns or (1, 8, 64, 256) (2 TCY + 40)/N TB20 TCKEXTMRL Delay from External T2CK 0.75 TCY + 40 — 1.75 TCY + 40 ns Clock Edge to Timer Increment TABLE 24-25: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TC10 TTXH T3CK High Synchronous TCY + 20 — — ns Must also meet Time Parameter TC15 TC11 TTXL T3CK Low Synchronous TCY + 20 — — ns Must also meet Time Parameter TC15 TC15 TTXP T3CK Input Synchronous, 2 TCY + 40 — — ns Period with prescaler TC20 TCKEXTMRL Delay from External T3CK 0.75 TCY + 40 — 1.75 TCY + 40 — Clock Edge to Timer Increment DS70000318G-page 308  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-6: INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure24-1 for load conditions. TABLE 24-26: INPUT CAPTURE x TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Max Units Conditions No. IC10 TccL ICx Input Low Time No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns IC11 TccH ICx Input High Time No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns IC15 TccP ICx Input Period (TCY + 40)/N — ns N = Prescale value (1, 4, 16) Note 1: These parameters are characterized but not tested in manufacturing. FIGURE 24-7: OUTPUT COMPARE x MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure24-1 for load conditions. TABLE 24-27: OUTPUT COMPARE x MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. OC10 TccF OCx Output Fall Time — — — ns See Parameter DO32 OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31 Note 1: These parameters are characterized but not tested in manufacturing.  2008-2014 Microchip Technology Inc. DS70000318G-page 309

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-8: OCx/PWMx MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 OCx Active Tri-State TABLE 24-28: SIMPLE OCx/PWMx MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. OC15 TFD Fault Input to PWMx I/O — — TCY + 20 ns Change OC20 TFLT Fault Input Pulse Width TCY + 20 — — ns Note 1: These parameters are characterized but not tested in manufacturing. DS70000318G-page 310  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-9: HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS MP30 FLTx MP20 PWMx FIGURE 24-10: HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure24-1 for load conditions. TABLE 24-29: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. MP10 TFPWM PWMx Output Fall Time — 2.5 — ns MP11 TRPWM PWMx Output Rise Time — 2.5 — ns MP20 TFD Fault Input  to PWM — — 15 ns I/O Change MP30 TFH Minimum PWMx Fault Pulse 8 — — ns DTC<1:0> = 10 Width MP31 TPDLY Tap Delay 1.04 — — ns ACLK = 120 MHz MP32 ACLK PWMx Input Clock — — 120 MHz See Note 2 Note 1: These parameters are characterized but not tested in manufacturing. 2: This parameter is a maximum allowed input clock for the PWMx module.  2008-2014 Microchip Technology Inc. DS70000318G-page 311

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-30: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Master Master Slave Maximum Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP Data Rate (Half-Duplex) (Full-Duplex) (Full-Duplex) 15 MHz Table24-31 — — 0,1 0,1 0,1 9 MHz — Table24-32 — 1 0,1 1 9 MHz — Table24-33 — 0 0,1 1 15 MHz — — Table24-34 1 0 0 11 MHz — — Table24-35 1 1 0 15 MHz — — Table24-36 0 1 0 11 MHz — — Table24-37 0 0 0 FIGURE 24-11: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 Note: Refer to Figure24-1 for load conditions. FIGURE 24-12: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 Note: Refer to Figure24-1 for load conditions. DS70000318G-page 312  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-31: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCKx Frequency — — 15 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdiV2scH, SDOx Data Output Setup to 30 — — ns TdiV2scL First SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2008-2014 Microchip Technology Inc. DS70000318G-page 313

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-13: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP40 SDIx MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure24-1 for load conditions. TABLE 24-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCKx Frequency — — 9 MHz See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2sc, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70000318G-page 314  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-14: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP30, SP31 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure24-1 for load conditions. TABLE 24-33: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscP Maximum SCKx Frequency — — 9 MHz -40ºC to +125ºC and see Note 3 SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2008-2014 Microchip Technology Inc. DS70000318G-page 315

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-15: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP50 SP52 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure24-1 for load conditions. DS70000318G-page 316  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input — — 15 MHz See Note 3 Frequency SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns High-Impedance(4) SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2008-2014 Microchip Technology Inc. DS70000318G-page 317

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-16: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP50 SP52 SCKx (CKP = 0) SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SP52 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure24-1 for load conditions. DS70000318G-page 318  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input — — 11 MHz See Note 3 Frequency SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns High-Impedance(4) SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns SSx Edge Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2008-2014 Microchip Technology Inc. DS70000318G-page 319

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-17: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOX MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure24-1 for load conditions. DS70000318G-page 320  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input — — 15 MHz See Note 3 Frequency SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2008-2014 Microchip Technology Inc. DS70000318G-page 321

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-18: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure24-1 for load conditions. DS70000318G-page 322  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-37: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA  +85°C for Industrial -40°CTA +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscP Maximum SCKx Input — — 11 MHz See Note 3 Frequency SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns See Note 4 High-Impedance SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns See Note 4 TscL2ssH Note 1: These parameters are characterized, but are not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the Master must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2008-2014 Microchip Technology Inc. DS70000318G-page 323

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-19: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Start Stop Condition Condition Note: Refer to Figure24-1 for load conditions. FIGURE 24-20: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM21 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure24-1 for load conditions. DS70000318G-page 324  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 T ABLE 24-38: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min(1) Max Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 pF to 400 pF 1 MHz mode(2) — 100 ns IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 pF to 400 pF 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) 40 — ns IM26 THD:DAT Data Input 100 kHz mode 0 — s Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(2) 0.2 — s IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — s Only relevant for Setup Time 400 kHz mode TCY/2 (BRG + 1) — s Repeated Start 1 MHz mode(2) TCY/2 (BRG + 1) — s condition IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — s After this period the Hold Time 400 kHz mode TCY/2 (BRG + 1) — s first clock pulse is 1 MHz mode(2) TCY/2 (BRG + 1) — s generated IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — s Setup Time 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns 1 MHz mode(2) TCY/2 (BRG + 1) — ns IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns From Clock 400 kHz mode — 1000 ns 1 MHz mode(2) — 400 ns IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be 400 kHz mode 1.3 — s free before a new 1 MHz mode(2) 0.5 — s transmission can start IM50 CB Bus Capacitive Loading — 400 pF IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 3 Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to “Inter-Integrated Circuit (I2C™)” (DS70000195) in the “dsPIC33/PIC24 Family Reference Manual”. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: Typical value for this parameter is 130 ns.  2008-2014 Microchip Technology Inc. DS70000318G-page 325

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-21: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS34 IS30 IS33 SDAx Start Stop Condition Condition FIGURE 24-22: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS70000318G-page 326  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-39: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min Max Units Conditions IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 pF to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 pF to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — s Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(1) 0 0.3 s IS30 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated Setup Time 400 kHz mode 0.6 — s Start condition 1 MHz mode(1) 0.25 — s IS31 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first Hold Time 400 kHz mode 0.6 — s clock pulse is generated 1 MHz mode(1) 0.25 — s IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — s Setup Time 400 kHz mode 0.6 — s 1 MHz mode(1) 0.6 — s IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — ns 1 MHz mode(1) 250 — ns IS40 TAA:SCL Output Valid 100 kHz mode 0 3500 ns From Clock 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before a new transmission 400 kHz mode 1.3 — s can start 1 MHz mode(1) 0.5 — s IS50 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).  2008-2014 Microchip Technology Inc. DS70000318G-page 327

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 T= ABLE 24-40: 10-BIT HIGH-SPEED ADC MODULE SPECIFICATIONS Standard Operating Conditions (see Note 2): 3.0V and 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min. Typ. Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply — — — — AVDD is internally connected to VDD; see Parameter DC10 in Table24-4 AD02 AVSS Module VSS Supply — — — — AVSS is internally connected to VSS Analog Input AD10 VINH-VINL Full-Scale Input Span VSS — VDD V AD11 VIN Absolute Input Voltage AVSS — AVDD V AD12 IAD Operating Current — 8 — mA AD13 — Leakage Current — ±0.6 — A VINL = AVSS = 0V, AVDD = 3.3V, Source Impedance = 100 AD17 RIN Recommended Impedance — — 100  Of Analog Voltage Source DC Accuracy @ 1.5 Msps AD20A Nr Resolution 10 Data Bits AD21A INL Integral Nonlinearity -0.5 -0.3/+0.5 +1.2 LSb AD22A DNL Differential Nonlinearity -0.9 ±0.6 +0.9 LSb AD23A GERR Gain Error 13 15 22 LSb AD24A EOFF Offset Error 6 7 8 LSb AD25A — Monotonicity(1) — — — — Guaranteed DC Accuracy @ 1.7 Msps AD20B Nr Resolution 10 Data Bits AD21B INL Integral Nonlinearity -0.5 -0.4/+1.1 +1.8 LSb AD22B DNL Differential Nonlinearity -1.0 ±1.0 +1.5 LSb AD23B GERR Gain Error 13 15 22 LSb AD24B EOFF Offset Error 6 7 8 LSb AD25B — Monotonicity(1) — — — — Guaranteed DC Accuracy @ 2.0 Msps AD20C Nr Resolution 10 Data Bits AD21C INL Integral Nonlinearity -0.8 -0.5/+1.8 +2.8 LSb AD22C DNL Differential Nonlinearity -1.0 -1.0/+1.8 +2.8 LSb AD23C GERR Gain Error 14 16 23 LSb AD24C EOFF Offset Error 6 7 8 LSb AD25C — Monotonicity(1) — — — — Guaranteed Dynamic Performance AD30 THD Total Harmonic Distortion — -73 — dB AD31 SINAD Signal to Noise and Distortion — 58 — dB AD32 SFDR Spurious Free Dynamic Range — -73 — dB AD33 FNYQ Input Signal Bandwidth — — 1 MHz AD34 ENOB Effective Number of Bits — 9.4 — bits Note 1: The Analog-to-Digital conversion result never decreases with an increase in input voltage, and has no missing codes. 2: Module is functional at VBOR < VDD < VDDMIN, but with degraded performance. Module functionality is tested but not characterized. DS70000318G-page 328  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-41: 10-BIT, HIGH-SPEED ADC MODULE TIMING REQUIREMENTS Standard Operating Conditions (see Note 2): 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min. Typ(1) Max. Units Conditions No. Clock Parameters AD50b TAD ADC Clock Period 35.8 — — ns Conversion Rate AD55b tCONV Conversion Time — 14 TAD — — AD56b FCNV Throughput Rate Devices with Single SAR — — 2.0 Msps Devices with Dual SARs — — 4.0 Msps Timing Parameters AD63b tDPU Time to Stabilize Analog Stage 1.0 — 10 s from ADC Off to ADC On Note 1: These parameters are characterized but not tested in manufacturing. 2: Module is functional at VBOR < VDD < VDDMIN, but with degraded performance. Module functionality is tested but not characterized. FIGURE 24-23: ANALOG-TO-DIGITAL CONVERSION TIMING PER INPUT TCONV Trigger Pulse TAD ADC Clock ADC Data 9 8 2 1 0 ADBUFxx Old Data New Data CONV  2008-2014 Microchip Technology Inc. DS70000318G-page 329

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-42: COMPARATOR MODULE SPECIFICATIONS Standard Operating Conditions (see Note 2): 3.0V to 3.6V DC CHARACTERISTICS Operating temperature: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min Typ Max Units Comments No. CM10 VIOFF Input Offset Voltage -58 +14/-40 66 mV CM11 VICM Input Common-Mode 0 — AVDD – 1.5 V Voltage Range(1) CM12 VGAIN Open Loop Gain(1) 90 — — db CM13 CMRR Common-Mode 70 — — db Rejection Ratio(1) CM14 TRESP Large Signal Response 21 30 49 ns V+ input step of 100mv while V- input held at AVDD/2. Delay measured from analog input pin to PWM output pin. Note 1: Parameters are for design guidance only and are not tested in manufacturing. 2: Module is functional at VBOR < VDD < VDDMIN, but with degraded performance. Module functionality is tested but not characterized. TABLE 24-43: DAC MODULE SPECIFICATIONS Standard Operating Conditions (see Note 2): 3.0V to 3.6V AC and DC CHARACTERISTICS Operating temperature: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min Typ Max Units Comments No. DA01 EXTREF External Voltage Reference(1) 0 AVDD – 1.6 V DA08 INTREF Internal Voltage Reference(1) 1.25 1.32 1.41 V DA02 CVRES Resolution 10 Bits DA03 INL Integral Nonlinearity Error -7 -1 +7 LSB AVDD = 3.3V, DACREF = (AVDD/2)V DA04 DNL Differential Nonlinearity Error -5 -0.5 +5 LSB DA05 EOFF Offset Error 0.4 -0.8 2.6 % DA06 EG Gain Error 0.4 -1.8 5.2 % DA07 TSET Settling Time(1) 711 1551 2100 nsec Measured when range=1 (high range), and CMREF<9:0> transitions from 0x1FF to 0x300. Note 1: Parameters are for design guidance only and are not tested in manufacturing. 2: Module is functional at VBOR < VDD < VDDMIN, but with degraded performance. Module functionality is tested but not characterized. DS70000318G-page 330  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-44: DAC OUTPUT BUFFER DC SPECIFICATIONS Standard Operating Conditions (see Note 1): 3.0V to 3.6V DC CHARACTERISTICS Operating temperature: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic Min Typ Max Units Comments No. DA10 RLOAD Resistive Output Load 3K — —  Impedance DA11 CLOAD Output Load Capacitance — 20 35 pF DA12 IOUT Output Current Drive -1740 ±1400 +1770 A Sink and source Strength DA13 VRANGE Full Output Drive Strength AVSS + 250 mV — AVDD – 900 mV V Voltage Range DA14 VLRANGE Output Drive Voltage AVSS + 50 mV — AVDD – 500 mV V Range at Reduced Current Drive of 50 A DA15 IDD Current Consumed when 369 626 948 A Module will always Module is Enabled, consume this High-Power Mode current even if no load is connected to the output DA16 ROUTON Output Impedance when — 1200 —  Module is Enabled Note 1: Module is functional at VBOR < VDD < VDDMIN, but with degraded performance. Module functionality is tested but not characterized.  2008-2014 Microchip Technology Inc. DS70000318G-page 331

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 332  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 25.0 HIGH-TEMPERATURE ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 electrical characteristics for devices operating in an ambient temperature range of -40°C to +150°C. Note: Programming of the Flash memory is not allowed above +125°C. The specifications between -40°C to +150°C are identical to those shown in Section24.0 “Electrical Characteristics” for operation between -40°C to +125°C, with the exception of the parameters listed in this section. Parameters in this section begin with an H, which denotes High temperature. For example, Parameter DC10 in Section24.0 “Electrical Characteristics” is the Industrial and Extended temperature equivalent of HDC10. Absolute maximum ratings for the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 high-temperature devices are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias(3).........................................................................................................-40°C to +150°C Storage temperature.............................................................................................................................. -65°C to +160°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(4) ....................................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(4) ....................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD  3.0V(4) .................................................... -0.3V to 5.6V Maximum current out of VSS pin.............................................................................................................................60 mA Maximum current into VDD pin(2).............................................................................................................................60 mA Maximum junction temperature.............................................................................................................................+155°C Maximum current sourced/sunk by any 4x I/O pin....................................................................................................4 mA Maximum current sourced/sunk by any 8x I/O pin....................................................................................................8 mA Maximum current sourced/sunk by any 16x I/O pin................................................................................................16 mA Maximum current sunk by all ports combined ......................................................................................................180 mA Maximum current sourced by all ports combined(2)..............................................................................................180 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods can affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table25-2). 3: AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 hours. Any design in which the total operating time from 125°C to 150°C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc. 4: Refer to the “Pin Diagrams” section for 5V tolerant pins.  2008-2014 Microchip Technology Inc. DS70000318G-page 333

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 25.1 High-Temperature DC Characteristics TABLE 25-1: OPERATING MIPS VS. VOLTAGE Max MIPS VDD Range Temperature Range Characteristic (in Volts) (in °C) dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 — 3.0V to 3.6V(1) -40°C to +150°C 20 Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer to ParameterBO10 in Table24-11 for BOR values. TABLE 25-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit High-Temperature Devices Operating Junction Temperature Range TJ -40 — +155 °C Operating Ambient Temperature Range TA -40 — +150 °C Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD -  IOH) PD PINT + PI/O W I/O Pin Power Dissipation: I/O =  ({VDD - VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ - TA)/JA W TABLE 25-3: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C for High Temperature Parameter Symbol Characteristic Min Typ Max Units Conditions No. Operating Voltage HDC10 Supply Voltage VDD — 3.0 3.3 3.6 V -40°C to +150°C DS70000318G-page 334  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C for High Temperature Parameter Typical(1) Max Units Conditions No. Power-Down Current (IPD)(2,4) HDC60e 1000 2000 A +150°C 3.3V Base Power-Down Current HDC61c 100 110 A +150°C 3.3V Watchdog Timer Current: IWDT(3) Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. 2: IPD (Sleep) current is measured as follows: • CPU core is off, oscillator is configured in EC mode and external clock active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • All peripheral modules are disabled (PMDx bits are all ones) • The VREGS bit (RCON<8>) = 0 (i.e., core regulator is set to stand-by while the device is in Sleep mode) • JTAG disabled 3: The  current is the additional current consumed when the WDT module is enabled. This current should be added to the base IPD current. 4: These currents are measured on the device containing the most memory in this family.  2008-2014 Microchip Technology Inc. DS70000318G-page 335

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-5: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +150°C for High Temperature Param. Symbol Characteristic Min. Typ. Max. Units Conditions Output Low Voltage I/O Pins: 4x Sink Driver Pins – IOL  3.6 mA, VDD = 3.3V — — 0.4 V RA0-RA2, RB0-RB2, RB5- See Note 1 RB10, RB15, RC1, RC2, RC9, RC10 Output Low Voltage DO10 VOL I/O Pins: IOL  6 mA, VDD = 3.3V — — 0.4 V 8x Sink Driver Pins – RC0, See Note 1 RC3-RC8, RC11-RC13 Output Low Voltage I/O Pins: IOL  12 mA, VDD = 3.3V — — 0.4 V 16x Sink Driver Pins – RA3, See Note 1 RA4, RB3, RB4, RB11-RB14 Output High Voltage I/O Pins: 4x Source Driver Pins – IOL-4 mA, VDD = 3.3V 2.4 — — V RA0-RA2, RB0-RB2, RB5- See Note 1 RB10, RB15, RC1, RC2, RC9, RC10 Output High Voltage DO20 VOH I/O Pins: IOL-8 mA, VDD = 3.3V 2.4 — — V 8x Source Driver Pins – RC0, See Note 1 RC3-RC8, RC11-RC13 Output High Voltage I/O Pins: IOL-16 mA, VDD = 3.3V 2.4 — — V 16x Source Driver Pins – RA3, See Note 1 RA4, RB3, RB4, RB11-RB14 Output High Voltage IOH-3.9 mA, VDD = 3.3V 1.5 — — I/O Pins: See Note 1 4x Source Driver Pins – IOH-3.7 mA, VDD = 3.3V RA0-RA2, RB0-RB2, RB5- 2.0 — — V See Note 1 RB10, RB15, RC1, RC2, RC9, IOH-2 mA, VDD = 3.3V RC10 3.0 — — See Note 1 Output High Voltage IOH-7.5 mA, VDD = 3.3V 1.5 — — I/O Pins: See Note 1 8x Source Driver Pins – RC0, IOH-6.8 mA, VDD = 3.3V DO20A VOH1 RC3-RC8, RC11-RC13 2.0 — — V See Note 1 IOH-3 mA, VDD = 3.3V 3.0 — — See Note 1 Output High Voltage IOH-15 mA, VDD = 3.3V 1.5 — — I/O Pins: See Note 1 16x Source Driver Pins – RA3, IOH-14 mA, VDD = 3.3V RA4, RB3, RB4, RB11-RB14 2.0 — — V See Note 1 IOH-7 mA, VDD = 3.3V 3.0 — — See Note 1 Note 1: Parameters are characterized, but not tested. DS70000318G-page 336  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-6: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. Program Flash Memory HD130 EP Cell Endurance 10,000 — — E/W -40C to +150C(2) HD134 TRETD Characteristic Retention 20 — — Year 1000 E/W cycles or less and no other specifications are violated Note 1: These parameters are assured by design, but are not characterized or tested in manufacturing. 2: Programming of the Flash memory is not allowed above +125°C.  2008-2014 Microchip Technology Inc. DS70000318G-page 337

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 25.2 AC Characteristics and Timing Parameters in this section begin with an H, which denotes Parameters High temperature. For example, ParameterOS53 in Section24.2 “AC Characteristics and Timing The information contained in this section defines Parameters” is the Industrial and Extended temperature dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ equivalent of HOS53. X04 AC characteristics and timing parameters for high- temperature devices. However, all AC timing specifications in this section are the same as those in Section24.2 “AC Characteristics and Timing Parameters”, with the exception of the parameters listed in this section. TABLE 25-7: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +150°C for High Temperature Operating voltage VDD range as described in Table25-1. FIGURE 25-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSC2 VSS 15 pF for OSC2 output TABLE 25-8: PLL CLOCK TIMING SPECIFICATIONS AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) CHARACTERISTICS Operating temperature -40°C  TA  +150°C for High Temperature Param Symbol Characteristic Min Typ Max Units Conditions No. HOS53 DCLK CLKO Stability (Jitter)(1) -5 0.5 5 % Measured over 100 ms period Note 1: These parameters are characterized, but are not tested in manufacturing. DS70000318G-page 338  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-9: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. HSP35 TscH2doV, SDOx Data Output Valid after — 10 25 ns TscL2doV SCKx Edge HSP40 TdiV2scH, Setup Time of SDIx Data Input 28 — — ns TdiV2scL to SCKx Edge HSP41 TscH2diL, Hold Time of SDIx Data Input 35 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized but not tested in manufacturing. TABLE 25-10: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. HSP35 TscH2doV, SDOx Data Output Valid after — 10 25 ns TscL2doV SCKx Edge HSP36 TdoV2sc, SDOx Data Output Setup to 35 — — ns TdoV2scL First SCKx Edge HSP40 TdiV2scH, Setup Time of SDIx Data Input 28 — — ns TdiV2scL to SCKx Edge HSP41 TscH2diL, Hold Time of SDIx Data Input 35 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized but not tested in manufacturing.  2008-2014 Microchip Technology Inc. DS70000318G-page 339

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-11: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. HSP35 TscH2doV, SDOx Data Output Valid after — — 35 ns TscL2doV SCKx Edge HSP40 TdiV2scH, Setup Time of SDIx Data Input 25 — — ns TdiV2scL to SCKx Edge HSP41 TscH2diL, Hold Time of SDIx Data Input to 25 — — ns TscL2diL SCKx Edge HSP51 TssH2doZ SSx  to SDOx Output 15 — 55 ns See Note 2 High-Impedance Note 1: These parameters are characterized but not tested in manufacturing. 2: Assumes 50 pF load on all SPIx pins. TABLE 25-12: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +150°C for High Temperature Param Symbol Characteristic(1) Min Typ Max Units Conditions No. HSP35 TscH2doV, SDOx Data Output Valid after — — 35 ns TscL2doV SCKx Edge HSP40 TdiV2scH, Setup Time of SDIx Data Input 25 — — ns TdiV2scL to SCKx Edge HSP41 TscH2diL, Hold Time of SDIx Data Input 25 — — ns TscL2diL to SCKx Edge HSP51 TssH2doZ SSx  to SDOX Output 15 — 55 ns See Note 2 High-Impedance HSP60 TssL2doV SDOx Data Output Valid after — — 55 ns SSx Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Assumes 50 pF load on all SPIx pins. DS70000318G-page 340  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 26.0 50 MIPS ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 electrical characteristics for devices operating at 50 MIPS. The specifications for 50 MIPS are identical to those shown in Section24.0 “Electrical Characteristics”, with the exception of the parameters listed in this section. Parameters in this section begin with the letter “M”, which denotes 50 MIPS operation. For example, Parameter DC29a in Section24.0 “Electrical Characteristics”, is the up to 40 MIPS operation equivalent of MDC29a. Absolute maximum ratings for the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 50 MIPS devices are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias...............................................................................................................-40°C to +85°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS(3) ...................................................-0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS, when Vdd  3.0V(3) ................................................. -0.3V to +5.6V Voltage on any 5V tolerant pin with respect to Vss, when VDD < 3.0V(3)........................................-0.3V to (VDD + 0.3V) Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin(2)...........................................................................................................................250 mA Maximum current sourced/sunk by any 4x I/O pin..................................................................................................15 mA Maximum current sourced/sunk by any 8x I/O pin..................................................................................................25 mA Maximum current sourced/sunk by any 16x I/O pin................................................................................................45 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports(2)...............................................................................................................200 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table24-2). 3: See the “Pin Diagrams” section for 5V tolerant pins.  2008-2014 Microchip Technology Inc. DS70000318G-page 341

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 26.1 DC Characteristics TABLE 26-1: OPERATING MIPS VS. VOLTAGE Max MIPS VDD Range Temp Range Characteristic (in Volts) (in °C) dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 — 3.0-3.6V(1) -40°C to +85°C 50 Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN. Refer to Parameter BO10 in Table24-11 for BOR values. TABLE 26-2: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Parameter Typical Max Units Conditions No. Operating Current (IDD)(1) MDC29d 105 125 mA -40°C MDC29a 105 125 mA +25°C 3.3V 50 MIPS MDC29b 105 125 mA +85°C Note 1: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are zeroed) • CPU executing while(1) statement • JTAG is disabled DS70000318G-page 342  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 26-3: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Parameter Typical Max Units Conditions No. Idle Current (IIDLE): Core Off, Clock On Base Current(1) MDC45d 64 105 mA -40°C MDC45a 64 105 mA +25°C 3.3V 50 MIPS MDC45b 64 105 mA +85°C Note 1: Base Idle current (IIDLE) is measured as follows: • CPU core is off, oscillator is configured in EC mode and external clock active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are zeroed) • The NVMSIDL bit (NVMCON<12>) = 1 (i.e., Flash regulator is set to standby while the device is in Idle mode) • JTAG is disabled  2008-2014 Microchip Technology Inc. DS70000318G-page 343

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 26-4: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)(1) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Doze Parameter No. Typical Max Units Conditions Ratio MDC74a 80 105 1:2 mA MDC74f 65 105 1:64 mA -40°C 3.3V 50 MIPS MDC74g 65 105 1:128 mA MDC75a 81 105 1:2 mA MDC75f 65 105 1:64 mA +25°C 3.3V 50 MIPS MDC75g 65 105 1:128 mA MDC76a 81 105 1:2 mA MDC76f 65 105 1:64 mA +85°C 3.3V 50 MIPS MDC76g 65 105 1:128 mA Note 1: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDOZE measurements are as follows: • Oscillator is configured in EC mode and external clock active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration Word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are zeroed) • CPU executing while(1) statement • JTAG is disabled DS70000318G-page 344  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 26.2 AC Characteristics and Timing Parameters This section defines the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 AC characteristics and timing parameters for 50 MIPS devices. TABLE 26-5: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Param Symb Characteristic Min Typ(1) Max Units Conditions No. MOS10 FIN External CLKI Frequency DC — 50 MHz EC (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency 3.5 — 10 MHz XT 10 — 50 MHz HS MOS20 TOSC TOSC = 1/FOSC 10 — DC ns MOS25 TCY Instruction Cycle Time(2) 20 — DC ns Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. TABLE 26-6: SIMPLE OCx/PWMx MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Param Symbol Characteristic(1) Min Typ Max Units Conditions No. MOC15 TFD Fault Input to PWMx I/O — — TCY + 10 ns Change MOC20 TFLT Fault Input Pulse Width TCY + 10 — — ns Note 1: These parameters are characterized but not tested in manufacturing.  2008-2014 Microchip Technology Inc. DS70000318G-page 345

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 346  2008-2014 Microchip Technology Inc.

 27.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS 2 0 d 0 8 Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes -201 only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating sP 4 range (e.g., outside specified power supply range) and therefore, outside the warranted range. M I C ic roc FIGURE 27-1: VOH – 4x DRIVER PINS FIGURE 27-3: VOH – 16x DRIVER PINS 3 hip 3 T --00..003300 --00..008800 F e chno --00..002255 3.6V --00..007700 3.6V J0 log 3.3V --00..006600 6 y 3.3V Inc --00..002200 --00..005500 G . A)A) 3V A)A) Absolute Maximum S H (H ( --00..001155 Absolute Maximum H (H ( --00..004400 3V 1 OO OO 0 II II --00..003300 --00..001100 1 --00..002200 / X -0.005 -0.010 0 2 0.000 0.000 a 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 1.00 2.00 3.00 4.00 n VOH (V) VOH (V) d d FIGURE 27-2: VOH – 8x DRIVER PINS s P --00..004400 I C 3.6V --00..003355 3 --00..003300 3.3V 3 F --00..002255 Absolute Maximum J A)A) 3V 1 H (H ( --00..002200 6 OO D II --00..001155 G S7 S 0 -0.010 0 X 0 03 -0.005 0 1 8 2 G 0.000 -pa 0.00 1.00 2.00 3.00 4.00 /X g e 0 3 VOH (V) 4 4 7

D FIGURE 27-4: VOL – 4x DRIVER PINS FIGURE 27-6: VOL – 16x DRIVER PINS d S 7 s 0 0 P 0 00..004400 00..112200 0 3 I 1 C 8 00..003355 G-p 3.6V 00..110000 3.6V 3 ag 00..003300 3.3V 3.3V 3 e 3 00..008800 F 4 00..002255 3V 3V J 8 A)A) A)A) 0 L (L ( 00..002200 L (L ( 00..006600 6 OO OO II 00..001155 Absolute Maximum II Absolute Maximum G 00..004400 S 00..001100 1 0.020 0 0.005 1 0.000 0.000 /X 0.00 1.00 2.00 3.00 4.00 0.00 1.00 2.00 3.00 4.00 0 VOL (V) VOL (V) 2 a n d FIGURE 27-5: VOL – 8x DRIVER PINS d s 00..006600 P I 00..005500 3.6V C 3 3.3V 3 00..004400 3V F  200 L (A)L (A) 00..003300 J1 8-2 IOIO Absolute Maximum 6 01 00..002200 G 4 M S icro 0.010 X ch 0 ip T 0.000 2 e / ch 0.00 1.00 2.00 3.00 4.00 X n o 0 lo VOL (V) g 4 y In c .

 FIGURE 27-7: TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 27-9: TYPICAL IDOZE CURRENT @ VDD = 3.3V 2 0 d 0 8 -2 11222200 118 s 01 P 4 M 11002200 108 IC icro 98 3 c hip 882200 A) 88 3 Technology Inc Current (µA)Current (µA)DD 464622220000 Current (mOZEO 4567488888 40 MIPS 50 MIPS FJ06G . PP D S II 220 I 38 1 28 0 20 1 18 / -40 25 65 85 125 150 X 1:1 1:2 1:64 1:128 0 Temperature (Celsius) Doze Ratio 2 a n FIGURE 27-8: TYPICAL IDD CURRENT @ VDD = 3.3V FIGURE 27-10: TYPICAL IIDLE CURRENT @ VDD = 3.3V d 112200 7700 d s 111100 P 6655 I 110000 C 3 6600 A)A) 9900 A)A) 3 mm mm F e (e ( 8800 e (e ( 5555 J gg gg aa aa 1 erer 7700 erer vv vv 6 AA AA 5500 G D 60 S7 S 0 45 0 50 X 0 0 3 0 18 40 40 2 G -pa 10 20 30 40 50 10 20 30 40 50 /X g e 3 MIPS MIPS 0 4 4 9

D FIGURE 27-11: TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 27-13: TYPICAL INTREF @ VDD = 3.3V d S 7 s 0 0 P 00 77..4455 11..3366 3 I 1 C 8 77..44 G-p 11..3355 3 a 77..3355 3 ge 350 cy (MHz)cy (MHz) 7777..22..5533 V)V) 1111....33333434 FJ0 enen F (F ( 6 ququ 77..22 RERE 11..3322 G FreFre 77..1155 NTNT S C C II 11..3311 RR 1 FF 77.11 0 7.05 1.3 1 / 7 1.29 X 0 -40 25 85 125 150 -40 25 85 125 150 2 Temperature (Celsius) Temperature (Celsius) a n d FIGURE 27-12: TYPICAL LPRC FREQUENCY @ VDD = 3.3V d s 3344 P I 3322 C 3 z)z) 3300 3 HH kk F  2008-2 equency (equency ( 22226868 J16 0 rr 2244 G 1 FF 4 M RC RC 2222 S icro LPLP X ch 20 0 ip T 2 e 18 / chn -40 25 85 125 150 X o 0 log Temperature (Celsius) 4 y In c .

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 18-Lead SOIC (.300”) Example XXXXXXXXXXXX dsPIC33FJ06 XXXXXXXXXXXX GS101-I/SO XXXXXXXXXXXX e3 YYWWNNN 0830235 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX dsPIC33FJ06GS XXXXXXXXXXXXXXXXXXXX 202-E/SO e3 XXXXXXXXXXXXXXXXXXXX YYWWNNN 0830235 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX dsPIC33FJ06GS XXXXXXXXXXXXXXXXX 202-E/SPe3 YYWWNNN 0830235 28-Lead QFN-S Example XXXXXXXX 33FJ06GS XXXXXXXX 202EMM e3 YYWWNNN 0830235 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information.  2008-2014 Microchip Technology Inc. DS70000318G-page 351

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 28.1 Package Marking Information (Continued) 28-Lead UQFN Example XXXXXXXX 33FJ06GS XXXXXXXX 202EMX e3 YYWWNNN 0830235 44-Lead QFN Example XXXXXXXXXX dsPIC33FJ16 XXXXXXXXXX GS504-E/ML e3 XXXXXXXXXX 0830235 YYWWNNN 44-Lead TQFP Example XXXXXXXXXX dsPIC33FJ XXXXXXXXXX 16GS504 XXXXXXXXXX -E/PTe3 YYWWNNN 0830235 44-Lead VTLA (TLA) Example XXXXXXXXXX dsPIC33FJ XXXXXXXXXX 16GS504 XXXXXXXXXX -E/TL e3 YYWWNNN 0830235 DS70000318G-page 352  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 28.2 Package Details Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2014 Microchip Technology Inc. DS70000318G-page 353

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000318G-page 354  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2014 Microchip Technology Inc. DS70000318G-page 355

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000318G-page 356  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2014 Microchip Technology Inc. DS70000318G-page 357

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000318G-page 358  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:13)(cid:14)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)(cid:20)(cid:21)(cid:7)(cid:16)(cid:9)(cid:22)(cid:13)(cid:4)(cid:5)(cid:12)(cid:13)(cid:6)(cid:9)(cid:23)(cid:10)(cid:15)(cid:24)(cid:9)(cid:25)(cid:9)(cid:26)(cid:27)(cid:27)(cid:9)(cid:28)(cid:12)(cid:16)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)(cid:10)(cid:15)(cid:20)(cid:22)(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 6(cid:15)(cid:7)&! (cid:19)7,8.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)(cid:4) (cid:20)(cid:30)-(cid:29) (cid:20)(cid:30)(cid:29)(cid:4) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)--(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)<(cid:29) (cid:20)(cid:3)(cid:24)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)-(cid:23)(cid:29) (cid:30)(cid:20)-?(cid:29) (cid:30)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:4) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:4)1  2008-2014 Microchip Technology Inc. DS70000318G-page 359

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)#(cid:21)(cid:7)(cid:8)(cid:9)$(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7)&(cid:6)(cid:9)(cid:23)’’(cid:24)(cid:9)(cid:25)(cid:9)()()(cid:27)*+(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)#$!(cid:4)(cid:10) ,(cid:12)(cid:18)-(cid:9)(cid:27)*.(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)/(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13)&(cid:18)- !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E2 E b 2 2 1 1 K N N L NOTE1 TOPVIEW BOTTOMVIEW A A3 A1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 (cid:3)< (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:29)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:5)(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) -(cid:20)?(cid:29) -(cid:20)(cid:5)(cid:4) (cid:23)(cid:20)(cid:5)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)- (cid:4)(cid:20)-< (cid:4)(cid:20)(cid:23)- ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)(cid:29)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# @ (cid:4)(cid:20)(cid:3)(cid:4) = = !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:3)(cid:23)1 DS70000318G-page 360  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)#(cid:21)(cid:7)(cid:8)(cid:9)$(cid:16)(cid:7)(cid:18)%(cid:9)!(cid:30)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:7)(cid:19)(cid:11)(cid:7)&(cid:6)(cid:9)(cid:23)’’(cid:24)(cid:9)(cid:25)(cid:9)()()(cid:27)*+(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)(cid:9)(cid:31)#$!(cid:4)(cid:10) ,(cid:12)(cid:18)-(cid:9)(cid:27)*.(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)/(cid:30)(cid:13)(cid:18)(cid:7)(cid:19)(cid:18)(cid:9)(cid:5)(cid:6)(cid:13)&(cid:18)- !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2008-2014 Microchip Technology Inc. DS70000318G-page 361

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 28-Lead Plastic Quad Flat, No Lead Package (MX) - 6x6x0.5mm Body [UQFN] Ultra-Thin with 0.40 x 0.60 mm Terminal Width/Length and Corner Anchors Note: (cid:41)(cid:82)(cid:85)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:80)(cid:82)(cid:86)(cid:87)(cid:3)(cid:70)(cid:88)(cid:85)(cid:85)(cid:72)(cid:81)(cid:87)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:3)(cid:71)(cid:85)(cid:68)(cid:90)(cid:76)(cid:81)(cid:74)(cid:86)(cid:15)(cid:3)(cid:83)(cid:79)(cid:72)(cid:68)(cid:86)(cid:72)(cid:3)(cid:86)(cid:72)(cid:72)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:48)(cid:76)(cid:70)(cid:85)(cid:82)(cid:70)(cid:75)(cid:76)(cid:83)(cid:3)(cid:51)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:76)(cid:81)(cid:74)(cid:3)(cid:54)(cid:83)(cid:72)(cid:70)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:79)(cid:82)(cid:70)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:68)(cid:87) (cid:75)(cid:87)(cid:87)(cid:83)(cid:29)(cid:18)(cid:18)(cid:90)(cid:90)(cid:90)(cid:17)(cid:80)(cid:76)(cid:70)(cid:85)(cid:82)(cid:70)(cid:75)(cid:76)(cid:83)(cid:17)(cid:70)(cid:82)(cid:80)(cid:18)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:76)(cid:81)(cid:74) (cid:39) (cid:36) (cid:37) (cid:49) (cid:49)(cid:50)(cid:55)(cid:40)(cid:3)(cid:20) (cid:20) (cid:21) (cid:11)(cid:39)(cid:36)(cid:55)(cid:56)(cid:48)(cid:3)(cid:36)(cid:12) (cid:40) (cid:11)(cid:39)(cid:36)(cid:55)(cid:56)(cid:48)(cid:3)(cid:37)(cid:12) (cid:21)(cid:59) (cid:19)(cid:17)(cid:20)(cid:24) (cid:38) (cid:21)(cid:59) (cid:19)(cid:17)(cid:20)(cid:24) (cid:38) (cid:55)(cid:50)(cid:51)(cid:3)(cid:57)(cid:44)(cid:40)(cid:58) (cid:36) (cid:38) (cid:19)(cid:17)(cid:20)(cid:19) (cid:38) (cid:54)(cid:40)(cid:36)(cid:55)(cid:44)(cid:49)(cid:42) (cid:51)(cid:47)(cid:36)(cid:49)(cid:40) (cid:3) (cid:11)(cid:36)(cid:22)(cid:12) (cid:36)(cid:20) (cid:69)(cid:21) (cid:19)(cid:17)(cid:19)(cid:27) (cid:38) (cid:49)(cid:50)(cid:55)(cid:40)(cid:3)(cid:23) (cid:54)(cid:44)(cid:39)(cid:40)(cid:3)(cid:57)(cid:44)(cid:40)(cid:58) (cid:39)(cid:21) (cid:19)(cid:17)(cid:20)(cid:19) (cid:38) (cid:36) (cid:37) (cid:72) (cid:40)(cid:21) (cid:46) (cid:21) (cid:20) (cid:49) (cid:47) (cid:69) (cid:19)(cid:17)(cid:20)(cid:19) (cid:38) (cid:36) (cid:37) (cid:49)(cid:50)(cid:55)(cid:40)(cid:3)(cid:23) (cid:19)(cid:17)(cid:19)(cid:24) (cid:38) (cid:37)(cid:50)(cid:55)(cid:55)(cid:50)(cid:48)(cid:3)(cid:57)(cid:44)(cid:40)(cid:58) (cid:48)(cid:76)(cid:70)(cid:85)(cid:82)(cid:70)(cid:75)(cid:76)(cid:83)(cid:3)(cid:55)(cid:72)(cid:70)(cid:75)(cid:81)(cid:82)(cid:79)(cid:82)(cid:74)(cid:92)(cid:3)(cid:39)(cid:85)(cid:68)(cid:90)(cid:76)(cid:81)(cid:74)(cid:3)(cid:3)(cid:38)(cid:19)(cid:23)(cid:16)(cid:19)(cid:21)(cid:19)(cid:28)(cid:37)(cid:3)(cid:54)(cid:75)(cid:72)(cid:72)(cid:87)(cid:3)(cid:20)(cid:3)(cid:82)(cid:73)(cid:3)(cid:21) DS70000318G-page 362  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 28-Lead Plastic Quad Flat, No Lead Package (MX) - 6x6x0.5mm Body [UQFN] Ultra-Thin with 0.40 x 0.60 mm Terminal Width/Length and Corner Anchors Note: (cid:41)(cid:82)(cid:85)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:80)(cid:82)(cid:86)(cid:87)(cid:3)(cid:70)(cid:88)(cid:85)(cid:85)(cid:72)(cid:81)(cid:87)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:3)(cid:71)(cid:85)(cid:68)(cid:90)(cid:76)(cid:81)(cid:74)(cid:86)(cid:15)(cid:3)(cid:83)(cid:79)(cid:72)(cid:68)(cid:86)(cid:72)(cid:3)(cid:86)(cid:72)(cid:72)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:48)(cid:76)(cid:70)(cid:85)(cid:82)(cid:70)(cid:75)(cid:76)(cid:83)(cid:3)(cid:51)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:76)(cid:81)(cid:74)(cid:3)(cid:54)(cid:83)(cid:72)(cid:70)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:79)(cid:82)(cid:70)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:68)(cid:87) (cid:75)(cid:87)(cid:87)(cid:83)(cid:29)(cid:18)(cid:18)(cid:90)(cid:90)(cid:90)(cid:17)(cid:80)(cid:76)(cid:70)(cid:85)(cid:82)(cid:70)(cid:75)(cid:76)(cid:83)(cid:17)(cid:70)(cid:82)(cid:80)(cid:18)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:76)(cid:81)(cid:74) (cid:56)(cid:81)(cid:76)(cid:87)(cid:86) (cid:48)(cid:44)(cid:47)(cid:47)(cid:44)(cid:48)(cid:40)(cid:55)(cid:40)(cid:53)(cid:54) (cid:39)(cid:76)(cid:80)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81)(cid:3)(cid:47)(cid:76)(cid:80)(cid:76)(cid:87)(cid:86) (cid:48)(cid:44)(cid:49) (cid:49)(cid:50)(cid:48) (cid:48)(cid:36)(cid:59) (cid:49)(cid:88)(cid:80)(cid:69)(cid:72)(cid:85)(cid:3)(cid:82)(cid:73)(cid:3)(cid:51)(cid:76)(cid:81)(cid:86) (cid:49) (cid:21)(cid:27) (cid:51)(cid:76)(cid:87)(cid:70)(cid:75) (cid:72) (cid:19)(cid:17)(cid:25)(cid:24)(cid:3)(cid:37)(cid:54)(cid:38) (cid:50)(cid:89)(cid:72)(cid:85)(cid:68)(cid:79)(cid:79)(cid:3)(cid:43)(cid:72)(cid:76)(cid:74)(cid:75)(cid:87) (cid:36) (cid:19)(cid:17)(cid:23)(cid:19) (cid:19)(cid:17)(cid:24)(cid:19) (cid:19)(cid:17)(cid:25)(cid:19) (cid:54)(cid:87)(cid:68)(cid:81)(cid:71)(cid:82)(cid:73)(cid:73) (cid:36)(cid:20) (cid:19)(cid:17)(cid:19)(cid:19) (cid:19)(cid:17)(cid:19)(cid:21) (cid:19)(cid:17)(cid:19)(cid:24) (cid:55)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:3)(cid:55)(cid:75)(cid:76)(cid:70)(cid:78)(cid:81)(cid:72)(cid:86)(cid:86) (cid:11)(cid:36)(cid:22)(cid:12) (cid:19)(cid:17)(cid:20)(cid:21)(cid:26)(cid:3)(cid:53)(cid:40)(cid:41) (cid:50)(cid:89)(cid:72)(cid:85)(cid:68)(cid:79)(cid:79)(cid:3)(cid:58)(cid:76)(cid:71)(cid:87)(cid:75) (cid:40) (cid:25)(cid:17)(cid:19)(cid:19)(cid:3)(cid:37)(cid:54)(cid:38) (cid:40)(cid:91)(cid:83)(cid:82)(cid:86)(cid:72)(cid:71)(cid:3)(cid:51)(cid:68)(cid:71)(cid:3)(cid:58)(cid:76)(cid:71)(cid:87)(cid:75) (cid:40)(cid:21) (cid:23)(cid:17)(cid:19)(cid:19) (cid:50)(cid:89)(cid:72)(cid:85)(cid:68)(cid:79)(cid:79)(cid:3)(cid:47)(cid:72)(cid:81)(cid:74)(cid:87)(cid:75) (cid:39) (cid:25)(cid:17)(cid:19)(cid:19)(cid:3)(cid:37)(cid:54)(cid:38) (cid:40)(cid:91)(cid:83)(cid:82)(cid:86)(cid:72)(cid:71)(cid:3)(cid:51)(cid:68)(cid:71)(cid:3)(cid:47)(cid:72)(cid:81)(cid:74)(cid:87)(cid:75) (cid:39)(cid:21) (cid:23)(cid:17)(cid:19)(cid:19) (cid:55)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:3)(cid:58)(cid:76)(cid:71)(cid:87)(cid:75) (cid:69) (cid:19)(cid:17)(cid:22)(cid:24) (cid:19)(cid:17)(cid:23)(cid:19) (cid:19)(cid:17)(cid:23)(cid:24) (cid:38)(cid:82)(cid:85)(cid:81)(cid:72)(cid:85)(cid:3)(cid:51)(cid:68)(cid:71) (cid:69)(cid:21) (cid:19)(cid:17)(cid:21)(cid:24) (cid:19)(cid:17)(cid:23)(cid:19) (cid:19)(cid:17)(cid:23)(cid:24) (cid:55)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:3)(cid:47)(cid:72)(cid:81)(cid:74)(cid:87)(cid:75) (cid:47) (cid:19)(cid:17)(cid:24)(cid:24) (cid:19)(cid:17)(cid:25)(cid:19) (cid:19)(cid:17)(cid:25)(cid:24) (cid:55)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:16)(cid:87)(cid:82)(cid:16)(cid:40)(cid:91)(cid:83)(cid:82)(cid:86)(cid:72)(cid:71)(cid:3)(cid:51)(cid:68)(cid:71) (cid:46) (cid:19)(cid:17)(cid:21)(cid:19) (cid:16) (cid:16) Notes: (cid:20)(cid:17) (cid:51)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:89)(cid:76)(cid:86)(cid:88)(cid:68)(cid:79)(cid:3)(cid:76)(cid:81)(cid:71)(cid:72)(cid:91)(cid:3)(cid:73)(cid:72)(cid:68)(cid:87)(cid:88)(cid:85)(cid:72)(cid:3)(cid:80)(cid:68)(cid:92)(cid:3)(cid:89)(cid:68)(cid:85)(cid:92)(cid:15)(cid:3)(cid:69)(cid:88)(cid:87)(cid:3)(cid:80)(cid:88)(cid:86)(cid:87)(cid:3)(cid:69)(cid:72)(cid:3)(cid:79)(cid:82)(cid:70)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:90)(cid:76)(cid:87)(cid:75)(cid:76)(cid:81)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:75)(cid:68)(cid:87)(cid:70)(cid:75)(cid:72)(cid:71)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68)(cid:17) (cid:21)(cid:17) (cid:51)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:3)(cid:76)(cid:86)(cid:3)(cid:86)(cid:68)(cid:90)(cid:3)(cid:86)(cid:76)(cid:81)(cid:74)(cid:88)(cid:79)(cid:68)(cid:87)(cid:72)(cid:71) (cid:22)(cid:17) (cid:39)(cid:76)(cid:80)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81)(cid:76)(cid:81)(cid:74)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:87)(cid:82)(cid:79)(cid:72)(cid:85)(cid:68)(cid:81)(cid:70)(cid:76)(cid:81)(cid:74)(cid:3)(cid:83)(cid:72)(cid:85)(cid:3)(cid:36)(cid:54)(cid:48)(cid:40)(cid:3)(cid:60)(cid:20)(cid:23)(cid:17)(cid:24)(cid:48) (cid:37)(cid:54)(cid:38)(cid:29)(cid:3)(cid:37)(cid:68)(cid:86)(cid:76)(cid:70)(cid:3)(cid:39)(cid:76)(cid:80)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81)(cid:17)(cid:3)(cid:55)(cid:75)(cid:72)(cid:82)(cid:85)(cid:72)(cid:87)(cid:76)(cid:70)(cid:68)(cid:79)(cid:79)(cid:92)(cid:3)(cid:72)(cid:91)(cid:68)(cid:70)(cid:87)(cid:3)(cid:89)(cid:68)(cid:79)(cid:88)(cid:72)(cid:3)(cid:86)(cid:75)(cid:82)(cid:90)(cid:81)(cid:3)(cid:90)(cid:76)(cid:87)(cid:75)(cid:82)(cid:88)(cid:87)(cid:3)(cid:87)(cid:82)(cid:79)(cid:72)(cid:85)(cid:68)(cid:81)(cid:70)(cid:72)(cid:86)(cid:17) (cid:53)(cid:40)(cid:41)(cid:29)(cid:3)(cid:53)(cid:72)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:70)(cid:72)(cid:3)(cid:39)(cid:76)(cid:80)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81)(cid:15)(cid:3)(cid:88)(cid:86)(cid:88)(cid:68)(cid:79)(cid:79)(cid:92)(cid:3)(cid:90)(cid:76)(cid:87)(cid:75)(cid:82)(cid:88)(cid:87)(cid:3)(cid:87)(cid:82)(cid:79)(cid:72)(cid:85)(cid:68)(cid:81)(cid:70)(cid:72)(cid:15)(cid:3)(cid:73)(cid:82)(cid:85)(cid:3)(cid:76)(cid:81)(cid:73)(cid:82)(cid:85)(cid:80)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:83)(cid:88)(cid:85)(cid:83)(cid:82)(cid:86)(cid:72)(cid:86)(cid:3)(cid:82)(cid:81)(cid:79)(cid:92)(cid:17) (cid:23)(cid:17) (cid:50)(cid:88)(cid:87)(cid:72)(cid:85)(cid:80)(cid:82)(cid:86)(cid:87)(cid:3)(cid:83)(cid:82)(cid:85)(cid:87)(cid:76)(cid:82)(cid:81)(cid:86)(cid:3)(cid:82)(cid:73)(cid:3)(cid:70)(cid:82)(cid:85)(cid:81)(cid:72)(cid:85)(cid:3)(cid:86)(cid:87)(cid:85)(cid:88)(cid:70)(cid:87)(cid:88)(cid:85)(cid:72)(cid:86)(cid:3)(cid:80)(cid:68)(cid:92)(cid:3)(cid:89)(cid:68)(cid:85)(cid:92)(cid:3)(cid:86)(cid:79)(cid:76)(cid:74)(cid:75)(cid:87)(cid:79)(cid:92)(cid:17) (cid:48)(cid:76)(cid:70)(cid:85)(cid:82)(cid:70)(cid:75)(cid:76)(cid:83)(cid:3)(cid:55)(cid:72)(cid:70)(cid:75)(cid:81)(cid:82)(cid:79)(cid:82)(cid:74)(cid:92)(cid:3)(cid:39)(cid:85)(cid:68)(cid:90)(cid:76)(cid:81)(cid:74)(cid:3)(cid:3)(cid:38)(cid:19)(cid:23)(cid:16)(cid:19)(cid:21)(cid:19)(cid:28)(cid:37)(cid:3)(cid:54)(cid:75)(cid:72)(cid:72)(cid:87)(cid:3)(cid:21)(cid:3)(cid:82)(cid:73)(cid:3)(cid:21)  2008-2014 Microchip Technology Inc. DS70000318G-page 363

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: (cid:41)(cid:82)(cid:85)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:80)(cid:82)(cid:86)(cid:87)(cid:3)(cid:70)(cid:88)(cid:85)(cid:85)(cid:72)(cid:81)(cid:87)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:3)(cid:71)(cid:85)(cid:68)(cid:90)(cid:76)(cid:81)(cid:74)(cid:86)(cid:15)(cid:3)(cid:83)(cid:79)(cid:72)(cid:68)(cid:86)(cid:72)(cid:3)(cid:86)(cid:72)(cid:72)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:48)(cid:76)(cid:70)(cid:85)(cid:82)(cid:70)(cid:75)(cid:76)(cid:83)(cid:3)(cid:51)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:76)(cid:81)(cid:74)(cid:3)(cid:54)(cid:83)(cid:72)(cid:70)(cid:76)(cid:73)(cid:76)(cid:70)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:79)(cid:82)(cid:70)(cid:68)(cid:87)(cid:72)(cid:71)(cid:3)(cid:68)(cid:87) (cid:75)(cid:87)(cid:87)(cid:83)(cid:29)(cid:18)(cid:18)(cid:90)(cid:90)(cid:90)(cid:17)(cid:80)(cid:76)(cid:70)(cid:85)(cid:82)(cid:70)(cid:75)(cid:76)(cid:83)(cid:17)(cid:70)(cid:82)(cid:80)(cid:18)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:76)(cid:81)(cid:74) DS70000318G-page 364  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04  2008-2014 Microchip Technology Inc. DS70000318G-page 365

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 DS70000318G-page 366  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04  2008-2014 Microchip Technology Inc. DS70000318G-page 367

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 ..(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:15)(cid:16)(cid:7)(cid:17)(cid:18)(cid:12)(cid:19)(cid:9)0-(cid:12)(cid:13)(cid:9)#(cid:21)(cid:7)(cid:8)(cid:9)$(cid:16)(cid:7)(cid:18)1(cid:7)(cid:19)(cid:11)(cid:9)(cid:23)(cid:15)0(cid:24)(cid:9)(cid:25)(cid:9)2(cid:27))2(cid:27))2(cid:9)(cid:28)(cid:28)(cid:9)(cid:29)(cid:30)(cid:8)(cid:14)%(cid:9)(cid:2)*(cid:27)(cid:27)(cid:9)(cid:28)(cid:28)(cid:9)(cid:31)0#$(cid:15) !(cid:30)(cid:18)(cid:6)" 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D1 E e E1 N b NOTE1 1 2 3 NOTE2 α A c φ β A1 A2 L L1 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)9(cid:14)(cid:28)#! 7 (cid:23)(cid:23) 9(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)<(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)(cid:24)(cid:29) (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)(cid:29) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) = (cid:4)(cid:20)(cid:30)(cid:29) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:29) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)C -(cid:20)(cid:29)C (cid:5)C : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:5) (cid:4)(cid:20)(cid:23)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:30)(cid:30)C (cid:30)(cid:3)C (cid:30)-C (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:30)(cid:30)C (cid:30)(cid:3)C (cid:30)-C !(cid:30)(cid:18)(cid:6)(cid:17)" (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) ,(cid:11)(cid:28)’%(cid:14)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:8)(cid:10)(cid:9)(cid:15)(cid:14)(cid:9)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:2)(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)A(cid:2)!(cid:7)B(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:30)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)?1 DS70000318G-page 368  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2008-2014 Microchip Technology Inc. DS70000318G-page 369

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 44-Terminal Very Thin Leadless Array Package (TL) – 6x6x0.9 mm Body With Exposed Pad [VTLA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) 2X 0.20 C 2X (DATUM A) 0.20 C TOP VIEW 0.10 C A1 C A SEATING PLANE 0.08 C SIDE VIEW 0.10 C A B D2 11 22 0.10 C A 23 10 DETAIL A (NE-1) X e E2 2 32 1 N 33 44X K (ND-1) X e BOTTOM VIEW Microchip Technology Drawing C04-157D Sheet 1 of 2 DS70000318G-page 370  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 44-Terminal Very Thin Leadless Array Package (TL) – 6x6x0.9 mm Body With Exposed Pad [VTLA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (DATUM e/2 A OR B) e 44X b 0.10 C A B 0.05 C 44X L DETAIL A Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Terminals N 44 Number of Terminals per Side ND 12 Number of Terminals per Side NE 10 Pitch e 0.50 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.025 - 0.075 Overall Width E 6.00 BSC Exposed Pad Width E2 4.40 4.55 4.70 Overall Length D 6.00 BSC Exposed Pad Length D2 4.40 4.55 4.70 Terminal Width b 0.20 0.25 0.30 Terminal Length L 0.20 0.25 0.30 Terminal-to-Exposed Pad K 0.20 - - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-157D Sheet 2 of 2  2008-2014 Microchip Technology Inc. DS70000318G-page 371

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 DS70000318G-page 372  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 APPENDIX A: REVISION HISTORY Revision B (June 2008) This revision includes minor typographical and Revision A (January 2008) formatting changes throughout the data sheet text. In addition, redundant information was removed that is This is the initial revision of this document. now available in the respective chapters of the dsPIC33F/PIC24H Family Reference Manual, which can be obtained from the Microchip web site (www.microchip.com). The major changes are referenced by their respective section in the following table. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Moved location of Note 1 (RPn pin) references (see “Pin Diagrams”). Signal Controllers” Section3.0 “Memory Organization” Updated CPU Core Register map SFR reset value for CORCON (see Table3-1). Removed Interrupt Controller Register Map SFR IPC29 and updated reset values for IPC0, IPC1, IPC14, IPC16, IPC23, IPC24, IPC27, and IPC28 (see Table3-5). Removed Interrupt Controller Register Map SFR IPC24 and IPC29 and updated reset values for IPC0, IPC1, IPC2, IPC14, IPC16, IPC23, IPC27, and IPC28 (see Table3-6). Removed Interrupt Controller Register Map SFR IPC24 and updated reset values for IPC1, IPC2, IPC4, IPC14, IPC16, IPC23, IPC24, IPC27, and IPC28 (see Table3-7). Updated Interrupt Controller Register Map SFR reset values for IPC1, IPC14, IPC16, IPC23, IPC24, IPC27, and IPC28 (see Table3-8). Updated Interrupt Controller Register Map SFR reset values for IPC1, IPC14, IPC16, IPC23, IPC24, IPC25, IPC26, IPC27, IPC28, and IPC29 (see Table3-9). Updated Interrupt Controller Register Map SFR reset values for IPC1, IPC4, IPC14, IPC16, IPC23, IPC24, IPC25, IPC26, IPC27, IPC28, and IPC29 (see Table3-10). Added SFR definitions for RPOR16 and RPOR17 (see Table3-34, Table3-35, and Table3-36). Updated bit definitions for PORTA, PORTB, and PORTC SFRs (ODCA, ODCB, and ODCC) (see Table3-37, Table3-38, Table3-39, and Table3-40). Updated bit definitions and reset value for System Control Register map SFR CLKDIV (see Table3-41). Added device-specific information to title of PMD Register Map (see Table3-47). Added device-specific PMD Register Maps (see Table3-46, Table3-45, and Table3-43).  2008-2014 Microchip Technology Inc. DS70000318G-page 373

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section7.0 “Oscillator Removed the first sentence of the third clock source item (External Clock) in Configuration” Section7.1.1 “System Clock sources” Updated the default bit values for DOZE and FRCDIV in the Clock Divisor Register (see Register7-2). Section8.0 “Power-Saving Added the following six registers: Features” • “PMD1: Peripheral Module Disable Control Register 1” • “PMD2: Peripheral Module Disable Control Register 2” • “PMD3: Peripheral Module Disable Control Register 3” • “PMD4: Peripheral Module Disable Control Register 4” • “PMD6: Peripheral Module Disable Control Register 6” • “PMD7: Peripheral Module Disable Control Register 7” Section9.0 “I/O Ports” Added paragraph and Table9-1 to Section9.1.1 “Open-Drain Configuration”, which provides details on I/O pins and their functionality. Removed 9.1.2 “5V Tolerance”. Updated MUX range and removed virtual pin details in Figure9-2. Updated PWM Input Name descriptions in Table9-1. Added Section9.4.2.3 “Virtual Pins”. Updated bit values in all Peripheral Pin Select Input Registers (see Register9-1 through Register9-14). Updated bit name information for Peripheral Pin Select Output Registers RPOR16 and RPOR17 (see Register9-30 and Register9-31). Added the following two registers: • “RPOR16: Peripheral Pin Select Output Register 16” • “RPOR17: Peripheral Pin Select Output Register 17” Removed the following sections: • 9.4.2 “Available Peripherals” • 9.4.3.2 “Virtual Input Pins” • 9.4.3.4 “Peripheral Mapping” • 9.4.5 “Considerations for Peripheral Pin Selection” (and all subsections) Section14.0 “High-Speed PWM” Added Note 1 (remappable pin reference) to Figure14-1. Added Note 2 (Duty Cycle resolution) to PWM Master Duty Cycle Register (Register14-5), PWM Generator Duty Cycle Register (Register14-7), and PWM Secondary Duty Cycle Register (Register14-8). Added Note 2 and Note 3 and updated bit information for CLSRC and FLTSRC in the PWM Fault Current-Limit Control Register (Register14-15). Section15.0 “Serial Peripheral Removed the following sections, which are now available in the related Interface (SPI)” section of the dsPIC33F/PIC24H Family Reference Manual: • 15.1 “Interrupts” • 15.2 “Receive Operations” • 15.3 “Transmit Operations” • 15.4 “SPI Setup” (retained Figure 15-1: SPI Module Block Diagram) DS70000318G-page 374  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section16.0 “Inter-Integrated Removed the following sections, which are now available in the related Circuit (I2C™)” section of the dsPIC33F/PIC24H Family Reference Manual: • 16.3 “I2C Interrupts” • 16.4 “Baud Rate Generator” (retained Figure 16-1: I2C Block Diagram) • 16.5 “I2C Module Addresses • 16.6 “Slave Address Masking” • 16.7 “IPMI Support” • 16.8 “General Call Address Support” • 16.9 “Automatic Clock Stretch” • 16.10 “Software Controlled Clock Stretching (STREN = 1)” • 16.11 “Slope Control” • 16.12 “Clock Arbitration” • 16.13 “Multi-Master Communication, Bus Collision, and Bus Arbitration Section17.0 “Universal Removed the following sections, which are now available in the related Asynchronous Receiver Transmitter section of the dsPIC33F/PIC24H Family Reference Manual: (UART)” • 17.1 “UART Baud Rate Generator” • 17.2 “Transmitting in 8-bit Data Mode • 17.3 “Transmitting in 9-bit Data Mode • 17.4 “Break and Sync Transmit Sequence” • 17.5 “Receiving in 8-bit or 9-bit Data Mode” • 17.6 “Flow Control Using UxCTS and UxRTS Pins” • 17.7 “Infrared Support” Removed IrDA references and Note 1, and updated the bit and bit value descriptions for UTXINV (UxSTA<14>) in the UARTx Status and Control Register (see Register17-2). Section18.0 “High-Speed 10-bit Updated bit value information for Analog-to-Digital Control Register (see Analog-to-Digital Converter (ADC)” Register18-1). Updated TRGSRC6 bit value for Timer1 period match in the Analog-to- Digital Convert Pair Control Register 3 (see Register18-8).  2008-2014 Microchip Technology Inc. DS70000318G-page 375

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section23.0 “Electrical Updated Typ values for Thermal Packaging Characteristics (Table23-3). Characteristics” Removed Typ value for DC Temperature and Voltage Specifications Parameter DC12 (Table23-4). Updated all Typ values and conditions for DC Characteristics: Operating Current (IDD), updated last sentence in Note 2 (Table 23-5). Updated all Typ values for DC Characteristics: Idle Current (IIDLE) (see Table23-6). Updated all Typ values for DC Characteristics: Power Down Current (IPD) (see Table23-7). Updated all Typ values for DC Characteristics: Doze Current (IDOZE) (see Table23-8). Added Note 4 (reference to new table containing digital-only and analog pin information, as well as Current Sink/Source capabilities) in the I/O Pin Input Specifications (Table23-9). Updated Max value for BOR electrical characteristics Parameter BO10 (see Table23-11). Swapped Min and Typ values for Program Memory Parameters D136 and D137 (Table23-12). Updated Typ values for Internal RC Accuracy Parameter F20 and added Extended temperature range to table heading (see Table23-19). Removed all values for Reset, Watchdog Timer, Oscillator Start-up Timer, and Power-up Timer Parameter SY20 and updated conditions, which now refers to Section20.4 “Watchdog Timer (WDT)” and LPRC Parameter F21a (see Table23-22). Added specifications to High-Speed PWM Module Timing Requirements for Tap Delay (Table23-29). Updated Min and Max values for 10-bit High-Speed Analog-to-Digital Module Parameters AD01 and AD11 (see Table23-36). Updated Max value and unit of measure for DAC AC Specification (see Table23-40). DS70000318G-page 376  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Revision C and D (March 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: • Changed all instances of OSCI to OSC1 and OSCO to OSC2 • Changed all instances of PGCx/EMUCx and PGDx/EMUDx (where x = 1, 2, or 3) to PGECx and PGEDx • Changed all instances of VDDCORE and VDDCORE/ VCAP to VCAP/VDDCORE Other major changes are referenced by their respective section in the following table. TABLE A-2: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Added “Application Examples” to list of features Signal Controllers” Updated all pin diagrams to denote the pin voltage tolerance (see “Pin Diagrams”). Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which references pin connections to VSS. Section1.0 “Device Overview” Added ACMP1-ACMP4 pin names and Peripheral Pin Select capability column to Pinout I/O Descriptions (see Table1-1). Section2.0 “Guidelines for Getting Added new section to the data sheet that provides guidelines on getting Started with 16-bit Digital Signal started with 16-bit Digital Signal Controllers. Controllers” Section3.0 “CPU” Updated CPU Core Block Diagram with a connection from the DSP Engine to the Y Data Bus (see Figure3-1). Vertically extended the X and Y Data Bus lines in the DSP Engine Block Diagram (see Figure3-3). Section4.0 “Memory Organization” Updated Reset value for ADCON in Table4-25. Removed reference to dsPIC33FJ06GS102 devices in the PMD Register Map and updated bit definitions for PMD1 and PMD6, and removed PMD7 (see Table4-43). Added a new PMD Register Map, which references dsPIC33FJ06GS102 devices (see Table4-44). Updated RAM stack address and SPLIM values in the third paragraph of Section4.2.6 “Software Stack” Removed Section4.2.7 “Data Ram Protection Feature”. Section5.0 “Flash Program Updated Section5.3 “Programming Operations” with programming time Memory” formula.  2008-2014 Microchip Technology Inc. DS70000318G-page 377

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section8.0 “Oscillator Added Note 2 to the Oscillator System Diagram (see Figure8-1). Configuration” Added a paragraph regarding FRC accuracy at the end of Section8.1.1 “System Clock Sources”. Added Note 1 and Note 2 to the OSCON register (see Register). Added Note 1 to the OSCTUN register (see Register8-4). Added Note 3 to Section8.4.2 “Oscillator Switching Sequence”. Section10.0 “I/O Ports” Removed Table 9-1 and added reference to pin diagrams for I/O pin availability and functionality. Added paragraph on ADPCFG register default values to Section10.3 “Configuring Analog Port Pins”. Added Note box regarding PPS functionality with input mapping to Section10.6.2.1 “Input Mapping”. Section15.0 “High-Speed PWM” Updated Note 2 in the PTCON register (see Register15-1). Added Note 4 to the PWMCONx register (see Register15-6). Updated Notes for the PHASEx and SPHASEx registers (see Register15-9 and Register15-10, respectively). Section16.0 “Serial Peripheral Added Note 2 and Note 3 to the SPIxCON1 register (see Register16-2). Interface (SPI)” Section18.0 “Universal Updated the Notes in the UxMode register (see Register18-1). Asynchronous Receiver Transmitter (UART)” Updated the UTXINV bit settings in the UxSTA register and added Note 1 (see Register18-2). Section19.0 “High-Speed 10-bit Updated the SLOWCLK and ADCS<2:0> bit settings and updated Note 1in Analog-to-Digital Converter (ADC)” the ADCON register (see Register19-1). Removed all notes in the ADPCFG register and replaced them with a single note (see Register19-4). Updated the SWTRGx bit settings in the ADCPCx registers (see Register19-5, Register19-6, Register19-7, and Register19-8). DS70000318G-page 378  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section24.0 “Electrical Updated Typical values for Thermal Packaging Characteristics (see Characteristics” Table24-3). Updated Min and Max values for Parameter DC12 (RAM Data Retention Voltage) and added Note 4 (see Table24-4). Updated Characteristics for I/O Pin Input Specifications (see Table24-9). Added ISOURCE to I/O Pin Output Specifications (see Table24-10). Updated Program Memory values for Parameters 136, 137, and 138 (renamed to 136a, 137a, and 138a), added Parameters 136b, 137b, and 138b, and added Note 2 (see Table24-12). Added Parameter OS42 (GM) to the External Clock Timing Requirements (see Table24-16). Updated Conditions for symbol TPDLY (Tap Delay) and added symbol ACLK (PWM Input Clock) to the High-Speed PWM Module Timing Requirements (see Table24-29). Updated Parameters AD01 and AD02 in the 10-bit High-Speed Analog-to- Digital Module Specifications (see Table24-36). Updated Parameters AD50b, AD55b, and AD56b, and removed Parameters AD57b and AD60b from the 10-bit High-Speed Analog-to-Digital Module Timing Requirements (see Table24-37).  2008-2014 Microchip Technology Inc. DS70000318G-page 379

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Revision E (December 2009) The revision includes the following global update: • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-3: MAJOR SECTION UPDATES Section Name Update Description “16-bit Microcontrollers and Digital Changed CN6 to CN5 on pin 16 of dsPIC33FJ16GS502 28-pin SPDIP, Signal Controllers (up to 16-Kbyte SOIC pin diagram. Flash and up to 2-Kbyte SRAM) with High-Speed PWM, ADC and Comparators” Section2.0 “Guidelines for Getting Removed the 10 Ohm resistor from Figure2-1. Started with 16-bit Digital Signal Controllers” Section4.0 “Memory Organization” Renamed bit 13 of the REFOCON SFR in the System Control Register Map from ROSIDL to ROSSLP and changed the All Resets value from ‘0000’ to ‘2300’ for the ACLKCON SFR (see 4-41). Section8.0 “Oscillator Configuration” Updated the default reset values from R/W-0 to R/W-1 for the SELACLK and APSTSCLR<2:0> bits in the ACLKCON register (see Register8-5). Renamed the ROSIDL bit to ROSSLP in the REFOCON register (see Register8-6). Section9.0 “Power-Saving Features” Updated the last paragraph of Section9.2.2 “Idle Mode” to clarify when instruction execution begins. Added Note 1 to the PMD1 register (see Register9-1). Section10.0 “I/O Ports” Changed the reference to digital-only pins to 5V tolerant pins in the second paragraph of Section10.2 “Open-Drain Configuration”. Section15.0 “High-Speed PWM” Updated the smallest pulse width value from 0x0008 to 0x0009 in Note 1 of the shaded note that follows the MDC register (see Register15-5). Updated the smallest pulse width value from 0x0008 to 0x0009 and the maximum pulse width value from 0x0FFEF to 0x0008 in Note 2 of the shaded note that follows the PDCx and SDCx registers (see Register15-7 and Register15-8). Added Note 2 and updated the FLTDAT<1:0> and CLDAT<1:0> bits, changing the word ‘data’ to ‘state’ in the IOCONx register (see Register15-14). Section18.0 “Universal Updated the two baud rate range features to: 10 Mbps to 38 bps at 40 Asynchronous Receiver Transmitter MIPS. (UART)” DS70000318G-page 380  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section19.0 “High-Speed 10-bit Updated Note 1 in the ADCPC0 register (see Register19-5). Analog-to-Digital Converter (ADC)” Updated Note 3 in the ADCPC1 register (see Register19-6). Updated Note 2 in the ADCPC2 and ADCPC3 registers (see Register19- 7 and Register19-8). Section21.0 “Special Features” Updated the second paragraph and removed the fourth paragraph in Section21.1 “Configuration Bits”. Updated the Device Configuration Register Map (see Table21-1). Section24.0 “Electrical Updated the Absolute Maximum Ratings for high temperature and added Characteristics” Note 4. Updated Idle Current (IIDLE) Typical values in Table24-6. Updated the Typ and Max values for Parameter DI50 in the I/O Pin Input Specifications table (see Table24-9). Updated the Typ and Max values for Parameters DO10 and DO27 and the Min and Typ values for Parameter DO20 in the I/O Pin Output Specifications (see Table24-10). Added parameter numbers to the Auxiliary PLL Clock Timing Specifications (see Table24-18). Added parameters numbers and updated the Internal RC Accuracy Min, Typ, and Max values (see Table24-19 and Table24-20). Added parameter numbers, Note 2, updated the Min and Typ parameter values for MP31 and MP32, and removed the conditions for MP10 and MP11 in the High-Speed PWM Module Timing Requirements (see Table24-29). Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics (see Table24-14). Added Parameter IM51 to the I2Cx Bus Data Timing Requirements (Master Mode) (see Table24-34). Updated the Max value for Parameter AD33 in the 10-bit High-Speed Analog-to-Digital Module Specifications (see Table24-36). Updated the titles and added parameter numbers to the Comparator and DAC Module Specifications (see Table24-38 and Table24-39) and the DAC Output Buffer Specifications (see Table24-40).  2008-2014 Microchip Technology Inc. DS70000318G-page 381

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Revision F (January 2012) All occurrences of VDDCORE have been removed throughout the document. This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-4: MAJOR SECTION UPDATES Section Name Update Description “16-Bit Digital Signal Controllers (up Added the VTLA package to the dsPIC33FJ16GS404 and to 16-Kbyte Flash and up to 2-Kbyte dsPIC33FJ16GS504 devices (see TABLE 1: “dsPIC33FJ06GS101/X02 SRAM) with High-Speed PWM, ADC and dsPIC33FJ16GSX02/X04 Controller Families”). and Comparators” Added the “Referenced Sources” section. The following updates were made to the “Pin Diagrams” section: • Added 5V tolerant pin shading to pins 24-26 in the 28-pin SPDIP, SOIC package for the dsPIC33FJ16GS402 • Updated pin 31 of the 44-pin QFN package for the dsPIC33FJ16GS404 • Added VTLA pin diagrams for the dsPIC33FJ16GS404 and dsPIC33FJ16GS504 devices Section1.0 “Device Overview” Removed the Precision Band Gap Reference from the device block diagram (see Figure1-1). Updated the Pinout I/O Descriptions for AVDD, and AVSS (see Table1-1). Section2.0 “Guidelines for Getting Updated the Minimum Recommended Connection (see Figure2-1). Started with 16-bit Digital Signal Controllers” Section8.0 “Oscillator Updated the Oscillator System Diagram (see Figure8-1). Configuration” Added auxiliary clock configuration restrictions in Section8.2 “Auxiliary Clock Generation”. Updated or added notes regarding register reset on a POR (see Register8-1 through Register8-5). Section19.0 “High-Speed 10-bit Added Note 2 to ADCON: Analog-to-Digital Control Register Analog-to-Digital Converter (ADC)” (see Register19-1). Removed all notes from ADSTAT: Analog-to-Digital Status Register (see Register19-2). Section20.0 “High-Speed Analog Updated the Comparator Module Block Diagram (see Figure20-1). Comparator” Section21.0 “Special Features” Add a new paragraph at the beginning of Section21.1 “Configuration Bits”. Added the RTSP Effect column to the dsPIC33F Configuration Bits Description table (see Table21-2). Updated the Connections for the On-chip Voltage Regulator diagram (see Figure21-1). Updated the first paragraph of Section21.7 “In-Circuit Debugger”. DS70000318G-page 382  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-4: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section24.0 “Electrical Updated the Absolute Maximum Ratings. Characteristics” Updated the Operating MIPS vs. Voltage (see Table24-1). Updated Parameter DC10 and Note 4, and removed Parameter DC18 from the DC Temperature and Voltage Specifications (see Table24-4). Updated Note 2 in the IDD Operating Current specification (see Table24-5). Updated all Typical values and Note 2 in the IIDLE Operating Current specification (see Table24-6). Updated Typical values for Parameters DC60d, DC60a, DC60b, and DC60c, and Note 2 in the IPD Operating Current specification (see Table24-7). Added all Typical values and Note 2 in the IDOZE Operating Current specification (see Table24-8). Updated Parameters DI19 and DI50, added Parameters DI128, DI129, DI60a, DI60b, and DI60c, and removed Parameter DI57 in the I/O Pin Input Specifications (see Table24-9). Revised all I/O Pinout Output Specifications (see Table24-10). Added Notes 2 and 3 to the BOR Electrical Characteristics (see Table24- 11). Added Note 1 to Internal Voltage Regulator Specifications (see Table24-13). Updated the External Clock Timing diagram (see Figure24-2). Added Note 2 to the PLL Clock Timing Specifications (see Table24-17). Removed Note 2 from the Internal FRC Accuracy (see Table24-19). Updated Parameters DO31 and DO32 in the I/O Timing Requirements (see Table24-21). Updated the External Clock Timing Requirements for Timer1, Timer2, and Timer3 (see Table24-23, Table24-24, and Table24-25, respectively). Updated Parameters OC15 and OC20 in the Simple OC/PWM Mode Timing Requirements (see Table24-28). Revised all SPIx Module Timing Characteristics diagrams and all Timing Requirements (see Figure24-11 through Figure24-18 and Table24-30 through Table24-37, respectively). Added Note 2 to the 10-bit High-Speed ADC Module Specifications (see Table24-40). Added Note 2 to the 10-bit High-Speed ADC Module Timing Requirements (see Table24-41). Added Note 2 to the Comparator Module Specifications (see Table24-42). Added Parameter DA08 and Note 2 in the DAC Module Specifications (see Table24-43). Updated Parameter DA16 and Note 2 in the DAC Output Buffer DC Specifications (see Table24-44).  2008-2014 Microchip Technology Inc. DS70000318G-page 383

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-4: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section26.0 “50 MIPS Electrical Added new chapter in support of 50 MIPS devices. Characteristics” Section27.0 “DC and AC Device Added new chapter. Characteristics Graphs” Section28.0 “Packaging Added 44-pin VTLA package marking information and diagrams (see Information” Section28.1 “Package Marking Information” and Section28.2 “Package Details”, respectively). “Product Identification System” Added the TL package definition. DS70000318G-page 384  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Revision G (May 2014) The values for the TUN<5:0> bits in Register8-4 (OSCTUN) have changed. The DC Characteristics Idle Current values in Section24.0 “Electrical Characteristics” have been updated. The timer specifications in Section26.0 “50 MIPS Electrical Characteristics” have been removed. All diagrams in Section28.0 “Packaging Information” have been updated. Minor text edits have been applied throughout the document.  2008-2014 Microchip Technology Inc. DS70000318G-page 385

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 386  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 INDEX A Code Examples Erasing a Program Memory Page..............................87 AC Characteristics............................................300, 338, 345 Initiating a Programming Sequence...........................88 Internal FRC Accuracy..............................................303 Loading Write Buffers.................................................88 Internal LPRC Accuracy............................................303 Port Write/Read........................................................156 Load Conditions................................................300, 338 PWRSAV Instruction Syntax....................................147 ADC Code Protection........................................................267, 273 Control Registers......................................................246 CodeGuard Security.........................................................267 Functionality..............................................................239 Configuration Bits.............................................................267 Arithmetic Logic Unit (ALU).................................................38 Description................................................................268 Assembler Configuration Register Map..............................................267 MPASM Assembler...................................................284 Configuring Analog Port Pins............................................156 Auxiliary Clock Generation................................................138 CPU B Control Registers........................................................34 Barrel Shifter.......................................................................42 CPU Clocking System......................................................136 Bit-Reversed Addressing....................................................76 PLL Configuration.....................................................137 Example......................................................................77 Selection...................................................................136 Implementation...........................................................76 Sources....................................................................136 Sequence Table (16-Entry).........................................77 Customer Change Notification Service.............................392 Block Diagrams Customer Notification Service..........................................392 16-Bit Timer1 Module................................................183 Customer Support.............................................................392 Connections for On-Chip Voltage Regulator.............270 D DSP Engine................................................................39 DAC..................................................................................264 dsPIC33F06GS101 Devices with 1 SAR..................240 Output Range...........................................................264 dsPIC33F06GS102 Devices with 1 SAR..................241 Data Accumulators and Adder/Subtracter..........................40 dsPIC33F06GS202 Devices with 1 SAR..................242 Data Space Write Saturation......................................42 dsPIC33F16GS402/404 Devices with 1 SAR...........243 Overflow and Saturation.............................................40 dsPIC33F16GS502 Devices with 2 SARs................244 Round Logic...............................................................41 dsPIC33F16GS504 Devices with 2 SARs................245 Write Back..................................................................41 dsPIC33FJ06GS101/X02 and Data Address Space...........................................................45 dsPIC33FJ16GSX02/X04...................................18 Alignment....................................................................45 dsPIC33FJ06GS101/X02 and Memory Map for dsPIC33FJ06GS101/102 Devices dsPIC33FJ16GSX02/X04 CPU Core..................32 with 256 Bytes of RAM.......................................46 High-Speed Analog Comparator...............................263 Memory Map for dsPIC33FJ06GS202 Device I2CX Module.............................................................226 with 1-Kbyte RAM...............................................47 Input Capture x.........................................................191 Memory Map for dsPIC33FJ16GS402/404/502/504 Multiplexing of Remappable Output for RPn.............159 Devices with 2-Kbyte RAM.................................48 Oscillator System......................................................135 Near Data Space........................................................45 Output Compare x Module........................................193 Software Stack...........................................................73 Partitioned Output Pair, Complementary Width..........................................................................45 PWM Mode.......................................................200 Data Addressing PLL............................................................................137 Overview.....................................................................31 Remappable MUX Input for U1RX............................157 DC and AC Characteristics Reset System..............................................................89 Graphs and Tables...................................................347 Shared Port Structure...............................................155 DC Characteristics....................................................288, 342 Simplified Conceptual High-Speed PWM.................199 SPIx Module..............................................................219 Doze Current (IDOZE)........................................294, 344 High Temperature.....................................................334 Timer2/3 (32-Bit).......................................................187 I/O Pin Input Specifications......................................295 Type B Timer............................................................185 I/O Pin Output Specifications............................297, 336 Type C Timer............................................................185 UART1......................................................................233 Idle Current (IIDLE)............................................292, 343 Watchdog Timer (WDT)............................................271 Operating Current (IDD)....................................290, 342 Operating MIPS vs. Voltage.....................288, 334, 342 Brown-out Reset (BOR)......................................94, 267, 270 Power-Down Current (IPD)................................293, 335 C Program Memory..............................................299, 337 C Compilers Temperature and Voltage.........................................334 MPLAB XC Compilers...............................................284 Temperature and Voltage Specifications..................289 Clock Switching.................................................................146 Thermal Operating Conditions..................................334 Enabling....................................................................146 Sequence..................................................................146  2008-2014 Microchip Technology Inc. DS70000318G-page 387

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Demo/Development Boards, Evaluation and Instruction Addressing Modes............................................73 Starter Kits................................................................286 File Register Instructions............................................73 Development Support.......................................................283 Fundamental Modes Supported.................................74 Third-Party Tools......................................................286 MAC Instructions........................................................74 Doze Mode........................................................................148 MCU Instructions........................................................73 DSP Engine.........................................................................38 Move and Accumulator Instructions............................74 Multiplier......................................................................40 Other Instructions.......................................................74 Instruction Set E Overview...................................................................278 Electrical Characteristics...................................................287 Summary..................................................................275 50 MIPS....................................................................341 Instruction-Based Power-Saving Modes...........................147 AC.............................................................................338 Idle............................................................................148 AC Characteristics and Sleep........................................................................147 Timing Parameters....................................300, 345 Interfacing Program and Data Memory Spaces..................78 BOR..........................................................................298 Internal RC Oscillator Equations Use with WDT...........................................................271 Device Operating Frequency....................................136 Internet Address...............................................................392 FOSC Calculation.......................................................137 Interrupts Maximum Row Write Time..........................................84 Alternate Interrupt Vector Table (AIVT)......................97 Minimum Row Write Time...........................................84 Control and Status Registers....................................100 Programming Time.....................................................84 IECx..................................................................100 XT with PLL Mode Example......................................137 IFSx..................................................................100 Errata..................................................................................14 INTCON1..........................................................100 External Reset (EXTR)........................................................95 INTCON2..........................................................100 INTTREG..........................................................100 F IPCx..................................................................100 Fail-Safe Clock Monitor (FSCM).......................................146 Interrupt Vector Table (IVT)........................................97 Flash Program Memory.......................................................83 Reset Sequence.........................................................97 Control Registers........................................................84 Setup Procedures.....................................................134 Operations..................................................................84 Initialization.......................................................134 Programming Algorithm..............................................87 Interrupt Disable...............................................134 RTSP Operation..........................................................84 Interrupt Service Routine..................................134 Table Instructions........................................................83 Trap Service Routine........................................134 Flexible Configuration.......................................................267 Interrupts Coincident with Power Save Instructions.........148 G J Guidelines for Getting Started with 16-Bit DSCs.................21 JTAG Boundary Scan Interface........................................267 H JTAG Interface..................................................................272 High-Speed 10-Bit Analog-to-Digital M Converter (ADC).......................................................239 Memory Organization.........................................................43 High-Speed Analog Comparator.......................................263 Microchip Internet Web Site..............................................392 Digital Logic..............................................................264 Modulo Addressing.............................................................75 Input Range..............................................................264 Applicability.................................................................76 Interaction with I/O Buffers........................................264 Operation Example.....................................................75 High-Speed PWM.............................................................197 Start and End Address...............................................75 Control Registers......................................................200 W Address Register Selection....................................75 High-Temperature Electrical Characteristics.....................333 MPLAB Assembler, Linker, Librarian................................284 I MPLAB ICD 3 In-Circuit Debugger...................................285 MPLAB PM3 Device Programmer....................................285 I/O Ports............................................................................155 MPLAB REAL ICE In-Circuit Emulator System................285 Parallel I/O (PIO).......................................................155 MPLAB X Integrated Development Write/Read Timing....................................................156 Environment Software..............................................283 I2C MPLAB X SIM Software Simulator...................................285 Control Registers......................................................227 MPLIB Object Librarian.....................................................284 Operating Modes......................................................225 MPLINK Object Linker......................................................284 In-Circuit Debugger...........................................................272 In-Circuit Emulation...........................................................267 O In-Circuit Serial Programming (ICSP).......................267, 272 Open-Drain Configuration.................................................156 Input Capture....................................................................191 Oscillator Configuration....................................................135 Control Register........................................................192 Control Registers......................................................139 Input Change Notification..................................................156 Output Compare...............................................................193 Modes.......................................................................194 Operation Diagram...................................................194 DS70000318G-page 388  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 P Interrupt Controller for dsPIC33FJ06GS102..............53 Interrupt Controller for dsPIC33FJ06GS202..............54 Packaging.........................................................................351 Interrupt Controller for dsPIC33FJ16GS402/404.......55 Details.......................................................................353 Interrupt Controller for dsPIC33FJ16GS502..............56 Marking.....................................................................351 Interrupt Controller for dsPIC33FJ16GS504..............57 Peripheral Module Disable (PMD)....................................148 NVM............................................................................71 Peripheral Pin Select (PPS)..............................................157 Output Compare for dsPIC33FJ06GS101/X02..........59 PICkit 3 In-Circuit Debugger/Programmer........................285 Output Compare for dsPIC33FJ16GSX02 Pinout I/O Descriptions (table)............................................19 and dsPIC33FJ06GSX04...................................59 Power-on Reset (POR).......................................................94 PMD for dsPIC33FJ06GS101....................................71 Power-Saving Features....................................................147 PMD for dsPIC33FJ06GS102....................................71 Clock Frequency and Switching................................147 PMD for dsPIC33FJ06GS202....................................72 Power-up Timer (PWRT)....................................................94 PMD for dsPIC33FJ16GS402/404.............................72 PPS PMD for dsPIC33FJ16GS502/504.............................72 Control Registers......................................................161 PORTA.......................................................................70 Selectable Input Sources..........................................158 PORTB for dsPIC33FJ06GS101................................70 Selection Output Sources.........................................159 PORTB for dsPIC33FJ06GS102/202 Program Address Space.....................................................43 and dsPIC33FJ16GS402/404/502/504...............70 Construction................................................................78 PORTC for dsPIC33FJ16GS404/504.........................70 Data Access from Program Memory Using PPS Input...................................................................68 Program Space Visibility.....................................81 PPS Output for dsPIC33FJ06GS101.........................68 Data Access from Program Memory Using PPS Output for dsPIC33FJ06GS102/202 Table Instructions...............................................80 and dsPIC33FJ16GS402/502.............................69 Data Access from, Address Generation......................79 PPS Output for dsPIC33FJ16GS404/504..................69 Memory Maps.............................................................43 SPI1............................................................................62 Table Read Instructions System Control...........................................................71 TBLRDH.............................................................80 Timers for dsPIC33FJ06GS101/X02..........................58 TBLRDL..............................................................80 Timers for dsPIC33FJ16GSX02/X04..........................58 Visibility Operation......................................................81 UART1........................................................................62 Program Memory Registers Interrupt Vector...........................................................44 ACLKCON (Auxiliary Clock Divisor Control).............144 Organization................................................................44 ADBASE (Analog-to-Digital Base)............................250 Reset Vector...............................................................44 ADCON (Analog-to-Digital Control)..........................247 R ADCPC0 (Analog-to-Digital Convert Pair Reference Clock Generation.............................................138 Control 0)..........................................................251 Register Maps ADCPC1 (Analog-to-Digital Convert Pair Analog Comparator Control for Control 1)..........................................................254 dsPIC33FJ06GS202...........................................67 ADCPC2 (Analog-to-Digital Convert Pair Analog Comparator Control for Control 2)..........................................................257 dsPIC33FJ16GS503/504....................................67 ADCPC3 (Analog-to-Digital Convert Pair Change Notification for dsPIC33FJ06GS101.............51 Control 3)..........................................................260 Change Notification for dsPIC33FJ06GS102/202 ADPCFG (Analog-to-Digital Port Configuration).......250 and dsPIC33FJ16GS402/502.............................51 ADSTAT (Analog-to-Digital Status)..........................249 Change Notification for ALTDTRx (PWMx Alternate Dead-Time)..................210 dsPIC33FJ16GS404/504....................................51 CLKDIV (Clock Divisor)............................................141 CPU Core....................................................................50 CMPCONx (Comparator Control x)..........................265 High-Speed 10-Bit ADC for dsPIC33FJ06GS101.......63 CMPDACx (Comparator DAC x Control)..................266 High-Speed 10-Bit ADC for dsPIC33FJ06GS102.......63 CORCON (Core Control)....................................36, 101 High-Speed 10-Bit ADC for dsPIC33FJ06GS202.......64 DTRx (PWMx Dead-Time)........................................210 High-Speed 10-Bit ADC for FCLCONx (PWMx Fault Current-Limit Control)........214 dsPIC33FJ16GS402/404....................................64 I2CxCON (I2Cx Control)...........................................228 High-Speed 10-Bit ADC for dsPIC33FJ16GS502.......65 I2CxMSK (I2Cx Slave Mode Address Mask)............232 High-Speed 10-Bit ADC for dsPIC33FJ16GS504.......66 I2CxSTAT (I2Cx Status)...........................................230 High-Speed PWM.......................................................59 ICxCON (Input Capture x Control)............................192 High-Speed PWM Generator 1...................................60 IEC0 (Interrupt Enable Control 0).............................112 High-Speed PWM Generator 2 for dsPIC33FJ06GS101/ IEC1 (Interrupt Enable Control 1).............................114 202 and dsPIC33FJ16GSX02/X04.....................60 IEC3 (Interrupt Enable Control 3).............................115 High-Speed PWM Generator 3 for IEC4 (Interrupt Enable Control 4).............................115 dsPIC33FJ16GSX02/X04...................................61 IEC5 (Interrupt Enable Control 5).............................116 High-Speed PWM Generator 4 for dsPIC33FJ06GS101 IEC6 (Interrupt Enable Control 6).............................117 and dsPIC33FJ16GS50X...................................61 IEC7 (Interrupt Enable Control 7).............................118 I2C1............................................................................62 IFS0 (Interrupt Flag Status 0)...................................105 Input Capture for dsPIC33FJ06GS202.......................58 IFS1 (Interrupt Flag Status 1)...................................107 Input Capture for dsPIC33FJ16GSX02/X04...............59 IFS3 (Interrupt Flag Status 3)...................................108 Interrupt Controller for dsPIC33FJ06GS101...............52 IFS4 (Interrupt Flag Status 4)...................................108  2008-2014 Microchip Technology Inc. DS70000318G-page 389

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 IFS5 (Interrupt Flag Status 5)...................................109 RPOR1 (Peripheral Pin Select Output 1)..................175 IFS6 (Interrupt Flag Status 6)...................................110 RPOR10 (Peripheral Pin Select Output 10)..............179 IFS7 (Interrupt Flag Status 7)...................................111 RPOR11 (Peripheral Pin Select Output 11)..............180 INTCON1 (Interrupt Control 1)..................................102 RPOR12 (Peripheral Pin Select Output 12)..............180 INTTREG (Interrupt Control and Status)...................133 RPOR13 (Peripheral Pin Select Output 13)..............181 IOCONx (PWMx I/O Control)....................................212 RPOR14 (Peripheral Pin Select Output 14)..............181 IPC0 (Interrupt Priority Control 0).............................119 RPOR16 (Peripheral Pin Select Output 16)..............182 IPC1 (Interrupt Priority Control 1).............................120 RPOR17 (Peripheral Pin Select Output 17)..............182 IPC14 (Interrupt Priority Control 14).........................125 RPOR2 (Peripheral Pin Select Output 2)..................175 IPC16 (Interrupt Priority Control 16).........................125 RPOR3 (Peripheral Pin Select Output 3)..................176 IPC2 (Interrupt Priority Control 2).............................121 RPOR4 (Peripheral Pin Select Output 4)..................176 IPC23 (Interrupt Priority Control 23).........................126 RPOR5 (Peripheral Pin Select Output 5)..................177 IPC24 (Interrupt Priority Control 24).........................127 RPOR6 (Peripheral Pin Select Output 6)..................177 IPC25 (Interrupt Priority Control 25).........................128 RPOR7 (Peripheral Pin Select Output 7)..................178 IPC26 (Interrupt Priority Control 26).........................129 RPOR8 (Peripheral Pin Select Output 8)..................178 IPC27 (Interrupt Priority Control 27).........................130 RPOR9 (Peripheral Pin Select Output 9)..................179 IPC28 (Interrupt Priority Control 28).........................131 SDCx (PWMx Secondary Duty Cycle)......................207 IPC29 (Interrupt Priority Control 29).........................132 SEVTCMP (PWM Special Event Compare).............204 IPC3 (Interrupt Priority Control 3).............................122 SPHASEx (PWMx Secondary Phase-Shift)..............209 IPC4 (Interrupt Priority Control 4).............................123 SPIxCON1 (SPIx Control 1)......................................221 IPC5 (Interrupt Priority Control 5).............................124 SPIxCON2 (SPIx Control 2)......................................223 IPC7 (Interrupt Priority Control 7).............................124 SPIxSTAT (SPIx Status and Control).......................220 LEBCONx (Leading-Edge Blanking Control)............217 SR (CPU STATUS).............................................34, 101 MDC (PWM Master Duty Cycle)...............................204 STRIGx (PWMx Secondary Trigger NVMCON (Flash Memory Control).............................85 Compare Value)...............................................216 NVMKEY (Nonvolatile Memory Key)..........................86 T1CON (Timer1 Control)..........................................184 OCxCON (Output Compare x Control.......................195 TRGCONx (PWMx Trigger Control).........................211 OSCCON (Oscillator Control)...................................139 TRIGx (PWMx Primary Trigger OSCTUN (FRC Oscillator Tuning)............................143 Compare Value)...............................................216 PDCx (PWMx Generator Duty Cycle).......................207 TxCON (Timerx Control, x = 2).................................188 PHASEx (PWMx Primary Phase-Shift).....................208 TyCON (Timery Control, y = 3).................................189 PLLFBD (PLL Feedback Divisor)..............................142 UxMODE (UARTx Mode)..........................................234 PMD1 (Peripheral Module Disable Control 1)...........149 UxSTA (UARTx Status and Control).........................236 PMD2 (Peripheral Module Disable Control 2)...........150 Reset..................................................................................89 PMD3 (Peripheral Module Disable Control 3)...........151 Configuration Mismatch..............................................95 PMD4 (Peripheral Module Disable Control 4)...........151 Illegal Condition..........................................................95 PMD6 (Peripheral Module Disable Control 6)...........152 Illegal Opcode.......................................................89, 95 PMD7 (Peripheral Module Disable Control 7)...........153 Security.................................................................89, 96 PTCON (PWM Time Base Control)..........................201 System........................................................................92 PTCON2 (PWM Clock Divider Select)......................203 Trap Conflict...............................................................95 PTPER (PWM Master Time Base)............................203 Uninitialized W Register..................................89, 95, 96 PWMCAPx (Primary PWMx Time Resets.................................................................................89 Base Capture)...................................................218 Resources Required for Digital Phase-Shift PWMCONx (PWMx Control).....................................205 ZVT Converter............................................................30 RCON (Reset Control)................................................90 Revision History................................................................373 REFOCON (Reference Oscillator Control)................145 S RPINR0 (Peripheral Pin Select Input 0)....................161 RPINR1 (Peripheral Pin Select Input 1)....................162 Serial Peripheral Interface (SPI).......................................219 RPINR11 (Peripheral Pin Select Input 11)................165 Software RESET Instruction (SWR)...................................95 RPINR18 (Peripheral Pin Select Input 18)................166 Software Stack Pointer, Frame Pointer RPINR20 (Peripheral Pin Select Input 20)................167 CALL Stack Frame.....................................................73 RPINR21 (Peripheral Pin Select Input 21)................168 Special Features of the CPU............................................267 RPINR29 (Peripheral Pin Select Input 29)................169 Symbols Used in Opcode Descriptions............................276 RPINR3 (Peripheral Pin Select Input 3)....................163 T RPINR30 (Peripheral Pin Select Input 30)................170 RPINR31 (Peripheral Pin Select Input 31)................171 Temperature and Voltage Specifications RPINR32 (Peripheral Pin Select Input 32)................172 AC.....................................................................300, 338 RPINR33 (Peripheral Pin Select Input 33)................173 Timer1...............................................................................183 RPINR34 (Peripheral Pin Select Input 34)................174 Timer2/3............................................................................185 RPINR7 (Peripheral Pin Select Input 7)....................164 16-Bit Operation.......................................................186 RPOR0 (Peripheral Pin Select Output 0)..................174 32-Bit Operation.......................................................186 DS70000318G-page 390  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Timing Diagrams Timing Specifications Analog-to-Digital Conversion per Input.....................329 10-Bit High-Speed ADC Module...............................328 Brown-out Situations...................................................94 Auxiliary PLL Clock...................................................302 External Clock...........................................................301 Comparator Module..................................................330 High-Speed PWMx...................................................311 DAC Module.............................................................330 High-Speed PWMx Fault..........................................311 DAC Output Buffer DC.............................................331 I/O.............................................................................304 High-Speed PWMx Requirements............................311 I2Cx Bus Data (Master Mode)..................................324 I2Cx Bus Data Requirements (Master Mode)...........325 I2Cx Bus Data (Slave Mode)....................................326 I2Cx Bus Data Requirements (Slave Mode).............327 I2Cx Bus Start/Stop Bits (Master Mode)...................324 Output Compare x Requirements.............................309 I2Cx Bus Start/Stop Bits Slave Mode)......................326 PLL Clock.........................................................302, 338 Input Capture x (ICx).................................................309 Reset, Watchdog Timer, Oscillator Start-up Timer, OCx/PWMx...............................................................310 Power-up Timer and Brown-out Reset Output Compare x (OCx)..........................................309 Requirements...................................................306 Reset, Watchdog Timer, Oscillator Start-up Timer Simple OCx/PWMx Mode Requirements.................310 and Power-up Timer.........................................305 Timer1 External Clock Requirements.......................307 SPIx Master Mode (Full-Duplex, CKE = 0, Timer2 External Clock Requirements.......................308 CKP = x, SMP = 1)...........................................315 Timer3 External Clock Requirements.......................308 SPIx Master Mode (Full-Duplex, CKE = 1, U CKP = x, CMP = 1)...........................................314 SPIx Master Mode (Half-Duplex, Universal Asynchronous Receiver Transmit Only, CKE = 0)...................................312 Transmitter (UART)..................................................233 SPIx Master Mode (Half-Duplex, Using the RCON Status Bits...............................................96 Transmit Only, CKE = 1)...................................312 V SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0)...........................................322 Voltage Regulator (On-Chip)............................................270 SPIx Slave Mode (Full-Duplex, CKE = 0, W CKP = 1, SMP = 0)...........................................320 Watchdog Timer (WDT)............................................267, 271 SPIx Slave Mode (Full-Duplex, CKE = 1, Programming Considerations...................................271 CKP = 0, SMP = 0)...........................................316 Watchdog Timer Time-out Reset (WDTO).........................95 SPIx Slave Mode (Full-Duplex, CKE = 1, WWW Address.................................................................392 CKP = 1, SMP = 0)...........................................318 WWW, On-Line Support.....................................................14 System Reset..............................................................93 Timer1, 2, 3 External Clock.......................................307 Timing Requirements 10-Bit, High-Speed ADC Requirements....................329 External Clock...................................................301, 345 I/O.............................................................................304 Input Capture x.........................................................309 Simple OCx/PWMx Mode.........................................345 SPIx Master Mode (CKE = 0)...................................339 SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1)...........................................315 SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1)...........................................314 SPIx Master Mode (Half-Duplex, Transmit Only)..................................................313 SPIx Module Master Mode (CKE = 1).......................339 SPIx Module Slave Mode (CKE = 0).........................340 SPIx Module Slave Mode (CKE = 1).........................340 SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0)...........................................323 SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0)...........................................321 SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0)...........................................317 SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0)...........................................319  2008-2014 Microchip Technology Inc. DS70000318G-page 391

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 392  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2008-2014 Microchip Technology Inc. DS70000318G-page 393

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 394  2008-2014 Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 06 GS1 02 T - 50E / SP - XXX Examples: a) dsPIC33FJ06GS102-E/SP: Microchip Trademark SMPS dsPIC33, 6-Kbyte program memory, 28-pin, Extended Architecture temperature, SPDIP package. Flash Memory Family Program Memory Size (Kbyte) Product Group Pin Count Tape and Reel Flag (if applicable) Speed (if applicable) Temperature Range Package Pattern Architecture: 33 = 16-bit Digital Signal Controller Flash Memory Family: FJ = Flash program memory, 3.3V Product Group: GS1 = Switch Mode Power Supply (SMPS) family GS2 = Switch Mode Power Supply (SMPS) family GS4 = Switch Mode Power Supply (SMPS) family GS5 = Switch Mode Power Supply (SMPS) family Pin Count: 01 = 18-pin 02 = 28-pin 04 = 44-pin Speed 50 = 50 MIPS Temperature Range: I = -40C to+85C (Industrial) E = -40C to+125C (Extended) H = -40C to+150C (High) Package: PT = Plastic Thin Quad Flatpack - 10x10x1 mm body (TQFP) ML = Plastic Quad Flat, No Lead Package - 8x8 mm body (QFN) MM = Plastic Quad Flat, No Lead Package - 6x6x0.9 mm body (QFN-S) SO = Plastic Small Outline - Wide - 7.50 mm body (SOIC) SP = Skinny Plastic Dual In-Line - 300 mil body (SPDIP) TL = Very Thin Leadless Array - 6x6 mm body (VTLA)  2008-2014 Microchip Technology Inc. DS70000318G-page 395

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70000318G-page 396  2008-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2008-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-63276-216-0 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2008-2014 Microchip Technology Inc. DS70000318G-page 397

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: DSPIC33FJ06GS101-E/P DSPIC33FJ06GS202T-I/MM DSPIC33FJ06GS202-I/MM DSPIC33FJ06GS102-I/SP DSPIC33FJ06GS202-I/SO DSPIC33FJ06GS202T-I/SO DSPIC33FJ06GS102-E/SP DSPIC33FJ06GS101T-I/SO DSPIC33FJ06GS102T-I/SO DSPIC33FJ06GS102-E/SO DSPIC33FJ06GS102-I/SO DSPIC33FJ16GS404-I/PT DSPIC33FJ06GS101-I/P DSPIC33FJ06GS202-E/SO DSPIC33FJ06GS202-E/SP DSPIC33FJ06GS202-E/MM DSPIC33FJ06GS202-I/SP DSPIC33FJ06GS102T-I/MM DSPIC33FJ16GS402-I/SO DSPIC33FJ06GS102-E/MM DSPIC33FJ06GS101-E/SO DSPIC33FJ06GS102-I/MM DSPIC33FJ06GS101-I/SO DSPIC33FJ16GS504-E/ML DSPIC33FJ16GS504-I/PT DSPIC33FJ16GS502-E/MM DSPIC33FJ16GS504-E/PT DSPIC33FJ16GS402-E/SP DSPIC33FJ16GS402-I/SP DSPIC33FJ16GS402-I/MM DSPIC33FJ16GS404-I/ML DSPIC33FJ16GS404T-I/ML DSPIC33FJ16GS502-E/SP DSPIC33FJ16GS502T-I/SO DSPIC33FJ16GS402-E/SO DSPIC33FJ16GS502-E/SO DSPIC33FJ16GS402-E/MM DSPIC33FJ16GS504-I/ML DSPIC33FJ16GS402T-I/SO DSPIC33FJ16GS502-I/SP DSPIC33FJ16GS504T-I/ML DSPIC33FJ16GS502-I/MM DSPIC33FJ16GS404-E/ML DSPIC33FJ16GS404-E/PT DSPIC33FJ16GS402T-I/MM DSPIC33FJ16GS502T-I/MM DSPIC33FJ16GS502-I/SO DSPIC33FJ16GS404T-I/PT DSPIC33FJ16GS504T-I/PT DSPIC33FJ16GS404-E/TL DSPIC33FJ16GS404-I/TL DSPIC33FJ16GS504-E/TL DSPIC33FJ16GS504-I/TL DSPIC33FJ16GS402-50I/MM DSPIC33FJ16GS402-50I/SO DSPIC33FJ16GS402-50I/SP DSPIC33FJ16GS402-H/MM DSPIC33FJ16GS402-H/SO DSPIC33FJ16GS402-H/SP DSPIC33FJ16GS402T-50I/MM DSPIC33FJ16GS402T-50I/SO DSPIC33FJ16GS404-50I/ML DSPIC33FJ16GS404-50I/TL DSPIC33FJ16GS404-H/ML DSPIC33FJ16GS404-H/PT DSPIC33FJ16GS404-H/TL DSPIC33FJ16GS404T-50I/ML DSPIC33FJ16GS404T-50I/TL DSPIC33FJ16GS502-50I/MM DSPIC33FJ16GS502-50I/SO DSPIC33FJ16GS502-50I/SP DSPIC33FJ16GS502- H/MM DSPIC33FJ16GS502-H/SO DSPIC33FJ16GS502-H/SP DSPIC33FJ16GS502T-50I/MM DSPIC33FJ16GS502T-50I/SO DSPIC33FJ16GS504-50I/ML DSPIC33FJ16GS504-50I/TL DSPIC33FJ16GS504-H/ML DSPIC33FJ16GS504-H/PT DSPIC33FJ16GS504-H/TL DSPIC33FJ16GS504T-50I/ML DSPIC33FJ16GS504T-50I/TL DSPIC33FJ16GS504T-E/TL DSPIC33FJ16GS504T-I/TL DSPIC33FJ16GS404T-E/TL DSPIC33FJ16GS404T-I/TL DSPIC33FJ16GS404-50I/PT DSPIC33FJ16GS404T-50I/PT DSPIC33FJ16GS504-50I/PT DSPIC33FJ16GS504T- 50I/PT DSPIC33FJ16GS502T-E/MX DSPIC33FJ16GS502-E/MX