dsPIC30F6011A/6012A/6013A/6014A Data Sheet High-Performance, 16-bit Digital Signal Controllers © 2011 Microchip Technology Inc. DS70143E

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-883-2 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70143E-page 2 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A High-Performance, 16-bit Digital Signal Controllers Peripheral Features: Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not • High-current sink/source I/O pins: 25mA/25mA intended to be a complete reference • Five 16-bit timers/counters; optionally pair up source. For more information on the CPU, 16-bit timers into 32-bit timer modules peripherals, register descriptions and • 16-bit Capture input functions general device functionality, refer to the • 16-bit Compare/PWM output functions: “dsPIC30F Family Reference Manual” (DS70046). For more information on the • Data Converter Interface (DCI) supports common device instruction set and programming, audio Codec protocols, including I2S and AC’97 refer to the “16-bit MCU and DSC • 3-wire SPI modules (supports four Frame modes) Programmer’s Reference Manual” • I2C™ module supports Multi-Master/Slave mode (DS70157). and 7-bit/10-bit addressing • Two addressable UART modules with FIFO High-Performance Modified RISC CPU: buffers • Two CAN bus modules compliant with CAN 2.0B • Modified Harvard architecture standard • C compiler optimized instruction set architecture • Flexible addressing modes Analog Features: • 83 base instructions • 12-bit Analog-to-Digital Converter (ADC) with: • 24-bit wide instructions, 16-bit wide data path - 200 Ksps conversion rate • Up to 144 Kbytes on-chip Flash program space - Up to 16 input channels • Up to 48K instruction words - Conversion available during Sleep and Idle • Up to 8 Kbytes of on-chip data RAM • Programmable Low-Voltage Detection (PLVD) • Up to 4 Kbytes of nonvolatile data EEPROM • Programmable Brown-out Reset • 16 x 16-bit working register array • Up to 30 MIPS operation: Special Microcontroller Features: - DC to 40MHz external clock input - 4MHz-10MHz oscillator input with PLL • Enhanced Flash program memory: active (4x, 8x, 16x) - 10,000 erase/write cycle (min.) for • Up to 41 interrupt sources: industrial temperature range, 100K (typical) - Eight user-selectable priority levels • Data EEPROM memory: - Five external interrupt sources - 100,000 erase/write cycle (min.) for - Four processor traps industrial temperature range, 1M (typical) • Self-reprogrammable under software control DSP Features: • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Dual data fetch • Flexible Watchdog Timer (WDT) with on-chip • Modulo and Bit-Reversed modes low-power RC oscillator for reliable operation • Two 40-bit wide accumulators with optional • Fail-Safe Clock Monitor operation: saturation logic - Detects clock failure and switches to on-chip • 17-bit x 17-bit single-cycle hardware fractional/ low-power RC oscillator integer multiplier • Programmable code protection • All DSP instructions are single cycle: • In-Circuit Serial Programming™ (ICSP™) - Multiply-Accumulate (MAC) operation • Selectable Power Management modes: • Single-cycle ±16 shift - Sleep, Idle and Alternate Clock modes © 2011 Microchip Technology Inc. DS70143E-page 3

dsPIC30F6011A/6012A/6013A/6014A CMOS Technology: • Low-power, high-speed Flash technology • Wide operating voltage range (2.5V to 5.5V) • Industrial and Extended temperature ranges • Low power consumption dsPIC30F6011A/6012A/6013A/6014A Controller Families Device Pins BPyrtoegsraImns tMruecmtioornys SBRyAteMs EEBPyRteOsM T16im-beirt InCpaupt COoPmuWtppM/uStt d InCteordfaecce 101A02 DK-bCsitp s UART SPI 2™IC CAN dsPIC30F6011A 64 132K 44K 6144 2048 5 8 8 — 16 ch 2 2 1 2 dsPIC30F6012A 64 144K 48K 8192 4096 5 8 8 AC’97, I2S 16 ch 2 2 1 2 dsPIC30F6013A 80 132K 44K 6144 2048 5 8 8 — 16 ch 2 2 1 2 dsPIC30F6014A 80 144K 48K 8192 4096 5 8 8 AC’97, I2S 16 ch 2 2 1 2 DS70143E-page 4 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A Pin Diagrams 64-Pin TQFP 54 D7D64/RD3/RD RD1 RG13RG12RG14C2RX/RG0C2TX/RG1C1TX/RF1C1RX/RF0VDDVSSOC8/CN16/ROC7/CN15/ROC6/IC6/CN1OC5/IC5/CN1OC4/RD3OC3/RD2EMUD2/OC2/ 4321098765432109 6666655555555554 RG15 1 48 EMUC1/SOSCO/T1CK/CN0/RC14 T2CK/RC1 2 47 EMUD1/SOSCI/T4CK/CN1/RC13 T3CK/RC2 3 46 EMUC2/OC1/RD0 SCK2/CN8/RG6 4 45 IC4/INT4/RD11 SDI2/CN9/RG7 5 44 IC3/INT3/RD10 SDO2/CN10/RG8 6 43 IC2/INT2/RD9 MCLR 7 42 IC1/INT1/RD8 SS2/CN11/RG9 8 41 VSS dsPIC30F6011A VSS 9 40 OSC2/CLKO/RC15 VDD 10 39 OSC1/CLKI AN5/IC8/CN7/RB5 11 38 VDD AN4/IC7/CN6/RB4 12 37 SCL/RG2 AN3/CN5/RB3 13 36 SDA/RG3 AN2/SS1/LVDIN/CN4/RB2 14 35 EMUC3/SCK1/INT0/RF6 AN1/VREF-/CN3/RB1 15 34 U1RX/SDI1/RF2 AN0/VREF+/CN2/RB0 16 33 EMUD3/U1TX/SDO1/RF3 7890123456789012 1112222222222333 67 D S8901 S D234545 BB D SBB11 S D1111FF RRVVRRBBVVBBBBRR C/AN6/OCFA/D/EMUD/AN7/AAAN8/AN9/AN10/RAN11/R AN12/RAN13/RAN14/ROCFB/CN12/RU2RX/CN17/U2TX/CN18/ MUPG 15/ E N C/ A G P © 2011 Microchip Technology Inc. DS70143E-page 5

dsPIC30F6011A/6012A/6013A/6014A Pin Diagrams (Continued) 64-Pin TQFP 54 D7D64/RD3/RD RD1 CSDO/RG13CSDI/RG12CSCK/RG14C2RX/RG0C2TX/RG1C1TX/RF1C1RX/RF0VDDVSSOC8/CN16/ROC7/CN15/ROC6/IC6/CN1OC5/IC5/CN1OC4/RD3OC3/RD2EMUD2/OC2/ 4321098765432109 6666655555555554 COFS/RG15 1 48 EMUC1/SOSCO/T1CK/CN0/RC14 T2CK/RC1 2 47 EMUD1/SOSCI/T4CK/CN1/RC13 T3CK/RC2 3 46 EMUC2/OC1/RD0 SCK2/CN8/RG6 4 45 IC4/INT4/RD11 SDI2/CN9/RG7 5 44 IC3/INT3/RD10 SDO2/CN10/RG8 6 43 IC2/INT2/RD9 MCLR 7 42 IC1/INT1/RD8 SS2/CN11/RG9 8 41 VSS VSS 9 dsPIC30F6012A 40 OSC2/CLKO/RC15 VDD 10 39 OSC1/CLKI AN5/IC8/CN7/RB5 11 38 VDD AN4/IC7/CN6/RB4 12 37 SCL/RG2 AN3/CN5/RB3 13 36 SDA/RG3 AN2/SS1/LVDIN/CN4/RB2 14 35 EMUC3/SCK1/INT0/RF6 AN1/VREF-/CN3/RB1 15 34 U1RX/SDI1/RF2 AN0/VREF+/CN2/RB0 16 33 EMUD3/U1TX/SDO1/RF3 7890123456789012 1112222222222333 67 D S8901 S D234545 BB D SBB11 S D1111FF RRVVRRBBVVBBBBRR C/AN6/OCFA/D/EMUD/AN7/AAAN8/AN9/AN10/RAN11/R AN12/RAN13/RAN14/ROCFB/CN12/RU2RX/CN17/U2TX/CN18/ MUPG 15/ E N C/ A G P DS70143E-page 6 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A Pin Diagrams (Continued) 80-Pin TQFP 1 D7 D6 D5D4 13 RD R R RR D 2/ RG13 RG12 RG14CN23/RA7 CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/ OC7/CN15/ OC6/CN14/OC5/CN13/ IC6/CN19/R IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC 0 9 8 7 6 5 4 3 2 1 0 9 8 7 65 4 3 2 1 8 7 7 7 7 7 7 7 7 7 7 6 6 6 66 6 6 6 6 60 EMUC1/SOSCO/T1CK/CN0/RC14 RG15 1 59 EMUD1/SOSCI/CN1/RC13 T2CK/RC1 2 58 EMUC2/OC1/RD0 T3CK/RC2 3 57 IC4/RD11 T4CK/RC3 4 56 IC3/RD10 T5CK/RC4 5 55 IC2/RD9 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 54 IC1/RD8 SDO2/CN10/RG8 8 53 INT4/RA15 MCLR 9 52 INT3/RA14 SS2/CN11/RG9 10 51 VSS dsPIC30F6013A VSS 11 50 OSC2/CLKO/RC15 VDD 12 49 OSC1/CLKI INT1/RA12 13 48 VDD INT2/RA13 14 47 SCL/RG2 AN5/CN7/RB5 15 46 SDA/RG3 AN4/CN6/RB4 16 45 EMUC3/SCK1/INT0/RF6 AN3/CN5/RB3 17 44 SDI1/RF7 AN2/SS1/LVDIN/CN4/RB2 18 43 EMUD3/SDO1/RF8 PGC/EMUC/AN1/CN3/RB1 19 42 U1RX/RF2 PGD/EMUD/AN0/CN2/RB0 20 41 U1TX/RF3 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 6 7 9 0 D S 8 9 0 1 S D 2 3 4 54 5 4 5 B B A 1 D S B B 1 1 S D 1 1 1 11 1 F F R R R A V V R R B B V V B B B BD D R R N6/OCFA/ AN7/ V-/REF V+/RREF A A AN8/ AN9/ AN10/R AN11/R AN12/R AN13/R AN14/R B/CN12/R7/CN20/R 8/CN21/R RX/CN17/ TX/CN18/ A CFIC IC U2 U2 O 5/ 1 N A © 2011 Microchip Technology Inc. DS70143E-page 7

dsPIC30F6011A/6012A/6013A/6014A Pin Diagrams (Continued) 80-Pin TQFP 1 D7 D6 D5D4 13 RD CSDO/RG13 CSDI/RG12 CSCK/RG14CN23/RA7 CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/CN16/R OC7/CN15/R OC6/CN14/ROC5/CN13/R IC6/CN19/RD IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/ 0 9 8 7 6 5 4 3 2 1 0 9 8 7 65 4 3 2 1 8 7 7 7 7 7 7 7 7 7 7 6 6 6 66 6 6 6 6 60 EMUC1/SOSCO/T1CK/CN0/RC14 COFS/RG15 1 59 EMUD1/SOSCI/CN1/RC13 T2CK/RC1 2 58 EMUC2/OC1/RD0 T3CK/RC2 3 57 IC4/RD11 T4CK/RC3 4 56 IC3/RD10 T5CK/RC4 5 55 IC2/RD9 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 54 IC1/RD8 SDO2/CN10/RG8 8 53 INT4/RA15 MCLR 9 52 INT3/RA14 SS2/CN11/RG9 10 dsPIC30F6014A 51 VSS VSS 11 50 OSC2/CLKO/RC15 VDD 12 49 OSC1/CLKI INT1/RA12 13 48 VDD INT2/RA13 14 47 SCL/RG2 AN5/CN7/RB5 15 46 SDA/RG3 AN4/CN6/RB4 16 45 EMUC3/SCK1/INT0/RF6 AN3/CN5/RB3 17 44 SDI1/RF7 AN2/SS1/LVDIN/CN4/RB2 18 43 EMUD3/SDO1/RF8 PGC/EMUC/AN1/CN3/RB1 19 42 U1RX/RF2 PGD/EMUD/AN0/CN2/RB0 20 41 U1TX/RF3 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 6 7 9 0 D S 8 9 0 1 S D 2 3 4 5 4 5 4 5 B B A 1 D S B B 1 1 S D 1 1 1 1 1 1 F F R R R A V V R R B B V V B B B B D D R R N6/OCFA/ AN7/ V-/REF V+/RREF A A AN8/ AN9/ AN10/R AN11/R AN12/R AN13/R AN14/R B/CN12/R 7/CN20/R 8/CN21/R RX/CN17/ TX/CN18/ A CF IC IC U2 U2 O 5/ 1 N A DS70143E-page 8 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A Table of Contents 1.0 Device Overview........................................................................................................................................................................11 2.0 CPU Architecture Overview........................................................................................................................................................17 3.0 Memory Organization.................................................................................................................................................................25 4.0 Address Generator Units............................................................................................................................................................39 5.0 Interrupts....................................................................................................................................................................................45 6.0 Flash Program Memory..............................................................................................................................................................51 7.0 Data EEPROM Memory.............................................................................................................................................................57 8.0 I/O Ports.....................................................................................................................................................................................61 9.0 Timer1 Module...........................................................................................................................................................................67 10.0 Timer2/3 Module........................................................................................................................................................................71 11.0 Timer4/5 Module .......................................................................................................................................................................77 12.0 Input Capture Module.................................................................................................................................................................81 13.0 Output Compare Module............................................................................................................................................................85 14.0 SPI™ Module.............................................................................................................................................................................91 15.0 I2C™ Module.............................................................................................................................................................................95 16.0 Universal Asynchronous Receiver Transmitter (UART) Module..............................................................................................103 17.0 CAN Module.............................................................................................................................................................................111 18.0 Data Converter Interface (DCI) Module....................................................................................................................................123 19.0 12-bit Analog-to-Digital Converter (ADC) Module....................................................................................................................133 20.0 System Integration...................................................................................................................................................................143 21.0 Instruction Set Summary..........................................................................................................................................................161 22.0 Development Support...............................................................................................................................................................169 23.0 Electrical Characteristics..........................................................................................................................................................173 24.0 Packaging Information..............................................................................................................................................................213 Appendix A: Revision History.............................................................................................................................................................223 Index..................................................................................................................................................................................................225 The Microchip Web Site.....................................................................................................................................................................231 Customer Change Notification Service..............................................................................................................................................231 Customer Support..............................................................................................................................................................................231 Reader Response..............................................................................................................................................................................232 Product Identification System............................................................................................................................................................233 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2011 Microchip Technology Inc. DS70143E-page 9

dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 10 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 1.0 DEVICE OVERVIEW Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157). This document contains specific information for the dsPIC30F6011A/6012A/6013A/6014A Digital Signal Controller (DSC) devices. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) func- tionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure1-1 and Figure1-2 show device block diagrams for dsPIC30F6011A/6012A and dsPIC30F6013A/6014A, respectively. © 2011 Microchip Technology Inc. DS70143E-page 11

dsPIC30F6011A/6012A/6013A/6014A FIGURE 1-1: dsPIC30F6011A/6012A BLOCK DIAGRAM Y Data Bus X Data Bus 16 16 16 16 Interrupt Data Latch Data Latch Controller DPaStVa &A cTcaebslse Y Data X Data 24Control Block 8 16 RAM RAM 16 Address Address 24 Latch Latch AN0/VREF+/CN2/RB0 AN1/VREF-/CN3/RB1 16 16 16 AN2/SS1/LVDIN/CN4/RB2 24 Y AGU X RAGU AN3/CN5/RB3 PCU PCH PCL X WAGU AN4/IC7/CN6/RB4 Program Counter AN5/IC8/CN7/RB5 Address Latch Stack Loop PGC/EMUC/AN6/OCFA/RB6 Control Control Program Memory Logic Logic PGD/EMUD/AN7/RB7 (Up to 144 Kbytes) AN8/RB8 AN9/RB9 Data EEPROM AN10/RB10 (Up to 4 Kbytes) Effective Address AN11/RB11 Data Latch 16 AN12/RB12 AN13/RB13 AN14/RB14 ROM Latch 16 AN15/OCFB/CN12/RB15 24 PORTB IR T2CK/RC1 T3CK/RC2 16 16 EMUD1/SOSCI/T4CK/CN1/RC13 EMUC1/SOSCO/T1CK/CN0/RC14 16 x 16 OSC2/CLKO/RC15 W Reg Array Decode PORTC Instruction Decode & 16 16 Control EMUC2/OC1/RD0 Control Signals DSP Divide EMUD2/OC2/RD1 to Various Blocks Power-up Engine Unit OC3/RD2 Timer OC4/RD3 OC5/IC5/CN13/RD4 OSC1/CLKI GeTnimeriantgion StOarst-cuipll aTtimorer OC6/IC6/CN14/RD5 OC7/CN15/RD6 ALU<16> OC8/CN16/RD7 POR/BOR IC1/INT1/RD8 MCLR Watchdog 16 16 IICC32//IINNTT32//RRDD190 Timer IC4/INT4/RD11 Low-Voltage PORTD VDD, VSS Detect AVDD, AVSS CAN1, Input O utput CAN2 12-bit ADC Capture Com pare I2C™ C1RX/RF0 Module Module C1TX/RF1 U1RX/SDI1/RF2 EMUD3/U1TX/SDO1/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 SPI1, UART1, EMUC3/SCK1/INT0/RF6 Timers DCI SPI2 UART2 PORTF C2RX/RG0 C2TX/RG1 SCL/RG2 SDA/RG3 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SS2/CN11/RG9 CSDI(1)/RG12 CSDO(1)/RG13 Note 1: CSDI, CSDO, CSCK, and COFS are codec functions on dsPIC30F6012A only. CSCK(1)/RG14 COFS(1)/RG15 PORTG DS70143E-page 12 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 1-2: dsPIC30F6013A/6014A BLOCK DIAGRAM CN22/RA6 Y Data Bus CN23/RA7 X Data Bus VREF-/RA9 16 16 16 VREF+/RA10 16 INT1/RA12 Interrupt Data Latch Data Latch INT2/RA13 Controller DPaStVa &A cTcaebslse Y Data X Data INT3/RA14 24Control Block 8 16 RAM RAM INT4/RA15 16 PORTA Address Address 24 Latch Latch PGD/EMUD/AN0/CN2/RB0 16 16 16 PGC/EMUC/AN1/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 24 X RAGU Y AGU AN3/CN5/RB3 PCU PCH PCL X WAGU AN4/CN6/RB4 Program Counter AN5/CN7/RB5 Address Latch CSotanctrkol CLoonotprol AN6/OCFA/RB6 Program Memory Logic Logic AN7/RB7 (Up to 144 Kbytes) AN8/RB8 AN9/RB9 Data EEPROM AN10/RB10 (Up to 4 Kbytes) Effective Address AN11/RB11 Data Latch 16 AN12/RB12 AN13/RB13 AN14/RB14 ROM Latch 16 AN15/OCFB/CN12/RB15 24 PORTB T2CK/RC1 IR T3CK/RC2 16 T4CK/RC3 16 T5CK/RC4 16 x 16 EMUD1/SOSCI/CN1/RC13 W Reg Array EMUC1/SOSCO/T1CK/CN0/RC14 Decode OSC2/CLKO/RC15 Instruction PORTC Decode & 16 16 Control EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 Control Signals DSP Divide OC4/RD3 to Various Blocks Power-up Engine Unit OC5/CN13/RD4 Timer OC6/CN14/RD5 OSC1/CLKI GeTnimeriantgion StOarst-cuipll aTtimorer OOCC78//CCNN1156//RRDD67 IC1/RD8 ALU<16> IC2/RD9 POR/BOR IC3/RD10 MCLR WaTticmhedrog 16 16 IICC45//RRDD1112 IC6/CN19/RD13 Low-Voltage IC7/CN20/RD14 VDD, VSS Detect IC8/CN21/RD15 AVDD, AVSS PORTD CAN1, Input O utput C1RX/RF0 CAN2 12-bit ADC Capture Com pare I2C™ C1TX/RF1 Module Module U1RX/RF2 U1TX/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 SDI1/RF7 SPI1, UART1, Timers DCI SPI2 UART2 EMUD3/SDO1/RF8 PORTF C2RX/RG0 C2TX/RG1 SCL/RG2 SDA/RG3 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SS2/CN11/RG9 CSDI(1)/RG12 CSDO(1)/RG13 CSCK(1)/RG14 Note 1: CSDI, CSDO, CSCK, and COFS are codec functions on dsPIC30F6014A only COFS(1)/RG15 PORTG © 2011 Microchip Technology Inc. DS70143E-page 13

dsPIC30F6011A/6012A/6013A/6014A Table1-1 provides a brief description of device I/O pin- outs and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name Description Type Type AN0-AN15 I Analog Analog input channels. AN0 and AN1 are also used for device programming data and clock inputs, respectively. AVDD P P Positive supply for analog module. This pin must be connected at all times. AVSS P P Ground reference for analog module. This pin must be connected at all times. CLKI I ST/CMOS External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator CLKO O — mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. CN0-CN23 I ST Input change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. COFS I/O ST Data Converter Interface frame synchronization pin. CSCK I/O ST Data Converter Interface serial clock input/output pin. CSDI I ST Data Converter Interface serial data input pin. CSDO O — Data Converter Interface serial data output pin. C1RX I ST CAN1 bus receive pin. C1TX O — CAN1 bus transmit pin. C2RX I ST CAN2 bus receive pin. C2TX O — CAN2 bus transmit pin EMUD I/O ST ICD Primary Communication Channel data input/output pin. EMUC I/O ST ICD Primary Communication Channel clock input/output pin. EMUD1 I/O ST ICD Secondary Communication Channel data input/output pin. EMUC1 I/O ST ICD Secondary Communication Channel clock input/output pin. EMUD2 I/O ST ICD Tertiary Communication Channel data input/output pin. EMUC2 I/O ST ICD Tertiary Communication Channel clock input/output pin. EMUD3 I/O ST ICD Quaternary Communication Channel data input/output pin. EMUC3 I/O ST ICD Quaternary Communication Channel clock input/output pin. IC1-IC8 I ST Capture inputs 1 through 8. INT0 I ST External interrupt 0. INT1 I ST External interrupt 1. INT2 I ST External interrupt 2. INT3 I ST External interrupt 3. INT4 I ST External interrupt 4. LVDIN I Analog Low-Voltage Detect Reference Voltage input pin. MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active-low Reset to the device. OCFA I ST Compare Fault A input (for Compare channels 1, 2, 3 and 4). OCFB I ST Compare Fault B input (for Compare channels 5, 6, 7 and 8). OC1-OC8 O — Compare outputs 1 through 8. OSC1 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. OSC2 I/O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Legend: CMOS= CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power DS70143E-page 14 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Description Type Type PGD I/O ST In-Circuit Serial Programming™ data input/output pin. PGC I ST In-Circuit Serial Programming clock input pin. RA6-RA7 I/O ST PORTA is a bidirectional I/O port. RA9-RA10 I/O ST RA12-RA15 I/O ST RB0-RB15 I/O ST PORTB is a bidirectional I/O port. RC1-RC4 I/O ST PORTC is a bidirectional I/O port. RC13-RC15 I/O ST RD0-RD15 I/O ST PORTD is a bidirectional I/O port. RF0-RF8 I/O ST PORTF is a bidirectional I/O port. RG0-RG3 I/O ST PORTG is a bidirectional I/O port. RG6-RG9 I/O ST RG12-RG15 I/O ST SCK1 I/O ST Synchronous serial clock input/output for SPI1. SDI1 I ST SPI1 Data In. SDO1 O — SPI1 Data Out. SS1 I ST SPI1 Slave Synchronization. SCK2 I/O ST Synchronous serial clock input/output for SPI2. SDI2 I ST SPI2 Data In. SDO2 O — SPI2 Data Out. SS2 I ST SPI2 Slave Synchronization. SCL I/O ST Synchronous serial clock input/output for I2C™. SDA I/O ST Synchronous serial data input/output for I2C. SOSCO O — 32 kHz low-power oscillator crystal output. SOSCI I ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. T1CK I ST Timer1 external clock input. T2CK I ST Timer2 external clock input. T3CK I ST Timer3 external clock input. T4CK I ST Timer4 external clock input. T5CK I ST Timer5 external clock input. U1RX I ST UART1 Receive. U1TX O — UART1 Transmit. U1ARX I ST UART1 Alternate Receive. U1ATX O — UART1 Alternate Transmit. U2RX I ST UART2 Receive. U2TX O — UART2 Transmit. VDD P — Positive supply for logic and I/O pins. VSS P — Ground reference for logic and I/O pins. VREF+ I Analog Analog Voltage Reference (High) input. VREF- I Analog Analog Voltage Reference (Low) input. Legend: CMOS= CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power © 2011 Microchip Technology Inc. DS70143E-page 15

dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 16 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 2.0 CPU ARCHITECTURE There are two methods of accessing data stored in OVERVIEW program memory: • The upper 32 Kbytes of data space memory can Note: This data sheet summarizes features of be mapped into the lower half (user space) of pro- this group ofdsPIC30F devices and is not gram space at any 16K program word boundary, intended to be a complete reference defined by the 8-bit Program Space Visibility Page source. For more information on the CPU, (PSVPAG) register. This lets any instruction peripherals, register descriptions and access program space as if it were data space, general device functionality, refer to the with a limitation that the access requires an addi- “dsPIC30F Family Reference Manual” tional cycle. Moreover, only the lower 16 bits of (DS70046). For more information on the each instruction word can be accessed using this device instruction set and programming, method. refer to the “16-bit MCU and DSC • Linear indirect access of 32K word pages within Programmer’s Reference Manual” program space is also possible using any working (DS70157). register, via table read and write instructions. Table read and write instructions can be used to 2.1 Core Overview access all 24 bits of an instruction word. Overhead-free circular buffers (Modulo Addressing) This section contains a brief overview of the CPU are supported in both X and Y address spaces. This is architecture of the dsPIC30F. For additional hard- primarily intended to remove the loop overhead for wareand programming information, please refer to DSP algorithms. the“dsPIC30F Family Reference Manual” (DS70046) and the“16-bit MCU and DSC Programmer’s The X AGU also supports Bit-Reversed Addressing on Reference Manual” (DS70157), respectively. destination effective addresses to greatly simplify input or output data reordering for radix-2 FFT algorithms. The core has a 24-bit instruction word. The Program Refer to Section4.0 “Address Generator Units” for Counter (PC) is 23-bits wide with the Least Significant details on modulo and Bit-Reversed Addressing. bit (LSb) always clear (refer to Section3.1 “Program Address Space”), and the Most Significant bit (MSb) The core supports Inherent (no operand), Relative, is ignored during normal program execution, except for Literal, Memory Direct, Register Direct, Register certain specialized instructions. Thus, the PC can Indirect, Register Offset and Literal Offset Addressing address up to 4M instruction words of user program modes. Instructions are associated with predefined space. An instruction prefetch mechanism is used to addressing modes, depending upon their functional help maintain throughput. Program loop constructs, requirements. free from loop count management overhead, are sup- For most instructions, the core is capable of executing ported using the DO and REPEAT instructions, both of a data (or program data) memory read, a working reg- which are interruptible at any point. ister (data) read, a data memory write and a program The working register array consists of 16 x 16-bit regis- (instruction) memory read per instruction cycle. As a ters, each of which can act as data, address or offset result, 3-operand instructions are supported, allowing registers. One working register (W15) operates as a C=A + B operations to be executed in a single cycle. software Stack Pointer for interrupts and calls. A DSP engine has been included to significantly The data space is 64 Kbytes (32K words) and is split enhance the core arithmetic capability and throughput. into two blocks, referred to as X and Y data memory. It features a high-speed 17-bit by 17-bit multiplier, a Each block has its own independent Address Genera- 40-bit ALU, two 40-bit saturating accumulators and a tion Unit (AGU). Most instructions operate solely 40-bit bidirectional barrel shifter. Data in the accumula- through the X memory, AGU, which provides the tor or any working register can be shifted up to 16 bits appearance of a single unified data space. The right, or 16 bits left in a single cycle. The DSP instruc- Multiply-Accumulate (MAC) class of dual source DSP tions operate seamlessly with all other instructions and instructions operate through both the X and Y AGUs, have been designed for optimal real-time performance. splitting the data address space into two parts (see The MAC class of instructions can concurrently fetch Section3.2 “Data Address Space”). The X and Y two data operands from memory while multiplying two data space boundary is device specific and cannot be W registers. To enable this concurrent fetching of data altered by the user. Each data word consists of 2 bytes, operands, the data space has been split for these and most instructions can address data either as words instructions and linear for all others. This has been or bytes. achieved in a transparent and flexible manner, by ded- icating certain working registers to each address space for the MAC class of instructions. © 2011 Microchip Technology Inc. DS70143E-page 17

dsPIC30F6011A/6012A/6013A/6014A The core does not support a multi-stage instruction 2.2.1 SOFTWARE STACK POINTER/ pipeline. However, a single stage instruction prefetch FRAME POINTER mechanism is used, which accesses and partially The dsPIC® DSC devices contain a software stack. decodes instructions a cycle ahead of execution, in W15 is the dedicated software Stack Pointer (SP), and order to maximize available execution time. Most will be automatically modified by exception processing instructions execute in a single cycle with certain and subroutine calls and returns. However, W15 can be exceptions. referenced by any instruction in the same manner as all The core features a vectored exception processing other W registers. This simplifies the reading, writing structure for traps and interrupts, with 62 independent and manipulation of the Stack Pointer (e.g., vectors. The exceptions consist of up to 8 traps (of creating stack frames). which 4 are reserved) and 54 interrupts. Each interrupt Note: In order to protect against misaligned is prioritized based on a user-assigned priority between stack accesses, W15<0> is always clear. 1 and 7 (1 being the lowest priority and 7 being the highest), in conjunction with a predetermined ‘natural W15 is initialized to 0x0800 during a Reset. The user order’. Traps have fixed priorities ranging from 8 to 15. may reprogram the SP during initialization to any location within data space. 2.2 Programmer’s Model W14 has been dedicated as a Stack Frame Pointer as The programmer’s model is shown in Figure2-1 and defined by the LNK and ULNK instructions. However, consists of 16 x 16-bit working registers (W0 through W14 can be referenced by any instruction in the same W15), 2 x 40-bit accumulators (ACCA and ACCB), manner as all other W registers. STATUS register (SR), Data Table Page register 2.2.2 STATUS REGISTER (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, The dsPIC DSC core has a 16-bit STATUS register DOEND, DCOUNT and RCOUNT) and Program Coun- (SR), the LSB of which is referred to as the SR Low ter (PC). The working registers can act as data, byte (SRL) and the Most Significant Byte (MSB) as the address or offset registers. All registers are memory SR High byte (SRH). See Figure2-1 for SR layout. mapped. W0 acts as the W register for file register SRL contains all the MCU ALU operation status flags addressing. (including the Z bit), as well as the CPU Interrupt Prior- Some of these registers have a shadow register asso- ity Level status bits, IPL<2:0> and the Repeat Active ciated with each of them, as shown in Figure2-1. The status bit, RA. During exception processing, SRL is shadow register is used as a temporary holding register concatenated with the MSB of the PC to form a com- and can transfer its contents to or from its host register plete word value which is then stacked. upon the occurrence of an event. None of the shadow The upper byte of the STATUS register contains the registers are accessible directly. The following rules DSP Adder/Subtracter status bits, the DO Loop Active apply for transfer of registers into and out of shadows. bit (DA) and the Digit Carry (DC) status bit. • PUSH.S and POP.S W0, W1, W2, W3, SR (DC, N, OV, Z and C bits 2.2.3 PROGRAM COUNTER only) are transferred. The Program Counter is 23-bits wide; bit 0 is always • DO instruction clear. Therefore, the PC can address up to 4M DOSTART, DOEND, DCOUNT shadows are instruction words. pushed on loop start, and popped on loop end. When a byte operation is performed on a working reg- ister, only the Least Significant Byte (LSB) of the target register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes can be manipulated through byte wide data memory space accesses. DS70143E-page 18 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 2-1: PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 DSP Operand W5 Registers W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register AD39 AD31 AD15 AD0 DSP ACCA Accumulators ACCB PC22 PC0 0 Program Counter 7 0 TTBALBPPAAGG Data Table Page Address 7 0 PPSSVVPPAAGG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address 22 DOEND DO Loop End Address 15 0 CORCON Core Configuration Register OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRH SRL © 2011 Microchip Technology Inc. DS70143E-page 19

dsPIC30F6011A/6012A/6013A/6014A 2.3 Divide Support However, some MCU ALU and DSP engine resources may be used concurrently by the same instruction The dsPIC DSC devices feature a 16/16-bit signed (e.g., ED, EDAC). fractional divide operation, as well as 32/16-bit and 16/ The DSP engine also has the capability to perform 16-bit signed and unsigned integer divide operations, in inherent accumulator-to-accumulator operations, the form of single instruction iterative divides. The which require no additional data. These instructions are following instructions and data sizes are supported: ADD, SUB and NEG. • DIVF - 16/16 signed fractional divide The DSP engine has various options selected through • DIV.sd - 32/16 signed divide various bits in the CPU Core Configuration register • DIV.ud - 32/16 unsigned divide (CORCON), as listed below: • DIV.sw - 16/16 signed divide 1. Fractional or integer DSP multiply (IF). • DIV.uw - 16/16 unsigned divide 2. Signed or unsigned DSP multiply (US). The 16/16 divides are similar to the 32/16 (same number 3. Conventional or convergent rounding (RND). of iterations), but the dividend is either zero-extended or 4. Automatic saturation on/off for ACCA (SATA). sign-extended during the first iteration. 5. Automatic saturation on/off for ACCB (SATB). The divide instructions must be executed within a 6. Automatic saturation on/off for writes to data REPEAT loop. Any other form of execution (e.g., a memory (SATDW). series of discrete divide instructions) will not function 7. Accumulator Saturation mode selection correctly because the instruction flow depends on (ACCSAT). RCOUNT. The divide instruction does not automatically set up the RCOUNT value and it must, therefore, be Note: For CORCON layout, see Table3-3. explicitly and correctly specified in the REPEAT instruc- A block diagram of the DSP engine is shown in tion as shown in Table2-2 (REPEAT will execute the tar- Figure2-2. get instruction {operand value + 1} times). The TABLE 2-1: DSP INSTRUCTIONS REPEAT loop count must be setup for 18 iterations of the DIV/DIVF instruction. Thus, a complete divide SUMMARY operation requires 19 cycles. Algebraic ACC Write Instruction Note: The divide flow is interruptible. However, Operation Back the user needs to save the context as CLR A = 0 Yes appropriate. ED A = (x – y)2 No EDAC A = A + (x – y)2 No 2.4 DSP Engine MAC A = A + (x * y) Yes The DSP engine consists of a high-speed 17-bit x MAC A = A + x2 No 17-bit multiplier, a barrel shifter and a 40-bit adder/ MOVSAC No change in A Yes subtracter (with two target accumulators, round and saturation logic). MPY A = x * y No The dsPIC30F is a single-cycle instruction flow archi- MPY A = x2 No tecture; therefore, concurrent operation of the DSP MPY.N A = – x * y No engine with MCU instruction flow is not possible. MSC A = A – x * y Yes TABLE 2-2: DIVIDE INSTRUCTIONS Instruction Function DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1 DIV.sd Signed divide: (Wm + 1:Wm)/Wn → W0; Rem → W1 DIV.ud Unsigned divide: (Wm + 1:Wm)/Wn → W0; Rem → W1 DIV.sw Signed divide: Wm/Wn → W0; Rem → W1 DIV.uw Unsigned divide: Wm/Wn → W0; Rem → W1 DS70143E-page 20 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM S a 40 40-bit Accumulator A 40 Round t 16 40-bit Accumulator B u Logic r a Carry/Borrow Out t Saturate e Adder Carry/Borrow In Negate 40 40 40 Barrel 16 Shifter 40 s u B a at D Sign-Extend X s u B a 32 16 at Zero Backfill D Y 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array © 2011 Microchip Technology Inc. DS70143E-page 21

dsPIC30F6011A/6012A/6013A/6014A 2.4.1 MULTIPLIER 2.4.2.1 Adder/Subtracter, Overflow and Saturation The 17 x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a The adder/subtracter is a 40-bit adder with an optional scaler to support either 1.31 fractional (Q31) or 32-bit zero input into one side and either true, or complement integer results. Unsigned operands are zero-extended data into the other input. In the case of addition, the into the 17th bit of the multiplier input value. Signed carry/borrow input is active high and the other input is operands are sign-extended into the 17th bit of the mul- true data (not complemented), whereas in the case of tiplier input value. The output of the 17 x 17-bit multi- subtraction, the carry/borrow input is active low and the plier/scaler is a 33-bit value which is sign-extended to other input is complemented. The adder/subtracter 40 bits. Integer data is inherently represented as a generates overflow status bits SA/SB and OA/OB, signed two’s complement value, where the MSB is which are latched and reflected in the STATUS defined as a sign bit. Generally speaking, the range of register: an N-bit two’s complement integer is -2N-1 to 2N-1 – 1. • Overflow from bit 39: this is a catastrophic For a 16-bit integer, the data range is -32768 (0x8000) overflow in which the sign of the accumulator is to 32767 (0x7FFF) including ‘0’. For a 32-bit integer, destroyed. the data range is -2,147,483,648 (0x80000000) to • Overflow into guard bits 32 through 39: this is a 2,147,483,647 (0x7FFF FFFF). recoverable overflow. This bit is set whenever all When the multiplier is configured for fractional multipli- the guard bits are not identical to each other. cation, the data is represented as a two’s complement The adder has an additional saturation block which fraction, where the MSB is defined as a sign bit and the controls accumulator data saturation, if selected. It radix point is implied to lie just after the sign bit (QX for- uses the result of the adder, the overflow status bits mat). The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to (1 – 21-N). For a described above, and the SATA/B (CORCON<7:6>) and ACCSAT (CORCON<4>) mode control bits to 16-bit fraction, the Q15 data range is -1.0 (0x8000) to determine when and to what value to saturate. 0.999969482 (0x7FFF) including ‘0’ and has a preci- sion of 3.01518x10-5. In Fractional mode, the 16x16 Six STATUS register bits have been provided to multiply operation generates a 1.31 product which has support saturation and overflow; they are: a precision of 4.65661 x 10-10. 1. OA: ACCA overflowed into guard bits The same multiplier is used to support the MCU multi- 2. OB: ACCB overflowed into guard bits ply instructions which include integer 16-bit signed, 3. SA: ACCA saturated (bit 31 overflow and satu- unsigned and mixed sign multiplies. ration) The MUL instruction may be directed to use byte or or word sized operands. Byte operands will direct a 16-bit ACCA overflowed into guard bits and saturated result, and word operands will direct a 32-bit result to (bit 39 overflow and saturation) the specified register(s) in the W array. 4. SB: ACCB saturated (bit 31 overflow and satu- ration) 2.4.2 DATA ACCUMULATORS AND or ADDER/SUBTRACTER ACCB overflowed into guard bits and saturated The data accumulator consists of a 40-bit adder/ (bit 39 overflow and saturation) subtracter with automatic sign extension logic. It can 5. OAB: Logical OR of OA and OB select one of two accumulators (A or B) as its pre- 6. SAB: Logical OR of SA and SB accumulation source and post-accumulation destina- The OA and OB bits are modified each time data tion. For the ADD and LAC instructions, the data to be passes through the adder/subtracter. When set, they accumulated or loaded can be optionally scaled via the indicate that the most recent operation has overflowed barrel shifter, prior to accumulation. into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the correspond- ing overflow trap flag enable bit (OVATE, OVBTE) in the INTCON1 register (refer to Section5.0 “Inter- rupts”) is set. This allows the user to take immediate action, for example, to correct system gain. DS70143E-page 22 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A The SA and SB bits are modified each time data 2.4.2.2 Accumulator ‘Write Back’ passes through the adder/subtracter but can only be The MAC class of instructions (with the exception of cleared by the user. When set, they indicate that the MPY, MPY.N, ED and EDAC) can optionally write a accumulator has overflowed its maximum range (bit 31 rounded version of the high word (bits 31 through 16) for 32-bit saturation, or bit 39 for 40-bit saturation) and of the accumulator that is not targeted by the instruction will be saturated (if saturation is enabled). When satu- into data space memory. The write is performed across ration is not enabled, SA and SB default to bit 39 over- the X bus into combined X and Y address space. The flow and thus indicate that a catastrophic overflow has following addressing modes are supported: occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning 1. W13, Register Direct: trap when saturation is disabled. The rounded contents of the non-target accumulator are written into W13 as a 1.15 The overflow and saturation status bits can optionally fraction. be viewed in the STATUS register (SR) as the logical 2. [W13] + = 2, Register Indirect with Post-Increment: OR of OA and OB (in bit OAB) and the logical OR of SA The rounded contents of the non-target accumu- and SB (in bit SAB). This allows programmers to check lator are written into the address pointed to by one bit in the STATUS register to determine if either W13 as a 1.15 fraction. W13 is then accumulator has overflowed, or one bit to determine if incremented by 2 (for a word write). either accumulator has saturated. This would be useful for complex number arithmetic which typically uses 2.4.2.3 Round Logic both the accumulators. The round logic is a combinational block which per- The device supports three saturation and overflow forms a conventional (biased) or convergent (unbi- modes: ased) round function during an accumulator write 1. Bit 39 Overflow and Saturation: (store). The Round mode is determined by the state of When bit 39 overflow and saturation occurs, the the RND bit in the CORCON register. It generates a 16- saturation logic loads the maximally positive 9.31 bit, 1.15 data value which is passed to the data space (0x7FFFFFFFFF), or maximally negative 9.31 write saturation logic. If rounding is not indicated by the value (0x8000000000) into the target accumula- instruction, a truncated 1.15 data value is stored and tor. The SA or SB bit is set and remains set until the least significant word (lsw) is simply discarded. cleared by the user. This is referred to as ‘super Conventional rounding takes bit 15 of the accumulator, saturation’ and provides protection against erro- zero-extends it and adds it to the ACCxH word (bits 16 neous data, or unexpected algorithm problems through 31 of the accumulator). If the ACCxL word (e.g., gain calculations). (bits0 through 15 of the accumulator) is between 2. Bit 31 Overflow and Saturation: 0x8000 and 0xFFFF (0x8000 included), ACCxH is When bit 31 overflow and saturation occurs, the incremented. If ACCxL is between 0x0000 and 0x7FFF, saturation logic then loads the maximally posi- ACCxH is left unchanged. A consequence of this tive 1.31 value (0x007FFFFFFF), or maximally algorithm is that over a succession of random rounding negative 1.31 value (0x0080000000) into the operations, the value will tend to be biased slightly target accumulator. The SA or SB bit is set and positive. remains set until cleared by the user. When this Convergent (or unbiased) rounding operates in the Saturation mode is in effect, the guard bits are same manner as conventional rounding, except when not used (so the OA, OB or OAB bits are never ACCxL equals 0x8000. If this is the case, the LSb set). (bit16 of the accumulator) of ACCxH is examined. If it 3. Bit 39 Catastrophic Overflow: is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not The bit 39 overflow status bit from the adder is modified. Assuming that bit 16 is effectively random in used to set the SA or SB bit which remain set nature, this scheme will remove any rounding bias that until cleared by the user. No saturation operation may accumulate. is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in The SAC and SAC.R instructions store either a trun- the INTCON1 register is set, a catastrophic cated (SAC) or rounded (SAC.R) version of the contents overflow can initiate a trap exception. of the target accumulator to data memory via the X bus (subject to data saturation, see Section2.4.2.4 “Data Space Write Saturation”). Note that for the MAC class of instructions, the accumulator write back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. © 2011 Microchip Technology Inc. DS70143E-page 23

dsPIC30F6011A/6012A/6013A/6014A 2.4.2.4 Data Space Write Saturation 2.4.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data The barrel shifter is capable of performing up to 16-bit space may also be saturated but without affecting the arithmetic or logic right shifts, or up to 16-bit left shifts contents of the source accumulator. The data space in a single cycle. The source can be either of the two write saturation logic block accepts a 16-bit, 1.15 frac- DSP accumulators, or the X bus (to support multi-bit tional value from the round logic block as its input, shifts of register or memory data). together with overflow status from the original source The shifter requires a signed binary value to determine (accumulator) and the 16-bit round adder. These are both the magnitude (number of bits) and direction of the combined and used to select the appropriate 1.15 shift operation. A positive value will shift the operand fractional value as output to write to data space right. A negative value will shift the operand left. A memory. value of ‘0’ will not modify the operand. If the SATDW bit in the CORCON register is set, data The barrel shifter is 40 bits wide, thereby obtaining a (after rounding or truncation) is tested for overflow and 40-bit result for DSP shift operations and a 16-bit result adjusted accordingly, For input data greater than for MCU shift operations. Data from the X bus is pre- 0x007FFF, data written to memory is forced to the max- sented to the barrel shifter between bit positions 16 to imum positive 1.15 value, 0x7FFF. For input data less 31 for right shifts, and bit positions 0 to 16 for left shifts. than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The MSb of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. DS70143E-page 24 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 3.0 MEMORY ORGANIZATION User program space access is restricted to the lower 4M instruction word address range (0x000000 to Note: This data sheet summarizes features of 0x7FFFFE) for all accesses other than TBLRD/TBLWT, this group ofdsPIC30F devices and is not which use TBLPAG<7> to determine user or configura- intended to be a complete reference tion space access. In Table3-1, Program Space source. For more information on the CPU, Address Construction, bit23 allows access to the peripherals, register descriptions and Device ID, the Unit ID and the configuration bits. general device functionality, refer to the Otherwise, bit 23 is always clear. “dsPIC30F Family Reference Manual” Note: The address map shown in Figure3-1 and (DS70046). For more information on the Figure3-2 is conceptual, and the actual device instruction set and programming, memory configuration may vary across refer to the “16-bit MCU and DSC individual devices depending on available Programmer’s Reference Manual” memory. (DS70157). 3.1 Program Address Space The program address space is 4M instruction words. It is addressable by a 24-bit value from either the 23-bit PC, table instruction Effective Address (EA), or data space EA, when program space is mapped into data space as defined by Table3-1. Note that the program space address is incremented by two between succes- sive program words in order to provide compatibility with data space addressing. © 2011 Microchip Technology Inc. DS70143E-page 25

dsPIC30F6011A/6012A/6013A/6014A FIGURE 3-1: PROGRAM SPACE MEMORY FIGURE 3-2: PROGRAM SPACE MEMORY MAP FOR dsPIC30F6011A/ MAP FOR dsPIC30F6012A/ 6013A 6014A Reset – GOTO Instruction 000000 Reset – GOTO Instruction 000000 Reset – Target Address 000002 Reset – Target Address 000002 000004 000004 Vector Tables Vector Tables Interrupt Vector Table Interrupt Vector Table 00007E 00007E User MemorySpace Alte(Pr4nr4oaKUgRte rseian eVsmsree t FrrcMuvltaecoestdrmi hoTonarsby)le 0000000000000010F808004E User MemorySpace Alte(Pr4nr8oaKUgRte rseian eVsmsree tF rrcMuvltaecoestdrmi hoTonarsby)le 0000000000000010F808004E 015FFE 017FFE 016000 018000 Reserved Reserved (Read ‘0’s) (Read ‘0’s) 7FF7FE 7FEFFE Data EEPROM 7FF800 Data EEPROM 7FF000 (2 Kbytes) (4 Kbytes) 7FFFFE 7FFFFE 800000 800000 Reserved Reserved mory mory Me 8005BE Me 8005BE Configuration Space UNIRTIeDs e(3rv2e idnstr.) F8880007000F556FFC0F0E0E Configuration Space UNIRTIeDs e(3rv2e idnstr.) F8880007000F556FFC0F0E0E Device Configuration F80000 Device Configuration F80000 Registers F8000E Registers F8000E F80010 F80010 Reserved Reserved FEFFFE FEFFFE DEVID (2) FF0000 DEVID (2) FF0000 FFFFFE FFFFFE DS70143E-page 26 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (TBLPAG<7> = 0) TBLRD/TBLWT Configuration TBLPAG<7:0> Data EA<15:0> (TBLPAG<7> = 1) Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0> FIGURE 3-3: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 23 bits Using Program 0 Program Counter 0 Counter Select 1 EA Using Program 0 PSVPAG Reg Space Visibility 8 bits 15 bits EA Using 1/0 TBLPAG Reg Table Instruction 8 bits 16 bits User/ Configuration Byte 24-bit EA Space Select Select Note: Program space visibility cannot be used to access bits <23:16> of a word in program memory. © 2011 Microchip Technology Inc. DS70143E-page 27

dsPIC30F6011A/6012A/6013A/6014A 3.1.1 DATA ACCESS FROM PROGRAM A set of table instructions are provided to move byte or MEMORY USING TABLE word sized data to and from program space. INSTRUCTIONS 1. TBLRDL: Table Read Low This architecture fetches 24-bit wide program memory. Word: Read the lsw of the program address; Consequently, instructions are always aligned. P<15:0> maps to D<15:0>. However, as the architecture is modified Harvard, data Byte: Read one of the LSBs of the program can also be present in program space. address; P<7:0> maps to the destination byte when byte There are two methods by which program space can select = 0; be accessed: via special table instructions, or through P<15:8> maps to the destination byte when byte the remapping of a 16K word program space page into select = 1. the upper half of data space (see Section3.1.2 “Data 2. TBLWTL: Table Write Low (refer to Section6.0 Access From Program Memory using Program “Flash Program Memory” for details on Flash Space Visibility”). The TBLRDL and TBLWTL instruc- Programming) tions offer a direct method of reading or writing the lsw of any address within program space, without going 3. TBLRDH: Table Read High through data space. The TBLRDH and TBLWTH instruc- Word: Read the most significant word of the pro- tions are the only method whereby the upper 8 bits of a gram address; P<23:16> maps to D<7:0>; program space word can be accessed as data. D<15:8> will always be = 0. Byte: Read one of the MSBs of the program The PC is incremented by two for each successive address; 24-bit program word. This allows program memory P<23:16> maps to the destination byte when addresses to directly map to data space addresses. byte select = 0; Program memory can thus be regarded as two 16-bit The destination byte will always be = 0 when word wide address spaces, residing side by side, each byte select = 1. with the same address range. TBLRDL and TBLWTL 4. TBLWTH: Table Write High (refer to Section6.0 access the space which contains the Least Significant “Flash Program Memory” for details on Flash Data Word, and TBLRDH and TBLWTH access the Programming). space which contains the Most Significant Data Byte. Figure3-3 shows how the EA is created for table oper- ations and data space accesses (PSV = 1). Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word. FIGURE 3-4: PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD) PC Address 23 16 8 0 0x000000 00000000 0x000002 00000000 0x000004 00000000 0x000006 00000000 TBLRDL.B (Wn<0> = 0) TBLRDL.W Program Memory ‘Phantom’ Byte TBLRDL.B (Wn<0> = 1) (read as ‘0’) DS70143E-page 28 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 3-5: PROGRAM DATA TABLE ACCESS (MSB) TBLRDH.W PC Address 23 16 8 0 0x000000 00000000 0x000002 00000000 0x000004 00000000 0x000006 00000000 TBLRDH.B (Wn<0> = 0) Program Memory ‘Phantom’ Byte (read as ‘0’) TBLRDH.B (Wn<0> = 1) 3.1.2 DATA ACCESS FROM PROGRAM Note that by incrementing the PC by 2 for each MEMORY USING PROGRAM SPACE program memory word, the Least Significant 15 bits of VISIBILITY data space addresses directly map to the Least Signif- icant 15 bits in the corresponding program space The upper 32 Kbytes of data space may optionally be addresses. The remaining bits are provided by the Pro- mapped into any 16K word program space page. This gram Space Visibility Page register, PSVPAG<7:0>, as provides transparent access of stored constant data shown in Figure3-6. from X data space without the need to use special instructions (i.e., TBLRDL/H, TBLWTL/H instructions). Note: PSV access is temporarily disabled during table reads/writes. Program space access through the data space occurs if the MSb of the data space EA is set and program For instructions that use PSV which are executed space visibility is enabled by setting the PSV bit in the outside a REPEAT loop: Core Control register (CORCON). The functions of • The following instructions will require one CORCON are discussed in Section2.4 “DSP instruction cycle in addition to the specified Engine”. execution time: Data accesses to this area add an additional cycle to - MAC class of instructions with data operand the instruction being executed, since two program prefetch memory fetches are required. - MOV instructions Note that the upper half of addressable data space is - MOV.D instructions always part of the X data space. Therefore, when a • All other instructions will require two instruction DSP operation uses program space mapping to access cycles in addition to the specified execution time this memory region, Y data space should typically con- of the instruction. tain state (variable) data for DSP operations, whereas X data space should typically contain coefficient For instructions that use PSV which are executed (constant) data. inside a REPEAT loop: Although each data space address, 0x8000 and higher, • The following instances will require two instruction maps directly into a corresponding program memory cycles in addition to the specified execution time address (see Figure3-6), only the lower 16bits of the of the instruction: 24-bit program word are used to contain the data. The - Execution in the first iteration upper 8 bits should be programmed to force an illegal - Execution in the last iteration instruction to maintain machine robustness. Refer to - Execution prior to exiting the loop due to an the “16-bit MCU and DSC Programmer’s Reference interrupt Manual” (DS70157) for details on instruction encoding. - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle. © 2011 Microchip Technology Inc. DS70143E-page 29

dsPIC30F6011A/6012A/6013A/6014A FIGURE 3-6: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Program Space 0x000100 Data Space 0x0000 15 PSVPAG(1) EA<15> = 0 0x02 8 Data 16 Space 0x8000 EA 15 23 15 0 Address EA<15> = 1 0x010000 15 Concatenation 23 Upper Half of Data Space is Mapped into Program Space 0xFFFF 0x017FFF BSET CORCON,#2 ; PSV bit set MOV #0x02, W0 ; Set PSVPAG register MOV W0, PSVPAG MOV 0x8000, W0 ; Access program memory location ; using a data space access Data Read Note1: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines the page in program space to which the upper half of data space is being mapped). DS70143E-page 30 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 3.2 Data Address Space 3.2.2 DATA SPACES The core has two data spaces. The data spaces can be The X data space is used by all instructions and sup- considered either separate (for some DSP instruc- ports all Addressing modes. There are separate read tions), or as one unified linear address range (for MCU and write data buses. The X read data bus is the return instructions). The data spaces are accessed using two data path for all instructions that view data space as Address Generation Units (AGUs) and separate data combined X and Y address space. It is also the X paths. address space data path for the dual operand read instructions (MAC class). The X write data bus is the 3.2.1 DATA SPACE MEMORY MAP only write path to data space for all instructions. The data space memory is split into two blocks, X and The X data space also supports Modulo Addressing for Y data space. A key element of this architecture is that all instructions, subject to addressing mode restric- Y space is a subset of X space, and is fully contained tions. Bit-Reversed Addressing is only supported for within X space. In order to provide an apparent linear writes to X data space. addressing space, X and Y spaces have contiguous The Y data space is used in concert with the X data addresses. space by the MAC class of instructions (CLR, ED, EDAC, When executing any instruction other than one of the MAC, MOVSAC, MPY, MPY.N and MSC) to provide two MAC class of instructions, the X block consists of the 64 concurrent data read paths. No writes occur across the Kbyte data address space (including all Y addresses). Y bus. This class of instructions dedicates two W reg- When executing one of the MAC class of instructions, ister pointers, W10 and W11, to always address Y data the X block consists of the 64 Kbyte data address space, independent of X data space, whereas W8 and space excluding the Y address block (for data reads W9 always address X data space. Note that during only). In other words, all other instructions regard the accumulator write back, the data address space is con- entire data memory as one composite address space. sidered a combination of X and Y data spaces, so the The MAC class instructions extract the Y address space write occurs across the X bus. Consequently, the write from data space and address it using EAs sourced from can be to any address in the entire data space. W10 and W11. The remaining X data space is The Y data space can only be used for the data addressed using W8 and W9. Both address spaces are prefetch operation associated with the MAC class of concurrently accessed only with the MAC class instructions. It also supports Modulo Addressing for instructions. automated circular buffers. Of course, all other instruc- The data space memory maps are shown in Figure3-8 tions can access the Y data address space through the and Figure3-9. X data path as part of the composite linear space. The boundary between the X and Y data spaces is defined as shown in Figure3-7 and Figure3-8 and is not user programmable. Should an EA point to data outside its own assigned address space, or to a loca- tion outside physical memory, an all zero word/byte will be returned. For example, although Y address space is visible by all non-MAC instructions using any address- ing mode, an attempt by a MAC instruction to fetch data from that space using W8 or W9 (X space pointers) will return 0x0000. © 2011 Microchip Technology Inc. DS70143E-page 31

dsPIC30F6011A/6012A/6013A/6014A FIGURE 3-7: DATA SPACE MEMORY MAP FOR dsPIC30F6011A/6013A LSB MSB 16 bits Address Address MSB LSB 0x0001 0x0000 2 Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 8 Kbyte Near X Data RAM (X) Data Space 6 Kbyte 0x17FF 0x17FE SRAM Space 0x1801 0x1800 0x1FFF 0x1FFE Y Data RAM (Y) 0x1FFF 0x1FFE 0x2001 0x2000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE DS70143E-page 32 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 3-8: DATA SPACE MEMORY MAP FOR dsPIC30F6012A/6014A LSB MSB 16 bits Address Address MSB LSB 0x0001 0x0000 2 Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 8 Kbyte Near X Data RAM (X) Data Space 8 Kbyte 0x17FF 0x17FE SRAM Space 0x1801 0x1800 0x1FFF 0x1FFE Y Data RAM (Y) 0x27FF 0x27FE 0x2801 0x2800 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE © 2011 Microchip Technology Inc. DS70143E-page 33

dsPIC30F6011A/6012A/6013A/6014A FIGURE 3-9: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE SFR SPACE E C UNUSED A P S X (Y SPACE) Y SPACE UNUSED E C A P S X E C UNUSED A P S X Non-MAC Class Ops (Read) MAC Class Ops (Read) Indirect EA from any W Indirect EA from W10, W11 Indirect EA from W8, W9 TABLE 3-2: EFFECT OF INVALID 3.2.4 DATA ALIGNMENT MEMORY ACCESSES To help maintain backward compatibility with PIC® Attempted Operation Data Returned MCU devices and improve data space memory usage efficiency, the dsPIC30F instruction set supports both EA = an unimplemented address 0x0000(1) word and byte operations. Data is aligned in data mem- W8 or W9 used to access Y data 0x0000 ory and registers as words, but all data space EAs space in a MAC instruction resolve to bytes. Data byte reads will read the complete W10 or W11 used to access X 0x0000 word which contains the byte, using the LSb of any EA data space in a MAC instruction to determine which byte to select. The selected byte is placed onto the LSB of the X data path (no byte Note 1: An address error trap is generated when accesses are possible from the Y data path as the MAC an unimplemented memory address is class of instruction can only fetch words). That is, data accessed. memory and registers are organized as two parallel All effective addresses are 16 bits wide and point to byte wide entities with shared (word) address decode bytes within the data space. Therefore, the data space but separate write lines. Data byte writes only write to address range is 64 Kbytes or 32K words. the corresponding side of the array or register which matches the byte address. 3.2.3 DATA SPACE WIDTH As a consequence of this byte accessibility, all Effective The core data width is 16 bits. All internal registers are Address calculations (including those generated by the organized as 16-bit wide words. Data space memory is DSP operations which are restricted to word-sized organized in byte addressable, 16-bit wide blocks. data) are internally scaled to step through word aligned memory. For example, the core would recognize that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. DS70143E-page 34 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A All word accesses must be aligned to an even address. 3.2.6 SOFTWARE STACK Misaligned word data fetches are not supported so The dsPIC DSC devices contain a software stack. W15 care must be taken when mixing byte and word opera- is used as the Stack Pointer. tions, or translating from 8-bit MCU code. Should a mis- aligned read or write be attempted, an address error The Stack Pointer always points to the first available trap will be generated. If the error occurred on a read, free word and grows from lower addresses towards the instruction underway is completed, whereas if it higher addresses. It pre-decrements for stack pops and occurred on a write, the instruction will be executed but post-increments for stack pushes as shown in Figure3- the write will not occur. In either case, a trap will then 11. Note that for a PC push during any CALL instruc- be executed, allowing the system and/or user to exam- tion, the MSB of the PC is zero-extended before the ine the machine state prior to execution of the address push, ensuring that the MSB is always clear. fault. Note: A PC push during exception processing will concatenate the SRL register to the FIGURE 3-10: DATA ALIGNMENT MSB of the PC prior to the push. MSB LSB 15 8 7 0 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at 0001 Byte1 Byte 0 0000 Reset. As is the case for the Stack Pointer, SPLIM<0> 0003 Byte3 Byte 2 0002 is forced to ‘0’ because all stack operations must be word aligned. Whenever an Effective Address (EA) is Byte5 Byte 4 0005 0004 generated using W15 as a source or destination pointer, the address thus generated is compared with the value in SPLIM. If the contents of the Stack Pointer All byte loads into any W register are loaded into the (W15) and the SPLIM register are equal and a push LSB. The MSB is not modified. operation is performed, a Stack Error Trap will not A sign-extend (SE) instruction is provided to allow occur. The Stack Error Trap will occur on a subsequent users to translate 8-bit signed data to 16-bit signed push operation. Thus, for example, if it is desirable to values. Alternatively, for 16-bit unsigned data, users cause a Stack Error Trap when the stack grows beyond can clear the MSB of any W register by executing a address 0x2000 in RAM, initialize the SPLIM with the zero-extend (ZE) instruction on the appropriate value, 0x1FFE. address. Similarly, a Stack Pointer underflow (stack error) trap is Although most instructions are capable of operating on generated when the Stack Pointer address is found to word or byte data sizes, it should be noted that some be less than 0x0800, thus preventing the stack from instructions, including the DSP instructions, operate interfering with the Special Function Register (SFR) only on words. space. A write to the SPLIM register should not be immediately 3.2.5 NEAR DATA SPACE followed by an indirect read operation using W15. An 8 Kbyte ‘near’ data space is reserved in X address memory space between 0x0000 and 0x1FFF, which is FIGURE 3-11: CALL STACK FRAME directly addressable via a 13-bit absolute address field within all memory direct instructions. The remaining X 0x0000 15 0 address space and all of the Y address space is addressable indirectly. Additionally, the whole of X data space is addressable using MOV instructions, which ds support memory direct addressing with a 16-bit waress address field. ows Toer Addr PC<15:0> W15 (before CALL) Grgh 000000000 PC<22:16> ck Hi <Free Word> W15 (after CALL) a St POP : [--W15] PUSH: [W15++] © 2011 Microchip Technology Inc. DS70143E-page 35

dsPIC30F6011A/6012A/6013A/6014A 3.2.7 DATA RAM PROTECTION FEATURE The dsPIC30F6011A/6012A/6013A/6014A devices support data RAM protection features which enable segments of RAM to be protected when used in con- junction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled. SSRAM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code when enabled. See Table3-3 for an overview of the BSRAM and SSRAM SFRs. DS70143E-page 36 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u 0 u 0 u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u Stat 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 uuu uuu uuu 0uu uuu 0uu et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u 0 u 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u 0 u 0 e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u 0 u 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 u u u 0 u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u 0 u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u 0 u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u 0 u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u 0 u 0 0 Bit 0 0 1 Bit 2 Bit H T H 4Bit 3 ACCAU ACCBU PCH TBLPAG PSVPAG DOSTAR DOEND Bit 5 Bit 6 Bit 7 Bit G — — — s. Bit 9Bit 8 W0 / WRE W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 SPLIM ACCAL ACCAH ACCBL ACCBH PCL —— —— —— RCOUNT DCOUNT DOSTARTL —— DOENDL —— s of register bit field n o Bit 11Bit 10 CCA<39>) CCB<39>) —— —— —— —— —— 0046) for descripti 2 n (A n (A s ‘’0DS7 (1)MAP Bit 13Bit 1 Sign-Extensio Sign-Extensio —— —— —— —— —— nted bit, read aence Manual” ( GISTER Bit 14 — — — — — = unimplemeFamily Refer E — F 3:CORE R AddressBit 15(Home) 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 0022 0024 0026 0028 002A 002C 002E 0030— 0032— 0034— 0036 0038 003A 003C— 003E 0040— u = uninitialized bit; Refer to the “dsPIC30 - 3 e L H TABLE SFR Nam W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 SPLIM ACCAL ACCAH ACCAU ACCBL ACCBH ACCBU PCL PCH TBLPAG PSVPAG RCOUNT DCOUNT DOSTART DOSTART DOENDL DOENDH Legend:Note1: © 2011 Microchip Technology Inc. DS70143E-page 37

dsPIC30F6011A/6012A/6013A/6014A 0 0 0 0 1 0 1 u 0 0 0 0 0 0 u u u u u 0 0 0 0 0 0 u u u u u 0 0 0 0 0 0 u u u u u 0 0 0 e 0 0 0 u u u u u 0 0 0 Stat 000 001 000 uuu uuu uuu uuu uuu 000 000 000 et 0 0 0 u u u u u 0 0 0 s 0 0 0 u u u u u 0 0 0 e 0 0 0 u u u u u 0 0 0 R 0 0 0 u u u u u 0 0 0 0 0 0 u u u u u 0 0 0 0 0 0 u u u u u 0 0 0 0 0 0 u u u u u 0 0 0 0 0 0 u u u u u 0 0 0 R R 0 S S Bit C IF 0 1 0 1 L_B L_S R R R R 1 D S S Bit Z RN 3:0> R_B R_S < I I Bit 2 OV PSV XWM W_BSR W_SSR I I 3 3 Bit N IPL — — T Bit 4 RA CCSA — — A W Bit 5 IPL0 SATD <3:0> — — M Bit 6 IPL1 SATB YW <13:0> — — T Bit 8Bit 7 DCIPL2 DL0SATA <15:1> <15:1> <15:1> <15:1> XB<14:0> DISICN —— —— ster bit fields. S E S E gi X X Y Y e Bit 9 DA DL1 3:0> — — ns of r < o D) Bit 10 SAB DL2 BWM — — descripti E or TINU Bit 11 OAB EDT — — 0046) f ON 2 s ‘’0DS7 (1)MAP (C Bit 13Bit 1 SASB —US —— —— —— nted bit, read aence Manual” ( GISTER Bit 14 OB — YMODEN — — — = unimplemeFamily Refer E — F 3:CORE R AddressBit 15(Home) 0042OA 0044— 0046XMODEN 0048 004A 004C 004E 0050BREN 0052— 0750— 0752— u = uninitialized bit; Refer to the “dsPIC30 - TABLE 3 SFR Name SR CORCON MODCON XMODSRT XMODEND YMODSRT YMODEND XBREV DISICNT BSRAM SSRAM Legend:Note1: DS70143E-page 38 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 4.0 ADDRESS GENERATOR UNITS 4.1.1 FILE REGISTER INSTRUCTIONS Most File register instructions use a 13-bit address field Note: This data sheet summarizes features of (f) to directly address data present in the first 8192 this group ofdsPIC30F devices and is not bytes of data memory (Near data space). Most File intended to be a complete reference register instructions employ a working register, W0, source. For more information on the CPU, which is denoted as WREG in these instructions. The peripherals, register descriptions and destination is typically either the same File register or general device functionality, refer to the WREG (with the exception of the MUL instruction), “dsPIC30F Family Reference Manual” which writes the result to a register or register pair. The (DS70046). For more information on the MOV instruction allows additional flexibility and can device instruction set and programming, access the entire data space. refer to the “16-bit MCU and DSC Programmer’s Reference Manual” 4.1.2 MCU INSTRUCTIONS (DS70157). The three-operand MCU instructions are of the form: The dsPIC DSC core contains two independent Operand 3 = Operand 1 <function> Operand 2 address generator units: the X AGU and Y AGU. The Y where: AGU supports word sized data reads for the DSP MAC class of instructions only. The dsPIC30F AGUs Operand 1 is always a working register (i.e., the support: Addressing mode can only be Register Direct) which is referred to as Wb. • Linear Addressing • Modulo (Circular) Addressing Operand 2 can be a W register, fetched from data memory or a 5-bit literal. The result location can be • Bit-Reversed Addressing either a W register or a data memory location. The fol- Linear and Modulo Data Addressing modes can be lowing addressing modes are supported by MCU applied to data space or program space. Bit-Reversed instructions: Addressing is only applicable to data space addresses. • Register Direct 4.1 Instruction Addressing Modes • Register Indirect • Register Indirect Post-modified The Addressing modes in Table4-1 form the basis of • Register Indirect Pre-modified the Addressing modes optimized to support the specific • 5-bit or 10-bit Literal features of individual instructions. The Addressing modes provided in the MAC class of instructions are Note: Not all instructions support all the somewhat different from those in the other instruction addressing modes given above. Individual types. instructions may support different subsets of these addressing modes. TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the File register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the EA. Register Indirect Post-modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. © 2011 Microchip Technology Inc. DS70143E-page 39

dsPIC30F6011A/6012A/6013A/6014A 4.1.3 MOVE AND ACCUMULATOR In summary, the following Addressing modes are INSTRUCTIONS supported by the MAC class of instructions: Move instructions and the DSP accumulator class of • Register Indirect instructions provide a greater degree of addressing • Register Indirect Post-modified by 2 flexibility than other instructions. In addition to the • Register Indirect Post-modified by 4 Addressing modes supported by most MCU instruc- • Register Indirect Post-modified by 6 tions, move and accumulator instructions also support • Register Indirect with Register Offset (Indexed) Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. 4.1.5 OTHER INSTRUCTIONS Note: For the MOV instructions, the addressing Besides the various Addressing modes outlined above, mode specified in the instruction can differ some instructions use literal constants of various sizes. for the source and destination EA. For example, BRA (branch) instructions use 16-bit However, the 4-bit Wb (register offset) signed literals to specify the branch destination directly, field is shared between both source and whereas the DISI instruction uses a 14-bit unsigned destination (but typically only used by literal field. In some instructions, such as ADD Acc, the one). source of an operand or result is implied by the opcode In summary, the following Addressing modes are itself. Certain operations, such as NOP, do not have any operands. supported by move and accumulator instructions: • Register Direct 4.2 Modulo Addressing • Register Indirect • Register Indirect Post-modified Modulo Addressing is a method of providing an auto- mated means to support circular data buffers using • Register Indirect Pre-modified hardware. The objective is to remove the need for soft- • Register Indirect with Register Offset (Indexed) ware to perform data address boundary checks when • Register Indirect with Literal Offset executing tightly looped code, as is typical in many • 8-bit Literal DSP algorithms. • 16-bit Literal Modulo Addressing can operate in either data or pro- Note: Not all instructions support all the gram space (since the data pointer mechanism is Addressing modes given above. essentially the same for both). One circular buffer can Individual instructions may support be supported in each of the X (which also provides the different subsets of these Addressing pointers into program space) and Y data spaces. Mod- modes. ulo Addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for Mod- 4.1.4 MAC INSTRUCTIONS ulo Addressing since these two registers are used as the Stack Frame Pointer and Stack Pointer, The dual source operand DSP instructions (CLR, ED, respectively. EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred to as MAC instructions, utilize a simplified set of In general, any particular circular buffer can only be Addressing modes to allow the user to effectively configured to operate in one direction, as there are cer- manipulate the data pointers through register indirect tain restrictions on the buffer start address (for incre- tables. menting buffers), or end address (for decrementing buffers) based upon the direction of the buffer. The two source operand prefetch registers must be a member of the set {W8, W9, W10, W11}. For data The only exception to the usage restrictions is for buf- reads, W8 and W9 will always be directed to the X fers which have a power-of-2 length. As these buffers RAGU and W10 and W11 will always be directed to the satisfy the start and end address criteria, they may Y AGU. The effective addresses generated (before and operate in a Bidirectional mode (i.e., address boundary after modification) must, therefore, be valid addresses checks will be performed on both the lower and upper within X data space for W8 and W9 and Y data space address boundaries). for W10 and W11. Note: Register indirect with register offset addressing is only available for W9 (in X space) and W11 (in Y space). DS70143E-page 40 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 4.2.1 START AND END ADDRESS 4.2.2 W ADDRESS REGISTER SELECTION The Modulo Addressing scheme requires that a start- ing and an ending address be specified and loaded into The Modulo and Bit-Reversed Addressing Control reg- the 16-bit Modulo Buffer Address registers: XMODSRT, ister MODCON<15:0> contains enable flags as well as XMODEND, YMODSRT, YMODEND (see Table3-3). a W register field to specify the W address registers. The XWM and YWM fields select which registers will Note: Y space Modulo Addressing EA calcula- operate with Modulo Addressing. If XWM = 15, X tions assume word sized data (LSb of RAGU and X WAGU Modulo Addressing is disabled. every EA is always clear). Similarly, if YWM = 15, Y AGU Modulo Addressing is The length of a circular buffer is not directly specified. It disabled. is determined by the difference between the corre- The X Address Space Pointer W register (XWM), to sponding start and end addresses. The maximum which Modulo Addressing is to be applied, is stored in possible length of the circular buffer is 32K words MODCON<3:0> (see Table3-3). Modulo Addressing is (64Kbytes). enabled for X data space when XWM is set to any value other than ‘15’ and the XMODEN bit is set at MODCON<15>. The Y Address Space Pointer W register (YWM), to which Modulo Addressing is to be applied, is stored in MODCON<7:4>. Modulo Addressing is enabled for Y data space when YWM is set to any value other than ‘15’ and the YMODEN bit is set at MODCON<14>. FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE Byte Address MOV #0x1100,W0 MOV W0,XMODSRT ;set modulo start address MOV #0x1163,W0 MOV W0,MODEND ;set modulo end address 0x1100 MOV #0x8001,W0 MOV W0,MODCON ;enable W1, X AGU for modulo MOV #0x0000,W0 ;W0 holds buffer fill value MOV #0x1110,W1 ;point W1 to buffer DO AGAIN,#0x31 ;fill the 50 buffer locations MOV W0,[W1++] ;fill the next location 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2011 Microchip Technology Inc. DS70143E-page 41

dsPIC30F6011A/6012A/6013A/6014A 4.2.3 MODULO ADDRESSING If the length of a bit-reversed buffer is M = 2N bytes, APPLICABILITY then the last ‘N’ bits of the data buffer start address must be zeros. Modulo Addressing can be applied to the Effective Address calculation associated with any W register. It XB<14:0> is the bit-reversed address modifier or ‘pivot is important to realize that the address boundaries point’, which is typically a constant. In the case of an check for addresses less than, or greater than the FFT computation, its value is equal to half of the FFT upper (for incrementing buffers), and lower (for decre- data buffer size. menting buffers) boundary addresses (not just equal Note: All bit-reversed EA calculations assume to). Address changes may, therefore, jump beyond word sized data (LSb of every EA is boundaries and still be adjusted correctly. always clear). The XB value is scaled Note: The modulo corrected Effective Address accordingly to generate compatible (byte) is written back to the register only when addresses. Pre-Modify or Post-Modify Addressing When enabled, Bit-Reversed Addressing will only be mode is used to compute the Effective executed for register indirect with pre-increment or Address. When an address offset (e.g., post-increment addressing and word sized data writes. [W7+W2]) is used, modulo address cor- It will not function for any other addressing mode or for rection is performed but the contents of byte sized data, and normal addresses will be gener- the register remain unchanged. ated instead. When Bit-Reversed Addressing is active, the W address pointer will always be added to the 4.3 Bit-Reversed Addressing address modifier (XB) and the offset associated with the Register Indirect Addressing mode will be ignored. Bit-Reversed Addressing is intended to simplify data In addition, as word sized data is a requirement, the re-ordering for radix-2 FFT algorithms. It is supported LSb of the EA is ignored (and always clear). by the X AGU for data writes only. Note: Modulo Addressing and Bit-Reversed The modifier, which may be a constant value or register Addressing should not be enabled contents, is regarded as having its bit order reversed. The together. In the event that the user address source and destination are kept in normal order. attempts to do this, Bit-Reversed Address- Thus, the only operand requiring reversal is the modifier. ing will assume priority when active for the 4.3.1 BIT-REVERSED ADDRESSING X WAGU, and X WAGU Modulo Address- ing will be disabled. However, Modulo IMPLEMENTATION Addressing will continue to function in the X Bit-Reversed Addressing is enabled when: RAGU. 1. BWM (W register selection) in the MODCON If Bit-Reversed Addressing has already been enabled register is any value other than ‘15’ (the stack by setting the BREN (XBREV<15>) bit, then a write to cannot be accessed using Bit-Reversed the XBREV register should not be immediately followed Addressing) and by an indirect read operation using the W register that 2. the BREN bit is set in the XBREV register and has been designated as the bit-reversed pointer. 3. the Addressing mode used is Register Indirect with Pre-Increment or Post-Increment. DS70143E-page 42 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value 4096 0x0800 2048 0x0400 1024 0x0200 512 0x0100 256 0x0080 128 0x0040 64 0x0020 32 0x0010 16 0x0008 8 0x0004 4 0x0002 2 0x0001 © 2011 Microchip Technology Inc. DS70143E-page 43

dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 44 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 5.0 INTERRUPTS • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from Note: This data sheet summarizes features of these two registers. INTCON1 contains the con- this group ofdsPIC30F devices and is not trol and status flags for the processor exceptions. intended to be a complete reference The INTCON2 register controls the external source. For more information on the CPU, interrupt request signal behavior and the use of peripherals, register descriptions and the alternate vector table. general device functionality, refer to the Note: Interrupt flag bits get set when an interrupt “dsPIC30F Family Reference Manual” condition occurs, regardless of the state of (DS70046). For more information on the its corresponding enable bit. User soft- device instruction set and programming, refer to the “16-bit MCU and DSC ware should ensure the appropriate inter- Programmer’s Reference Manual” rupt flag bits are clear prior to enabling an (DS70157). interrupt. All interrupt sources can be user assigned to one of 7 The dsPIC30F Sensor and General Purpose Family has priority levels, 1 through 7, via the IPCx registers. Each up to 41 interrupt sources and 4 processor exceptions (traps) which must be arbitrated based on a priority interrupt source is associated with an interrupt vector, scheme. as shown in Table5-1. Levels 7 and 1 represent the highest and lowest maskable priorities, respectively. The CPU is responsible for reading the Interrupt Vector Table (IVT) and transferring the address contained in the Note: Assigning a priority level of ‘0’ to an inter- interrupt vector to the Program Counter. The interrupt rupt source is equivalent to disabling that vector is transferred from the program data bus into the interrupt. Program Counter via a 24-bit wide multiplexer on the If the NSTDIS bit (INTCON1<15>) is set, nesting of input of the Program Counter. interrupts is prevented. Thus, if an interrupt is currently The Interrupt Vector Table (IVT) and Alternate Interrupt being serviced, processing of a new interrupt is pre- Vector Table (AIVT) are placed near the beginning of vented even if the new interrupt is of higher priority than program memory (0x000004). The IVT and AIVT are the one currently being serviced. shown in Table5-1. Note: The IPL bits become read only whenever The interrupt controller is responsible for pre-processing the NSTDIS bit has been set to ‘1’. the interrupts and processor exceptions prior to them being presented to the processor core. The peripheral Certain interrupts have specialized control bits for fea- interrupts and traps are enabled, prioritized and con- tures like edge or level triggered interrupts, interrupt- trolled using centralized Special Function Registers: on-change, etc. Control of these features remains • IFS0<15:0>, IFS1<15:0>, IFS2<15:0> within the peripheral module which generates the All interrupt request flags are maintained in these interrupt. three registers. The flags are set by their respective The DISI instruction can be used to disable the pro- peripherals or external signals, and they are cessing of interrupts of priorities 6 and lower for a cer- cleared via software. tain number of instructions, during which the DISI bit • IEC0<15:0>, IEC1<15:0>, IEC2<15:0> (INTCON2<14>) remains set. All interrupt enable control bits are maintained in When an interrupt is serviced, the PC is loaded with the these three registers. These control bits are used to individually enable interrupts from the peripherals address stored in the vector location in program mem- or external signals. ory that corresponds to the interrupt. There are 63 dif- ferent vectors within the IVT (refer to Table5-1). These • IPC0<15:0>... IPC10<7:0> vectors are contained in locations 0x000004 through The user assignable priority level associated with each of these 41 interrupts is held centrally in these 0x0000FE of program memory (refer to Table5-1). twelve registers. These locations contain 24-bit addresses and in order to preserve robustness, an address error trap will take • IPL<3:0> place should the PC attempt to fetch any of these The current CPU priority level is explicitly stored in the IPL bits. IPL<3> is present in the CORCON words during normal execution. This prevents execu- register, whereas IPL<2:0> are present in the tion of random data as a result of accidentally decre- STATUS register (SR) in the processor core. menting a PC into vector space, accidentally mapping a data space address into vector space, or the PC roll- • INTTREG<15:0> The associated interrupt vector number and the ing over to 0x000000 after reaching the end of imple- new CPU interrupt priority level are latched into mented program memory space. Execution of a GOTO vector number (VECNUM<5:0>) and Interrupt level instruction to this vector space will also generate an (ILR<3:0>) bit fields in the INTTREG register. The address error trap. new interrupt priority level is the priority of the pending interrupt. © 2011 Microchip Technology Inc. DS70143E-page 45

dsPIC30F6011A/6012A/6013A/6014A 5.1 Interrupt Priority TABLE 5-1: INTERRUPT VECTOR TABLE The user-assignable interrupt priority (IP<2:0>) bits for INT Vector Interrupt Source each individual interrupt source are located in the Least Number Number Significant 3bits of each nibble within the IPCx regis- Highest Natural Order Priority ter(s). Bit 3 of each nibble is not used and is read as a 0 8 INT0 – External Interrupt 0 ‘0’. These bits define the priority level assigned to a 1 9 IC1 – Input Capture 1 particular interrupt by the user. 2 10 OC1 – Output Compare 1 Note: The user-assignable priority levels start at 3 11 T1 – Timer1 0 as the lowest priority and level 7 as the 4 12 IC2 – Input Capture 2 highest priority. 5 13 OC2 – Output Compare 2 Since more than one interrupt request source may be 6 14 T2 – Timer2 assigned to a specific user-assigned priority level, a 7 15 T3 – Timer3 means is provided to assign priority within a given level. 8 16 SPI1 This method is called “Natural Order Priority” and is 9 17 U1RX – UART1 Receiver final. 10 18 U1TX – UART1 Transmitter Natural order priority is determined by the position of an 11 19 ADC – ADC Convert Done interrupt in the vector table, and only affects interrupt 12 20 NVM – NVM Write Complete operation when multiple interrupts with the same user- 13 21 SI2C – I2C™ Slave Interrupt assigned priority become pending at the same time. 14 22 MI2C – I2C Master Interrupt Table5-1 lists the interrupt numbers and interrupt 15 23 Input Change Interrupt sources for the dsPIC DSC device and their associated 16 24 INT1 – External Interrupt 1 vector numbers. 17 25 IC7 – Input Capture 7 Note1: The natural order priority scheme has 0 18 26 IC8 – Input Capture 8 as the highest priority and 53 as the 19 27 OC3 – Output Compare 3 lowest priority. 20 28 OC4 – Output Compare 4 2: The natural order priority number is the 21 29 T4 – Timer4 same as the INT number. 22 30 T5 – Timer5 The ability for the user to assign every interrupt to one 23 31 INT2 – External Interrupt 2 of seven priority levels implies that the user can assign 24 32 U2RX – UART2 Receiver a very high overall priority level to an interrupt with a 25 33 U2TX – UART2 Transmitter low natural order priority. For example, the PLVD 26 34 SPI2 (Low-Voltage Detect) can be given a priority of 7. The 27 35 C1 – Combined IRQ for CAN1 INT0 (External Interrupt 0) may be assigned to priority level 1, thus giving it a very low effective priority. 28 36 IC3 – Input Capture 3 29 37 IC4 – Input Capture 4 30 38 IC5 – Input Capture 5 31 39 IC6 – Input Capture 6 32 40 OC5 – Output Compare 5 33 41 OC6 – Output Compare 6 34 42 OC7 – Output Compare 7 35 43 OC8 – Output Compare 8 36 44 INT3 – External Interrupt 3 37 45 INT4 – External Interrupt 4 38 46 C2 – Combined IRQ for CAN2 39-40 47-48 Reserved 41 49 DCI – Codec Transfer Done(1) 42 50 LVD – Low-Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority Note 1: Reserved on dsPIC30F6011A and dsPIC30F6013A because the DCI module is not available on these devices. DS70143E-page 46 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 5.2 Reset Sequence Note that many of these trap conditions can only be detected when they occur. Consequently, the question- A Reset is not a true exception, because the interrupt able instruction is allowed to complete prior to trap controller is not involved in the Reset process. The pro- exception processing. If the user chooses to recover cessor initializes its registers in response to a Reset from the error, the result of the erroneous action that which forces the PC to zero. The processor then begins caused the trap may have to be corrected. program execution at location 0x000000. A GOTO There are 8 fixed priority levels for traps: level 8 through instruction is stored in the first program memory loca- level 15, which implies that the IPL3 is always set tion immediately followed by the address target for the during processing of a trap. GOTO instruction. The processor executes the GOTO to the specified address and then begins operation at the If the user is not currently executing a trap, and he sets specified target (start) address. the IPL<3:0> bits to a value of ‘0111’ (level 7), then all interrupts are disabled but traps can still be processed. 5.2.1 RESET SOURCES 5.3.1 TRAP SOURCES In addition to external Reset and Power-on Reset (POR), there are 6 sources of error conditions which The following traps are provided with increasing prior- ‘trap’ to the Reset vector. ity. However, since all traps can be nested, priority has little effect. • Watchdog Time-out: The watchdog has timed out, indicating that the Math Error Trap: processor is no longer executing the correct flow of code. The math error trap executes under the following four circumstances: • Uninitialized W Register Trap: An attempt to use an uninitialized W register as • Should an attempt be made to divide by zero, the an address pointer will cause a Reset. divide operation will be aborted on a cycle • Illegal Instruction Trap: boundary and the trap taken. Attempted execution of any unused opcodes will • If enabled, a math error trap will be taken when an result in an illegal instruction trap. Note that a arithmetic operation on either accumulator A or B fetch of an illegal instruction does not result in an causes an overflow from bit 31 and the accumula- illegal instruction trap if that instruction is flushed tor guard bits are not utilized. prior to execution due to a flow change. • If enabled, a math error trap will be taken when an • Brown-out Reset (BOR): arithmetic operation on either accumulator A or B A momentary dip in the power supply to the causes a catastrophic overflow from bit 39 and all device has been detected which may result in saturation is disabled. malfunction. • If the shift amount specified in a shift instruction is • Trap Lockout: greater than the maximum allowed shift amount, a Occurrence of multiple trap conditions trap will occur. simultaneously will cause a Reset. Address Error Trap: • Software Reset Instruction This trap is initiated when any of the following 5.3 Traps circumstances occurs: Traps can be considered as non-maskable interrupts • A misaligned data word access is attempted indicating a software or hardware error, which adhere • A data fetch from and unimplemented data to a predefined priority, as shown in Table5-1. They are memory location is attempted intended to provide the user a means to correct • A data fetch from an unimplemented program erroneous operation during debug and when operating memory location is attempted within the application. • An instruction fetch from vector space is Note: If the user does not intend to take correc- attempted tive action in the event of a trap error con- Note: In the MAC class of instructions, wherein dition, these vectors must be loaded with the data space is split into X and Y data the address of a default handler that sim- space, unimplemented X space includes ply contains the RESET instruction. If, on all of Y space, and unimplemented Y the other hand, one of the vectors contain- space includes all of X space. ing an invalid address is called, an address error trap is generated. © 2011 Microchip Technology Inc. DS70143E-page 47

dsPIC30F6011A/6012A/6013A/6014A • Execution of a “BRA #literal” instruction or a FIGURE 5-1: TRAP VECTORS “GOTO #literal” instruction, where literal is an unimplemented program memory address Reset - GOTO Instruction 0x000000 Reset - GOTO Address 0x000002 • Executing instructions after modifying the PC to Reserved 0x000004 point to unimplemented program memory Oscillator Fail Trap Vector Address Error Trap Vector addresses. The PC may be modified by loading a g Stack Error Trap Vector vinaslutreu cintioton the stack and executing a RETURN ecreasinPriority IVT MaRRRtheee Essseeerrrrrovvvreee Tdddr aVVVpeee cccVtttoooerrrctor D Interrupt 0 Vector 0x000014 Stack Error Trap: Interrupt 1 Vector ~ This trap is initiated under the following conditions: ~ ~ • The Stack Pointer is loaded with a value which is Interrupt 52 Vector greater than the (user programmable) limit value Interrupt 53 Vector 0x00007E Reserved 0x000080 written into the SPLIM register (stack overflow) Reserved 0x000082 Reserved 0x000084 • The Stack Pointer is loaded with a value which is Oscillator Fail Trap Vector less than 0x0800 (simple stack underflow) Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Oscillator Fail Trap: AIVT Reserved Vector Reserved Vector This trap is initiated if the external oscillator fails and Reserved Vector Interrupt 0 Vector 0x000094 operation becomes reliant on an internal RC backup. Interrupt 1 Vector ~ ~ 5.3.2 HARD AND SOFT TRAPS ~ Interrupt 52 Vector It is possible that multiple traps can become active Interrupt 53 Vector 0x0000FE within the same cycle (e.g., a misaligned word stack write to an overflowed address). In such a case, the fixed priority shown in Figure5-1 is implemented, 5.4 Interrupt Sequence which may require the user to check if other traps are pending in order to completely correct the fault. All interrupt event flags are sampled in the beginning of each instruction cycle by the IFSx registers. A pending ‘Soft’ traps include exceptions of priority level 8 through Interrupt Request (IRQ) is indicated by the flag bit level 11, inclusive. The arithmetic error trap (level 11) being equal to a ‘1’ in an IFSx register. The IRQ will falls into this category of traps. cause an interrupt to occur if the corresponding bit in ‘Hard’ traps include exceptions of priority level 12 the Interrupt Enable (IECx) register is set. For the through level 15, inclusive. The address error (level remainder of the instruction cycle, the priorities of all 12), stack error (level 13) and oscillator error (level 14) pending interrupt requests are evaluated. traps fall into this category. If there is a pending IRQ with a priority level greater Each hard trap that occurs must be acknowledged than the current processor priority level in the IPL bits, before code execution of any type may continue. If a the processor will be interrupted. lower priority hard trap occurs while a higher priority The processor then stacks the current Program Coun- trap is pending, acknowledged, or is being processed, ter and the low byte of the processor STATUS register a hard trap conflict will occur. (SRL), as shown in Figure5-2. The low byte of the The device is automatically reset in a hard trap conflict STATUS register contains the processor priority level at condition. The TRAPR status bit (RCON<15>) is set the time prior to the beginning of the interrupt cycle. when the Reset occurs so that the condition may be The processor then loads the priority level for this inter- detected in software. rupt into the STATUS register. This action will disable all lower priority interrupts until the completion of the Interrupt Service Routine. DS70143E-page 48 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 5-2: INTERRUPT STACK 5.6 Fast Context Saving FRAME A context saving option is available using shadow reg- isters. Shadow registers are provided for the DC, N, 0x0000 15 0 OV, Z and C bits in SR, and the registers W0 through W3. The shadows are only one level deep. The shadow s registers are accessible using the PUSH.S and POP.S d ars instructions only. ws Todre When the processor vectors to an interrupt, the ws Ad PC<15:0> W15 (before CALL) PUSH.S instruction can be used to store the current Groher SRL IPL3 PC<22:16> value of the aforementioned registers into their ck Hig <Free Word> W15 (after CALL) respective shadow registers. a St If an ISR of a certain priority uses the PUSH.S and POP :[--W15] POP.S instructions for fast context saving, then a PUSH:[W15++] higher priority ISR should not include the same instruc- tions. Users must save the key registers in software during a lower priority interrupt if the higher priority ISR uses fast context saving. Note1: The user can always lower the priority level by writing a new value into SR. The 5.7 External Interrupt Requests Interrupt Service Routine must clear the interrupt flag bits in the IFSx register The interrupt controller supports up to five external before lowering the processor interrupt interrupt request signals, INT0-INT4. These inputs are priority, in order to avoid recursive edge sensitive; they require a low-to-high or a high-to- interrupts. low transition to generate an interrupt request. The 2: The IPL3 bit (CORCON<3>) is always INTCON2 register has five bits, INT0EP-INT4EP, that clear when interrupts are being pro- select the polarity of the edge detection circuitry. cessed. It is set only during execution of traps. 5.8 Wake-up from Sleep and Idle The RETFIE (return from interrupt) instruction will The interrupt controller may be used to wake-up the unstack the Program Counter and STATUS registers to processor from either Sleep or Idle modes, if Sleep or return the processor to its state prior to the interrupt Idle mode is active when the interrupt is generated. sequence. If an enabled interrupt request of sufficient priority is received by the interrupt controller, then the standard 5.5 Alternate Vector Table interrupt request is presented to the processor. At the same time, the processor will wake-up from Sleep or In program memory, the Interrupt Vector Table (IVT) is Idle and begin execution of the Interrupt Service followed by the Alternate Interrupt Vector Table (AIVT), Routine (ISR) needed to process the interrupt request. as shown in Table5-1. Access to the alternate vector table is provided by the ALTIVT bit in the INTCON2 reg- ister. If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT sup- ports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not required, the program memory allo- cated to the AIVT may be used for other purposes. AIVT is not a protected section and may be freely programmed by the user. © 2011 Microchip Technology Inc. DS70143E-page 49

dsPIC30F6011A/6012A/6013A/6014A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 et State 0 0000 0 0 0000 0 0000 0 0000 0 0000 0 0000 0 0000 0 0000 0 0100 0 0100 0 0100 0 0100 0 0100 0 0100 0 0100 0 0100 0 0100 0 0100 0 0100 0 0000 Res 000 000 000 000 000 000 000 000 010 010 010 010 010 010 010 010 010 010 010 000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 0 — NT0EP NT0IF NT1IF OC5IF NT0IE NT1IE OC5IE — Bit 2Bit 1 STKERROSCFAIL INT2EPINT1EPI OC1IFIC1IFI IC8IFIC7IFI OC7IFOC6IF OC1IEIC1IEI IC8IEIC7IEI OC7IEOC6IE INT0IP<2:0> IC2IP<2:0> SPI1IP<2:0> NVMIP<2:0> INT1IP<2:0> OC4IP<2:0> U2RXIP<2:0> IC3IP<2:0> OC5IP<2:0> INT3IP<2:0> —— <5:0> M R U Bit 3 ADDRER INT3EP T1IF OC3IF OC8IF T1IE OC3IE OC8IE — — — — — — — — — — — VECN R Bit 5Bit 4 —MATHER —INT4EP OC2IFIC2IF T4IFOC4IF INT4IFINT3IF OC2IEIC2IE T4IEOC4IE INT4IEINT3IE IC1IP<2:0> OC2IP<2:0> U1RXIP<2:0> SI2CIP<2:0> IC7IP<2:0> T4IP<2:0> U2TXIP<2:0> IC4IP<2:0> OC6IP<2:0> NT41IP<2:0> (2)DCIIP<2:0> I 6 F F F E E E Bit — — T2I T5I C2I T2I T5I C2I — elds. Bit 7 — — T3IF INT2IF — T3IE INT2IE — — — — — — — — — — — — — gister bit fi e (1)5-2:INTERRUPT CONTROLLER REGISTER MAP ADRBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8 0080NSTDIS————OVATEOVBTECOVTE 0082ALTIVT DISI—————— 0084CNIFMI2CIF SI2CIFNVMIFADIFU1TXIFU1RXIFSPI1IF 0086IC6IFIC5IFIC4IFIC3IFC1IFSPI2IFU2TXIFU2RXIF 20088—————LVDIF—DCIIF 008CCNIEMI2CIESI2CIENVMIEADIEU1TXIEU1RXIESPI1IE 008EIC6IEIC5IEIC4IEIC3IEC1IESPI2IEU2TXIEU2RXIE 20090—————LVDIE—DCIIE 0094—T1IP<2:0>—OC1IP<2:0> 0096—T31P<2:0>—T2IP<2:0> 0098—ADIP<2:0>—U1TXIP<2:0> 009A—CNIP<2:0>—MI2CIP<2:0> 009C—OC3IP<2:0>—IC8IP<2:0> 009E—INT2IP<2:0>—T5IP<2:0> 00A0—C1IP<2:0>—SPI2IP<2:0> 00A2—IC6IP<2:0>—IC5IP<2:0> 00A4—OC8IP<2:0>—OC7IP<2:0> 00A6—————C2IP<2:0> 00A8—————LVDIP<2:0> 00B0—————ILR<3:0> u = uninitialized bit; — = unimplemented bit, read as ‘’0Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of rThese bits are not available in the dsPIC30F6011A and dsPIC30F6013A devices. TABLE SFR Name INTCON1 INTCON2 IFS0 IFS1 IFS2 IEC0 IEC1 IEC2 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC10 INTTREG Legend:Note1:2: DS70143E-page 50 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 6.0 FLASH PROGRAM MEMORY 6.2 Run-Time Self-Programming (RTSP) Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not RTSP is accomplished using TBLRD (table read) and intended to be a complete reference TBLWT (table write) instructions. source. For more information on the CPU, With RTSP, the user may erase program memory, 32 peripherals, register descriptions and instructions (96 bytes) at a time and can write program general device functionality, refer to the memory data, 32 instructions (96 bytes) at a time. “dsPIC30F Family Reference Manual” (DS70046). For more information on the 6.3 Table Instruction Operation device instruction set and programming, Summary refer to the “16-bit MCU and DSC Programmer’s Reference Manual” The TBLRDL and the TBLWTL instructions are used to (DS70157). read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in The dsPIC30F family of devices contains internal pro- Word or Byte mode. gram Flash memory for executing user code. There are two methods by which the user can program this The TBLRDH and TBLWTH instructions are used to read memory: or write to bits<23:16> of program memory. TBLRDH and TBLWTH can access program memory in Word or • Run-Time Self-Programming (RTSP) Byte mode. • In-Circuit Serial Programming™ (ICSP™) A 24-bit program memory address is formed using 6.1 In-Circuit Serial Programming bits<7:0> of the TBLPAG register and the Effective Address (EA) from a W register specified in the table (ICSP) instruction, as shown in Figure6-1. dsPIC30F devices can be serially programmed while in the end application circuit. This is simply done with two lines for Programming Clock and Programming Data (which are named PGC and PGD respectively), and three other lines for Power (VDD), Ground (VSS) and Master Clear (MCLR). this allows customers to manu- facture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. FIGURE 6-1: ADDRESSING FOR TABLE AND NVM REGISTERS 24 bits Using Program 0 Program Counter 0 Counter NVMADR Reg EA Using NVMADR 1/0 NVMADRU Reg Addressing 8 bits 16 bits Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 bits 16 bits Byte User/Configuration Select Space Select 24-bit EA © 2011 Microchip Technology Inc. DS70143E-page 51

dsPIC30F6011A/6012A/6013A/6014A 6.4 RTSP Operation 6.5 Control Registers The dsPIC30F Flash program memory is organized The four SFRs used to read and write the program into rows and panels. Each row consists of 32 instruc- Flash memory are: tions or 96 bytes. Each panel consists of 128 rows or • NVMCON 4K x 24 instructions. RTSP allows the user to erase one • NVMADR row (32 instructions) at a time and to program four instructions at one time. RTSP may be used to program • NVMADRU multiple program memory panels, but the table pointer • NVMKEY must be changed at each panel boundary. 6.5.1 NVMCON REGISTER Each panel of program memory contains write latches that hold 32 instructions of programming data. Prior to The NVMCON register controls which blocks are to be the actual programming operation, the write data must erased, which memory type is to be programmed and be loaded into the panel write latches. The data to be start of the programming cycle. programmed into the panel is loaded in sequential 6.5.2 NVMADR REGISTER order into the write latches: instruction 0, instruction 1, etc. The instruction words loaded must always be from The NVMADR register is used to hold the lower two a group of 32 boundary. bytes of the Effective Address. The NVMADR register captures the EA<15:0> of the last table instruction that The basic sequence for RTSP programming is to set up has been executed and selects the row to write. a table pointer, then do a series of TBLWT instructions to load the write latches. Programming is performed by 6.5.3 NVMADRU REGISTER setting the special bits in the NVMCON register. Four TBLWTL and four TBLWTH instructions are required to The NVMADRU register is used to hold the upper byte load the four instructions. If multiple panel program- of the Effective Address. The NVMADRU register cap- ming is required, the table pointer needs to be changed tures the EA<23:16> of the last table instruction that and the next set of multiple write latches written. has been executed. All of the table write operations are single word writes 6.5.4 NVMKEY REGISTER (2 instruction cycles) because only the table latches arewritten. A programming cycle is required for NVMKEY is a write only register that is used for write programming each row. protection. To start a programming or an erase sequence, the user must consecutively write 0x55 and The Flash program memory is readable, writable, and 0xAA to the NVMKEY register. Refer to Section6.6 erasable during normal operation over the entire VDD “Programming Operations” for further details. range. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. DS70143E-page 52 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 6.6 Programming Operations 4. Write 32 instruction words of data from data RAM “image” into the program Flash write A complete programming sequence is necessary for latches. programming or erasing the internal Flash in RTSP 5. Program 32 instruction words into program mode. A programming operation is nominally 2 msec in Flash. duration and the processor stalls (waits) until the oper- a) Set up NVMCON register for multi-word, ation is finished. Setting the WR bit (NVMCON<15>) program Flash, program, and set WREN starts the operation, and the WR bit is automatically bit. cleared when the operation is finished. b) Write 0x55 to NVMKEY. 6.6.1 PROGRAMMING ALGORITHM FOR c) Write 0xAA to NVMKEY. PROGRAM FLASH d) Set the WR bit. This will begin program The user can erase and program one row of program cycle. Flash memory at a time. The general process is: e) CPU will stall for duration of the program cycle. 1. Read one row of program Flash (32 instruction words) and store into data RAM as a data f) The WR bit is cleared by the hardware “image”. when program cycle ends. 2. Update the data image with the desired new 6. Repeat steps 1 through 5 as needed to program data. desired amount of program Flash memory. 3. Erase program Flash row. 6.6.2 ERASING A ROW OF PROGRAM a) Set up NVMCON register for multi-word, MEMORY program Flash, erase, and set WREN bit. b) Write address of row to be erased into Example6-1 shows a code sequence that can be used NVMADRU/NVMADR. to erase a row (32 instructions) of program memory. c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. e) Set the WR bit. This will begin erase cycle. f) CPU will stall for the duration of the erase cycle. g) The WR bit is cleared when erase cycle ends. EXAMPLE 6-1: ERASING A ROW OF PROGRAM MEMORY ; Setup NVMCON for erase operation, multi word write ; program memory selected, and writes enabled MOV #0x4041,W0 ; MOV W0 NVMCON ; Init NVMCON SFR , ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR),W0 ; MOV W0 NVMADRU ; Initialize PM Page Boundary SFR , MOV #tbloffset(PROG_ADDR),W0 ; Intialize in-page EA[15:0] pointer MOV W0, NVMADR ; Initialize NVMADR SFR DISI #5 ; Block all interrupts with priority <7 for ; next 5 instructions MOV #0x55,W0 MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted © 2011 Microchip Technology Inc. DS70143E-page 53

dsPIC30F6011A/6012A/6013A/6014A 6.6.3 LOADING WRITE LATCHES Example6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000,W0 ; MOV W0 TBLPAG ; Initialize PM Page Boundary SFR , MOV #0x6000,W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0,W2 ; MOV #HIGH_BYTE_0,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , ; 1st_program_word MOV #LOW_WORD_1,W2 ; MOV #HIGH_BYTE_1,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , ; 2nd_program_word MOV #LOW_WORD_2,W2 ; MOV #HIGH_BYTE_2,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , • • • ; 31st_program_word MOV #LOW_WORD_31,W2 ; MOV #HIGH_BYTE_31,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , Note: In Example6-2, the contents of the upper byte of W3 has no effect. 6.6.4 INITIATING THE PROGRAMMING executed, the user must wait for the programming time SEQUENCE until programming is complete. The two instructions following the start of the programming sequence For protection, the write initiate sequence for NVMKEY should be NOPs. must be used to allow any erase or program operation to proceed. After the programming command has been EXAMPLE 6-3: INITIATING A PROGRAMMING SEQUENCE DISI #5 ; Block all interrupts with priority <7 for ; next 5 instructions MOV #0x55,W0 ; MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted DS70143E-page 54 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 0 u u 0 0 u u 0 0 u u 0 0 u u 0 S 0 u u 0 T 0 u u 0 E 0 u u 0 S 0 u u 0 E All R 0000 uuuu 0000 0000 0 u 0 0 0 u 0 0 0 u 0 0 0 u 0 0 0 Bit 1 Bit 2 Bit > 0 6: > < 6 Bit 3 OGOP R<23:1 <7:0> R D Y Bit 4 P VMA KE N 5 Bit 6 Bit s. d > el Bit 7 — R<15:0 er bit fi D st 8 RI A gi Bit TW NVM — — of re 9 ns Bit — — — ptio Bit 10 — — — or descri Bit 11 — — — 0046) f (1)AP Bit 13Bit 12 WRERR— —— —— nted bit, read as ‘’0ence Manual” (DS7 GISTER M Bit 14 WREN — — — = unimplemeF Family Refer M RE Bit 15 WR — — ed bit; sPIC30 zd 1:NV Addr. 0760 0762 0764 0766 u = uninitialiRefer to the “ - BLE 6 e Name MCON MADR MADRU MKEY end:e1: A Fil V V V V egot T N N N N LN © 2011 Microchip Technology Inc. DS70143E-page 55

dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 56 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 7.0 DATA EEPROM MEMORY A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- Note: This data sheet summarizes features of sible for waiting for the appropriate duration of time this group ofdsPIC30F devices and is not before initiating another data EEPROM write/erase intended to be a complete reference operation. Attempting to read the data EEPROM while source. For more information on the CPU, a programming or erase operation is in progress results peripherals, register descriptions and in unspecified data. general device functionality, refer to the Control bit WR initiates write operations similar to pro- “dsPIC30F Family Reference Manual” gram Flash writes. This bit cannot be cleared, only set, (DS70046). For more information on the in software. They are cleared in hardware at the com- device instruction set and programming, pletion of the write operation. The inability to clear the refer to the “16-bit MCU and DSC WR bit in software prevents the accidental or Programmer’s Reference Manual” premature termination of a write operation. (DS70157). The WREN bit, when set, will allow a write operation. The Data EEPROM Memory is readable and writable On power-up, the WREN bit is clear. The WRERR bit is during normal operation over the entire VDD range. The set when a write operation is interrupted by a MCLR data EEPROM memory is directly mapped in the Reset or a WDT Time-out Reset during normal opera- program memory address space. tion. In these situations, following Reset, the user can check the WRERR bit and rewrite the location. The The four SFRs used to read and write the program address register NVMADR remains unchanged. Flash memory are used to access data EEPROM memory, as well. As described in Section6.5 “Control Note: Interrupt flag bit NVMIF in the IFS0 regis- Registers”, these registers are: ter is set when write is complete. It must • NVMCON be cleared in software. • NVMADR 7.1 Reading the Data EEPROM • NVMADRU • NVMKEY A TBLRD instruction reads a word at the current pro- The EEPROM data memory allows read and write of gram word address. This example uses W0 as a single words and 16-word blocks. When interfacing to pointer to data EEPROM. The result is placed in data memory, NVMADR in conjunction with the register W4 as shown in Example7-1. NVMADRU register are used to address the EEPROM location being accessed. TBLRDL and TBLWTL EXAMPLE 7-1: DATA EEPROM READ instructions are used to read and write data EEPROM. MOV #LOW_ADDR_WORD,W0 ; Init Pointer The dsPIC30F devices have up to 8 Kbytes (4K MOV #HIGH_ADDR_WORD,W1 words) of data EEPROM with an address range from MOV W1 TBLPAG , 0x7FF000 to 0x7FFFFE. TBLRDL [ W0 ], W4 ; read data EEPROM A word write operation should be preceded by an erase of the corresponding memory location(s). The write typ- ically requires 2 ms to complete but the write time will vary with voltage and temperature. © 2011 Microchip Technology Inc. DS70143E-page 57

dsPIC30F6011A/6012A/6013A/6014A 7.2 Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in the NVMCON register. Setting the WR bit initiates the erase as shown in Example7-2. EXAMPLE 7-2: DATA EEPROM BLOCK ERASE ; Select data EEPROM block, ERASE, WREN bits MOV #0x4045,W0 MOV W0 NVMCON ; Initialize NVMCON SFR , ; Start erase cycle by setting WR after writing key sequence DISI #5 ; Block all interrupts with priority <7 for ; next 5 instructions MOV #0x55,W0 ; MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Initiate erase sequence NOP NOP ; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete 7.2.2 ERASING A WORD OF DATA EEPROM The TBLPAG and NVMADR registers must point to the block. Select erase a block of data Flash, and set the ERASE and WREN bits in the NVMCON register. Set- ting the WR bit initiates the erase as shown in Example7-3. EXAMPLE 7-3: DATA EEPROM WORD ERASE ; Select data EEPROM word, ERASE, WREN bits MOV #0x4044,W0 MOV W0 NVMCON , ; Start erase cycle by setting WR after writing key sequence DISI #5 ; Block all interrupts with priority <7 for ; next 5 instructions MOV #0x55,W0 ; MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Initiate erase sequence NOP NOP ; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete DS70143E-page 58 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 7.3 Writing to the Data EEPROM The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to To write an EEPROM data location, the following NVMCON, then set WR bit) for each word. It is strongly sequence must be followed: recommended that interrupts be disabled during this 1. Erase data EEPROM word. codesegment. a) Select word, data EEPROM erase and set Additionally, the WREN bit in NVMCON must be set to WREN bit in NVMCON register. enable writes. This mechanism prevents accidental b) Write address of word to be erased into writes to data EEPROM due to unexpected code exe- NVMADR. cution. The WREN bit should be kept clear at all times c) Enable NVM interrupt (optional). except when updating the EEPROM. The WREN bit is not cleared byhardware. d) Write 0x55 to NVMKEY. e) Write 0xAA to NVMKEY. After a write sequence has been initiated, clearing the WREN bit will not affect the current write cycle. The WR f) Set the WR bit. This will begin erase cycle. bit will be inhibited from being set unless the WREN bit g) Either poll NVMIF bit or wait for NVMIF is set. The WREN bit must be set on a previous instruc- interrupt. tion. Both WR and WREN cannot be set with the same h) The WR bit is cleared when the erase cycle instruction. ends. At the completion of the write cycle, the WR bit is 2. Write data word into data EEPROM write cleared in hardware and the Non-Volatile Memory latches. Write Complete Interrupt Flag bit (NVMIF) is set. The 3. Program 1 data word into data EEPROM. user may either enable this interrupt or poll this bit. a) Select word, data EEPROM program and NVMIF must be cleared by software. set WREN bit in NVMCON register. 7.3.1 WRITING A WORD OF DATA b) Enable NVM write done interrupt (optional). EEPROM c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. Once the user has erased the word to be programmed, then a table write instruction is used to write one write e) Set the WR bit. This will begin program latch, as shown in Example7-4. cycle. f) Either poll NVMIF bit or wait for NVM interrupt. g) The WR bit is cleared when the write cycle ends. EXAMPLE 7-4: DATA EEPROM WORD WRITE ; Point to data memory MOV #LOW_ADDR_WORD,W0 ; Init pointer MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #LOW(WORD),W2 ; Get data TBLWTL W2 [ W0] ; Write data , ; The NVMADR captures last table access address ; Select data EEPROM for 1 word op MOV #0x4004,W0 MOV W0 NVMCON , ; Operate key to allow write operation DISI #5 ; Block all interrupts with priority <7 for ; next 5 instructions MOV #0x55,W0 MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Initiate program sequence NOP NOP ; Write cycle will complete in 2 ms. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2011 Microchip Technology Inc. DS70143E-page 59

dsPIC30F6011A/6012A/6013A/6014A 7.3.2 WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 ; Init pointer MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 ; Get 1st data TBLWTL W2 [ W0]++ ; write data , MOV #data2,W2 ; Get 2nd data TBLWTL W2 [ W0]++ ; write data , MOV #data3,W2 ; Get 3rd data TBLWTL W2 [ W0]++ ; write data , MOV #data4,W2 ; Get 4th data TBLWTL W2 [ W0]++ ; write data , MOV #data5,W2 ; Get 5th data TBLWTL W2 [ W0]++ ; write data , MOV #data6,W2 ; Get 6th data TBLWTL W2 [ W0]++ ; write data , MOV #data7,W2 ; Get 7th data TBLWTL W2 [ W0]++ ; write data , MOV #data8,W2 ; Get 8th data TBLWTL W2 [ W0]++ ; write data , MOV #data9,W2 ; Get 9th data TBLWTL W2 [ W0]++ ; write data , MOV #data10,W2 ; Get 10th data TBLWTL W2 [ W0]++ ; write data , MOV #data11,W2 ; Get 11th data TBLWTL W2 [ W0]++ ; write data , MOV #data12,W2 ; Get 12th data TBLWTL W2 [ W0]++ ; write data , MOV #data13,W2 ; Get 13th data TBLWTL W2 [ W0]++ ; write data , MOV #data14,W2 ; Get 14th data TBLWTL W2 [ W0]++ ; write data , MOV #data15,W2 ; Get 15th data TBLWTL W2 [ W0]++ ; write data , MOV #data16,W2 ; Get 16th data TBLWTL W2 [ W0]++ ; write data. The NVMADR captures last table access address. , MOV #0x400A,W0 ; Select data EEPROM for multi word op MOV W0 NVMCON ; Operate Key to allow program operation , DISI #5 ; Block all interrupts with priority <7 for ; next 5 instructions MOV #0x55,W0 MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Start write cycle NOP NOP 7.4 Write Verify 7.5 Protection Against Spurious Write Depending on the application, good programming There are conditions when the device may not want to practice may dictate that the value written to the mem- write to the data EEPROM memory. To protect against ory should be verified against the original value. This spurious EEPROM writes, various mechanisms have should be used in applications where excessive writes been built-in. On power-up, the WREN bit is cleared; can stress bits near the specification limit. also, the Power-up Timer prevents EEPROMwrite. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. DS70143E-page 60 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 8.0 I/O PORTS Any bit and its associated data and control registers that are not valid for a particular device will be dis- Note: This data sheet summarizes features of abled. That means the corresponding LATx and TRISx this group ofdsPIC30F devices and is not registers and the port pin will read as zeros. intended to be a complete reference When a pin is shared with another peripheral or func- source. For more information on the CPU, tion that is defined as an input only, it is nevertheless peripherals, register descriptions and regarded as a dedicated port because there is no general device functionality, refer to the other competing source of outputs. An example is the “dsPIC30F Family Reference Manual” INT4 pin. (DS70046). The format of the registers for PORTA are shown in All of the device pins (except VDD, VSS, MCLR and Table8-1. OSC1/CLKI) are shared between the peripherals and The TRISA (Data Direction Control) register controls the parallel I/O ports. the direction of the RA<7:0> pins, as well as the INTx All I/O input ports feature Schmitt Trigger inputs for pins and the VREF pins. The LATA register supplies improved noise immunity. data to the outputs and is readable/writable. Reading the PORTA register yields the state of the input pins, 8.1 Parallel I/O (PIO) Ports while writing the PORTA register modifies the contents of the LATA register. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as A parallel I/O (PIO) port that shares a pin with a periph- a general purpose output pin is disabled. The I/O pin eral is, in general, subservient to the peripheral. The may be read but the output driver for the parallel port bit peripheral’s output buffer data and control signals are will be disabled. If a peripheral is enabled but the provided to a pair of multiplexers. The multiplexers peripheral is not actively driving a pin, that pin may be select whether the peripheral or the associated port driven by a port. has ownership of the output data and control signals of the I/O pad cell. Figure8-2 shows how ports are shared All port pins have three registers directly associated with other peripherals and the associated I/O cell (pad) with the operation of the port pin. The Data Direction to which they are connected. Table8-2 through register (TRISx) determines whether the pin is an input Table8-9 show the formats of the registers for the or an output. If the data direction bit is a ‘1’, then the pin shared ports, PORTB through PORTG. is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx), read the latch. Note: The actual bits in use vary between Writes to the latch, write the latch (LATx). Reads from devices. the port (PORTx), read the port pins and writes to the port pins, write the latch (LATx). FIGURE 8-1: BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE Dedicated Port Module Read TRIS I/O Cell TRIS Latch Data Bus D Q WR TRIS CK Data Latch D Q I/O Pad WR LAT + CK WR Port Read LAT Read Port © 2011 Microchip Technology Inc. DS70143E-page 61

dsPIC30F6011A/6012A/6013A/6014A 8.2 Configuring Analog Port Pins When reading the Port register, all pins configured as analog input channels will read as cleared (a low level). The use of the ADPCFG and TRIS registers control the Pins configured as digital inputs will not convert an ana- operation of the ADC port pins. The port pins that are log input. Analog levels on any pin that is defined as a desired as analog inputs must have their correspond- digital input (including the ANx pins) may cause the ing TRIS bit set (input). If the TRIS bit is cleared (out- input buffer to consume current that exceeds the put), the digital output level (VOH or VOL) will be device specifications. converted. FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Cell Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data 0 Read TRIS I/O Pad Data Bus D Q WR TRIS CK TRIS Latch D Q WR LAT + CK WR Port Data Latch Read LAT Input Data Read Port DS70143E-page 62 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A Reset State 1111 0110 1100 0000 0000 0000 0000 0000 0000 0000 0000 0000 Reset State 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 Reset State 1110 0000 0000 0110 0000 0000 0000 0000 0000 0000 0000 0000 Reset State 1110 0000 0001 1110 0000 0000 0000 0000 0000 0000 0000 0000 Bit 0 — — — Bit 0 TRISB0 RB0 LATB0 Bit 0 — — — Bit 0 — — — Bit 1 — — — Bit 1 RISB1 RB1 ATB1 1 C1 1 C1 1 C1 1 C1 T L Bit RIS RC AT Bit RIS RC AT Bit 3Bit 2 —— —— —— Bit 3Bit 2 TRISB3TRISB2 RB3RB2 LATB3LATB2 3Bit 2 TRISC2T RC2 LATC2L 3Bit 2 C3TRISC2T 3RC2 C3LATC2L Bit 4 — — — Bit 4 TRISB4 RB4 LATB4 4Bit — — — 4Bit C4TRIS 4RC C4LAT Bit 5 — — — 1) Bit 5 TRISB5 RB5 LATB5 Bit — — — Bit TRIS RC LAT (1)8-1:PORTA REGISTER MAP FOR dsPIC30F6013A/6014A Addr.Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6 02C0TRISA15TRISA14TRISA13TRISA12—TRISA10TRISA9—TRISA7TRISA6 02C2RA15RA14RA13RA12—RA10RA9—RA7RA6 02C4LATA15LATA14LATA13LATA12—LATA10LATA9—LATA7LATA6 — = unimplemented bit, read as ‘’0Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.PORTA is not implemented in the dsPIC30F6011A/6012A devices. (8-2:PORTB REGISTER MAP FOR dsPIC30F6011A/6012A/6013A/6014A Addr.Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6 02C6TRISB15TRISB14TRISB13TRISB12TRISB11TRISB10TRISB9TRISB8TRISB7TRISB6 02C8RB15RB14RB13RB12RB11RB10RB9RB8RB7RB6 02CBLATB15LATB14LATB13LATB12LATB11LATB10LATB9LATB8LATB7LATB6 — = unimplemented bit, read as ‘’0Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. (1)8-3:PORTC REGISTER MAP FOR dsPIC30F6011A/6012A Addr.Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5 02CCTRISC15TRISC14TRISC13———————— 02CERC15RC14RC13———————— 02D0LATC15LATC14LATC13———————— — = unimplemented bit, read as ‘’0Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. (1)8-4:PORTC REGISTER MAP FOR dsPIC30F6013A/6014A Addr.Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5 02CCTRISC15TRISC14TRISC13———————— 02CERC15RC14RC13———————— 02D0LATC15LATC14LATC13———————— — = unimplemented bit, read as ‘’0Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. ABLE SFR Name RISA (2)ORTA ATA egend:ote1:2: ABLE SFR Name RISB ORTB ATB egend:ote1: ABLE SFR Name RISC ORTC ATC egend:ote1: ABLE SFR Name RISC ORTC ATC egend:ote1: T T P L LN T T P L LN T T P L LN T T P L LN © 2011 Microchip Technology Inc. DS70143E-page 63

dsPIC30F6011A/6012A/6013A/6014A 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 e 1 0 0 e 1 0 0 set Stat 11 111 00 000 00 000 set Stat 11 111 00 000 00 000 et State 0 0111 0 0000 0 0000 et State 1 1111 0 0000 0 0000 Re 11 00 00 Re 11 00 00 es 00 00 00 es 00 00 00 R 0 0 0 R 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 0 TRISD0 RD0 LATD0 Bit 0 TRISD0 RD0 LATD0 Bit 0 RISF0 RF0 ATF0 Bit 0 RISF0 RF0 ATF0 T L T L Bit 1 TRISD1 RD1 LATD1 Bit 1 TRISD1 RD1 LATD1 Bit 1 RISF1 RF1 ATF1 Bit 1 RISF1 RF1 ATF1 T L T L Bit 2 TRISD2 RD2 LATD2 Bit 2 TRISD2 RD2 LATD2 Bit 2 RISF2 RF2 ATF2 Bit 2 RISF2 RF2 ATF2 T L T L Bit 3 TRISD3 RD3 LATD3 Bit 3 TRISD3 RD3 LATD3 Bit 3 RISF3 RF3 ATF3 Bit 3 RISF3 RF3 ATF3 Bit 4 TRISD4 RD4 LATD4 Bit 4 TRISD4 RD4 LATD4 Bit 4 RISF4T RF4 ATF4L Bit 4 RISF4T RF4 ATF4L Bit 5 TRISD5 RD5 LATD5 Bit 5 TRISD5 RD5 LATD5 Bit 5 RISF5T RF5 ATF5L Bit 5 RISF5T RF5 ATF5L Bit 6 TRISD6 RD6 LATD6 Bit 6 TRISD6 RD6 LATD6 Bit 6 RISF6T RF6 ATF6L Bit 6 RISF6T RF6 ATF6L (1)EGISTER MAP FOR dsPIC30F6011A/6012A Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7 ——TRISD11TRISD10TRISD9TRISD8TRISD7 ——RD11RD10RD9RD8RD7 ——LATD11LATD10LATD9LATD8LATD7 = unimplemented bit, read as ‘’0Family Reference Manual” (DS70046) for descriptions of register bit fields. (1)EGISTER MAP FOR dsPIC30F6013A/6014A Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7 TRISD13TRISD12TRISD11TRISD10TRISD9TRISD8TRISD7 RD13RD12RD11RD10RD9RD8RD7 LATD13LATD12LATD11LATD10LATD9LATD8LATD7 = unimplemented bit, read as ‘’0Family Reference Manual” (DS70046) for descriptions of register bit fields. (1)EGISTER MAP FOR dsPIC30F6011A/6012A Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7 ———————T ——————— ———————L = unimplemented bit, read as ‘’0Family Reference Manual” (DS70046) for descriptions of register bit fields. (1)EGISTER MAP FOR dsPIC30F6013A/6014A Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7 —————TRISF8TRISF7T —————RF8RF7 —————LATF8LATF7L = unimplemented bit, read as ‘’0Family Reference Manual” (DS70046) for descriptions of register bit fields. RTD R Bit 14 — — — ed bit; — sPIC30F RTD R Bit 14 TRISD14 RD14 LATD14 ed bit; — sPIC30F RTF R Bit 14 — — — ed bit; — sPIC30F RTF R Bit 14 — — — ed bit; — sPIC30F TABLE 8-5:PO SFR Addr.Bit 15Name TRISD02D2— PORTD02D4— LATD02D6— Legend:u = uninitializNote1:Refer to the “d TABLE 8-6:PO SFR Addr.Bit 15Name TRISD02D2TRISD15 PORTD02D4RD15 LATD02D6LATD15 Legend:u = uninitializNote1:Refer to the “d TABLE 8-7:PO SFR Addr.Bit 15Name TRISF02DE— PORTF02E0— LATF02E2— Legend:u = uninitializNote1:Refer to the “d TABLE 8-8:PO SFR Addr.Bit 15Name TRISF02DE— PORTF02E0— LATF02E2— Legend:u = uninitializNote1:Refer to the “d DS70143E-page 64 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 1 0 0 1 0 0 1 0 0 1 0 0 e 0 0 0 Stat 110 000 000 et 1 0 0 s 1 0 0 e 0 0 0 R 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 G0 0 G0 Bit RIS RG AT T L 1 G1 1 G1 Bit RIS RG AT T L 2 G2 2 G2 Bit RIS RG AT T L 3 G3 3 G3 Bit RIS RG AT T L 4 Bit — — — 5 1) Bit — — — (4A 6 G6 6 G6 01 Bit RIS RG AT 6 T L 2A/6013A/ 8Bit 7 G8TRISG7 8RG7 G8LATG7 ster bit fields. 1A/601 9Bit G9TRIS 9RG G9LAT ons of regi 601 Bit TRIS RG LAT cripti F es PIC30 Bit 10 — — — 46) for d R ds Bit 11 — — — s ‘’0DS700 GISTER MAP FO Bit 13Bit 12 TRISG13TRISG12 RG13RG12 LATG13LATG12 nimplemented bit, read amily Reference Manual” ( TG RE Bit 14 TRISG14 RG14 LATG14 d bit; — = uPIC30F Fa OR 15 G15 15 G15 alizee “ds 9:P dr.Bit E4TRIS E6RG E8LAT u = uninitiRefer to th 8- Ad 02 02 02 ABLE SFR Name RISG ORTG ATG egend:ote1: T T P L LN © 2011 Microchip Technology Inc. DS70143E-page 65

dsPIC30F6011A/6012A/6013A/6014A 8.3 Input Change Notification Module The input change notification module provides the dsPIC30F devices the ability to generate interrupt requests to the processor, in response to a change of state on selected input pins. This module is capable of detecting input change of states even in Sleep mode, when the clocks are disabled. There are up to 24 exter- nal signals (CN0 through CN23) that may be selected (enabled) for generating an interrupt request on a change of state. TABLE 8-10: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F6011A/6012A (BITS 15-8)(1) SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset State Name CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE 0000 0000 0000 0000 CNEN2 00C2 — — — — — — — — 0000 0000 0000 0000 CNPU1 00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE 0000 0000 0000 0000 CNPU2 00C6 — — — — — — — — 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-11: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F6011A/6012A (BITS 7-0)(1) SFR Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State Name CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000 CNEN2 00C2 — — — — — CN18IE CN17IE CN16IE 0000 0000 0000 0000 CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000 CNPU2 00C6 — — — — — CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-12: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F6013A/6014A (BITS 15-8)(1) SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset State Name CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE 0000 0000 0000 0000 CNEN2 00C2 — — — — — — — — 0000 0000 0000 0000 CNPU1 00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE 0000 0000 0000 0000 CNPU2 00C6 — — — — — — — — 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-13: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F6013A/6014A (BITS 7-0)(1) SFR Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State Name CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000 CNEN2 00C2 CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 0000 0000 0000 CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000 CNPU2 00C6 CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. DS70143E-page 66 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 9.0 TIMER1 MODULE These Operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Note: This data sheet summarizes features of Figure9-1 presents a block diagram of the 16-bit this group ofdsPIC30F devices and is not Timer1 module. intended to be a complete reference source. For more information on the CPU, 16-bit Timer Mode: In the 16-bit Timer mode, the timer peripherals, register descriptions and increments on every instruction cycle up to a match general device functionality, refer to the value preloaded into the Period register PR1, then “dsPIC30F Family Reference Manual” resets to ‘0’ and continues to count. (DS70046). When the CPU goes into the Idle mode, the timer will stop incrementing unless the TSIDL (T1CON<13>) This section describes the 16-bit General Purpose bit=0. If TSIDL = 1, the timer module logic will resume Timer1 module and associated operational modes. the incrementing sequence upon termination of the Figure9-1 depicts the simplified block diagram of the CPU Idle mode. 16-bit Timer1 module. 16-bit Synchronous Counter Mode: In the 16-bit The following sections provide a detailed description Synchronous Counter mode, the timer increments on including setup and control registers, along with asso- the rising edge of the applied external clock signal ciated block diagrams for the operational modes of the which is synchronized with the internal phase clocks. timers. The timer counts up to a match value preloaded in PR1, The Timer1 module is a 16-bit timer which can serve as then resets to ‘0’ and continues. the time counter for the real-time clock, or operate as a When the CPU goes into the Idle mode, the timer will free-running interval timer/counter. The 16-bit timer has stop incrementing unless the respective TSIDL bit = 0. the following modes: If TSIDL = 1, the timer module logic will resume the • 16-bit Timer incrementing sequence upon termination of the CPU • 16-bit Synchronous Counter Idle mode. • 16-bit Asynchronous Counter 16-bit Asynchronous Counter Mode: In the 16-bit Further, the following operational characteristics are Asynchronous Counter mode, the timer increments on supported: every rising edge of the applied external clock signal. The timer counts up to a match value preloaded in PR1, • Timer gate operation then resets to ‘0’ and continues. • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes When the timer is configured for the Asynchronous • Interrupt on 16-bit Period register match or falling mode of operation and the CPU goes into the Idle edge of external gate signal mode, the timer will stop incrementing if TSIDL = 1. FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM PR1 Equal Comparator x 16 TSYNC 1 Sync TMR1 Reset 0 0 T1IF Event Flag 1 Q D TGATE E Q CK S AT TGATE C G T T TCKPS<1:0> TON 2 SOSCO/ T1CK 1 x Gate Prescaler LPOSCEN Sync 0 1 1, 8, 64, 256 SOSCI TCY 0 0 © 2011 Microchip Technology Inc. DS70143E-page 67

dsPIC30F6011A/6012A/6013A/6014A 9.1 Timer Gate Operation 9.4 Timer Interrupt The 16-bit timer can be placed in the Gated Time The 16-bit timer has the ability to generate an interrupt on Accumulation mode. This mode allows the internal TCY period match. When the timer count matches the Period to increment the respective timer when the gate input register, the T1IF bit is asserted and an interrupt will be signal (T1CK pin) is asserted high. Control bit TGATE generated if enabled. The T1IF bit must be cleared in (T1CON<6>) must be set to enable this mode. The software. The timer interrupt flag, T1IF, is located in the timer must be enabled (TON = 1) and the timer clock IFS0 Control register in the interrupt controller. source set to internal (TCS = 0). When the Gated Time Accumulation mode is enabled, When the CPU goes into the Idle mode, the timer will an interrupt will also be generated on the falling edge of stop incrementing unless TSIDL = 0. If TSIDL = 1, the the gate signal (at the end of the accumulation cycle). timer will resume the incrementing sequence upon Enabling an interrupt is accomplished via the respec- termination of the CPU Idle mode. tive timer interrupt enable bit, T1IE. The timer interrupt enable bit is located in the IEC0 Control register in the 9.2 Timer Prescaler interrupt controller. The input clock (FOSC/4 or external clock) to the 16-bit 9.5 Real-Time Clock Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256, selected by control bits TCKPS<1:0> (T1CON<5:4>). Timer1, when operating in Real-Time Clock (RTC) The prescaler counter is cleared when any of the mode, provides time of day and event time-stamping following occurs: capabilities. Key operational features of the RTC are: • A write to the TMR1 register • Operation from 32kHz LP oscillator • A write to the T1CON register • 8-bit prescaler • A device Reset, such as a POR and BOR • Low power However, if the timer is disabled (TON = 0), then the • Real-Time Clock interrupts timer prescaler cannot be reset since the prescaler These Operating modes are determined by setting the clock is halted. appropriate bit(s) in the T1CON Control register. The TMR1 register is not cleared when the T1CON register is written. It is cleared by writing to the TMR1 FIGURE 9-2: RECOMMENDED register. COMPONENTS FOR TIMER1 LP OSCILLATOR 9.3 Timer Operation During Sleep RTC Mode During CPU Sleep mode, the timer will operate if: C1 • The timer module is enabled (TON = 1) and SOSCI • The timer clock source is selected as external 32.768 kHz dsPIC30FXXXX (TCS = 1) and XTAL • The TSYNC bit (T1CON<2>) is asserted to a logic SOSCO ‘0’ which defines the external clock source as C2 R asynchronous. When all three conditions are true, the timer will con- tinue to count up to the Period register and be reset to 0x0000. C1 = C2 = 18 pF; R = 100K When a match between the timer and the Period regis- ter occurs, an interrupt can be generated if the respective timer interrupt enable bit is asserted. DS70143E-page 68 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal, up to the value specified in the Period register and is then reset to ‘0’. The TSYNC bit must be asserted to a logic ‘0’ (Asynchronous mode) for correct operation. Enabling the LPOSCEN bit (OSCCON<1>) will disable the normal Timer and Counter modes and enable a timer carry-out wake-up event. When the CPU enters Sleep mode, the RTC will con- tinue to operate provided the 32kHz external crystal oscillator is active and the control bits have not been changed. The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt will be generated if enabled. The T1IF bit must be cleared in software. The respective Timer interrupt flag, T1IF, is located in the IFS0 status register in the interrupt controller. Enabling an interrupt is accomplished via the respec- tive timer interrupt enable bit, T1IE. The timer interrupt enable bit is located in the IEC0 Control register in the interrupt controller. © 2011 Microchip Technology Inc. DS70143E-page 69

dsPIC30F6011A/6012A/6013A/6014A u 1 0 u 1 0 u 1 0 u 1 0 e u 1 0 Stat uuu 111 000 et u 1 0 s u 1 0 e u 1 0 R u 1 0 u 1 0 u 1 0 u 1 0 u 1 0 0 Bit — 1 S Bit TC C Bit 2 SYN T 3 Bit — 0 Bit 4 CKPS T 1 Bit 5 CKPS T E Bit 8Bit 7Bit 6 Timer1 Register Period Register 1 ——TGAT ns of register bit fields. o Bit 9 — escripti d Bit 10 — 46) for 0 0 (1)R MAP Bit 12Bit 11 —— nted bit, read as ‘’0ence Manual” (DS7 GISTE Bit 13 TSIDL nimplememily Refer 1:TIMER1 RE Addr.Bit 15Bit 14 0100 0102 0104TON— u = uninitialized bit; — = uRefer to the “dsPIC30F Fa - 9 e LE Nam N d:1: TAB SFR TMR1 PR1 T1CO LegenNote DS70143E-page 70 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 10.0 TIMER2/3 MODULE For 32-bit timer/counter operation, Timer2 is the lsw and Timer3 is the most significant word (msw) of the Note: This data sheet summarizes features of 32-bit timer. this group ofdsPIC30F devices and is not Note: For 32-bit timer operation, T3CON control intended to be a complete reference bits are ignored. Only T2CON control bits source. For more information on the CPU, are used for setup and control. Timer2 peripherals, register descriptions and gen- clock and gate inputs are utilized for the eral device functionality, refer to the 32-bit timer module but an interrupt is gen- “dsPIC30F Family Reference Manual” erated with the Timer3 interrupt flag (T3IF) (DS70046). and the interrupt is enabled with the This section describes the 32-bit General Purpose Timer3 interrupt enable bit (T3IE). Timer module (Timer2/3) and associated Operational 16-bit Timer Mode: In the 16-bit mode, Timer2 and modes. Figure10-1 depicts the simplified block dia- Timer3 can be configured as two independent 16-bit gram of the 32-bit Timer2/3 module. Figure10-2 and timers. Each timer can be set up in either 16-bit Timer Figure10-3 show Timer2/3 configured as two mode or 16-bit Synchronous Counter mode. See independent 16-bit timers, Timer2 and Timer3, Section9.0 “Timer1 Module”, Timer1 Module for respectively. details on these two Operating modes. The Timer2/3 module is a 32-bit timer (which can be The only functional difference between Timer2 and configured as two 16-bit timers) with selectable Timer3 is that Timer2 provides synchronization of the Operating modes. These timers are utilized by other clock prescaler output. This is useful for high frequency peripheral modules, such as: external clock inputs. • Input Capture 32-bit Timer Mode: In the 32-bit Timer mode, the timer • Output Compare/Simple PWM increments on every instruction cycle, up to a match The following sections provide a detailed description, value preloaded into the combined 32-bit Period including setup and control registers, along with asso- register PR3/PR2, then resets to ‘0’ and continues to ciated block diagrams for the Operational modes of the count. timers. For synchronous 32-bit reads of the Timer2/Timer3 The 32-bit timer has the following modes: pair, reading the lsw (TMR2 register) will cause the msw to be read and latched into a 16-bit holding regis- • Two independent 16-bit timers (Timer2 and ter, termed TMR3HLD. Timer3) with all 16-bit Operating modes (except Asynchronous Counter mode) For synchronous 32-bit writes, the holding register (TMR3HLD) must first be written to. When followed by • Single 32-bit timer operation a write to the TMR2 register, the contents of TMR3HLD • Single 32-bit synchronous counter will be transferred and latched into the MSB of the Further, the following operational characteristics are 32-bit timer (TMR3). supported: 32-bit Synchronous Counter Mode: In the 32-bit • ADC event trigger Synchronous Counter mode, the timer increments on • Timer gate operation the rising edge of the applied external clock signal • Selectable prescaler settings which is synchronized with the internal phase clocks. The timer counts up to a match value preloaded in the • Timer operation during Idle and Sleep modes combined 32-bit period register PR3/PR2, then resets • Interrupt on a 32-bit period register match to ‘0’ and continues. These Operating modes are determined by setting the When the timer is configured for the Synchronous appropriate bit(s) in the 16-bit T2CON and T3CON Counter mode of operation and the CPU goes into the SFRs. Idle mode, the timer will stop incrementing unless the the TSIDL bit (T2CON<13>) = 0. If TSIDL = 1, the timer module logic will resume the incrementing sequence upon termination of the CPU Idle mode. © 2011 Microchip Technology Inc. DS70143E-page 71

dsPIC30F6011A/6012A/6013A/6014A FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 16 Write TMR2 Read TMR2 16 Reset TMR3 TMR2 Sync MSB LSB ADC Event Trigger Comparator x 32 Equal PR3 PR2 0 T3IF Event Flag 1 Q D TGATE (T2CON<6>) Q CK TGATE (T2CON<6>) E S AT C G T T TCKPS<1:0> TON 2 T2CK 1 x Gate Prescaler Sync 0 1 1, 8, 64, 256 TCY 0 0 Note: Timer configuration bit T32 (T2CON<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70143E-page 72 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM PR2 Equal Comparator x 16 TMR2 Sync Reset 0 T2IF Event Flag 1 Q D TGATE Q CK TGATE E SAT CG TT TCKPS<1:0> TON 2 T2CK 1 x Gate Prescaler Sync 0 1 1, 8, 64, 256 TCY 0 0 FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM PR3 ADC Event Trigger Equal Comparator x 16 TMR3 Reset 0 T3IF Event Flag 1 Q D TGATE Q CK TGATE E S AT C G T T TCKPS<1:0> TON 2 T3CK Sync 1 x Prescaler 0 1 1, 8, 64, 256 TCY 0 0 © 2011 Microchip Technology Inc. DS70143E-page 73

dsPIC30F6011A/6012A/6013A/6014A 10.1 Timer Gate Operation 10.4 Timer Operation During Sleep Mode The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal TCY to During CPU Sleep mode, the timer will not operate increment the respective timer when the gate input sig- because the internal clocks are disabled. nal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in 10.5 Timer Interrupt this mode, Timer2 is the originating clock source. The TGATE setting is ignored for Timer3. The timer must be The 32-bit timer module can generate an interrupt on enabled (TON = 1) and the timer clock source set to period match or on the falling edge of the external gate internal (TCS = 0). signal. When the 32-bit timer count matches the respective 32-bit period register, or the falling edge of The falling edge of the external signal terminates the the external “gate” signal is detected, the T3IF bit count operation but does not reset the timer. The user (IFS0<7>) is asserted and an interrupt will be gener- must reset the timer in order to start counting from zero. ated if enabled. In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must 10.2 ADC Event Trigger be cleared in software. When a match occurs between the 32-bit timer (TMR3/ Enabling an interrupt is accomplished via the TMR2) and the 32-bit combined period register (PR3/ respective timer interrupt enable bit, T3IE (IEC0<7>). PR2), or between the 16-bit timer TMR3 and the 16-bit period register PR3, a special ADC trigger event signal is generated by Timer3. 10.3 Timer Prescaler The input clock (FOSC/4 or external clock) to the timer has a prescale option of 1:1, 1:8, 1:64 and 1:256, selected by control bits TCKPS<1:0> (T2CON<5:4> and T3CON<5:4>). For the 32-bit timer operation, the originating clock source is Timer2. The prescaler oper- ation for Timer3 is not applicable in this mode. The prescaler counter is cleared when any of the following occurs: • A write to the TMR2/TMR3 register • A write to the T2CON/T3CON register • A device Reset, such as a POR and BOR However, if the timer is disabled (TON = 0), then the Timer 2 prescaler cannot be reset since the prescaler clock is halted. TMR2/TMR3 is not cleared when T2CON/T3CON is written. DS70143E-page 74 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A u u u 1 1 0 0 u u u 1 1 0 0 u u u 1 1 0 0 u u u 1 1 0 0 e u u u 1 1 0 0 Stat uuu uuu uuu 111 111 000 000 et u u u 1 1 0 0 s u u u 1 1 0 0 e u u u 1 1 0 0 R u u u 1 1 0 0 u u u 1 1 0 0 u u u 1 1 0 0 u u u 1 1 0 0 u u u 1 1 0 0 0 Bit — — 1 S S Bit TC TC 2 Bit — — Bit 3 T32 — 0 0 Bit 4 CKPS CKPS T T y) Bit 5 ons onl CKPS1 CKPS1 ati T T Bit 8Bit 7Bit 6 Timer2 Register Register (for 32-bit timer oper Timer3 Register Period Register 2 Period Register 3 ——TGATE ——TGATE ns of register bit fields. ng ptio Bit 9 Holdi — — escri 0 er3 or d Bit 1 Tim — — 46) f 0 0 (1)ER MAP Bit 12Bit 11 —— —— nted bit, read as ‘’0ence Manual” (DS7 EGIST Bit 13 TSIDL TSIDL nimplememily Refer 0-1:TIMER2/3 R Addr.Bit 15Bit 14 0106 0108 010A 010C 010E 0110TON— 0112TON— u = uninitialized bit; — = uRefer to the “dsPIC30F Fa 1 ABLE FR Name MR2 MR3HLD MR3 R2 R3 2CON 3CON egend:ote1: T S T T T P P T T LN © 2011 Microchip Technology Inc. DS70143E-page 75

dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 76 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 11.0 TIMER4/5 MODULE • The Timer4/5 module does not support the ADC event trigger feature Note: This data sheet summarizes features of • Timer4/5 can not be utilized by other peripheral this group ofdsPIC30F devices and is not modules, such as input capture and intended to be a complete reference output compare source. For more information on the CPU, The Operating modes of the Timer4/5 module are peripherals, register descriptions and determined by setting the appropriate bit(s) in the general device functionality, refer to the 16-bit T4CON and T5CON SFRs. “dsPIC30F Family Reference Manual” (DS70046). For 32-bit timer/counter operation, Timer4 is the lsw and Timer5 is the msw of the 32-bit timer. This section describes the second 32-bit General Pur- pose Timer module (Timer4/5) and associated Opera- Note: For 32-bit timer operation, T5CON control tional modes. Figure11-1 depicts the simplified block bits are ignored. Only T4CON control bits diagram of the 32-bit Timer4/5 module. Figure11-2 and are used for setup and control. Timer4 Figure11-3 show Timer4/5 configured as two clock and gate inputs are utilized for the independent 16-bit timers, Timer4 and Timer5, 32-bit timer module but an interrupt is gen- respectively. erated with the Timer5 interrupt flag (T5IF) and the interrupt is enabled with the The Timer4/5 module is similar in operation to the Timer5 interrupt enable bit (T5IE). Timer2/3 module. However, there are some differences which are as follows: FIGURE 11-1: 32-BIT TIMER4/5 BLOCK DIAGRAM Data Bus<15:0> TMR5HLD 16 16 Write TMR4 Read TMR4 16 Reset TMR5 TMR4 Sync MSB LSB Comparator x 32 Equal PR5 PR4 0 T5IF Event Flag 1 Q D TGATE (T4CON<6>) Q CK TGATE (T4CON<6>) E T S A C G T T TCKPS<1:0> TON 2 T4CK 1 x Prescaler Gate 0 1 1, 8, 64, 256 Sync TCY 0 0 Note: Timer configuration bit T32 (T4CON<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T4CON register. © 2011 Microchip Technology Inc. DS70143E-page 77

dsPIC30F6011A/6012A/6013A/6014A FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM PR4 Equal Comparator x 16 TMR4 Sync Reset 0 T4IF Event Flag 1 Q D TGATE Q CK TGATE E S AT C G T T TCKPS<1:0> TON 2 T4CK 1 x Gate Prescaler Sync 0 1 1, 8, 64, 256 TCY 0 0 FIGURE 11-3: 16-BIT TIMER5 BLOCK DIAGRAM PR5 ADC Event Trigger Equal Comparator x 16 TMR5 Reset 0 T5IF Event Flag 1 Q D TGATE Q CK TGATE E T S A C G T T TCKPS<1:0> TON 2 T5CK Sync 1 x Prescaler 0 1 1, 8, 64, 256 TCY 0 0 Note: In the dsPIC30F6011A and dsPIC30F6012A devices, there is no T5CK pin. Therefore, in this device the following modes should not be used for Timer5: TCS = 1 (16-bit Counter) TCS = 0, TGATE = 1 (Gated Time Accumulation) DS70143E-page 78 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A u u u 1 1 0 0 u u u 1 1 0 0 u u u 1 1 0 0 u u u 1 1 0 0 e u u u 1 1 0 0 Stat uuu uuu uuu 111 111 000 000 et u u u 1 1 0 0 s u u u 1 1 0 0 e u u u 1 1 0 0 R u u u 1 1 0 0 u u u 1 1 0 0 u u u 1 1 0 0 u u u 1 1 0 0 u u u 1 1 0 0 0 Bit — — 1 S S Bit TC TC 2 Bit — — Bit 3 T32 — 0 0 Bit 4 CKPS CKPS T T Bit 5 ns only) CKPS1 CKPS1 o T T ati Bit 8Bit 7Bit 6 Timer 4 Register ding Register (for 32-bit oper Timer 5 Register Period Register 4 Period Register 5 ——TGATE ——TGATE ns of register bit fields. Bit 10Bit 9 Timer 5 Hol —— —— 6) for descriptio 4 0 0 (1)ER MAP Bit 12Bit 11 —— —— nted bit, read as ‘’0ence Manual” (DS7 GIST Bit 13 TSIDL TSIDL mplemey Refer 5 RE Bit 14 — — — = uniF Famil -1:TIMER4/ Addr.Bit 15 0114 0116 0118 011A 011C 011ETON 0120TON u = uninitialized bit; Refer to the “dsPIC30 1 1 e LE Nam HLD N N d:1: AB SFR MR4 MR5 MR5 R4 R5 4CO 5CO egenote T T T T P P T T LN © 2011 Microchip Technology Inc. DS70143E-page 79

dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 80 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 12.0 INPUT CAPTURE MODULE These Operating modes are determined by setting the appropriate bits in the ICxCON register (where Note: This data sheet summarizes features of x=1,2,...,N). The dsPIC DSC devices contain up to 8 this group ofdsPIC30F devices and is not capture channels (i.e., the maximum value of N is 8). intended to be a complete reference source. For more information on the CPU, 12.1 Simple Capture Event Mode peripherals, register descriptions and general device functionality, refer to the The simple capture events in the dsPIC30F product “dsPIC30F Family Reference Manual” family are: (DS70046). • Capture every falling edge • Capture every rising edge This section describes the input capture module and associated Operational modes. The features provided • Capture every 4th rising edge by this module are useful in applications requiring fre- • Capture every 16th rising edge quency (period) and pulse measurement. Figure12-1 • Capture every rising and falling edge depicts a block diagram of the input capture module. These simple Input Capture modes are configured by Input capture is useful for such modes as: setting the appropriate bits ICM<2:0> (ICxCON<2:0>). • Frequency/Period/Pulse Measurements • Additional Sources of External Interrupts 12.1.1 CAPTURE PRESCALER The key operational features of the input capture There are four input capture prescaler settings speci- module are: fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the capture channel is turned off, the prescaler counter will • Simple Capture Event mode be cleared. In addition, any Reset will clear the • Timer2 and Timer3 mode selection prescaler counter. • Interrupt on input capture event FIGURE 12-1: INPUT CAPTURE MODE BLOCK DIAGRAM From General Purpose Timer Module T2_CNT T3_CNT 16 16 ICTMR ICx pin 1 0 Prescaler Clock Edge FIFO 1, 4, 16 Synchronizer Detection R/W Logic Logic 3 ICM<2:0> ICxBUF Mode Select ICBNE, ICOV ICI<1:0> Interrupt ICxCON Logic Data Bus SSeett FFllaagg IICCxxIIFF Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2011 Microchip Technology Inc. DS70143E-page 81

dsPIC30F6011A/6012A/6013A/6014A 12.1.2 CAPTURE BUFFER OPERATION 12.2 Input Capture Operation During Sleep and Idle Modes Each capture channel has an associated FIFO buffer which is four 16-bit words deep. There are two status An input capture event will generate a device wake-up flags which provide status on the FIFO buffer: or interrupt, if enabled, if the device is in CPU Idle or • ICBFNE – Input Capture Buffer Not Empty Sleep mode. • ICOV – Input Capture Overflow Independent of the timer being enabled, the input cap- The ICBFNE will be set on the first input capture event ture module will wake-up from the CPU Sleep or Idle and remain set until all capture events have been read mode when a capture event occurs if ICM<2:0> = 111 from the FIFO. As each word is read from the FIFO, the and the interrupt enable bit is asserted. The same wake- remaining words are advanced by one position within up can generate an interrupt if the conditions for pro- the buffer. cessing the interrupt have been satisfied. The wake-up feature is useful as a method of adding extra external pin In the event that the FIFO is full with four capture interrupts. events and a fifth capture event occurs prior to a read of the FIFO, an overflow condition will occur and the 12.2.1 INPUT CAPTURE IN CPU SLEEP ICOV bit will be set to a logic ‘1’. The fifth capture event MODE is lost and is not stored in the FIFO. No additional events will be captured until all four events have been CPU Sleep mode allows input capture module opera- read from the buffer. tion with reduced functionality. In the CPU Sleep mode, the ICI<1:0> bits are not applicable and the input cap- If a FIFO read is performed after the last read and no ture module can only function as an external interrupt new capture event has been received, the read will source. yield indeterminate results. The capture module must be configured for interrupt 12.1.3 TIMER2 AND TIMER3 SELECTION only on rising edge (ICM<2:0> = 111) in order for the MODE input capture module to be used while the device is in Sleep mode. The prescale settings of 4:1 or 16:1 are The input capture module consists of up to 8 input cap- not applicable in this mode. ture channels. Each channel can select between one of two timers for the time base, Timer2 or Timer3. 12.2.2 INPUT CAPTURE IN CPU IDLE Selection of the timer resource is accomplished MODE through SFR bit, ICTMR (ICxCON<7>). Timer3 is the CPU Idle mode allows input capture module operation default timer resource available for the input capture with full functionality. In the CPU Idle mode, the Inter- module. rupt mode selected by the ICI<1:0> bits is applicable, 12.1.4 HALL SENSOR MODE as well as the 4:1 and 16:1 capture prescale settings which are defined by control bits ICM<2:0>. This mode When the input capture module is set for capture on requires the selected timer to be enabled. Moreover, every edge, rising and falling, ICM<2:0> = 001, the fol- the ICSIDL bit must be asserted to a logic ‘0’. lowing operations are performed by the input capture If the input capture module is defined as logic: ICM<2:0>=111 in CPU Idle mode, the input capture • The input capture interrupt flag is set on every pin will serve only as an external interrupt pin. edge, rising and falling. • The interrupt on Capture mode setting bits, 12.3 Input Capture Interrupts ICI<1:0>, is ignored since every capture generates an interrupt. The input capture channels have the ability to generate an interrupt based upon the selected number of cap- • A capture overflow condition is not generated in ture events. The selection number is set by control bits this mode. ICI<1:0> (ICxCON<6:5>). Each channel provides an interrupt flag (ICxIF) bit. The respective capture channel interrupt flag is located in the corresponding IFSx status register. Enabling an interrupt is accomplished via the respec- tive capture channel interrupt enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC control register. DS70143E-page 82 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 e u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 Stat uuu 000 uuu 000 uuu 000 uuu 000 uuu 000 uuu 000 uuu 000 uuu 000 et u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 s u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 e u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 R u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 u 0 0 Bit > > > > > > > > Bit 1 M<2:0 M<2:0 M<2:0 M<2:0 M<2:0 M<2:0 M<2:0 M<2:0 C C C C C C C C I I I I I I I I 2 Bit E E E E E E E E Bit 3 CBN CBN CBN CBN CBN CBN CBN CBN I I I I I I I I 4 V V V V V V V V Bit CO CO CO CO CO CO CO CO I I I I I I I I 5 Bit 0> 0> 0> 0> 0> 0> 0> 0> 1: 1: 1: 1: 1: 1: 1: 1: < < < < < < < < 6 CI CI CI CI CI CI CI CI Bit I I I I I I I I 8Bit 7 pture Register ICTMR pture Register ICTMR pture Register ICTMR pture Register ICTMR pture Register ICTMR pture Register ICTMR pture Register ICTMR pture Register ICTMR er bit fields. Bit 1 Ca — 2 Ca — 3 Ca — 4 Ca — 5 Ca — 6 Ca — 7 Ca — 8 Ca — egist Bit 9 Input — Input — Input — Input — Input — Input — Input — Input — ptions of r cri s e 0 d (1)P Bit 1 — — — — — — — — 46) for URE REGISTER MA Bit 13Bit 12Bit 11 ICSIDL—— ICSIDL—— ICSIDL—— ICSIDL—— ICSIDL—— ICSIDL—— ICSIDL—— ICSIDL—— mplemented bit, read as ‘’0y Reference Manual” (DS700 T nimil NPUT CAP Bit 15Bit 14 —— —— —— —— —— —— —— —— alized bit; — = ue “dsPIC30F Fa -1:I Addr. 0140 0142 0144 0146 0148 014A 014C 014E 0150 0152 0154 0156 0158 015A 015C 015E u = uninitiRefer to th 2 1 e BLE R Nam BUF CON BUF CON BUF CON BUF CON BUF CON BUF CON BUF CON BUF CON end:e1: TA SF IC1 IC1 IC2 IC2 IC3 IC3 IC4 IC4 IC5 IC5 IC6 IC6 IC7 IC7 IC8 IC8 LegNot © 2011 Microchip Technology Inc. DS70143E-page 83

dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 84 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 13.0 OUTPUT COMPARE MODULE The key operational features of the output compare module include: Note: This data sheet summarizes features of • Timer2 and Timer3 Selection mode this group ofdsPIC30F devices and is not • Simple Output Compare Match mode intended to be a complete reference source. For more information on the CPU, • Dual Output Compare Match mode peripherals, register descriptions and • Simple PWM mode general device functionality, refer to the • Output Compare During Sleep and Idle modes “dsPIC30F Family Reference Manual” • Interrupt on Output Compare/PWM Event (DS70046). These Operating modes are determined by setting the This section describes the output compare module and appropriate bits in the 16-bit OCxCON SFR (where associated operational modes. The features provided x=1,2,3,...,N). The dsPIC DSC devices contain up to by this module are useful in applications requiring oper- 8 compare channels (i.e., the maximum value of N is 8). ational modes, such as: OCxRS and OCxR in Figure13-1 represent the Dual • Generation of Variable Width Output Pulses Compare registers. In the Dual Compare mode, the • Power Factor Correction OCxR register is used for the first compare and OCxRS is used for the second compare. Figure13-1 depicts a block diagram of the output compare module. FIGURE 13-1: OUTPUT COMPARE MODE BLOCK DIAGRAM Set Flag bit OCxIF OCxRS OCxR Output S Q Logic R OCx Output 3 Enable OCM<2:0> Mode Select Comparator OCTSEL OCFA 0 1 0 1 (for x = 1, 2, 3 or 4) or OCFB (for x = 5, 6, 7 or 8) From General Purpose Timer Module TMR2<15:0 TMR3<15:0> T2P2_MATCH T3P3_MATCH Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. © 2011 Microchip Technology Inc. DS70143E-page 85

dsPIC30F6011A/6012A/6013A/6014A 13.1 Timer2 and Timer3 Selection Mode 13.3.2 CONTINUOUS PULSE MODE Each output compare channel can select between one For the user to configure the module for the generation of two 16-bit timers, Timer2 or Timer3. of a continuous stream of output pulses, the following steps are required: The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource 1. Determine instruction cycle time TCY. for the output compare module. 2. Calculate desired pulse value based on TCY. 3. Calculate timer to start pulse width from timer 13.2 Simple Output Compare Match start value of 0x0000. Mode 4. Write pulse width start and stop times into OCxR and OCxRS (x denotes channel 1, 2, ...,N) When control bits OCM<2:0> (OCxCON<2:0>) = 001, Compare registers, respectively. 010 or 011, the selected output compare channel is 5. Set Timer Period register to value equal to, or configured for one of three simple Output Compare greater than value in OCxRS Compare register. Match modes: 6. Set OCM<2:0> = 101. • Compare forces I/O pin low 7. Enable timer, TON (TxCON<15>) = 1. • Compare forces I/O pin high • Compare toggles I/O pin 13.4 Simple PWM Mode The OCxR register is used in these modes. The OCxR When control bits OCM<2:0> (OCxCON<2:0>) = 110 register is loaded with a value and is compared to the or 111, the selected output compare channel is config- selected incrementing timer count. When a compare ured for the PWM mode of operation. When configured occurs, one of these Compare Match modes occurs. If for the PWM mode of operation, OCxR is the main latch the counter resets to zero before reaching the value in (read only) and OCxRS is the secondary latch. This OCxR, the state of the OCx pin remains unchanged. enables glitchless PWM transitions. 13.3 Dual Output Compare Match Mode The user must perform the following steps in order to configure the output compare module for PWM When control bits OCM<2:0> (OCxCON<2:0>) = 100 operation: or 101, the selected output compare channel is config- 1. Set the PWM period by writing to the appropriate ured for one of two Dual Output Compare modes, period register. which are: 2. Set the PWM duty cycle by writing to the OCxRS • Single Output Pulse mode register. • Continuous Output Pulse mode 3. Configure the output compare module for PWM operation. 13.3.1 SINGLE PULSE MODE 4. Set the TMRx prescale value and enable the For the user to configure the module for the generation Timer, TON (TxCON<15>) = 1. of a single output pulse, the following steps are required (assuming timer is off): 13.4.1 INPUT PIN FAULT PROTECTION FOR PWM 1. Determine instruction cycle time TCY. 2. Calculate desired pulse width value based on When control bits OCM<2:0> (OCxCON<2:0>) = 111, TCY. the selected output compare channel is again config- 3. Calculate time to start pulse from timer start ured for the PWM mode of operation with the additional value of 0x0000. feature of input Fault protection. While in this mode, if a logic ‘0’ is detected on the OCFA/B pin, the respective 4. Write pulse width start and stop times into OCxR PWM output pin is placed in the high-impedance input and OCxRS Compare registers (x denotes state. The OCFLT bit (OCxCON<4>) indicates whether channel 1, 2, ...,N). a Fault condition has occurred. This state will be main- 5. Set Timer Period register to value equal to, or tained until both of the following events have occurred: greater than value in OCxRS Compare register. • The external Fault condition has been removed. 6. Set OCM<2:0> = 100. • The PWM mode has been re-enabled by writing 7. Enable timer, TON (TxCON<15>) = 1. to the appropriate control bits. To initiate another single pulse, issue another write to set OCM<2:0> = 100. DS70143E-page 86 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 13.4.2 PWM PERIOD When the selected TMRx is equal to its respective period register, PRx, the following four events occur on The PWM period is specified by writing to the PRx the next increment cycle: register. The PWM period can be calculated using Equation13-1. • TMRx is cleared • The OCx pin is set EQUATION 13-1: - Exception 1: If PWM duty cycle is 0x0000, the OCx pin will remain low PWM period = [(PRx) + 1] • 4 • TOSC • - Exception 2: If duty cycle is greater than PRx, (TMRx prescale value) the pin will remain high • The PWM duty cycle is latched from OCxRS into PWM frequency is defined as 1/[PWM period]. OCxR • The corresponding timer interrupt flag is set See Figure13-2 for key PWM period comparisons. Timer3 is referred to in Figure13-2 for clarity. FIGURE 13-2: PWM OUTPUT TIMING Period Duty Cycle TMR3 = PR3 TMR3 = PR3 T3IF = 1 T3IF = 1 (Interrupt Flag) (Interrupt Flag) OCxR = OCxRS OCxR = OCxRS TMR3 = Duty Cycle TMR3 = Duty Cycle (OCxR) (OCxR) © 2011 Microchip Technology Inc. DS70143E-page 87

dsPIC30F6011A/6012A/6013A/6014A 13.5 Output Compare Operation During 13.7 Output Compare Interrupts CPU Sleep Mode The output compare channels have the ability to gener- When the CPU enters Sleep mode, all internal clocks ate an interrupt on a compare match, for whichever are stopped. Therefore, when the CPU enters the Match mode has been selected. Sleep state, the output compare channel will drive the For all modes except the PWM mode, when a compare pin to the active state that was observed prior to event occurs, the respective interrupt flag (OCxIF) is entering the CPU Sleep state. asserted and an interrupt will be generated if enabled. For example, if the pin was high when the CPU entered The OCxIF bit is located in the corresponding IFS the Sleep state, the pin will remain high. Likewise, if the status register and must be cleared in software. The pin was low when the CPU entered the Sleep state, the interrupt is enabled via the respective compare inter- pin will remain low. In either case, the output compare rupt enable (OCxIE) bit located in the corresponding module will resume operation when the device wakes IEC control register. up. For the PWM mode, when an event occurs, the respec- tive timer interrupt flag (T2IF or T3IF) is asserted and 13.6 Output Compare Operation During an interrupt will be generated if enabled. The IF bit is CPU Idle Mode located in the IFS0 status register and must be cleared in software. The interrupt is enabled via the respective When the CPU enters the Idle mode, the output timer interrupt enable bit (T2IE or T3IE) located in the compare module can operate with full functionality. IEC0 control register. The output compare interrupt flag The output compare channel will operate during the is never set during the PWM mode of operation. CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at logic ‘0’ and the selected time base (Timer2 or Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. DS70143E-page 88 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Stat 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit > > > > > > > > 0 0 0 0 0 0 0 0 1 2: 2: 2: 2: 2: 2: 2: 2: Bit M< M< M< M< M< M< M< M< C C C C C C C C O O O O O O O O 2 Bit Bit 3 CTSEL CTSE CTSEL CTSEL CTSEL CTSEL CTSEL CTSEL O O O O O O O O T T T T T T T T 4 L L L L L L L L Bit CF CF CF CF CF CF CF CF O O O O O O O O 5 Bit er — er — er — er — er — er — er — er — 1) Bit 9Bit 8Bit 7Bit 6 Output Compare 1 Secondary Regist Output Compare 1 Main Register ———— Output Compare 2 Secondary Regist Output Compare 2 Main Register ———— Output Compare 3 Secondary Regist Output Compare 3 Main Register ———— Output Compare 4 Secondary Regist Output Compare 4 Main Register ———— Output Compare 5 Secondary Regist Output Compare 5 Main Register ———— Output Compare 6 Secondary Regist Output Compare 6 Main Register ———— Output Compare 7 Secondary Regist Output Compare 7 Main Register ———— Output Compare 8 Secondary Regist Output Compare 8 Main Register ———— descriptions of register bit fields. (P or COMPARE REGISTER MA 4Bit 13Bit 12Bit 11Bit 10 OCSIDL——— OCSIDL——— OCSIDL——— OCSIDL——— OCSIDL——— OCSIDL——— OCSIDL——— OCSIDL——— = unimplemented bit, read as ‘’0Family Reference Manual” (DS70046) f PUT Bit 1 — — — — — — — — d bit; — PIC30F T 5 es -1:OU Addr.Bit 1 0180 0182 0184— 0186 0188 018A— 018C 018E 0190— 0192 0194 0196— 0198 019A 019C— 019E 01A0 01A2— 01A4 01A6 01A8— 01AA 01AC 01AE— u = uninitializRefer to the “d 3 TABLE 1 SFR Name OC1RS OC1R OC1CON OC2RS OC2R OC2CON OC3RS OC3R OC3CON OC4RS OC4R OC4CON OC5RS OC5R OC5CON OC6RS OC6R OC6CON OC7RS OC7R OC7CON OC8RS OC8R OC8CON Legend:Note1: © 2011 Microchip Technology Inc. DS70143E-page 89

dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 90 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 14.0 SPI™ MODULE Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer Note: This data sheet summarizes features of is completed, the contents of the shift register (SPIxSR) this group ofdsPIC30F devices and is not are moved to the receive buffer. If any transmit data has intended to be a complete reference been written to the buffer register, the contents of the source. For more information on the CPU, transmit buffer are moved to SPIxSR. The received peripherals, register descriptions and data is thus placed in SPIxBUF and the transmit data in general device functionality, refer to the SPIxSR is ready for the next transfer. “dsPIC30F Family Reference Manual” Note: Both the transmit buffer (SPIxTXB) and (DS70046). the receive buffer (SPIxRXB) are mapped The Serial Peripheral Interface (SPI™) module is a to the same register address, SPIxBUF. synchronous serial interface. It is useful for communi- In Master mode, the clock is generated by prescaling cating with other peripheral devices, such as the system clock. Data is transmitted as soon as a EEPROMs, shift registers, display drivers and A/D con- value is written to SPIxBUF. The interrupt is generated verters, or other microcontrollers. It is compatible with at the middle of the transfer of the last bit. Motorola's SPI and SIOP interfaces. In Slave mode, data is transmitted and received as external clock pulses appear on SCK. Again, the inter- 14.1 Operating Function Description rupt is generated when the last bit is latched. If SSx Each SPI module consists of a 16-bit shift register, control is enabled, then transmission and reception are SPIxSR (where x = 1 or 2), used for shifting data in and enabled only when SSx = low. The SDOx output will be out, and a buffer register, SPIxBUF. A control register, disabled in SSx mode with SSx high. SPIxCON, configures the module. Additionally, a status The clock provided to the module is (FOSC/4). This register, SPIxSTAT, indicates various status conditions. clock is then prescaled by the primary (PPRE<1:0>) The serial interface consists of 4 pins: SDIx (serial data and the secondary (SPRE<2:0>) prescale factors. The input), SDOx (serial data output), SCKx (shift clock CKE bit determines whether transmit occurs on transi- input or output), and SSx (active-low slave select). tion from active clock state to Idle clock state, or vice versa. The CKP bit selects the Idle state (high or low) In Master mode operation, SCK is a clock output but in for the clock. Slave mode, it is a clock input. A series of eight (8) or sixteen (16) clock pulses shift 14.1.1 WORD AND BYTE out bits from the SPIxSR to SDOx pin and simultane- COMMUNICATION ously shift in data from SDIx pin. An interrupt is gener- A control bit, MODE16 (SPIxCON<10>), allows the ated when the transfer is complete and the module to communicate in either 16-bit or 8-bit mode. corresponding interrupt flag bit (SPI1IF or SPI2IF) is 16-bit operation is identical to 8-bit operation except set. This interrupt can be disabled through an interrupt that the number of bits transmitted is 16 instead of 8. enable bit (SPI1IE or SPI2IE). The user software must disable the module prior to The receive operation is double-buffered. When a com- changing the MODE16 bit. The SPI module is reset plete byte is received, it is transferred from SPIxSR to when the MODE16 bit is changed by the user. SPIxBUF. A basic difference between 8-bit and 16-bit operation is If the receive buffer is full when new data is being trans- that the data is transmitted out of bit 7 of the SPIxSR for ferred from SPIxSR to SPIxBUF, the module will set the 8-bit operation, and data is transmitted out of bit15 of SPIROV bit indicating an overflow condition. The trans- the SPIxSR for 16-bit operation. In both modes, data is fer of the data from SPIxSR to SPIxBUF will not be shifted into bit 0 of the SPIxSR. completed and the new data will be lost. The module will not respond to SCL transitions while SPIROV is ‘1’, 14.1.2 SDOx DISABLE effectively disabling the module until SPIxBUF is read by user software. A control bit, DISSDO, is provided to the SPIxCON reg- ister to allow the SDOx output to be disabled. This will allow the SPI module to be connected in an input only configuration. SDO can also be used for general purpose I/O. © 2011 Microchip Technology Inc. DS70143E-page 91

dsPIC30F6011A/6012A/6013A/6014A 14.2 Framed SPI Support pin is an input or an output (i.e., whether the module receives or generates the frame synchronization The module supports a basic framed SPI protocol in pulse). The frame pulse is an active-high pulse for a Master or Slave mode. The control bit FRMEN enables single SPI clock cycle. When frame synchronization is framed SPI support and causes the SSx pin to perform enabled, the data transmission starts only on the the frame synchronization pulse (FSYNC) function. subsequent transmit edge of the SPI clock. The control bit SPIFSD determines whether the SSx FIGURE 14-1: SPI BLOCK DIAGRAM Internal Data Bus Read Write SPIxBUF SPIxBUF Receive Transmit SPIxSR SDIx bit 0 SDOx Shift Clock SS and FSYNC Clock Edge Control Select Control SSx Secondary Primary Prescaler Prescaler FCY 1:1 – 1:8 1, 4, 16, 64 SCKx Enable Master Clock Note: x = 1 or 2. FIGURE 14-2: SPI MASTER/SLAVE CONNECTION SPI Master SPI Slave SDOx SDIy Serial Input Buffer Serial Input Buffer (SPIxBUF) (SPIyBUF) SDIx SDOy Shift Register Shift Register (SPIxSR) (SPIySR) MSb LSb MSb LSb Serial Clock SCKx SCKy PROCESSOR 1 PROCESSOR 2 Note: x = 1 or 2, y = 1 or 2. DS70143E-page 92 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 14.3 Slave Select Synchronization 14.5 SPI Operation During CPU Idle Mode The SSx pin allows a Synchronous Slave mode. The SPI must be configured in SPI Slave mode with SSx pin When the device enters Idle mode, all clock sources control enabled (SSEN = 1). When the SSx pin is low, remain functional. The SPISIDL bit (SPIxSTAT<13>) transmission and reception are enabled and the SDOx selects if the SPI module will stop or continue on Idle. If pin is driven. When SSx pin goes high, the SDOx pin is SPISIDL = 0, the module will continue to operate when no longer driven. Also, the SPI module is re- the CPU enters Idle mode. If SPISIDL = 1, the module synchronized, and all counters/control circuitry are will stop when the CPU enters Idle mode. reset. Therefore, when the SSx pin is asserted low again, transmission/reception will begin at the MSb even if SSx had been deasserted in the middle of a transmit/receive. 14.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shutdown. If the CPU enters Sleep mode while an SPI transaction is in progress, then the transmission and reception is aborted. The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2011 Microchip Technology Inc. DS70143E-page 93

dsPIC30F6011A/6012A/6013A/6014A Reset State 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Reset State 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Bit 0 SPIRBF PPRE0 Bit 0 SPIRBF PPRE0 Bit 1 SPITBF PPRE1 Bit 1 SPITBF PPRE1 Bit 2 — PRE0 Bit 2 — PRE0 S S 1 1 3 E 3 E Bit — PR Bit — PR S S Bit 4 — SPRE2 Bit 4 — SPRE2 Bit 5 — MSTEN Bit 5 — MSTEN Bit 9Bit 8Bit 7Bit 6 ———SPIROV SMPCKESSENCKP Transmit and Receive Buffer criptions of register bit fields. Bit 9Bit 8Bit 7Bit 6 ———SPIROV SMPCKESSENCKP Transmit and Receive Buffer criptions of register bit fields. s s e 6 e Bit 10 — MODE16 046) for d Bit 10 — MODE1 046) for d 0 O 0 Bit 11 — DISSDO ual” (DS7 Bit 11 — DISSD ual” (DS7 n 2 n (1)P Bit 12 — — ce Ma (1)P Bit 1 — — ce Ma A n A n e L D e 4-1:SPI1 REGISTER M Addr.Bit 15Bit 14Bit 13 0220SPIEN—SPISIDL 0222—FRMENSPIFSD 0224 — = unimplemented bit, read as ‘’0Refer to the “dsPIC30F Family Refer 4-2:SPI2 REGISTER M Addr.Bit 15Bit 14Bit 13 0226SPIEN—SPISID 0228—FRMENSPIFS 022A — = unimplemented bit, read as ‘’0Refer to the “dsPIC30F Family Refer 1 1 e TABLE SFR Name SPI1STAT SPI1CON SPI1BUF Legend:Note1: TABLE SFR Nam SPI2STAT SPI2CON SPI2BUF Legend:Note1: DS70143E-page 94 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 15.0 I2C™ MODULE 15.1.1 VARIOUS I2C MODES The following types of I2C operation are supported: Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not • I2C slave operation with 7-bit addressing intended to be a complete reference • I2C slave operation with 10-bit addressing source. For more information on the CPU, • I2C master operation with 7-bit or 10-bit addressing peripherals, register descriptions and See the I2C programmer’s model in Figure15-1. general device functionality, refer to the “dsPIC30F Family Reference Manual” 15.1.2 PIN CONFIGURATION IN I2C MODE (DS70046). I2C has a 2-pin interface: the SCL pin is clock and the The Inter-Integrated Circuit (I2C™) module provides SDA pin is data. complete hardware support for both Slave and Multi- Master modes of the I2C serial communication 15.1.3 I2C REGISTERS standard, with a 16-bit interface. I2CCON and I2CSTAT are control and status registers, This module offers the following key features: respectively. The I2CCON register is readable and writ- • I2C interface supporting both master and slave able. The lower 6 bits of I2CSTAT are read only. The remaining bits of the I2CSTAT are read/write. operation • I2C Slave mode supports 7-bit and 10-bit I2CRSR is the shift register used for shifting data, addressing whereas I2CRCV is the buffer register to which data • I2C Master mode supports 7-bit and 10-bit bytes are written, or from which data bytes are read. I2CRCV is the receive buffer as shown in Figure15-1. addressing I2CTRN is the transmit register to which bytes are • I2C port allows bidirectional transfers between written during a transmit operation, as shown in master and slaves Figure15-2. • Serial clock synchronization for I2C port can be The I2CADD register holds the slave address. A status used as a handshake mechanism to suspend and bit, ADD10, indicates 10-bit Address mode. The resume serial transfer (SCLREL control) I2CBRG acts as the Baud Rate Generator (BRG) • I2C supports multi-master operation, detects bus reload value. collision and will arbitrate accordingly In receive operations, I2CRSR and I2CRCV together 15.1 Operating Function Description form a double-buffered receiver. When I2CRSR receives a complete byte, it is transferred to I2CRCV The hardware fully implements all the master and slave and an interrupt pulse is generated. During functions of the I2C Standard and Fast mode transmission, the I2CTRN is not double-buffered. specifications, as well as 7 and 10-bit addressing. Note: Following a Restart condition in 10-bit Thus, the I2C module can operate either as a slave or mode, the user only needs to match the a master on an I2C bus. first 7-bit address. FIGURE 15-1: PROGRAMMER’S MODEL I2CRCV (8 bits) Bit 7 Bit 0 I2CTRN (8 bits) Bit 7 Bit 0 I2CBRG (9 bits) Bit 8 Bit 0 I2CCON (16 bits) Bit 15 Bit 0 I2CSTAT (16 bits) Bit 15 Bit 0 I2CADD (10 bits) Bit 9 Bit 0 © 2011 Microchip Technology Inc. DS70143E-page 95

dsPIC30F6011A/6012A/6013A/6014A FIGURE 15-2: I2C™ BLOCK DIAGRAM Internal Data Bus I2CRCV Read Shift SCL Clock I2CRSR LSB SDA Addr_Match Match Detect Write I2CADD Read Start and Stop bit Detect Write T Start, Restart, A Stop bit Generate ST C I2 Read c gi o L Collision ol Detect ntr o Write C N O C C Acknowledge 2 I Read Generation Clock Stretching Write I2CTRN LSB Shift Read Clock Reload Control Write BRG Down I2CBRG Counter Read FCY DS70143E-page 96 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 15.2 I2C Module Addresses 15.3.2 SLAVE RECEPTION The I2CADD register contains the Slave mode If the R_W bit received is a ‘0’ during an address addresses. The register is a 10-bit register. match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL. After 8 bits are If the A10M bit (I2CCON<10>) is ‘0’, the address is received, if I2CRCV is not full or I2COV is not set, interpreted by the module as a 7-bit address. When an I2CRSR is transferred to I2CRCV. ACK is sent on the address is received, it is compared to the 7 Least ninth clock. Significant bits of the I2CADD register. If the RBF flag is set, indicating that I2CRCV is still If the A10M bit is ‘1’, the address is assumed to be a holding data from a previous operation (RBF = 1), then 10-bit address. When an address is received, it will be ACK is not sent; however, the interrupt pulse is gener- compared with the binary value ‘11110 A9 A8’ (where ated. In the case of an overflow, the contents of the A9 and A8 are two Most Significant bits of I2CADD). If I2CRSR are not loaded into the I2CRCV. that value matches, the next address will be compared with the Least Significant 8 bits of I2CADD, as specified Note: The I2CRCV will be loaded if the I2COV in the 10-bit addressing protocol. bit = 1 and the RBF flag = 0. In this case, a read of the I2CRCV was performed but TABLE 15-1: 7-BIT I2C™ SLAVE the user did not clear the state of the ADDRESSES SUPPORTED BY I2COV bit before the next receive DSPIC30F occurred. The Acknowledgement is not Address Description sent (ACK = 1) and the I2CRCV is updated. 0x00 General call address or start byte 0x01-0x03 Reserved 15.4 I2C 10-bit Slave Mode Operation 0x04-0x07 HS mode Master codes In 10-bit mode, the basic receive and transmit opera- 0x08-0x77 Valid 7-bit addresses tions are the same as in the 7-bit mode. However, the 0x78-0x7b Valid 10-bit addresses (lower 7 bits) criteria for address match is more complex. 0x7c-0x7f Reserved The I2C specification dictates that a slave must be addressed for a write operation with two address bytes 15.3 I2C 7-bit Slave Mode Operation following a Start bit. Once enabled (I2CEN = 1), the slave module will wait The A10M bit is a control bit that signifies that the for a Start bit to occur (i.e., the I2C module is ‘Idle’). Fol- address in I2CADD is a 10-bit address rather than a 7-bit lowing the detection of a Start bit, 8 bits are shifted into address. The address detection protocol for the first byte I2CRSR and the address is compared against of a message address is identical for 7-bit and 10-bit I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0> messages, but the bits being compared are different. are compared against I2CRSR<7:1> and I2CRSR<0> I2CADD holds the entire 10-bit address. Upon receiv- is the R_W bit. All incoming bits are sampled on the ing an address following a Start bit, I2CRSR <7:3> is rising edge of SCL. compared against a literal ‘11110’ (the default 10-bit If an address match occurs, an Acknowledgement will address) and I2CRSR<2:1> are compared against be sent, and the slave event interrupt flag (SI2CIF) is I2CADD<9:8>. If a match occurs and if R_W = 0, the set on the falling edge of the ninth (ACK) bit. The interrupt pulse is sent. The ADD10 bit will be cleared to address value is loaded into the I2CRCV buffer, and indicate a partial address match. If a match fails or the RBF bit is set. R_W = 1, the ADD10 bit is cleared and the module returns to the Idle state. 15.3.1 SLAVE TRANSMISSION The low byte of the address is then received and com- If the R_W bit received is a ‘1’, then the serial port will pared with I2CADD<7:0>. If an address match occurs, go into Transmit mode. It will send ACK on the ninth bit the interrupt pulse is generated and the ADD10 bit is and then hold SCL to ‘0’ until the CPU responds by writ- set, indicating a complete 10-bit address match. If an ing to I2CTRN. SCL is released by setting the SCLREL address match did not occur, the ADD10 bit is cleared bit, and 8 bits of data are shifted out. Data bits are and the module returns to the Idle state. shifted out on the falling edge of SCL, such that SDA is valid during SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2011 Microchip Technology Inc. DS70143E-page 97

dsPIC30F6011A/6012A/6013A/6014A 15.4.1 10-BIT MODE SLAVE Clock stretching takes place following the ninth clock of TRANSMISSION the receive sequence. On the falling edge of the ninth clock at the end of the ACK sequence, if the RBF bit is Once a slave is addressed in this fashion with the full set, the SCLREL bit is automatically cleared, forcing 10-bit address (we will refer to this state as the SCL output to be held low. The user’s ISR must set “PRIOR_ADDR_MATCH”), the master can begin the SCLREL bit before reception is allowed to continue. sending data bytes for a slave reception operation. By holding the SCL line low, the user has time to ser- vice the ISR and read the contents of the I2CRCV 15.4.2 10-BIT MODE SLAVE RECEPTION before the master device can initiate another receive Once addressed, the master can generate a Repeated sequence. This will prevent buffer overruns from Start, reset the high byte of the address and set the occurring. R_W bit without generating a Stop bit, thus initiating a slave transmit operation. Note1: If the user reads the contents of the I2CRCV, clearing the RBF bit before the 15.5 Automatic Clock Stretch falling edge of the ninth clock, the SCLREL bit will not be cleared and clock In the Slave modes, the module can synchronize buffer stretching will not occur. reads and write to the master device by clock stretching. 2: The SCLREL bit can be set in software 15.5.1 TRANSMIT CLOCK STRETCHING regardless of the state of the RBF bit. The user should be careful to clear the RBF Both 10-bit and 7-bit Transmit modes implement clock bit in the ISR before the next receive stretching by asserting the SCLREL bit after the falling sequence in order to prevent an overflow edge of the ninth clock, if the TBF bit is cleared, condition. indicating the buffer is empty. In Slave Transmit modes, clock stretching is always 15.5.4 CLOCK STRETCHING DURING performed irrespective of the STREN bit. 10-BIT ADDRESSING (STREN = 1) Clock synchronization takes place following the ninth Clock stretching takes place automatically during the clock of the transmit sequence. If the device samples addressing sequence. Because this module has a an ACK on the falling edge of the ninth clock and if the register for the entire address, it is not necessary for TBF bit is still clear, then the SCLREL bit is automati- the protocol to wait for the address to be updated. cally cleared. The SCLREL being cleared to ‘0’ will assert the SCL line low. The user’s ISR must set the After the address phase is complete, clock stretching SCLREL bit before transmission is allowed to continue. will occur on each data receive or transmit sequence as By holding the SCL line low, the user has time to ser- was described earlier. vice the ISR and load the contents of the I2CTRN before the master device can initiate another transmit 15.6 Software Controlled Clock sequence. Stretching (STREN = 1) Note1: If the user loads the contents of I2CTRN, When the STREN bit is ‘1’, the SCLREL bit may be setting the TBF bit before the falling edge cleared by software to allow software to control the of the ninth clock, the SCLREL bit will not clock stretching. The logic will synchronize writes to the be cleared and clock stretching will not SCLREL bit with the SCL clock. Clearing the SCLREL occur. bit will not assert the SCL output until the module 2: The SCLREL bit can be set in software, detects a falling edge on the SCL output and SCL is regardless of the state of the TBF bit. sampled low. If the SCLREL bit is cleared by the user while the SCL line has been sampled low, the SCL out- 15.5.2 RECEIVE CLOCK STRETCHING put will be asserted (held low). The SCL output will remain low until the SCLREL bit is set, and all other The STREN bit in the I2CCON register can be used to devices on the I2C bus have deasserted SCL. This enable clock stretching in Slave Receive mode. When ensures that a write to the SCLREL bit will not violate the STREN bit is set, the SCL pin will be held low at the the minimum high time requirement for SCL. end of each data receive sequence. If the STREN bit is ‘0’, a software write to the SCLREL 15.5.3 CLOCK STRETCHING DURING bit will be disregarded and have no effect on the 7-BIT ADDRESSING (STREN = 1) SCLREL bit. When the STREN bit is set in Slave Receive mode, the SCL line is held low when the buffer register is full. The method for stretching the SCL output is the same for both 7 and 10-bit Addressing modes. DS70143E-page 98 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 15.7 Interrupts 15.12 I2C Master Operation The I2C module generates two interrupt flags, MI2CIF The master device generates all of the serial clock (I2C Master Interrupt Flag) and SI2CIF (I2C Slave Inter- pulses and the Start and Stop conditions. A transfer is rupt Flag). The MI2CIF interrupt flag is activated on ended with a Stop condition or with a Repeated Start completion of a master message event. The SI2CIF condition. Since the Repeated Start condition is also interrupt flag is activated on detection of a message the beginning of the next serial transfer, the I2C bus will directed to the slave. not be released. In Master Transmitter mode, serial data is output 15.8 Slope Control through SDA, while SCL outputs the serial clock. The The I2C standard requires slope control on the SDA first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In and SCL signals for Fast mode (400 kHz). The control this case, the data direction bit (R_W) is logic ‘0’. Serial bit, DISSLW, enables the user to disable slew rate con- data is transmitted 8 bits at a time. After each byte is trol if desired. It is necessary to disable the slew rate transmitted, an ACK bit is received. Start and Stop con- control for 1 MHz mode. ditions are output to indicate the beginning and the end of a serial transfer. 15.9 IPMI Support In Master Receive mode, the first byte transmitted con- The control bit, IPMIEN, enables the module to support tains the slave address of the transmitting device Intelligent Peripheral Management Interface (IPMI). (7bits) and the data direction bit. In this case, the data When this bit is set, the module accepts and acts upon direction bit (R_W) is logic ‘1’. Thus, the first byte trans- all addresses. mitted is a 7-bit slave address, followed by a ‘1’ to indi- cate receive bit. Serial data is received via SDA while 15.10 General Call Address Support SCL outputs the serial clock. Serial data is received 8bits at a time. After each byte is received, an ACK bit The general call address can address all devices. is transmitted. Start and Stop conditions indicate the When this address is used, all devices should, in beginning and end of transmission. theory, respond with an Acknowledgement. 15.12.1 I2C MASTER TRANSMISSION The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It Transmission of a data byte, a 7-bit address, or the sec- consists of all ‘0’s with R_W = 0. ond half of a 10-bit address is accomplished by simply The general call address is recognized when the Gen- writing a value to the I2CTRN register. The user should eral Call Enable (GCEN) bit is set (I2CCON<7> = 1). only write to I2CTRN when the module is in a Wait Following a Start bit detection, 8 bits are shifted into state. This action will set the Buffer Full Flag (TBF) and I2CRSR and the address is compared with I2CADD, allow the Baud Rate Generator to begin counting and and is also compared with the general call address start the next transmission. Each bit of address/data which is fixed in hardware. will be shifted out onto the SDA pin after the falling edge of SCL is asserted. The Transmit Status Flag, If a general call address match occurs, the I2CRSR is TRSTAT (I2CSTAT<14>), indicates that a master transferred to the I2CRCV after the eighth clock, the transmit is in progress. RBF flag is set and on the falling edge of the ninth bit (ACK bit), the master event interrupt flag (MI2CIF) is 15.12.2 I2C MASTER RECEPTION set. Master mode reception is enabled by programming the When the interrupt is serviced, the source for the inter- Receive Enable bit, RCEN (I2CCON<3>). The I2C rupt can be checked by reading the contents of the module must be Idle before the RCEN bit is set, other- I2CRCV to determine if the address was device wise the RCEN bit will be disregarded. The Baud Rate specific or a general call address. Generator begins counting and, on each rollover, the state of the SCL pin ACK and data are shifted into the 15.11 I2C Master Support I2CRSR on the rising edge of each clock. As a master device, six operations are supported: • Assert a Start condition on SDA and SCL. • Assert a Restart condition on SDA and SCL. • Write to the I2CTRN register initiating transmission of data/address. • Generate a Stop condition on SDA and SCL. • Configure the I2C port to receive data. • Generate an ACK condition at the end of a received byte of data. © 2011 Microchip Technology Inc. DS70143E-page 99

dsPIC30F6011A/6012A/6013A/6014A 15.12.3 BAUD RATE GENERATOR If a Start, Restart, Stop or Acknowledge condition was In I2C Master mode, the reload value for the BRG is in progress when the bus collision occurred, the condi- tion is aborted, the SDA and SCL lines are deasserted, located in the I2CBRG register. When the BRG is and the respective control bits in the I2CCON register loaded with this value, the BRG counts down to ‘0’ and are cleared to ‘0’. When the user services the bus col- stops until another reload has taken place. If clock arbi- lision Interrupt Service Routine, and if the I2C bus is tration is taking place, for instance, the BRG is reloaded free, the user can resume communication by asserting when the SCL pin is sampled high. a Start condition. As per the I2C standard, FSCK may be 100 kHz or The master will continue to monitor the SDA and SCL 400kHz. However, the user can specify any baud rate pins, and if a Stop condition occurs, the MI2CIF bit will up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal. be set. EQUATION 15-1: SERIAL CLOCK RATE A write to the I2CTRN will start the transmission of data at the first data bit regardless of where the transmitter left off when bus collision occurred. I2CBRG = ( FCY – FCY ) – 1 FSCK 1,111,111 In a multi-master environment, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C 15.12.4 CLOCK ARBITRATION bus can be taken when the P bit is set in the I2CSTAT register, or the bus is Idle and the S and P bits are Clock arbitration occurs when the master deasserts the cleared. SCL pin (SCL allowed to float high) during any receive, transmit, or Restart/Stop condition. When the SCL pin is allowed to float high, the Baud Rate Generator is 15.13 I2C Module Operation During CPU suspended from counting until the SCL pin is actually Sleep and Idle Modes sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of 15.13.1 I2C OPERATION DURING CPU I2CBRG and begins counting. This ensures that the SLEEP MODE SCL high time will always be at least one BRG rollover When the device enters Sleep mode, all clock sources count in the event that the clock is held low by an exter- to the module are shutdown and stay at logic‘0’. If nal device. Sleep occurs in the middle of a transmission and the state machine is partially into a transmission as the 15.12.5 MULTI-MASTER COMMUNICATION, clocks stop, then the transmission is aborted. Similarly, BUS COLLISION AND BUS if Sleep occurs in the middle of a reception, then the ARBITRATION reception is aborted. Multi-master operation support is achieved by bus arbi- tration. When the master outputs address/data bits 15.13.2 I2C OPERATION DURING CPU IDLE onto the SDA pin, arbitration takes place when the MODE master outputs a ‘1’ on SDA by letting SDA float high For the I2C, the I2CSIDL bit selects if the module will while another master asserts a ‘0’. When the SCL pin stop on Idle or continue on Idle. If I2CSIDL = 0, the floats high, data should be stable. If the expected data module will continue operation on assertion of the Idle on SDA is a ‘1’ and the data sampled on the SDA mode. If I2CSIDL = 1, the module will stop on Idle. pin=0, then a bus collision has taken place. The master will set the MI2CIF pulse and reset the master portion of the I2C port to its Idle state. If a transmit was in progress when the bus collision occurred, the transmission is halted, the TBF flag is cleared, the SDA and SCL lines are deasserted and a value can now be written to I2CTRN. When the user services the I2C master event Interrupt Service Rou- tine, if the I2C bus is free (i.e., the P bit is set), the user can resume communication by asserting a Start condition. DS70143E-page 100 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 e 0 1 0 0 0 0 Stat 000 111 000 000 000 000 et 0 0 0 0 0 0 s 0 0 0 0 0 0 e 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 0 SEN TBF Bit 1 RSEN RBF 2 N W Bit PE R_ Bit 4Bit 3 Receive Register Transmit Register Rate Generator ACKENRCEN PS Register Bit 5 Baud CKDT D_A dress A d A N V Bit 6 STRE I2CO Bit 7 GCEN WCOL elds. Bit 8 — — SMEN ADD10I egister bit fi W T of r Bit 9 — — — DISSL GCSTA ptions cri s Bit 10 — — — A10M BCL — 6) for de Bit 11 — — — PMIEN — — DS7004 1) Bit 12 — — — CLRELI — — Manual” ( (P S e c A L n R M Bit 13 — — — 2CSID — — s ‘’0Refere EGISTE Bit 14 — — — —I TRSTAT — d bit, read a30F Family R eC 25-2:IC™ Addr.Bit 15 0200— 0202— 0204— 0206I2CEN 0208ACKSTAT 020A— — = unimplementRefer to the “dsPI 1 TABLE SFR Name I2CRCV I2CTRN I2CBRG I2CCON I2CSTAT I2CADD Legend:Note1: © 2011 Microchip Technology Inc. DS70143E-page 101

dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 102 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 16.0 UNIVERSAL ASYNCHRONOUS 16.1 UART Module Overview RECEIVER TRANSMITTER The key features of the UART module are: (UART) MODULE • Full-duplex, 8 or 9-bit data communication Note: This data sheet summarizes features of • Even, odd or no parity options (for 8-bit data) this group ofdsPIC30F devices and is not • One or two Stop bits intended to be a complete reference • Fully integrated Baud Rate Generator with 16-bit source. For more information on the CPU, prescaler peripherals, register descriptions and • Baud rates range from 38 bps to 1.875 Mbps at a general device functionality, refer to the 30 MHz instruction rate “dsPIC30F Family Reference Manual” • 4-word deep transmit data buffer (DS70046). • 4-word deep receive data buffer This section describes the Universal Asynchronous • Parity, framing and buffer overrun error detection Receiver Transmitter communications module. • Support for interrupt only on address detect (9th bit = 1) • Separate transmit and receive interrupts • Loopback mode for diagnostic support FIGURE 16-1: UART TRANSMITTER BLOCK DIAGRAM Internal Data Bus Control and Status bits Write Write UTX8 UxTXREG Low Byte Transmit Control – Control TSR – Control Buffer – Generate Flags – Generate Interrupt Load TSR UxTXIF UTXBRK Data Transmit Shift Register (UxTSR) ‘0’ (Start) UxTX ‘1’ (Stop) Parity GePnaerritaytor 16 Divider 1fr6oxm B Baauudd C Rloactek Generator Control Signals Note: x = 1 or 2. © 2011 Microchip Technology Inc. DS70143E-page 103

dsPIC30F6011A/6012A/6013A/6014A FIGURE 16-2: UART RECEIVER BLOCK DIAGRAM Internal Data Bus 16 Read Write Read Read Write UxMODE UxSTA URX8 UxRXREG Low Byte Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters LPBACK 8-9 From UxTX 1 Load RSR to Buffer Control R R UxRX Receive Shift Register Signals ER ER 0 (UxRSR) P F · Start bit Detect · Parity Check · Stop bit Detect 16 Divider · Shift Clock Generation · Wake Logic 16x Baud Clock from Baud Rate Generator UxRXIF DS70143E-page 104 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 16.2 Enabling and Setting Up UART 16.3 Transmitting Data 16.2.1 ENABLING THE UART 16.3.1 TRANSMITTING IN 8-BIT DATA MODE The UART module is enabled by setting the UARTEN bit in the UxMODE register (where x = 1 or 2). Once The following steps must be performed in order to enabled, the UxTX and UxRX pins are configured as an transmit 8-bit data: output and an input respectively, overriding the TRIS 1. Set up the UART: and LATCH register bit settings for the corresponding First, the data length, parity and number of Stop I/O port pins. The UxTX pin is at logic ‘1’ when no bits must be selected. Then, the transmit and transmission is taking place. receive interrupt enable and priority bits are set up in the UxMODE and UxSTA registers. Also, 16.2.2 DISABLING THE UART the appropriate baud rate value must be written The UART module is disabled by clearing the UARTEN to the UxBRG register. bit in the UxMODE register. This is the default state 2. Enable the UART by setting the UARTEN bit after any Reset. If the UART is disabled, all I/O pins (UxMODE<15>). operate as port pins under the control of the latch and 3. Set the UTXEN bit (UxSTA<10>), thereby TRIS bits of the corresponding port pins. enabling a transmission. Disabling the UART module resets the buffers to empty 4. Write the byte to be transmitted to the lower byte states. Any data characters in the buffers are lost and of UxTXREG. The value will be transferred to the the baud rate counter is reset. Transmit Shift register (UxTSR) immediately All error and status flags associated with the UART and the serial bit stream will start shifting out module are reset when the module is disabled. The during the next rising edge of the baud clock. URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and Alternatively, the data byte may be written while UTXBF bits are cleared, whereas RIDLE and TRMT UTXEN = 0, following which, the user may set are set. Other control bits, including ADDEN, UTXEN. This will cause the serial bit stream to URXISEL<1:0>, UTXISEL, as well as the UxMODE begin immediately because the baud clock will and UxBRG registers, are not affected. start from a cleared state. Clearing the UARTEN bit while the UART is active will 5. A transmit interrupt will be generated, depend- abort all pending transmissions and receptions and ing on the value of the interrupt control bit reset the module as defined above. Re-enabling the UTXISEL (UxSTA<15>). UART will restart the UART in the same configuration. 16.3.2 TRANSMITTING IN 9-BIT DATA 16.2.3 SETTING UP DATA, PARITY AND MODE STOP BIT SELECTIONS The sequence of steps involved in the transmission of Control bits PDSEL<1:0> in the UxMODE register are 9-bit data is similar to 8-bit transmission, except that a used to select the data length and parity used in the 16-bit data word (of which the upper 7 bits are always transmission. The data length may either be 8 bits with clear) must be written to the UxTXREG register. even, odd or no parity, or 9 bits with no parity. 16.3.3 TRANSMIT BUFFER (UXTXB) The STSEL bit determines whether one or two Stop bits The transmit buffer is 9 bits wide and 4 characters will be used during data transmission. deep. Including the Transmit Shift register (UxTSR), The default (power-on) setting of the UART is 8 bits, no the user effectively has a 5-deep FIFO (First-In, First- parity and 1 Stop bit (typically represented as 8, N, 1). Out) buffer. The UTXBF status bit (UxSTA<9>) indicates whether the transmit buffer is full. If a user attempts to write to a full buffer, the new data will not be accepted into the FIFO, and no data shift will occur within the buffer. This enables recovery from a buffer overrun condition. The FIFO is reset during any device Reset but is not affected when the device enters or wakes up from a power-saving mode. © 2011 Microchip Technology Inc. DS70143E-page 105

dsPIC30F6011A/6012A/6013A/6014A 16.3.4 TRANSMIT INTERRUPT 16.4.2 RECEIVE BUFFER (UXRXB) The transmit interrupt flag (U1TXIF or U2TXIF) is The receive buffer is 4 words deep. Including the located in the corresponding interrupt flag register. Receive Shift register (UxRSR), the user effectively has a 5-word deep FIFO buffer. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends URXDA (UxSTA<0>) = 1 indicates that the receive buf- on the UTXISEL control bit: fer has data available. URXDA = 0 implies that the buf- fer is empty. If a user attempts to read an empty buffer, 1. If UTXISEL = 0, an interrupt is generated when the old values in the buffer will be read and no data shift a word is transferred from the transmit buffer to will occur within the FIFO. the Transmit Shift register (UxTSR). This implies that the transmit buffer has at least one empty The FIFO is reset during any device Reset. It is not word. affected when the device enters or wakes up from a 2. If UTXISEL = 1, an interrupt is generated when Power-Saving mode. a word is transferred from the transmit buffer to 16.4.3 RECEIVE INTERRUPT the Transmit Shift register (UxTSR) and the transmit buffer is empty. The receive interrupt flag (U1RXIF or U2RXIF) can be read from the corresponding interrupt flag register. The Switching between the two Interrupt modes during interrupt flag is set by an edge generated by the operation is possible and sometimes offers more receiver. The condition for setting the receive interrupt flexibility. flag depends on the settings specified by the 16.3.5 TRANSMIT BREAK URXISEL<1:0> (UxSTA<7:6>) control bits. Setting the UTXBRK bit (UxSTA<11>) will cause the a) If URXISEL<1:0> = 00 or 01, an interrupt is gen- UxTX line to be driven to logic ‘0’. The UTXBRK bit erated every time a data word is transferred overrides all transmission activity. Therefore, the user from the Receive Shift register (UxRSR) to the should generally wait for the transmitter to be Idle receive buffer. There may be one or more before setting UTXBRK. characters in the receive buffer. b) If URXISEL<1:0> = 10, an interrupt is generated To send a break character, the UTXBRK bit must be set when a word is transferred from the Receive Shift by software and must remain set for a minimum of 13 register (UxRSR) to the receive buffer, which as a baud clock cycles. The UTXBRK bit is then cleared by result of the transfer, contains 3 characters. software to generate Stop bits. The user must wait for a duration of at least one or two baud clock cycles in c) If URXISEL<1:0> = 11, an interrupt is set when order to ensure a valid Stop bit(s) before reloading the a word is transferred from the Receive Shift reg- UxTXB, or starting other transmitter activity. Transmis- ister (UxRSR) to the receive buffer, which as a sion of a break character does not generate a transmit result of the transfer, contains 4 characters (i.e., interrupt. becomes full). Switching between the Interrupt modes during opera- 16.4 Receiving Data tion is possible, though generally not advisable during normal operation. 16.4.1 RECEIVING IN 8-BIT OR 9-BIT DATA MODE 16.5 Reception Error Handling The following steps must be performed while receiving 16.5.1 RECEIVE BUFFER OVERRUN 8-bit or 9-bit data: ERROR (OERR BIT) 1. Set up the UART (see Section16.3.1 “Transmitting in 8-bit data mode”). The OERR bit (UxSTA<1>) is set if all of the following conditions occur: 2. Enable the UART (see Section16.3.1 “Transmitting in 8-bit data mode”). a) The receive buffer is full. 3. A receive interrupt will be generated when one b) The Receive Shift register is full, but unable to or more data words have been received, transfer the character to the receive buffer. depending on the receive interrupt settings c) The Stop bit of the character in the UxRSR is specified by the URXISEL bits (UxSTA<7:6>). detected, indicating that the UxRSR needs to 4. Read the OERR bit to determine if an overrun transfer the character to the buffer. error has occurred. The OERR bit must be reset Once OERR is set, no further data is shifted in UxRSR in software. (until the OERR bit is cleared in software or a Reset 5. Read the received data from UxRXREG. The occurs). The data held in UxRSR and UxRXREG act of reading UxRXREG will move the next remains valid. word to the top of the receive FIFO, and the PERR and FERR values will be updated. DS70143E-page 106 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 16.5.2 FRAMING ERROR (FERR) 16.6 Address Detect Mode The FERR bit (UxSTA<2>) is set if a ‘0’ is detected Setting the ADDEN bit (UxSTA<5>) enables this spe- instead of a Stop bit. If two Stop bits are selected, both cial mode in which a 9th bit (URX8) value of ‘1’ identi- Stop bits must be ‘1’, otherwise FERR will be set. The fies the received word as an address, rather than data. read only FERR bit is buffered along with the received This mode is only applicable for 9-bit data communica- data. It is cleared on any Reset. tion. The URXISEL control bit does not have any impact on interrupt generation in this mode since an 16.5.3 PARITY ERROR (PERR) interrupt (if enabled) will be generated every time the The PERR bit (UxSTA<3>) is set if the parity of the received word has the 9th bit set. received word is incorrect. This error bit is applicable only if a Parity mode (odd or even) is selected. The 16.7 Loopback Mode read only PERR bit is buffered along with the received data bytes. It is cleared on any Reset. Setting the LPBACK bit enables this special mode in which the UxTX pin is internally connected to the UxRX 16.5.4 IDLE STATUS pin. When configured for the Loopback mode, the UxRX pin is disconnected from the internal UART When the receiver is active (i.e., between the initial receive logic. However, the UxTX pin still functions as detection of the Start bit and the completion of the Stop in a normal operation. bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the com- pletion of the Stop bit and detection of the next Start bit, To select this mode: the RIDLE bit is ‘1’, indicating that the UART is Idle. 1. Configure UART for desired mode of operation. 2. Set LPBACK = 1 to enable Loopback mode. 16.5.5 RECEIVE BREAK 3. Enable transmission as defined in Section16.3 The receiver will count and expect a certain number of “Transmitting Data”. bit times based on the values programmed in the PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>) 16.8 Baud Rate Generator bits. If the break is longer than 13 bit times, the reception is The UART has a 16-bit Baud Rate Generator to allow considered complete after the number of bit times maximum flexibility in baud rate generation. The Baud specified by PDSEL and STSEL. The URXDA bit is set, Rate Generator register (UxBRG) is readable and FERR is set, zeros are loaded into the receive FIFO, writable. The baud rate is computed as shown in interrupts are generated if appropriate and the RIDLE Equation16-1: bit is set. EQUATION 16-1: BAUD RATE When the module receives a long break signal and the receiver has detected the Start bit, the data bits and the Baud Rate = FCY/(16 * (BRG + 1)) invalid Stop bit (which sets the FERR), the receiver must wait for a valid Stop bit before looking for the next Start bit. It cannot assume that the break condition on Where: the line is the next Start bit. BRG = 16-bit value held in UxBRG register Break is regarded as a character containing all ‘0’s with (0 through 65535) the FERR bit set. The break character is loaded into the FCY = Instruction Clock Rate (1/TCY) buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit Therefore, the maximum baud rate possible is: has not yet been received. FCY/16 (if BRG = 0), and the minimum baud rate possible is: FCY/(16 * 65536). With a full 16-bit Baud Rate Generator at 30 MIPS operation, the minimum baud rate achievable is 28.5bps. © 2011 Microchip Technology Inc. DS70143E-page 107

dsPIC30F6011A/6012A/6013A/6014A 16.9 Auto-Baud Support 16.10.2 UART OPERATION DURING CPU IDLE MODE To allow the system to determine baud rates of received characters, the input can be optionally linked For the UART, the USIDL bit selects if the module will to a capture input (IC1 for UART1, IC2 for UART2). To stop operation when the device enters Idle mode or enable this mode, the user must program the input cap- whether the module will continue on Idle. If USIDL=0, ture module to detect the falling and rising edges of the the module will continue operation during Idle mode. If Start bit. USIDL = 1, the module will stop on Idle. 16.10 UART Operation During CPU Sleep and Idle Modes 16.10.1 UART OPERATION DURING CPU SLEEP MODE When the device enters Sleep mode, all clock sources to the module are shutdown and stay at logic ‘0’. If entry into Sleep mode occurs while a transmission is in prog- ress, then the transmission is aborted. The UxTX pin is driven to logic ‘1’. Similarly, if entry into Sleep mode occurs while a reception is in progress, then the recep- tion is aborted. The UxSTA, UxMODE, transmit and receive registers and buffers, and the UxBRG register are not affected by Sleep mode. If the WAKE bit (UxMODE<7>) is set before the device enters Sleep mode, then a falling edge on the UxRX pin will generate a receive interrupt. The Receive Interrupt Select mode bit (URXISEL) has no effect for this func- tion. If the receive interrupt is enabled, then this will wake-up the device from Sleep. The UARTEN bit must be set in order to generate a wake-up interrupt. DS70143E-page 108 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 0 0 u 0 0 0 0 u 0 0 0 0 u 0 0 0 0 u 0 0 0 0 u 0 0 0 0 u 0 0 0 0 u 0 0 0 0 u 0 0 e 0 1 u 0 0 e 0 1 u 0 0 Stat 000 000 uuu 000 000 Stat 000 000 uuu 000 000 et 0 1 u 0 0 et 0 1 u 0 0 s 0 0 0 0 0 s 0 0 0 0 0 e 0 0 0 0 0 e 0 0 0 0 0 R 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 0 TSEL RXDA Bit 0 TSEL RXDA S U S U Bit 1 PDSEL0 OERR Bit 1 PDSEL0 OERR Bit 2 PDSEL1 FERR Bit 2 PDSEL1 FERR Bit 5Bit 4Bit 3 ABAUD—— ADDENRIDLEPERR Transmit Register Receive Register Bit 5Bit 4Bit 3 BAUD—— DDENRIDLEPERR Transmit Register Receive Register A A 0 Bit 8Bit 7Bit 6 —WAKELPBACK TRMTURXISEL1URXISEL UTX8 URX8 ud Rate Generator Prescaler ns of register bit fields. Bit 8Bit 7Bit 6 —WAKELPBACK TRMTURXISEL1URXISEL0 UTX8 URX8 ud Rate Generator Prescaler ns of register bit fields. a o a o 1Bit 10Bit 9 —— RKUTXENUTXBF —— —— B s ‘’0DS70046) for descripti Bit 10Bit 9 —— KUTXENUTXBF —— —— B s ‘’0DS70046) for descripti (1)6-1:UART1 REGISTER MAP Addr.Bit 15Bit 14Bit 13Bit 12Bit 1 020CUARTEN—USIDL—— 020EUTXISEL———UTXB 0210————— 0212————— 0214 u = uninitialized bit; — = unimplemented bit, read aRefer to the “dsPIC30F Family Reference Manual” ( (1)6-2:UART2 REGISTER MAP Addr.Bit 15Bit 14Bit 13Bit 12Bit 11 0216UARTEN—USIDL—— 0218UTXISEL———UTXBR 021A————— 021C————— 021E u = uninitialized bit; — = unimplemented bit, read aRefer to the “dsPIC30F Family Reference Manual” ( 1 1 ABLE FR Name 1MODE 1STA 1TXREG 1RXREG 1BRG egend:ote1: ABLE SFR Name 2MODE 2STA 2TXREG 2RXREG 2BRG egend:ote1: T S U U U U U LN T U U U U U LN © 2011 Microchip Technology Inc. DS70143E-page 109

dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 110 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 17.0 CAN MODULE The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine Note: This data sheet summarizes features of handles all functions for receiving and transmitting this group ofdsPIC30F devices and is not messages on the CAN bus. Messages are transmitted intended to be a complete reference by first loading the appropriate data registers. Status source. For more information on the CPU, and errors can be checked by reading the appropriate peripherals, register descriptions and registers. Any message detected on the CAN bus is general device functionality, refer to the checked for errors and then matched against filters to “dsPIC30F Family Reference Manual” see if it should be received and stored in one of the (DS70046). receive registers. 17.1 Overview 17.2 Frame Types The Controller Area Network (CAN) module is a serial The CAN module transmits various types of frames interface, useful for communicating with other CAN which include data messages or remote transmission modules or microcontroller devices. This interface/ requests initiated by the user, as other frames that are protocol was designed to allow communications within automatically generated for control purposes. The noisy environments. following frame types are supported: The CAN module is a communication controller imple- • Standard Data Frame: menting the CAN 2.0 A/B protocol, as defined in the A standard data frame is generated by a node BOSCH specification. The module will support when the node wishes to transmit data. It includes CAN1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B an 11-bit Standard Identifier (SID) but not an 18-bit Active versions of the protocol. The module implemen- Extended Identifier (EID). tation is a full CAN system. The CAN specification is not covered within this data sheet. The reader may • Extended Data Frame: refer to the BOSCH CAN specification for further An extended data frame is similar to a standard details. data frame but includes an extended identifier as The module features are as follows: well. • Implementation of the CAN protocol CAN1.2, • Remote Frame: CAN2.0A and CAN2.0B It is possible for a destination node to request the • Standard and extended data frames data from the source. For this purpose, the desti- • 0-8 bytes data length nation node sends a remote frame with an identi- • Programmable bit rate up to 1 Mbps fier that matches the identifier of the required data frame. The appropriate data source node will then • Support for remote frames send a data frame as a response to this remote • Double-buffered receiver with two prioritized request. received message storage buffers (each buffer may contain up to 8 bytes of data) • Error Frame: • 6 full (standard/extended identifier) acceptance An error frame is generated by any node that filters, 2 associated with the high priority receive detects a bus error. An error frame consists of 2 buffer and 4 associated with the low priority fields: an error flag field and an error delimiter receive buffer field. • 2 full acceptance filter masks, one each associated with the high and low priority receive • Overload Frame: buffers An overload frame can be generated by a node as • Three transmit buffers with application specified a result of 2 conditions. First, the node detects a prioritization and abort capability (each buffer may dominant bit during interframe space which is an contain up to 8 bytes of data) illegal condition. Second, due to internal condi- • Programmable wake-up functionality with tions, the node is not yet able to start reception of integrated low-pass filter the next message. A node may generate a maxi- • Programmable Loopback mode supports self-test mum of 2 sequential overload frames to delay the operation start of the next message. • Signaling via interrupt capabilities for all CAN • Interframe Space: receiver and transmitter error states Interframe space separates a proceeding frame • Programmable clock source (of whatever type) from a following data or remote • Programmable link to Input Capture module (IC2, frame. for both CAN1 and CAN2) for time-stamping and network synchronization • Low-power Sleep and Idle mode © 2011 Microchip Technology Inc. DS70143E-page 111

dsPIC30F6011A/6012A/6013A/6014A FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask BUFFERS RXM1 Acceptance Filter RXF2 Acceptance Mask Acceptance Filter A TXB0 TXB1 TXB2 RXM0 RXF3 c A c MSGREQTXABTTXLARBTXERRMTXBUFF MESSAGE MSGREQTXABTTXLARBTXERRMTXBUFF MESSAGE MSGREQTXABTTXLARBTXERRMTXBUFF MESSAGE ccep AAcccceeppRRttaaXXnnFFcc01ee FFiilltteerr AAcccceeppRRttaaXXnnFFcc45ee FFiilltteerr ept t R R X Identifier M Identifier X Message B A B Queue 0 B 1 Control Transmit Byte Sequencer Data Field Data Field Receive RERRCNT Error PROTOCOL Counter TERRCNT ENGINE Transmit Err Pas Error Bus Off Counter Transmit Shift Receive Shift Protocol Finite CRC Generator CRC Check State Machine Bit Transmit Timing Bit Timing Logic Logic Generator CiTX(1) CiRX(1) Note1: i = 1 or 2 refers to a particular CAN module (CAN1 or CAN2). DS70143E-page 112 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 17.3 Modes of Operation The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or The CAN module can operate in one of several Operation the CPU is in Sleep mode. The WAKFIL bit modes selected by the user. These modes include: (CiCFG2<14>) enables or disables the filter. • Initialization Mode Note: Typically, if the CAN module is allowed to • Disable Mode transmit in a particular mode of operation • Normal Operation Mode and a transmission is requested immedi- • Listen Only Mode ately after the CAN module has been • Loopback Mode placed in that mode of operation, the mod- • Error Recognition Mode ule waits for 11 consecutive recessive bits Modes are requested by setting the REQOP<2:0> bits on the bus before starting transmission. If (CiCTRL<10:8>). Entry into a mode is Acknowledged the user switches to Disable mode within by monitoring the OPMODE<2:0> bits (CiCTRL<7:5>). this 11-bit period, then this transmission is The module will not change the mode and the aborted and the corresponding TXABT bit OPMODE bits until a change in mode is acceptable, is set and TXREQ bit is cleared. generally during bus Idle time which is defined as at 17.3.3 NORMAL OPERATION MODE least 11 consecutive recessive bits. Normal Operating mode is selected when 17.3.1 INITIALIZATION MODE REQOP<2:0>=000. In this mode, the module is acti- In the Initialization mode, the module will not transmit or vated and the I/O pins will assume the CAN bus func- receive. The error counters are cleared and the inter- tions. The module will transmit and receive CAN bus rupt flags remain unchanged. The programmer will messages via the CxTX and CxRX pins. have access to configuration registers that are access 17.3.4 LISTEN ONLY MODE restricted in other modes. The module will protect the user from accidentally violating the CAN protocol If the Listen Only mode is activated, the module on the through programming errors. All registers which control CAN bus is passive. The transmitter buffers revert to the configuration of the module can not be modified the port I/O function. The receive pins remain inputs. while the module is on-line. The CAN module will not For the receiver, no error flags or Acknowledge signals be allowed to enter the Configuration mode while a are sent. The error counters are deactivated in this transmission is taking place. The Configuration mode state. The Listen Only mode can be used for detecting serves as a lock to protect the following registers. the baud rate on the CAN bus. To use this, it is neces- • All Module Control Registers sary that there are at least two further nodes that • Baud Rate and Interrupt Configuration Registers communicate with each other. • Bus Timing Registers 17.3.5 LISTEN ALL MESSAGES MODE • Identifier Acceptance Filter Registers The module can be set to ignore all errors and receive • Identifier Acceptance Mask Registers any message. The Error Recognition mode is activated 17.3.2 DISABLE MODE by setting REQOP<2:0> = 111. In this mode, the data which is in the message assembly buffer until the time In Disable mode, the module will not transmit or an error occurred, is copied in the receive buffer and receive. The module has the ability to set the WAKIF bit can be read via the CPU interface. due to bus activity, however, any pending interrupts will remain and the error counters will retain their value. 17.3.6 LOOPBACK MODE If the REQOP<2:0> bits (CiCTRL<10:8>) = 001, the If the Loopback mode is activated, the module will con- module will enter the Module Disable mode. If the module nect the internal transmit signal to the internal receive is active, the module will wait for 11 recessive bits on the signal at the module boundary. The transmit and CAN bus, detect that condition as an Idle bus, then receive pins revert to their port I/O function. accept the module disable command. When the OPMODE<2:0> bits (CiCTRL<7:5>)=001, that indi- cates whether the module successfully went into Module Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. © 2011 Microchip Technology Inc. DS70143E-page 113

dsPIC30F6011A/6012A/6013A/6014A 17.4 Message Reception 17.4.4 RECEIVE OVERRUN An overrun condition occurs when the Message 17.4.1 RECEIVE BUFFERS Assembly Buffer (MAB) has assembled a valid The CAN bus module has 3 receive buffers. However, received message, the message is accepted through one of the receive buffers is always committed to mon- the acceptance filters and when the receive buffer itoring the bus for incoming messages. This buffer is associated with the filter has not been designated as called the Message Assembly Buffer (MAB). So there clear of the previous message. are 2 receive buffers visible, RXB0 and RXB1, that can The overrun error flag, RXnOVR (CiINTF<15> or essentially instantaneously receive a complete CiINTF<14>), and the ERRIF bit (CiINTF<5>) will be message from the protocol engine. set and the message in the MAB will be discarded. All messages are assembled by the MAB and are trans- If the DBEN bit is clear, RXB1 and RXB0 operate inde- ferred to the RXBn buffers only if the acceptance filter pendently. When this is the case, a message intended criterion are met. When a message is received, the for RXB0 will not be diverted into RXB1 if RXB0 con- RXnIF flag (CiINTF<0> or CiINRF<1>) will be set. This tains an unread message and the RX0OVR bit will be bit can only be set by the module when a message is set. received. The bit is cleared by the CPU when it has com- pleted processing the message in the buffer. If the If the DBEN bit is set, the overrun for RXB0 is handled RXnIE bit (CiINTE<0> or CiINTE<1>) is set, an interrupt differently. If a valid message is received for RXB0 and will be generated when a message is received. RXFUL=1 indicates that RXB0 is full and RXFUL=0 indicates that RXB1 is empty, the message for RXB0 RXF0 and RXF1 filters with RXM0 mask are associated will be loaded into RXB1. An overrun error will not be with RXB0. The filters RXF2, RXF3, RXF4, and RXF5 generated for RXB0. If a valid message is received for and the mask RXM1 are associated with RXB1. RXB0 and RXFUL=1, indicating that both RXB0 and RXB1 are full, the message will be lost and an overrun 17.4.2 MESSAGE ACCEPTANCE FILTERS will be indicated for RXB1. The message acceptance filters and masks are used to determine if a message in the message assembly buf- 17.4.5 RECEIVE ERRORS fer should be loaded into either of the receive buffers. The CAN module will detect the following receive Once a valid message has been received into the Mes- errors: sage Assembly Buffer (MAB), the identifier fields of the message are compared to the filter values. If there is a • Cyclic Redundancy Check (CRC) Error match, that message will be loaded into the appropriate • Bit Stuffing Error receive buffer. • Invalid Message Receive Error The acceptance filter looks at incoming messages for The receive error counter is incremented by one in the RXIDE bit (CiRXnSID<0>) to determine how to case one of these errors occur. The RXWAR bit compare the identifiers. If the RXIDE bit is clear, the (CiINTF<9>) indicates that the receive error counter message is a standard frame and only filters with the has reached the CPU warning limit of 96 and an EXIDE bit (CiRXFnSID<0>) clear are compared. If the interrupt is generated. RXIDE bit is set, the message is an extended frame, and only filters with the EXIDE bit set are compared. 17.4.6 RECEIVE INTERRUPTS Configuring the RXM<1:0> bits to ‘01’ or ‘10’ can Receive interrupts can be divided into 3 major groups, override the EXIDE bit. each including various conditions that generate interrupts: 17.4.3 MESSAGE ACCEPTANCE FILTER MASKS • Receive Interrupt: A message has been successfully received and The mask bits essentially determine which bits to apply loaded into one of the receive buffers. This inter- the filter to. If any mask bit is set to a zero, then that bit rupt is activated immediately after receiving the will automatically be accepted regardless of the filter End of Frame (EOF) field. Reading the RXnIF flag bit. There are 2 programmable acceptance filter masks will indicate which receive buffer caused the associated with the receive buffers, one for each buffer. interrupt. • Wake-up Interrupt: The CAN module has woken up from Disable mode or the device has woken up from Sleep mode. DS70143E-page 114 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A • Receive Error Interrupts: Setting the TXREQ bit simply flags a message buffer as A receive error interrupt will be indicated by the enqueued for transmission. When the module detects ERRIF bit. This bit shows that an error condition an available bus, it begins transmitting the message occurred. The source of the error can be deter- which has been determined to have the highest priority. mined by checking the bits in the CAN Interrupt If the transmission completes successfully on the first status register, CiINTF. attempt, the TXREQ bit is cleared automatically, and an interrupt is generated if TXIE was set. - Invalid Message Received: If any type of error occurred during reception of If the message transmission fails, one of the error con- the last message, an error will be indicated by dition flags will be set, and the TXREQ bit will remain the IVRIF bit. set indicating that the message is still pending for trans- mission. If the message encountered an error condition - Receiver Overrun: during the transmission attempt, the TXERR bit will be The RXnOVR bit indicates that an overrun set, and the error condition may cause an interrupt. If condition occurred. the message loses arbitration during the transmission attempt, the TXLARB bit is set. No interrupt is - Receiver Warning: generated to signal the loss of arbitration. The RXWAR bit indicates that the receive error counter (RERRCNT<7:0>) has reached the 17.5.4 ABORTING MESSAGE warning limit of 96. TRANSMISSION - Receiver Error Passive: The system can also abort a message by clearing the The RXEP bit indicates that the receive error TXREQ bit associated with each message buffer. Set- counter has exceeded the error passive limit of ting the ABAT bit (CiCTRL<12>) will request an abort of 127 and the module has gone into error passive all pending messages. If the message has not yet state. started transmission, or if the message started but is interrupted by loss of arbitration or an error, the abort 17.5 Message Transmission will be processed. The abort is indicated when the module sets the TXABT bit and the TXnIF flag is not 17.5.1 TRANSMIT BUFFERS automatically set. The CAN module has three transmit buffers. Each of 17.5.5 TRANSMISSION ERRORS the three buffers occupies 14 bytes of data. Eight of the bytes are the maximum 8 bytes of the transmitted mes- The CAN module will detect the following transmission sage. Five bytes hold the standard and extended errors: identifiers and other message arbitration information. • Acknowledge Error • Form Error 17.5.2 TRANSMIT MESSAGE PRIORITY • Bit Error Transmit priority is a prioritization within each node of These transmission errors will not necessarily generate the pending transmittable messages. There are an interrupt but are indicated by the transmission error 4levels of transmit priority. If TXPRI<1:0> counter. However, each of these errors will cause the (CiTXnCON<1:0>, where n = 0, 1 or 2 represents a par- transmission error counter to be incremented by one. ticular transmit buffer) for a particular message buffer is Once the value of the error counter exceeds the value set to ‘11’, that buffer has the highest priority. If of 96, the ERRIF (CiINTF<5>) and the TXWAR bit TXPRI<1:0> for a particular message buffer is set to (CiINTF<10>) are set. Once the value of the error ‘10’ or ‘01’, that buffer has an intermediate priority. If counter exceeds the value of 96, an interrupt is TXPRI<1:0> for a particular message buffer is ‘00’, that generated and the TXWAR bit in the Error Flag register buffer has the lowest priority. is set. 17.5.3 TRANSMISSION SEQUENCE To initiate transmission of the message, the TXREQ bit (CiTXnCON<3>) must be set. The CAN bus module resolves any timing conflicts between setting of the TXREQ bit and the Start of Frame (SOF), ensuring that if the priority was changed, it is resolved correctly before the SOF occurs. When the TXREQ is set, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits are automatically cleared. © 2011 Microchip Technology Inc. DS70143E-page 115

dsPIC30F6011A/6012A/6013A/6014A 17.5.6 TRANSMIT INTERRUPTS 17.6 Baud Rate Setting Transmit interrupts can be divided into 2 major groups, All nodes on any particular CAN bus must have the each including various conditions that generate same nominal bit rate. In order to set the baud rate, the interrupts: following parameters have to be initialized: • Transmit Interrupt: • Synchronization Jump Width At least one of the three transmit buffers is empty • Baud Rate Prescaler (not scheduled) and can be loaded to schedule a • Phase Segments message for transmission. Reading the TXnIF • Length determination of Phase Segment 2 flags will indicate which transmit buffer is available and caused the interrupt. • Sample Point • Propagation Segment bits • Transmit Error Interrupts: A transmission error interrupt will be indicated by 17.6.1 BIT TIMING the ERRIF flag. This flag shows that an error con- All controllers on the CAN bus must have the same dition occurred. The source of the error can be baud rate and bit length. However, different controllers determined by checking the error flags in the CAN are not required to have the same master oscillator Interrupt status register, CiINTF. The flags in this clock. At different clock frequencies of the individual register are related to receive and transmit errors. controllers, the baud rate has to be adjusted by - Transmitter Warning Interrupt: adjusting the number of time quanta in each segment. The TXWAR bit indicates that the transmit error The nominal bit time can be thought of as being divided counter has reached the CPU warning limit of into separate non-overlapping time segments. These 96. segments are shown in Figure17-2. - Transmitter Error Passive: • Synchronization Segment (Sync Seg) The TXEP bit (CiINTF<12>) indicates that the • Propagation Time Segment (Prop Seg) transmit error counter has exceeded the error • Phase Segment 1 (Phase1 Seg) passive limit of 127 and the module has gone to • Phase Segment 2 (Phase2 Seg) error passive state. The time segments and also the nominal bit time are - Bus Off: made up of integer units of time called time quanta or The TXBO bit (CiINTF<13>) indicates that the TQ. By definition, the nominal bit time has a minimum transmit error counter has exceeded 255 and of 8TQ and a maximum of 25TQ. Also, by definition, the module has gone to the bus off state. the minimum nominal bit time is 1μsec corresponding to a maximum bit rate of 1MHz. FIGURE 17-2: CAN BIT TIMING Input Signal Prop Phase Phase Sync Sync Segment Segment 1 Segment 2 Sample Point TQ DS70143E-page 116 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 17.6.2 PRESCALER SETTING 17.6.5 SAMPLE POINT There is a programmable prescaler with integral values The sample point is the point of time at which the bus ranging from 1 to 64, in addition to a fixed divide-by-2 level is read and interpreted as the value of that respec- for clock generation. The time quantum (TQ) is a fixed tive bit. The location is at the end of Phase1 Seg. If the unit of time derived from the oscillator period, and is bit timing is slow and contains many TQ, it is possible to given by Equation17-1. specify multiple sampling of the bus line at the sample point. The level determined by the CAN bus then corre- Note: FCAN must not exceed 30 MHz. If sponds to the result from the majority decision of three CANCKS = 0, then FCY must not exceed values. The majority samples are taken at the sample 7.5 MHz. point and twice before with a distance of TQ/2. The CAN module allows the user to choose between sam- EQUATION 17-1: TIME QUANTUM FOR pling three times at the same point or once at the same CLOCK GENERATION point, by setting or clearing the SAM bit (CiCFG2<6>). Typically, the sampling of the bit should take place at TQ = 2 (BRP<5:0> + 1) / FCAN about 60-70% through the bit time, depending on the system parameters. 17.6.3 PROPAGATION SEGMENT 17.6.6 SYNCHRONIZATION This part of the bit time is used to compensate physical To compensate for phase shifts between the oscillator delay times within the network. These delay times con- frequencies of the different bus stations, each CAN sist of the signal propagation time on the bus line and controller must be able to synchronize to the relevant the internal delay time of the nodes. The Prop Seg can signal edge of the incoming signal. When an edge in be programmed from 1TQ to 8TQ by setting the the transmitted data is detected, the logic will compare PRSEG<2:0> bits (CiCFG2<2:0>). the location of the edge to the expected time (Synchro- nous Segment). The circuit will then adjust the values 17.6.4 PHASE SEGMENTS of Phase1 Seg and Phase2 Seg. There are 2 The phase segments are used to optimally locate the mechanisms used to synchronize. sampling of the received bit within the transmitted bit time. The sampling point is between Phase1 Seg and 17.6.6.1 Hard Synchronization Phase2 Seg. These segments are lengthened or short- Hard synchronization is only done whenever there is a ened by resynchronization. The end of the Phase1 Seg ‘recessive’ to ‘dominant’ edge during bus Idle indicating determines the sampling point within a bit period. The the start of a message. After hard synchronization, the segment is programmable from 1TQ to 8TQ. Phase2 bit time counters are restarted with the Sync Seg. Hard Seg provides delay to the next transmitted data transi- synchronization forces the edge which has caused the tion. The segment is programmable from 1TQ to 8TQ, hard synchronization to lie within the synchronization or it may be defined to be equal to the greater of segment of the restarted bit time. If a hard synchroniza- Phase1 Seg or the information processing time (2TQ). tion is done, there will not be a resynchronization within The Phase1 Seg is initialized by setting bits that bit time. SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is initialized by setting SEG2PH<2:0> (CiCFG2<10:8>). 17.6.6.2 Resynchronization The following requirement must be fulfilled while setting As a result of resynchronization, Phase1 Seg may be the lengths of the phase segments: lengthened or Phase2 Seg may be shortened. The Prop Seg + Phase1 Seg > = Phase2 Seg amount of lengthening or shortening of the phase buf- fer segment has an upper bound known as the syn- chronization jump width, and is specified by the SJW<1:0> bits (CiCFG1<7:6>). The value of the syn- chronization jump width will be added to Phase1 Seg or subtracted from Phase2 Seg. The resynchronization jump width is programmable between 1TQ and 4TQ. The following requirement must be fulfilled while setting the SJW<1:0> bits: Phase2 Seg>Synchronization Jump Width © 2011 Microchip Technology Inc. DS70143E-page 117

dsPIC30F6011A/6012A/6013A/6014A u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u u u 0 u u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u 0 u u 0 u u u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u u u u u u 0 u u u State uuuu uuuu 0000 uuuu uuuu 0000 uuuu uuuu 0000 uuuu uuuu 0000 uuuu uuuu 0000 uuuu uuuu 0000 uuuu uuuu 0000 uuuu uuuu 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 uuuu uuuu uuuu et u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 0 0 u u u u u 0 0 0 u s u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 0 0 u u u u u 0 0 0 u e u u u u u u u u u u u u u u u u u u u u u u u u 0 0 u u u u u 0 0 0 u R u u u u u u u u u u u u u u u u u u u u u u u u u 0 u u u u u 0 u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u u u u u u u 0 u u u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u u u u u u u u 0 u u u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u u u u u u u u 0 u u u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u 0 0 u u u u u u u u 0 u u u Bit 0 EXIDE — EXIDE — EXIDE — EXIDE — EXIDE — EXIDE — MIDE — MIDE — TXIDE — <1:0> TXIDE — RI 1 R P R Bit — — — — — — — — — — — — — — — — SR — TX SR — > > Bit 2 — — — — — — — — <13:6 — — <13:6 — er er 0Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3 Receive Acceptance Filter 0 Standard Identifier <10:0> Receive Acceptance Filter 0 Extended Identifier <17:6> ——————— Receive Acceptance Filter 1 Standard Identifier <10:0> Receive Acceptance Filter 1 Extended Identifier <17:6> ——————— Receive Acceptance Filter 2 Standard Identifier <10:0> Receive Acceptance Filter 2 Extended Identifier <17:6> ——————— Receive Acceptance Filter 3 Standard Identifier <10:0> Receive Acceptance Filter 3 Extended Identifier <17:6> ——————— Receive Acceptance Filter 4 Standard Identifier <10:0> Receive Acceptance Filter 4 Extended Identifier <17:6> ——————— Receive Acceptance Filter 5 Standard Identifier <10:0> Receive Acceptance Filter 5 Extended Identifier <17:6> ——————— Receive Acceptance Mask 0 Standard Identifier <10:0> Receive Acceptance Mask 0 Extended Identifier <17:6> ——————— Receive Acceptance Mask 1 Standard Identifier <10:0> Receive Acceptance Mask 1 Extended Identifier <17:6> ——————— ——Transmit Buffer 2 Standard Identifier <5:0> ——Transmit Buffer 2 Extended Identifi TXRTRTXRB1TXRB0DLC<3:0> Transmit Buffer 2 Byte 0 Transmit Buffer 2 Byte 2 Transmit Buffer 2 Byte 4 Transmit Buffer 2 Byte 6 ———TXABTTXLARBTXERRTXREQ ——Transmit Buffer 1 Standard Identifier <5:0> ——Transmit Buffer 1 Extended Identifi TXRTRTXRB1TXRB0DLC<3:0> ptions of register bit fields. (1)-1:CAN1 REGISTER MAP AddrBit 15Bit 14Bit 13Bit 12Bit 11Bit 1 0300——— 0302———— 0304Receive Acceptance Filter 0 Extended Identifier <5:0> 0308——— 030A———— 030CReceive Acceptance Filter 1 Extended Identifier <5:0> 0310——— 0312———— 0314Receive Acceptance Filter 2 Extended Identifier <5:0> 0318——— 031A———— 031CReceive Acceptance Filter 3 Extended Identifier <5:0> 0320——— 0322———— 0324Receive Acceptance Filter 4 Extended Identifier <5:0> 0328——— 032A———— 032CReceive Acceptance Filter 5 Extended Identifier <5:0> 0330——— 0332———— 0334Receive Acceptance Mask 0 Extended Identifier <5:0> 0338——— 033A———— 033CReceive Acceptance Mask 1 Extended Identifier <5:0> 0340Transmit Buffer 2 Standard Identifier <10:6>— 0342Transmit Buffer 2 Extended Identifier <17:14>—— 0344Transmit Buffer 2 Extended Identifier <5:0> 0346Transmit Buffer 2 Byte 1 0348Transmit Buffer 2 Byte 3 034ATransmit Buffer 2 Byte 5 034CTransmit Buffer 2 Byte 7 034E—————— 0350Transmit Buffer 1 Standard Identifier <10:6>— Transmit Buffer 1 Extended Identifier <17:14>0352—— 0354Transmit Buffer 1 Extended Identifier <5:0> u = uninitialized bit; — = unimplemented bit, read as ‘’0Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descri ABLE 17 SFR Name 1RXF0SID 1RXF0EIDH 1RXF0EIDL 1RXF1SID 1RXF1EIDH 1RXF1EIDL 1RXF2SID 1RXF2EIDH 1RXF2EIDL 1RXF3SID 1RXF3EIDH 1RXF3EIDL 1RXF4SID 1RXF4EIDH 1RXF4EIDL 1RXF5SID 1RXF5EIDH 1RXF5EIDL 1RXM0SID 1RXM0EIDH 1RXM0EIDL 1RXM1SID 1RXM1EIDH 1RXM1EIDL 1TX2SID 1TX2EID 1TX2DLC 1TX2B1 1TX2B2 1TX2B3 1TX2B4 1TX2CON 1TX1SID 1TX1EID 1TX1DLC egend:ote1: T C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C LN DS70143E-page 118 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A u u u u 0 u u 0 u u u u 0 u u u u u u u 0 u u u u u u u 0 0 0 u 0 0 0 u u u u 0 u u 0 u u u u 0 u u u u u u u 0 u u u u u u u 0 0 0 u 0 0 0 u u u u 0 u u 0 u u u u 0 u u u u u u u 0 u u u u u u u 0 0 0 u 0 0 0 u u u u 0 u u u u u u u 0 u u u u u u u 0 u u u u u u u 0 0 0 u 0 0 0 State uuuu uuuu uuuu uuuu 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 uuuu uuuu 000u uuuu uuuu uuuu uuuu 0000 uuuu uuuu 000u uuuu uuuu uuuu uuuu 0000 1000 0000 uuuu 0000 0000 0000 et u u u u 0 0 0 u u u u u 0 u u u u u u u 0 u u u u u u u 0 0 0 u 0 0 0 s u u u u 0 0 0 u u u u u 0 u u u u u u u 0 u u u u u u u 0 0 0 u 0 0 0 e u u u u 0 0 0 u u u u u 0 u u u u u u u 0 u u u u u u u 0 1 0 u 0 0 0 R u u u u 0 u 0 u u u u u 0 u u u u u u u 0 u u u u u u u 0 0 0 0 0 0 0 u u u u 0 u u u u u u u 0 u 0 u u u u u 0 u 0 u u u u u 0 0 0 0 0 0 0 u u u u 0 u u u u u u u 0 0 0 u u u u u 0 0 0 u u u u u 0 0 0 0 0 0 0 u u u u 0 u u u u u u u 0 0 0 u u u u u 0 0 0 u u u u u 0 0 0 u 0 0 0 u u u u 0 u u u u u u u 0 0 0 u u u u u 0 0 0 u u u u u 0 0 0 0 0 0 0 Bit 2Bit 1Bit 0 —TXPRI<1:0> SRRTXIDE <13:6> ——— —TXPRI<1:0> SRRRXIDE DLC<3:0> FILHIT<2:0> SRRRXIDE DLC<3:0> DBENJTOFFFILHIT0 E<2:0>— > PRSEG<2:0> TX0IFRX1IFRX0IF TX0IERX1ERX0IE Bit 7Bit 6Bit 5Bit 4Bit 3 Transmit Buffer 1 Byte 0 Transmit Buffer 1 Byte 2 Transmit Buffer 1 Byte 4 Transmit Buffer 1 Byte 6 —TXABTTXLARBTXERRTXREQ Transmit Buffer 0 Standard Identifier <5:0> Transmit Buffer 0 Extended Identifier TXRB0DLC<3:0> Transmit Buffer 0 Byte 0 Transmit Buffer 0 Byte 2 Transmit Buffer 0 Byte 4 Transmit Buffer 0 Byte 6 —TXABTTXLARBTXERRTXREQ 1 Standard Identifier <10:0> eceive Buffer 1 Extended Identifier <17:6> ———RXRB0 Receive Buffer 1 Byte 0 Receive Buffer 1 Byte 2 Receive Buffer 1 Byte 4 Receive Buffer 1 Byte 6 RXFUL———RXRTRRO 0 Standard Identifier <10:0> eceive Buffer 0 Extended Identifier <17:6> ———RXRB0 Receive Buffer 0 Byte 0 Receive Buffer 0 Byte 2 Receive Buffer 0 Byte 4 Receive Buffer 0 Byte 6 RXFUL———RXRTRRO OPMODE<2:0>—ICOD SJW<1:0>BRP<5:0 SEG2PHTSSAMSEG1PH<2:0> IVRIFWAKIFERRIFTX2IFTX1IF IVRIEWAKIEERRIETX2IETX1IE Receive Error Count Register elds. D) Bit 10Bit 9Bit 8 ——— ——— ——— TXRTRTXRB1 ——— Receive Buffer R RXRTRRXRB1 ——— Receive Buffer R RXRTRRXRB1 ——— REQOP<2:0> ——— SEG2PH<2:0> TXWARRXWAREWARN ——— descriptions of register bit fi (1)-1:CAN1 REGISTER MAP (CONTINUE AddrBit 15Bit 14Bit 13Bit 12Bit 11 0356Transmit Buffer 1 Byte 1 0358Transmit Buffer 1 Byte 3 035ATransmit Buffer 1 Byte 5 035CTransmit Buffer 1 Byte 7 035E————— 0360Transmit Buffer 0 Standard Identifier <10:6> 0362Transmit Buffer 0 Extended Identifier <17:14>— 0364Transmit Buffer 0 Extended Identifier <5:0> 0366Transmit Buffer 0 Byte 1 0368Transmit Buffer 0 Byte 3 036ATransmit Buffer 0 Byte 5 036CTransmit Buffer 0 Byte 7 036E————— 0370——— 0372———— 0374Receive Buffer 1 Extended Identifier <5:0> 0376Receive Buffer 1 Byte 1 0378Receive Buffer 1 Byte 3 037AReceive Buffer 1 Byte 5 037CReceive Buffer 1 Byte 7 037E————— 0380——— 0382———— 0384Receive Buffer 0 Extended Identifier <5:0> 0386Receive Buffer 0 Byte 1 0388Receive Buffer 0 Byte 3 038AReceive Buffer 0 Byte 5 038CReceive Buffer 0 Byte 7 038E————— 0390CANCAP—CSIDLABATCANCKS 0392————— 0394—WAKFIL——— 0396RX0OVRRX1OVRTXBOTXEPRXEP 0398————— 039ATransmit Error Count Register u = uninitialized bit; — = unimplemented bit, read as ‘’0Refer to the “dsPIC30F Family Reference Manual” (DS70046) for 7 ABLE 1 SFR Name 1TX1B1 1TX1B2 1TX1B3 1TX1B4 1TX1CON 1TX0SID 1TX0EID 1TX0DLC 1TX0B1 1TX0B2 1TX0B3 1TX0B4 1TX0CON 1RX1SID 1RX1EID 1RX1DLC 1RX1B1 1RX1B2 1RX1B3 1RX1B4 1RX1CON 1RX0SID 1RX0EID 1RX0DLC 1RX0B1 1RX0B2 1RX0B3 1RX0B4 1RX0CON 1CTRL 1CFG1 1CFG2 1INTF 1INTE 1EC egend:ote1: T C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C LN © 2011 Microchip Technology Inc. DS70143E-page 119

dsPIC30F6011A/6012A/6013A/6014A u u 0u u0 u u 0 u u 0u u0 u u 0 u u 0u u0 u u0 u uu u 0 uu 0 0 u 00 u0 0 u 0 0 u 00 u0 0 u 0 0 u 00 u0 u u0 u uu u 0 uu 0 u u 0u u0 u u 0 u u 0u u0 u u 0 u u 0u u0 u u0 u uu u 0 uu 0 u u 0u u0 u u 0 u u 0u u0 u u 0 u u 0u u0 u uu u uu u 0 uu u State uuuu uuuu 0000 uuuu uuuu 0000 uuuu uuuu 0000 uuuu uuuu 0000 uuuu uuuu 0000 uuuu uuuu 0000 uuuu uuuu 0000 uuuu uuuu 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 uuuu uuuu uuuu et u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 u u 0 0 0 u u u u u 0 0 0 u s u u 0u u0 u u 0 u u 0u u0 u u 0 u u 0u u0 0 0u u uu u 0 00 u e u u uu uu u u u u u uu uu u u u u u uu uu 0 0u u uu u 0 00 u R u u uu uu u u u u u uu uu u u u u u uu uu u 0u u uu u 0 u0 u u 0 uu 0u u 0 u u 0 uu 0u u 0 u u 0 uu 0u u uu u uu u 0 uu u 0 0 u0 0u 0 0 u 0 0 u0 0u 0 0 u 0 0 u0 0u u uu u uu u 0 uu u 0 0 u0 0u 0 0 u 0 0 u0 0u 0 0 u 0 0 u0 0u u uu u uu u 0 uu u 0 0 u0 0u 0 0 u 0 0 u0 0u 0 0 u 0 0 u0 0u u uu u uu u 0 uu u Bit 0 EXIDE —EXIDE — EXIDE — EXIDE —EXIDE — EXIDE — MIDE —MIDE — TXIDE — <1:0> TXIDE — RI Bit 1 — —— — — — — —— — — — — —— — SRR — TXP SRR — > > Bit 2 — — — — — — — — <13:6— — <13:6 — er er (1)-2:CAN2 REGISTER MAP Addr.Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3 03C0———Receive Acceptance Filter 0 Standard Identifier <10:0> 03C2————Receive Acceptance Filter 0 Extended Identifier <17:6> 03C4Receive Acceptance Filter 0 Extended Identifier <5:0>——————————Receive Acceptance Filter 1 Standard Identifier <10:0>03C8 03CA————Receive Acceptance Filter 1 Extended Identifier <17:6>03CCReceive Acceptance Filter 1 Extended Identifier <5:0>——————— ———Receive Acceptance Filter 2 Standard Identifier <10:0>03D003D2————Receive Acceptance Filter 2 Extended Identifier <17:6> 03D4Receive Acceptance Filter 2 Extended Identifier <5:0>——————— ———Receive Acceptance Filter 3 Standard Identifier <10:0>03D8 03DA————Receive Acceptance Filter 3 Extended Identifier <17:6> 03DCReceive Acceptance Filter 3 Extended Identifier <5:0>——————————Receive Acceptance Filter 4 Standard Identifier <10:0>03E0 03E2————Receive Acceptance Filter 4 Extended Identifier <17:6>03E4Receive Acceptance Filter 4 Extended Identifier <5:0>——————— ———Receive Acceptance Filter 5 Standard Identifier <10:0>03E8 03EA————Receive Acceptance Filter 5 Extended Identifier <17:6> 03ECReceive Acceptance Filter 5 Extended Identifier <5:0>——————— ———Receive Acceptance Mask 0 Standard Identifier <10:0>03F0 03F2————Receive Acceptance Mask 0 Extended Identifier <17:6> 03F4Receive Acceptance Mask 0 Extended Identifier <5:0>——————————Receive Acceptance Mask 1 Standard Identifier <10:0>03F8 03FA————Receive Acceptance Mask 1 Extended Identifier <17:6>03FCReceive Acceptance Mask 1 Extended Identifier <5:0>——————— 0400Transmit Buffer 2 Standard Identifier <10:6>———Transmit Buffer 2 Standard Identifier <5:0> 0402Transmit Buffer 2 Extended Identifier <17:14>————Transmit Buffer 2 Extended Identifi0404Transmit Buffer 2 Extended Identifier <5:0>TXRTRTXRB1TXRB0DLC<3:0> 0406Transmit Buffer 2 Byte 1Transmit Buffer 2 Byte 0 0408Transmit Buffer 2 Byte 3Transmit Buffer 2 Byte 2040ATransmit Buffer 2 Byte 5Transmit Buffer 2 Byte 4 040CTransmit Buffer 2 Byte 7Transmit Buffer 2 Byte 6 040E—————————TXABTTXLARBTXERRTXREQ 0410Transmit Buffer 1 Standard Identifier <10:6>———Transmit Buffer 1 Standard Identifier <5:0>0412Transmit Buffer 1 Extended Identifier <17:14>————Transmit Buffer 1 Extended Identifi 0414Transmit Buffer 1 Extended Identifier <5:0>TXRTRTXRB1TXRB0DLC<3:0> u = uninitialized bit; — = unimplemented bit, read as ‘’0Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 17 SFR Name C2RXF0SID C2RXF0EIDH C2RXF0EIDLC2RXF1SID C2RXF1EIDHC2RXF1EIDL C2RXF2SID C2RXF2EIDH C2RXF2EIDL C2RXF3SID C2RXF3EIDH C2RXF3EIDLC2RXF4SID C2RXF4EIDHC2RXF4EIDL C2RXF5SID C2RXF5EIDH C2RXF5EIDL C2RXM0SID C2RXM0EIDH C2RXM0EIDLC2RXM1SID C2RXM1EIDHC2RXM1EIDL C2TX2SID C2TX2EIDC2TX2DLC C2TX2B1 C2TX2B2C2TX2B3 C2TX2B4 C2TX2CON C2TX1SIDC2TX1EID C2TX1DLC Legend:Note1: DS70143E-page 120 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A u uu u 0u u 0u u uu 0 uu u uu u u0 u uu u uu u 00 0 u 00 0 u uu u 0u u 0u u uu 0 uu u uu u u0 u uu u uu u 00 0 u 00 0 u uu u 0u u 0u u uu 0 uu u uu u u0 u uu u uu u 00 0 u 00 0 u uu u 0u u uu u uu 0 uu u uu u u0 u uu u uu u 00 0 u 00 0 State uuuu uuuu uuuu uuuu 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 uuuu uuuu 000u uuuu uuuu uuuu uuuu 0000 uuuu uuuu 000u uuuu uuuu uuuu uuuu 0000 1000 0000 uuuu 0000 0000 0000 et u u u u 0 0 0 u u u u u 0 u u u u u u u 0 u u u u u u u 0 0 0 u 0 0 0 s u uu u 00 0 uu u uu 0 uu u uu u u0 u uu u uu u 00 0 u 00 0 e u uu u 00 0 uu u uu 0 uu u uu u u0 u uu u uu u 01 0 u 00 0 R u uu u 0u 0 uu u uu 0 uu u uu u u0 u uu u uu u 00 0 0 00 0 u uu u 0u u uu u uu 0 u0 u uu u u0 u 0u u uu u 00 0 0 00 0 u uu u 0u u uu u uu 0 00 u uu u u0 0 0u u uu u 00 0 0 00 0 u uu u 0u u uu u uu 0 00 u uu u u0 0 0u u uu u 00 0 u 00 0 u uu u 0u u uu u uu 0 00 u uu u u0 0 0u u uu u 00 0 0 00 0 (1)-2:CAN2 REGISTER MAP (CONTINUED) Addr.Bit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 0416Transmit Buffer 1 Byte 1Transmit Buffer 1 Byte 0 0418Transmit Buffer 1 Byte 3Transmit Buffer 1 Byte 2041ATransmit Buffer 1 Byte 5Transmit Buffer 1 Byte 4 041CTransmit Buffer 1 Byte 7Transmit Buffer 1 Byte 6 041E—————————TXABTTXLARBTXERRTXREQ—TXPRI<1:0>0420Transmit Buffer 0 Standard Identifier <10:6>———Transmit Buffer 0 Standard Identifier <5:0>SRRTXIDE 0422Transmit Buffer 0 Extended Identifier <17:14>————Transmit Buffer 0 Extended Identifier <13:6> 0424Transmit Buffer 0 Extended Identifier <5:0>TXRTRTXRB1TXRB0DLC<3:0>———0426Transmit Buffer 0 Byte 1Transmit Buffer 0 Byte 0 0428Transmit Buffer 0 Byte 3Transmit Buffer 0 Byte 2 042ATransmit Buffer 0 Byte 5Transmit Buffer 0 Byte 4042CTransmit Buffer 0 Byte 7Transmit Buffer 0 Byte 6 042E—————————TXABTTXLARBTXERRTXREQ—TXPRI<1:0> 0430———Receive Buffer 1 Standard Identifier <10:0>SRRRXIDE0432————Receive Buffer 1 Extended Identifier <17:6> 0434Receive Buffer 1 Extended Identifier <5:0>RXRTRRXRB1———RXRB0DLC<3:0> 0436Receive Buffer 1 Byte 1Receive Buffer 1 Byte 00438Receive Buffer 1 Byte 3Receive Buffer 1 Byte 2 043AReceive Buffer 1 Byte 5Receive Buffer 1 Byte 4 043CReceive Buffer 1 Byte 7Receive Buffer 1 Byte 6043E————————RXFUL———RXRTRROFILHIT<2:0> 0440———Receive Buffer 0 Standard Identifier <10:0>SRRRXIDE 0442————Receive Buffer 0 Extended Identifier <17:6>0444Receive Buffer 0 Extended Identifier <5:0>RXRTRRXRB1———RXRB0DLC<3:0> 0446Receive Buffer 0 Byte 1Receive Buffer 0 Byte 0 0448Receive Buffer 0 Byte 3Receive Buffer 0 Byte 2044AReceive Buffer 0 Byte 5Receive Buffer 0 Byte 4 044CReceive Buffer 0 Byte 7Receive Buffer 0 Byte 6 044E————————RXFUL———RXRTRRODBENJTOFFFILHIT00450CANCAP—CSIDLEABATCANCKSREQOP<2:0>OPMODE<2:0>—ICODE<2:0>— 0452————————SJW<1:0>BRP<5:0> 0454—WAKFIL———SEG2PH<2:0>SEG2PHTSSAMSEG1PH<2:0>PRSEG<2:0> 0456RX0OVRRX1OVRTXBOTXEPRXEPTXWARRXWAREWARNIVRIFWAKIFERRIFTX2IFTX1IFTX0IFRX1IFRX0IF0458————————IVRIEWAKIEERRIETX2IETX1IETX0IERX1ERX0IE 045ATransmit Error Count RegisterReceive Error Count Register u = uninitialized bit; — = unimplemented bit, read as ‘’0Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 7 ABLE 1 SFR Name 2TX1B1 2TX1B22TX1B3 2TX1B4 2TX1CON2TX0SID 2TX0EID 2TX0DLC2TX0B1 2TX0B2 2TX0B32TX0B4 2TX0CON 2RX1SID2RX1EID 2RX1DLC 2RX1B12RX1B2 2RX1B3 2RX1B42RX1CON 2RX0SID 2RX0EID2RX0DLC 2RX0B1 2RX0B22RX0B3 2RX0B4 2RX0CON2CTRL 2CFG1 2CFG2 2INTF2INTE 2EC egend:ote1: T C CC C CC C CC C CC C CC C CC C CC C CC C CC C CC C C CC C LN DS70143E-page 121 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 122 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 18.0 DATA CONVERTER 18.2.3 CSDI PIN INTERFACE (DCI) MODULE The serial data input (CSDI) pin is configured as an input only pin when the module is enabled. Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not 18.2.3.1 COFS PIN intended to be a complete reference The Codec Frame Synchronization (COFS) pin is used source. For more information on the CPU, to synchronize data transfers that occur on the CSDO peripherals, register descriptions and and CSDI pins. The COFS pin may be configured as an general device functionality, refer to the input or an output. The data direction for the COFS pin “dsPIC30F Family Reference Manual” is determined by the COFSD control bit in the (DS70046). DCICON1 register. The DCI module accesses the shadow registers while 18.1 Module Introduction the CPU is in the process of accessing the memory The dsPIC30F Data Converter Interface (DCI) module mapped buffer registers. allows simple interfacing of devices, such as audio 18.2.4 BUFFER DATA ALIGNMENT coder/decoders (Codecs), ADC and DAC. The following interfaces are supported: Data values are always stored left justified in the buf- fers since most Codec data is represented as a signed • Framed Synchronous Serial Transfer (Single or 2’s complement fractional number. If the received word Multi-Channel) • Inter-IC Sound (I2S) Interface length is less than 16 bits, the unused LSbs in the receive buffer registers are set to ‘0’ by the module. If • AC-Link Compliant mode the transmitted word length is less than 16 bits, the The DCI module provides the following general unused LSbs in the transmit buffer register are ignored features: by the module. The word length setup is described in subsequent sections of this document. • Programmable word size up to 16 bits • Support for up to 16 time slots, for a maximum 18.2.5 TRANSMIT/RECEIVE SHIFT frame size of 256 bits REGISTER • Data buffering for up to 4 samples without CPU The DCI module has a 16-bit shift register for shifting overhead serial data in and out of the module. Data is shifted in/ out of the shift register MSb first, since audio PCM data 18.2 Module I/O Pins is transmitted in signed 2’s complement format. There are four I/O pins associated with the module. 18.2.6 DCI BUFFER CONTROL When enabled, the module controls the data direction of each of the four pins. The DCI module contains a buffer control unit for trans- ferring data between the shadow buffer memory and 18.2.1 CSCK PIN the serial shift register. The buffer control unit is a sim- The CSCK pin provides the serial clock for the DCI ple 2-bit address counter that points to word locations module. The CSCK pin may be configured as an input in the shadow buffer memory. For the receive memory or output using the CSCKD control bit in the DCICON1 space (high address portion of DCI buffer memory), the SFR. When configured as an output, the serial clock is address counter is concatenated with a ‘0’ in the MSb provided by the dsPIC30F. When configured as an location to form a 3-bit address. For the transmit mem- input, the serial clock must be provided by an external ory space (high portion of DCI buffer memory), the device. address counter is concatenated with a ‘1’ in the MSb location. 18.2.2 CSDO PIN Note: The DCI buffer control unit always The serial data output (CSDO) pin is configured as an accesses the same relative location in the output only pin when the module is enabled. The transmit and receive buffers, so only one CSDO pin drives the serial bus whenever data is to be address counter is provided. transmitted. The CSDO pin is tri-stated or driven to ‘0’ during CSCK periods when data is not transmitted, depending on the state of the CSDOM control bit. This allows other devices to place data on the serial bus during transmission periods not used by the DCI module. © 2011 Microchip Technology Inc. DS70143E-page 123

dsPIC30F6011A/6012A/6013A/6014A FIGURE 18-1: DCI MODULE BLOCK DIAGRAM BCG Control bits SCKD Sample Rate FOSC/4 CSCK Generator FSD Word Size Selection bits Frame Frame Length Selection bits Synchronization COFS DCI Mode Selection bits Generator s u B a at bit D RReecgeisivteer sB wuf/fSehr adow 6- 1 DCI Buffer Control Unit 15 0 Transmit Buffer DCI Shift Register CSDI Registers w/Shadow CSDO DS70143E-page 124 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 18.3 DCI Module Operation Frame lengths, up to 16 data words, may be selected. The frame length in CSCK periods can vary up to a 18.3.1 MODULE ENABLE maximum of 256 depending on the word size that is selected. The DCI module is enabled or disabled by setting/ clearing the DCIEN control bit in the DCICON1 SFR. Note: The COFSG control bits will have no Clearing the DCIEN control bit has the effect of reset- effect in AC-Link mode since the frame ting the module. In particular, all counters associated length is set to 256 CSCK periods by the with CSCK generation, frame sync, and the DCI buffer protocol. control unit are reset. 18.3.4 FRAME SYNC MODE The DCI clocks are shutdown when the DCIEN bit is cleared. CONTROL BITS When enabled, the DCI controls the data direction for The type of frame sync signal is selected using the the four I/O pins associated with the module. The Port, Frame Synchronization mode control bits LAT and TRIS register values for these I/O pins are (COFSM<1:0>) in the DCICON1 SFR. The following overridden by the DCI module when the DCIEN bit is set. operating modes can be selected: It is also possible to override the CSCK pin separately • Multi-Channel mode when the bit clock generator is enabled. This permits • I2S mode the bit clock generator to operate without enabling the • AC-Link mode (16-bit) rest of the DCI module. • AC-Link mode (20-bit) 18.3.2 WORD SIZE SELECTION BITS The operation of the COFSM control bits depends on whether the DCI module generates the frame sync The WS<3:0> word size selection bits in the DCICON2 signal as a master device, or receives the frame sync SFR determine the number of bits in each DCI data signal as a slave device. word. Essentially, the WS<3:0> bits determine the counting period for a 4-bit counter clocked from the The master device in a DSP/Codec pair is the device CSCK signal. that generates the frame sync signal. The frame sync signal initiates data transfers on the CSDI and CSDO Any data length, up to 16-bits, may be selected. The pins and usually has the same frequency as the data value loaded into the WS<3:0> bits is one less the sample rate (COFS). desired word length. For example, a 16-bit data word size is selected when WS<3:0> = 1111. The DCI module is a frame sync master if the COFSD control bit is cleared and is a frame sync slave if the Note: These WS<3:0> control bits are used only COFSD control bit is set. in the Multi-Channel and I2S modes. These bits have no effect in AC-Link mode since 18.3.5 MASTER FRAME SYNC the data slot sizes are fixed by the protocol. OPERATION 18.3.3 FRAME SYNC GENERATOR When the DCI module is operating as a frame sync master device (COFSD = 0), the COFSM mode bits The frame sync generator (COFSG) is a 4-bit counter determine the type of frame sync pulse that is that sets the frame length in data words. The frame generated by the frame sync generator logic. sync generator is incremented each time the word size A new COFS signal is generated when the frame sync counter is reset (refer to Section18.3.2 “Word Size generator resets to ‘0’. Selection Bits”). The period for the frame synchroni- zation generator is set by writing the COFSG<3:0> In the Multi-Channel mode, the frame sync pulse is control bits in the DCICON2 SFR. The COFSG period driven high for the CSCK period to initiate a data trans- in clock cycles is determined by the following formula: fer. The number of CSCK cycles between successive frame sync pulses will depend on the word size and EQUATION 18-1: COFSG PERIOD frame sync generator control bits. A timing diagram for the frame sync signal in Multi-Channel mode is shown Frame Length = Word Length • (FSG Value + 1) in Figure18-2. In the AC-Link mode of operation, the frame sync sig- nal has a fixed period and duty cycle. The AC-Link frame sync signal is high for 16 CSCK cycles and is low for 240 CSCK cycles. A timing diagram with the timing details at the start of an AC-Link frame is shown in Figure18-3. © 2011 Microchip Technology Inc. DS70143E-page 125

dsPIC30F6011A/6012A/6013A/6014A In the I2S mode, a frame sync signal having a 50% duty In the I2S mode, a new data word will be transferred cycle is generated. The period of the I2S frame sync one CSCK cycle after a low-to-high or a high-to-low signal in CSCK cycles is determined by the word size transition is sampled on the COFS pin. A rising or fall- and frame sync generator control bits. A new I2S data ing edge on the COFS pin resets the frame sync transfer boundary is marked by a high-to-low or a generator logic. low-to-high transition edge on the COFS pin. In the AC-Link mode, the tag slot and subsequent data slots for the next frame will be transferred one CSCK 18.3.6 SLAVE FRAME SYNC OPERATION cycle after the COFS pin is sampled high. When the DCI module is operating as a frame sync The COFSG and WS bits must be configured to pro- slave (COFSD = 1), data transfers are controlled by the vide the proper frame length when the module is oper- Codec device attached to the DCI module. The ating in the Slave mode. Once a valid frame sync pulse COFSM control bits control how the DCI module has been sampled by the module on the COFS pin, an responds to incoming COFS signals. entire data frame transfer will take place. The module In the Multi-Channel mode, a new data frame transfer will not respond to further frame sync pulses until the will begin one CSCK cycle after the COFS pin is sam- data frame transfer has completed. pled high (see Figure18-2). The pulse on the COFS pin resets the frame sync generator logic. FIGURE 18-2: FRAME SYNC TIMING, MULTI-CHANNEL MODE CSCK COFS CSDI/CSDO MSB LSB FIGURE 18-3: FRAME SYNC TIMING, AC-LINK START OF FRAME BIT_CLK CSDO or CSDI S12 S12 S12 Tag Tag Tag bit 2 bit 1 LSb MSb bit 14 bit 13 SYNC FIGURE 18-4: I2S INTERFACE FRAME SYNC TIMING CSCK CSDI or CSDO MSB LSB MSB LSB WS Note: A 5-bit transfer is shown here for illustration purposes. The I2S protocol does not specify word length – this will be system dependent. DS70143E-page 126 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 18.3.7 BIT CLOCK GENERATOR EQUATION 18-2: BIT CLOCK FREQUENCY The DCI module has a dedicated 12-bit time base that produces the bit clock. The bit clock rate (period) is set FCY FBCK = by writing a non-zero 12-bit value to the BCG<11:0> 2 • (BCG + 1) control bits in the DCICON3 SFR. When the BCG<11:0> bits are set to zero, the bit clock The required bit clock frequency will be determined by will be disabled. If the BCG<11:0> bits are set to a non- the system sampling rate and frame size. Typical bit zero value, the bit clock generator is enabled. These clock frequencies range from 16x to 512x the converter bits should be set to ‘0’ and the CSCKD bit set to ‘1’ if sample rate depending on the data converter and the the serial clock for the DCI is received from an external communication protocol that is used. device. To achieve bit clock frequencies associated with com- The formula for the bit clock frequency is given in mon audio sampling rates, the user will need to select Equation18-2. a crystal frequency that has an ‘even’ binary value. Examples of such crystal frequencies are listed in Table18-1. TABLE 18-1: DEVICE FREQUENCIES FOR COMMON CODEC CSCK FREQUENCIES FS (kHz) FCSCK/FS FCSCK (MHz)(1) FOSC (MHZ) PLL FCY (MIPS) BCG(2) 8 256 2.048 8.192 4 8.192 1 12 256 3.072 6.144 8 12.288 1 32 32 1.024 8.192 8 16.384 7 44.1 32 1.4112 5.6448 8 11.2896 3 48 64 3.072 6.144 16 24.576 3 Note1: When the CSCK signal is applied externally (CSCKD = 1), the external clock high and low times must meet the device timing requirements. 2: When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the operation of the DCI module. © 2011 Microchip Technology Inc. DS70143E-page 127

dsPIC30F6011A/6012A/6013A/6014A 18.3.8 SAMPLE CLOCK EDGE 18.3.11 RECEIVE SLOT ENABLE BITS CONTROL BIT The RSCON SFR contains control bits that are used to The sample clock edge (CSCKE) control bit determines enable up to 16 time slots for reception. These control the sampling edge for the CSCK signal. If the CSCK bit bits are the RSE<15:0> bits. The size of each receive is cleared (default), data will be sampled on the falling time slot is determined by the WS<3:0> word size edge of the CSCK signal. The AC-Link protocols and selection bits and can vary from 1 to 16 bits. most Multi-Channel formats require that data be sam- If a receive time slot is enabled via one of the RSE bits pled on the falling edge of the CSCK signal. If the (RSEx = 1), the shift register contents will be written to CSCK bit is set, data will be sampled on the rising edge the current DCI receive shadow buffer location and the of CSCK. The I2S protocol requires that data be buffer control unit will be incremented to point to the sampled on the rising edge of the CSCK signal. next buffer location. 18.3.9 DATA JUSTIFICATION Data is not packed in the receive memory buffer loca- CONTROL BIT tions if the selected word size is less than 16 bits. Each received slot data word is stored in a separate 16-bit In most applications, the data transfer begins one buffer location. Data is always stored in a left justified CSCK cycle after the COFS signal is sampled active. format in the receive memory buffer. This is the default configuration of the DCI module. An alternate data alignment can be selected by setting the 18.3.12 SLOT ENABLE BITS OPERATION DJST control bit in the DCICON1 SFR. When DJST = 1, WITH FRAME SYNC data transfers will begin during the same CSCK cycle The TSE and RSE control bits operate in concert with when the COFS signal is sampled active. the DCI frame sync generator. In the Master mode, a 18.3.10 TRANSMIT SLOT ENABLE BITS COFS signal is generated whenever the frame sync generator is reset. In the Slave mode, the frame sync The TSCON SFR has control bits that are used to generator is reset whenever a COFS pulse is received. enable up to 16 time slots for transmission. These con- trol bits are the TSE<15:0> bits. The size of each time The TSE and RSE control bits allow up to 16 consecu- slot is determined by the WS<3:0> word size selection tive time slots to be enabled for transmit or receive. bits and can vary up to 16 bits. After the last enabled time slot has been transmitted/ received, the DCI will stop buffering data until the next If a transmit time slot is enabled via one of the TSE bits occurring COFS pulse. (TSEx = 1), the contents of the current transmit shadow buffer location will be loaded into the CSDO Shift regis- 18.3.13 SYNCHRONOUS DATA ter and the DCI buffer control unit is incremented to TRANSFERS point to the next location. The DCI buffer control unit will be incremented by one During an unused transmit time slot, the CSDO pin will word location whenever a given time slot has been drive ‘0’s or will be tri-stated during all disabled time enabled for transmission or reception. In most cases, slots depending on the state of the CSDOM bit in the data input and output transfers will be synchronized, DCICON1 SFR. which means that a data sample is received for a given The data frame size in bits is determined by the chosen channel at the same time a data sample is transmitted. data word size and the number of data word elements Therefore, the transmit and receive buffers will be filled in the frame. If the chosen frame size has less than 16 with equal amounts of data when a DCI interrupt is elements, the additional slot enable bits will have no generated. effect. In some cases, the amount of data transmitted and Each transmit data word is written to the 16-bit transmit received during a data frame may not be equal. As an buffer as left justified data. If the selected word size is example, assume a two-word data frame is used. Fur- less than 16 bits, then the LSbs of the transmit buffer thermore, assume that data is only received during memory will have no effect on the transmitted data. The slot#0 but is transmitted during slot #0 and slot #1. In user should write ‘0’s to the unused LSbs of each this case, the buffer control unit counter would be incre- transmit buffer location. mented twice during a data frame but only one receive register location would be filled with data. DS70143E-page 128 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 18.3.14 BUFFER LENGTH CONTROL 18.3.16 TRANSMIT STATUS BITS The amount of data that is buffered between interrupts There are two transmit status bits in the DCISTAT SFR. is determined by the buffer length (BLEN<1:0>) control The TMPTY bit is set when the contents of the transmit bits in the DCICON1 SFR. The size of the transmit and buffer registers are transferred to the transmit shadow receive buffers may be varied from 1 to 4 data words registers. The TMPTY bit may be polled in software to using the BLEN control bits. The BLEN control bits are determine when the transmit buffer registers may be compared to the current value of the DCI buffer control written. The TMPTY bit is cleared automatically by the unit address counter. When the 2 LSbs of the DCI hardware when a write to one of the four transmit address counter match the BLEN<1:0> value, the buf- buffers occurs. fer control unit will be reset to ‘0’. In addition, the con- tents of the receive shadow registers are transferred to The TUNF bit is read only and indicates that a transmit the receive buffer registers and the contents of the underflow has occurred for at least one of the transmit transmit buffer registers are transferred to the transmit buffer registers that is in use. The TUNF bit is set at the shadow registers. time the transmit buffer registers are transferred to the transmit shadow registers. The TUNF status bit is 18.3.15 BUFFER ALIGNMENT WITH DATA cleared automatically when the buffer register that FRAMES underflowed is written by the CPU. There is no direct coupling between the position of the Note: The transmit status bits only indicate sta- AGU address pointer and the data frame boundaries. tus for buffer locations that are used by the This means that there will be an implied assignment of module. If the buffer length is set to less each transmit and receive buffer that is a function of the than four words, for example, the unused BLEN control bits and the number of enabled data slots buffer locations will not affect the transmit via the TSE and RSE control bits. status bits. As an example, assume that a 4-word data frame is 18.3.17 RECEIVE STATUS BITS chosen and that we want to transmit on all four time slots in the frame. This configuration would be estab- There are two receive status bits in the DCISTAT SFR. lished by setting the TSE0, TSE1, TSE2 and TSE3 The RFUL status bit is read only and indicates that new control bits in the TSCON SFR. With this module setup, data is available in the receive buffers. The RFUL bit is the TXBUF0 register would naturally be assigned to cleared automatically when all receive buffers in use slot #0, the TXBUF1 register would naturally be have been read by the CPU. assigned to slot #1, and so on. The ROV status bit is read only and indicates that a Note: When more than four time slots are active receive overflow has occurred for at least one of the within a data frame, the user code must receive buffer locations. A receive overflow occurs keep track of which time slots are to be when the buffer location is not read by the CPU before read/written at each interrupt. In some new data is transferred from the shadow registers. The cases, the alignment between transmit/ ROV status bit is cleared automatically when the buffer receive buffers and their respective slot register that caused the overflow is read by the CPU. assignments could be lost. Examples of When a receive overflow occurs for a specific buffer such cases include an emulation break- location, the old contents of the buffer are overwritten. point or a hardware trap. In these situa- tions, the user should poll the SLOT status Note: The receive status bits only indicate status bits to determine what data should be for buffer locations that are used by the loaded into the buffer registers to module. If the buffer length is set to less resynchronize the software with the DCI than four words, for example, the unused module. buffer locations will not affect the transmit status bits. © 2011 Microchip Technology Inc. DS70143E-page 129

dsPIC30F6011A/6012A/6013A/6014A 18.3.18 SLOT STATUS BITS 18.5 DCI Module Operation During CPU Sleep and Idle Modes The SLOT<3:0> status bits in the DCISTAT SFR indi- cate the current active time slot. These bits will corre- 18.5.1 DCI MODULE OPERATION DURING spond to the value of the frame sync generator counter. The user may poll these status bits in software when a CPU SLEEP MODE DCI interrupt occurs to determine what time slot data The DCI module has the ability to operate while in was last received and which time slot data should be Sleep mode and wake the CPU when the CSCK signal loaded into the TXBUF registers. is supplied by an external device (CSCKD = 1). The DCI module will generate an asynchronous interrupt 18.3.19 CSDO MODE BIT when a DCI buffer transfer has completed and the CPU The CSDOM control bit controls the behavior of the is in Sleep mode. CSDO pin during unused transmit slots. A given trans- mit time slot is unused if it’s corresponding TSEx bit in 18.5.2 DCI MODULE OPERATION DURING the TSCON SFR is cleared. CPU IDLE MODE If the CSDOM bit is cleared (default), the CSDO pin will If the DCISIDL control bit is cleared (default), the mod- be low during unused time slot periods. This mode will ule will continue to operate normally even in Idle mode. be used when there are only two devices attached to If the DCISIDL bit is set, the module will halt when Idle the serial bus. mode is asserted. If the CSDOM bit is set, the CSDO pin will be tri-stated 18.6 AC-Link Mode Operation during unused time slot periods. This mode allows mul- tiple devices to share the same CSDO line in a multi- The AC-Link protocol is a 256-bit frame with one 16-bit channel application. Each device on the CSDO line is data slot, followed by twelve 20-bit data slots. The DCI configured so that it will only transmit data during module has two Operating modes for the AC-Link pro- specific time slots. No two devices will transmit data tocol. These Operating modes are selected by the during the same time slot. COFSM<1:0> control bits in the DCICON1 SFR. The first AC-Link mode is called ‘16-bit AC-Link mode’ and 18.3.20 DIGITAL LOOPBACK MODE is selected by setting COFSM<1:0> = 10. The second Digital Loopback mode is enabled by setting the AC-Link mode is called ‘20-bit AC-Link mode’ and is DLOOP control bit in the DCICON1 SFR. When the selected by setting COFSM<1:0> = 11. DLOOP bit is set, the module internally connects the CSDO signal to CSDI. The actual data input on the 18.6.1 16-BIT AC-LINK MODE CSDI I/O pin will be ignored in Digital Loopback mode. In the 16-bit AC-Link mode, data word lengths are restricted to 16 bits. Note that this restriction only 18.3.21 UNDERFLOW MODE CONTROL BIT affects the 20-bit data time slots of the AC-Link proto- When an underflow occurs, one of two actions may col. For received time slots, the incoming data is simply occur depending on the state of the Underflow mode truncated to 16 bits. For outgoing time slots, the 4 LSbs (UNFM) control bit in the DCICON1 SFR. If the UNFM of the data word are set to ‘0’ by the module. This trun- bit is cleared (default), the module will transmit ‘0’s on cation of the time slots limits the ADC and DAC data to the CSDO pin during the active time slot for the buffer 16 bits, but permits proper data alignment in the location. In this Operating mode, the Codec device TXBUF and RXBUF registers. Each RXBUF and attached to the DCI module will simply be fed digital TXBUF register will contain one data time slot value. ‘silence’. If the UNFM control bit is set, the module will transmit the last data written to the buffer location. This 18.6.2 20-BIT AC-LINK MODE Operating mode permits the user to send continuous The 20-bit AC-Link mode allows all bits in the data time data to the Codec device without consuming CPU slots to be transmitted and received but does not main- overhead. tain data alignment in the TXBUF and RXBUF registers. 18.4 DCI Module Interrupts The 20-bit AC-Link mode functions similar to the Multi- The frequency of DCI module interrupts is dependent Channel mode of the DCI module, except for the duty on the BLEN<1:0> control bits in the DCICON2 SFR. cycle of the frame synchronization signal. The AC-Link An interrupt to the CPU is generated each time the set frame synchronization signal should remain high for 16 buffer length has been reached and a shadow register CSCK cycles and should be low for the following transfer takes place. A shadow register transfer is 240cycles. defined as the time when the previously written TXBUF values are transferred to the transmit shadow registers and new received values in the receive shadow registers are transferred into the RXBUF registers. DS70143E-page 130 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A The 20-bit mode treats each 256-bit AC-Link frame as 18.7.1 I2S FRAME AND DATA WORD sixteen, 16-bit time slots. In the 20-bit AC-Link mode, LENGTH SELECTION the module operates as if COFSG<3:0> = 1111 and The WS and COFSG control bits are set to produce the WS<3:0> = 1111. The data alignment for 20-bit data period for one half of an I2S data frame. That is, the slots is ignored. For example, an entire AC-Link data frame length is the total number of CSCK cycles frame can be transmitted and received in a packed required for a left or a right data word transfer. fashion by setting all bits in the TSCON and RSCON SFRs. Since the total available buffer length is 64 bits, The BLEN bits must be set for the desired buffer length. it would take 4 consecutive interrupts to transfer the Setting BLEN<1:0> = 01 will produce a CPU interrupt, AC-Link frame. The application software must keep once per I2S frame. track of the current AC-Link frame segment. 18.7.2 I2S DATA JUSTIFICATION 18.7 I2S Mode Operation As per the I2S specification, a data word transfer will, by default, begin one CSCK cycle after a transition of the The DCI module is configured for I2S mode by writing WS signal. A MSb left justified option can be selected a value of ‘01’ to the COFSM<1:0> control bits in the using the DJST control bit in the DCICON1 SFR. DCICON1 SFR. When operating in the I2S mode, the DCI module will generate frame synchronization sig- If DJST = 1, the I2S data transfers will be MSb left jus- nals with a 50% duty cycle. Each edge of the frame tified. The MSb of the data word will be presented on synchronization signal marks the boundary of a new the CSDO pin during the same CSCK cycle as the ris- data word transfer. ing or falling edge of the COFS signal. The CSDO pin is tri-stated after the data word has been sent. The user must also select the frame length and data word size using the COFSG and WS control bits in the DCICON2 SFR. © 2011 Microchip Technology Inc. DS70143E-page 131

dsPIC30F6011A/6012A/6013A/6014A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Stat 000 000 000 000 000 000 000 000 000 000 000 000 000 000 et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 0 OFSM0 MPTY TSE0 RSE0 C T 1 Bit 1 OFSM <3:0> TUNF TSE1 RSE1 C S W Bit 2 — RFUL TSE2 RSE2 Bit 3 — ROV TSE3 RSE3 Bit 4 — — — TSE4 RSE4 Bit 5 DJST 0> — TSE5 RSE5 1: Bit 8Bit 7Bit 6 COFSDUNFMCSDOM COFSG<3:0> BCG<1 SLOT0—— TSE8TSE7TSE6 RSE8RSE7RSE6 Buffer 0 Data Register Buffer 1 Data Register Buffer 2 Data Register Buffer 3 Data Register Buffer 0 Data Register Buffer 1 Data Register Buffer 2 Data Register Buffer 3 Data Register gister bit fields. Bit 9 CSCKE — SLOT1 TSE9 RSE9 Receive Receive Receive Receive Transmit Transmit Transmit Transmit ptions of re Bit 10 CSCKD BLEN0 SLOT2 TSE10 RSE10 or descri 6) f Bit 11 DLOOP BLEN1 SLOT3 TSE11 RSE11 DS7004 1) Bit 12 — — — — TSE12 RSE12 e Manual” ( (DCI REGISTER MAP Bit 15Bit 14Bit 13 DCIEN—DCISIDL ——— ——— ——— TSE15TSE14TSE13 RSE15RSE14RSE13 mplemented bit, read as ‘’0he “dsPIC30F Family Referenc 2: ddr. 240 242 244 246 248 24C 250 252 254 256 258 25A 25C 25E — = uniefer to t - A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 8 1 ABLE FR Name CICON1 CICON2 CICON3 CISTAT SCON SCON XBUF0 XBUF1 XBUF2 XBUF3 XBUF0 XBUF1 XBUF2 XBUF3 egend:ote1: T S D D D D T R R R R R T T T T LN DS70143E-page 132 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 19.0 12-BIT ANALOG-TO-DIGITAL The ADC module has six 16-bit registers: CONVERTER (ADC) MODULE • ADC Control Register 1 (ADCON1) • ADC Control Register 2 (ADCON2) Note: This data sheet summarizes features of • ADC Control Register 3 (ADCON3) this group ofdsPIC30F devices and is not • ADC Input Select Register (ADCHS) intended to be a complete reference source. For more information on the CPU, • ADC Port Configuration Register (ADPCFG) peripherals, register descriptions and • ADC Input Scan Selection Register (ADCSSL) general device functionality, refer to the The ADCON1, ADCON2 and ADCON3 registers con- “dsPIC30F Family Reference Manual” trol the operation of the ADC module. The ADCHS reg- (DS70046). ister selects the input channels to be converted. The ADPCFG register configures the port pins as analog The 12-bit Analog-to-Digital Converter (ADC) allows inputs or as digital I/O. The ADCSSL register selects conversion of an analog input signal to a 12-bit digital inputs for scanning. number. This module is based on a Successive Approximation Register (SAR) architecture and pro- Note: The SSRC<2:0>, ASAM, SMPI<3:0>, vides a maximum sampling rate of 200ksps. The ADC BUFM and ALTS bits, as well as the module has up to 16 analog inputs which are multi- ADCON3 and ADCSSL registers, must plexed into a sample and hold amplifier. The output of not be written to while ADON = 1. This the sample and hold is the input into the converter would lead to indeterminate results. which generates the result. The analog reference volt- age is software selectable to either the device supply The block diagram of the 12-bit ADC module is shown voltage (AVDD/AVSS) or the voltage level on the in Figure19-1. (VREF+/VREF-) pin. The ADC has a unique feature of being able to operate while the device is in Sleep mode with RC oscillator selection. FIGURE 19-1: 12-BIT ADC FUNCTIONAL BLOCK DIAGRAM AVDD AVSS VREF+ VREF- 0000 Comparator AN0 DAC 0001 AN1 0010 AN2 0011 12-bit SAR Conversion Logic AN3 0100 AANN45 0101 16-Dwuoardl ,P 1o2r-tbit DataFormat RAM AN6 0110 ace erf AN7 0111 s Int AN8 1000 Sample SamplCeo/Snetrqoulence Bu 1001 AN9 1010 Input AN10 Switches Input MUX 1011 Control AN11 1100 AN12 1101 AN13 1110 AN14 1111 AN15 VREF- S/H CH0 AN1 © 2011 Microchip Technology Inc. DS70143E-page 133

dsPIC30F6011A/6012A/6013A/6014A 19.1 ADC Result Buffer 19.3 Selecting the Conversion Sequence The module contains a 16-word dual port read only buf- fer, called ADCBUF0...ADCBUFF, to buffer the ADC Several groups of control bits select the sequence in results. The RAM is 12 bits wide but the data obtained which the ADC connects inputs to the sample/hold is represented in one of four different 16-bit data for- channel, converts a channel, writes the buffer memory mats. The contents of the sixteen ADC Result Buffer and generates interrupts. registers, ADCBUF0 through ADCBUFF, cannot be The sequence is controlled by the sampling clocks. written by user software. The SMPI bits select the number of acquisition/ 19.2 Conversion Operation conversion sequences that would be performed before an interrupt occurs. This can vary from 1 sample per After the ADC module has been configured, the sample interrupt to 16 samples per interrupt. acquisition is started by setting the SAMP bit. Various The BUFM bit will split the 16-word results buffer into sources, such as a programmable bit, timer time-outs two 8-word groups. Writing to the 8-word buffers will be and external events, will terminate acquisition and start alternated on each interrupt event. a conversion. When the A/D conversion is complete, the result is loaded into ADCBUF0...ADCBUFF, and Use of the BUFM bit will depend on how much time is the DONE bit and the ADC interrupt flag ADIF are set available for the moving of the buffers after the after the number of samples specified by the SMPI bit. interrupt. The ADC module can be configured for different inter- If the processor can quickly unload a full buffer within rupt rates as described in Section19.3 “Selecting the the time it takes to acquire and convert one channel, Conversion Sequence”. the BUFM bit can be ‘0’ and up to 16 conversions (cor- Use the following steps to perform an Analog-to-Digital responding to the 16 input channels) may be done per conversion: interrupt. The processor will have one acquisition and conversion time to move the sixteen conversions. 1. Configure the ADC module: If the processor cannot unload the buffer within the a) Configure the analog pins, voltage refer- acquisition and conversion time, the BUFM bit should be ence and digital I/O. ‘1’. For example, if SMPI<3:0> (ADCON2<5:2>) = 0111, b) Select the ADC input channels. then eight conversions will be loaded into 1/2 of the c) Select the ADC conversion clock. buffer, following which an interrupt occurs. The next d) Select the ADC conversion trigger. eight conversions will be loaded into the other 1/2 of the e) Turn on the ADC module. buffer. The processor will have the entire time between 2. Configure ADC interrupt (if required): interrupts to move the eight conversions. a) Clear the ADIF bit. The ALTS bit can be used to alternate the inputs b) Select the ADC interrupt priority. selected during the sampling sequence. The input multiplexer has two sets of sample inputs: MUX A and 3. Start sampling. MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are 4. Wait the required acquisition time. selected for sampling. If the ALTS bit is ‘1’ and 5. Trigger acquisition end, start conversion: SMPI<3:0> = 0000 on the first sample/convert 6. Wait for ADC conversion to complete, by either: sequence, the MUX A inputs are selected and, on the • Waiting for the ADC interrupt, or next acquire/convert sequence, the MUX B inputs are selected. • Waiting for the DONE bit to get set. 7. Read ADC result buffer, clear ADIF if required. The CSCNA bit (ADCON2<10>) will allow the multi- plexer input to be alternately scanned across a selected number of analog inputs for the MUX A group. The inputs are selected by the ADCSSL register. If a particular bit in the ADCSSL register is ‘1’, the corre- sponding input is selected. The inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. If the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. DS70143E-page 134 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 19.4 Programming the Start of The internal RC oscillator is selected by setting the Conversion Trigger ADRC bit. For correct ADC conversions, the ADC conversion The conversion trigger will terminate acquisition and clock (TAD) must be selected to ensure a minimum TAD start the requested conversions. time of 334 nsec (for VDD = 5V). Refer to Section23.0 The SSRC<2:0> bits select the source of the “Electrical Characteristics” for minimum TAD under conversion trigger. The SSRC bits provide for up to four other operating conditions. alternate sources of conversion trigger. Example19-1 shows a sample calculation for the When SSRC<2:0> = 000, the conversion trigger is ADCS<5:0> bits, assuming a device operating speed under software control. Clearing the SAMP bit will of 30 MIPS. cause the conversion trigger event after ~11 TAD. When SSRC<2:0> = 111 (Auto-Start mode), the con- EXAMPLE 19-1: ADC CONVERSION version trigger is under ADC clock control. The SAMC CLOCK AND SAMPLING bits select the number of ADC clocks between the start RATE CALCULATION of acquisition and the start of conversion. This provides the fastest conversion rates on multiple channels. Minimum TAD = 334 nsec SAMC must always be at least one clock cycle. TCY = 33 .33 nsec (30 MIPS) Other trigger sources can come from timer modules or TAD ADCS<5:0> = 2 – 1 external interrupts. TCY 334 nsec = 2 • – 1 33.33 nsec 19.5 Aborting a Conversion = 19.04 Clearing the ADON bit during a conversion will abort Therefore, the current conversion and stop the sampling sequenc- Set ADCS<5:0> = 19 ing until the next sampling trigger. The ADCBUF will not be updated with the partially completed ADC conver- TCY Actual TAD = (ADCS<5:0> + 1) sion sample. That is, the ADCBUF will continue to con- 2 tain the value of the last completed conversion (or the 33.33 nsec = (19 + 1) last value written to the ADCBUF register). 2 If the clearing of the ADON bit coincides with an auto- = 334 nsec start, the clearing has a higher priority and a new conversion will not start. If SSRC<2:0> = ‘111’ and SAMC<4:0> = ‘00001’ Since, 19.6 Selecting the ADC Conversion Sampling Time = Acquisition Time + Conversion Time Clock = 1 TAD + 14 TAD The ADC conversion requires 14 TAD. The source of = 15 x 334 nsec the ADC conversion clock is software selected, using a Therefore, 1 6-bit counter. There are 64 possible options for TAD. Sampling Rate = (15 x 334 nsec) EQUATION 19-1: ADC CONVERSION = ~200 kHz CLOCK TAD = TCY * (0.5*(ADCS<5:0> + 1)) © 2011 Microchip Technology Inc. DS70143E-page 135

dsPIC30F6011A/6012A/6013A/6014A 19.7 ADC Speeds The dsPIC30F 12-bit ADC specifications permit a max- imum of 200 ksps sampling rate. The table below sum- marizes the conversion speeds for the dsPIC30F 12-bit ADC and the required operating conditions. TABLE 19-1: 12-BIT ADC EXTENDED CONVERSION RATES dsPIC30F 12-bit ADC Conversion Rates TAD Sampling Speed Minimum Time Min Rs Max VDD Temperature Channels Configuration Up to 200 334 ns 1 TAD 2.5 kΩ 4.5V -40°C to +85°C ksps(1) to VREF- VREF+ 5.5V ANx CHX S/H ADC Up to 100 668 ns 1 TAD 2.5 kΩ 3.0V -40°C to +125°C ksps to VRoErF- VRoErF+ 5.5V AVSS AVDD ANx CHX S/H ADC ANx or VREF- Note1: External VREF- and VREF+ pins must be used for correct operation. See Figure19-2 for recommended circuit. DS70143E-page 136 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A The following figure depicts the recommended circuit for the conversion rates above 100 ksps. The dsPIC30F6014A is shown as an example. FIGURE 19-2: ADC VOLTAGE REFERENCE SCHEMATIC VDD 0 9 8 7 6 5 4 3 2 D S 9 8 7 6 54 3 21 8 7 7 7 7 7 7 7 7 D S 6 6 6 6 66 6 66 V V 1 60 2 59 3 58 4 57 See Note 1: 5 56 6 55 VDD VDD VDD 7 54 C8 C7 C6 8 53 1 μF 0.1 μF 0.01 μF 9 52 10 dsPIC30F6014A VSS VDD VSS 50 VDD 49 VDD 13 VDD 14 47 AVDD AVDD AVDD 15 46 16 45 C5 C4 C3 17 44 1 μF 0.1 μF 0.01 μF 18 43 19 42 VDD 20 -EF +EF DD SS S D 41 1 2 R R V V 7 8 9 0 S D 3 4 5 6 7 8 9 0 R2 2 2 V V A A 2 2 2 3 V V 3 3 3 3 3 3 3 4 10 C2 C1 R1 VDD 0.1 μF 0.01 μF 10 VDD Note 1: Ensure adequate bypass capacitors are provided on each VDD pin. The configuration procedures below give the required • Configure the ADC clock period to be: setup values for the conversion speeds above 100 1 ksps. = 334 ns (14 + 1) x 200,000 19.7.1 200 KSPS CONFIGURATION GUIDELINE by writing to the ADCS<5:0> control bits in the ADCON3 register. The following configuration items are required to achieve a 200 ksps conversion rate. • Configure the sampling time to be 1 TAD by writing: SAMC<4:0> = 00001. • Comply with conditions provided in Table19-2. The following figure shows the timing diagram of the • Connect external VREF+ and VREF- pins following the recommended circuit as shown in Figure19-2. ADC running at 200 ksps. The TAD selection in conjunc- tion with the guidelines described above allows a con- • Set SSRC<2.0> = 111 in the ADCON1 register to version speed of 200 ksps. See Example19-1 for code enable the auto convert option. example. • Enable automatic sampling by setting the ASAM control bit in the ADCON1 register. • Write the SMPI<3.0> control bits in the ADCON2 register for the desired number of conversions between interrupts. © 2011 Microchip Technology Inc. DS70143E-page 137

dsPIC30F6011A/6012A/6013A/6014A FIGURE 19-3: CONVERTING 1 CHANNEL AT 200 KSPS, AUTO-SAMPLE START, 1 TAD SAMPLING TIME TSAMP TSAMP = 1 TAD = 1 TAD ADCLK TCONV TCONV = 14 TAD = 14 TAD SAMP DONE ADCBUF0 ADCBUF1 Instruction Execution BSET ADCON1, ASAM 19.8 ADC Acquisition Requirements to charge the capacitor CHOLD. The combined impedance of the analog sources must therefore be The analog input model of the 12-bit ADC isshown in small enough to fully charge the holding capacitor Figure19-4. The total sampling time for the ADC is a within the chosen sample time. To minimize the effects function of the internal amplifier settling time and the of pin leakage currents on the accuracy of the ADC, the holding capacitor charge time. maximum recommended source impedance, RS, is 2.5 For the ADC to meet its specified accuracy, the charge kΩ. After the analog input channel is selected holding capacitor (CHOLD) must be allowed to fully (changed), this sampling function must be completed charge to the voltage level on the analog input pin. The prior to starting the conversion. The internal holding source impedance (RS), the interconnect impedance capacitor will be in a discharged state prior to each (RIC) and the internal sampling switch (RSS) sample operation. impedance combine to directly affect the time required FIGURE 19-4: 12-BIT ADC ANALOG INPUT MODEL VDD RIC ≤ 250Ω Sampling RSS ≤ 3 kΩ Switch VT = 0.6V Rs ANx RSS CHOLD VA CPIN I leakage = DAC capacitance VT = 0.6V ± 500 nA = 18 pF VSS Legend: CPIN = input capacitance VT = threshold voltage I leakage = leakage current at the pin due to various junctions RIC = interconnect resistance RSS = sampling switch resistance CHOLD = sample/hold capacitance (from DAC) Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 2.5 kΩ. DS70143E-page 138 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 19.9 Module Power-down Modes If the ADC interrupt is enabled, the device will wake-up from Sleep. If the ADC interrupt is not enabled, the The module has 2 internal Power modes. ADC module will then be turned off, although the When the ADON bit is ‘1’, the module is in Active mode; ADON bit will remain set. it is fully powered and functional. 19.10.2 ADC OPERATION DURING CPU When ADON is ‘0’, the module is in Off mode. The dig- IDLE MODE ital and analog portions of the circuit are disabled for maximum current savings. The ADSIDL bit selects if the module will stop on Idle or continue on Idle. If ADSIDL = 0, the module will con- In order to return to the Active mode from Off mode, the tinue operation on assertion of Idle mode. If ADSIDL = user must wait for the ADC circuitry to stabilize. 1, the module will stop on Idle. 19.10 ADC Operation During CPU Sleep 19.11 Effects of a Reset and Idle Modes A device Reset forces all registers to their Reset state. 19.10.1 ADC OPERATION DURING CPU This forces the ADC module to be turned off, and any SLEEP MODE conversion and sampling sequence is aborted. The val- ues that are in the ADCBUF registers are not modified. When the device enters Sleep mode, all clock sources The ADC Result register will contain unknown data to the module are shutdown and stay at logic ‘0’. after a Power-on Reset. If Sleep occurs in the middle of a conversion, the con- version is aborted. The converter will not continue with 19.12 Output Formats a partially completed conversion on exit from Sleep mode. The ADC result is 12 bits wide. The data buffer RAM is also 12 bits wide. The 12-bit data can be read in one of Register contents are not affected by the device four different formats. The FORM<1:0> bits select the entering or leaving Sleep mode. format. Each of the output formats translates to a 16-bit The ADC module can operate during Sleep mode if the result on the data bus. ADC clock source is set to RC (ADRC = 1). When the RC clock source is selected, the ADC module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed which elim- inates all digital switching noise from the conversion. When the conversion is complete, the CONV bit will be cleared and the result loaded into the ADCBUF register. FIGURE 19-5: ADC OUTPUT DATA FORMATS RAM Contents: d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Read to Bus: Signed Fractional d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 Fractional d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 Signed Integer d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Integer 0 0 0 0 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 © 2011 Microchip Technology Inc. DS70143E-page 139

dsPIC30F6011A/6012A/6013A/6014A 19.13 Configuring Analog Port Pins 19.14 Connection Considerations The use of the ADPCFG and TRIS registers control the The analog inputs have diodes to VDD and VSS as ESD operation of the ADC port pins. The port pins that are protection. This requires that the analog input be desired as analog inputs must have their correspond- between VDD and VSS. If the input voltage exceeds this ing TRIS bit set (input). If the TRIS bit is cleared (out- range by greater than 0.3V (either direction), one of the put), the digital output level (VOH or VOL) will be diodes becomes forward biased and it may damage the converted. device if the input current specification is exceeded. The ADC operation is independent of the state of the An external RC filter is sometimes added for anti- CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits. aliasing of the input signal. The R component should be selected to ensure that the sampling time requirements When reading the Port register, all pins configured as are satisfied. Any external components connected (via analog input channels will read as cleared. high-impedance) to an analog input pin (capacitor, Pins configured as digital inputs will not convert an ana- zener diode, etc.) should have very little leakage log input. Analog levels on any pin that is defined as a current at the pin. digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. DS70143E-page 140 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A u u u u u u u u u u u u u u u u 0 0 0 0 0 0 u u u u u u u u u u u u u u u u 0 0 0 0 0 0 u u u u u u u u u u u u u u u u 0 0 0 0 0 0 u u u u u u u u u u u u u u u u 0 0 0 0 0 0 e u u u u u u u u u u u u u u u u 0 0 0 0 0 0 Stat uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu uuu 000 000 000 000 000 000 et u u u u u u u u u u u u u u u u 0 0 0 0 0 0 s u u u u u u u u u u u u u u u u 0 0 0 0 0 0 e u u u u u u u u u u u u u u u u 0 0 0 0 0 0 R u u u u u u u u u u u u u u u u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 0 DONE ALTS PCFG0 CSSL0 Bit 1 SAMP BUFM A<3:0> PCFG1 CSSL1 S Bit 2 ASAM <5:0> CH0 PCFG2 CSSL2 S C 3 3 3 D G L Bit — 3:0> A PCF CSS < 4 MPI NA G4 L4 Bit — S H0 CF SS C P C Bit 6Bit 5 ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 SRC<2:0> — — —— PCFG6PCFG5 CSSL6CSSL5 S Bit 7 BUFS ADRC — PCFG7 CSSL7 bit fields. 8 8 er Bit 8 M<1:0> — PCFG CSSL of regist Bit 10Bit 9 —FOR CSCNA— MC<4:0> CH0SB<3:0> PCFG10PCFG9 CSSL10CSSL9 6) for descriptions A 4 1 S 11 11 00 (1)AP Bit 12Bit 1 — — — — — — — — — — — — — — — — —— —— CH0NB PCFG12PCFG CSSL12CSSL nted bit, read as ‘’0ence Manual” (DS7 19-2:ADC REGISTER M Addr.Bit 15Bit 14Bit 13 0280——— 0282——— 0284——— 0286——— 0288——— 028A——— 028C——— 028E——— 0290——— 0292——— 0294——— 0296——— 0298——— 029A——— 029C——— 029E——— 02A0ADON—ADSIDL 02A2VCFG<2:0> 02A4——— 02A6——— 02A8PCFG15PCFG14PCFG13 02AACSSL15CSSL14CSSL13 u = uninitialized bit; — = unimplemeRefer to the “dsPIC30F Family Refer ABLE SFR Name DCBUF0 DCBUF1 DCBUF2 DCBUF3 DCBUF4 DCBUF5 DCBUF6 DCBUF7 DCBUF8 DCBUF9 DCBUFA DCBUFB DCBUFC DCBUFD DCBUFE DCBUFF DCON1 DCON2 DCON3 DCHS DPCFG DCSSL egend:ote1: T A A A A A A A A A A A A A A A A A A A A A A LN © 2011 Microchip Technology Inc. DS70143E-page 141

dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 142 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 20.0 SYSTEM INTEGRATION 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following Note: This data sheet summarizes features of modules and features: this group ofdsPIC30F devices and is not intended to be a complete reference • Various external and internal oscillator options as source. For more information on the CPU, clock sources peripherals, register descriptions and • An on-chip PLL to boost internal operating general device functionality, refer to the frequency “dsPIC30F Family Reference Manual” • A clock switching mechanism between various (DS70046). For more information on the clock sources device instruction set and programming, • Programmable clock postscaler for system power refer to the “16-bit MCU and DSC savings Programmer’s Reference Manual” (DS70157). • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and takes fail-safe measures There are several features intended to maximize • Oscillator Control register (OSCCON) system reliability, minimize cost through elimination of • Configuration bits for main oscillator selection external components, provide power-saving operating modes and offer code protection: Configuration bits determine the clock source upon Power-on Reset (POR) and Brown-out Reset (BOR). • Oscillator Selection Thereafter, the clock source can be changed between • Reset permissible clock sources. The OSCCON register con- - Power-on Reset (POR) trols the clock switching and reflects system clock - Power-up Timer (PWRT) related status bits. - Oscillator Start-up Timer (OST) Table20-1 provides a summary of the dsPIC30F - Programmable Brown-out Reset (BOR) oscillator operating modes. A simplified diagram of the • Watchdog Timer (WDT) oscillator system is shown in Figure20-1. • Low Voltage Detect • Power-Saving modes (Sleep and Idle) • Code Protection • Unit ID Locations • In-Circuit Serial Programming (ICSP) dsPIC30F devices have a Watchdog Timer, which is permanently enabled via the Configuration bits or can be software controlled. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a delay on power-up only, designed to keep the part in Reset while the power supply stabilizes. With these two tim- ers on-chip, most applications need no external Reset circuitry. Sleep mode is designed to offer a very low-current Power-Down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer Wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit a wide variety of applications. In the Idle mode, the clock sources are still active, but the CPU is shut-off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2011 Microchip Technology Inc. DS70143E-page 143

dsPIC30F6011A/6012A/6013A/6014A TABLE 20-1: OSCILLATOR OPERATING MODES Oscillator Mode Description XTL 200 kHz-4 MHz crystal on OSC1:OSC2 XT 4 MHz-10 MHz crystal on OSC1:OSC2 XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled XT w/PLL 16x 4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled(1) LP 32 kHz crystal on SOSCO:SOSCI(2) HS 10 MHz-25 MHz crystal. HS/2 w/PLL 4x 10 MHz-20 MHz crystal, divide by 2, 4x PLL enabled(3) HS/2 w/PLL 8x 10 MHz-20 MHz crystal, divide by 2, 8x PLL enabled(3) HS/2 w/PLL 16x 10 MHz-15 MHz crystal, divide by 2, 16x PLL enabled(1) HS/3 w/PLL 4x 12 MHz-25 MHz crystal, divide by 3, 4x PLL enabled(4) HS/3 w/PLL 8x 12 MHz-25 MHz crystal, divide by 3, 8x PLL enabled(4) HS/3 w/PLL 16x 12 MHz-22.5 MHz crystal, divide by 3, 16x PLL enabled(1)(4) EC External clock input (0-40 MHz) ECIO External clock input (0-40 MHz), OSC2 pin is I/O EC w/PLL 4x External clock input (4-10 MHz), OSC2 pin is I/O, 4x PLL enabled EC w/PLL 8x External clock input (4-10 MHz), OSC2 pin is I/O, 8x PLL enabled EC w/PLL 16x External clock input (4-7.5 MHz), OSC2 pin is I/O, 16x PLL enabled(1) ERC External RC oscillator, OSC2 pin is FOSC/4 output(5) ERCIO External RC oscillator, OSC2 pin is I/O(5) FRC 7.37 MHz internal RC oscillator FRC w/PLL 4x 7.37 MHz internal RC oscillator, 4x PLL enabled FRC w/PLL 8x 7.37 MHz internal RC oscillator, 8x PLL enabled FRC w/PLL 16x 7.37 MHz internal RC oscillator, 16x PLL enabled LPRC 512 kHz internal RC oscillator Note 1: Any higher will violate device operating frequency range. 2: LP oscillator can be conveniently shared as system clock, as well as Real-Time Clock for Timer1. 3: Any higher will violate PLL input range. 4: Any lower will violate PLL input range. 5: Requires external R and C. Frequency operation up to 4 MHz. DS70143E-page 144 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM Oscillator Configuration bits PWRSAV Instruction Wake-up Request FPLL OSC1 Primary PLL Oscillator x4, x8, x16 PLL OSC2 Lock COSC<2:0> Primary Osc TUN<3:0> NOSC<2:0> 4 Primary OSWEN Oscillator Stability Detector Internal Fast RC Oscillator (FRC) Oscillator POR Done Start-up Clock Timer Switching Programmable and Control Secondary Osc Clock Divider System Block Clock SOSCO Secondary 32 kHz LP 2 Oscillator Oscillator SOSCI Stability Detector POST<1:0> Internal Low- LPRC Power RC Oscillator (LPRC) CF Fail-Safe Clock FCKSM<1:0> Monitor (FSCM) 2 Oscillator Trap to Timer1 © 2011 Microchip Technology Inc. DS70143E-page 145

dsPIC30F6011A/6012A/6013A/6014A 20.2 Oscillator Configurations 20.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<2:0> Configuration bits that select one of four oscillator groups, and b) FPR<4:0> Configuration bits that select the oscillator choices within the primary group. The selection is as shown in Table20-2. TABLE 20-2: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Oscillator Mode FOS<2:0> FPR<4:0> OSC2 Function Source ECIO w/PLL 4x PLL 1 1 1 0 1 1 0 1 I/O ECIO w/PLL 8x PLL 1 1 1 0 1 1 1 0 I/O ECIO w/PLL 16x PLL 1 1 1 0 1 1 1 1 I/O FRC w/PLL 4x PLL 1 1 1 0 0 0 0 1 I/O FRC w/PLL 8x PLL 1 1 1 0 1 0 1 0 I/O FRC w/PLL 16x PLL 1 1 1 0 0 0 1 1 I/O XT w/PLL 4x PLL 1 1 1 0 0 1 0 1 OSC2 XT w/PLL 8x PLL 1 1 1 0 0 1 1 0 OSC2 XT w/PLL 16x PLL 1 1 1 0 0 1 1 1 OSC2 HS/2 w/PLL 4x PLL 1 1 1 1 0 0 0 1 OSC2 HS/2 w/PLL 8x PLL 1 1 1 1 0 0 1 0 OSC2 HS/2 w/PLL 16x PLL 1 1 1 1 0 0 1 1 OSC2 HS/3 w/PLL 4x PLL 1 1 1 1 0 1 0 1 OSC2 HS/3 w/PLL 8x PLL 1 1 1 1 0 1 1 0 OSC2 HS/3 w/PLL 16x PLL 1 1 1 1 0 1 1 1 OSC2 ECIO External 0 1 1 0 1 1 0 0 I/O XT External 0 1 1 0 0 1 0 0 OSC2 HS External 0 1 1 0 0 0 1 0 OSC2 EC External 0 1 1 0 1 0 1 1 CLKOUT ERC External 0 1 1 0 1 0 0 1 CLKOUT ERCIO External 0 1 1 0 1 0 0 0 I/O XTL External 0 1 1 0 0 0 0 0 OSC2 LP Secondary 0 0 0 x x x x x (Note 1, 2) FRC Internal FRC 0 0 1 x x x x x (Note 1, 2) LPRC Internal LPRC 0 1 0 x x x x x (Note 1, 2) Note 1: OSC2 pin function is determined by FPR<4:0>. 2: OSC1 pin cannot be used as an I/O pin even if the secondary oscillator or an internal clock source is selected at all times. DS70143E-page 146 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 20.2.2 OSCILLATOR START-UP TIMER 20.2.5 FAST RC OSCILLATOR (FRC) (OST) The FRC oscillator is a fast (7.37 MHz ±2% nominal) In order to ensure that a crystal oscillator (or ceramic internal RC oscillator. This oscillator is intended to pro- resonator) has started and stabilized, an Oscillator vide reasonable device operating speeds without the Start-up Timer is included. It is a simple 10-bit counter use of an external crystal, ceramic resonator or RC net- that counts 1024 TOSC cycles before releasing the work. The FRC oscillator can be used with the PLL to oscillator clock to the rest of the system. The time-out obtain higher clock frequencies. period is designated as TOST. The TOST time is involved The dsPIC30F operates from the FRC oscillator when- every time the oscillator has to restart (i.e., on POR, ever the current oscillator selection control bits in the BOR and wake-up from Sleep). The Oscillator Start-up OSCCON register (OSCCON<14:12>) are set to ‘001’. Timer is applied to the LP, XT, XTL and HS Oscillator The 6-bit field specified by TUN<3:0> (OSCTUN<3:0>) modes (upon wake-up from Sleep, POR and BOR) for allows the user to tune the internal fast RC oscillator the primary oscillator. (nominal 7.37 MHz). The user can tune the FRC oscil- 20.2.3 LP OSCILLATOR CONTROL lator within a range of ±6% in steps of 0.75% around the factory-calibrated setting (see Table20-4). Enabling the LP oscillator is controlled with two elements: Note: OSCTUN functionality has been provided to help customers compensate for • The current oscillator group bits COSC<2:0> temperature effects on the FRC frequency • The LPOSCEN bit (OSCCON register) over a wide range of temperatures. The The LP oscillator is ON (even during Sleep mode) if tuning step size is an approximation and is LPOSCEN = 1. The LP oscillator is the device clock if: neither characterized nor tested. • COSC<2:0> = 000 (LP selected as main oscillator) If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are and set to ‘00101’, ‘00110’ or ‘00111’, then a PLL • LPOSCEN = 1 multiplier of 4, 8 or 16 (respectively) is applied. Keeping the LP oscillator ON at all times allows for a Note: When a 16x PLL is used, the FRC oscilla- fast switch to the 32 kHz system clock for lower power tor must not be tuned to a frequency operation. Returning to the faster main oscillator will greater than 7.5 MHz. still require a start-up time. TABLE 20-4: FRC TUNING 20.2.4 PHASE LOCKED LOOP (PLL) TUN<3:0> The PLL multiplies the clock which is generated by the FRC Frequency Bits primary oscillator. The PLL is selectable to have either gains of x4, x8 and x16. Input and output frequency 0111 +5.25% ranges are summarized in Table20-3. 0110 +4.50% 0101 +3.75% TABLE 20-3: PLL FREQUENCY RANGE 0100 +3.00% PLL 0011 +2.25% Fin Fout Multiplier 0010 +1.50% 4 MHz-10 MHz x4 16 MHz-40 MHz 0001 +0.75% 4 MHz-10 MHz x8 32 MHz-80 MHz 0000 Center Frequency (oscillator is running at calibrated frequency) 4 MHz-7.5 MHz x16 64 MHz-120 MHz 1111 -0.75% The PLL features a lock output, which is asserted when 1110 -1.50% the PLL enters a phase locked state. Should the loop 1101 -2.25% fall out of lock (e.g., due to noise), the lock signal will be rescinded. The state of this signal is reflected in the 1100 -3.00% read-only LOCK bit in the OSCCON register. 1011 -3.75% 1010 -4.50% 1001 -5.25% 1000 -6.00% © 2011 Microchip Technology Inc. DS70143E-page 147

dsPIC30F6011A/6012A/6013A/6014A 20.2.6 LOW-POWER RC OSCILLATOR COSC<2:0> bits are loaded with FRC oscillator selec- (LPRC) tion. This will effectively shut-off the original oscillator that was trying to start. The LPRC oscillator is a component of the Watchdog Timer (WDT) and oscillates at a nominal frequency of The user may detect this situation and restart the 512 kHz. The LPRC oscillator is the clock source for oscillator in the clock fail trap ISR. the Power-up Timer (PWRT) circuit, WDT and clock Upon a clock failure detection, the FSCM module will monitor circuits. It may also be used to provide a low initiate a clock switch to the FRC oscillator as follows: frequency clock source option for applications where 1. The COSC bits (OSCCON<14:12>) are loaded power consumption is critical, and timing accuracy is with the FRC oscillator selection value. not required. 2. CF bit is set (OSCCON<3>). The LPRC oscillator is always enabled at a Power-on 3. OSWEN control bit (OSCCON<0>) is cleared. Reset, because it is the clock source for the PWRT. After the PWRT expires, the LPRC oscillator will remain For the purpose of clock switching, the clock sources ON if one of the following is TRUE: are sectioned into four groups: • The Fail-Safe Clock Monitor is enabled • Primary • The WDT is enabled • Secondary • The LPRC oscillator is selected as the system • Internal FRC clock via the COSC<2:0> control bits in the • Internal LPRC OSCCON register The user can switch between these functional groups, If one of the above conditions is not true, the LPRC will but cannot switch between options within a group. If the shut-off after the PWRT expires. primary group is selected, then the choice within the group is always determined by the FPR<4:0> Note1: OSC2 pin function is determined by the Configuration bits. Primary Oscillator mode selection (FPR<4:0>). The OSCCON register holds the control and status bits related to clock switching. 2: Note that OSC1 pin cannot be used as an I/O pin, even if the secondary oscillator or • COSC<2:0>: Read-only status bits always reflect an internal clock source is selected at all the current oscillator group in effect times. • NOSC<2:0>: Control bits which are written to indicate the new oscillator group of choice 20.2.7 FAIL-SAFE CLOCK MONITOR - On POR and BOR, COSC<2:0> and The Fail-Safe Clock Monitor (FSCM) allows the device NOSC<2:0> are both loaded with the to continue to operate even in the event of an oscillator Configuration bit values FOS<2:0> failure. The FSCM function is enabled by appropriately • LOCK: The LOCK status bit indicates a PLL lock programming the FCKSM Configuration bits (Clock • CF: Read-only status bit indicating if a clock fail Switch and Monitor Selection bits) in the FOSC device detect has occurred Configuration register. If the FSCM function is • OSWEN: Control bit changes from a ‘0’ to a ‘1’ enabled, the LPRC internal oscillator will run at all when a clock transition sequence is initiated. times (except during Sleep mode) and will not be Clearing the OSWEN control bit will abort a clock subject to control by the SWDTEN bit. transition in progress (used for hang-up situations). In the event of an oscillator failure, the FSCM will If Configuration bits FCKSM<1:0> = 1x, then the clock generate a clock failure trap event and will switch the sys- switching and Fail-Safe Clock Monitor functions are tem clock over to the FRC oscillator. The user will then disabled. This is the default Configuration bit setting. have the option to either attempt to restart the oscillator or execute a controlled shutdown. The user may decide If clock switching is disabled, then the FOS<2:0> and to treat the trap as a warm Reset by simply loading the FPR<4:0> bits directly control the oscillator selection Reset address into the oscillator fail trap vector. In this and the COSC<2:0> bits do not control the clock event, the CF (Clock Fail) status bit (OSCCON<3>) is selection. However, these bits will reflect the clock also set whenever a clock failure is recognized. source selection. In the event of a clock failure, the WDT is unaffected Note: The application should not attempt to and continues to run on the LPRC clock. switch to a clock of frequency lower than 100 kHz when the Fail-Safe Clock Monitor If the oscillator has a very slow start-up time coming is enabled. If clock switching is performed, out of POR, BOR or Sleep, it is possible that the the device may generate an oscillator fail PWRT timer will expire before the oscillator has trap and switch to the fast RC oscillator. started. In such cases, the FSCM will be activated and the FSCM will initiate a clock failure trap, and the DS70143E-page 148 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 20.2.8 PROTECTION AGAINST ACCIDENTAL WRITES TO OSCCON A write to the OSCCON register is intentionally made difficult because it controls clock switching and clock scaling. To write to the OSCCON low byte, the following code sequence must be executed without any other instructions in between: Byte Write 0x46 to OSCCON low Byte Write 0x57 to OSCCON low Byte write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. To write to the OSCCON high byte, the following instructions must be executed without any other instructions in between: Byte Write 0x78 to OSCCON high Byte Write 0x9A to OSCCON high Byte write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. 20.3 Oscillator Control Registers The oscillators are controlled with two SFRs, OSCCON and OSCTUN and one Configuration register, FOSC. Note: The description of the OSCCON and OSCTUN SFRs, as well as the FOSC Configuration register provided in this section are applicable only to the dsPIC30F6011A/6012A/6013A/6014A devices in the dsPIC30F product family. © 2011 Microchip Technology Inc. DS70143E-page 149

dsPIC30F6011A/6012A/6013A/6014A R EGISTER 20-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-y R-y R-y U-0 R/W-y R/W-y R/W-y — COSC<2:0> — NOSC<2:0> bit 15 bit 8 R/W-0 R/W-0 R-0 U-0 R/W-0 U-0 R/W-0 R/W-0 POST<1:0> LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 Legend: y = Values dependent on FOSC R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Group Selection bits (read-only) 111 = PLL Oscillator; PLL source selected by FPR<4:0> bits 011 = External Oscillator; OSC1/OSC2 pins; External Oscillator configuration selected by FPR<4:0> bits 010 = LPRC internal low-power RC 001 = FRC internal fast RC 000 = LP crystal oscillator; SOSCI/SOSCO pins Set to FOS<2:0> values on POR or BOR. Loaded with NOSC<2:0> at the completion of a successful clock switch. Set to FRC value when FSCM detects a failure and switches clock to FRC. bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Group Selection bits 111 = PLL Oscillator; PLL source selected by FPR<4:0> bits 011 = External Oscillator; OSC1/OSC2 pins; External Oscillator configuration selected by FPR<4:0> bits 010 = LPRC internal low-power RC 001 = FRC internal fast RC 000 = LP crystal oscillator; SOSCI/SOSCO pins Set to FOS<2:0> values on POR or BOR. bit 7-6 POST<1:0>: Oscillator Postscaler Selection bits 11 = Oscillator postscaler divides clock by 64 10 = Oscillator postscaler divides clock by 16 01 = Oscillator postscaler divides clock by 4 00 = Oscillator postscaler does not alter clock bit 5 LOCK: PLL Lock status bit (Read Only) 1 = Indicates that PLL is in lock 0 = Indicates that PLL is out of lock (or disabled) bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit (read/clearable by application) 1 = FSCM has detected clock failure 0 = FSCM has NOT detected clock failure bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: 32 kHz Secondary (LP) Oscillator Enable 1 = Secondary Oscillator is enabled 0 = Secondary Oscillator is disabled bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request Oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete DS70143E-page 150 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A R EGISTER 20-2: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — TUN<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 -4 Unimplemented: Read as ‘0’ bit 3-0 TUN<3:0>: Lower two bits of TUN field. The four bit field specified by TUN<3:0> specifies the user tuning capability for the internal fast RC oscillator (nominal 7.37 MHz). 0111 = Maximum Frequency 0110 = 0101 = 0100 = 0011 = 0010 = 0001 = 0000 = Center Frequency, Oscillator is running at calibrated frequency 1111 = 1110 = 1101 = 1100 = 1011 = 1010 = 1001 = 1000 = Minimum Frequency © 2011 Microchip Technology Inc. DS70143E-page 151

dsPIC30F6011A/6012A/6013A/6014A R EGISTER 20-3: FOSC: OSCILLATOR CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R/P R/P U-0 U-0 U-0 R/P R/P R/P FCKSM<1:0> — — — FOS<2:0> bit 15 bit 8 U-0 U-0 U-0 R/P R/P R/P R/P R/P — — — FPR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘0’ bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, fail safe clock monitor is disabled 01 = Clock switching is enabled, fail safe clock monitor is disabled 00 = Clock switching is enabled, fail safe clock monitor is enabled bit 13-11 Unimplemented: Read as ‘0’ bit 10-8 FOS<2:0>: Oscillator Group Selection on POR bits 111 = PLL Oscillator; PLL source selected by FPR<4:0> bits, see Table20-2. 011 = EXT: External Oscillator; OSC1/OSC2 pins; External Oscillator configuration selected by FPR<4:0> bits 010 = LPRC: Internal Low Power RC 001 = FRC: Internal Fast RC 000 = LPOSC: Low Power Crystal Oscillator; SOSCI/SOSCO pins bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 FPR<4:0>: Oscillator Selection within Primary Group bits, see Table20-2. DS70143E-page 152 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 20.4 Reset 20.4.1 POR: POWER-ON RESET The dsPIC30F differentiates between various kinds of A power-on event will generate an internal POR pulse Reset: when a VDD rise is detected. The Reset pulse will occur at the POR circuit threshold voltage (VPOR), which is • Power-on Reset (POR) nominally 1.85V. The device supply voltage character- • MCLR Reset during normal operation istics must meet specified starting voltage and rise rate • MCLR Reset during Sleep requirements. The POR pulse will reset a POR timer • Watchdog Timer (WDT) Reset (during normal and place the device in the Reset state. The POR also operation) selects the device clock source identified by the oscillator configuration fuses. • Programmable Brown-out Reset (BOR) • RESET Instruction The POR circuit inserts a small delay, TPOR, which is nominally 10 μs and ensures that the device bias • Reset caused by trap lockup (TRAPR) circuits are stable. Furthermore, a user selected power- • Reset caused by illegal opcode, or by using an up time-out (TPWRT) is applied. The TPWRT parameter uninitialized W register as an Address Pointer is based on device Configuration bits and can be 0 ms (IOPUWR) (no delay), 4 ms, 16 ms or 64 ms. The total delay is at Different registers are affected in different ways by device power-up TPOR + TPWRT. When these delays various Reset conditions. Most registers are not have expired, SYSRST will be negated on the next affected by a WDT wake-up, since this is viewed as the leading edge of the Q1 clock, and the PC will jump to resumption of normal operation. Status bits from the the Reset vector. RCON register are set or cleared differently in different The timing for the SYSRST signal is shown in Reset situations, as indicated in Table20-5. These bits Figure20-3 through Figure20-5. are used in software to determine the nature of the Reset. A block diagram of the on-chip Reset circuit is shown in Figure20-2. A MCLR noise filter is provided in the MCLR Reset path. The filter detects and ignores small pulses. Internally generated Resets do not drive MCLR pin low. FIGURE 20-2: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Digital Glitch Filter MCLR Sleep or Idle WDT Module VDD Rise POR S Detect VDD Brown-out BOR Reset BOREN Trap Conflict R Q SYSRST Illegal Opcode/ Uninitialized W Register © 2011 Microchip Technology Inc. DS70143E-page 153

dsPIC30F6011A/6012A/6013A/6014A FIGURE 20-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR Internal POR TOST OST Time-out TPWRT PWRT Time-out Internal Reset FIGURE 20-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR Internal POR TOST OST Time-out TPWRT PWRT Time-out Internal Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR Internal POR TOST OST Time-out TPWRT PWRT Time-out Internal Reset DS70143E-page 154 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 20.4.1.1 POR with Long Crystal Start-up Time A BOR will generate a Reset pulse which will reset the (with FSCM Enabled) device. The BOR will select the clock source, based on the device Configuration bit values (FOS<2:0> and The oscillator start-up circuitry is not linked to the POR FPR<4:0>). Furthermore, if an oscillator mode is circuitry. Some crystal circuits (especially low frequency selected, the BOR will activate the Oscillator Start-up crystals) will have a relatively long start-up time. There- Timer (OST). The system clock is held until OST fore, one or more of the following conditions is possible expires. If the PLL is used, then the clock will be held after the POR timer and the PWRT have expired: until the LOCK bit (OSCCON<5>) is ‘1’. • The oscillator circuit has not begun to oscillate. Concurrently, the POR time-out (TPOR) and the PWRT • The Oscillator Start-up Timer has NOT expired (if time-out (TPWRT) will be applied before the internal a crystal oscillator is used). Reset is released. If TPWRT = 0 and a crystal oscillator • The PLL has not achieved a LOCK (if PLL is is being used, then a nominal delay of TFSCM = 100 μs used). is applied. The total delay in this case is If the FSCM is enabled and one of the above conditions (TPOR+TFSCM). is true, then a clock failure trap will occur. The device The BOR status bit (RCON<1>) will be set to indicate will automatically switch to the FRC oscillator and the that a BOR has occurred. The BOR circuit, if enabled, user can switch to the desired crystal oscillator in the will continue to operate while in Sleep or Idle modes trap ISR. and will reset the device should VDD fall below the BOR threshold voltage. 20.4.1.2 Operating without FSCM and PWRT If the FSCM is disabled and the Power-up Timer FIGURE 20-6: EXTERNAL POWER-ON (PWRT) is also disabled, then the device will exit rapidly RESET CIRCUIT (FOR from Reset on power-up. If the clock source is FRC, SLOW VDD POWER-UP) LPRC, EXTRC or EC, it will be active immediately. VDD If the FSCM is disabled and the system clock has not started, the device will be in a frozen state at the Reset D R vector until the system clock starts. From the user’s R1 MCLR perspective, the device will appear to be in Reset until a system clock is available. C dsPIC30F 20.4.2 BOR: PROGRAMMABLE BROWN-OUT RESET Note1: External Power-on Reset circuit is required only if the VDD power-up slope The BOR (Brown-out Reset) module is based on an is too slow. The diode D helps discharge internal voltage reference circuit. The main purpose of the capacitor quickly when VDD powers the BOR module is to generate a device Reset when a down. brown-out condition occurs. Brown-out conditions are generally caused by glitches on the AC mains (i.e., 2: R should be suitably chosen so as to missing portions of the AC cycle waveform due to bad make sure that the voltage drop across power transmission lines or voltage sags due to exces- R does not violate the device’s electrical sive current draw when a large inductive load is turned specification. on). 3: R1 should be suitably chosen so as to The BOR module allows selection of one of the limit any current flowing into MCLR from external capacitor C, in the event of following voltage trip points: MCLR/VPP pin breakdown due to Elec- • 2.6V-2.71V trostatic Discharge (ESD) or Electrical • 4.1V-4.4V Overstress (EOS). • 4.58V-4.73V Note: The BOR voltage trip points indicated here Note: Dedicated supervisory devices, such as are nominal values provided for design the MCP1XX and MCP8XX, may also be guidance only. used as an external Power-on Reset circuit. © 2011 Microchip Technology Inc. DS70143E-page 155

dsPIC30F6011A/6012A/6013A/6014A Table20-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. TABLE 20-5: INITIALIZATION CONDITION FOR RCON REGISTER CASE 1 Program Condition TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR Counter Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1 Brown-out Reset 0x000000 0 0 0 0 0 0 0 0 1 MCLR Reset during normal 0x000000 0 0 1 0 0 0 0 0 0 operation Software Reset during 0x000000 0 0 0 1 0 0 0 0 0 normal operation MCLR Reset during Sleep 0x000000 0 0 1 0 0 0 1 0 0 MCLR Reset during Idle 0x000000 0 0 1 0 0 1 0 0 0 WDT Time-out Reset 0x000000 0 0 0 0 1 0 0 0 0 WDT Wake-up PC + 2 0 0 0 0 1 0 1 0 0 Interrupt Wake-up from PC + 2(1) 0 0 0 0 0 0 1 0 0 Sleep Clock Failure Trap 0x000004 0 0 0 0 0 0 0 0 0 Trap Reset 0x000000 1 0 0 0 0 0 0 0 0 Illegal Operation Trap 0x000000 0 1 0 0 0 0 0 0 0 Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. Table20-6 shows a second example of the bit conditions for the RCON register. In this case, it is not assumed the user has set/cleared specific bits prior to action specified in the condition column. TABLE 20-6: INITIALIZATION CONDITION FOR RCON REGISTER CASE 2 Program Condition TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR Counter Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1 Brown-out Reset 0x000000 u u u u u u u 0 1 MCLR Reset during normal 0x000000 u u 1 0 0 0 0 u u operation Software Reset during 0x000000 u u 0 1 0 0 0 u u normal operation MCLR Reset during Sleep 0x000000 u u 1 u 0 0 1 u u MCLR Reset during Idle 0x000000 u u 1 u 0 1 0 u u WDT Time-out Reset 0x000000 u u 0 0 1 0 0 u u WDT Wake-up PC + 2 u u u u 1 u 1 u u Interrupt Wake-up from PC + 2(1) u u u u u u 1 u u Sleep Clock Failure Trap 0x000004 u u u u u u u u u Trap Reset 0x000000 1 u u u u u u u u Illegal Operation Reset 0x000000 u 1 u u u u u u u Legend: u = unchanged Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70143E-page 156 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 20.5 Watchdog Timer (WDT) 20.7 Power-Saving Modes 20.5.1 WATCHDOG TIMER OPERATION There are two power-saving states that can be entered through the execution of a special instruction, PWRSAV. The primary function of the Watchdog Timer (WDT) is These are: Sleep and Idle. to reset the processor in the event of a software malfunction. The WDT is a free running timer, which The format of the PWRSAV instruction is as follows: runs off an on-chip RC oscillator, requiring no external PWRSAV <parameter>, component. Therefore, the WDT timer will continue to operate even if the main processor clock (e.g., the where: crystal oscillator) fails. ‘parameter’ defines Idle or Sleep mode. 20.5.2 ENABLING AND DISABLING THE 20.7.1 SLEEP MODE WDT In Sleep mode, the clock to the CPU and peripherals is The Watchdog Timer can be “Enabled” or “Disabled” shutdown. If an on-chip oscillator is being used, it is only through a Configuration bit (FWDTEN) in the shutdown. Configuration register FWDT. The Fail-Safe Clock Monitor is not functional during Setting FWDTEN = 1 enables the Watchdog Timer. Sleep, since there is no clock to monitor. However, The enabling is done when programming the device. LPRC clock remains active if WDT is operational during By default, after chip-erase, FWDTEN bit = 1. Any Sleep. device programmer capable of programming The Brown-out protection circuit, if enabled, will remain dsPIC30F devices allows programming of this and functional during Sleep. other Configuration bits. The processor wakes up from Sleep if at least one of If enabled, the WDT will increment until it overflows or the following conditions has occurred: “times out”. A WDT time-out will force a device Reset (except during Sleep). To prevent a WDT time-out, the • On any interrupt that is individually enabled and user must clear the Watchdog Timer using a CLRWDT meets the required priority level instruction. • On any Reset (POR, BOR and MCLR) • On WDT time-out If a WDT times out during Sleep, the device will wake- up. The WDTO bit in the RCON register will be cleared On waking up from Sleep mode, the processor will to indicate a wake-up resulting from a WDT time-out. restart the same clock that was active prior to entry into Sleep mode. When clock switching is enabled, Setting FWDTEN = 0 allows user software to enable/ bits COSC<2:0> will determine the oscillator source disable the Watchdog Timer via the SWDTEN control that will be used on wake-up. If clock switch is bit (RCON<5>). disabled, then there is only one system clock. 20.6 Low-Voltage Detect Note: If a POR or BOR occurred, the selection of the oscillator is based on the FOS<2:0> The Low-Voltage Detect (LVD) module is used to and FPR<4:0> Configuration bits. detect when the VDD of the device drops below a threshold value, VLVD, which is determined by the If the clock source is an oscillator, the clock to the LVDL<3:0> bits (RCON<11:8>) and is thus user pro- device is held off until OST times out (indicating a grammable. The internal voltage reference circuitry stable oscillator). If PLL is used, the system clock is requires a nominal amount of time to stabilize, and the held off until LOCK = 1 (indicating that the PLL is BGST bit (RCON<13>) indicates when the voltage stable). Either way, TPOR, TLOCK and TPWRT delays are reference has stabilized. applied. In some devices, the LVD threshold voltage may be If EC, FRC, LPRC or EXTRC oscillators are used, then applied externally on the LVDIN pin. a delay of TPOR (~ 10 μs) is applied. This is the smallest delay possible on wake-up from Sleep. The LVD module is enabled by setting the LVDEN bit (RCON<12>). Moreover, if LP oscillator was active during Sleep, and LP is the oscillator used on wake-up, then the start-up delay will be equal to TPOR. PWRT delay and OST timer delay are not applied. In order to have the small- est possible start-up delay when waking up from Sleep, one of these faster wake-up options should be selected before entering Sleep. © 2011 Microchip Technology Inc. DS70143E-page 157

dsPIC30F6011A/6012A/6013A/6014A Any interrupt that is individually enabled (using the Unlike wake-up from Sleep, there are no time delays corresponding IE bit) and meets the prevailing priority involved in wake-up from Idle. level will be able to wake-up the processor. The proces- sor will process the interrupt and branch to the ISR. The 20.8 Device Configuration Registers Sleep status bit in RCON register is set upon wake-up. The Configuration bits in each device Configuration Note: In spite of various delays applied (TPOR, register specify some of the device modes and are TLOCK and TPWRT), the crystal oscillator programmed by a device programmer, or by using the (and PLL) may not be active at the end of In-Circuit Serial Programming (ICSP) feature of the the time-out (e.g., for low-frequency crys- device. Each device Configuration register is a 24-bit tals). In such cases, if FSCM is enabled, register, but only the lower 16 bits of each register are then the device will detect this as a clock used to hold configuration data. There are seven device failure and process the clock failure trap, Configuration registers available to the user: the FRC oscillator will be enabled, and the 1. FOSC (0xF80000): Oscillator Configuration user will have to re-enable the crystal oscil- register lator. If FSCM is not enabled, then the device will simply suspend execution of 2. FWDT (0xF80002): Watchdog Timer code until the clock is stable, and will Configuration register remain in Sleep until the oscillator clock has 3. FBORPOR (0xF80004): BOR and POR started. Configuration register 4. FBS (0xF80006): Boot Code Segment All Resets will wake-up the processor from Sleep Configuration register mode. Any Reset, other than POR, will set the Sleep status bit. In a POR, the Sleep bit is cleared. 5. FSS (0xF80008): Secure Code Segment Configuration register If Watchdog Timer is enabled, then the processor will 6. FGS (0xF8000A): General Code Segment wake-up from Sleep mode upon WDT time-out. The Configuration register Sleep and WDTO status bits are both set. 7. FICD (0xF8000C): Debug Configuration 20.7.2 IDLE MODE Register In Idle mode, the clock to the CPU is shutdown while The placement of the Configuration bits is automatically peripherals keep running. Unlike Sleep mode, the clock handled when you select the device in your device pro- source remains active. grammer. The desired state of the Configuration bits may be specified in the source code (dependent on the lan- Several peripherals have a control bit in each module guage tool used), or through the programming interface. that allows them to operate during Idle. After the device has been programmed, the application LPRC fail-safe clock remains active if clock failure software may read the Configuration bit values through detect is enabled. the table read instructions. For additional information, The processor wakes up from Idle if at least one of the please refer to the “dsPIC30F Flash Programming following conditions is true: Specification” (DS70102) and the “dsPIC30F Family Reference Manual” (DS70046). • On any interrupt that is individually enabled (IE bit is ‘1’) and meets the required priority level Note: If the code protection Configuration Fuse • On any Reset (POR, BOR, MCLR) bits (FBS(BSS<2:0>), FSS(SSS<2:0>), FGS<GSS>, FGS<GWRP>) have been • On WDT time-out programmed, an erase of the entire code- Upon wake-up from Idle mode, the clock is re-applied protected device is only possible at to the CPU and instruction execution begins immedi- voltages VDD ≥ 4.5V. ately, starting with the instruction following the PWRSAV instruction. Any interrupt that is individually enabled (using IE bit) and meets the prevailing priority level will be able to wake-up the processor. The processor will process the interrupt and branch to the ISR. The IDLE status bit in RCON register is set upon wake-up. Any Reset, other than POR, will set the Idle status bit. On a POR, the Idle bit is cleared. If Watchdog Timer is enabled, then the processor will wake-up from Idle mode upon WDT time-out. The Idle and WDTO status bits are both set. DS70143E-page 158 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 20.9 Peripheral Module Disable (PMD) 20.10 In-Circuit Debugger Registers When MPLAB® ICD 2 is selected as a debugger, the The Peripheral Module Disable (PMD) registers pro- in-circuit debugging functionality is enabled. This func- vide a method to disable a peripheral module by stop- tion allows simple debugging functions when used with ping all clock sources supplied to that module. When a MPLAB IDE. When the device has this feature enabled, peripheral is disabled via the appropriate PMD control some of the resources are not available for general bit, the peripheral is in a minimum power consumption use. These resources include the first 80 bytes of data state. The control and status registers associated with RAM and two I/O pins. the peripheral will also be disabled so writes to those One of four pairs of debug I/O pins may be selected by registers will have no effect and read values will be the user using configuration options in MPLAB IDE. invalid. These pin pairs are named EMUD/EMUC, A peripheral module will only be enabled if both the EMUD1/EMUC1, EMUD2/EMUC2 and associated bit in the PMD register is cleared and the EMUD3/EMUC3. peripheral is supported by the specific dsPIC DSC vari- In each case, the selected EMUD pin is the Emulation/ ant. If the peripheral is present in the device, it is Debug Data line, and the EMUC pin is the Emulation/ enabled in the PMD register by default. Debug Clock line. These pins will interface to the MPLAB ICD 2 module available from Microchip. The Note: If a PMD bit is set, the corresponding selected pair of debug I/O pins is used by MPLAB ICD2 module is disabled after a delay of 1 to send commands and receive responses, as well as instruction cycle. Similarly, if a PMD bit is to send and receive data. To use the in-circuit debugger cleared, the corresponding module is function of the device, the design must implement ICSP enabled after a delay of 1 instruction cycle (assuming the module control registers connections to MCLR, VDD, VSS, PGC, PGD and the selected EMUDx/EMUCx pin pair. are already configured to enable module operation). This gives rise to two possibilities: 1. If EMUD/EMUC is selected as the debug I/O pin pair, then only a 5-pin interface is required, as the EMUD and EMUC pin functions are multi- plexed with the PGD and PGC pin functions in all dsPIC30F devices. 2. If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/ EMUC3 is selected as the debug I/O pin pair, then a 7-pin interface is required, as the EMUDx/EMUCx pin functions (x = 1, 2 or 3) are not multiplexed with the PGD and PGC pin functions. © 2011 Microchip Technology Inc. DS70143E-page 159

dsPIC30F6011A/6012A/6013A/6014A Reset State Depends on type of Reset. Depends on Configuration bits. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Bit 2Bit 1Bit 0 FPR<4:0> FWPSB<3:0> —FPWRT<1:0> BSS<2:0>BWRP SSS<2:0>SWRP GSS<1:0>GWRP —ICS<1:0> N D D 0 R E M M Bit PO OSW ADC OC1 Bit 3 — — — N Bit 2Bit 1 IDLEBOR —LPOSCE TUN<3:0> C2MDC1MD OC3MDOC2MD Bit 5Bit 4 — FWPSA<1:0> BORV<1:0> —— —— —— —— P D D Bit 3 SLEE CF SPI1M OC4M Bit 6 — — — — — — — Bit 4 WDTO — — SPI2MD OC5MD Bit 7 — — OREN — — — — (1)20-7:SYSTEM INTEGRATION REGISTER MAP FOR dsPIC30F601XA AddrBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5. 0740TRAPRIOPUWRBGSTLVDENLVDL<3:0>EXTRSWRSWDTEN 0742—COSC<2:0>—NOSC<2:0>POST<1:0>LOCK 0744——————————— ——0770T5MDT4MDT3MDT2MDT1MDDCIMDI2CMDU2MDU1MD 0772IC8MDIC7MDIC6MDIC5MDIC4MDIC3MDIC2MDIC1MDOC8MDOC7MDOC6MD — = unimplemented bit, read as ‘’0Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. (1)20-8:DEVICE CONFIGURATION REGISTER MAP AddressBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8 F80000FCKSM<1:0>———FOS<2:0> F80002FWDTEN——————— (2)(2)(2)F80004MCLREN————PWMPINHPOLLPOLB F80006——RBS<1:0>———EBS F80008——RSS<1:0>——ESS<1:0> F8000A———————— F8000CBKBUGCOE—————— — = unimplemented bit, read as ‘’0Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.11These bits are reserved (read as ‘’ and must be programmed as ‘’). TABLE SFR Name RCON OSCCON OSCTUN PMD1 PMD2 Legend:Note1: TABLE Name FOSC FWDT FBORPOR FBS FSS FGS FICD Legend:Note1:2: DS70143E-page 160 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 21.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: Note: This data sheet summarizes features of • The W register (with or without an address this group ofdsPIC30F devices and is not modifier) or file register (specified by the value of intended to be a complete reference ‘Ws’ or ‘f’) source. For more information on the CPU, • The bit in the W register or file register peripherals, register descriptions and (specified by a literal value or indirectly by the general device functionality, refer to the contents of register ‘Wb’) “dsPIC30F Family Reference Manual” (DS70046). For more information on the The literal instructions that involve data movement may device instruction set and programming, use some of the following operands: refer to the “16-bit MCU and DSC • A literal value to be loaded into a W register or file Programmer’s Reference Manual” register (specified by the value of ‘k’) (DS70157). • The W register or file register where the literal The dsPIC30F instruction set adds many value is to be loaded (specified by ‘Wb’ or ‘f’) enhancements to the previous PIC MCU instruction However, literal instructions that involve arithmetic or sets, while maintaining an easy migration from PIC logical operations use some of the following operands: MCU instruction sets. • The first source operand which is a register ‘Wb’ Most instructions are a single program memory word without any address modifier (24 bits). Only three instructions require two program • The second source operand which is a literal memory locations. value Each single-word instruction is a 24-bit word divided • The destination of the result (only if not the same into an 8-bit opcode which specifies the instruction as the first source operand) which is typically a type, and one or more operands which further specify register ‘Wd’ with or without an address modifier the operation of the instruction. The MAC class of DSP instructions may use some of the The instruction set is highly orthogonal and is grouped following operands: into five basic categories: • The accumulator (A or B) to be used (required • Word or byte-oriented operations operand) • Bit-oriented operations • The W registers to be used as the two operands • Literal operations • The X and Y address space prefetch operations • DSP operations • The X and Y address space prefetch destinations • Control operations • The accumulator write back destination Table21-1 shows the general symbols used in The other DSP instructions do not involve any describing the instructions. multiplication, and may include: The dsPIC30F instruction set summary in Table21-2 • The accumulator to be used (required) lists all the instructions, along with the status flags • The source or destination operand (designated as affected by each instruction. Wso or Wdo, respectively) with or without an Most word or byte-oriented W register instructions address modifier (including barrel shift instructions) have three • The amount of shift specified by a W register ‘Wn’ operands: or a literal value • The first source operand which is typically a The control instructions may use some of the following register ‘Wb’ without any address modifier operands: • The second source operand which is typically a • A program memory address register ‘Ws’ with or without an address modifier • The mode of the table read and table write • The destination of the result which is typically a instructions register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: • The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2011 Microchip Technology Inc. DS70143E-page 161

dsPIC30F6011A/6012A/6013A/6014A All instructions are a single word, except for certain which are single-word instructions but take two or three double word instructions, which were made double cycles. Certain instructions that involve skipping over word instructions so that all the required information is the subsequent instruction require either two or three available in these 48 bits. In the second word, the cycles if the skip is performed, depending on whether 8MSbs are ‘0’s. If this second word is executed as an the instruction being skipped is a single-word or two- instruction (by itself), it will execute as a NOP. word instruction. Moreover, double word moves require two cycles. The double word instructions execute in Most single-word instructions are executed in a single two instruction cycles. instruction cycle, unless a conditional test is true or the Program Counter is changed as a result of the instruc- Note: For more details on the instruction set, tion. In these cases, the execution takes two instruction refer to the “16-bit MCU and DSC cycles with the additional instruction cycle(s) executed Programmer’s Reference Manual”. as a NOP. Notable exceptions are the BRA (uncondi- tional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double Word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator write back destination address register ∈ {W13, [W13] + = 2} bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...15} C, DC, N, OV, Z MCU status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address ∈ {0x0000...0x1FFF} lit1 1-bit unsigned literal ∈ {0,1} lit4 4-bit unsigned literal ∈ {0...15} lit5 5-bit unsigned literal ∈ {0...31} lit8 8-bit unsigned literal ∈ {0...255} lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal ∈ {0...16384} lit16 16-bit unsigned literal ∈ {0...65535} lit23 23-bit unsigned literal ∈ {0...8388608}; LSB must be 0 None Field does not require an entry, may be blank OA, OB, SA, SB DSP status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate PC Program Counter Slit10 10-bit signed literal ∈ {-512...511} Slit16 16-bit signed literal ∈ {-32768...32767} Slit6 6-bit signed literal ∈ {-16...16} DS70143E-page 162 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wb Base W register ∈ {W0..W15} Wd Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register ∈ { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing) Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈ {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈ {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 working registers ∈ {W0..W15} Wnd One of 16 destination working registers ∈ {W0..W15} Wns One of 16 source working registers ∈ {W0..W15} WREG W0 (working register used in file register instructions) Ws Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register ∈ { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wx X data space prefetch address register for DSP instructions ∈ {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12],none} Wxd X data space prefetch destination register for DSP instructions ∈ {W4..W7} Wy Y data space prefetch address register for DSP instructions ∈ {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Wyd Y data space prefetch destination register for DSP instructions ∈ {W4..W7} © 2011 Microchip Technology Inc. DS70143E-page 163

dsPIC30F6011A/6012A/6013A/6014A TABLE 21-2: INSTRUCTION SET OVERVIEW Base Assembly Assembly Syntax Description # of # of Status Flags Instr # Mnemonic Words Cycles Affected 1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB 2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z 3 AND AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z 4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z 5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None 6 BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if greater than or equal 1 1 (2) None BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None BRA GT,Expr Branch if greater than 1 1 (2) None BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None BRA LE,Expr Branch if less than or equal 1 1 (2) None BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None BRA LT,Expr Branch if less than 1 1 (2) None BRA LTU,Expr Branch if unsigned less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OA,Expr Branch if Accumulator A overflow 1 1 (2) None BRA OB,Expr Branch if Accumulator B overflow 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA SA,Expr Branch if Accumulator A saturated 1 1 (2) None BRA SB,Expr Branch if Accumulator B saturated 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None 7 BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None 8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None DS70143E-page 164 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Assembly Syntax Description # of # of Status Flags Instr # Mnemonic Words Cycles Affected 9 BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None 10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3) 11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) 12 BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z 13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z 14 CALL CALL lit23 Call subroutine 2 2 None CALL Wn Call indirect subroutine 1 2 None 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB 16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep 17 COM COM f f = f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z 18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb - Ws) 1 1 C,DC,N,OV,Z 19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z 20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z (Wb - Ws - C) 21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1 None (2 or 3) 22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1 None (2 or 3) 23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1 None (2 or 3) 24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if ≠ 1 1 None (2 or 3) 25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C 26 DEC DEC f f = f -1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f -1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws - 1 1 1 C,DC,N,OV,Z 27 DEC2 DEC2 f f = f -2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f -2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws - 2 1 1 C,DC,N,OV,Z 28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None © 2011 Microchip Technology Inc. DS70143E-page 165

dsPIC30F6011A/6012A/6013A/6014A TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Assembly Syntax Description # of # of Status Flags Instr # Mnemonic Words Cycles Affected 29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV 30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV 31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 None DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indirect 1 2 None 39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z 41 IOR IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 43 LNK LNK #lit14 Link frame pointer 1 1 None 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z 45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply and Accumulate 1 1 OA,OB,OAB, , SA,SB,SAB AWB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB 46 MOV MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 N,Z MOV f,WREG Move f to WREG 1 1 N,Z MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N,Z MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None 47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store accumulator 1 1 None DS70143E-page 166 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Assembly Syntax Description # of # of Status Flags Instr # Mnemonic Words Cycles Affected 48 MPY MPY Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, Wm*Wn,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB MPY Square Wm to Accumulator 1 1 OA,OB,OAB, Wm*Wm,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB 49 MPY.N MPY.N -(Multiply Wm by Wn) to Accumulator 1 1 None Wm*Wn,Acc,Wx,Wxd,Wy,Wyd 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, , SA,SB,SAB AWB 51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(Ws) MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(lit5) MUL f W3:W2 = f * WREG 1 1 None 52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f = f + 1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 53 NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None 54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None W(nd):W(nd+1) POP.S Pop Shadow Registers 1 1 All 55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None 56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep 57 RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None 58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None 59 RESET RESET Software device Reset 1 1 None 60 RETFIE RETFIE Return from interrupt 1 3 (2) None 61 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None 62 RETURN RETURN Return from Subroutine 1 3 (2) None 63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z 64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z 65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z © 2011 Microchip Technology Inc. DS70143E-page 167

dsPIC30F6011A/6012A/6013A/6014A TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Assembly Syntax Description # of # of Status Flags Instr # Mnemonic Words Cycles Affected 66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None 68 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z 69 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None 70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB 71 SL SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z 72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f - WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f - WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn - lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb - Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb - lit5 1 1 C,DC,N,OV,Z 73 SUBB SUBB f f = f - WREG - (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f - WREG - (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn - lit10 - (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb - Ws - (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb - lit5 - (C) 1 1 C,DC,N,OV,Z 74 SUBR SUBR f f = WREG - f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG - f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws - Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 - Wb 1 1 C,DC,N,OV,Z 75 SUBBR SUBBR f f = WREG - f - (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG -f - (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws - Wb - (C) 1 1 C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 - Wb - (C) 1 1 C,DC,N,OV,Z 76 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None SWAP Wn Wn = byte swap Wn 1 1 None 77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None 78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None 79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 81 ULNK ULNK Unlink frame pointer 1 1 None 82 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z 83 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N DS70143E-page 168 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 22.0 DEVELOPMENT SUPPORT 22.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® • Integrated Development Environment operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2011 Microchip Technology Inc. DS70143E-page 169

dsPIC30F6011A/6012A/6013A/6014A 22.2 MPLAB C Compilers for Various 22.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 22.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 22.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 22.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS70143E-page 170 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 22.7 MPLAB SIM Software Simulator 22.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 22.10 PICkit 3 In-Circuit Debugger/ Programmer and 22.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2011 Microchip Technology Inc. DS70143E-page 171

dsPIC30F6011A/6012A/6013A/6014A 22.11 PICkit 2 Development 22.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 22.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS70143E-page 172 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 23.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. For detailed information about the dsPIC30F architecture and core, refer to “dsPIC30F Family Reference Manual” (DS70046). Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR)(1)................................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V Voltage on MCLR with respect to VSS .......................................................................................................0V to +13.25V Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin(2)...........................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports(2)...............................................................................................................200 mA Note 1: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latchup. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. 2: Maximum allowable current is a function of device maximum power dissipation. See Table23-2 for PDMAX. †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2011 Microchip Technology Inc. DS70143E-page 173

dsPIC30F6011A/6012A/6013A/6014A 23.1 DC Characteristics TABLE 23-1: OPERATING MIPS VS. VOLTAGE Max MIPS VDD Range Temp Range dsPIC30F601XA-30I dsPIC30F601XA-20E 4.5-5.5V -40°C to 85°C 30 — 4.5-5.5V -40°C to 125°C — 20 3.0-3.6V -40°C to 85°C 15 — 3.0-3.6V -40°C to 125°C — 10 2.5-3.0V -40°C to 85°C 10 — TABLE 23-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit dsPIC30F601xA-30I Operating Junction Temperature Range T -40 — +125 °C J Operating Ambient Temperature Range T -40 — +85 °C A dsPIC30F601xA-20E Operating Junction Temperature Range T -40 — +150 °C J Operating Ambient Temperature Range T -40 — +125 °C A Power Dissipation: Internal chip power dissipation: P = V × (I –∑I ) P P + P W INT DD DD OH D INT I/O I/O Pin power dissipation: P = ∑({V –V }× I )+∑(V × I ) I/O DD OH OH OL OL θ Maximum Allowed Power Dissipation PDMAX (T - T)/ W J A JA TABLE 23-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes θ Package Thermal Resistance, 80-pin TQFP (14x14x1mm) 34 — °C/W 1 JA θ Package Thermal Resistance, 64-pin TQFP (14x14x1mm) 34 — °C/W 1 JA θ Package Thermal Resistance, 80-pin TQFP (12x12x1mm) 39 — °C/W 1 JA θ Package Thermal Resistance, 64-pin TQFP (10x10x1mm) 39 — °C/W 1 JA θ Note 1: Junction to ambient thermal resistance, Theta-ja ( ) numbers are achieved by package simulations. JA DS70143E-page 174 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A T ABLE 23-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Operating Voltage(2) DC10 VDD Supply Voltage 2.5 — 5.5 V Industrial temperature DC11 VDD Supply Voltage 3.0 — 5.5 V Extended temperature DC12 VDR RAM Data Retention Voltage(3) 1.75 — — V DC16 VPOR VDD Start Voltage — VSS — V to ensure internal Power-on Reset signal DC17 SVDD VDD Rise Rate 0.05 — — V/ms 0-5V in 0.1 sec to ensure internal 0-3V in 60 ms Power-on Reset signal Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which VDD can be lowered without losing RAM data. © 2011 Microchip Technology Inc. DS70143E-page 175

dsPIC30F6011A/6012A/6013A/6014A T ABLE 23-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Parameter Typical(1) Max Units Conditions No. Operating Current (IDD)(2) DC31a 3.1 6 mA 25°C DC31b 3.2 6 mA 85°C 3.3V DC31c 3.1 6 mA 125°C 0.128 MIPS DC31e 5.7 9 mA 25°C LPRC (512 kHz) DC31f 5.5 9 mA 85°C 5V DC31g 5.5 9 mA 125°C DC30a 10 15 mA 25°C DC30b 10 15 mA 85°C 3.3V DC30c 10 15 mA 125°C (1.8 MIPS) DC30e 17 26 mA 25°C FRC (7.37 MHz) DC30f 17 26 mA 85°C 5V DC30g 17 26 mA 125°C DC23a 19 30 mA 25°C DC23b 20 30 mA 85°C 3.3V DC23c 20 30 mA 125°C 4 MIPS DC23e 32 50 mA 25°C DC23f 32 50 mA 85°C 5V DC23g 33 50 mA 125°C DC24a 45 68 mA 25°C DC24b 45 68 mA 85°C 3.3V DC24c 46 68 mA 125°C 10 MIPS DC24e 74 105 mA 25°C DC24f 74 105 mA 85°C 5V DC24g 75 105 mA 125°C DC27d 140 180 mA 25°C DC27e 138 180 mA 85°C 5V 20 MIPS DC27f 138 180 mA 125°C DC29a 203 250 mA 25°C 5V 30 MIPS DC29b 202 250 mA 85°C Note1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail to rail. All I/O pins are configured as Inputs and pulled to VDD. MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating. DS70143E-page 176 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A T ABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Parameter Typical(1) Max Units Conditions No. Operating Current (IIDLE)(2) DC51a 2.5 5 mA 25°C DC51b 2.6 5 mA 85°C 3.3V DC51c 2.6 5 mA 125°C 0.128 MIPS DC51e 5.5 8 mA 25°C LPRC (512 kHz) DC51f 5.3 8 mA 85°C 5V DC51g 5.2 8 mA 125°C DC50a 6.7 13 mA 25°C DC50b 6.7 13 mA 85°C 3.3V DC50c 6.8 13 mA 125°C (1.8 MIPS) DC50e 8.5 19 mA 25°C FRC (7.37 MHz) DC50f 8.5 19 mA 85°C 5V DC50g 8.6 19 mA 125°C DC43a 8.7 20 mA 25°C DC43b 8.7 20 mA 85°C 3.3V DC43c 8.8 20 mA 125°C 4 MIPS DC43e 14 31 mA 25°C DC43f 14 31 mA 85°C 5V DC43g 14 31 mA 125°C DC44a 16 37 mA 25°C DC44b 17 37 mA 85°C 3.3V DC44c 17 37 mA 125°C 10 MIPS DC44e 28 62 mA 25°C DC44f 28 62 mA 85°C 5V DC44g 28 62 mA 125°C DC47d 48 110 mA 25°C DC47e 49 110 mA 85°C 5V 20 MIPS DC47f 49 110 mA 125°C DC49a 69 150 mA 25°C 5V 30 MIPS DC49b 70 150 mA 85°C Note1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base IIDLE current is measured with Core off, Clock on and all modules turned off. © 2011 Microchip Technology Inc. DS70143E-page 177

dsPIC30F6011A/6012A/6013A/6014A T ABLE 23-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Parameter Typical Max Units Conditions No. Power Down Current (IPD) DC60a 0.5 — μA 25°C DC60b 1 40 μA 85°C 3.3V DC60c 24 65 μA 125°C Base Power Down Current(1) DC60e 0.7 — μA 25°C DC60f 4 55 μA 85°C 5V DC60g 35 90 μA 125°C DC61a 9 20 μA 25°C DC61b 9 20 μA 85°C 3.3V DC61c 8 20 μA 125°C Watchdog Timer Current: ΔIWDT(2) DC61e 18 40 μA 25°C DC61f 16 40 μA 85°C 5V DC61g 15 40 μA 125°C DC62a 4 10 μA 25°C DC62b 5 10 μA 85°C 3.3V DC62c 4 10 μA 125°C Timer 1 w/32 kHz Crystal: ΔITI32(2) DC62e 4 15 μA 25°C DC62f 6 15 μA 85°C 5V DC62g 5 15 μA 125°C DC63a 30 55 μA 25°C DC63b 34 55 μA 85°C 3.3V DC63c 35 55 μA 125°C BOR On: ΔIBOR(2) DC63e 36 60 μA 25°C DC63f 39 60 μA 85°C 5V DC63g 40 60 μA 125°C DC66a 20 35 μA 25°C DC66b 22 35 μA 85°C 3.3V DC66c 23 35 μA 125°C Low Voltage Detect: ΔILVD(2) DC66e 24 40 μA 25°C DC66f 26 40 μA 85°C 5V DC66g 26 40 μA 125°C Note1: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. LVD, BOR, WDT, etc. are all switched off. 2: The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. DS70143E-page 178 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A T ABLE 23-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VIL Input Low Voltage(2) DI10 I/O pins: with Schmitt Trigger buffer VSS — 0.2VDD V DI15 MCLR VSS — 0.2VDD V DI16 OSC1 (in XT, HS and LP modes) VSS — 0.2VDD V DI17 OSC1 (in RC mode)(3) VSS — 0.3VDD V DI18 SDA, SCL VSS — 0.3VDD V SMbus disabled DI19 SDA, SCL VSS — 0.8 V SMbus enabled VIH Input High Voltage(2) DI20 I/O pins: with Schmitt Trigger buffer 0.8VDD — VDD V DI25 MCLR 0.8VDD — VDD V DI26 OSC1 (in XT, HS and LP modes) 0.7VDD — VDD V DI27 OSC1 (in RC mode)(3) 0.9VDD — VDD V DI28 SDA, SCL 0.7VDD — VDD V SMbus disabled DI29 SDA, SCL 2.1 — VDD V SMbus enabled ICNPU CNXX Pull-up Current(2) DI30 50 250 400 μA VDD = 5V, VPIN = VSS IIL Input Leakage Current(2)(4)(5) DI50 I/O ports — 0.01 ±1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance DI51 Analog input pins — 0.50 — μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance DI55 MCLR — 0.05 ±5 μA VSS ≤ VPIN ≤ VDD DI56 OSC1 — 0.05 ±5 μA VSS ≤ VPIN ≤ VDD, XT, HS and LP Osc mode Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that the dsPIC30F device be driven with an external clock while in RC mode. 4: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2011 Microchip Technology Inc. DS70143E-page 179

dsPIC30F6011A/6012A/6013A/6014A T A BLE 23-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VOL Output Low Voltage(2) DO10 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 5V — — 0.15 V IOL = 2.0 mA, VDD = 3V DO16 OSC2/CLKOUT — — 0.6 V IOL = 1.6 mA, VDD = 5V (RC or EC Osc mode) — — 0.72 V IOL = 2.0 mA, VDD = 3V VOH Output High Voltage(2) DO20 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 5V VDD – 0.2 — — V IOH = -2.0 mA, VDD = 3V DO26 OSC2/CLKOUT VDD – 0.7 — — V IOH = -1.3 mA, VDD = 5V (RC or EC Osc mode) VDD – 0.1 — — V IOH = -2.0 mA, VDD = 3V Capacitive Loading Specs on Output Pins(2) DO50 COSC2 OSC2/SOSC2 pin — — 15 pF In XTL, XT, HS and LP modes when external clock is used to drive OSC1. DO56 CIO All I/O pins and OSC2 — — 50 pF RC or EC Osc mode DO58 CB SCL, SDA — — 400 pF In I2C™ mode Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. FIGURE 23-1: LOW-VOLTAGE DETECT CHARACTERISTICS VDD LV10 LVDIF (LVDIF set by hardware) DS70143E-page 180 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A T ABLE 23-10: ELECTRICAL CHARACTERISTICS: LVDL Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. LV10 VPLVD LVDL Voltage on VDD transition LVDL = 0000(2) — — — V high to low LVDL = 0001(2) — — — V LVDL = 0010(2) — — — V LVDL = 0011(2) — — — V LVDL = 0100 2.50 — 2.65 V LVDL = 0101 2.70 — 2.86 V LVDL = 0110 2.80 — 2.97 V LVDL = 0111 3.00 — 3.18 V LVDL = 1000 3.30 — 3.50 V LVDL = 1001 3.50 — 3.71 V LVDL = 1010 3.60 — 3.82 V LVDL = 1011 3.80 — 4.03 V LVDL = 1100 4.00 — 4.24 V LVDL = 1101 4.20 — 4.45 V LVDL = 1110 4.50 — 4.77 V LV15 VLVDIN External LVD input pin LVDL = 1111 — — — V threshold voltage Note 1: These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. FIGURE 23-2: BROWN-OUT RESET CHARACTERISTICS VDD (Device not in Brown-out Reset) BO15 BO10 (Device in Brown-out Reset) Reset (due to BOR) Power Up Time-out © 2011 Microchip Technology Inc. DS70143E-page 181

dsPIC30F6011A/6012A/6013A/6014A T ABLE 23-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. BO10 VBOR BOR Voltage(2) on BORV = 11(3) — — — V Not in operating VDD transition high to range low BORV = 10 2.6 — 2.71 V BORV = 01 4.1 — 4.4 V BORV = 00 4.58 — 4.73 V BO15 VBHYS — 5 — mV Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: ’11’ values not in usable operating range. TABLE 23-12: DC CHARACTERISTICS: PROGRAM AND EEPROM Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Data EEPROM Memory(2) D120 ED Byte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time 0.8 2 2.6 ms RTSP D123 TRETD Characteristic Retention 40 100 — Year Provided no other specifications are violated D124 IDEW IDD During Programming — 10 30 mA Row Erase Program FLASH Memory(2) D130 EP Cell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VEB VDD for Bulk Erase 4.5 — 5.5 V D133 VPEW VDD for Erase/Write 3.0 — 5.5 V D134 TPEW Erase/Write Cycle Time 0.8 2 2.6 ms RTSP D135 TRETD Characteristic Retention 40 100 — Year Provided no other specifications are violated D137 IPEW IDD During Programming — 10 30 mA Row Erase D138 IEB IDD During Programming — 10 30 mA Bulk Erase Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. DS70143E-page 182 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 23.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 23-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Operating voltage VDD range as described in Table23-1. FIGURE 23-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS CL Pin RL = 464Ω CL = 50 pF for all pins except OSC2 VSS 5 pF for OSC2 output FIGURE 23-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 OS20 OS30 OS30 OS31 OS31 OS25 CLKOUT OS40 OS41 © 2011 Microchip Technology Inc. DS70143E-page 183

dsPIC30F6011A/6012A/6013A/6014A T ABLE 23-14: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS10 FOSC External CLKIN Frequency(2) DC — 40 MHz EC (External clocks allowed only 4 — 10 MHz EC with 4x PLL in EC mode) 4 — 10 MHz EC with 8x PLL 4 — 7.5(3) MHz EC with 16x PLL Oscillator Frequency(2) DC — 4 MHz RC 0.4 — 4 MHz XTL 4 — 10 MHz XT 4 — 10 MHz XT with 4x PLL 4 — 10 MHz XT with 8x PLL 4 — 7.5(3) MHz XT with 16x PLL 10 — 25 MHz HS 10 — 20(4) MHz HS/2 with 4x PLL 10 — 20(4) MHz HS/2 with 8x PLL 10 — 15(3) MHz HS/2 with 16x PLL 12(4) — 25 MHz HS/3 with 4x PLL 12(4) — 25 MHz HS/3 with 8x PLL 12(4) — 22.5(3) MHz HS/3 with 16x PLL — 32.768 — kHz LP OS20 TOSC TOSC = 1/FOSC — — — — See parameter OS10 for FOSC value OS25 TCY Instruction Cycle Time(2)(5) 33 — DC ns See Table23-16 OS30 TosL, External Clock(2) in (OSC1) .45 x TOSC — — ns EC TosH High or Low Time OS31 TosR, External Clock(2) in (OSC1) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKOUT Rise Time(2)(6) — — — ns See parameter DO31 OS41 TckF CLKOUT Fall Time(2)(6) — — — ns See parameter DO32 Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: Limited by the PLL output frequency range. 4: Limited by the PLL input frequency range. 5: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. 6: Measurements are taken in EC or ERC modes. The CLKOUT signal is measured on the OSC2 pin. CLKOUT is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). DS70143E-page 184 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A TABLE 23-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5V) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. OS50 FPLLI PLL Input Frequency Range(2) 4 — 10 MHz EC with 4x PLL 4 — 10 MHz EC with 8x PLL 4 — 7.5(4) MHz EC with 16x PLL 4 — 10 MHz XT with 4x PLL 4 — 10 MHz XT with 8x PLL 4 — 7.5(4) MHz XT with 16x PLL 5(3) — 10 MHz HS/2 with 4x PLL 5(3) — 10 MHz HS/2 with 8x PLL 5(3) — 7.5(4) MHz HS/2 with 16x PLL 4 — 8.33(3) MHz HS/3 with 4x PLL 4 — 8.33(3) MHz HS/3 with 8x PLL 4 — 7.5(4) MHz HS/3 with 16x PLL OS51 FSYS On-Chip PLL Output(2) 16 — 120 MHz EC, XT, HS/2, HS/3 modes with PLL OS52 TLOC PLL Start-up Time (Lock Time) — 20 50 μs Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Limited by oscillator frequency range. 4: Limited by device operating frequency range. TABLE 23-16: PLL JITTER Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Characteristic Min Typ(1) Max Units Conditions No. OS61 x4 PLL — 0.251 0.413 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V — 0.251 0.413 % -40°C ≤ TA ≤ +125°C VDD = 3.0 to 3.6V — 0.256 0.47 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V — 0.256 0.47 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V x8 PLL — 0.355 0.584 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V — 0.355 0.584 % -40°C ≤ TA ≤ +125°C VDD = 3.0 to 3.6V — 0.362 0.664 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V — 0.362 0.664 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V x16 PLL — 0.67 0.92 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V — 0.632 0.956 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V — 0.632 0.956 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V Note 1: These parameters are characterized but not tested in manufacturing. © 2011 Microchip Technology Inc. DS70143E-page 185

dsPIC30F6011A/6012A/6013A/6014A T ABLE 23-17: INTERNAL CLOCK TIMING EXAMPLES Clock Oscillator (MFHOzS)C(1 ) TCY (μsec)(2) wM/IoP PSL(3L) wM PIPLSL( 3x)4 wM PIPLSL( 3x)8 wM PILPLS (x31)6 Mode EC 0.200 20.0 0.05 — — — 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 — 25 0.16 6.25 — — — XT 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 — Note 1: Assumption: Oscillator Postscaler is divide by 1. 2: Instruction Execution Cycle Time: TCY = 1/MIPS. 3: Instruction Execution Frequency: MIPS = (FOSC * PLLx)/4. TABLE 23-18: AC CHARACTERISTICS: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. Internal FRC Accuracy @ FRC Freq. = 7.37 MHz(1) OS63 FRC — — ±2.00 % -40°C ≤ TA ≤ +85°C VDD = 3.0-5.5V — — ±5.00 % -40°C ≤ TA ≤ +125°C VDD = 3.0-5.5V Note 1: Frequency calibrated at 7.372 MHz ±2%, 25°C and 5V. TUN bits (OSCCON<3:0>) can be used to compensate for temperature drift. TABLE 23-19: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. LPRC @ Freq. = 512 kHz(1) OS65A -50 — +50 % VDD = 5.0V, ±10% OS65B -60 — +60 % VDD = 3.3V, ±10% OS65C -70 — +70 % VDD = 2.5V Note 1: Change of LPRC frequency as VDD changes. DS70143E-page 186 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-5: CLKOUT AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure23-3 for load conditions. TABLE 23-20: CLKOUT AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1)(2)(3) Min Typ(4) Max Units Conditions No. DO31 TIOR Port output rise time — 7 20 ns DO32 TIOF Port output fall time — 7 20 ns DI35 TINP INTx pin high or low time (output) 20 — — ns DI40 TRBP CNx high or low time (input) 2 TCY — — ns Note 1: These parameters are asynchronous events not related to any internal clock edges 2: Measurements are taken in RC mode and EC mode where CLKOUT output is 4 x TOSC. 3: These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2011 Microchip Technology Inc. DS70143E-page 187

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD SY12 MCLR Internal SY10 POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure23-3 for load conditions. DS70143E-page 188 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A T A B LE 23-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SY10 TmcL MCLR Pulse Width (low) 2 — — μs -40°C to +85°C SY11 TPWRT Power-up Timer Period 2 4 6 ms -40°C to +85°C, VDD = 8 16 24 5V 32 64 96 User programmable SY12 TPOR Power-on Reset Delay(3) 3 10 30 μs -40°C to +85°C SY13 TIOZ I/O high-impedance from MCLR — 0.8 1.0 μs Low or Watchdog Timer Reset SY20 TWDT1 Watchdog Timer Time-out Period 0.6 2.0 3.4 ms VDD = 2.5V TWDT2 (No Prescaler) 0.8 2.0 3.2 ms VDD = 3.3V, ±10% TWDT3 1.0 2.0 3.0 ms VDD = 5V, ±10% SY25 TBOR Brown-out Reset Pulse Width(4) 100 — — μs VDD ≤ VBOR (D034) SY30 TOST Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 900 μs -40°C to +85°C Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Characterized by design but not tested 4: Refer to Figure23-2 and Table23-11 for BOR. © 2011 Microchip Technology Inc. DS70143E-page 189

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-7: BAND GAP START-UP TIME CHARACTERISTICS VBGAP 0V Enable Band Gap (see Note) Band Gap SY40 Stable Note: Set LVDEN bit (RCON<12>) or BOREN bit (FBORPOR<7>). TABLE 23-22: BAND GAP START-UP TIME REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SY40 TBGAP Band Gap Start-up Time — 40 65 µs Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. RCON<13> Status bit Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. DS70143E-page 190 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-8: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRX Note: Refer to Figure23-3 for load conditions. TABLE 23-23: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TA10 TTXH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TA15 Synchronous, 10 — — ns with prescaler Asynchronous 10 — — ns TA11 TTXL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TA15 Synchronous, 10 — — ns with prescaler Asynchronous 10 — — ns TA15 TTXP TxCK Input Period Synchronous, TCY + 10 — — ns no prescaler Synchronous, Greater of: — — — N = prescale with prescaler 20 ns or value (TCY + 40)/N (1, 8, 64, 256) Asynchronous 20 — — ns OS60 Ft1 SOSC1/T1CK oscillator input DC — 50 kHz frequency range (oscillator enabled by setting bit TCS (T1CON, bit 1)) TA20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 — Edge to Timer Increment TCY Note1: Timer1 is a Type A. © 2011 Microchip Technology Inc. DS70143E-page 191

dsPIC30F6011A/6012A/6013A/6014A T ABLE 23-24: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TB10 TtxH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TB15 Synchronous, 10 — — ns with prescaler TB11 TtxL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TB15 Synchronous, 10 — — ns with prescaler TB15 TtxP TxCK Input Period Synchronous, TCY + 10 — — ns N = prescale no prescaler value Synchronous, Greater of: (1, 8, 64, 256) with prescaler 20 ns or (TCY + 40)/N TB20 TCKEXT- Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — MRL Edge to Timer Increment Note1: Timer2 and Timer4 are Type B. TABLE 23-25: TYPE C TIMER (TIMER3 AND TIMER5) EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet parameter TC15 TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet parameter TC15 TC15 TtxP TxCK Input Period Synchronous, TCY + 10 — — ns N = prescale no prescaler value Synchronous, Greater of: (1, 8, 64, 256) with prescaler 20 ns or (TCY + 40)/N TC20 TCKEXT- Delay from External TxCK Clock 0.5 TCY — 1.5 — MRL Edge to Timer Increment TCY Note1: Timer3 and Timer5 are Type C. DS70143E-page 192 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICX IC10 IC11 IC15 Note: Refer to Figure23-3 for load conditions. TABLE 23-26: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Max Units Conditions No. IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns With Prescaler 10 — ns IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns With Prescaler 10 — ns IC15 TccP ICx Input Period (2 TCY + 40)/N — ns N = prescale value (1, 4, 16) Note 1: These parameters are characterized but not tested in manufacturing. FIGURE 23-10: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure23-3 for load conditions. TABLE 23-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. OC10 TccF OCx Output Fall Time — — — ns See Parameter DO32 OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31 Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2011 Microchip Technology Inc. DS70143E-page 193

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-11: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 23-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Para Symb m Characteristic(1) Min Typ(2) Max Units Conditions ol No. OC15 TFD Fault Input to PWM I/O — — 50 ns Change OC20 TFLT Fault Input Pulse Width 50 — — ns Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70143E-page 194 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-12: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING CHARACTERISTICS CSCK (SCKE = 0) CS11 CS10 CS21 CS20 CSCK (SCKE = 1) CS20 CS21 COFS CS55CS56 CS35 CS51 CS50 70 HIGH-Z MSb LSb HIGH-Z CSDO CS30 CS31 CSDI MSb IN LSb IN CS40 CS41 Note: Refer to Figure23-3 for load conditions. © 2011 Microchip Technology Inc. DS70143E-page 195

dsPIC30F6011A/6012A/6013A/6014A T ABLE 23-29: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. CS10 TcSCKL CSCK Input Low Time TCY/2 + 20 — — ns (CSCK pin is an input) CSCK Output Low Time(3) 30 — — ns (CSCK pin is an output) CS11 TcSCKH CSCK Input High Time TCY/2 + 20 — — ns (CSCK pin is an input) CSCK Output High Time(3) 30 — — ns (CSCK pin is an output) CS20 TcSCKF CSCK Output Fall Time(4) — 10 25 ns (CSCK pin is an output) CS21 TcSCKR CSCK Output Rise Time(4) — 10 25 ns (CSCK pin is an output) CS30 TcSDOF CSDO Data Output Fall Time(4) — 10 25 ns CS31 TcSDOR CSDO Data Output Rise Time(4) — 10 25 ns CS35 TDV Clock edge to CSDO data valid — — 10 ns CS36 TDIV Clock edge to CSDO tri-stated 10 — 20 ns CS40 TCSDI Setup time of CSDI data input to 20 — — ns CSCK edge (CSCK pin is input or output) CS41 THCSDI Hold time of CSDI data input to 20 — — ns CSCK edge (CSCK pin is input or output) CS50 TcoFSF COFS Fall Time — 10 25 ns (COFS pin is output)(4) CS51 TcoFSR COFS Rise Time — 10 25 ns (COFS pin is output)(4) CS55 TscoFS Setup time of COFS data input to 20 — — ns CSCK edge (COFS pin is input) CS56 THCOFS Hold time of COFS data input to 20 — — ns CSCK edge (COFS pin is input) Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all DCI pins. DS70143E-page 196 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-13: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 CS62 CS21 CS20 CS71 CS70 CS72 SYNC (COFS) CS76 CS75 CS80 LSb MSb LSb SDO (CSDO) CS76 CS75 SDI MSb IN (CSDI) CS65 CS66 TABLE 23-30: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1)(2) Min Typ(3) Max Units Conditions No. CS60 TBCLKL BIT_CLK Low Time 36 40.7 45 ns CS61 TBCLKH BIT_CLK High Time 36 40.7 45 ns CS62 TBCLK BIT_CLK Period — 81.4 — ns Bit clock is input CS65 TSACL Input Setup Time to — — 10 ns Falling Edge of BIT_CLK CS66 THACL Input Hold Time from — — 10 ns Falling Edge of BIT_CLK CS70 TSYNCLO SYNC Data Output Low Time — 19.5 — μs Note 1 CS71 TSYNCHI SYNC Data Output High Time — 1.3 — μs Note 1 CS72 TSYNC SYNC Data Output Period — 20.8 — μs Note 1 CS75 TRACL Rise Time, SYNC, — 10 25 ns CLOAD = 50 pF, VDD = 5V SDATA_OUT CS76 TFACL Fall Time, SYNC, SDATA_OUT — 10 25 ns CLOAD = 50 pF, VDD = 5V CS80 TOVDACL Output valid delay from rising — — 15 ns edge of BIT_CLK Note 1: These parameters are characterized but not tested in manufacturing. 2: These values assume BIT_CLK frequency is 12.288 MHz. 3: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2011 Microchip Technology Inc. DS70143E-page 197

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-14: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb BIT14 - - - - - -1 LSb SP31 SP30 SDIx MSb IN BIT14 - - - -1 LSb IN SP40 SP41 Note: Refer to Figure23-3 for load conditions. TABLE 23-31: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscL SCKX Output Low Time(3) TCY / 2 — — ns SP11 TscH SCKX Output High Time(3) TCY/2 — — ns SP20 TscF SCKX Output Fall Time(4) — — — ns See parameter DO32 SP21 TscR SCKX Output Rise Time(4) — — — ns See parameter DO31 SP30 TdoF SDOX Data Output Fall Time(4) — — — ns See parameter DO32 SP31 TdoR SDOX Data Output Rise — — — ns See parameter DO31 Time(4) SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns TscL2doV SCKX Edge SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns TdiV2scL to SCKX Edge SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns TscL2diL to SCKX Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. DS70143E-page 198 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-15: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SCKX (CKP = 1) SP35 SP20 SP21 SDOX MSb BIT14 - - - - - -1 LSb SP40 SP30,SP31 SDIX MSb IN BIT14 - - - -1 LSb IN SP41 Note: Refer to Figure23-3 for load conditions. TABLE 23-32: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscL SCKX output low time(3) TCY/2 — — ns SP11 TscH SCKX output high time(3) TCY/2 — — ns SP20 TscF SCKX output fall time(4) — — — ns See parameter DO32 SP21 TscR SCKX output rise time(4) — — — ns See parameter DO31 SP30 TdoF SDOX data output fall time(4) — — — ns See parameter DO32 SP31 TdoR SDOX data output rise time(4) — — — ns See parameter DO31 SP35 TscH2doV, SDOX data output valid after — — 30 ns TscL2doV SCKX edge SP36 TdoV2sc, SDOX data output setup to 30 — — ns TdoV2scL first SCKX edge SP40 TdiV2scH, Setup time of SDIX data input 20 — — ns TdiV2scL to SCKX edge SP41 TscH2diL, Hold time of SDIX data input 20 — — ns TscL2diL to SCKX edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2011 Microchip Technology Inc. DS70143E-page 199

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-16: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOX MSb BIT14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIX MSb IN BIT14 - - - -1 LSb IN SP41 SP40 Note: Refer to Figure23-3 for load conditions. TABLE 23-33: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscL SCKX Input Low Time 30 — — ns SP71 TscH SCKX Input High Time 30 — — ns SP72 TscF SCKX Input Fall Time(3) — 10 25 ns SP73 TscR SCKX Input Rise Time(3) — 10 25 ns SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parameter DO32 SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parameter DO31 SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns TscL2doV SCKX Edge SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns TdiV2scL to SCKX Edge SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns TscL2diL to SCKX Edge SP50 TssL2scH, SSX↓ to SCKX↑ or SCKX↓ Input 120 — — ns TssL2scL SP51 TssH2doZ SSX↑ to SDOX Output 10 — 50 ns High-impedance(3) SP52 TscH2ssH SSX after SCK Edge 1.5 TCY + 40 — — ns TscL2ssH Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. DS70143E-page 200 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-17: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SCKX (CKP = 1) SP35 SP72 SP73 SP52 SDOX MSb BIT14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIX MSb IN BIT14 - - - -1 LSb IN SP41 SP40 Note: Refer to Figure23-3 for load conditions. © 2011 Microchip Technology Inc. DS70143E-page 201

dsPIC30F6011A/6012A/6013A/6014A TABLE 23-34: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscL SCKX Input Low Time 30 — — ns SP71 TscH SCKX Input High Time 30 — — ns SP72 TscF SCKX Input Fall Time(3) — 10 25 ns SP73 TscR SCKX Input Rise Time(3) — 10 25 ns SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parameter DO32 SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parameter DO31 SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns TscL2doV SCKX Edge SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns TdiV2scL to SCKX Edge SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns TscL2diL to SCKX Edge SP50 TssL2scH, SSX↓ to SCKX↓ or SCKX↑ input 120 — — ns TssL2scL SP51 TssH2doZ SS↑ to SDOX Output 10 — 50 ns High-impedance(4) SP52 TscH2ssH SSX↑ after SCKX Edge 1.5 TCY + 40 — — ns TscL2ssH SP60 TssL2doV SDOX Data Output Valid after — — 50 ns SSX Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. DS70143E-page 202 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-18: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM34 IM30 IM33 SDA Start Stop Condition Condition Note: Refer to Figure23-3 for load conditions. FIGURE 23-19: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM21 IM10 SCL IM11 IM26 IM10 IM25 IM33 SDA In IM40 IM40 IM45 SDA Out Note: Refer to Figure23-3 for load conditions. © 2011 Microchip Technology Inc. DS70143E-page 203

dsPIC30F6011A/6012A/6013A/6014A )T ABLE 23-35: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min(1) Max Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TCY / 2 (BRG + 1) — µs 400 kHz mode TCY / 2 (BRG + 1) — µs 1 MHz mode(2) TCY / 2 (BRG + 1) — µs IM11 THI:SCL Clock High Time 100 kHz mode TCY / 2 (BRG + 1) — µs 400 kHz mode TCY / 2 (BRG + 1) — µs 1 MHz mode(2) TCY / 2 (BRG + 1) — µs IM20 TF:SCL SDA and SCL 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 100 ns IM21 TR:SCL SDA and SCL 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) — — ns IM26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 µs 1 MHz mode(2) — — ns IM30 TSU:STA Start Condition 100 kHz mode TCY / 2 (BRG + 1) — µs Only relevant for Setup Time 400 kHz mode TCY / 2 (BRG + 1) — µs repeated Start condition 1 MHz mode(2) TCY / 2 (BRG + 1) — µs IM31 THD:STA Start Condition 100 kHz mode TCY / 2 (BRG + 1) — µs After this period the Hold Time 400 kHz mode TCY / 2 (BRG + 1) — µs first clock pulse is generated 1 MHz mode(2) TCY / 2 (BRG + 1) — µs IM33 TSU:STO Stop Condition 100 kHz mode TCY / 2 (BRG + 1) — µs Setup Time 400 kHz mode TCY / 2 (BRG + 1) — µs 1 MHz mode(2) TCY / 2 (BRG + 1) — µs IM34 THD:STO Stop Condition 100 kHz mode TCY / 2 (BRG + 1) — ns Hold Time 400 kHz mode TCY / 2 (BRG + 1) — ns 1 MHz mode(2) TCY / 2 (BRG + 1) — ns IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns From Clock 400 kHz mode — 1000 ns 1 MHz mode(2) — — ns IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — µs Time the bus must be free before a new 400 kHz mode 1.3 — µs transmission can start 1 MHz mode(2) — — µs IM50 CB Bus Capacitive Loading — 400 pF Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit™ (I2C)” (DS70046) in the “dsPIC30F Family Reference Manual” . 2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only). DS70143E-page 204 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-20: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS31 IS34 IS30 IS33 SDA Start Stop Condition Condition FIGURE 23-21: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS10 SCL IS30 IS26 IS31 IS25 IS33 SDA In IS40 IS40 IS45 SDA Out © 2011 Microchip Technology Inc. DS70143E-page 205

dsPIC30F6011A/6012A/6013A/6014A IT) ABLE 23-36: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Max Units Conditions No. IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs Device must operate at a minimum of 10 MHz. 1 MHz mode(1) 0.5 — μs IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — μs IS20 TF:SCL SDA and SCL 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 μs 1 MHz mode(1) 0 0.3 μs IS30 TSU:STA Start Condition 100 kHz mode 4.7 — μs Only relevant for repeated Setup Time 400 kHz mode 0.6 — μs Start condition 1 MHz mode(1) 0.25 — μs IS31 THD:STA Start Condition 100 kHz mode 4.0 — μs After this period the first Hold Time 400 kHz mode 0.6 — μs clock pulse is generated 1 MHz mode(1) 0.25 — μs IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — μs Setup Time 400 kHz mode 0.6 — μs 1 MHz mode(1) 0.6 — μs IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — ns 1 MHz mode(1) 250 ns IS40 TAA:SCL Output Valid 100 kHz mode 0 3500 ns From Clock 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode 1.3 — μs before a new transmission 1 MHz mode(1) 0.5 — μs can start IS50 CB Bus Capacitive Loading — 400 pF Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only). DS70143E-page 206 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-22: CAN MODULE I/O TIMING CHARACTERISTICS CXTX Pin Old Value New Value (output) CA10 CA11 CXRX Pin (input) CA20 TABLE 23-37: CAN MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. CA10 TioF Port Output Fall Time — — — ns See parameter DO32 CA11 TioR Port Output Rise Time — — — ns See parameter DO31 CA20 Tcwf Pulse Width to Trigger 500 — — ns CAN Wake-up Filter Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2011 Microchip Technology Inc. DS70143E-page 207

dsPIC30F6011A/6012A/6013A/6014A TABLE 23-38: 12-BIT ADC MODULE SPECIFICATIONS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of — Lesser of V VDD - 0.3 VDD + 0.3 or 2.7 or 5.5 AD02 AVSS Module VSS Supply VSS - 0.3 — VSS + 0.3 V Reference Inputs AD05 VREFH Reference Voltage High AVSS + 2.7 — AVDD V AD06 VREFL Reference Voltage Low AVSS — AVDD - 2.7 V AD07 VREF Absolute Reference AVSS - 0.3 — AVDD + 0.3 V Voltage AD08 IREF Current Drain — 150 200 μA operating .001 1 μA off Analog Input AD10 VINH-VINL Full-Scale Input Span VREFL — VREFH V See Note AD11 VIN Absolute Input Voltage AVSS - 0.3 — AVDD + 0.3 V AD12 — Leakage Current — ±0.001 ±0.610 μA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V Source Impedance = 2.5 KΩ AD13 — Leakage Current — ±0.001 ±0.610 μA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Source Impedance = 2.5 KΩ AD15 RSS Switch Resistance — 3.2K — Ω AD16 CSAMPLE Sample Capacitor — 18 pF AD17 RIN Recommended Impedance — — 2.5K Ω of Analog Voltage Source DC Accuracy AD20 Nr Resolution 12 data bits bits AD21 INL Integral Nonlinearity(3) — — <±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD21A INL Integral Nonlinearity(3) — — <±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD22 DNL Differential Nonlinearity(3) — — <±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD22A DNL Differential Nonlinearity(3) — — <±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD23 GERR Gain Error(3) +1.25 +1.5 +3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V Note 1: The ADC conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: Parameters are characterized but not tested. Use as design guidance only. 3: Measurements taken with external VREF+ and VREF- used as the ADC voltage references. DS70143E-page 208 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A TABLE 23-38: 12-BIT ADC MODULE SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. AD23A GERR Gain Error(3) +1.25 +1.5 +3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD24 EOFF Offset Error -2 -1.5 -1.25 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD24A EOFF Offset Error -2 -1.5 -1.25 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD25 — Monotonicity(1) — — — — Guaranteed Dynamic Performance AD30 THD Total Harmonic Distortion — -71 — dB See Note 2 AD31 SINAD Signal to Noise and — 68 — dB See Note 2 Distortion AD32 SFDR Spurious Free Dynamic — 83 — dB See Note 2 Range AD33 FNYQ Input Signal Bandwidth — — 100 kHz AD34 ENOB Effective Number of Bits 10.95 11.1 — bits Note 1: The ADC conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: Parameters are characterized but not tested. Use as design guidance only. 3: Measurements taken with external VREF+ and VREF- used as the ADC voltage references. © 2011 Microchip Technology Inc. DS70143E-page 209

dsPIC30F6011A/6012A/6013A/6014A FIGURE 23-23: 12-BIT ADC TIMING CHARACTERISTICS (ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 TSAMP AD55 DONE ADIF ADRES(0) 1 2 3 4 5 6 7 8 9 1 – Software sets ADCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 18. “12-bit A/D Converter” (DS70046) of the ”dsPIC30F Family Reference Manual”. 3 – Software clears ADCON. SAMP to start conversion. 4 – Sampling ends, conversion sequence starts. 5 – Convert bit 11. 6 – Convert bit 10. 7 – Convert bit 1. 8 – Convert bit 0. 9 – One TAD for end of conversion. DS70143E-page 210 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A TABLE 23-39: 12-BIT ADC TIMING REQUIREMENTS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Clock Parameters AD50 TAD ADC Clock Period — 334 — ns VDD = 3-5.5V (Note 1) AD51 tRC ADC Internal RC Oscillator Period 1.2 1.5 1.8 μs Conversion Rate AD55 tCONV Conversion Time — 14 TAD ns AD56 FCNV Throughput Rate — 200 — ksps VDD = VREF = 3-5.5V AD57 TSAMP Sample Time — 1 TAD — ns VDD = 3-5.5V Source resistance Rs = 0-2.5 kΩ Timing Parameters AD60 tPCS Conversion Start from Sample — 1 TAD — ns Trigger AD61 tPSS Sample Start from Setting 0.5 TAD — 1.5 ns Sample (SAMP) Bit TAD AD62 tCSS Conversion Completion to — 0.5 TAD — ns Sample Start (ASAM = 1) AD63 tDPU(2) Time to Stabilize Analog Stage — — 20 μs from ADC Off to ADC On Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 2: tDPU is the time required for the ADC module to stabilize when it is turned on (ADCON1<ADON> = 1). During this time the ADC result is indeterminate. © 2011 Microchip Technology Inc. DS70143E-page 211

dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 212 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A 24.0 PACKAGING INFORMATION 24.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXXXX dsPIC30F6011A XXXXXXXXXXXX -30I/PF e3 YYWWNNN 0512XXX 80-Lead TQFP Example XXXXXXXXXXXX dsPIC30F6014A XXXXXXXXXXXX -30I/PF e3 YYWWNNN 0512XXX Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011 Microchip Technology Inc. DS70143E-page 213

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(cid:15)(cid:16)? ’(cid:31)(cid:13)(cid:6)(cid:12)( (cid:15)(cid:31) (cid:21)(cid:27)(cid:14)(cid:15)(cid:14)!(cid:21)"#(cid:11)(cid:28)(cid:14)(cid:21)(cid:27)$(cid:13)%(cid:14)&(cid:13)(cid:11)’#(cid:23)(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29))(cid:14)*#’(cid:14)(#"’(cid:14)*(cid:13)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)+(cid:21)’(cid:25)(cid:21)(cid:27)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:25)(cid:11)’(cid:22)(cid:25)(cid:13)$(cid:14)(cid:11)(cid:23)(cid:13)(cid:11)(cid:31) (cid:18)(cid:31) ,(cid:25)(cid:11)(&(cid:13)(cid:23)"(cid:14)(cid:11)’(cid:14)(cid:22)(cid:24)(cid:23)(cid:27)(cid:13)(cid:23)"(cid:14)(cid:11)(cid:23)(cid:13)(cid:14)(cid:24)(cid:10)’(cid:21)(cid:24)(cid:27)(cid:11)(cid:28)-(cid:14)"(cid:21).(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29)(cid:31) (cid:16)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)"(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:27)$(cid:14)/(cid:15)(cid:14)$(cid:24)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:21)(cid:27)(cid:22)(cid:28)#$(cid:13)(cid:14)((cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:31)(cid:14)(cid:20)(cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:14)"(cid:25)(cid:11)(cid:28)(cid:28)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:13)%(cid:22)(cid:13)(cid:13)$(cid:14)(cid:4)(cid:31)(cid:18)0(cid:14)(((cid:14)(cid:10)(cid:13)(cid:23)(cid:14)"(cid:21)$(cid:13)(cid:31) (cid:5)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:21)(cid:27)(cid:12)(cid:14)(cid:11)(cid:27)$(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:21)(cid:27)(cid:12)(cid:14)(cid:10)(cid:13)(cid:23)(cid:14)(cid:7)(cid:3)(cid:20)/(cid:14)1(cid:15)(cid:5)(cid:31)0(cid:20)(cid:31) 2(cid:3),3 2(cid:11)"(cid:21)(cid:22)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:31)(cid:14)(cid:26)(cid:25)(cid:13)(cid:24)(cid:23)(cid:13)’(cid:21)(cid:22)(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)(cid:13)%(cid:11)(cid:22)’(cid:14)!(cid:11)(cid:28)#(cid:13)(cid:14)"(cid:25)(cid:24)+(cid:27)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13)"(cid:31) (cid:8)/43 (cid:8)(cid:13)&(cid:13)(cid:23)(cid:13)(cid:27)(cid:22)(cid:13)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27))(cid:14)#"#(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13))(cid:14)&(cid:24)(cid:23)(cid:14)(cid:21)(cid:27)&(cid:24)(cid:23)((cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:10)#(cid:23)(cid:10)(cid:24)"(cid:13)"(cid:14)(cid:24)(cid:27)(cid:28)(cid:29)(cid:31) (cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:26)(cid:13)(cid:22)(cid:25)(cid:27)(cid:24)(cid:28)(cid:24)(cid:12)(cid:29)(cid:2)(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12),(cid:4)(cid:5)(cid:9)(cid:4)(cid:17)(cid:17)2 DS70143E-page 214 © 2011 Microchip Technology Inc.

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dsPIC30F6011A/6012A/6013A/6014A (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)$(cid:28)(cid:27)$(cid:28)(cid:27)(cid:9)(cid:29)(cid:29)(cid:9)(cid:30)(cid:31)(cid:8) !(cid:9)"#$$(cid:9)(cid:29)(cid:29)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’(cid:31)(cid:13)(cid:6)( 4(cid:24)(cid:23)(cid:14)’(cid:25)(cid:13)(cid:14)((cid:24)"’(cid:14)(cid:22)#(cid:23)(cid:23)(cid:13)(cid:27)’(cid:14)(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)$(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12)")(cid:14)(cid:10)(cid:28)(cid:13)(cid:11)"(cid:13)(cid:14)"(cid:13)(cid:13)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:22)(cid:21)&(cid:21)(cid:22)(cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)(cid:11)’(cid:14) (cid:25)’’(cid:10)366+++(cid:31)((cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:31)(cid:22)(cid:24)(6(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12) D D1 E e E1 N b NOTE1 123 NOTE2 α A c φ A2 β A1 L L1 7(cid:27)(cid:21)’" (cid:20)(cid:30)88(cid:30)(cid:20)/(cid:26)/(cid:8)(cid:3) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:14)8(cid:21)((cid:21)’" (cid:20)(cid:30)9 9:(cid:20) (cid:20)(cid:7); 9#(*(cid:13)(cid:23)(cid:14)(cid:24)&(cid:14)8(cid:13)(cid:11)$" 9 (cid:17)(cid:5) 8(cid:13)(cid:11)$(cid:14) (cid:21)’(cid:22)(cid:25) (cid:13) (cid:4)(cid:31)0(cid:4)(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)=(cid:13)(cid:21)(cid:12)(cid:25)’ (cid:7) > > (cid:15)(cid:31)(cid:18)(cid:4) (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:7)(cid:18) (cid:4)(cid:31)(cid:6)0 (cid:15)(cid:31)(cid:4)(cid:4) (cid:15)(cid:31)(cid:4)0 (cid:3)’(cid:11)(cid:27)$(cid:24)&&(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:31)(cid:4)0 > (cid:4)(cid:31)(cid:15)0 4(cid:24)(cid:24)’(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) 8 (cid:4)(cid:31)(cid:5)0 (cid:4)(cid:31)(cid:17)(cid:4) (cid:4)(cid:31)(cid:19)0 4(cid:24)(cid:24)’(cid:10)(cid:23)(cid:21)(cid:27)’ 8(cid:15) (cid:15)(cid:31)(cid:4)(cid:4)(cid:14)(cid:8)/4 4(cid:24)(cid:24)’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13) (cid:3) (cid:4)? (cid:16)(cid:31)0? (cid:19)? :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)@(cid:21)$’(cid:25) / (cid:15)(cid:18)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2) (cid:15)(cid:18)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)@(cid:21)$’(cid:25) /(cid:15) (cid:15)(cid:4)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2)(cid:15) (cid:15)(cid:4)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), 8(cid:13)(cid:11)$(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:22) (cid:4)(cid:31)(cid:4)(cid:6) > (cid:4)(cid:31)(cid:18)(cid:4) 8(cid:13)(cid:11)$(cid:14)@(cid:21)$’(cid:25) * (cid:4)(cid:31)(cid:15)(cid:19) (cid:4)(cid:31)(cid:18)(cid:18) (cid:4)(cid:31)(cid:18)(cid:19) (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)(cid:26)(cid:24)(cid:10) (cid:4) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)2(cid:24)’’(cid:24)( (cid:5) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? ’(cid:31)(cid:13)(cid:6)(cid:12)( (cid:15)(cid:31) (cid:21)(cid:27)(cid:14)(cid:15)(cid:14)!(cid:21)"#(cid:11)(cid:28)(cid:14)(cid:21)(cid:27)$(cid:13)%(cid:14)&(cid:13)(cid:11)’#(cid:23)(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29))(cid:14)*#’(cid:14)(#"’(cid:14)*(cid:13)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)+(cid:21)’(cid:25)(cid:21)(cid:27)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:25)(cid:11)’(cid:22)(cid:25)(cid:13)$(cid:14)(cid:11)(cid:23)(cid:13)(cid:11)(cid:31) (cid:18)(cid:31) ,(cid:25)(cid:11)(&(cid:13)(cid:23)"(cid:14)(cid:11)’(cid:14)(cid:22)(cid:24)(cid:23)(cid:27)(cid:13)(cid:23)"(cid:14)(cid:11)(cid:23)(cid:13)(cid:14)(cid:24)(cid:10)’(cid:21)(cid:24)(cid:27)(cid:11)(cid:28)-(cid:14)"(cid:21).(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29)(cid:31) (cid:16)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)"(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:27)$(cid:14)/(cid:15)(cid:14)$(cid:24)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:21)(cid:27)(cid:22)(cid:28)#$(cid:13)(cid:14)((cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:31)(cid:14)(cid:20)(cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:14)"(cid:25)(cid:11)(cid:28)(cid:28)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:13)%(cid:22)(cid:13)(cid:13)$(cid:14)(cid:4)(cid:31)(cid:18)0(cid:14)(((cid:14)(cid:10)(cid:13)(cid:23)(cid:14)"(cid:21)$(cid:13)(cid:31) (cid:5)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:21)(cid:27)(cid:12)(cid:14)(cid:11)(cid:27)$(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:21)(cid:27)(cid:12)(cid:14)(cid:10)(cid:13)(cid:23)(cid:14)(cid:7)(cid:3)(cid:20)/(cid:14)1(cid:15)(cid:5)(cid:31)0(cid:20)(cid:31) 2(cid:3),3 2(cid:11)"(cid:21)(cid:22)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:31)(cid:14)(cid:26)(cid:25)(cid:13)(cid:24)(cid:23)(cid:13)’(cid:21)(cid:22)(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)(cid:13)%(cid:11)(cid:22)’(cid:14)!(cid:11)(cid:28)#(cid:13)(cid:14)"(cid:25)(cid:24)+(cid:27)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13)"(cid:31) (cid:8)/43 (cid:8)(cid:13)&(cid:13)(cid:23)(cid:13)(cid:27)(cid:22)(cid:13)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27))(cid:14)#"#(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13))(cid:14)&(cid:24)(cid:23)(cid:14)(cid:21)(cid:27)&(cid:24)(cid:23)((cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:10)#(cid:23)(cid:10)(cid:24)"(cid:13)"(cid:14)(cid:24)(cid:27)(cid:28)(cid:29)(cid:31) (cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:26)(cid:13)(cid:22)(cid:25)(cid:27)(cid:24)(cid:28)(cid:24)(cid:12)(cid:29)(cid:2)(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12),(cid:4)(cid:5)(cid:9)(cid:4)<02 DS70143E-page 216 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)$(cid:28)(cid:27)$(cid:28)(cid:27)(cid:9)(cid:29)(cid:29)(cid:9)(cid:30)(cid:31)(cid:8) !(cid:9)"#$$(cid:9)(cid:29)(cid:29)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’(cid:31)(cid:13)(cid:6)( 4(cid:24)(cid:23)(cid:14)’(cid:25)(cid:13)(cid:14)((cid:24)"’(cid:14)(cid:22)#(cid:23)(cid:23)(cid:13)(cid:27)’(cid:14)(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)$(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12)")(cid:14)(cid:10)(cid:28)(cid:13)(cid:11)"(cid:13)(cid:14)"(cid:13)(cid:13)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:22)(cid:21)&(cid:21)(cid:22)(cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)(cid:11)’(cid:14) (cid:25)’’(cid:10)366+++(cid:31)((cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:31)(cid:22)(cid:24)(6(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12) © 2011 Microchip Technology Inc. DS70143E-page 217

dsPIC30F6011A/6012A/6013A/6014A )$(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:21)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:3)(cid:28)(cid:27)(cid:3)(cid:28)(cid:27)(cid:9)(cid:29)(cid:29)(cid:9)(cid:30)(cid:31)(cid:8) !(cid:9)"#$$(cid:9)(cid:29)(cid:29)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’(cid:31)(cid:13)(cid:6)( 4(cid:24)(cid:23)(cid:14)’(cid:25)(cid:13)(cid:14)((cid:24)"’(cid:14)(cid:22)#(cid:23)(cid:23)(cid:13)(cid:27)’(cid:14)(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)$(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12)")(cid:14)(cid:10)(cid:28)(cid:13)(cid:11)"(cid:13)(cid:14)"(cid:13)(cid:13)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:22)(cid:21)&(cid:21)(cid:22)(cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)(cid:11)’(cid:14) (cid:25)’’(cid:10)366+++(cid:31)((cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:31)(cid:22)(cid:24)(6(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12) D D1 e E E1 b N NOTE1 123 NOTE2 α c φ A β L A1 L1 A2 7(cid:27)(cid:21)’" (cid:20)(cid:30)88(cid:30)(cid:20)/(cid:26)/(cid:8)(cid:3) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:14)8(cid:21)((cid:21)’" (cid:20)(cid:30)9 9:(cid:20) (cid:20)(cid:7); 9#(*(cid:13)(cid:23)(cid:14)(cid:24)&(cid:14)8(cid:13)(cid:11)$" 9 <(cid:4) 8(cid:13)(cid:11)$(cid:14) (cid:21)’(cid:22)(cid:25) (cid:13) (cid:4)(cid:31)(cid:17)0(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)=(cid:13)(cid:21)(cid:12)(cid:25)’ (cid:7) > > (cid:15)(cid:31)(cid:18)(cid:4) (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:7)(cid:18) (cid:4)(cid:31)(cid:6)0 (cid:15)(cid:31)(cid:4)(cid:4) (cid:15)(cid:31)(cid:4)0 (cid:3)’(cid:11)(cid:27)$(cid:24)&&(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:31)(cid:4)0 > (cid:4)(cid:31)(cid:15)0 4(cid:24)(cid:24)’(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) 8 (cid:4)(cid:31)(cid:5)0 (cid:4)(cid:31)(cid:17)(cid:4) (cid:4)(cid:31)(cid:19)0 4(cid:24)(cid:24)’(cid:10)(cid:23)(cid:21)(cid:27)’ 8(cid:15) (cid:15)(cid:31)(cid:4)(cid:4)(cid:14)(cid:8)/4 4(cid:24)(cid:24)’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13) (cid:3) (cid:4)? (cid:16)(cid:31)0? (cid:19)? :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)@(cid:21)$’(cid:25) / (cid:15)(cid:17)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2) (cid:15)(cid:17)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)@(cid:21)$’(cid:25) /(cid:15) (cid:15)(cid:5)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2)(cid:15) (cid:15)(cid:5)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), 8(cid:13)(cid:11)$(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:22) (cid:4)(cid:31)(cid:4)(cid:6) > (cid:4)(cid:31)(cid:18)(cid:4) 8(cid:13)(cid:11)$(cid:14)@(cid:21)$’(cid:25) * (cid:4)(cid:31)(cid:18)(cid:18) (cid:4)(cid:31)(cid:16)(cid:18) (cid:4)(cid:31)(cid:16)< (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)(cid:26)(cid:24)(cid:10) (cid:4) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)2(cid:24)’’(cid:24)( (cid:5) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? ’(cid:31)(cid:13)(cid:6)(cid:12)( (cid:15)(cid:31) (cid:21)(cid:27)(cid:14)(cid:15)(cid:14)!(cid:21)"#(cid:11)(cid:28)(cid:14)(cid:21)(cid:27)$(cid:13)%(cid:14)&(cid:13)(cid:11)’#(cid:23)(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29))(cid:14)*#’(cid:14)(#"’(cid:14)*(cid:13)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)+(cid:21)’(cid:25)(cid:21)(cid:27)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:25)(cid:11)’(cid:22)(cid:25)(cid:13)$(cid:14)(cid:11)(cid:23)(cid:13)(cid:11)(cid:31) (cid:18)(cid:31) ,(cid:25)(cid:11)(&(cid:13)(cid:23)"(cid:14)(cid:11)’(cid:14)(cid:22)(cid:24)(cid:23)(cid:27)(cid:13)(cid:23)"(cid:14)(cid:11)(cid:23)(cid:13)(cid:14)(cid:24)(cid:10)’(cid:21)(cid:24)(cid:27)(cid:11)(cid:28)-(cid:14)"(cid:21).(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29)(cid:31) (cid:16)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)"(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:27)$(cid:14)/(cid:15)(cid:14)$(cid:24)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:21)(cid:27)(cid:22)(cid:28)#$(cid:13)(cid:14)((cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:31)(cid:14)(cid:20)(cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:14)"(cid:25)(cid:11)(cid:28)(cid:28)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:13)%(cid:22)(cid:13)(cid:13)$(cid:14)(cid:4)(cid:31)(cid:18)0(cid:14)(((cid:14)(cid:10)(cid:13)(cid:23)(cid:14)"(cid:21)$(cid:13)(cid:31) (cid:5)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:21)(cid:27)(cid:12)(cid:14)(cid:11)(cid:27)$(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:21)(cid:27)(cid:12)(cid:14)(cid:10)(cid:13)(cid:23)(cid:14)(cid:7)(cid:3)(cid:20)/(cid:14)1(cid:15)(cid:5)(cid:31)0(cid:20)(cid:31) 2(cid:3),3 2(cid:11)"(cid:21)(cid:22)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:31)(cid:14)(cid:26)(cid:25)(cid:13)(cid:24)(cid:23)(cid:13)’(cid:21)(cid:22)(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)(cid:13)%(cid:11)(cid:22)’(cid:14)!(cid:11)(cid:28)#(cid:13)(cid:14)"(cid:25)(cid:24)+(cid:27)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13)"(cid:31) (cid:8)/43 (cid:8)(cid:13)&(cid:13)(cid:23)(cid:13)(cid:27)(cid:22)(cid:13)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27))(cid:14)#"#(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13))(cid:14)&(cid:24)(cid:23)(cid:14)(cid:21)(cid:27)&(cid:24)(cid:23)((cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:10)#(cid:23)(cid:10)(cid:24)"(cid:13)"(cid:14)(cid:24)(cid:27)(cid:28)(cid:29)(cid:31) (cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:26)(cid:13)(cid:22)(cid:25)(cid:27)(cid:24)(cid:28)(cid:24)(cid:12)(cid:29)(cid:2)(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12),(cid:4)(cid:5)(cid:9)(cid:15)(cid:15)(cid:17)2 DS70143E-page 218 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A )0(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:21)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)(cid:3)(cid:28)(cid:27)(cid:3)(cid:28)(cid:27)(cid:9)(cid:29)(cid:29)(cid:9)(cid:30)(cid:31)(cid:8) !(cid:9)"#$$(cid:9)(cid:29)(cid:29)(cid:9)(cid:21)(cid:31)(cid:31)(cid:13)(cid:22)*(cid:14)(cid:18)(cid:13)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’(cid:31)(cid:13)(cid:6)( 4(cid:24)(cid:23)(cid:14)’(cid:25)(cid:13)(cid:14)((cid:24)"’(cid:14)(cid:22)#(cid:23)(cid:23)(cid:13)(cid:27)’(cid:14)(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)$(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12)")(cid:14)(cid:10)(cid:28)(cid:13)(cid:11)"(cid:13)(cid:14)"(cid:13)(cid:13)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:22)(cid:21)&(cid:21)(cid:22)(cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)(cid:11)’(cid:14) (cid:25)’’(cid:10)366+++(cid:31)((cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:31)(cid:22)(cid:24)(6(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12) © 2011 Microchip Technology Inc. DS70143E-page 219

dsPIC30F6011A/6012A/6013A/6014A )$(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)"(cid:28)(cid:27)"(cid:28)(cid:27)(cid:9)(cid:29)(cid:29)(cid:9)(cid:30)(cid:31)(cid:8) !(cid:9)"#$$(cid:9)(cid:29)(cid:29)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’(cid:31)(cid:13)(cid:6)( 4(cid:24)(cid:23)(cid:14)’(cid:25)(cid:13)(cid:14)((cid:24)"’(cid:14)(cid:22)#(cid:23)(cid:23)(cid:13)(cid:27)’(cid:14)(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)$(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12)")(cid:14)(cid:10)(cid:28)(cid:13)(cid:11)"(cid:13)(cid:14)"(cid:13)(cid:13)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:22)(cid:21)&(cid:21)(cid:22)(cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)(cid:11)’(cid:14) (cid:25)’’(cid:10)366+++(cid:31)((cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:31)(cid:22)(cid:24)(6(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12) D D1 E e E1 b N NOTE1 123 NOTE2 α A c φ β A1 A2 L L1 7(cid:27)(cid:21)’" (cid:20)(cid:30)88(cid:30)(cid:20)/(cid:26)/(cid:8)(cid:3) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:14)8(cid:21)((cid:21)’" (cid:20)(cid:30)9 9:(cid:20) (cid:20)(cid:7); 9#(*(cid:13)(cid:23)(cid:14)(cid:24)&(cid:14)8(cid:13)(cid:11)$" 9 <(cid:4) 8(cid:13)(cid:11)$(cid:14) (cid:21)’(cid:22)(cid:25) (cid:13) (cid:4)(cid:31)0(cid:4)(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)=(cid:13)(cid:21)(cid:12)(cid:25)’ (cid:7) > > (cid:15)(cid:31)(cid:18)(cid:4) (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:7)(cid:18) (cid:4)(cid:31)(cid:6)0 (cid:15)(cid:31)(cid:4)(cid:4) (cid:15)(cid:31)(cid:4)0 (cid:3)’(cid:11)(cid:27)$(cid:24)&&(cid:14)(cid:14) (cid:7)(cid:15) (cid:4)(cid:31)(cid:4)0 > (cid:4)(cid:31)(cid:15)0 4(cid:24)(cid:24)’(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) 8 (cid:4)(cid:31)(cid:5)0 (cid:4)(cid:31)(cid:17)(cid:4) (cid:4)(cid:31)(cid:19)0 4(cid:24)(cid:24)’(cid:10)(cid:23)(cid:21)(cid:27)’ 8(cid:15) (cid:15)(cid:31)(cid:4)(cid:4)(cid:14)(cid:8)/4 4(cid:24)(cid:24)’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13) (cid:3) (cid:4)? (cid:16)(cid:31)0? (cid:19)? :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)@(cid:21)$’(cid:25) / (cid:15)(cid:5)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), :!(cid:13)(cid:23)(cid:11)(cid:28)(cid:28)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2) (cid:15)(cid:5)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)@(cid:21)$’(cid:25) /(cid:15) (cid:15)(cid:18)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), (cid:20)(cid:24)(cid:28)$(cid:13)$(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)8(cid:13)(cid:27)(cid:12)’(cid:25) (cid:2)(cid:15) (cid:15)(cid:18)(cid:31)(cid:4)(cid:4)(cid:14)2(cid:3), 8(cid:13)(cid:11)$(cid:14)(cid:26)(cid:25)(cid:21)(cid:22)5(cid:27)(cid:13)"" (cid:22) (cid:4)(cid:31)(cid:4)(cid:6) > (cid:4)(cid:31)(cid:18)(cid:4) 8(cid:13)(cid:11)$(cid:14)@(cid:21)$’(cid:25) * (cid:4)(cid:31)(cid:15)(cid:19) (cid:4)(cid:31)(cid:18)(cid:18) (cid:4)(cid:31)(cid:18)(cid:19) (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)(cid:26)(cid:24)(cid:10) (cid:4) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? (cid:20)(cid:24)(cid:28)$(cid:14)(cid:2)(cid:23)(cid:11)&’(cid:14)(cid:7)(cid:27)(cid:12)(cid:28)(cid:13)(cid:14)2(cid:24)’’(cid:24)( (cid:5) (cid:15)(cid:15)? (cid:15)(cid:18)? (cid:15)(cid:16)? ’(cid:31)(cid:13)(cid:6)(cid:12)( (cid:15)(cid:31) (cid:21)(cid:27)(cid:14)(cid:15)(cid:14)!(cid:21)"#(cid:11)(cid:28)(cid:14)(cid:21)(cid:27)$(cid:13)%(cid:14)&(cid:13)(cid:11)’#(cid:23)(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29))(cid:14)*#’(cid:14)(#"’(cid:14)*(cid:13)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)+(cid:21)’(cid:25)(cid:21)(cid:27)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:25)(cid:11)’(cid:22)(cid:25)(cid:13)$(cid:14)(cid:11)(cid:23)(cid:13)(cid:11)(cid:31) (cid:18)(cid:31) ,(cid:25)(cid:11)(&(cid:13)(cid:23)"(cid:14)(cid:11)’(cid:14)(cid:22)(cid:24)(cid:23)(cid:27)(cid:13)(cid:23)"(cid:14)(cid:11)(cid:23)(cid:13)(cid:14)(cid:24)(cid:10)’(cid:21)(cid:24)(cid:27)(cid:11)(cid:28)-(cid:14)"(cid:21).(cid:13)(cid:14)((cid:11)(cid:29)(cid:14)!(cid:11)(cid:23)(cid:29)(cid:31) (cid:16)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)"(cid:14)(cid:2)(cid:15)(cid:14)(cid:11)(cid:27)$(cid:14)/(cid:15)(cid:14)$(cid:24)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:21)(cid:27)(cid:22)(cid:28)#$(cid:13)(cid:14)((cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:31)(cid:14)(cid:20)(cid:24)(cid:28)$(cid:14)&(cid:28)(cid:11)"(cid:25)(cid:14)(cid:24)(cid:23)(cid:14)(cid:10)(cid:23)(cid:24)’(cid:23)#"(cid:21)(cid:24)(cid:27)"(cid:14)"(cid:25)(cid:11)(cid:28)(cid:28)(cid:14)(cid:27)(cid:24)’(cid:14)(cid:13)%(cid:22)(cid:13)(cid:13)$(cid:14)(cid:4)(cid:31)(cid:18)0(cid:14)(((cid:14)(cid:10)(cid:13)(cid:23)(cid:14)"(cid:21)$(cid:13)(cid:31) (cid:5)(cid:31) (cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:21)(cid:27)(cid:12)(cid:14)(cid:11)(cid:27)$(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:21)(cid:27)(cid:12)(cid:14)(cid:10)(cid:13)(cid:23)(cid:14)(cid:7)(cid:3)(cid:20)/(cid:14)1(cid:15)(cid:5)(cid:31)0(cid:20)(cid:31) 2(cid:3),3 2(cid:11)"(cid:21)(cid:22)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27)(cid:31)(cid:14)(cid:26)(cid:25)(cid:13)(cid:24)(cid:23)(cid:13)’(cid:21)(cid:22)(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)(cid:13)%(cid:11)(cid:22)’(cid:14)!(cid:11)(cid:28)#(cid:13)(cid:14)"(cid:25)(cid:24)+(cid:27)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13)"(cid:31) (cid:8)/43 (cid:8)(cid:13)&(cid:13)(cid:23)(cid:13)(cid:27)(cid:22)(cid:13)(cid:14)(cid:2)(cid:21)((cid:13)(cid:27)"(cid:21)(cid:24)(cid:27))(cid:14)#"#(cid:11)(cid:28)(cid:28)(cid:29)(cid:14)+(cid:21)’(cid:25)(cid:24)#’(cid:14)’(cid:24)(cid:28)(cid:13)(cid:23)(cid:11)(cid:27)(cid:22)(cid:13))(cid:14)&(cid:24)(cid:23)(cid:14)(cid:21)(cid:27)&(cid:24)(cid:23)((cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:10)#(cid:23)(cid:10)(cid:24)"(cid:13)"(cid:14)(cid:24)(cid:27)(cid:28)(cid:29)(cid:31) (cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:26)(cid:13)(cid:22)(cid:25)(cid:27)(cid:24)(cid:28)(cid:24)(cid:12)(cid:29)(cid:2)(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12),(cid:4)(cid:5)(cid:9)(cid:4)(cid:6)(cid:18)2 DS70143E-page 220 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A )$(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:14)(cid:18)(cid:9)(cid:19)(cid:20)(cid:7)(cid:8)(cid:9)(cid:21)(cid:11)(cid:7)(cid:13)(cid:22)(cid:7)(cid:15)(cid:23)(cid:9)(cid:24)(cid:10)(cid:16)(cid:25)(cid:9)(cid:26)(cid:9)(cid:27)"(cid:28)(cid:27)"(cid:28)(cid:27)(cid:9)(cid:29)(cid:29)(cid:9)(cid:30)(cid:31)(cid:8) !(cid:9)"#$$(cid:9)(cid:29)(cid:29)(cid:9)%(cid:16)(cid:19)(cid:21)(cid:10)& ’(cid:31)(cid:13)(cid:6)( 4(cid:24)(cid:23)(cid:14)’(cid:25)(cid:13)(cid:14)((cid:24)"’(cid:14)(cid:22)#(cid:23)(cid:23)(cid:13)(cid:27)’(cid:14)(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:13)(cid:14)$(cid:23)(cid:11)+(cid:21)(cid:27)(cid:12)")(cid:14)(cid:10)(cid:28)(cid:13)(cid:11)"(cid:13)(cid:14)"(cid:13)(cid:13)(cid:14)’(cid:25)(cid:13)(cid:14)(cid:20)(cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:14) (cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:22)(cid:21)&(cid:21)(cid:22)(cid:11)’(cid:21)(cid:24)(cid:27)(cid:14)(cid:28)(cid:24)(cid:22)(cid:11)’(cid:13)$(cid:14)(cid:11)’(cid:14) (cid:25)’’(cid:10)366+++(cid:31)((cid:21)(cid:22)(cid:23)(cid:24)(cid:22)(cid:25)(cid:21)(cid:10)(cid:31)(cid:22)(cid:24)(6(cid:10)(cid:11)(cid:22)5(cid:11)(cid:12)(cid:21)(cid:27)(cid:12) © 2011 Microchip Technology Inc. DS70143E-page 221

dsPIC30F6011A/6012A/6013A/6014A NOTES: DS70143E-page 222 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A APPENDIX A: REVISION HISTORY Revision D (March 2008) This revision reflects these updates: Revision A (January 2005) • Added FUSE Configuration Register (FICD) Original data sheet for dsPIC30F6011A, 6012A, 6013A details (see Section20.8 “Device Configuration and 6014A devices. Registers” and Table20-8) • Removed erroneous statement regarding genera- Revision B (September 2005) tion of CAN receive errors (see Section17.4.5 “Receive Errors”) Revision B of this data sheet reflects these changes: • Electrical Specifications: • 12-Bit ADC allows up to 200 ksps sampling rate - Resolved TBD values for parameters DO10, (see Section19.6 “Selecting the ADC Conver- DO16, DO20, and DO26 (see Table23-9) sion Clock” and Section19.7 “ADC Speeds”), - 10-bit High-Speed ADC tPDU timing parame- • FRC Oscillator revised to allow tuning in ±0.75% ter (time to stabilize) has been updated from increments (see Section20.2.5 “Fast RC Oscil- 20 µs typical to 20 µs maximum (see lator (FRC)” and Table20-4). Table23-39) • Revised electrical characteristics: - Parameter OS65 (Internal RC Accuracy) has - Operating Current (IDD) (see Table23-5) been expanded to reflect multiple Min and - Idle Current (IIDLE) (see Table23-6) Max values for different temperatures (see - Power-Down Current (IPD) (seeTable23-7) Table23-19) - Brown-Out Reset (BOR) (see Table23-11) - Parameter DC12 (RAM Data Retention Volt- age) has been updated to include a Min value - External Clock Timing Requirements (see (see Table23-4) Table23-14) - Parameter D134 (Erase/Write Cycle Time) - PLL Clock Timing Specification (VDD = 2.5- has been updated to include Min and Max 5.5 V) (see Table23-15) values and the Typ value has been removed - PLL Jitter (seeTable23-16) (see Table23-12) - Internal FRC Jitter Accuracy and Drift (see - Removed parameters OS62 (Internal FRC Table23-18) Jitter) and OS64 (Internal FRC Drift) and - 12-Bit ADC Module Specifications (see Note 2 from AC Characteristics (see Table23-38) Table23-18) - 12-Bit ADC Conversion Timing Requirements - Parameter OS63 (Internal FRC Accuracy) (see Table23-39) has been expanded to reflect multiple Min and Max values for different temperatures Revision C (October 2006) (see Table23-18) - Updated I/O Pin characteristics parameters Revision C of this data sheet reflects these changes: DI19 and DI29 (see Table23-8) • BSRAM and SSRAM SFRs added for Data RAM - Removed parameters DC27a, DC27b, protection (see Section3.2.7 “Data Ram Protec- DC47a, and DC47b (references to IDD, 20 tion Feature”) MIPs @ 3.3V) in Table23-5 and Table23-6 • Added INTTREG register (see Section5.0 - Removed parameters CS77 and CS78 “Interrupts”) (references to TFACL and TRACL @ 3.3V) in • Revised I2C Slave Addresses (see Table15-1) Table23-30 • Base Instruction CP1 removed from instruction - Updated Min and Max values and Conditions set (see Table21-2) for parameter SY11 and updated Min, Typ, • Revised electrical characteristics: and Max values and Conditions for parame- - Operating Current (IDD) (see Table23-5) ter SY20 (see Table23-21) - Idle Current (IIDLE) (see Table23-6) • Preliminary marking removed from document - Power-Down Current (IPD) (seeTable23-7) footer - I/O Pin Input Specifications (see Table23-8) • Additional minor corrections throughout the document - Brown-Out Reset (BOR) (see Table23-11) - Watchdog Timer (see Table23-21) © 2011 Microchip Technology Inc. DS70143E-page 223

dsPIC30F6011A/6012A/6013A/6014A Revision E (February 2011) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in TableA-1. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description Section20.0 “System Added a shaded note on OSCTUN functionality in Section20.2.5 “Fast RC Integration” Oscillator (FRC)”. Section23.0 “Electrical Updated the maximum MIPS for the Operating MIPS vs. Voltage VDD range of Characteristics” 3.0-3.6V for dsPIC30F601XA-20I and dsPIC30F601XA-30I devices (see Table23-1). Added Operating Current (IDD) parameters DC27a and DC27b (see Table23-5). Added Idle Current (IIDLE) parameters DC47a and DC47b (see Table23-6). Updated the maximum value for parameter DI19 and the minimum value for parameter DI29 in the I/O Pin Input Specifications (see Table23-8). Removed parameter D136 and updated the minimum, typical, maximum, and conditions for parameters D122 and D134 in the Program and EEPROM specifications (see Table23-12). DS70143E-page 224 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A INDEX 32-bit Timer2/3...........................................................72 32-bit Timer4/5...........................................................77 Numerics CAN Buffers and Protocol Engine............................112 DCI Module...............................................................124 12-bit Analog-to-Digital Converter (ADC) Module.............133 Dedicated Port Structure............................................61 A DSP Engine................................................................21 dsPIC30F6011A/6012A..............................................12 AC Characteristics............................................................183 dsPIC30F6013A/6014A..............................................13 Internal FRC Jitter, Accuracy and Drift.....................186 External Power-on Reset Circuit..............................155 Internal LPRC Accuracy............................................186 Load Conditions........................................................183 I2C..............................................................................96 AC Temperature and Voltage Specifications....................183 Input Capture Mode....................................................81 AC-Link Mode Operation..................................................130 Oscillator System......................................................145 16-bit Mode...............................................................130 Output Compare Mode...............................................85 20-bit Mode...............................................................130 Reset System...........................................................153 ADC..................................................................................133 Shared Port Structure.................................................62 Aborting a Conversion..............................................135 SPI..............................................................................92 ADCHS Register.......................................................133 SPI Master/Slave Connection.....................................92 ADCON1 Register.....................................................133 UART Receiver.........................................................104 ADCON2 Register.....................................................133 UART Transmitter.....................................................103 ADCON3 Register.....................................................133 BOR. See Brown-out Reset. ADCSSL Register.....................................................133 Brown-out Reset...............................................................143 ADPCFG Register.....................................................133 Characteristics..................................................181, 182 Configuring Analog Port Pins..............................62, 140 Timing Requirements...............................................189 Connection Considerations.......................................140 C Conversion Operation...............................................134 C Compilers Effects of a Reset......................................................139 MPLAB C18..............................................................170 Operation During CPU Idle Mode.............................139 CAN Module.....................................................................111 Operation During CPU Sleep Mode..........................139 Baud Rate Setting....................................................116 Output Formats.........................................................139 CAN1 Register Map..................................................118 Power-down Modes..................................................139 CAN2 Register Map..................................................120 Programming the Start of Conversion Trigger..........135 Frame Types............................................................111 Register Map.............................................................141 I/O Timing Characteristics........................................207 Result Buffer.............................................................134 I/O Timing Requirements..........................................207 Sampling Requirements............................................138 Message Reception..................................................114 Selecting the Conversion Clock................................135 Message Transmission.............................................115 Selecting the Conversion Sequence.........................134 Modes of Operation..................................................113 ADC Conversion Speeds..................................................136 Overview...................................................................111 Address Generator Units....................................................39 CLKOUT and I/O Timing Alternate Vector Table........................................................49 Characteristics..........................................................187 Analog-to-Digital Converter. See ADC. Requirements...........................................................187 Assembler Code Examples MPASM Assembler...................................................170 Data EEPROM Block Erase.......................................58 Automatic Clock Stretch......................................................98 Data EEPROM Block Write........................................60 During 10-bit Addressing (STREN = 1).......................98 Data EEPROM Read..................................................57 During 7-bit Addressing (STREN = 1).........................98 Data EEPROM Word Erase.......................................58 Receive Mode.............................................................98 Data EEPROM Word Write........................................59 Transmit Mode............................................................98 Erasing a Row of Program Memory...........................53 B Initiating a Programming Sequence...........................54 Loading Write Latches................................................54 Band Gap Start-up Time Code Protection................................................................143 Requirements............................................................190 Core Architecture Timing Characteristics..............................................190 Overview.....................................................................17 Barrel Shifter.......................................................................24 CPU Architecture Overview................................................17 Bit-Reversed Addressing....................................................42 Customer Change Notification Service.............................227 Example......................................................................43 Customer Notification Service..........................................227 Implementation...........................................................42 Customer Support.............................................................227 Modifier Values Table.................................................43 Sequence Table (16-Entry).........................................43 D Block Diagrams Data Accumulators and Adder/Subtractor..........................22 12-bit ADC Functional...............................................133 Data Space Write Saturation......................................24 16-bit Timer1 Module..................................................67 Overflow and Saturation.............................................22 16-bit Timer2...............................................................73 Round Logic...............................................................23 16-bit Timer3...............................................................73 Write Back..................................................................23 16-bit Timer4...............................................................78 Data Address Space...........................................................31 16-bit Timer5...............................................................78 Alignment....................................................................34 © 2011 Microchip Technology Inc. DS70143E-page 225

dsPIC30F6011A/6012A/6013A/6014A Alignment (Figure)......................................................35 AC-Link Mode...................................................197 Effect of Invalid Memory Accesses (Table).................34 Multichannel, I2S Modes...................................195 MCU and DSP (MAC Class) Instructions Example.....34 Timing Requirements Memory Map...............................................................31 AC-Link Mode...................................................197 Memory Map for dsPIC30F6011A/6013A...................32 Multichannel, I2S Modes...................................196 Memory Map for dsPIC30F6012A/6014A...................33 Transmit Slot Enable Bits.........................................128 Near Data Space........................................................35 Transmit Status Bits..................................................129 Software Stack............................................................35 Transmit/Receive Shift Register...............................123 Spaces........................................................................31 Underflow Mode Control Bit......................................130 Width...........................................................................34 Word Size Selection Bits..........................................125 Data Converter Interface (DCI) Module............................123 Development Support.......................................................169 Data EEPROM Memory......................................................57 Device Configuration Erasing........................................................................58 Register Map............................................................160 Erasing, Block.............................................................58 Device Configuration Registers........................................158 Erasing, Word.............................................................58 FBORPOR................................................................158 Protection Against Spurious Write..............................60 FBS...........................................................................158 Reading.......................................................................57 FGS..........................................................................158 Write Verify.................................................................60 FOSC........................................................................158 Writing.........................................................................59 FSS...........................................................................158 Writing, Block..............................................................60 FWDT.......................................................................158 Writing, Word..............................................................59 Device Overview.................................................................91 DC Characteristics............................................................174 Disabling the UART..........................................................105 Brown-out Reset...............................................181, 182 Divide Support....................................................................20 I/O Pin Input Specifications.......................................180 Instructions (Table).....................................................20 I/O Pin Output Specifications....................................180 DSP Engine........................................................................20 Idle Current (IIDLE)....................................................177 Multiplier.....................................................................22 Low-Voltage Detect...................................................180 Dual Output Compare Match Mode....................................86 LVDL.........................................................................181 Continuous Pulse Mode..............................................86 Operating Current (IDD).............................................176 Single Pulse Mode......................................................86 Power-Down Current (IPD)........................................178 E Program and EEPROM.............................................182 DCI Module Electrical Characteristics..................................................173 Bit Clock Generator...................................................127 AC.............................................................................183 Buffer Alignment with Data Frames..........................129 DC............................................................................174 Buffer Control............................................................123 Enabling and Setting Up UART Buffer Data Alignment...............................................123 Setting Up Data, Parity and Stop Bit Selections.......105 Buffer Length Control................................................129 Enabling the UART...........................................................105 COFS Pin..................................................................123 Equations CSCK Pin..................................................................123 ADC Conversion Clock.............................................135 CSDI Pin...................................................................123 Baud Rate.................................................................107 CSDO Mode Bit........................................................130 Bit Clock Frequency..................................................127 CSDO Pin.................................................................123 COFSG Period..........................................................125 Data Justification Control Bit.....................................128 Serial Clock Rate......................................................100 Device Frequencies for Common Codec CSCK Frequen- Time Quantum for Clock Generation........................117 cies (Table).......................................................127 Errata....................................................................................9 Digital Loopback Mode.............................................130 External Clock Timing Characteristics Enable.......................................................................125 Type A, B and C Timer.............................................191 Frame Sync Generator.............................................125 External Clock Timing Requirements...............................184 Frame Sync Mode Control Bits.................................125 Type A Timer............................................................191 I/O Pins.....................................................................123 Type B Timer............................................................192 Interrupts...................................................................130 Type C Timer............................................................192 Introduction...............................................................123 External Interrupt Requests................................................49 Master Frame Sync Operation..................................125 F Operation..................................................................125 Operation During CPU Idle Mode.............................130 Fast Context Saving...........................................................49 Operation During CPU Sleep Mode..........................130 Flash Program Memory......................................................51 Receive Slot Enable Bits...........................................128 Control Registers........................................................52 Receive Status Bits...................................................129 NVMADR............................................................52 Register Map.............................................................132 NVMADRU.........................................................52 Sample Clock Edge Control Bit.................................128 NVMCON............................................................52 Slave Frame Sync Operation....................................126 NVMKEY............................................................52 Slot Enable Bits Operation with Frame Sync............128 I Slot Status Bits..........................................................130 Synchronous Data Transfers....................................128 I/O Pin Specifications Timing Characteristics Input..........................................................................180 Output.......................................................................180 DS70143E-page 226 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A I/O Ports..............................................................................61 Move and Accumulator Instructions...........................40 Parallel (PIO)..............................................................61 Other Instructions.......................................................40 I2C 10-bit Slave Mode Operation........................................97 Instruction Set Reception....................................................................98 Overview...................................................................164 Transmission...............................................................98 Summary..................................................................161 I2C 7-bit Slave Mode Operation..........................................97 Internet Address...............................................................227 Reception....................................................................97 Interrupt Controller Transmission...............................................................97 Register Map..............................................................50 I2C Master Mode Operation................................................99 Interrupt Priority..................................................................46 Baud Rate Generator................................................100 Interrupt Sequence.............................................................48 Clock Arbitration........................................................100 Interrupt Stack Frame.................................................49 Multi-Master Communication, Bus Collision and Bus Ar- Interrupts............................................................................45 bitration.............................................................100 L Reception....................................................................99 Transmission...............................................................99 Load Conditions................................................................183 I2C Master Mode Support...................................................99 Low Voltage Detect (LVD)................................................157 I2C Module..........................................................................95 Low-Voltage Detect Characteristics..................................180 Addresses...................................................................97 LVDL Characteristics........................................................181 Bus Data Timing Characteristics M Master Mode.....................................................203 Slave Mode.......................................................205 Memory Organization.........................................................25 Bus Data Timing Requirements Core Register Map.....................................................37 Master Mode.....................................................204 Microchip Internet Web Site..............................................227 Slave Mode.......................................................206 Modes of Operation Bus Start/Stop Bits Timing Characteristics Disable......................................................................113 Master Mode.....................................................203 Initialization...............................................................113 Slave Mode.......................................................205 Listen All Messages..................................................113 General Call Address Support....................................99 Listen Only................................................................113 Interrupts.....................................................................99 Loopback..................................................................113 IPMI Support...............................................................99 Normal Operation.....................................................113 Operating Function Description..................................95 Module................................................................................95 Operation During CPU Sleep and Idle Modes..........100 Modulo Addressing.............................................................40 Pin Configuration........................................................95 Applicability.................................................................42 Programmer’s Model...................................................95 Operation Example.....................................................41 Register Map.............................................................101 Start and End Address...............................................41 Registers.....................................................................95 W Address Register Selection....................................41 Slope Control..............................................................99 MPLAB ASM30 Assembler, Linker, Librarian...................170 Software Controlled Clock Stretching (STREN = 1)....98 MPLAB Integrated Development Environment Software..169 Various Modes............................................................95 MPLAB PM3 Device Programmer....................................172 I2S Mode Operation..........................................................131 MPLAB REAL ICE In-Circuit Emulator System................171 Data Justification.......................................................131 MPLINK Object Linker/MPLIB Object Librarian................170 Frame and Data Word Length Selection...................131 N Idle Current (IIDLE)............................................................177 In-Circuit Debugger (ICD 2)..............................................159 NVM In-Circuit Serial Programming (ICSP).........................51, 143 Register Map..............................................................55 Initialization Condition for RCON Register Case 1...........156 O Initialization Condition for RCON Register Case 2...........156 OC/PWM Module Timing Characteristics.........................194 Input Capture (CAPX) Timing Characteristics..................193 Input Capture Module.........................................................81 Operating Current (IDD)....................................................176 Oscillator Interrupts.....................................................................82 Control Registers......................................................149 Register Map...............................................................83 Operating Modes (Table)..........................................144 Input Capture Operation During Sleep and Idle Modes......82 System Overview......................................................143 CPU Idle Mode............................................................82 Oscillator Configurations...................................................146 CPU Sleep Mode........................................................82 Fail-Safe Clock Monitor............................................148 Input Capture Timing Requirements.................................193 Fast RC (FRC)..........................................................147 Input Change Notification Module.......................................66 Initial Clock Source Selection...................................146 Register Map for dsPIC30F6011A/6012 A (Bits 7-0)..66 Low-Power RC (LPRC)............................................148 Register Map for dsPIC30F6011A/6012A (Bits 15-8).66 LP Oscillator Control.................................................147 Register Map for dsPIC30F6013A/6014A (Bits 15-8).66 Phase Locked Loop (PLL)........................................147 Register Map for dsPIC30F6013A/6014A (Bits 7-0)...66 Start-up Timer (OST)................................................147 Instruction Addressing Modes.............................................39 Oscillator Selection...........................................................143 File Register Instructions............................................39 Oscillator Start-up Timer Fundamental Modes Supported..................................39 Timing Characteristics..............................................188 MAC Instructions.........................................................40 Timing Requirements...............................................189 MCU Instructions........................................................39 Output Compare Interrupts.................................................88 © 2011 Microchip Technology Inc. DS70143E-page 227

dsPIC30F6011A/6012A/6013A/6014A Output Compare Module.....................................................85 Erasing a Row of Program Memory............................53 Register Map...............................................................89 Initiating the Programming Sequence.........................54 Timing Characteristics..............................................193 Loading Write Latches................................................54 Timing Requirements................................................193 Protection Against Accidental Writes to OSCCON...........149 Output Compare Operation During CPU Idle Mode............88 R Output Compare Sleep Mode Operation.............................88 Reader Response.............................................................228 P Reset........................................................................143, 153 Packaging Information......................................................213 Reset Sequence.................................................................47 Marking.....................................................................213 Reset Sources............................................................47 Peripheral Module Disable (PMD) Registers....................159 Reset Sources Pinout Descriptions.............................................................14 Brown-out Reset (BOR)..............................................47 POR. See Power-on Reset. Illegal Instruction Trap................................................47 PORTA Trap Lockout...............................................................47 Register Map for dsPIC30F6013A/6014A...................63 Uninitialized W Register Trap.....................................47 PORTB Watchdog Time-out....................................................47 Register Map for dsPIC30F6011A/6012A/6013A/6014A Reset Timing Characteristics............................................188 63 Reset Timing Requirements.............................................189 PORTC Resets Register Map for dsPIC30F6011A/6012A...................63 Brown-out Rest (BOR), Programmable....................155 Register Map for dsPIC30F6013A/6014A...................63 POR with Long Crystal Start-up Time.......................155 PORTD POR, Operating without FSCM and PWRT..............155 Register Map for dsPIC30F6011A/6012A...................64 Power-on Reset (POR).............................................153 Register Map for dsPIC30F6013A/6014A...................64 RTSP Operation.................................................................52 PORTF Run-Time Self-Programming (RTSP).................................51 Register Map for dsPIC30F6011A/6012A...................64 S Register Map for dsPIC30F6013A/6014A...................64 PORTG Serial Peripheral Interface. See SPI Register Map for dsPIC30F6011A/6012A/6013A/ Simple Capture Event Mode...............................................81 6014A..................................................................65 Buffer Operation.........................................................82 Power Saving Modes Hall Sensor Mode.......................................................82 Idle............................................................................158 Prescaler....................................................................81 Sleep.........................................................................157 Timer2 and Timer3 Selection Mode............................82 Power-Down Current (IPD)................................................178 Simple OC/PWM Mode Timing Requirements.................194 Power-on Reset (POR).....................................................143 Simple Output Compare Match Mode................................86 Oscillator Start-up Timer (OST)................................143 Simple PWM Mode.............................................................86 Power-up Timer (PWRT)..........................................143 Input Pin Fault Protection...........................................86 Power-Saving Modes........................................................157 Period.........................................................................87 Power-Saving Modes (Sleep and Idle)..............................143 Software Simulator (MPLAB SIM)....................................171 Power-up Timer Software Stack Pointer, Frame Pointer..............................18 Timing Characteristics..............................................188 CALL Stack Frame.....................................................35 Timing Requirements................................................189 SPI Module.........................................................................91 Program Address Space.....................................................25 Framed SPI Support...................................................92 Construction................................................................27 Operating Function Description..................................91 Data Access from Program Memory Operation During CPU Idle Mode...............................93 Using Program Space Visibility...........................29 Operation During CPU Sleep Mode............................93 Data Access from Program Memory SDOx Disable.............................................................91 Using Table Instructions.....................................28 Slave Select Synchronization.....................................93 Data Access from, Address Generation......................27 SPI1 Register Map......................................................94 Data Space Window into Operation............................30 SPI2 Register Map......................................................94 Data Table Access (Least Significant Word)..............28 Timing Characteristics Data Table Access (MSB)...........................................29 Master Mode (CKE = 0)....................................198 Memory Map for dsPIC30F6011A/6013A...................26 Master Mode (CKE = 1)....................................199 Memory Map for dsPIC30F6012A/6014A...................26 Slave Mode (CKE = 1)..............................200, 201 Table Instructions Timing Requirements TBLRDH..............................................................28 Master Mode (CKE = 0)....................................198 TBLRDL..............................................................28 Master Mode (CKE = 1)....................................199 TBLWTH.............................................................28 Slave Mode (CKE = 0)......................................200 TBLWTL..............................................................28 Slave Mode (CKE = 1)......................................202 Program and EEPROM Characteristics............................182 Word and Byte Communication..................................91 Program Counter.................................................................18 STATUS Register...............................................................18 Programmable...................................................................143 Symbols used in Opcode Descriptions.............................162 Programmer’s Model...........................................................18 System Integration............................................................143 Diagram......................................................................19 Register Map for dsPIC30F601xA............................160 Programming Operations....................................................53 Algorithm for Program Flash.......................................53 DS70143E-page 228 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A T (MCLR Not Tied to VDD), Case 1.....................154 Time-out Sequence on Power-up Table Instruction Operation Summary................................51 Temperature and Voltage Specifications (MCLR Not Tied to VDD), Case 2.....................154 Time-out Sequence on Power-up AC.............................................................................183 Timer1 Module....................................................................67 (MCLR Tied to VDD).........................................154 Timing Diagrams.See Timing Characteristics 16-bit Asynchronous Counter Mode...........................67 Timing Requirements 16-bit Synchronous Counter Mode.............................67 Band Gap Start-up Time...........................................190 16-bit Timer Mode.......................................................67 Brown-out Reset.......................................................189 Gate Operation...........................................................68 CAN Module I/O.......................................................207 Interrupt.......................................................................68 CLKOUT and I/O......................................................187 Operation During Sleep Mode....................................68 DCI Module Prescaler.....................................................................68 AC-Link Mode...................................................197 Real-Time Clock.........................................................68 Multichannel, I2S Modes...................................196 Interrupts.............................................................69 External Clock..........................................................184 Oscillator Operation............................................69 I2C Bus Data (Master Mode)....................................204 Register Map...............................................................70 I2C Bus Data (Slave Mode)......................................206 Timer2 and Timer3 Selection Mode....................................86 Input Capture............................................................193 Timer2/3 Module.................................................................71 Oscillator Start-up Timer...........................................189 16-bit Timer Mode.......................................................71 Output Compare Module..........................................193 32-bit Synchronous Counter Mode.............................71 Power-up Timer........................................................189 32-bit Timer Mode.......................................................71 Reset........................................................................189 ADC Event Trigger......................................................74 Simple OC/PWM Mode............................................194 Gate Operation...........................................................74 SPI Module Interrupt.......................................................................74 Master Mode (CKE = 0)....................................198 Operation During Sleep Mode....................................74 Master Mode (CKE = 1)....................................199 Register Map...............................................................75 Slave Mode (CKE = 0)......................................200 Timer Prescaler...........................................................74 Slave Mode (CKE = 1)......................................202 Timer4/5 Module.................................................................77 Type A Timer External Clock....................................191 Register Map...............................................................79 Type B Timer External Clock....................................192 Timing Characteristics Type C Timer External Clock....................................192 ADC Watchdog Timer (WDT)............................................189 Low-speed (ASAM = 0, SSRC = 000)..............209 Timing Specifications Band Gap Start-up Time...........................................190 External Clock Requirements...................................184 CAN Module I/O........................................................207 PLL Clock.................................................................185 CLKOUT and I/O.......................................................187 PLL Jitter..................................................................185 DCI Module Trap Vectors.......................................................................48 AC-Link Mode...................................................197 Multichannel, I2S Modes...................................195 Traps..................................................................................47 Hard and Soft.............................................................48 External Clock...........................................................183 I2C Bus Data Sources......................................................................47 Address Error Trap.............................................47 Master Mode.....................................................203 Math Error Trap..................................................47 Slave Mode.......................................................205 I2C Bus Start/Stop Bits Oscillator Fail Trap.............................................48 Stack Error Trap.................................................48 Master Mode.....................................................203 Slave Mode.......................................................205 U Input Capture (CAPX)...............................................193 UART Module OC/PWM Module......................................................194 Address Detect Mode...............................................107 Oscillator Start-up Timer...........................................188 Auto Baud Support...................................................108 Output Compare Module...........................................193 Baud Rate Generator...............................................107 Power-up Timer........................................................188 Enabling and Setting Up...........................................105 Reset.........................................................................188 Framing Error (FERR)..............................................107 SPI Module Idle Status.................................................................107 Master Mode (CKE = 0)....................................198 Loopback Mode........................................................107 Master Mode (CKE = 1)....................................199 Operation During CPU Sleep and Idle Modes..........108 Slave Mode (CKE = 0)......................................200 Overview...................................................................103 Slave Mode (CKE = 1)......................................201 Parity Error (PERR)..................................................107 Type A, B and C Timer External Clock.....................191 Receive Break..........................................................107 Watchdog Timer (WDT)............................................188 Receive Buffer (UxRXB)...........................................106 Timing Diagrams Receive Buffer Overrun Error (OERR Bit)................106 CAN Bit.....................................................................116 Receive Interrupt......................................................106 Frame Sync, AC-Link Start of Frame........................126 Receiving Data.........................................................106 Frame Sync, Multi-Channel Mode............................126 Receiving in 8-bit or 9-bit Data Mode.......................106 I2S Interface Frame Sync..........................................126 Reception Error Handling.........................................106 PWM Output...............................................................87 Transmit Break.........................................................106 Time-out Sequence on Power-up Transmit Buffer (UxTXB)..........................................105 © 2011 Microchip Technology Inc. DS70143E-page 229

dsPIC30F6011A/6012A/6013A/6014A Transmit Interrupt......................................................106 Transmitting Data......................................................105 Transmitting in 8-bit Data Mode................................105 Transmitting in 9-bit Data Mode................................105 UART1 Register Map................................................109 UART2 Register Map................................................109 UART Operation Idle Mode..................................................................108 Sleep Mode...............................................................108 Unit ID Locations...............................................................143 Universal Asynchronous Receiver Transmitter. See UART. W Wake-up from Sleep.........................................................143 Wake-up from Sleep and Idle..............................................49 Watchdog Timer (WDT)............................................143, 157 Enabling and Disabling.............................................157 Operation..................................................................157 Timing Characteristics..............................................188 Timing Requirements................................................189 WWW Address..................................................................227 WWW, On-Line Support........................................................9 DS70143E-page 230 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design • Development Systems Information Line resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. © 2011 Microchip Technology Inc. DS70143E-page 231

dsPIC30F6011A/6012A/6013A/6014A READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: dsPIC30F6011A/6012A/6013A/6014A Literature Number: DS70143E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70143E-page 232 © 2011 Microchip Technology Inc.

dsPIC30F6011A/6012A/6013A/6014A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC30F6011AT-30I/PF-ES Custom ID (3 digits) or Trademark Engineering Sample (ES) Architecture Package S = Die (Waffle Pack) W = Die (Wafers) Flash PT = 10x10 (64 TQFP ) PF = 14x14 (64 TQFP ) PT = 12x12 (80 TQFP ) Memory Size in Bytes PF = 14x14 (80 TQFP) 0 = ROMless 1 = 1K to 6K 2 = 7K to 12K 3 = 13K to 24K 4 = 25K to 48K Temperature 5 = 49K to 96K I = Industrial -40°C to +85°C 6 = 97K to 192K E = Extended High Temp -40°C to +125°C 7 = 193K to 384K 8 = 385K t o 768K 9 = 769K and Up Speed 30 = 30 MIPS Device ID T = Tape and Reel A,B,C… = Revision Level Example: dsPIC30F6011AT-30I/PF = 30 MIPS, Industrial temp., TQFP (14x14) package, Rev. A © 2011 Microchip Technology Inc. DS70143E-page 233

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: DSPIC30F6013T-20E/PF DSPIC30F6012T-30E/PF DSPIC30F6012T-20E/PF DSPIC30F6012T-30I/PF DSPIC30F6011T-30I/PF DSPIC30F6012T-20I/PF DSPIC30F6013T-20I/PF DSPIC30F6011T-20I/PF DSPIC30F6011T-20E/PF DSPIC30F6011A-20E/PF DSPIC30F6011A-20E/PT DSPIC30F6011A-30I/PF DSPIC30F6011A-30I/PT DSPIC30F6011AT-20E/PT DSPIC30F6011AT-30I/PT DSPIC30F6012A-20E/PF DSPIC30F6012A-20E/PT DSPIC30F6012A-30I/PF DSPIC30F6012A-30I/PT DSPIC30F6012AT-20E/PT DSPIC30F6012AT-30I/PT DSPIC30F6013A-20E/PF DSPIC30F6013A-20E/PT DSPIC30F6013A-30I/PF DSPIC30F6013A-30I/PT DSPIC30F6013AT-20E/PT DSPIC30F6013AT-30I/PT DSPIC30F6014A-20E/PF DSPIC30F6014A-20E/PT DSPIC30F6014A-30I/PF DSPIC30F6014A-30I/PT DSPIC30F6014AT-20E/PT DSPIC30F6014AT-30I/PT DSPIC30F6014T-30I/PF DSPIC30F6013T-30I/PF DSPIC30F6014T-20E/PF DSPIC30F6014T-20I/PF DSPIC30F6011AT-30I/PF DSPIC30F6012AT-20E/PF DSPIC30F6012AT-30I/PF DSPIC30F6013AT-20E/PF DSPIC30F6013AT-30I/PF DSPIC30F6014AT-20E/PF DSPIC30F6014AT-30I/PF