dsPIC30F6010A/6015 Data Sheet High-Performance, 16-bit Digital Signal Controllers © 2011 Microchip Technology Inc. DS70150E

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-953-2 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70150E-page 2 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 High-Performance, 16-bit Digital Signal Controllers Peripheral Features: Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not • High-current sink/source I/O pins: 25 mA/25 mA intended to be a complete reference • Timer module with programmable prescaler: source. For more information on the CPU, peripherals, register descriptions and - Five 16-bit timers/counters; optionally pair general device functionality, refer to the 16-bit timers into 32-bit timer modules “dsPIC30F Family Reference Manual” • 16-bit Capture input functions (DS70046). For more information on the • 16-bit Compare/PWM output functions device instruction set and programming, refer to the “16-bit MCU and DSC • 3-wire SPI modules (supports 4 Frame modes) Programmer’s Reference Manual” • I2CTM module supports Multi-Master/Slave mode (DS70157). and 7-bit/10-bit addressing • Two UART modules with FIFO Buffers High-Performance Modified RISC CPU: • Two CAN modules, 2.0B compliant (dsPIC306010A) • Modified Harvard architecture • One CAN module, 2.0B compliant (dsPIC306015) • C compiler optimized instruction set architecture Motor Control PWM Module Features: with flexible Addressing modes • 83 base instructions • Eight PWM output channels: • 24-bit wide instructions, 16-bit wide data path - Complementary or Independent Output • 144 Kbytes on-chip Flash program space modes (Instruction words) - Edge and Center-Aligned modes • 8 Kbytes of on-chip data RAM • Four duty cycle generators • 4 Kbytes of nonvolatile data EEPROM • Dedicated time base • Up to 30 MIPS operation: • Programmable output polarity - DC to 40 MHz external clock input • Dead-Time control for Complementary mode - 4 MHz-10 MHz oscillator input with • Manual output control PLL active (4x, 8x, 16x) • Trigger for A/D conversions - 7.37 MHz internal RC with PLL active (4x, 8x, 16x) Quadrature Encoder Interface Module • 44 interrupt sources: Features: - Five external interrupt sources • Phase A, Phase B and Index Pulse input - Eight user selectable priority levels for each interrupt source • 16-bit up/down position counter - Four processor trap sources • Count direction status • 16 x 16-bit working register array • Position Measurement (x2 and x4) mode • Programmable digital noise filters on inputs DSP Engine Features: • Alternate 16-bit Timer/Counter mode • Interrupt on position counter rollover/underflow • Dual data fetch • Accumulator write-back for DSP operations Analog Features: • Modulo and Bit-Reversed Addressing modes • 10-bit Analog-to-Digital Converter (ADC) with • Two, 40-bit wide accumulators with optional four S/H Inputs: saturation logic - 1 Msps conversion rate • 17-bit x 17-bit single-cycle hardware fractional/ integer multiplier - 16 input channels • All DSP instructions single cycle - Conversion available during Sleep and Idle • ±16-bit single-cycle shift • Programmable Brown-out Reset © 2011 Microchip Technology Inc. DS70150E-page 3

dsPIC30F6010A/6015 Special Microcontroller Features: CMOS Technology: • Enhanced Flash program memory: • Low-power, high-speed Flash technology - 10,000 erase/write cycle (min.) for • Wide operating voltage range (2.5V to 5.5V) industrial temperature range, 100K (typical) • Industrial and Extended temperature ranges • Data EEPROM memory: • Low-power consumption - 100,000 erase/write cycle (min.) for industrial temperature range, 1M (typical) • Self-reprogrammable under software control • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Flexible Watchdog Timer (WDT) with on-chip, low-power RC oscillator for reliable operation • Fail-Safe Clock Monitor operation detects clock failure and switches to on-chip, low-power RC oscillator • Programmable code protection • In-Circuit Serial Programming™ (ICSP™) • Selectable Power Management modes - Sleep, Idle and Alternate Clock modes dsPIC30F Motor Control and Power Conversion Family Device Pins MInePsmtrrou.g cBrtayiomtenss/ SBRyAteMs EEBPyRteOsM T16im-beirt InCpaupt COoPmuWtppM/uSttd CMPooWnttoMrorl A1/D M 1s0p-bsit QEunacd UART SPI 2IC™ CAN dsPIC30F6010A 80 144K/48K 8192 4096 5 8 8 8 ch 16 ch Yes 2 2 1 2 dsPIC30F6015 64 144K/48K 8192 4096 5 8 8 8 ch 16 ch Yes 2 2 1 1 DS70150E-page 4 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 Pin Diagram 80-Pin TQFP 7 D R 6/ 1 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2PWM1H/RE1 PWM1L/RE0 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VSS OC8/UPDN/CN1 OC7/CN15/RD6 OC6/CN14/RD5OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 EMUD2/OC2/RD 0 9 8 7 6 5 4 3 2 1 0 9 8 7 65 4 3 2 1 8 7 7 7 7 7 7 7 7 7 7 6 6 6 66 6 6 6 6 60 EMUC1/SOSCO/T1CK/CN0/RC14 PWM3H/RE5 1 59 EMUD1/SOSCI/CN1/RC13 PWM4L/RE6 2 58 EMUC2/OC1/RD0 PWM4H/RE7 3 57 IC4/RD11 T2CK/RC1 4 56 IC3/RD10 T4CK/RC3 5 SCK2/CN8/RG6 6 55 IC2/RD9 SDI2/CN9/RG7 7 54 IC1/RD8 SDO2/CN10/RG8 8 53 INT4/RA15 MCLR 9 52 INT3/RA14 SS2/CN11/RG9 10 dsPIC30F6010A 51 VSS VSS 11 50 OSC2/CLKO/RC15 VDD 12 49 OSC1/CLKI FLTA/INT1/RE8 13 48 VDD FLTB/INT2/RE9 14 47 SCL/RG2 AN5/QEB/CN7/RB5 15 46 SDA/RG3 AN4/QEA/CN6/RB4 16 45 EMUC3/SCK1/INT0/RF6 AN3/INDX/CN5/RB3 17 44 SDI1/RF7 AN2/SS1/CN4/RB2 18 43 EMUD3/SDO1/RF8 PGC/EMUC/AN1/CN3/RB1 19 42 U1RX/RF2 PGD/EMUD/AN0/CN2/RB0 20 41 U1TX/RF3 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 RB6 RB7 RA9 A10 VDD VSS RB8 RB9 B10 B11 VSS VDD B12 B13 B14 B15D14 D15 RF4 RF5 AN6/OCFA/ AN7/ V-/REF V+/RREF A A AN8/ AN9/ AN10/R AN11/R AN12/R AN13/R AN14/R CFB/CN12/RIC7/CN20/R IC8/CN21/R U2RX/CN17/ U2TX/CN18/ O 5/ 1 N A © 2011 Microchip Technology Inc. DS70150E-page 5

dsPIC30F6010A/6015 Pin Diagram 64-Pin TQFP 7 D R 54 N16/D64/RD3/RD RD1 PWM3L/RE4PWM2H/RE3PWM2L/RE2PWM1H/RE1PWM1L/RE0C1TX/RF1C1RX/RF0VDDVSSOC8/UPDN/COC7/CN15/ROC6/IC6/CN1OC5/IC5/CN1OC4/RD3OC3/RD2EMUD2/OC2/ 4321098765432109 6666655555555554 PWM3H/RE5 1 48 EMUC1/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 47 EMUD1/SOSCI/T4CK/CN1/RC13 PWM4H/RE7 3 46 EMUC2/OC1/RD0 SCK2/CN8/RG6 4 45 IC4/INT4/RD11 SDI2/CN9/RG7 5 44 IC3/INT3/RD10 SDO2/CN10/RG8 6 43 IC2/FLTB/INT2/RD9 MCLR 7 42 IC1/FLTA/INT1/RD8 SS2/CN11/RG9 8 dsPIC30F6015 41 VSS VSS 9 40 OSC2/CLKO/RC15 VDD 10 39 OSC1/CLKI AN5/QEB/IC8/CN7/RB5 11 38 VDD AN4/QEA/IC7/CN6/RB4 12 37 SCL/RG2 AN3/INDX/CN5/RB3 13 36 SDA/RG3 AN2/SS1/CN4/RB2 14 35 EMUC3/SCK1/INT0/RF6 AN1/VREF-/CN3/RB1 15 34 U1RX/SDI1/RF2 AN0/VREF+/CN2/RB0 16 33 EMUD3/U1TX/SDO1/RF3 7890123456789012 1112222222222333 67 D S8901 S D234545 BB D SBB11 S D1111FF RRVVRRBBVVBBBBRR C/AN6/OCFA/D/EMUD/AN7/AAAN8/AN9/AN10/RAN11/R AN12/RAN13/RAN14/ROCFB/CN12/RU2RX/CN17/U2TX/CN18/ MUPG 15/ E N C/ A G P DS70150E-page 6 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 CPU Architecture Overview........................................................................................................................................................15 3.0 Memory Organization.................................................................................................................................................................23 4.0 Address Generator Units............................................................................................................................................................35 5.0 Interrupts....................................................................................................................................................................................41 6.0 Flash Program Memory..............................................................................................................................................................49 7.0 Data EEPROM Memory.............................................................................................................................................................55 8.0 I/O Ports.....................................................................................................................................................................................59 9.0 Timer1 Module...........................................................................................................................................................................65 10.0 Timer2/3 Module........................................................................................................................................................................69 11.0 Timer4/5 Module .......................................................................................................................................................................77 12.0 Input Capture Module ................................................................................................................................................................81 13.0 Output Compare Module............................................................................................................................................................85 14.0 Quadrature Encoder Interface (QEI) Module.............................................................................................................................91 15.0 Motor Control PWM Module.......................................................................................................................................................97 16.0 SPI Module...............................................................................................................................................................................107 17.0 I2C™ Module...........................................................................................................................................................................111 18.0 Universal Asynchronous Receiver Transmitter (UART) Module..............................................................................................119 19.0 CAN Module.............................................................................................................................................................................127 20.0 10-bit High-Speed Analog-to-Digital Converter (ADC) Module................................................................................................139 21.0 System Integration...................................................................................................................................................................151 22.0 Instruction Set Summary..........................................................................................................................................................165 23.0 Development Support...............................................................................................................................................................173 24.0 Electrical Characteristics..........................................................................................................................................................177 25.0 Packaging Information..............................................................................................................................................................217 Appendix A: Revision History.............................................................................................................................................................225 Index................................................................................................................................................................................................. 227 The Microchip Web Site.....................................................................................................................................................................233 Customer Change Notification Service..............................................................................................................................................233 Customer Support..............................................................................................................................................................................233 Reader Response..............................................................................................................................................................................234 Product Identification System............................................................................................................................................................235 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2011 Microchip Technology Inc. DS70150E-page 7

dsPIC30F6010A/6015 NOTES: DS70150E-page 8 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 1.0 DEVICE OVERVIEW Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157). This document contains device-specific information for the dsPIC30F6010A and dsPIC30F6015 devices. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) functionality within a high-perfor- mance 16-bit microcontroller (MCU) architecture. Figure1-1 shows a device block diagram for the dsPIC30F6010A device. Figure1-2 shows a device block diagram for the dsPIC30F6015 device. © 2011 Microchip Technology Inc. DS70150E-page 9

dsPIC30F6010A/6015 FIGURE 1-1: dsPIC30F6010A BLOCK DIAGRAM Y Data Bus X Data Bus 16 16 16 16 16 VREF-/RA9 VREF+/RA10 Interrupt Data Latch Data Latch PSV & Table INT3/RA14 Controller 24CDoantatr oAl cBcleoscsk 8 16 YR DAaMta XR DAaMta INT4/RA15 (4 Kbytes) (4 Kbytes) PORTA Address Address 24 Latch Latch PGD/EMUD/AN0/CN2/RB0 PGC/EMUC/AN1/CN3/RB1 16 16 16 AN2/SS1/CN4/RB2 24 X RAGU Y AGU AN3/INDX/CN5/RB3 PCU PCH PCL X WAGU AN4/QEA/CN6/RB4 Program Counter AN5/QEB/CN7/RB5 Address Latch CSotanctrkol CLoonotprol AN6/OCFA/RB6 Program Memory Logic Logic AN7/RB7 (144 Kbytes) AN8/RB8 AN9/RB9 Data EEPROM AN10/RB10 (4 Kbytes) Effective Address AN11/RB11 Data Latch 16 AN12/RB12 AN13/RB13 AN14/RB14 ROM Latch 16 AN15/OCFB/CN12/RB15 24 PORTB IR T2CK/RC1 T4CK/RC3 16 16 EMUD1/SOSCI/CN1/RC13 EMUC1/SOSCO/T1CK/CN0/RC14 16 x 16 OSC2/CLKO/RC15 W Reg Array Decode PORTC Instruction Decode and 16 16 Control EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 Ctoo Vnatrroiol uSsig Bnlaolcsk s Power-up E DngSiPne D Uivnidite OOCC54//CRND133/RD4 Timer OC6/CN14/RD5 OSC1/CLKI GeTnimeriantgion StaOrts-cuipll aTtoimrer OOCC78//CUNPD15N/R/CDN616/RD7 IC1/RD8 POR/BOR ALU<16> IC2/RD9 Reset IC3/RD10 MCLR Watchdog 16 16 IC4/RD11 Timer IC5/RD12 IC6/CN19/RD13 Low-Voltage IC7/CN20/RD14 VDD, VSS Detect IC8/CN21/RD15 AVDD, AVSS PORTD PWM1L/RE0 CAN1, Input O utput PWM1H/RE1 CAN2 10-bit ADC Capture Com pare I2C™ PWM2L/RE2 Module Module PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SSPPII21, Timers QEI MotoPrW CMontrol UUAARRTT12, FFLLTTAB//IINNTT12//RREE89 PORTE C1RX/RF0 C2RX/RG0 C1TX/RF1 C2TX/RG1 U1RX/RF2 SCL/RG2 U1TX/RF3 SDA/RG3 SCK2/CN8/RG6 U2RX/CN17/RF4 SDI2/CN9/RG7 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 SDO2/CN10/RG8 SDI1/RF7 SS2/CN11/RG9 EMUD3/SDO1/RF8 PORTG PORTF DS70150E-page 10 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 1-2: dsPIC30F6015 BLOCK DIAGRAM Y Data Bus X Data Bus 16 16 16 16 16 Interrupt Data Latch Data Latch Controller PSV & Table Y Data X Data Data Access 24Control Block 8 16 RAM RAM (4 Kbytes) (4 Kbytes) Address Address 24 Latch Latch AN0/VREF+/CN2/RB0 16 16 16 AN1/VREF-/CN3/RB1 AN2/SS1/CN4/RB2 24 X RAGU Y AGU AN3/INDX/CN5/RB3 PCU PCH PCL X WAGU AN4/QEA/IC7/CN6/RB4 Program Counter AN5/QEB/IC8/CN7/RB5 Address Latch CSotanctrkol CLoonotprol PGC/EMUC/AN6/OCFA/RB6 Program Memory Logic Logic PGD/EMUD/AN7/RB7 (144 Kbytes) AN8/RB8 AN9/RB9 Data EEPROM AN10/RB10 (4 Kbytes) Effective Address AN11/RB11 Data Latch 16 AN12/RB12 AN13/RB13 AN14/RB14 ROM Latch 16 AN15/OCFB/CN12/RB15 24 PORTB IR EMUD1/SOSCI/T4CK/CN1/RC13 16 16 EMUC1/SOSCO/T1CK/CN0/RC14 OSC2/CLKO/RC15 16 x 16 W Reg Array Decode PORTC Instruction Decode and 16 16 Control Ctoo Vnatrroiol uSsig Bnlaolcsk s Power-up E DngSiPne D Uivnidite EEOMMCUU3/CDR22D//2OOCC12//RRDD01 Timer OC4/RD3 OSC1/CLKI Timing Oscillator OC5/IC5/CN13/RD4 Generation Start-up Timer OC6/IC6/CN14/RD5 OC7/CN15/RD6 POR/BOR ALU<16> OC8/UPDN/CN16/RD7 Reset IC1/FLTA/INT1/RD8 MCLR Watchdog 16 16 IC2/FLTB/INT2/RD9 Timer IC3/INT3/RD10 IC4/INT4/RD11 Low-Voltage VDD, VSS Detect AVDD, AVSS PORTD Input O utput PWM1L/RE0 CAN1 10-bit ADC Capture Com pare I2C™ PWM1H/RE1 Module Module PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 PWM4L/RE6 SSPPII21, Timers QEI MotoPrW CMontrol UUAARRTT12, PWM4H/RE7 PORTE SCL/RG2 C1RX/RF0 SDA/RG3 C1TX/RF1 SCK2/CN8/RG6 U1RX/SDI1/RF2 SDI2/CN9/RG7 EMUD3/U1TX/SDO1/RF3 SDO2/CN10/RG8 U2RX/CN17/RF4 SS2/CN11/RG9 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 PORTG PORTF © 2011 Microchip Technology Inc. DS70150E-page 11

dsPIC30F6010A/6015 Table1-1 provides a brief description of the device I/O pinout and the functions that are multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: dsPIC30F6010A/6015 I/O PIN DESCRIPTIONS Pin Buffer Pin Name Description Type Type AN0-AN15 I Analog Analog input channels. AN0 and AN1 are also used for device programming data and clock inputs, respectively. AVDD P P Positive supply for analog module. This pin must be connected at all times. AVSS P P Ground reference for analog module. This pin must be connected at all times. CLKI I ST/CMOS External clock source input. Always associated with OSC1 pin function. CLKO O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. CN0-CN23 I ST Input change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. C1RX I ST CAN1 bus receive pin. C1TX O — CAN1 bus transmit pin. C2RX I ST CAN2 bus receive pin. C2TX O — CAN2 bus transmit pin. EMUD I/O ST ICD Primary Communication Channel data input/output pin. EMUC I/O ST ICD Primary Communication Channel clock input/output pin. EMUD1 I/O ST ICD Secondary Communication Channel data input/output pin. EMUC1 I/O ST ICD Secondary Communication Channel clock input/output pin. EMUD2 I/O ST ICD Tertiary Communication Channel data input/output pin. EMUC2 I/O ST ICD Tertiary Communication Channel clock input/output pin. EMUD3 I/O ST ICD Quaternary Communication Channel data input/output pin. EMUC3 I/O ST ICD Quaternary Communication Channel clock input/output pin. IC1-IC8 I ST Capture inputs 1 through 8. INDX I ST Quadrature Encoder Index Pulse input. QEA I ST Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. QEB I ST Quadrature Encoder Phase B input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. UPDN O — Position Up/Down Counter Direction State. INT0 I ST External interrupt 0. INT1 I ST External interrupt 1. INT2 I ST External interrupt 2. INT3 I ST External interrupt 3. INT4 I ST External interrupt 4. Legend: CMOS= CMOS compatible input or output Analog= Analog input ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power DS70150E-page 12 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 TABLE 1-1: dsPIC30F6010A/6015 I/O PIN DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Description Type Type FLTA I ST PWM Fault A input. FLTB I ST PWM Fault B input. PWM1L O — PWM1 Low output. PWM1H O — PWM1 High output. PWM2L O — PWM2 Low output. PWM2H O — PWM2 High output. PWM3L O — PWM3 Low output. PWM3H O — PWM3 High output. PWM4L O — PWM4 Low output. PWM4H O — PWM4 High output. MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active-low Reset to the device. OCFA I ST Compare Fault A input (for Compare channels 1, 2, 3 and 4). OCFB I ST Compare Fault B input (for Compare channels 5, 6, 7 and 8). OC1-OC8 O — Compare outputs 1 through 8. OSC1 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. OSC2 I/O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. PGD I/O ST In-Circuit Serial Programming™ data input/output pin. PGC I ST In-Circuit Serial Programming clock input pin. RA9-RA10 I/O ST PORTA is a bidirectional I/O port. RA14-RA15 I/O ST RB0-RB15 I/O ST PORTB is a bidirectional I/O port. RC1 I/O ST PORTC is a bidirectional I/O port. RC3 I/O ST RC13-RC15 I/O ST RD0-RD15 I/O ST PORTD is a bidirectional I/O port. RE0-RE9 I/O ST PORTE is a bidirectional I/O port. RF0-RF8 I/O ST PORTF is a bidirectional I/O port. RG0-RG3 I/O ST PORTG is a bidirectional I/O port. RG6-RG9 I/O ST SCK1 I/O ST Synchronous serial clock input/output for SPI1. SDI1 I ST SPI1 Data In. SDO1 O — SPI1 Data Out. SS1 I ST SPI1 Slave Synchronization. SCK2 I/O ST Synchronous serial clock input/output for SPI2. SDI2 I ST SPI2 Data In. SDO2 O — SPI2 Data Out. SS2 I ST SPI2 Slave Synchronization. SCL I/O ST Synchronous serial clock input/output for I2C™. SDA I/O ST Synchronous serial data input/output for I2C. SOSCO O — 32 kHz low-power oscillator crystal output. SOSCI I ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. T1CK I ST Timer1 external clock input. T2CK I ST Timer2 external clock input. T4CK I ST Timer4 external clock input. Legend: CMOS= CMOS compatible input or output Analog= Analog input ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power © 2011 Microchip Technology Inc. DS70150E-page 13

dsPIC30F6010A/6015 TABLE 1-1: dsPIC30F6010A/6015 I/O PIN DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Description Type Type U1RX I ST UART1 Receive. U1TX O — UART1 Transmit. U1ARX I ST UART1 Alternate Receive. U1ATX O — UART1 Alternate Transmit. U2RX I ST UART2 Receive. U2TX O — UART2 Transmit. VDD P — Positive supply for logic and I/O pins. VSS P — Ground reference for logic and I/O pins. VREF+ I Analog Analog Voltage Reference (High) input. VREF- I Analog Analog Voltage Reference (Low) input. Legend: CMOS= CMOS compatible input or output Analog= Analog input ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power DS70150E-page 14 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 2.0 CPU ARCHITECTURE • Linear indirect access of 32K word pages within pro- gram space is also possible using any working reg- OVERVIEW ister, via table read and write instructions. Table read and write instructions can be used to access all Note: This data sheet summarizes features of 24 bits of an instruction word. this group ofdsPIC30F devices and is not intended to be a complete reference Overhead-free circular buffers (Modulo Addressing) source. For more information on the are supported in both X and Y address spaces. This is peripherals, register descriptions and primarily intended to remove the loop overhead for general device functionality, refer to the DSP algorithms. “dsPIC30F Family Reference Manual” The X AGU also supports Bit-Reversed Addressing on (DS70046). For more information on the destination Effective Addresses, to greatly simplify device instruction set and programming, input or output data reordering for radix-2 FFT algo- refer to the “16-bit MCU and DSC Programmer’s Reference Manual” rithms. Refer to Section4.0 “Address Generator (DS70157). Units” for details on Modulo and Bit-Reversed Addressing. This chapter summarizes the CPU and peripheral The core supports Inherent (no operand), Relative, Lit- functions of the dsPIC30F6010A/6015. eral, Memory Direct, Register Direct, Register Indirect, 2.1 Core Overview Register Offset and Literal Offset Addressing modes. Instructions are associated with predefined addressing The core has a 24-bit instruction word. The Program modes, depending upon their functional requirements. Counter (PC) is 23 bits wide with the Least Significant For most instructions, the core is capable of executing bit (LSb) always clear (see Section3.1 “Program a data (or program data) memory read, a working reg- Address Space”), and the Most Significant bit (MSb) ister (data) read, a data memory write and a program is ignored during normal program execution, except for (instruction) memory read per instruction cycle. As a certain specialized instructions. Thus, the PC can result, 3-operand instructions are supported, allowing address up to 4M instruction words of user program C=A + B operations to be executed in a single cycle. space. An instruction prefetch mechanism is used to help maintain throughput. Program loop constructs, A DSP engine has been included to significantly free from loop count management overhead, are sup- enhance the core arithmetic capability and throughput. ported using the DO and REPEAT instructions, both of It features a high-speed 17-bit by 17-bit multiplier, a which are interruptible at any point. 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. Data in the accumula- The working register array consists of 16x16-bit regis- tor or any working register can be shifted up to 16 bits ters, each of which can act as data, address or offset right or 16 bits left in a single cycle. The DSP instruc- registers. One working register (W15) operates as a tions operate seamlessly with all other instructions and Software Stack Pointer for interrupts and calls. have been designed for optimal real-time performance. The data space is 64 Kbytes (32K words) and is split into The MAC class of instructions can concurrently fetch two blocks, referred to as X and Y data memory. Each two data operands from memory, while multiplying two block has its own independent Address Generation Unit W registers. To enable this concurrent fetching of data (AGU). Most instructions operate solely through the X operands, the data space has been split for these memory AGU, which provides the appearance of a sin- instructions and linear for all others. This has been gle unified data space. The Multiply-Accumulate (MAC) achieved in a transparent and flexible manner, by ded- class of dual source DSP instructions operate through icating certain working registers to each address space both the X and Y AGUs, splitting the data address space for the MAC class of instructions. into two parts (see Section3.2 “Data Address The core does not support a multi-stage instruction Space”). The X and Y data space boundary is device- pipeline. However, a single stage instruction prefetch specific and cannot be altered by the user. Each data mechanism is used, which accesses and partially word consists of 2 bytes, and most instructions can decodes instructions a cycle ahead of execution, in address data either as words or bytes. order to maximize available execution time. Most There are two methods of accessing data stored in instructions execute in a single cycle, with certain program memory: exceptions. • The upper 32 Kbytes of data space memory can be The core features a vectored exception processing mapped into the lower half (user space) of program structure for traps and interrupts, with 62 independent space at any 16K program word boundary, defined by vectors. The exceptions consist of up to 8 traps (of the 8-bit Program Space Visibility Page (PSVPAG) which 4 are reserved) and 54 interrupts. Each interrupt register. This lets any instruction access program is prioritized based on a user-assigned priority between space as if it were data space, with a limitation that 1 and 7 (1 being the lowest priority and 7 being the the access requires an additional cycle. Moreover, highest) in conjunction with a predetermined ‘natural only the lower 16 bits of each instruction word can be order’. Traps have fixed priorities, ranging from 8 to 15. accessed using this method. © 2011 Microchip Technology Inc. DS70150E-page 15

dsPIC30F6010A/6015 2.2 Programmer’s Model 2.2.1 SOFTWARE STACK POINTER/ FRAME POINTER The programmer’s model is shown in Figure2-1 and consists of 16x16-bit working registers (W0 through The dsPIC DSC devices contain a software stack. W15 W15), 2x40-bit accumulators (AccA and AccB), is the dedicated Software Stack Pointer (SP), and will STATUS register (SR), Data Table Page register be automatically modified by exception processing and (TBLPAG), Program Space Visibility Page register subroutine calls and returns. However, W15 can be ref- (PSVPAG), DO and REPEAT registers (DOSTART, erenced by any instruction in the same manner as all DOEND, DCOUNT and RCOUNT), and Program other W registers. This simplifies the reading, writing Counter (PC). The working registers can act as data, and manipulation of the Stack Pointer (e.g., creating address or offset registers. All registers are memory stack frames). mapped. W0 acts as the W register for file register Note: In order to protect against misaligned addressing. stack accesses, W15<0> is always clear. Some of these registers have a shadow register asso- W15 is initialized to 0x0800 during a Reset. The user ciated with each of them, as shown in Figure2-1. The may reprogram the SP during initialization to any shadow register is used as a temporary holding register location within data space. and can transfer its contents to or from its host register upon the occurrence of an event. None of the shadow W14 has been dedicated as a Stack Frame Pointer as registers are accessible directly. The following rules defined by the LNK and ULNK instructions. However, apply for transfer of registers into and out of shadows. W14 can be referenced by any instruction in the same manner as all other W registers. • PUSH.S and POP.S W0, W1, W2, W3, SR (DC, N, OV, Z and C bits 2.2.2 STATUS REGISTER only) are transferred. The dsPIC DSC core has a 16-bit STATUS register • DO instruction (SR), the LSB of which is referred to as the SR Low DOSTART, DOEND, DCOUNT shadows are Byte (SRL) and the MSB as the SR High Byte (SRH). pushed on loop start and popped on loop end. See Figure 2-1 for SR layout. When a byte operation is performed on a working SRL contains all the MCU ALU operation status flags register, only the Least Significant Byte of the target (including the Z bit), as well as the CPU Interrupt Prior- register is affected. However, a benefit of memory ity Level Status bits, IPL<2:0>, and the Repeat Active mapped working registers is that both the Least and Status bit, RA. During exception processing, SRL is Most Significant Bytes can be manipulated through concatenated with the MSB of the PC to form a byte-wide data memory space accesses. complete word value which is then stacked. The upper byte of the SR register contains the DSP adder/subtractor Status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address up to 4M instruction words. DS70150E-page 16 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 2-1: dsPIC30F6010A/6015 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 DSP Operand W5 Registers W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP Offset W13/DSP Write-Back W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register AD39 AD31 AD15 AD0 DSP AccA Accumulators AccB PC22 PC0 0 Program Counter 7 0 TTBALBPPAAGG Data Table Page Address 7 0 PPSSVVPPAAGG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address 22 DOEND DO Loop End Address 15 0 CORCON Core Configuration Register OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRH SRL © 2011 Microchip Technology Inc. DS70150E-page 17

dsPIC30F6010A/6015 2.3 Divide Support 2.4 DSP Engine The dsPIC DSC devices feature a 16/16-bit signed The DSP engine consists of a high-speed 17-bit x fractional divide operation, as well as 32/16-bit and 17-bit multiplier, a barrel shifter, and a 40-bit adder/sub- 16/16-bit signed and unsigned integer divide opera- tractor (with two target accumulators, round and tions, in the form of single instruction iterative divides. saturation logic). The following instructions and data sizes are The dsPIC30F devices have a single instruction flow supported: which can execute either DSP or MCU instructions. • DIVF – 16/16 signed fractional divide Many of the hardware resources are shared between • DIV.sd – 32/16 signed divide the DSP and MCU instructions. For example, the instruction set has both DSP and MCU multiply • DIV.ud – 32/16 unsigned divide instructions which use the same hardware multiplier. • DIV.s – 16/16 signed divide The DSP engine also has the capability to perform inher- • DIV.u – 16/16 unsigned divide ent accumulator-to-accumulator operations, which The divide instructions must be executed within a require no additional data. These instructions are ADD, REPEAT loop. Any other form of execution (e.g., a SUB and NEG. series of discrete divide instructions) will not function The DSP engine has various options selected through correctly because the instruction flow depends on various bits in the CPU Core Configuration register RCOUNT. The divide instruction does not automatically (CORCON), as listed below: set up the RCOUNT value, and it must, therefore, be explicitly and correctly specified in the REPEAT instruc- 1. Fractional or Integer DSP Multiply (IF). tion, as shown in Table2-2 (REPEAT will execute the 2. Signed or Unsigned DSP Multiply (US). target instruction {operand value + 1} times). The 3. Conventional or Convergent Rounding (RND). REPEAT loop count must be set up for 18 iterations of 4. Automatic Saturation On/Off for AccA (SATA). the DIV/DIVF instruction. Thus, a complete divide operation requires 19cycles. 5. Automatic Saturation On/Off for AccB (SATB). 6. Automatic Saturation On/Off for Writes to Data Note: The divide flow is interruptible. However, Memory (SATDW). the user needs to save the context as 7. Accumulator Saturation mode Selection appropriate. (ACCSAT). Note: For CORCON layout, see Table3-3. A block diagram of the DSP engine is shown in Figure2-2. TABLE 2-1: DSP INSTRUCTION SUMMARY Instruction Algebraic Operation CLR A = 0 ED A = (x – y)2 EDAC A = A + (x – y)2 MAC A = A + (x * y) MOVSAC No change in A MPY A = x * y MPY.N A = – x * y MSC A = A – x * y TABLE 2-2: DIVIDE INSTRUCTIONS Instruction Function DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1 DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1 DIV.s Signed divide: Wm/Wn → W0; Rem → W1 DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1 DIV.u Unsigned divide: Wm/Wn → W0; Rem → W1 DS70150E-page 18 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM S a 40 40-bit Accumulator A 40 Round t 16 40-bit Accumulator B u Logic r a Carry/Borrow Out t Saturate e Adder Carry/Borrow In Negate 40 40 40 Barrel 16 Shifter 40 s u B a at D Sign-Extend X s u B a 32 16 at Zero Backfill D Y 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array © 2011 Microchip Technology Inc. DS70150E-page 19

dsPIC30F6010A/6015 2.4.1 MULTIPLIER 2.4.2.1 Adder/Subtractor, Overflow and Saturation The 17x17-bit multiplier is capable of signed or unsigned operations and can multiplex its output using The adder/subtractor is a 40-bit adder with an optional a scaler to support either 1.31 fractional (Q31) or 32-bit zero input into one side and either true or complement integer results. Unsigned operands are zero-extended data into the other input. In the case of addition, the into the 17th bit of the multiplier input value. Signed carry/borrow input is active-high and the other input is operands are sign-extended into the 17th bit of the mul- true data (not complemented), whereas in the case of tiplier input value. The output of the 17x17-bit multiplier/ subtraction, the carry/borrow input is active-low and the scaler is a 33-bit value, which is sign-extended to other input is complemented. The adder/subtractor 40bits. Integer data is inherently represented as a generates Overflow Status bits, SA/SB and OA/OB, signed two’s complement value, where the MSB is which are latched and reflected in the STATUS register. defined as a sign bit. Generally speaking, the range of • Overflow from bit 39: this is a catastrophic an N-bit two’s complement integer is -2N-1 to 2N-1 – 1. overflow in which the sign of the accumulator is For a 16-bit integer, the data range is -32768 (0x8000) destroyed. to 32767 (0x7FFF), including 0. For a 32-bit integer, the • Overflow into guard bits 32 through 39: this is a data range is -2,147,483,648 (0x80000000) to recoverable overflow. This bit is set whenever all 2,147,483,645 (0x7FFF FFFF). the guard bits are not identical to each other. When the multiplier is configured for fractional multipli- The adder has an additional saturation block which cation, the data is represented as a two’s complement controls accumulator data saturation, if selected. It fraction, where the MSB is defined as a sign bit and the uses the result of the adder, the Overflow Status bits radix point is implied to lie just after the sign bit described above, and the SATA/B (CORCON<7:6>) (QXformat). The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to (1-21-N). and ACCSAT (CORCON<4>) mode control bits to determine when and to what value to saturate. For a 16-bit fraction, the Q15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF), including 0 and Six STATUS register bits have been provided to has a precision of 3.01518x10-5. In Fractional mode, a support saturation and overflow. They are: 16x16 multiply operation generates a 1.31 product, 1. OA: which has a precision of 4.65661x10-10. AccA overflowed into guard bits The same multiplier is used to support the MCU multi- 2. OB: ply instructions, which include integer 16-bit signed, AccB overflowed into guard bits unsigned and mixed sign multiplies. 3. SA: The MUL instruction may be directed to use byte or AccA saturated (bit 31 overflow and saturation) word-sized operands. Byte operands will direct a 16-bit or result, and word operands will direct a 32-bit result to AccA overflowed into guard bits and saturated the specified register(s) in the W array. (bit 39 overflow and saturation) 4. SB: 2.4.2 DATA ACCUMULATORS AND AccB saturated (bit 31 overflow and saturation) ADDER/SUBTRACTOR or The data accumulator consists of a 40-bit adder/sub- AccB overflowed into guard bits and saturated tractor with automatic sign extension logic. It can select (bit 39 overflow and saturation) one of two accumulators (A or B) as its pre- 5. OAB: accumulation source and post-accumulation destina- Logical OR of OA and OB tion. For the ADD and LAC instructions, the data to be 6. SAB: accumulated or loaded can be optionally scaled via the Logical OR of SA and SB barrel shifter, prior to accumulation. The OA and OB bits are modified each time data passes through the adder/subtractor. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warn- ing trap when set and the corresponding overflow trap flag enable bit (OVATE, OVBTE) in the INTCON1 regis- ter (refer to Section5.0 “Interrupts”) is set. This allows the user to take immediate action, for example, to correct system gain. DS70150E-page 20 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 The SA and SB bits are modified each time data passes 2.4.2.2 Accumulator ‘Write-Back’ through the adder/subtractor, but can only be cleared by The MAC class of instructions (with the exception of the user. When set, they indicate that the accumulator MPY, MPY.N, ED and EDAC) can optionally write a has overflowed its maximum range (bit 31 for 32-bit rounded version of the high word (bits 31 through 16) saturation, or bit 39 for 40-bit saturation) and will be of the accumulator that is not targeted by the instruction saturated if saturation is enabled. When saturation is not into data space memory. The write is performed across enabled, SA and SB default to bit 39 overflow and thus the X bus into combined X and Y address space. The indicate that a catastrophic overflow has occurred. If the following addressing modes are supported: COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when 1. W13, Register Direct: saturation is disabled. The rounded contents of the non-target accumulator are written into W13 as a 1.15 The Overflow and Saturation Status bits can optionally fraction. be viewed in the STATUS register (SR) as the logical 2. [W13]+ = 2, Register Indirect with Post-Increment: OR of OA and OB (in bit OAB) and the logical OR of SA The rounded contents of the non-target accumu- and SB (in bit SAB). This allows programmers to check lator are written into the address pointed to by one bit in the STATUS register to determine if either W13 as a 1.15 fraction. W13 is then accumulator has overflowed, or one bit to determine if incremented by 2 (for a word write). either accumulator has saturated. This would be useful for complex number arithmetic which typically uses 2.4.2.3 Round Logic both the accumulators. The round logic is a combinational block, which per- The device supports three Saturation and Overflow forms a conventional (biased) or convergent (unbiased) modes. round function during an accumulator write (store). The 1. Bit 39 Overflow and Saturation: Round mode is determined by the state of the RND bit When bit 39 overflow and saturation occurs, the in the CORCON register. It generates a 16-bit, 1.15 data saturation logic loads the maximally positive 9.31 value which is passed to the data space write saturation (0x7FFFFFFFFF) or maximally negative 9.31 logic. If rounding is not indicated by the instruction, a value (0x8000000000) into the target accumula- truncated 1.15 data value is stored and the least tor. The SA or SB bit is set and remains set until significant word is simply discarded. cleared by the user. This is referred to as ‘super Conventional rounding takes bit 15 of the accumulator, saturation’ and provides protection against erro- zero-extends it and adds it to the ACCxH word (bits 16 neous data or unexpected algorithm problems through 31 of the accumulator). If the ACCxL word (bits (e.g., gain calculations). 0 through 15 of the accumulator) is between 0x8000 2. Bit 31 Overflow and Saturation: and 0xFFFF (0x8000 included), ACCxH is incre- When bit 31 overflow and saturation occurs, the mented. If ACCxL is between 0x0000 and 0x7FFF, saturation logic then loads the maximally posi- ACCxH is left unchanged. A consequence of this algo- tive 1.31 value (0x007FFFFFFF) or maximally rithm is that over a succession of random rounding negative 1.31 value (0x0080000000) into the operations, the value will tend to be biased slightly target accumulator. The SA or SB bit is set and positive. remains set until cleared by the user. When this Convergent (or unbiased) rounding operates in the Saturation mode is in effect, the guard bits are not same manner as conventional rounding, except when used so the OA, OB or OAB bits are never set. ACCxL equals 0x8000. If this is the case, the LSb 3. Bit 39 Catastrophic Overflow (bit16 of the accumulator) of ACCxH is examined. If it The bit 39 Overflow Status bit from the adder is is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not used to set the SA or SB bit, which remain set modified. Assuming that bit 16 is effectively random in until cleared by the user. No saturation operation nature, this scheme will remove any rounding bias that is performed and the accumulator is allowed to may accumulate. overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic The SAC and SAC.R instructions store either a trun- overflow can initiate a trap exception. cated (SAC) or rounded (SAC.R) version of the contents of the target accumulator to data memory, via the X bus (subject to data saturation, see Section2.4.2.4 “Data Space Write Saturation”). Note that for the MAC class of instructions, the accumulator write-back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. © 2011 Microchip Technology Inc. DS70150E-page 21

dsPIC30F6010A/6015 2.4.2.4 Data Space Write Saturation 2.4.3 BARREL SHIFTER In addition to adder/subtractor saturation, writes to data The barrel shifter is capable of performing up to 16-bit space may also be saturated, but without affecting the arithmetic or logic right shifts, or up to 16-bit left shifts contents of the source accumulator. The data space in a single cycle. The source can be either of the two write saturation logic block accepts a 16-bit, 1.15 DSP accumulators or the X bus (to support multi-bit fractional value from the round logic block as its input, shifts of register or memory data). together with overflow status from the original source The shifter requires a signed binary value to determine (accumulator) and the 16-bit round adder. These are both the magnitude (number of bits) and direction of the combined and used to select the appropriate 1.15 shift operation. A positive value will shift the operand fractional value as output to write to data space right. A negative value will shift the operand left. A memory. value of ‘0’ will not modify the operand. If the SATDW bit in the CORCON register is set, data The barrel shifter is 40 bits wide, thereby obtaining a (after rounding or truncation) is tested for overflow and 40-bit result for DSP shift operations and a 16-bit result adjusted accordingly. For input data greater than for MCU shift operations. Data from the X bus is pre- 0x007FFF, data written to memory is forced to the max- sented to the barrel shifter between bit positions 16 to imum positive 1.15 value, 0x7FFF. For input data less 31 for right shifts, and bit positions 0 to 15 for left shifts. than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The MSb of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. DS70150E-page 22 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 3.0 MEMORY ORGANIZATION FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR Note: This data sheet summarizes features of dsPIC30F6010A/6015 this group ofdsPIC30F devices and is not intended to be a complete reference Reset – GOTO Instruction 000000 source. For more information on the CPU, Reset – Target Address 000002 000004 peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the Vector Tables Interrupt Vector Table device instruction set and programming, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157). 3.1 Program Address Space 00007E Reserved 000080 y or Alternate Vector Table 000084 The program address space is 4M instruction words. It me 0000FE ec iEsf feacdtdivree ssAadbdlere sbsy (tEhAe) , 23o-rb idt aPtaC ,s ptaabclee EinAs,t ruwchtieonn ser MSpa ProUgrsaemr F Mlaesmhory 000100 U (48K instructions) program space is mapped into data space, as defined 017FFE by Table3-1. Note that the program space address is 018000 Reserved incremented by two between successive program (Read ‘0’s) words, in order to provide compatibility with data space 7FEFFE addressing. 7FF000 Data EEPROM User program space access is restricted to the lower (4 Kbytes) 4M instruction word address range (0x000000 to 7FFFFE 800000 0x7FFFFE), for all accesses other than TBLRD/TBLWT, which use TBLPAG<7> to determine user or configura- tion space access. In Table3-1, read/write instructions, bit23 allows access to the device ID, the user ID and the Configuration bits. Otherwise, bit 23 is always clear. Reserved y or m e M 8005BE uration Space UNITID (32 instr.) 88000055FCE0 nfig 800600 o Reserved C F7FFFE Device Configuration F80000 Registers F8000E F80010 Reserved FEFFFE DEVID (2) FF0000 FFFFFE © 2011 Microchip Technology Inc. DS70150E-page 23

dsPIC30F6010A/6015 TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 TBLRD/TBLWT User TBLPAG<7:0> Data EA <15:0> (TBLPAG<7> = 0) TBLRD/TBLWT Configuration TBLPAG<7:0> Data EA <15:0> (TBLPAG<7> = 1) Program Space Visibility User 0 PSVPAG<7:0> Data EA <14:0> FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 23 bits Using Program 0 Program Counter 0 Counter Select 1 EA Using Program 0 PSVPAG Reg Space Visibility 8 bits 15 bits EA Using 1/0 TBLPAG Reg Table Instruction 8 bits 16 bits User/ Byte Configuration 24-bit EA Select Space Select Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory. DS70150E-page 24 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 3.1.1 DATA ACCESS FROM PROGRAM A set of table instructions are provided to move byte or MEMORY USING TABLE word-sized data to and from program space. INSTRUCTIONS 1. TBLRDL: Table Read Low This architecture fetches 24-bit wide program memory. Word: Read the least significant word of the Consequently, instructions are always aligned. How- program address; ever, as the architecture is modified Harvard, data can P<15:0> maps to D<15:0>. also be present in program space. Byte: Read one of the Least Significant Bytes of the program address; There are two methods by which program space can P<7:0> maps to the destination byte when byte be accessed; via special table instructions, or through select = 0; the remapping of a 16K word program space page into P<15:8> maps to the destination byte when byte the upper half of data space (see Section3.1.2 “Data select = 1. Access from Program Memory Using Program 2. TBLWTL: Table Write Low (refer to Section6.0 Space Visibility”). The TBLRDL and TBLWTL instruc- “Flash Program Memory” for details on Flash tions offer a direct method of reading or writing the least Programming). significant word of any address within program space, without going through data space. The TBLRDH and 3. TBLRDH: Table Read High TBLWTH instructions are the only method whereby the Word: Read the most significant word of the upper 8 bits of a program space word can be accessed program address; as data. P<23:16> maps to D<7:0>; D<15:8> always be = 0. The PC is incremented by two for each successive Byte: Read one of the Most Significant Bytes of 24-bit program word. This allows program memory the program address; addresses to directly map to data space addresses. P<23:16> maps to the destination byte when Program memory can thus be regarded as two 16-bit byte select = 0; word-wide address spaces, residing side by side, each The destination byte will always be = 0 when with the same address range. TBLRDL and TBLWTL byte select = 1. access the space which contains the lsw, and TBLRDH 4. TBLWTH: Table Write High (refer to Section6.0 and TBLWTH access the space which contains the “Flash Program Memory” for details on Flash MSB. Programming). Figure3-2 shows how the EA is created for table oper- ations and data space accesses (PSV = 1). Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word. FIGURE 3-3: PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD) PC Address 23 16 8 0 0x000000 00000000 0x000002 00000000 0x000004 00000000 0x000006 00000000 TBLRDL.B (Wn<0> = 0) TBLRDL.W Program Memory ‘Phantom’ Byte TBLRDL.B (Wn<0> = 1) (Read as ‘0’) © 2011 Microchip Technology Inc. DS70150E-page 25

dsPIC30F6010A/6015 FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE) TBLRDH.W PC Address 23 16 8 0 0x000000 00000000 0x000002 00000000 0x000004 00000000 0x000006 00000000 TBLRDH.B (Wn<0> = 0) Program Memory ‘Phantom’ Byte (Read as ‘0’) TBLRDH.B (Wn<0> = 1) 3.1.2 DATA ACCESS FROM PROGRAM Note that by incrementing the PC by 2 for each MEMORY USING PROGRAM SPACE program memory word, the Least Significant 15 bits of VISIBILITY data space addresses directly map to the Least Signif- icant 15 bits in the corresponding program space The upper 32 Kbytes of data space may optionally be addresses. The remaining bits are provided by the mapped into any 16K word program space page. This Program Space Visibility Page register, PSVPAG<7:0>, provides transparent access of stored constant data as shown in Figure3-5. from X data space, without the need to use special instructions (i.e., TBLRDL/H, TBLWTL/H instructions). Note: PSV access is temporarily disabled during table reads/writes. Program space access through the data space occurs if the MSb of the data space EA is set and program For instructions that use PSV which are executed space visibility is enabled, by setting the PSV bit in the outside a REPEAT loop: Core Control register (CORCON). The functions of • The following instructions will require one instruc- CORCON are discussed in Section2.4 “DSP tion cycle in addition to the specified execution Engine”. time: Data accesses to this area add an additional cycle to - MAC class of instructions with data operand the instruction being executed, since two program prefetch memory fetches are required. - MOV instructions Note that the upper half of addressable data space is - MOV.D instructions always part of the X data space. Therefore, when a • All other instructions will require two instruction DSP operation uses program space mapping to access cycles in addition to the specified execution time this memory region, Y data space should typically con- of the instruction. tain state (variable) data for DSP operations, whereas X data space should typically contain coefficient For instructions that use PSV which are executed (constant) data. inside a REPEAT loop: Although each data space address, 0x8000 and higher, • The following instances will require two instruction maps directly into a corresponding program memory cycles in addition to the specified execution time address (see Figure3-5), only the lower 16 bits of the of the instruction: 24-bit program word are used to contain the data. The - Execution in the first iteration upper 8 bits should be programmed to force an illegal - Execution in the last iteration instruction to maintain machine robustness. Refer - Execution prior to exiting the loop due to an tothe “16-bit MCU and DSC Programmer’s Reference interrupt Manual” (DS70157) for details on instruction encoding. - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction, accessing data using PSV, to execute in a single cycle. DS70150E-page 26 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space Program Space 0x0000 0x000100 15 PSVPAG(1) EA<15> = 0 0x00 8 Data 16 Space 0x8000 EA 15 23 15 0 Address EA<15> = 1 0x001200 15 Concatenation 23 Upper half of Data Space is mapped into Program Space 0xFFFF 0x017FFE BSET CORCON,#2 ; PSV bit set MOV #0x00, W0 ; Set PSVPAG register MOV W0, PSVPAG MOV 0x9200, W0 ; Access program memory location ; using a data space access Data Read Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines the page in program space to which the upper half of data space is being mapped). 3.2 Data Address Space When executing any instruction other than one of the MAC class of instructions, the X block consists of the The core has two data spaces. The data spaces can be 64Kbyte data address space (including all Y considered either separate (for some DSP instruc- addresses). When executing one of the MAC class of tions), or as one unified linear address range (for MCU instructions, the X block consists of the 64 Kbyte data instructions). The data spaces are accessed using two address space excluding the Y address block (for data Address Generation Units (AGUs) and separate data reads only). In other words, all other instructions regard paths. the entire data memory as one composite address space. The MAC class instructions extract the Y 3.2.1 DATA SPACE MEMORY MAP address space from data space and address it using The data space memory is split into two blocks, X and EAs sourced from W10 and W11. The remaining X data Y data space. A key element of this architecture is that space is addressed using W8 and W9. Both address Y space is a subset of X space, and is fully contained spaces are concurrently accessed only with the MAC within X space. In order to provide an apparent Linear class instructions. Addressing space, X and Y spaces have contiguous A data space memory map is shown in Figure3-6. addresses. Figure3-7 shows a graphical summary of how X and Y data spaces are accessed for MCU and DSP instructions. © 2011 Microchip Technology Inc. DS70150E-page 27

dsPIC30F6010A/6015 FIGURE 3-6: dsPIC30F6010A/6015 DATA SPACE MEMORY MAP Least Significant Byte Most Significant Byte 16 bits Address Address MSB LSB 0x0001 0x0000 2 Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 8 Kbyte Near X Data RAM (X) Data Space 8 Kbyte 0x17FF 0x17FE SRAM Space 0x1801 0x1800 0x1FFF 0x1FFE Y Data RAM (Y) 0x27FF 0x27FE 0x2801 0x2800 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE DS70150E-page 28 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE SFR SPACE E C UNUSED A P S X (Y SPACE) Y SPACE UNUSED E C A P S X E C UNUSED A P S X Non-MAC Class Ops (Read/Write) MAC Class Ops Read-Only MAC Class Ops (Write) Indirect EA using any W Indirect EA using W10, W11Indirect EA using W8, W9 © 2011 Microchip Technology Inc. DS70150E-page 29

dsPIC30F6010A/6015 3.2.2 DATA SPACES 3.2.3 DATA SPACE WIDTH The X data space is used by all instructions and sup- The core data width is 16 bits. All internal registers are ports all addressing modes. There are separate read organized as 16-bit wide words. Data space memory is and write data buses. The X read data bus is the return organized in byte addressable, 16-bit wide blocks. data path for all instructions that view data space as combined X and Y address space. It is also the X 3.2.4 DATA ALIGNMENT address space data path for the dual operand read To help maintain backward compatibility with PIC® instructions (MAC class). The X write data bus is the devices and improve data space memory usage effi- only write path to data space for all instructions. ciency, the dsPIC30F instruction set supports both The X data space also supports Modulo Addressing for word and byte operations. Data is aligned in data mem- all instructions, subject to addressing mode restric- ory and registers as words, but all data space EAs tions. Bit-Reversed Addressing is only supported for resolve to bytes. Data byte reads will read the complete writes to X data space. word, which contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is The Y data space is used in concert with the X data placed onto the LSB of the X data path (no byte space by the MAC class of instructions (CLR, ED, EDAC, accesses are possible from the Y data path as the MAC MAC, MOVSAC, MPY, MPY.N and MSC) to provide two class of instruction can only fetch words). That is, data concurrent data read paths. No writes occur across the memory and registers are organized as two parallel Y bus. This class of instructions dedicates two W reg- byte wide entities with shared (word) address decode, ister pointers, W10 and W11, to always address Y data but separate write lines. Data byte writes only write to space, independent of X data space, whereas W8 and the corresponding side of the array or register which W9 always address X data space. Note that during matches the byte address. accumulator write-back, the data address space is con- sidered a combination of X and Y data spaces, so the As a consequence of this byte accessibility, all Effective write occurs across the X bus. Consequently, the write Address calculations (including those generated by the can be to any address in the entire data space. DSP operations, which are restricted to word-sized data) are internally scaled to step through word-aligned The Y data space can only be used for the data memory. For example, the core would recognize that prefetch operation associated with the MAC class of Post-Modified Register Indirect Addressing mode, instructions. It also supports Modulo Addressing for [Ws++], will result in a value of Ws + 1 for byte automated circular buffers. Of course, all other instruc- operations and Ws + 2 for word operations. tions can access the Y data address space through the X data path, as part of the composite linear space. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so The boundary between the X and Y data spaces is care must be taken when mixing byte and word opera- defined as shown in Figure3-6 and is not user pro- tions, or translating from 8-bit MCU code. Should a grammable. Should an EA point to data outside its own misaligned read or write be attempted, an address assigned address space, or to a location outside phys- error trap will be generated. If the error occurred on a ical memory, an all-zero word/byte will be returned. For read, the instruction underway is completed, whereas if example, although Y address space is visible by all it occurred on a write, the instruction will be executed non-MAC instructions using any addressing mode, an but the write will not occur. In either case, a trap will attempt by a MAC instruction to fetch data from that then be executed, allowing the system and/or user to space, using W8 or W9 (X space pointers), will return examine the machine state prior to execution of the 0x0000. address Fault. TABLE 3-2: EFFECT OF INVALID FIGURE 3-8: DATA ALIGNMENT MEMORY ACCESSES Attempted Operation Data Returned MSB LSB 15 8 7 0 EA = an unimplemented address 0x0000 0001 Byte 1 Byte 0 0000 W8 or W9 used to access Y data 0x0000 0003 Byte 3 Byte 2 0002 space in a MAC instruction W10 or W11 used to access X 0x0000 0005 Byte 5 Byte 4 0004 data space in a MAC instruction All Effective Addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes or 32K words. DS70150E-page 30 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 All byte loads into any W register are loaded into the Similarly, a Stack Pointer underflow (stack error) trap is LSB. The MSB is not modified. generated when the Stack Pointer address is found to be less than 0x0800, thus preventing the stack from A sign-extend (SE) instruction is provided to allow interfering with the Special Function Register (SFR) users to translate 8-bit signed data to 16-bit signed space. values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a A write to the SPLIM register should not be immediately zero-extend (ZE) instruction on the appropriate followed by an indirect read operation using W15. address. Although most instructions are capable of operating on FIGURE 3-9: CALL STACK FRAME word or byte data sizes, it should be noted that some instructions, including the DSP instructions, operate 0x0000 15 0 only on words. 3.2.5 NEAR DATA SPACE ds An 8 Kbyte ‘near’ data space is reserved in X address Towardress mdireemctolyry a sdpdarecses baebtlwe eveian a0 x1030-b0i0t aabnsdo l0uxte1 FaFdFd,r ewshsi cfhie lids ows er Ad PC<15:0> W15 (before CALL) within all memory direct instructions. The remaining X ck GrHigh 0000<0F0re0e0 0W PoCrd<>22:16> W15 (after CALL) address space and all of the Y address space is a St addressable indirectly. Additionally, the whole of X data space is addressable using MOV instructions, which POP: [--W15] PUSH: [W15++] support memory direct addressing with a 16-bit address field. 3.2.6 SOFTWARE STACK 3.2.7 DATA RAM PROTECTION FEATURE The dsPIC DSC device contains a software stack. W15 The dsPIC30F6010A/6015 devices support Data RAM is used as the Stack Pointer. protection features which enable segments of RAM to be protected when used in conjunction with Boot and The Stack Pointer always points to the first available Secure Code Segment Security. BSRAM (Secure RAM free word and grows from lower addresses towards segment for BS) is accessible only from the Boot Seg- higher addresses. It pre-decrements for stack pops and ment Flash code when enabled. SSRAM (Secure RAM post-increments for stack pushes, as shown in segment for RAM) is accessible only from the Secure Figure3-9. Note that for a PC push during any CALL Segment Flash code when enabled. instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. See Table3-3 for an overview of the BSRAM and SSRAM SFRs. Note: A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to ‘0’, because all stack operations must be word-aligned. Whenever an Effective Address (EA) is generated using W15 as a source or destination pointer, the address thus generated is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value, 0x1FFE. © 2011 Microchip Technology Inc. DS70150E-page 31

D TABLE 3-3: CORE REGISTER MAP(1) d S 701 SFR Name Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 5 (Home) P 0 E -p W0 0000 W0 / WREG 0000 0000 0000 0000 I a C ge W1 0002 W1 0000 0000 0000 0000 32 W2 0004 W2 0000 0000 0000 0000 3 W3 0006 W3 0000 0000 0000 0000 0 W4 0008 W4 0000 0000 0000 0000 F W5 000A W5 0000 0000 0000 0000 6 W6 000C W6 0000 0000 0000 0000 0 W7 000E W7 0000 0000 0000 0000 1 W8 0010 W8 0000 0000 0000 0000 0 W9 0012 W9 0000 0000 0000 0000 A W10 0014 W10 0000 0000 0000 0000 / W11 0016 W11 0000 0000 0000 0000 6 W12 0018 W12 0000 0000 0000 0000 0 W13 001A W13 0000 0000 0000 0000 1 W14 001C W14 0000 0000 0000 0000 5 W15 001E W15 0000 1000 0000 0000 SPLIM 0020 SPLIM 0000 0000 0000 0000 ACCAL 0022 ACCAL 0000 0000 0000 0000 ACCAH 0024 ACCAH 0000 0000 0000 0000 ACCAU 0026 Sign Extension (ACCA<39>) ACCAU 0000 0000 0000 0000 ACCBL 0028 ACCBL 0000 0000 0000 0000 ACCBH 002A ACCBH 0000 0000 0000 0000 ACCBU 002C Sign Extension (ACCB<39>) ACCBU 0000 0000 0000 0000 PCL 002E PCL 0000 0000 0000 0000 PCH 0030 — — — — — — — — — PCH 0000 0000 0000 0000 TBLPAG 0032 — — — — — — — — TBLPAG 0000 0000 0000 0000 © 2 PSVPAG 0034 — — — — — — — — PSVPAG 0000 0000 0000 0000 0 1 RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu 1 M DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu ic ro DOSTARTL 003A DOSTARTL 0 uuuu uuuu uuuu uuu0 c h DOSTARTH 003C — — — — — — — — — DOSTARTH 0000 0000 0uuu uuuu ip T DOENDL 003E DOENDL 0 uuuu uuuu uuuu uuu0 e c h DOENDH 0040 — — — — — — — — — DOENDH 0000 0000 0uuu uuuu n olo Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ g Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. y In c .

© TABLE 3-3: CORE REGISTER MAP(1) (CONTINUED) 2 011 SFR Name A(Hdodmrees)s Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State M ic SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000 ro ch CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000 ip T MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000 e c XMODSRT 0048 XS<15:1> 0 uuuu uuuu uuuu uuu0 h n o XMODEND 004A XE<15:1> 1 uuuu uuuu uuuu uuu1 lo g YMODSRT 004C YS<15:1> 0 uuuu uuuu uuuu uuu0 y In YMODEND 004E YE<15:1> 1 uuuu uuuu uuuu uuu1 c . XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu DISICNT 0052 — — DISICNT<13:0> 0000 0000 0000 0000 BSRAM 0750 — — — — — — — — — — — — — IW_BSR IR_BSR RL_BSR 0000 0000 0000 0000 SSRAM 0752 — — — — — — — — — — — — — IW_SSR IR_SSR RL_SSR 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. d s P I C 3 0 F 6 0 1 0 D A S 7 0 / 15 6 0 E 0 -p a 1 g e 3 5 3

dsPIC30F6010A/6015 NOTES: DS70150E-page 34 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 4.0 ADDRESS GENERATOR UNITS 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field Note: This data sheet summarizes features of (f) to directly address data present in the first this group ofdsPIC30F devices and is not 8192bytes of data memory (near data space). Most file intended to be a complete reference register instructions employ a working register W0, source. For more information on the CPU, which is denoted as WREG in these instructions. The peripherals, register descriptions and destination is typically either the same file register, or general device functionality, refer to the WREG (with the exception of the MUL instruction), “dsPIC30F Family Reference Manual” which writes the result to a register or register pair. The (DS70046). For more information on the MOV instruction allows additional flexibility and can device instruction set and programming, access the entire data space during file register refer to the “16-bit MCU and DSC operation. Programmer’s Reference Manual” (DS70157). 4.1.2 MCU INSTRUCTIONS The dsPIC DSC core contains two independent The three-operand MCU instructions are of the form: Address Generator Units (AGU): the X AGU and Y Operand 3 = Operand 1 <function> Operand 2 AGU. The Y AGU supports word-sized data reads for the DSP MAC class of instructions only. The dsPIC DSC where Operand 1 is always a working register (i.e., the AGUs support three types of data addressing: addressing mode can only be Register Direct), which is referred to as Wb. Operand 2 can be a W register, • Linear Addressing fetched from data memory, or a 5-bit literal. The result • Modulo (Circular) Addressing location can be either a W register or an address • Bit-Reversed Addressing location. The following addressing modes are supported by MCU instructions: Linear and Modulo Data Addressing modes can be applied to data space or program space. Bit-Reversed • Register Direct Addressing mode is only applicable to data space • Register Indirect addresses. • Register Indirect Post-Modified • Register Indirect Pre-Modified 4.1 Instruction Addressing Modes • 5-bit or 10-bit Literal The addressing modes in Table4-1 form the basis of Note: Not all instructions support all the the addressing modes optimized to support the specific addressing modes given above. Individual features of individual instructions. The addressing instructions may support different subsets modes provided in the MAC class of instructions are of these addressing modes. somewhat different from those in the other instruction types. TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the EA. Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. © 2011 Microchip Technology Inc. DS70150E-page 35

dsPIC30F6010A/6015 4.1.3 MOVE AND ACCUMULATOR In summary, the following addressing modes are INSTRUCTIONS supported by the MAC class of instructions: Move instructions and the DSP Accumulator class of • Register Indirect instructions provide a greater degree of addressing • Register Indirect Post-Modified by 2 flexibility than other instructions. In addition to the • Register Indirect Post-Modified by 4 addressing modes supported by most MCU instruc- • Register Indirect Post-Modified by 6 tions, Move and Accumulator instructions also support • Register Indirect with Register Offset (Indexed) Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. 4.1.5 OTHER INSTRUCTIONS Note: For the MOV instructions, the addressing Besides the various addressing modes outlined above, mode specified in the instruction can differ some instructions use literal constants of various sizes. for the source and destination EA. How- For example, BRA (branch) instructions use 16-bit ever, the 4-bit Wb (Register Offset) field is signed literals to specify the branch destination directly, shared between both source and whereas the DISI instruction uses a 14-bit unsigned destination (but typically only used by literal field. In some instructions, such as ADD Acc, the one). source of an operand or result is implied by the opcode In summary, the following addressing modes are itself. Certain operations, such as NOP, do not have any operands. supported by Move and Accumulator instructions: • Register Direct 4.2 Modulo Addressing • Register Indirect • Register Indirect Post-Modified Modulo Addressing is a method of providing an automated means to support circular data buffers using • Register Indirect Pre-Modified hardware. The objective is to remove the need for • Register Indirect with Register Offset (Indexed) software to perform data address boundary checks • Register Indirect with Literal Offset when executing tightly looped code, as is typical in • 8-bit Literal many DSP algorithms. • 16-bit Literal Modulo Addressing can operate in either data or Note: Not all instructions support all the program space (since the data pointer mechanism is addressing modes given above. Individual essentially the same for both). One circular buffer can be instructions may support different subsets supported in each of the X (which also provides the of these addressing modes. pointers into program space) and Y data spaces. Modulo Addressing can operate on any W register pointer. 4.1.4 MAC INSTRUCTIONS However, it is not advisable to use W14 or W15 for Modulo Addressing, since these two registers are used The dual source operand DSP instructions (CLR, ED, as the Stack Frame Pointer and Stack Pointer, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also respectively. referred to as MAC instructions, utilize a simplified set of addressing modes to allow the user to effectively In general, any particular circular buffer can only be manipulate the data pointers through Register Indirect configured to operate in one direction, as there are tables. certain restrictions on the buffer start address (for incrementing buffers) or end address (for decrementing The two source operand prefetch registers must be a buffers) based upon the direction of the buffer. member of the set {W8, W9, W10, W11}. For data reads, W8 and W9 will always be directed to the X RAGU and The only exception to the usage restrictions is for W10 and W11 will always be directed to the Y AGU. The buffers which have a power-of-2 length. As these Effective Addresses generated (before and after modifi- buffers satisfy the start and end address criteria, they cation) must, therefore, be valid addresses within X data may operate in a Bidirectional mode, (i.e., address space for W8 and W9 and Y data space for W10 and boundary checks will be performed on both the lower W11. and upper address boundaries). Note: Register Indirect with Register Offset Addressing is only available for W9 (in X space) and W11 (in Y space). DS70150E-page 36 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 4.2.1 START AND END ADDRESS 4.2.2 W ADDRESS REGISTER SELECTION The Modulo Addressing scheme requires that a startingand an ending address be specified and The Modulo and Bit-Reversed Addressing Control loaded into the 16-bit Modulo Buffer Address registers: register, MODCON<15:0>, contains enable flags, as XMODSRT, XMODEND, YMODSRT and YMODEND well as a W register field to specify the W Address (see Table 3-3). registers. The XWM and YWM fields select which registers will operate with Modulo Addressing. If Note: Y space Modulo Addressing EA calcula- XWM= 15, X RAGU and X WAGU Modulo Addressing tions assume word-sized data (LSb of are disabled. Similarly, if YWM = 15, Y AGU Modulo every EA is always clear). Addressing is disabled. The length of a circular buffer is not directly specified. It The X Address Space Pointer W register (XWM) to is determined by the difference between the which Modulo Addressing is to be applied, is stored in corresponding start and end addresses. The maximum MODCON<3:0> (see Table 3-3). Modulo Addressing is possible length of the circular buffer is 32K words enabled for X data space when XWM is set to any value (64Kbytes). other than 15 and the XMODEN bit is set at MODCON<15>. The Y Address Space Pointer W register (YWM) to which Modulo Addressing is to be applied, is stored in MODCON<7:4>. Modulo Addressing is enabled for Y data space when YWM is set to any value other than 15 and the YMODEN bit is set at MODCON<14>. FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE Byte Address MOV #0x1100,W0 MOV W0, XMODSRT ;set modulo start address MOV #0x1163,W0 MOV W0,MODEND ;set modulo end address 0x1100 MOV #0x8001,W0 MOV W0,MODCON ;enable W1, X AGU for modulo MOV #0x0000,W0 ;W0 holds buffer fill value MOV #0x1110,W1 ;point W1 to buffer DO AGAIN,#0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0,W0 ;increment the fill value 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2011 Microchip Technology Inc. DS70150E-page 37

dsPIC30F6010A/6015 4.2.3 MODULO ADDRESSING If the length of a Bit-Reversed buffer is M = 2N bytes, APPLICABILITY then the last ‘N’ bits of the data buffer start address must be zeros. Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W XB<14:0> is the Bit-Reversed Address modifier or register. It is important to realize that the address ‘pivot point’ which is typically a constant. In the case of boundaries check for addresses less than or greater an FFT computation, its value is equal to half of the FFT than the upper (for incrementing buffers) and lower (for data buffer size. decrementing buffers) boundary addresses (not just Note: All Bit-Reversed EA calculations assume equal to). Address changes may, therefore, jump word-sized data (LSb of every EA is beyond boundaries and still be adjusted correctly. always clear). The XB value is scaled Note: The modulo corrected Effective Address accordingly to generate compatible (byte) is written back to the register only when addresses. Pre-Modify or Post-Modify Addressing When enabled, Bit-Reversed Addressing will only be mode is used to compute the Effective executed for Register Indirect with Pre-Increment or Address. When an address offset (e.g., Post-Increment Addressing and word-sized data writes. [W7+W2]) is used, Modulo Address cor- It will not function for any other addressing mode or for rection is performed, but the contents of byte-sized data, and normal addresses will be generated the register remains unchanged. instead. When Bit-Reversed Addressing is active, the W Address Pointer will always be added to the address 4.3 Bit-Reversed Addressing modifier (XB) and the offset associated with the Register Indirect Addressing mode will be ignored. In addition, as Bit-Reversed Addressing is intended to simplify data word-sized data is a requirement, the LSb of the EA is re-ordering for radix-2 FFT algorithms. It is supported ignored (and always clear). by the X AGU for data writes only. Note: Modulo Addressing and Bit-Reversed The modifier, which may be a constant value or register Addressing should not be enabled contents, is regarded as having its bit order reversed. together. In the event that the user The address source and destination are kept in normal attempts to do this, Bit-Reversed order. Thus, the only operand requiring reversal is the Addressing will assume priority when modifier. active for the X WAGU, and X WAGU 4.3.1 BIT-REVERSED ADDRESSING Modulo Addressing will be disabled. How- ever, Modulo Addressing will continue to IMPLEMENTATION function in the X RAGU. Bit-Reversed Addressing is enabled when: If Bit-Reversed Addressing has already been enabled 1. BWM (W register selection) in the MODCON reg- by setting the BREN (XBREV<15>) bit, then a write to ister is any value other than 15 (the stack cannot the XBREV register should not be immediately followed be accessed using Bit-Reversed Addressing) by an indirect read operation using the W register that and has been designated as the Bit-Reversed Pointer. 2. the BREN bit is set in the XBREV register and 3. the addressing mode used is Register Indirect with Pre-Increment or Post-Increment. FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer DS70150E-page 38 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value 4096 0x0800 2048 0x0400 1024 0x0200 512 0x0100 256 0x0080 128 0x0040 64 0x0020 32 0x0010 16 0x0008 8 0x0004 4 0x0002 2 0x0001 © 2011 Microchip Technology Inc. DS70150E-page 39

dsPIC30F6010A/6015 NOTES: DS70150E-page 40 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 5.0 INTERRUPTS • INTTREG<15:0> The associated interrupt vector number and the Note: This data sheet summarizes features of new CPU interrupt priority level are latched into this group ofdsPIC30F devices and is not Vector number (VECNUM<5:0>) and Interrupt intended to be a complete reference level ILR<3:0> bit fields in the INTTREG register. source. For more information on the CPU, The new interrupt priority level is the priority of the peripherals, register descriptions and pending interrupt. general device functionality, refer to the Note: Interrupt flag bits get set when an interrupt “dsPIC30F Family Reference Manual” condition occurs, regardless of the state of (DS70046). For more information on the its corresponding enable bit. User soft- device instruction set and programming, ware should ensure the appropriate inter- refer to the “16-bit MCU and DSC rupt flag bits are clear prior to enabling an Programmer’s Reference Manual” interrupt. (DS70157). All interrupt sources can be user assigned to one of The dsPIC30F6010A/6015 has 44 interrupt sources seven priority levels, 1 through 7, via the IPCx and four processor exceptions (traps), which must be registers. Each interrupt source is associated with an arbitrated based on a priority scheme. interrupt vector, as shown in Table5-1. Levels 7 and 1 The CPU is responsible for reading the Interrupt represent the highest and lowest maskable priorities, Vector Table (IVT) and transferring the address con- respectively. tained in the interrupt vector to the program counter. The interrupt vector is transferred from the program Note: Assigning a priority level of 0 to an inter- data bus into the program counter, via a 24-bit wide rupt source is equivalent to disabling that multiplexer on the input of the program counter. interrupt. The Interrupt Vector Table (IVT) and Alternate Inter- If the NSTDIS bit (INTCON1<15>) is set, nesting of rupt Vector Table (AIVT) are placed near the beginning interrupts is prevented. Thus, if an interrupt is currently of program memory (0x000004). The IVT and AIVT being serviced, processing of a new interrupt is pre- are shown in Figure5-1. vented, even if the new interrupt is of higher priority The interrupt controller is responsible for pre- than the one currently being serviced. processing the interrupts and processor exceptions, Note: The IPL bits become read-only whenever prior to their being presented to the processor core. the NSTDIS bit has been set to ‘1’. The peripheral interrupts and traps are enabled, prioritized and controlled using centralized Special Certain interrupts have specialized control bits for Function Registers: features like edge or level triggered interrupts, inter- • IFS0<15:0>, IFS1<15:0>, IFS2<15:0> rupt-on-change, etc. Control of these features remains All Interrupt Request Flags are maintained in these within the peripheral module which generates the three registers. The flags are set by their respective interrupt. peripherals or external signals, and they are cleared The DISI instruction can be used to disable the via software. processing of interrupts of priorities 6 and lower for a • IEC0<15:0>, IEC1<15:0>, IEC2<15:0> certain number of instructions, during which the DISI bit All Interrupt Enable Control bits are maintained in (INTCON2<14>) remains set. these three registers. These control bits are used to When an interrupt is serviced, the PC is loaded with the individually enable interrupts from the peripherals or address stored in the vector location in program external signals. memory that corresponds to the interrupt. There are 63 • IPC0<15:0>... IPC11<7:0> different vectors within the IVT (refer to Figure5-2). The user assignable priority level associated with These vectors are contained in locations 0x000004 each of these 44 interrupts is held centrally in these through 0x0000FE of program memory (refer to twelve registers. Figure5-2). These locations contain 24-bit addresses, • IPL<3:0> and in order to preserve robustness, an address error The current CPU priority level is explicitly stored in trap will take place should the PC attempt to fetch any the IPL bits. IPL<3> is present in the CORCON reg- of these words during normal execution. This prevents ister, whereas IPL<2:0> are present in the STATUS execution of random data as a result of accidentally register (SR) in the processor core. decrementing a PC into vector space, accidentally • INTCON1<15:0>, INTCON2<15:0> mapping a data space address into vector space, or the Global interrupt control functions are derived from PC rolling over to 0x000000 after reaching the end of these two registers. INTCON1 contains the control implemented program memory space. Execution of a and status flags for the processor exceptions. The GOTO instruction to this vector space will also generate INTCON2 register controls the external interrupt an address error trap. request signal behavior and the use of the alternate vector table. © 2011 Microchip Technology Inc. DS70150E-page 41

dsPIC30F6010A/6015 5.1 Interrupt Priority TABLE 5-1: INTERRUPT VECTOR TABLE The user-assignable Interrupt Priority bits (IP<2:0>) INT Vector Interrupt Source for each individual interrupt source are located in the Number Number Least Significant 3 bits of each nibble within the IPCx Highest Natural Order Priority register(s). Bit 3 of each nibble is not used and is read 0 8 INT0 – External Interrupt 0 as a ‘0’. These bits define the priority level assigned 1 9 IC1 – Input Capture 1 to a particular interrupt by the user. 2 10 OC1 – Output Compare 1 Note: The user-assignable priority levels start at 3 11 T1 – Timer1 0, as the lowest priority and level 7, as the 4 12 IC2 – Input Capture 2 highest priority. 5 13 OC2 – Output Compare 2 Since more than one interrupt request source may be 6 14 T2 – Timer2 assigned to a specific user-assigned priority level, a 7 15 T3 – Timer3 means is provided to assign priority within a given level. 8 16 SPI1 This method is called “Natural Order Priority”. 9 17 U1RX – UART1 Receiver Natural Order Priority is determined by the position of 10 18 U1TX – UART1 Transmitter an interrupt in the vector table, and only affects 11 19 ADC – ADC Convert Done interrupt operation when multiple interrupts with the 12 20 NVM - NVM Write Complete same user-assigned priority become pending at the 13 21 SI2C – I2C™ Slave Interrupt same time. 14 22 MI2C – I2C Master Interrupt Table5-1 lists the interrupt numbers and interrupt 15 23 Input Change Interrupt sources for the dsPIC DSC devices and their associated 16 24 INT1 – External Interrupt 1 vector numbers. 17 25 IC7 – Input Capture 7 Note1: The Natural Order Priority scheme has 0 18 26 IC8 – Input Capture 8 as the highest priority and 53 as the 19 27 OC3 – Output Compare 3 lowest priority. 20 28 OC4 – Output Compare 4 2: The Natural Order Priority number is the 21 29 T4 – Timer4 same as the INT number. 22 30 T5 – Timer5 The ability for the user to assign every interrupt to one 23 31 INT2 – External Interrupt 2 of seven priority levels means that the user can assign 24 32 U2RX – UART2 Receiver a very high overall priority level to an interrupt with a 25 33 U2TX – UART2 Transmitter low natural order priority. 26 34 SPI2 27 35 C1 – Combined IRQ for CAN1 28 36 IC3 – Input Capture 3 29 37 IC4 – Input Capture 4 30 38 IC5 – Input Capture 5 31 39 IC6 – Input Capture 6 32 40 OC5 – Output Compare 5 33 41 OC6 – Output Compare 6 34 42 OC7 – Output Compare 7 35 43 OC8 – Output Compare 8 36 44 INT3 – External Interrupt 3 37 45 INT4 - External Interrupt 4 38 46 C2 – Combined IRQ for CAN2 39 47 PWM – PWM Period Match 40 48 QEI – QEI Interrupt 41 49 Reserved 42 50 Reserved 43 51 FLTA – PWM Fault A 44 52 FLTB – PWM Fault B 45-53 53-61 Reserved Lowest Natural Order Priority DS70150E-page 42 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 5.2 Reset Sequence 5.3 Traps A Reset is not a true exception because the interrupt Traps can be considered as non-maskable interrupts controller is not involved in the Reset process. The pro- indicating a software or hardware error, which adhere cessor initializes its registers in response to a Reset to a predefined priority, as shown in Figure5-1. They which forces the PC to zero. The processor then begins are intended to provide the user a means to correct program execution at location 0x000000. A GOTO erroneous operation during debug and when operating instruction is stored in the first program memory loca- within the application. tion, immediately followed by the address target for the Note: If the user does not intend to take correc- GOTO instruction. The processor executes the GOTO to tive action in the event of a trap error the specified address and then begins operation at the condition, these vectors must be loaded specified target (start) address. with the address of a default handler that 5.2.1 RESET SOURCES simply contains the RESET instruction. If, on the other hand, one of the vectors There are 6 sources of error which will cause a device containing an invalid address is called, an Reset. address error trap is generated. • Watchdog Time-out: Note that many of these trap conditions can only be The watchdog has timed out, indicating that the detected when they occur. Consequently, the question- processor is no longer executing the correct flow able instruction is allowed to complete prior to trap of code. exception processing. If the user chooses to recover • Uninitialized W Register Trap: from the error, the result of the erroneous action that An attempt to use an uninitialized W register as caused the trap may have to be corrected. an Address Pointer will cause a Reset. There are 8 fixed priority levels for traps: Level 8 • Illegal Instruction Trap: through Level 15, which means that IPL3 is always set Attempted execution of any unused opcodes will during processing of a trap. result in an illegal instruction trap. Note that a fetch of an illegal instruction does not result in an If the user is not currently executing a trap, and he sets illegal instruction trap if that instruction is flushed the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all prior to execution due to a flow change. interrupts are disabled, but traps can still be processed. • Brown-out Reset (BOR): 5.3.1 TRAP SOURCES A momentary dip in the power supply to the device has been detected which may result in The following traps are provided with increasing prior- malfunction. ity. However, since all traps can be nested, priority has little effect. • Trap Lockout: Occurrence of multiple trap conditions Math Error Trap: simultaneously will cause a Reset. The math error trap executes under the following four circumstances: 1. Should an attempt be made to divide by zero, the divide operation will be aborted on a cycle boundary and the trap taken. 2. If enabled, a math error trap will be taken when an arithmetic operation on either Accumulator A or B causes an overflow from bit 31 and the Accumulator Guard bits are not utilized. 3. If enabled, a math error trap will be taken when an arithmetic operation on either Accumulator A or B causes a catastrophic overflow from bit 39 and all saturation is disabled. 4. If the shift amount specified in a shift instruction is greater than the maximum allowed shift amount, a trap will occur. © 2011 Microchip Technology Inc. DS70150E-page 43

dsPIC30F6010A/6015 Address Error Trap: 5.3.2 HARD AND SOFT TRAPS This trap is initiated when any of the following It is possible that multiple traps can become active circumstances occurs: within the same cycle (e.g., a misaligned word stack write to an overflowed address). In such a case, the 1. A misaligned data word access is attempted. fixed priority shown in Figure5-2 is implemented, 2. A data fetch from our unimplemented data which may require the user to check if other traps are memory location is attempted. pending in order to completely correct the Fault. 3. A data access of an unimplemented program ‘Soft’ traps include exceptions of priority level 8 through memory location is attempted. level 11, inclusive. The arithmetic error trap (level 11) 4. An instruction fetch from vector space is falls into this category of traps. attempted. ‘Hard’ traps include exceptions of priority level 12 Note: In the MAC class of instructions, wherein through level 15, inclusive. The address error (level the data space is split into X and Y data 12), stack error (level 13) and oscillator error (level 14) space, unimplemented X space includes traps fall into this category. all of Y space, and unimplemented Y space includes all of X space. Each hard trap that occurs must be Acknowledged before code execution of any type may continue. If a 5. Execution of a “BRA #literal” instruction or a lower priority hard trap occurs while a higher priority “GOTO #literal” instruction, where literal trap is pending, Acknowledged, or is being processed, is an unimplemented program memory address. a hard trap conflict will occur. 6. Executing instructions after modifying the PC to The device is automatically reset in a hard trap conflict point to unimplemented program memory condition. The TRAPR Status bit (RCON<15>) is set addresses. The PC may be modified by loading when the Reset occurs, so that the condition may be a value into the stack and executing a RETURN detected in software. instruction. FIGURE 5-1: TRAP VECTORS Stack Error Trap: This trap is initiated under the following conditions: Reset – GOTO Instruction 0x000000 1. The Stack Pointer is loaded with a value which Reset – GOTO Address 0x000002 is greater than the (user programmable) limit Reserved 0x000004 value written into the SPLIM register (stack Oscillator Fail Trap Vector overflow). Address Error Trap Vector Stack Error Trap Vector 2. The Stack Pointer is loaded with a value which g Math Error Trap Vector Osciisll aletosrs Fthaainl T0rxa0p8:00 (simple stack underflow). DecreasinPriority IVT RRReeessseeerrrvvveeeddd VVVeeeccctttooorrr Interrupt 0 Vector 0x000014 This trap is initiated if the external oscillator fails and Interrupt 1 Vector operation becomes reliant on an internal RC backup. Interrupt 52 Vector Interrupt 53 Vector 0x00007E Reserved 0x000080 Reserved 0x000082 Reserved 0x000084 Oscillator Fail Trap Vector Stack Error Trap Vector Address Error Trap Vector Math Error Trap Vector AIVT Reserved Vector Reserved Vector Reserved Vector Interrupt 0 Vector 0x000094 Interrupt 1 Vector Interrupt 52 Vector Interrupt 53 Vector 0x0000FE DS70150E-page 44 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 5.4 Interrupt Sequence 5.5 Alternate Vector Table All interrupt event flags are sampled in the beginning of In program memory, the Interrupt Vector Table (IVT) is each instruction cycle by the IFSx registers. A pending followed by the Alternate Interrupt Vector Table (AIVT), Interrupt Request (IRQ) is indicated by the flag bit as shown in Figure5-1. Access to the Alternate Vector being equal to a ‘1’ in an IFSx register. The IRQ will Table is provided by the ALTIVT bit in the INTCON2 cause an interrupt to occur if the corresponding bit in register. If the ALTIVT bit is set, all interrupt and excep- the Interrupt Enable register (IECx) is set. For the tion processes will use the alternate vectors instead of remainder of the instruction cycle, the priorities of all the default vectors. The alternate vectors are organized pending interrupt requests are evaluated. in the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing If there is a pending IRQ with a priority level greater a means to switch between an application and a than the current processor priority level in the IPL bits, support environment, without requiring the interrupt the processor will be interrupted. vectors to be reprogrammed. This feature also enables The processor then stacks the current program counter switching between applications for evaluation of and the low byte of the processor STATUS register different software algorithms at run time. (SRL), as shown in Figure5-2. The low byte of the If the AIVT is not required, the program memory allo- STATUS register contains the processor priority level at cated to the AIVT may be used for other purposes. the time prior to the beginning of the interrupt cycle. AIVT is not a protected section and may be freely The processor then loads the priority level for this inter- programmed by the user. rupt into the STATUS register. This action will disable all lower priority interrupts until the completion of the 5.6 Fast Context Saving Interrupt Service Routine. A context saving option is available using shadow reg- FIGURE 5-2: INTERRUPT STACK isters. Shadow registers are provided for the DC, N, FRAME OV, Z and C bits in SR, and the registers W0 through W3. The shadows are only one level deep. The shadow 0x0000 15 0 registers are accessible using the PUSH.S and POP.S instructions only. ds When the processor vectors to an interrupt, the ars PUSH.S instruction can be used to store the current ws oe value of the aforementioned registers into their s Tddr respective shadow registers. Growher A S R L IPPCL3< 1 P5:C0<>22:16> W15 (before CALL) If an ISR of a certain priority uses the PUSH.S and ck Hig <Free Word> W15 (after CALL) POP.S instructions for fast context saving, then a a higher priority ISR should not include the same instruc- St POP : [--W15] tions. Users must save the key registers in software PUSH : [W15++] during a lower priority interrupt, if the higher priority ISR uses fast context saving. Note1: The user can always lower the priority 5.7 External Interrupt Requests level by writing a new value into SR. The Interrupt Service Routine must clear the The interrupt controller supports five external interrupt interrupt flag bits in the IFSx register request signals, INT0-INT4. These inputs are edge before lowering the processor interrupt sensitive; they require a low-to-high or a high-to-low priority in order to avoid recursive transition to generate an interrupt request. The interrupts. INTCON2 register has five bits, INT0EP-INT4EP, that select the polarity of the edge detection circuitry. 2: The IPL3 bit (CORCON<3>) is always clear when interrupts are being pro- 5.8 Wake-up from Sleep and Idle cessed. It is set only during execution of traps. The interrupt controller may be used to wake-up the processor from either Sleep or Idle modes, if Sleep or The RETFIE (Return from Interrupt) instruction will Idle mode is active when the interrupt is generated. unstack the program counter and STATUS registers to return the processor to its state prior to the interrupt If an enabled interrupt request of sufficient priority is sequence. received by the interrupt controller, then the standard interrupt request is presented to the processor. At the same time, the processor will wake-up from Sleep or Idle and begin execution of the Interrupt Service Routine (ISR) needed to process the interrupt request. © 2011 Microchip Technology Inc. DS70150E-page 45

D TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC30F6010A(1) d S 701 NSaFmRe ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 5 P 0 E INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 0000 0000 0000 -p I a INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 0000 0000 0000 C g e 4 IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000 3 6 IFS1 0086 IC6IF IC5IF IC4IF IC3IF C1IF SPI2IF U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF 0000 0000 0000 0000 0 IFS2 0088 — — — FLTBIF FLTAIF — — QEIIF PWMIF C2IF INT4IF INT3IF OC8IF OC7IF OC6IF OC5IF 0000 0000 0000 0000 F IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000 6 IEC1 008E IC6IE IC5IE IC4IE IC3IE C1IE SPI2IE U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE 0000 0000 0000 0000 0 IEC2 0090 — — — FLTBIE FLTAIE — — QEIIE PWMIE C2IE INT4IE INT3IE OC8IE OC7IE OC6IE OC5IE 0000 0000 0000 0000 1 IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100 0 IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100 A IPC2 0098 — ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100 IPC3 009A — CNIP<2:0> — MI2CIP<2:0> — SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100 / 6 IPC4 009C — OC3IP<2:0> — IC8IP<2:0> — IC7IP<2:0> — INT1IP<2:0> 0100 0100 0100 0100 0 IPC5 009E — INT2IP<2:0> — T5IP<2:0> — T4IP<2:0> — OC4IP<2:0> 0100 0100 0100 0100 1 IPC6 00A0 — C1IP<2:0> — SPI2IP<2:0> — U2TXIP<2:0> — U2RXIP<2:0> 0100 0100 0100 0100 5 IPC7 00A2 — IC6IP<2:0> — IC5IP<2:0> — IC4IP<2:0> — IC3IP<2:0> 0100 0100 0100 0100 IPC8 00A4 — OC8IP<2:0> — OC7IP<2:0> — OC6IP<2:0> — OC5IP<2:0> 0100 0100 0100 0100 IPC9 00A6 — PWMIP<2:0> — C2IP<2:0> — INT41IP<2:0> — INT3IP<2:0> 0100 0100 0100 0100 IPC10 00A8 — FLTAIP<2:0> — — — — — — — — — QEIIP<2:0> 0100 0000 0000 0000 IPC11 00AA — — — — — — — — — — — — — FLTBIP<2:0> 0000 0000 0000 0100 INTTREG 00B0 — — — — ILR<3:0> — — VECNUM<5:0> 0000 0000 0000 0000 Legend: — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

© TABLE 5-3: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC30F6015(1) 2 0 SFR 1 ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 Name M ic INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 0000 0000 0000 roc INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 0000 0000 0000 h ip IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000 T e IFS1 0086 IC6IF IC5IF IC4IF IC3IF C1IF SPI2IF U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF 0000 0000 0000 0000 c h n IFS2 0088 — — — FLTBIF FLTAIF — — QEIIF PWMIF — INT4IF INT3IF OC8IF OC7IF OC6IF OC5IF 0000 0000 0000 0000 o lo IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000 g y In IEC1 008E IC6IE IC5IE IC4IE IC3IE C1IE SPI2IE U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE 0000 0000 0000 0000 c. IEC2 0090 — — — FLTBIE FLTAIE — — QEIIE PWMIE — INT4IE INT3IE OC8IE OC7IE OC6IE OC5IE 0000 0000 0000 0000 IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100 IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100 IPC2 0098 — ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100 IPC3 009A — CNIP<2:0> — MI2CIP<2:0> — SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100 IPC4 009C — OC3IP<2:0> — IC8IP<2:0> — IC7IP<2:0> — INT1IP<2:0> 0100 0100 0100 0100 IPC5 009E — INT2IP<2:0> — T5IP<2:0> — T4IP<2:0> — OC4IP<2:0> 0100 0100 0100 0100 IPC6 00A0 — C1IP<2:0> — SPI2IP<2:0> — U2TXIP<2:0> — U2RXIP<2:0> 0100 0100 0100 0100 IPC7 00A2 — IC6IP<2:0> — IC5IP<2:0> — IC4IP<2:0> — IC3IP<2:0> 0100 0100 0100 0100 IPC8 00A4 — OC8IP<2:0> — OC7IP<2:0> — OC6IP<2:0> — OC5IP<2:0> 0100 0100 0100 0100 IPC9 00A6 — PWMIP<2:0> — — — — — INT41IP<2:0> — INT3IP<2:0> 0100 0000 0100 0100 IPC10 00A8 — FLTAIP<2:0> — — — — — — — — — QEIIP<2:0> 0100 0000 0000 0000 d IPC11 00AA — — — — — — — — — — — — — FLTBIP<2:0> 0000 0000 0000 0100 s INTTREG 00B0 — — — — ILR<3:0> — — VECNUM<5:0> 0000 0000 0000 0000 P Legend: — = unimplemented bit, read as ‘0’ I Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. C 3 0 F 6 0 1 0 D A S 7 0 / 15 6 0 E 0 -p a 1 g e 4 5 7

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dsPIC30F6010A/6015 6.0 FLASH PROGRAM MEMORY 6.2 Run-Time Self-Programming (RTSP) Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not RTSP is accomplished using TBLRD (table read) and intended to be a complete reference TBLWT (table write) instructions. source. For more information on the CPU, With RTSP, the user may erase program memory, peripherals, register descriptions and 32instructions (96 bytes) at a time and can write general device functionality, refer to the program memory data, 32 instructions (96 bytes) at a “dsPIC30F Family Reference Manual” time. (DS70046). For more information on the device instruction set and programming, 6.3 Table Instruction Operation Summary refer to the “16-bit MCU and DSC Pro- grammer’s Reference Manual” The TBLRDL and the TBLWTL instructions are used to (DS70157). read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in The dsPIC30F family of devices contains internal Word or Byte mode. program Flash memory for executing user code. There are two methods by which the user can program this The TBLRDH and TBLWTH instructions are used to read memory: or write to bits<23:16> of program memory. TBLRDH and TBLWTH can access program memory in Word or 1. In-Circuit Serial Programming™ (ICSP™) Byte mode. 2. Run-Time Self-Programming (RTSP) A 24-bit program memory address is formed using bits<7:0> of the TBLPAG register and the Effective 6.1 In-Circuit Serial Programming Address (EA) from a W register specified in the table (ICSP) instruction, as shown in Figure6-1. dsPIC30F devices can be serially programmed while in the end application circuit. This is simply done with two lines for Programming Clock and Programming Data (which are named PGC and PGD, respectively), and three other lines for Power (VDD), Ground (VSS) and Master Clear (MCLR). This allows customers to manu- facture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. FIGURE 6-1: ADDRESSING FOR TABLE AND NVM REGISTERS 24 bits Using Program 0 Program Counter 0 Counter NVMADR Reg EA Using NVMADR 1/0 NVMADRU Reg Addressing 8 bits 16 bits Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 bits 16 bits Byte User/Configuration Select Space Select 24-bit EA © 2011 Microchip Technology Inc. DS70150E-page 49

dsPIC30F6010A/6015 6.4 RTSP Operation 6.5 RTSP Control Registers The dsPIC30F Flash program memory is organized The four SFRs used to read and write the program into rows and panels. Each row consists of 32 instruc- Flash memory are: tions, or 96 bytes. Each panel consists of 128 rows, or • NVMCON 4K x 24 instructions. RTSP allows the user to erase one • NVMADR row (32 instructions) at a time and to program 32instructions at one time. • NVMADRU • NVMKEY Each panel of program memory contains write latches that hold 32 instructions of programming data. Prior to 6.5.1 NVMCON REGISTER the actual programming operation, the write data must be loaded into the panel write latches. The data to be The NVMCON register controls which blocks are to be programmed into the panel is loaded in sequential erased, which memory type is to be programmed and order into the write latches; instruction 0, instruction 1, start of the programming cycle. etc. The addresses loaded must always be from a 32 6.5.2 NVMADR REGISTER address boundary. The NVMADR register is used to hold the lower two The basic sequence for RTSP programming is to set up bytes of the Effective Address. The NVMADR register a Table Pointer, then do a series of TBLWT instructions captures the EA<15:0> of the last table instruction that to load the write latches. Programming is performed by has been executed and selects the row to write. setting the special bits in the NVMCON register. 32 TBLWTL and 32 TBLWTH instructions are required to 6.5.3 NVMADRU REGISTER load the 32 instructions. The NVMADRU register is used to hold the upper byte All of the table write operations are single-word writes of the Effective Address. The NVMADRU register cap- (2 instruction cycles), because only the table latches tures the EA<23:16> of the last table instruction that are written. has been executed. After the latches are written, a programming operation needs to be initiated to program the data. 6.5.4 NVMKEY REGISTER The Flash program memory is readable, writable and NVMKEY is a write-only register that is used for write erasable during normal operation over the entire VDD protection. To start a programming or an erase range. sequence, the user must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section6.6 “Programming Operations” for further details. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. DS70150E-page 50 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 6.6 Programming Operations 4. Write 32 instruction words of data from data RAM “image” into the program Flash write A complete programming sequence is necessary for latches. programming or erasing the internal Flash in RTSP 5. Program 32 instruction words into program mode. A programming operation is nominally 2 msec in Flash. duration and the processor stalls (waits) until the oper- a) Set up NVMCON register for multi-word, ation is finished. Setting the WR bit (NVMCON<15>) program Flash, program, and set WREN starts the operation, and the WR bit is automatically bit. cleared when the operation is finished. b) Write 0x55 to NVMKEY. 6.6.1 PROGRAMMING ALGORITHM FOR c) Write 0xAA to NVMKEY. PROGRAM FLASH d) Set the WR bit. This will begin program The user can erase or program one row of program cycle. Flash memory at a time. The general process is: e) CPU will stall for duration of the program cycle. 1. Read one row of program Flash (32 instruction words) and store into data RAM as a data f) The WR bit is cleared by the hardware “image”. when program cycle ends. 2. Update the data image with the desired new 6. Repeat steps 1 through 5 as needed to program data. desired amount of program Flash memory. 3. Erase program Flash row. 6.6.2 ERASING A ROW OF PROGRAM a) Set up NVMCON register for multi-word, MEMORY program Flash, erase, and set WREN bit. Example6-1 shows a code sequence that can be used b) Write address of row to be erased into to erase a row (32 instructions) of program memory. NVMADRU/NVMDR. c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. e) Set the WR bit. This will begin erase cycle. f) CPU will stall for the duration of the erase cycle. g) The WR bit is cleared when erase cycle ends. EXAMPLE 6-1: ERASING A ROW OF PROGRAM MEMORY ; Setup NVMCON for erase operation, multi word write ; program memory selected, and writes enabled MOV #0x4041,W0 ; MOV W0 NVMCON ; Init NVMCON SFR , ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR),W0 ; MOV W0 NVMADRU ; Initialize PM Page Boundary SFR , MOV #tbloffset(PROG_ADDR),W0 ; Intialize in-page EA[15:0] pointer MOV W0, NVMADR ; Intialize NVMADR SFR DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55,W0 MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted © 2011 Microchip Technology Inc. DS70150E-page 51

dsPIC30F6010A/6015 6.6.3 LOADING WRITE LATCHES Example6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the Table Pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000,W0 ; MOV W0 TBLPAG ; Initialize PM Page Boundary SFR , MOV #0x6000,W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0,W2 ; MOV #HIGH_BYTE_0,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , ; 1st_program_word MOV #LOW_WORD_1,W2 ; MOV #HIGH_BYTE_1,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , ; 2nd_program_word MOV #LOW_WORD_2,W2 ; MOV #HIGH_BYTE_2,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , • • • ; 31st_program_word MOV #LOW_WORD_31,W2 ; MOV #HIGH_BYTE_31,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , Note: In Example6-2, the contents of the upper byte of W3 has no effect. 6.6.4 INITIATING THE PROGRAMMING SEQUENCE For protection, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs. EXAMPLE 6-3: INITIATING A PROGRAMMING SEQUENCE DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55,W0 MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted DS70150E-page 52 © 2011 Microchip Technology Inc.

© TABLE 6-1: NVM REGISTER MAP(1) 2 01 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 1 M NVMCON 0760 WR WREN WRERR — — — — TWRI — PROGOP<6:0> 0000 0000 0000 0000 ic ro NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu c hip NVMADRU 0764 — — — — — — — — NVMADR<23:16> 0000 0000 uuuu uuuu T NVMKEY 0766 — — — — — — — — KEY<7:0> 0000 0000 0000 0000 e ch Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ no Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. lo g y In c . d s P I C 3 0 F 6 0 1 0 D A S 7 0 / 15 6 0 E 0 -p a 1 g e 5 5 3

dsPIC30F6010A/6015 NOTES: DS70150E-page 54 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 7.0 DATA EEPROM MEMORY A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- Note: This data sheet summarizes features of sible for waiting for the appropriate duration of time this group ofdsPIC30F devices and is not before initiating another data EEPROM write/erase intended to be a complete reference operation. Attempting to read the data EEPROM while source. For more information on the CPU, a programming or erase operation is in progress results peripherals, register descriptions and in unspecified data. general device functionality, refer to the Control bit WR initiates write operations, similar to pro- “dsPIC30F Family Reference Manual” gram Flash writes. This bit cannot be cleared, only set, (DS70046). For more information on the in software. This bit is cleared in hardware at the com- device instruction set and programming, pletion of the write operation. The inability to clear the refer to the “16-bit MCU and DSC WR bit in software prevents the accidental or Programmer’s Reference Manual” premature termination of a write operation. (DS70157). The WREN bit, when set, will allow a write operation. The data EEPROM memory is readable and writable On power-up, the WREN bit is clear. The WRERR bit is during normal operation over the entire VDD range. The set when a write operation is interrupted by a MCLR data EEPROM memory is directly mapped in the Reset, or a WDT Time-out Reset, during normal oper- program memory address space. ation. In these situations, following Reset, the user can check the WRERR bit and rewrite the location. The The four SFRs used to read and write the program address register NVMADR remains unchanged. Flash memory are used to access data EEPROM memory, as well. As described in Section4.0 Note: Interrupt flag bit NVMIF in the IFS0 regis- “Address Generator Units”, these registers are: ter is set when write is complete. It must • NVMCON be cleared in software. • NVMADR 7.1 Reading the Data EEPROM • NVMADRU • NVMKEY A TBLRD instruction reads a word at the current pro- The EEPROM data memory allows read and write of gram word address. This example uses W0 as a single words and 16-word blocks. When interfacing to pointer to data EEPROM. The result is placed in data memory, NVMADR, in conjunction with the register W4, as shown in Example7-1. NVMADRU register, is used to address the EEPROM location being accessed. TBLRDL and TBLWTL instruc- EXAMPLE 7-1: DATA EEPROM READ tions are used to read and write data EEPROM. The MOV #LOW_ADDR_WORD,W0 ; Init Pointer dsPIC30F6010 device has 8 Kbytes (4K words) of data MOV #HIGH_ADDR_WORD,W1 EEPROM, with an address range from 0x7FF000 to MOV W1 TBLPAG , 0x7FFFFE. TBLRDL [ W0 ], W4 ; read data EEPROM A word write operation should be preceded by an erase of the corresponding memory location(s). The write typically requires 2 ms to complete, but the write time will vary with voltage and temperature. © 2011 Microchip Technology Inc. DS70150E-page 55

dsPIC30F6010A/6015 7.2 Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM and set the WR and WREN bits in the NVMCON register. Setting the WR bit initiates the erase, as shown in Example7-2. EXAMPLE 7-2: DATA EEPROM BLOCK ERASE ; Select data EEPROM block, WR, WREN bits MOV #4045,W0 MOV W0 NVMCON ; Initialize NVMCON SFR , ; Start erase cycle by setting WR after writing key sequence DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55,W0 ; MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Initiate erase sequence NOP NOP ; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete 7.2.2 ERASING A WORD OF DATA EEPROM The NVMADRU and NVMADR registers must point to the block. Select a block of data Flash and set the WR and WREN bits in the NVMCON register. Setting the WR bit initiates the erase, as shown in Example7-3. EXAMPLE 7-3: DATA EEPROM WORD ERASE ; Select data EEPROM word, WR, WREN bits MOV #4044,W0 MOV W0 NVMCON , ; Start erase cycle by setting WR after writing key sequence DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55,W0 ; MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Initiate erase sequence NOP NOP ; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete DS70150E-page 56 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 7.3 Writing to the Data EEPROM The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to To write an EEPROM data location, the following NVMCON, then set WR bit) for each word. It is strongly sequence must be followed: recommended that interrupts be disabled during this 1. Erase data EEPROM word. codesegment. a) Select word, data EEPROM, erase and set Additionally, the WREN bit in NVMCON must be set to WREN bit in NVMCON register. enable writes. This mechanism prevents accidental b) Write address of word to be erased into writes to data EEPROM, due to unexpected code exe- NVMADRU/NVMADR. cution. The WREN bit should be kept clear at all times, c) Enable NVM interrupt (optional). except when updating the EEPROM. The WREN bit is not cleared byhardware. d) Write 0x55 to NVMKEY. e) Write 0xAA to NVMKEY. After a write sequence has been initiated, clearing the WREN bit will not affect the current write cycle. The WR f) Set the WR bit. This will begin erase cycle. bit will be inhibited from being set unless the WREN bit g) Either poll NVMIF bit or wait for NVMIF is set. The WREN bit must be set on a previous instruc- interrupt. tion. Both WR and WREN cannot be set with the same h) The WR bit is cleared when the erase cycle instruction. ends. At the completion of the write cycle, the WR bit is 2. Write data word into data EEPROM write cleared in hardware and the Nonvolatile Memory Write latches. Complete Interrupt Flag bit (NVMIF) is set. The user 3. Program 1 data word into data EEPROM. may either enable this interrupt, or poll this bit. NVMIF a) Select word, data EEPROM, program and must be cleared by software. set WREN bit in NVMCON register. 7.3.1 WRITING A WORD OF DATA b) Enable NVM write done interrupt (optional). EEPROM c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. Once the user has erased the word to be programmed, then a table write instruction is used to write one write e) Set the WR bit. This will begin program latch, as shown in Example7-4. cycle. f) Either poll NVMIF bit or wait for NVM interrupt. g) The WR bit is cleared when the write cycle ends. EXAMPLE 7-4: DATA EEPROM WORD WRITE ; Point to data memory MOV #LOW_ADDR_WORD,W0 ; Init pointer MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #LOW(WORD),W2 ; Get data TBLWTL W2 [ W0] ; Write data , ; The NVMADR captures last table access address ; Select data EEPROM for 1 word op MOV #0x4004,W0 MOV W0 NVMCON , ; Operate key to allow write operation DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55,W0 MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Initiate program sequence NOP NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2011 Microchip Technology Inc. DS70150E-page 57

dsPIC30F6010A/6015 7.3.2 WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 ; Init pointer MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 ; Get 1st data TBLWTL W2 [ W0]++ ; write data , MOV #data2,W2 ; Get 2nd data TBLWTL W2 [ W0]++ ; write data , MOV #data3,W2 ; Get 3rd data TBLWTL W2 [ W0]++ ; write data , MOV #data4,W2 ; Get 4th data TBLWTL W2 [ W0]++ ; write data , MOV #data5,W2 ; Get 5th data TBLWTL W2 [ W0]++ ; write data , MOV #data6,W2 ; Get 6th data TBLWTL W2 [ W0]++ ; write data , MOV #data7,W2 ; Get 7th data TBLWTL W2 [ W0]++ ; write data , MOV #data8,W2 ; Get 8th data TBLWTL W2 [ W0]++ ; write data , MOV #data9,W2 ; Get 9th data TBLWTL W2 [ W0]++ ; write data , MOV #data10,W2 ; Get 10th data TBLWTL W2 [ W0]++ ; write data , MOV #data11,W2 ; Get 11th data TBLWTL W2 [ W0]++ ; write data , MOV #data12,W2 ; Get 12th data TBLWTL W2 [ W0]++ ; write data , MOV #data13,W2 ; Get 13th data TBLWTL W2 [ W0]++ ; write data , MOV #data14,W2 ; Get 14th data TBLWTL W2 [ W0]++ ; write data , MOV #data15,W2 ; Get 15th data TBLWTL W2 [ W0]++ ; write data , MOV #data16,W2 ; Get 16th data TBLWTL W2 [ W0]++ ; write data. The NVMADR captures last table access address. , MOV #0x400A,W0 ; Select data EEPROM for multi word op MOV W0 NVMCON ; Operate Key to allow program operation , DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55,W0 MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Start write cycle NOP NOP 7.4 Write Verify 7.5 Protection Against Spurious Write Depending on the application, good programming There are conditions when the device may not want to practice may dictate that the value written to the mem- write to the data EEPROM memory. To protect against ory should be verified against the original value. This spurious EEPROM writes, various mechanisms have should be used in applications where excessive writes been built-in. On power-up, the WREN bit is cleared; can stress bits near the specification limit. also, the Power-up Timer prevents EEPROMwrite. The write initiate sequence and the WREN bit together, help prevent an accidental write during brown-out, power glitch or software malfunction. DS70150E-page 58 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 8.0 I/O PORTS Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins and writes to the Note: This data sheet summarizes features of port pins, write the latch (LATx). this group ofdsPIC30F devices and is not Any bit and its associated data and control registers intended to be a complete reference that are not valid for a particular device will be source. For more information on the CPU, disabled. That means the corresponding LATx and peripherals, register descriptions and TRISx registers and the port pin will read as zeros. general device functionality, refer to the “dsPIC30F Family Reference Manual” When a pin is shared with another peripheral or func- (DS70046). tion that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no All of the device pins (except VDD, VSS, MCLR and other competing source of outputs. An example is the OSC1/CLKI) are shared between the peripherals and INT4 pin. Figure8-1 shows the structure for a the parallel I/O ports. dedicated port. All I/O input ports feature Schmitt Trigger inputs for The format of the registers for PORTA are shown in improved noise immunity. Table8-1. The TRISA register (Data Direction Control) controls 8.1 Parallel I/O (PIO) Ports the direction of the RA<7:0> pins, as well as the INTx pins and the VREF pins. The LATA register supplies When a peripheral is enabled and the peripheral is data to the outputs and is readable/writable. Reading actively driving an associated pin, the use of the pin as the PORTA register yields the state of the input pins, a general purpose output pin is disabled. The I/O pin while writing the PORTA register modifies the contents may be read, but the output driver for the parallel port of the LATA register. bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be A parallel I/O (PIO) port that shares a pin with a periph- driven by a port. eral is, in general, subservient to the peripheral. The peripheral’s output buffer data and control signals are All port pins have three registers directly associated provided to a pair of multiplexers. The multiplexers with the operation of the port pin. The data direction select whether the peripheral or the associated port register (TRISx) determines whether the pin is an input has ownership of the output data and control signals of or an output. If the data direction bit is a ‘1’, then the pin the I/O pad cell. Figure8-2 shows how ports are shared is an input. All port pins are defined as inputs after a with other peripherals, and the associated I/O cell (pad) Reset. Reads from the latch (LATx), read the latch. to which they are connected. Table8-1 shows the formats of the registers for the shared ports, PORTB through PORTG. FIGURE 8-1: BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE Dedicated Port Module Read TRIS I/O Cell TRIS Latch Data Bus D Q WR TRIS CK Data Latch D Q I/O Pad WR LAT+ CK WR Port Read LAT Read Port © 2011 Microchip Technology Inc. DS70150E-page 59

dsPIC30F6010A/6015 FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Cell Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data 0 Read TRIS I/O Pad Data Bus D Q WR TRIS CK TRIS Latch D Q WR LAT + CK WR Port Data Latch Read LAT Input Data Read Port 8.2 Configuring Analog Port Pins 8.2.1 I/O PORT WRITE/READ TIMING The use of the ADPCFG and TRIS registers control the One instruction cycle is required between a port operation of the A/D port pins. The port pins that are direction change or port write operation and a read desired as analog inputs must have their correspond- operation of the same port. Typically this instruction ing TRIS bit set (input). If the TRIS bit is cleared would be a NOP. (output), the digital output level (VOH or VOL) will be converted. EXAMPLE 8-1: PORT WRITE/READ EXAMPLE When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). MOV 0xFF00, W0 ; Configure PORTB<15:8> ; as inputs Pins configured as digital inputs will not convert an ana- MOV W0, TRISBB ; and PORTB<7:0> as outputs log input. Analog levels on any pin that is defined as a NOP ; Delay 1 cycle digital input (including the ANx pins) may cause the BTSS PORTB, #13 ; Next Instruction input buffer to consume current that exceeds the device specifications. DS70150E-page 60 © 2011 Microchip Technology Inc.

© TABLE 8-1: dsPIC30F6010A PORT REGISTER MAP(1) 2 0 11 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State M Name icro TRISA 02C0 TRISA15 TRISA14 — — — TRISA10 TRISA9 — — — — — — — — — 1100 0110 0000 0000 c h PORTA 02C2 RA15 RA14 — — — RA10 RA9 — — — — — — — — — 0000 0000 0000 0000 ip T LATA 02C4 LATA15 LATA14 — — — LATA10 LATA9 — — — — — — — — — 0000 0000 0000 0000 e ch TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 n o PORTB 02C8 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000 lo g LATB 02CB LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000 y In TRISC 02CC TRISC15 TRISC14 TRISC13 — — — — — — — — — TRISC3 — TRISC1 — 1110 0000 0000 1010 c . PORTC 02CE RC15 RC14 RC13 — — — — — — — — — RC3 — RC1 — 0000 0000 0000 0000 LATC 02D0 LATC15 LATC14 LATC13 — — — — — — — — — LATC3 — LATC1 — 0000 0000 0000 0000 TRISD 02D2 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111 PORTD 02D4 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000 0000 0000 LATD 02D6 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 0000 0000 0000 0000 TRISE 02D8 — — — — — — TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 0000 0011 1111 1111 PORTE 02DA — — — — — — RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000 LATE 02DC — — — — — — LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 0000 0000 0000 0000 TRISF 02EE — — — — — — — TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 0000 0001 1111 1111 PORTF 02E0 — — — — — — — RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 0000 0000 0000 0000 LATF 02E2 — — — — — — — LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 0000 0000 0000 0000 d TRISG 02E4 — — — — — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 0000 0011 1100 1111 s PORTG 02E6 — — — — — — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 RG0 0000 0000 0000 0000 P LATG 02E8 — — — — — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 LATG0 0000 0000 0000 0000 I Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ C Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 3 0 F 6 0 1 0 D A S 7 0 / 15 6 0 E 0 -p a 1 g e 6 5 1

D TABLE 8-2: dsPIC30F6015 PORT REGISTER MAP(1) d S 70 SFR s 1 Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 5 Name P 0 E -p TRISA 02C0 — — — — — — — — — — — — — — — — 0000 0000 0000 0000 I a C g PORTA 02C2 — — — — — — — — — — — — — — — — 0000 0000 0000 0000 e 62 LATA 02C4 — — — — — — — — — — — — — — — — 0000 0000 0000 0000 3 TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 0 PORTB 02C8 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000 F LATB 02CB LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000 6 TRISC 02CC TRISC15 TRISC14 TRISC13 — — — — — — — — — — — — — 1110 0000 0000 0000 0 PORTC 02CE RC15 RC14 RC13 — — — — — — — — — — — — — 0000 0000 0000 0000 1 LATC 02D0 LATC15 LATC14 LATC13 — — — — — — — — — — — — — 0000 0000 0000 0000 0 TRISD 02D2 — — — — TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 0000 1111 1111 1111 A PORTD 02D4 — — — — RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000 0000 0000 / LATD 02D6 — — — — LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 0000 0000 0000 0000 6 TRISE 02D8 — — — — — — — — TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 0000 0000 1111 1111 0 1 PORTE 02DA — — — — — — — — RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000 5 LATE 02DC — — — — — — — — LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 0000 0000 0000 0000 TRISF 02EE — — — — — — — — — TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 0000 0000 0111 1111 PORTF 02E0 — — — — — — — — — RF6 RF5 RF4 RF3 RF2 RF1 RF0 0000 0000 0000 0000 LATF 02E2 — — — — — — — — — LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 0000 0000 0000 0000 TRISG 02E4 — — — — — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 — — 0000 0011 1100 1100 PORTG 02E6 — — — — — — RG9 RG8 RG7 RG6 — — RG3 RG2 — — 0000 0000 0000 0000 LATG 02E8 — — — — — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 — — 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F6010A/6015 8.3 Input Change Notification Module The input change notification module provides the dsPIC30F devices the ability to generate interrupt requests to the processor in response to a change-of- state on selected input pins. This module is capable of detecting input change-of-states, even in Sleep mode when the clocks are disabled. There are 22 external signals (CN0 through CN21) for dsPIC30F6010A and 19 external signals (CN0 through CN19) for dsPIC30F6015 that may be selected (enabled) for generating an interrupt request on a change-of-state. Please refer to the Pin Diagrams for CN pin locations. TABLE 8-3: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 15-8)(1) SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset State Name CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE 0000 0000 0000 0000 CNEN2 00C2 — — — — — — — — 0000 0000 0000 0000 CNPU1 00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE 0000 0000 0000 0000 CNPU2 00C6 — — — — — — — — 0000 0000 0000 0000 Legend: — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-4: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0) FOR dsPIC30F6010A(1) SFR Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State Name CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000 CNEN2 00C2 — — CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 0000 0000 0000 CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000 CNPU2 00C6 — — CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000 Legend: — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-5: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0) FOR dsPIC30F6015(1) SFR Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State Name CNEN1 00C0 CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000 CNEN2 00C2 — — — — — CN18IE CN17IE CN16IE 0000 0000 0000 0000 CNPU1 00C4 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000 CNPU2 00C6 — — — — — CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000 Legend: — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. © 2011 Microchip Technology Inc. DS70150E-page 63

dsPIC30F6010A/6015 NOTES: DS70150E-page 64 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 9.0 TIMER1 MODULE These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure9- Note: This data sheet summarizes features of 1 presents a block diagram of the 16-bit timer module. this group ofdsPIC30F devices and is not 16-bit Timer Mode: In the 16-bit Timer mode, the timer intended to be a complete reference increments on every instruction cycle up to a match source. For more information on the CPU, value, preloaded into the period register, PR1, then peripherals, register descriptions and resets to ‘0’ and continues to count. general device functionality, refer to the “dsPIC30F Family Reference Manual” When the CPU goes into the Idle mode, the timer will (DS70046). stop incrementing, unless the TSIDL (T1CON<13>) bit= 0. If TSIDL = 1, the timer module logic will resume This section describes the 16-bit General Purpose the incrementing sequence upon termination of the (GP) Timer1 module and associated operational CPU Idle mode. modes. 16-bit Synchronous Counter Mode: In the 16-bit Note: Timer1 is a Type A timer. Refer to Synchronous Counter mode, the timer increments on Section24.0 “Electrical Characteris- the rising edge of the applied external clock signal, tics” for the Type A timer specifications. which is synchronized with the internal phase clocks. The following sections provide a detailed description, The timer counts up to a match value preloaded in PR1, including setup and control registers along with associ- then resets to 0 and continues. ated block diagrams for the operational modes of the When the CPU goes into the Idle mode, the timer will timers. stop incrementing, unless the respective TSIDL bit = 0. The Timer1 module is a 16-bit timer which can serve as If TSIDL = 1, the timer module logic will resume the the time counter for the Real-Time Clock, or operate as incrementing sequence upon termination of the CPU a free running interval timer/counter. The 16-bit timer Idle mode. has the following modes: 16-bit Asynchronous Counter Mode: In the 16-bit • 16-bit Timer Asynchronous Counter mode, the timer increments on • 16-bit Synchronous Counter every rising edge of the applied external clock signal. • 16-bit Asynchronous Counter The timer counts up to a match value preloaded in PR1, Further, the following operational characteristics are then resets to ‘0’ and continues. supported: When the timer is configured for the Asynchronous mode • Timer gate operation of operation and the CPU goes into the Idle mode, the • Selectable prescaler settings timer will stop incrementing if TSIDL = 1. • Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling edge of external gate signal FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) PR1 Equal Comparator x 16 TSYNC 1 Sync TMR1 Reset 0 0 T1IF Event Flag 1 Q D TGATE E Q CK T S A C G TGATE T T TCKPS<1:0> TON 2 SOSCO/ 1 x T1CK LPOSCEN Gate Prescaler Sync 0 1 1, 8, 64, 256 SOSCI TCY 0 0 © 2011 Microchip Technology Inc. DS70150E-page 65

dsPIC30F6010A/6015 9.1 Timer Gate Operation 9.4 Timer Interrupt The 16-bit timer can be placed in the Gated Time The 16-bit timer has the ability to generate an interrupt Accumulation mode. This mode allows the internal TCY on period match. When the timer count matches the to increment the respective timer when the gate input period register, the T1IF bit is asserted and an interrupt signal (T1CK pin) is asserted high. Control bit TGATE will be generated, if enabled. The T1IF bit must be (T1CON<6>) must be set to enable this mode. The cleared in software. The Timer Interrupt Flag, T1IF, is timer must be enabled (TON = 1) and the timer clock located in the IFS0 Control register in the interrupt source set to internal (TCS = 0). controller. When the CPU goes into the Idle mode, the timer will When the Gated Time Accumulation mode is enabled, stop incrementing, unless TSIDL = 0. If TSIDL = 1, the an interrupt will also be generated on the falling edge of timer will resume the incrementing sequence upon the gate signal (at the end of the accumulation cycle). termination of the CPU Idle mode. Enabling an interrupt is accomplished via the respective Timer Interrupt Enable bit, T1IE. The Timer 9.2 Timer Prescaler Interrupt Enable bit is located in the IEC0 Control register in the interrupt controller. The input clock (FOSC/4 or external clock) to the 16-bit Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256 9.5 Real-Time Clock selected by control bits, TCKPS<1:0> (T1CON<5:4>). The prescaler counter is cleared when any of the Timer1, when operating in Real-Time Clock (RTC) following occurs: mode, provides time-of-day and event time-stamping • write to the TMR1 register capabilities. Key operational features of the RTC are: • clearing of the TON bit (T1CON<15>) • Operation from 32 kHz LP oscillator • device Reset such as POR and BOR • 8-bit prescaler However, if the timer is disabled (TON = 0), then the • Low power timer prescaler cannot be reset since the prescaler • Real-Time Clock interrupts clock is halted. These Operating modes are determined by setting the TMR1 is not cleared when T1CON is written. It is appropriate bit(s) in the T1CON Control register. cleared by writing to the TMR1 register. FIGURE 9-2: RECOMMENDED 9.3 Timer Operation During Sleep COMPONENTS FOR Mode TIMER1 LP OSCILLATOR RTC During CPU Sleep mode, the timer will operate if: • The timer module is enabled (TON = 1) and C1 • The timer clock source is selected as external SOSCI (TCS = 1) and • The TSYNC bit (T1CON<2>) is asserted to a logic 32.768 kHz dsPIC30FXXXX XTAL ‘0’, which defines the external clock source as asynchronous SOSCO When all three conditions are true, the timer will con- C2 R tinue to count up to the period register and be reset to C1 = C2 = 18 pF; R = 100K 0x0000. When a match between the timer and the period regis- ter occurs, an interrupt can be generated, if the respective timer interrupt enable bit is asserted. DS70150E-page 66 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal, up to the value specified in the period register, and is then reset to ‘0’. The TSYNC bit must be asserted to a logic ‘0’ (Asynchronous mode) for correct operation. Enabling LPOSCEN (OSCCON<1>) will disable the normal Timer and Counter modes and enable a timer carry-out wake-up event. When the CPU enters Sleep mode, the RTC will con- tinue to operate, provided the 32 kHz external crystal oscillator is active and the control bits have not been changed. The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt will be generated, if enabled. The T1IF bit must be cleared in software. The respective Timer Interrupt Flag, T1IF, is located in the IFS0 STATUS register in the interrupt controller. Enabling an interrupt is accomplished via the respec- tive Timer Interrupt Enable bit, T1IE. The Timer Interrupt Enable bit is located in the IEC0 Control register in the interrupt controller. © 2011 Microchip Technology Inc. DS70150E-page 67

D TABLE 9-1: TIMER1 REGISTER MAP(1) d S 70 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 1 5 P 0E TMR1 0100 Timer1 Register uuuu uuuu uuuu uuuu -pa PR1 0102 Period Register 1 1111 1111 1111 1111 IC g e T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 0000 0000 0000 68 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ 3 Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 0 F 6 0 1 0 A / 6 0 1 5 © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F6010A/6015 10.0 TIMER2/3 MODULE For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word Note: This data sheet summarizes features of of the 32-bit timer. this group ofdsPIC30F devices and is not Note: For 32-bit timer operation, T3CON control intended to be a complete reference bits are ignored. Only T2CON control bits source. For more information on the CPU, are used for setup and control. Timer2 peripherals, register descriptions and gen- clock and gate inputs are utilized for the eral device functionality, refer to the 32-bit timer module, but an interrupt is “dsPIC30F Family Reference Manual” generated with the Timer3 Interrupt Flag (DS70046). (T3IF) and the interrupt is enabled with the This section describes the 32-bit General Purpose Timer3 Interrupt Enable bit (T3IE). (GP) Timer module (Timer2/3) and associated opera- 16-bit Mode: In the 16-bit mode, Timer2 and Timer3 tional modes. Figure10-1 depicts the simplified block can be configured as two independent 16-bit timers. diagram of the 32-bit Timer2/3 module. Figure10-3 Each timer can be set up in either 16-bit Timer mode or and Figure10-5 show Timer2/3 configured as two 16-bit Synchronous Counter mode. See Section9.0 independent 16-bit timers; Timer2 and Timer3, “Timer1 Module”, Timer1 Module, for details on these respectively. two operating modes. Note: Timer2 is a Type B timer and Timer3 is a The only functional difference between Timer2 and Type C timer. Please refer to the appropri- Timer3 is that Timer2 provides synchronization of the ate timer type in Section24.0 “Electrical clock prescaler output. This is useful for high frequency Characteristics”. external clock inputs. The Timer2/3 module is a 32-bit timer, which can be 32-bit Timer Mode: In the 32-bit Timer mode, the timer configured as two 16-bit timers, with selectable operat- increments on every instruction cycle up to a match ing modes. These timers are utilized by other value, preloaded into the combined 32-bit period peripheral modules such as: register, PR3/PR2, then resets to ‘0’ and continues to count. • Input Capture • Output Compare/Simple PWM For synchronous 32-bit reads of the Timer2/Timer3 pair, reading the lsw (TMR2 register) will cause the The following sections provide a detailed description, msw to be read and latched into a 16-bit holding including setup and control registers, along with asso- register, termed TMR3HLD. ciated block diagrams for the operational modes of the timers. For synchronous 32-bit writes, the holding register (TMR3HLD) must first be written to. When followed by The 32-bit timer has the following modes: a write to the TMR2 register, the contents of TMR3HLD • Two independent 16-bit timers (Timer2 and will be transferred and latched into the MSB of the Timer3) with all 16-bit operating modes (except 32-bit timer (TMR3). Asynchronous Counter mode) 32-bit Synchronous Counter Mode: In the 32-bit • Single 32-bit Timer operation Synchronous Counter mode, the timer increments on • Single 32-bit Synchronous Counter the rising edge of the applied external clock signal, Further, the following operational characteristics are which is synchronized with the internal phase clocks. supported: The timer counts up to a match value preloaded in the combined 32-bit period register, PR3/PR2, then resets • ADC Event Trigger to ‘0’ and continues. • Timer Gate Operation When the timer is configured for the Synchronous • Selectable Prescaler Settings Counter mode of operation and the CPU goes into the • Timer Operation during Idle and Sleep modes Idle mode, the timer will stop incrementing, unless the • Interrupt on a 32-bit Period Register Match TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer module logic will resume the incrementing sequence These operating modes are determined by setting the upon termination of the CPU Idle mode. appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2011 Microchip Technology Inc. DS70150E-page 69

dsPIC30F6010A/6015 FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM FOR dsPIC30F6010A Data Bus<15:0> TMR3HLD 16 16 Write TMR2 Read TMR2 16 Reset TMR3 TMR2 Sync MSB LSB ADC Event Trigger Comparator x 32 Equal PR3 PR2 0 T3IF Event Flag 1 Q D TGATE (T2CON<6>) Q CK TGATE (T2CON<6>) E T S A C G T T TCKPS<1:0> TON 2 T2CK 1 x Prescaler Gate Sync 0 1 1, 8, 64, 256 TCY 0 0 Note: Timer Configuration bit T32, T2CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70150E-page 70 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 10-2: 32-BIT TIMER2/3 BLOCK DIAGRAM FOR dsPIC30F6015 Data Bus<15:0> TMR3HLD 16 16 Write TMR2 Read TMR2 16 Reset TMR3 TMR2 Sync MSB LSB ADC Event Trigger Comparator x 32 Equal PR3 PR2 0 T3IF Event Flag 1 Q D TGATE(T2CON<6>) Q CK TGATE (T2CON<6>) E T S A C G T T TCKPS<1:0> TON 2 1 x Prescaler Gate Sync 0 1 1, 8, 64, 256 TCY 0 0 Note: Timer Configuration bit T32, T2CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. © 2011 Microchip Technology Inc. DS70150E-page 71

dsPIC30F6010A/6015 FIGURE 10-3: 16-BIT TIMER2 BLOCK DIAGRAM (TYPE B TIMER) FOR dsPIC30F6010A PR2 Equal Comparator x 16 TMR2 Sync Reset 0 T2IF Event Flag 1 Q D TGATE Q CK TGATE E T S A C G T T TCKPS<1:0> TON 2 T2CK 1 x Gate Prescaler Sync 0 1 1, 8, 64, 256 TCY 0 0 FIGURE 10-4: 16-BIT TIMER2 BLOCK DIAGRAM (TYPE B TIMER) FOR DSPIC30F6015 PR2 Equal Comparator x 16 TMR2 Sync Reset 0 T2IF Event Flag 1 Q D TGATE Q CK TGATE E T S A C G T T TCKPS<1:0> TON 2 1 x Gate Prescaler Sync 0 1 1, 8, 64, 256 TCY 0 0 Note:The dsPIC30F6015 does not have an external pin input to TIMER2. The following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) DS70150E-page 72 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 10-5: 16-BIT TIMER3 BLOCK DIAGRAM (TYPE C TIMER) PR3 ADC Event Trigger Equal Comparator x 16 TMR3 Reset 0 T3IF Event Flag 1 Q D TGATE Q CK TGATE E T S A C G T T TCKPS<1:0> TON 2 Sync 1 x Prescaler 0 1 1, 8, 64, 256 TCY 0 0 Note:The dsPIC30F6010A/6015 devices do not have an external pin input to Timer3. These modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) © 2011 Microchip Technology Inc. DS70150E-page 73

dsPIC30F6010A/6015 10.1 Timer Gate Operation 10.4 Timer Operation During Sleep Mode The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY During CPU Sleep mode, the timer will not operate, to increment the respective timer when the gate input because the internal clocks are disabled. signal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in 10.5 Timer Interrupt this mode, Timer2 is the originating clock source. The TGATE setting is ignored for Timer3. The timer must be The 32-bit timer module can generate an interrupt on enabled (TON = 1) and the timer clock source set to period match, or on the falling edge of the external gate internal (TCS = 0). signal. When the 32-bit timer count matches the respective 32-bit period register, or the falling edge of The falling edge of the external signal terminates the the external “gate” signal is detected, the T3IF bit count operation, but does not reset the timer. The user (IFS0<7>) is asserted and an interrupt will be gener- must reset the timer in order to start counting from zero. ated if enabled. In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must 10.2 ADC Event Trigger be cleared in software. When a match occurs between the 32-bit timer (TMR3/ Enabling an interrupt is accomplished via the TMR2) and the 32-bit combined period register (PR3/ respective Timer Interrupt Enable bit, T3IE (IEC0<7>). PR2), a special ADC trigger event signal is generated by Timer3. 10.3 Timer Prescaler The input clock (FOSC/4 or external clock) to the timer has a prescale option of 1:1, 1:8, 1:64, and 1:256 selected by control bits TCKPS<1:0> (T2CON<5:4> and T3CON<5:4>). For the 32-bit timer operation, the originating clock source is Timer2. The prescaler oper- ation for Timer3 is not applicable in this mode. The prescaler counter is cleared when any of the following occurs: • write to the TMR2/TMR3 register • clearing either of the TON (T2CON<15> or T3CON<15>) bits to ‘0’ • device Reset, such as POR and BOR However, if the timer is disabled (TON = 0), then the Timer2 prescaler cannot be reset, since the prescaler clock is halted. TMR2/TMR3 is not cleared when T2CON/T3CON is written. DS70150E-page 74 © 2011 Microchip Technology Inc.

© TABLE 10-1: TIMER2/3 REGISTER MAP(1) 2 01 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 M TMR2 0106 Timer2 Register uuuu uuuu uuuu uuuu ic ro TMR3HLD 0108 Timer3 Holding Register (For 32-bit timer operations only) uuuu uuuu uuuu uuuu c hip TMR3 010A Timer3 Register uuuu uuuu uuuu uuuu T PR2 010C Period Register 2 1111 1111 1111 1111 e c h PR3 010E Period Register 3 1111 1111 1111 1111 n olo T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 0000 0000 0000 g y T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 0000 0000 0000 Inc Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ . Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. d s P I C 3 0 F 6 0 1 0 D A S 7 0 / 15 6 0 E 0 -p a 1 g e 7 5 5

dsPIC30F6010A/6015 NOTES: DS70150E-page 76 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 11.0 TIMER4/5 MODULE The Timer4/5 module is similar in operation to the Timer2/3 module. However, there are some Note: This data sheet summarizes features of differences, which are listed below: this group ofdsPIC30F devices and is not • The Timer4/5 module does not support the ADC intended to be a complete reference Event Trigger feature source. For more information on the CPU, • Timer4/5 cannot be utilized by other peripheral peripherals, register descriptions and gen- modules such as Input Capture and Output Compare eral device functionality, refer to the “dsPIC30F Family Reference Manual” The operating modes of the Timer4/5 module are (DS70046). determined by setting the appropriate bit(s) in the 16-bit T4CON and T5CON SFRs. This section describes the second 32-bit General For 32-bit timer/counter operation, Timer4 is the lsw Purpose (GP) Timer module (Timer4/5) and associated and Timer5 is the msw of the 32-bit timer. operational modes. Figure11-1 depicts the simplified block diagram of the 32-bit Timer4/5 Module. Note: For 32-bit timer operation, T5CON control Figure11-2 and Figure11-3 show Timer4/5 configured bits are ignored. Only T4CON control bits as two independent 16-bit timers, Timer4 and Timer5, are used for setup and control. Timer4 respectively. clock and gate inputs are utilized for the 32-bit timer module, but an interrupt is Note: Timer4 is a Type B timer and Timer5 is a generated with the Timer5 Interrupt Flag Type C timer. Please refer to the appropri- (T5IF) and the interrupt is enabled with the ate timer type in Section24.0 “Electrical Timer5 Interrupt Enable bit (T5IE). Characteristics”. FIGURE 11-1: 32-BIT TIMER4/5 BLOCK DIAGRAM Data Bus<15:0> TMR5HLD 16 16 Write TMR4 Read TMR4 16 Reset TMR5 TMR4 Sync MSB LSB Comparator x 32 Equal PR5 PR4 0 T5IF Event Flag 1 Q D TGATE(T4CON<6>) Q CK TGATE E (T4CON<6>) T S A C G T T TCKPS<1:0> TON 2 T4CK 1 x Prescaler Gate 0 1 1, 8, 64, 256 Sync TCY 0 0 Note: Timer Configuration bit T45, T4CON(<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T4CON register. © 2011 Microchip Technology Inc. DS70150E-page 77

dsPIC30F6010A/6015 FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM (TYPE B TIMER) PR4 Equal Comparator x 16 TMR4 Sync Reset 0 T4IF Event Flag 1 Q D TGATE Q CK TGATE E T S A C G T T TCKPS<1:0> TON 2 T4CK 1 x Gate Prescaler Sync 0 1 1, 8, 64, 256 TCY 0 0 FIGURE 11-3: 16-BIT TIMER5 BLOCK DIAGRAM (TYPE C TIMER) PR5 ADC Event Trigger Equal Comparator x 16 TMR5 Reset 0 T5IF Event Flag 1 Q D TGATE Q CK TGATE E T S A C G T T TCKPS<1:0> TON 2 Sync 1 x Prescaler 0 1 1, 8, 64, 256 TCY 0 0 Note:The dsPIC30F6010A/6015 devices do not have an external pin input to Timer5. These modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) DS70150E-page 78 © 2011 Microchip Technology Inc.

© TABLE 11-1: TIMER4/5 REGISTER MAP(1) 2 01 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 M TMR4 0114 Timer4 Register uuuu uuuu uuuu uuuu ic ro TMR5HLD 0116 Timer5 Holding Register (For 32-bit operations only) uuuu uuuu uuuu uuuu c hip TMR5 0118 Timer5 Register uuuu uuuu uuuu uuuu T PR4 011A Period Register 4 1111 1111 1111 1111 e c h PR5 011C Period Register 5 1111 1111 1111 1111 n olo T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T45 — TCS — 0000 0000 0000 0000 g y T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 0000 0000 0000 Inc Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ . Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. d s P I C 3 0 F 6 0 1 0 D A S 7 0 / 15 6 0 E 0 -p a 1 g e 7 5 9

dsPIC30F6010A/6015 NOTES: DS70150E-page 80 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 12.0 INPUT CAPTURE MODULE 12.1 Simple Capture Event Mode Note: This data sheet summarizes features of The simple capture events in the dsPIC30F product this group ofdsPIC30F devices and is not family are: intended to be a complete reference • Capture every falling edge source. For more information on the CPU, • Capture every rising edge peripherals, register descriptions and • Capture every 4th rising edge general device functionality, refer to the • Capture every 16th rising edge “dsPIC30F Family Reference Manual” (DS70046). • Capture every rising and falling edge These simple Input Capture modes are configured by This section describes the input capture module and setting the appropriate bits ICM<2:0> (ICxCON<2:0>). associated operational modes. The features provided by this module are useful in applications requiring 12.1.1 CAPTURE PRESCALER frequency (period) and pulse measurement. Figure12-1 depicts a block diagram of the input capture module. There are four input capture prescaler settings, speci- Input capture is useful for such modes as: fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the capture channel is turned off, the prescaler counter will • Frequency/Period/Pulse Measurements be cleared. In addition, any Reset will clear the • Additional sources of External Interrupts prescaler counter. The key operational features of the input capture module are: • Simple Capture Event mode • Timer2 and Timer3 mode selection • Interrupt on input capture event These operating modes are determined by setting the appropriate bits in the ICxCON register (where x=1,2,...,N). The dsPIC30F6010A and dsPIC30F6015 devices have eight capture channels. FIGURE 12-1: INPUT CAPTURE MODE BLOCK DIAGRAM From GP Timer Module T2_CNT T3_CNT 16 16 ICx ICTMR Pin 1 0 Prescaler Clock Edge FIFO 1, 4, 16 Synchronizer Detection R/W Logic Logic 3 ICM<2:0> ICxBUF Mode Select ICBNE, ICOV ICI<1:0> Interrupt ICxCON Logic Data Bus SSeett FFllaagg IICCxxIIFF Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2011 Microchip Technology Inc. DS70150E-page 81

dsPIC30F6010A/6015 12.1.2 CAPTURE BUFFER OPERATION 12.2 Input Capture Operation During Sleep and Idle Modes Each capture channel has an associated FIFO buffer, which is four 16-bit words deep. There are two status An input capture event will generate a device wake-up flags, which provide status on the FIFO buffer: or interrupt, if enabled, if the device is in CPU Idle or • ICBNE – Input Capture Buffer Not Empty Sleep mode. • ICOV – Input Capture Overflow Independent of the timer being enabled, the input The ICBFNE will be set on the first input capture event capture module will wake-up from the CPU Sleep or Idle and remain set until all capture events have been read mode when a capture event occurs, if ICM<2:0> = 111 from the FIFO. As each word is read from the FIFO, the and the interrupt enable bit is asserted. The same wake- remaining words are advanced by one position within up can generate an interrupt, if the conditions for pro- the buffer. cessing the interrupt have been satisfied. The wake-up feature is useful as a method of adding extra external pin In the event that the FIFO is full with four capture interrupts. events and a fifth capture event occurs prior to a read of the FIFO, an overflow condition will occur and the 12.2.1 INPUT CAPTURE IN CPU SLEEP ICOV bit will be set to a logic ‘1’. The fifth capture event MODE is lost and is not stored in the FIFO. No additional events will be captured till all four events have been CPU Sleep mode allows input capture module opera- read from the buffer. tion with reduced functionality. In the CPU Sleep mode, the ICI<1:0> bits are not applicable, and the If a FIFO read is performed after the last read and no input capture module can only function as an external new capture event has been received, the read will interrupt source. yield indeterminate results. The capture module must be configured for interrupt 12.1.3 TIMER2 AND TIMER3 SELECTION only on the rising edge (ICM<2:0> = 111), in order for MODE the input capture module to be used while the device is in Sleep mode. The prescale settings of 4:1 or 16:1 Each capture channel can select between one of two are not applicable in this mode. timers for the time base, Timer2 or Timer3. Selection of the timer resource is accomplished 12.2.2 INPUT CAPTURE IN CPU IDLE through SFR bit ICTMR (ICxCON<7>). Timer3 is the MODE default timer resource available for the input capture CPU Idle mode allows input capture module operation module. with full functionality. In the CPU Idle mode, the Inter- 12.1.4 HALL SENSOR MODE rupt mode selected by the ICI<1:0> bits is applicable, as well as the 4:1 and 16:1 capture prescale settings, When the input capture module is set for capture on which are defined by control bits ICM<2:0>. This mode every edge, rising and falling, ICM<2:0> = 001, the fol- requires the selected timer to be enabled. Moreover, the lowing operations are performed by the input capture ICSIDL bit must be asserted to a logic ‘0’. logic: If the input capture module is defined as • The input capture interrupt flag is set on every ICM<2:0>=111 in CPU Idle mode, the input capture edge, rising and falling. pin will serve only as an external interrupt pin. • The interrupt on Capture mode setting bits, ICI<1:0>, is ignored, since every capture 12.3 Input Capture Interrupts generates an interrupt. The input capture channels have the ability to generate • A capture overflow condition is not generated in an interrupt, based upon the selected number of cap- this mode. ture events. The selection number is set by control bits ICI<1:0> (ICxCON<6:5>). Each channel provides an interrupt flag bit (ICxIF). The respective Capture Channel Interrupt Flag is located in the corresponding IFSx STATUS register. Enabling an interrupt is accomplished via the respec- tive Capture Channel Interrupt Enable bit (ICxIE). The Capture Interrupt Enable bit is located in the corresponding IEC Control register. DS70150E-page 82 © 2011 Microchip Technology Inc.

© TABLE 12-1: INPUT CAPTURE REGISTER MAP(1) 2 01 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 M IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu ic ro IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 c h ip IC2BUF 0144 Input 2 Capture Register uuuu uuuu uuuu uuuu T e IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 c h n IC3BUF 0148 Input 3 Capture Register uuuu uuuu uuuu uuuu o log IC3CON 014A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 y In IC4BUF 014C Input 4 Capture Register uuuu uuuu uuuu uuuu c . IC4CON 014E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 IC5BUF 0150 Input 5 Capture Register uuuu uuuu uuuu uuuu IC5CON 0152 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 IC6BUF 0154 Input 6 Capture Register uuuu uuuu uuuu uuuu IC6CON 0156 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 IC7BUF 0158 Input 7 Capture Register uuuu uuuu uuuu uuuu IC7CON 015A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 IC8BUF 015C Input 8 Capture Register uuuu uuuu uuuu uuuu IC8CON 015E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. d s P I C 3 0 F 6 0 1 0 D A S 7 0 / 15 6 0 E 0 -p a 1 g e 8 5 3

dsPIC30F6010A/6015 NOTES: DS70150E-page 84 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 13.0 OUTPUT COMPARE MODULE The key operational features of the output compare module include: Note: This data sheet summarizes features of • Timer2 and Timer3 Selection mode this group ofdsPIC30F devices and is not • Simple Output Compare Match mode intended to be a complete reference source. For more information on the CPU, • Dual Output Compare Match mode peripherals, register descriptions and • Simple PWM mode general device functionality, refer to the • Output Compare during Sleep and Idle modes “dsPIC30F Family Reference Manual” • Interrupt on Output Compare/PWM Event (DS70046). These operating modes are determined by setting the This section describes the output compare module and appropriate bits in the 16-bit OCxCON SFR (where associated operational modes. The features provided x=1,2,3,...,N). The dsPIC30F6010A and by this module are useful in applications requiring dsPIC30F6015 devices have eight compare channels. operational modes such as: OCxRS and OCxR in Figure13-1 represent the Dual • Generation of Variable Width Output Pulses Compare registers. In the Dual Compare mode, the • Power Factor Correction OCxR register is used for the first compare and OCxRS is used for the second compare. Figure13-1 depicts a block diagram of the output compare module. FIGURE 13-1: OUTPUT COMPARE MODE BLOCK DIAGRAM Set Flag bit OCxIF OCxRS OCxR Output S Q OCx Logic R Output Enable 3 OCM<2:0> Comparator Mode Select OCFA (for x = 1, 2, 3 or 4) OCTSEL 0 1 0 1 or OCFB (for x = 5, 6, 7 or 8) From GP Timer Module TMR2<15:0 TMR3<15:0>T2P2_MATCH T3P3_MATCH Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. © 2011 Microchip Technology Inc. DS70150E-page 85

dsPIC30F6010A/6015 13.1 Timer2 and Timer3 Selection Mode 13.3.2 CONTINUOUS PULSE MODE Each output compare channel can select between one For the user to configure the module for the generation of two 16-bit timers; Timer2 or Timer3. of a continuous stream of output pulses, the following steps are required: The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource • Determine instruction cycle time TCY. for the Output Compare module. • Calculate desired pulse value based on TCY. • Calculate timer to start pulse width from timer start 13.2 Simple Output Compare Match value of 0x0000. Mode • Write pulse-width start and stop times into OCxR and OCxRS (x denotes channel 1, 2, ...,N) When control bits OCM<2:0> (OCxCON<2:0>) = 001, Compare registers, respectively. 010 or 011, the selected output compare channel is • Set Timer Period register to value equal to, or configured for one of three simple output compare greater than, value in OCxRS Compare register. match modes: • Set OCM<2:0> = 101. • Compare forces I/O pin low • Enable timer, TON (TxCON<15>) = 1. • Compare forces I/O pin high • Compare toggles I/O pin 13.4 Simple PWM Mode The OCxR register is used in these modes. The OCxR When control bits OCM<2:0> (OCxCON<2:0>) = 110 register is loaded with a value and is compared to the or 111, the selected output compare channel is config- selected incrementing timer count. When a compare ured for the PWM mode of operation. When configured occurs, one of these compare match modes occurs. If for the PWM mode of operation, OCxR is the main latch the counter resets to zero before reaching the value in (read-only) and OCxRS is the secondary latch. This OCxR, the state of the OCx pin remains unchanged. enables glitchless PWM transitions. 13.3 Dual Output Compare Match Mode The user must perform the following steps in order to configure the output compare module for PWM When control bits OCM<2:0> (OCxCON<2:0>) = 100 operation: or 101, the selected output compare channel is config- 1. Set the PWM period by writing to the appropriate ured for one of two Dual Output Compare modes, period register. which are: 2. Set the PWM duty cycle by writing to the OCxRS • Single Output Pulse mode register. • Continuous Output Pulse mode 3. Configure the output compare module for PWM operation. 13.3.1 SINGLE PULSE MODE 4. Set the TMRx prescale value and enable the For the user to configure the module for the generation Timer, TON (TxCON<15>) = 1. of a single output pulse, the following steps are required (assuming timer is off): 13.4.1 INPUT PIN FAULT PROTECTION FOR PWM • Determine instruction cycle time TCY. • Calculate desired pulse-width value based on When control bits OCM<2:0> (OCxCON<2:0>) = 111, TCY. the selected output compare channel is again • Calculate time to start pulse from timer start value configured for the PWM mode of operation, with the of 0x0000. additional feature of input Fault protection. While in this mode, if a logic ‘0’ is detected on the OCFA/B pin, the • Write pulse-width start and stop times into OCxR respective PWM output pin is placed in the high- and OCxRS Compare registers (x denotes impedance input state. The OCFLT bit (OCxCON<4>) channel 1, 2, ...,N). indicates whether a Fault condition has occurred. This • Set Timer Period register to value equal to, or state will be maintained until both of the following greater than, value in OCxRS Compare register. events have occurred: • Set OCM<2:0> = 100. • The external Fault condition has been removed. • Enable timer, TON (TxCON<15>) = 1. • The PWM mode has been re-enabled by writing To initiate another single pulse, issue another write to to the appropriate control bits. set OCM<2:0> = 100. DS70150E-page 86 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 13.4.2 PWM PERIOD When the selected TMRx is equal to its respective period register, PRx, the following four events occur on The PWM period is specified by writing to the PRx the next increment cycle: register. The PWM period can be calculated using Equation13-1. • TMRx is cleared. • The OCx pin is set. EQUATION 13-1: PWM PERIOD - Exception 1: If PWM duty cycle is 0x0000, the OCx pin will remain low. PWM Period = [(PRx) + 1] • 4 • TOSC • - Exception 2: If duty cycle is greater than PRx, (TMRx Prescale Value) the pin will remain high. • The PWM duty cycle is latched from OCxRS into PWM frequency is defined as 1/[PWM period]. OCxR. • The corresponding timer interrupt flag is set. See Figure13-2 for key PWM period comparisons. Timer3 is referred to in the figure for clarity. FIGURE 13-2: PWM OUTPUT TIMING Period Duty Cycle TMR3 = PR3 TMR3 = PR3 T3IF = 1 T3IF = 1 (Interrupt Flag) (Interrupt Flag) OCxR = OCxRS OCxR = OCxRS TMR3 = Duty Cycle (OCxR) TMR3 = Duty Cycle (OCxR) © 2011 Microchip Technology Inc. DS70150E-page 87

dsPIC30F6010A/6015 13.5 Output Compare Operation During 13.7 Output Compare Interrupts CPU Sleep Mode The output compare channels have the ability to gener- When the CPU enters the Sleep mode, all internal ate an interrupt on a compare match, for whichever clocks are stopped. Therefore, when the CPU enters match mode has been selected. the Sleep state, the output compare channel will drive For all modes except the PWM mode, when a compare the pin to the active state that was observed prior to event occurs, the respective interrupt flag (OCxIF) is entering the CPU Sleep state. asserted and an interrupt will be generated, if enabled. For example, if the pin was high when the CPU The OCxIF bit is located in the corresponding IFS STA- entered the Sleep state, the pin will remain high. Like- TUS register and must be cleared in software. The wise, if the pin was low when the CPU entered the interrupt is enabled via the respective Compare Inter- Sleep state, the pin will remain low. In either case, the rupt Enable bit (OCxIE), located in the corresponding output compare module will resume operation when IEC Control register. the device wakes up. For the PWM mode, when an event occurs, the respec- tive Timer Interrupt Flag (T2IF or T3IF) is asserted and 13.6 Output Compare Operation During an interrupt will be generated, if enabled. The IF bit is CPU Idle Mode located in the IFS0 STATUS register, and must be cleared in software. The interrupt is enabled via the When the CPU enters the Idle mode, the output respective Timer Interrupt Enable bit (T2IE or T3IE), compare module can operate with full functionality. located in the IEC0 Control register. The output The output compare channel will operate during the compare interrupt flag is never set during the PWM CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at mode of operation. logic 0 and the selected time base (Timer2 or Timer3) is enabled and the TSIDL bit of the selected timer is set to logic 0. DS70150E-page 88 © 2011 Microchip Technology Inc.

© TABLE 13-1: OUTPUT COMPARE REGISTER MAP(1) 2 01 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 M OC1RS 0180 Output Compare 1 Secondary Register 0000 0000 0000 0000 ic ro OC1R 0182 Output Compare 1 Main Register 0000 0000 0000 0000 c hip OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000 T OC2RS 0186 Output Compare 2 Secondary Register 0000 0000 0000 0000 e c h OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000 n olo OC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSE OCM<2:0> 0000 0000 0000 0000 g y OC3RS 018C Output Compare 3 Secondary Register 0000 0000 0000 0000 Inc OC3R 018E Output Compare 3 Main Register 0000 0000 0000 0000 . OC3CON 0190 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000 OC4RS 0192 Output Compare 4 Secondary Register 0000 0000 0000 0000 OC4R 0194 Output Compare 4 Main Register 0000 0000 0000 0000 OC4CON 0196 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000 OC5RS 0198 Output Compare 5 Secondary Register 0000 0000 0000 0000 OC5R 019A Output Compare 5 Main Register 0000 0000 0000 0000 OC5CON 019C — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000 OC6RS 019E Output Compare 6 Secondary Register 0000 0000 0000 0000 OC6R 01A0 Output Compare 6 Main Register 0000 0000 0000 0000 OC6CON 01A2 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000 OC7RS 01A4 Output Compare 7 Secondary Register 0000 0000 0000 0000 d OC7R 01A6 Output Compare 7 Main Register 0000 0000 0000 0000 s OC7CON 01A8 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000 P OC8RS 01AA Output Compare 8 Secondary Register 0000 0000 0000 0000 I OC8R 01AC Output Compare 8 Main Register 0000 0000 0000 0000 C OC8CON 01AE — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000 3 Legend: — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 0 F 6 0 1 0 D A S 7 0 / 15 6 0 E 0 -p a 1 g e 8 5 9

dsPIC30F6010A/6015 NOTES: DS70150E-page 90 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 14.0 QUADRATURE ENCODER The operational features of the QEI include: INTERFACE (QEI) MODULE • Three input channels for two phase signals and index pulse Note: This data sheet summarizes features of • 16-bit up/down position counter this group ofdsPIC30F devices and is not • Count direction status intended to be a complete reference • Position Measurement (x2 and x4) mode source. For more information on the CPU, peripherals, register descriptions and • Programmable digital noise filters on inputs general device functionality, refer to the • Alternate 16-bit Timer/Counter mode “dsPIC30F Family Reference Manual” • Quadrature Encoder Interface interrupts (DS70046). These operating modes are determined by setting the This section describes the Quadrature Encoder Inter- appropriate bits, QEIM<2:0> (QEICON<10:8>). face (QEI) module and associated operational modes. Figure14-1 depicts the Quadrature Encoder Interface The QEI module provides the interface to incremental block diagram. encoders for obtaining mechanical position data. FIGURE 14-1: QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM TQCKPS<1:0> Sleep Input TQCS 2 TCY 0 Synchronize Prescaler Det 1, 8, 64, 256 1 1 QEIM<2:0> 0 QEIIF D Q TQGATE Event CK Q Flag 16-bit Up/Down Counter Programmable 2 (POSCNT) QEA Digital Filter Quadrature Reset Encoder UPDN_SRC Interface Logic Comparator/ Zero Detect Equal 0 QEICON<11> 3 QEIM<2:0> 1 Mode Select Max Count Register (MAXCNT) Programmable QEB Digital Filter Programmable INDX Digital Filter 3 PCDOUT Existing Pin Logic 0 UPDN Up/Down 1 © 2011 Microchip Technology Inc. DS70150E-page 91

dsPIC30F6010A/6015 14.1 Quadrature Encoder Interface If the POSRES bit is set to ‘1’, then the position counter Logic is reset when the index pulse is detected. If the POSRES bit is set to ‘0’, then the position counter is not A typical incremental (a.k.a. optical) encoder has three reset when the index pulse is detected. The position outputs: Phase A, Phase B, and an index pulse. These counter will continue counting up or down, and will be signals are useful and often required in position and reset on the rollover or underflow condition. speed control of ACIM and SR motors. The interrupt is still generated on the detection of the The two channels, Phase A (QEA) and Phase B (QEB), index pulse and not on the position counter overflow/ have a unique relationship. If Phase A leads Phase B, underflow. then the direction (of the motor) is deemed positive or forward. If Phase A lags Phase B, then the direction (of 14.2.3 COUNT DIRECTION STATUS the motor) is deemed negative or reverse. As mentioned in the previous section, the QEI logic A third channel, termed index pulse, occurs once per generates an UPDN signal, based upon the relation- revolution and is used as a reference to establish an ship between Phase A and Phase B. In addition to the absolute position. The index pulse coincides with output pin, the state of this internal UPDN signal is Phase A and Phase B, both low. supplied to a SFR bit, UPDN (QEICON<11>) as a read- only bit. To place the state of this signal on an I/O pin, 14.2 16-bit Up/Down Position Counter the SFR bit, PCDOUT (QEICON<6>), must be 1. Mode 14.3 Position Measurement Mode The 16-bit up/down counter counts up or down on every count pulse, which is generated by the difference There are two measurement modes which are of the Phase A and Phase B input signals. The counter supported and are termed x2 and x4. These modes are acts as an integrator, whose count value is proportional selected by the QEIM<2:0> mode select bits located in to position. The direction of the count is determined by SFR QEICON<10:8>. the UPDN signal, which is generated by the When control bits QEIM<2:0> = 100 or 101, the x2 Quadrature Encoder Interface logic. Measurement mode is selected and the QEI logic only looks at the Phase A input for the position counter 14.2.1 POSITION COUNTER ERROR increment rate. Every rising and falling edge of the CHECKING Phase A signal causes the position counter to be incre- Position count error checking in the QEI is provided for mented or decremented. The Phase B signal is still and indicated by the CNTERR bit (QEICON<15>). The utilized for the determination of the counter direction, error checking only applies when the position counter just as in the x4 mode. is configured for Reset on the Index Pulse modes Within the x2 Measurement mode, there are two (QEIM<2:0> = ‘110’ or ‘100’). In these modes, the variations of how the position counter is reset: contents of the POSCNT register are compared with 1. Position counter reset by detection of index the values (0xFFFF or MAXCNT + 1, depending on pulse, QEIM<2:0> = 100. direction). If these values are detected, an error condi- tion is generated by setting the CNTERR bit and a QEI 2. Position counter reset by match with MAXCNT, count error interrupt is generated. The QEI count error QEIM<2:0> = 101. interrupt can be disabled by setting the CEID bit When control bits QEIM<2:0> = 110 or 111, the x4 (DFLTCON<8>). The position counter continues to Measurement mode is selected and the QEI logic looks count encoder edges after an error has been detected. at both edges of the Phase A and Phase B input sig- The POSCNT register continues to count up/down until nals. Every edge of both signals causes the position a natural rollover/underflow. No interrupt is generated counter to increment or decrement. for the natural rollover/underflow event. The CNTERR Within the x4 Measurement mode, there are two bit is a read/write bit and reset in software by the user. variations of how the position counter is reset: 14.2.2 POSITION COUNTER RESET 1. Position counter reset by detection of index pulse, QEIM<2:0> = 110. The Position Counter Reset Enable bit, POSRES (QEI<2>), controls whether the position counter is reset 2. Position counter reset by match with MAXCNT, when the index pulse is detected. This bit is only QEIM<2:0> = 111. applicable when QEIM<2:0> = 100 or 110. The x4 Measurement mode provides for finer resolu- tion data (more position counts) for determining motor position. DS70150E-page 92 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 14.4 Programmable Digital Noise In addition, control bit, UDSRC (QEICON<0>), deter- Filters mines whether the timer count direction state is based on the logic state, written into the UPDN control/Status The digital noise filter section is responsible for bit (QEICON<11>), or the QEB pin state. When rejecting noise on the incoming quadrature signals. UDSRC = 1, the timer count direction is controlled from Schmitt Trigger inputs and a three-clock cycle delay the QEB pin. Likewise, when UDSRC = 0, the timer filter combine to reject low level noise and large, short count direction is controlled by the UPDN bit. duration noise spikes that typically occur in noise prone Note: This Timer does not support the External applications, such as a motor system. Asynchronous Counter mode of operation. The filter ensures that the filtered output signal is not If using an external clock source, the clock permitted to change until a stable value has been will automatically be synchronized to the registered for three consecutive clock cycles. internal instruction cycle. For the QEA, QEB and INDX pins, the clock divide frequency for the digital filter is programmed by bits 14.6 QEI Module Operation During CPU QECK<2:0> (DFLTCON<6:4>) and are derived from Sleep Mode the base instruction cycle TCY. To enable the filter output for channels QEA, QEB and 14.6.1 QEI OPERATION DURING CPU INDX, the QEOUT bit must be ‘1’. The filter network for SLEEP MODE all channels is disabled on POR and BOR. The QEI module will be halted during the CPU Sleep mode. 14.5 Alternate 16-bit Timer/Counter 14.6.2 TIMER OPERATION DURING CPU When the QEI module is not configured for the QEI SLEEP MODE mode QEIM<2:0> = 001, the module can be configured as a simple 16-bit timer/counter. The setup and control During CPU Sleep mode, the timer will not operate, of the auxiliary timer is accomplished through the QEI- because the internal clocks are disabled. CON SFR register. This timer functions identically to Timer1. The QEA pin is used as the timer clock input. 14.7 QEI Module Operation During CPU When configured as a timer, the POSCNT register Idle Mode serves as the Timer Count register and the MAXCNT Since the QEI module can function as a Quadrature register serves as the Period register. When a Timer/ Encoder Interface, or as a 16-bit timer, the following Period register match occur, the QEI interrupt flag will section describes operation of the module in both be asserted. modes. The only exception between the general purpose timers and this timer is the added feature of external 14.7.1 QEI OPERATION DURING CPU IDLE up/down input select. When the UPDN pin is asserted MODE high, the timer will increment up. When the UPDN pin When the CPU is placed in the Idle mode, the QEI is asserted low, the timer will be decremented. module will operate if the QEISIDL bit (QEICON<13>) Note: Changing the operational mode (i.e., from = 0. This bit defaults to a logic ‘0’ upon executing POR QEI to Timer or vice versa), will not affect and BOR. For halting the QEI module during the CPU the Timer/Position Count register contents. Idle mode, QEISIDL should be set to ‘1’. The UPDN control/Status bit (QEICON<11>) can be used to select the count direction state of the Timer register. When UPDN = 1, the timer will count up. When UPDN = 0, the timer will count down. © 2011 Microchip Technology Inc. DS70150E-page 93

dsPIC30F6010A/6015 14.7.2 TIMER OPERATION DURING CPU 14.8 Quadrature Encoder Interface IDLE MODE Interrupts When the CPU is placed in the Idle mode and the QEI The Quadrature Encoder Interface has the ability to module is configured in the 16-bit Timer mode, the generate an interrupt on occurrence of the following 16-bit timer will operate if the QEISIDL bit (QEI- events: CON<13>) = 0. This bit defaults to a logic ‘0’ upon executing POR and BOR. For halting the timer module • Interrupt on 16-bit up/down position counter during the CPU Idle mode, QEISIDL should be set rollover/underflow to‘1’. • Detection of qualified index pulse, or if CNTERR bit is set If the QEISIDL bit is cleared, the timer will function normally, as if the CPU Idle mode had not been • Timer period match event (overflow/underflow) entered. • Gate accumulation event The QEI Interrupt Flag bit, QEIIF, is asserted upon occurrence of any of the above events. The QEIIF bit must be cleared in software. QEIIF is located in the IFS2 STATUS register. Enabling an interrupt is accomplished via the respec- tive enable bit, QEIIE. The QEIIE bit is located in the IEC2 Control register. DS70150E-page 94 © 2011 Microchip Technology Inc.

© TABLE 14-1: QEI REGISTER MAP(1) 2 011 NSaFmRe Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State M ic QEICON 0122 CNTERR — QEISIDL INDX UPDN QEIM<2:0> SWPAB PCDOUT TQGATE TQCKPS<1:0> POSRES TQCS UDSRC 0000 0000 0000 0000 ro ch DFLTCON 0124 — — — — — IMV<1:0> CEID QEOUT QECK<2:0> — — — — 0000 0000 0000 0000 ip T POSCNT 0126 Position Counter<15:0> 0000 0000 0000 0000 e c MAXCNT 0128 Maximun Count<15:0> 1111 1111 1111 1111 h no Legend: — = unimplemented bit, read as ‘0’ lo Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. g y In c . d s P I C 3 0 F 6 0 1 0 D A S 7 0 / 15 6 0 E 0 -p a 1 g e 9 5 5

dsPIC30F6010A/6015 NOTES: DS70150E-page 96 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 15.0 MOTOR CONTROL PWM The Motor Control PWM module has the following MODULE features: • Eight PWM I/O pins with four duty cycle generators Note: This data sheet summarizes features of • Up to 16-bit resolution this group ofdsPIC30F devices and is not • ‘On-the-Fly’ PWM frequency changes intended to be a complete reference • Edge and Center-Aligned Output modes source. For more information on the CPU, peripherals, register descriptions and gen- • Single Pulse Generation mode eral device functionality, refer to the • Interrupt support for asymmetrical updates in “dsPIC30F Family Reference Manual” Center-Aligned mode (DS70046). • Output override control for Electrically Commutative Motor (ECM) operation This module simplifies the task of generating multiple, • ‘Special Event’ comparator for scheduling other synchronized Pulse-Width Modulated outputs. In partic- peripheral events ular, the following power and motion control applications are supported by the PWM module: • Fault pins to optionally drive each of the PWM output pins to a defined state • Three Phase AC Induction Motor • Duty cycle updates are configurable to be • Switched Reluctance (SR) Motor immediate or synchronized to the PWM time base • Brushless DC (BLDC) Motor This module contains four duty cycle generators, num- • Uninterruptible Power Supply (UPS) bered 1 through 4. The module has eight PWM output pins, numbered PWM1H/PWM1L through PWM4H/ PWM4L. The eight I/O pins are grouped into high/low numbered pairs, denoted by the suffix H or L, respec- tively. For complementary loads, the low PWM pins are always the complement of the corresponding high I/O pin. The Motor Control PWM module allows several modes of operation which are beneficial for specific power control applications. © 2011 Microchip Technology Inc. DS70150E-page 97

dsPIC30F6010A/6015 FIGURE 15-1: PWM MODULE BLOCK DIAGRAM PWMCON1 PWM Enable and Mode SFRs PWMCON2 DTCON1 Dead-Time Control SFRs DTCON2 FLTACON Fault Pin Control SFRs FLTBCON PWM Manual OVDCON Control SFR PWM Generator 4 PDC4 Buffer s u B a PDC4 at D 16-bit Comparator ChaGOnvenenerelr ri4da etDo Ler oaagdni-dcT ime PPWWMM44HL PTMR GenPeWraMtor 3 Channel 3 Dead-Time Output PWM3H Generator and Override Logic PWM3L Driver Comparator Block PWM PWM2H Generator 2 Channel 2 Dead-Time Generator and PTPER Override Logic PWM2L PWM Generator 1 Channel 1 Dead-Time PWM1H Generator and PTPER Buffer Override Logic PWM1L PTCON FLTA FLTB Comparator Special Event Special Event Trigger Postscaler SEVTDIR SEVTCMP PTDIR PWM Time Base Note: Details of PWM Generator 1, 2 and 3 are not shown for clarity. DS70150E-page 98 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 15.1 PWM Time Base 15.1.1 FREE-RUNNING MODE The PWM time base is provided by a 15-bit timer with In the Free-Running mode, the PWM time base counts a prescaler and postscaler. The time base is accessible upwards until the value in the Time Base Period regis- via the PTMR SFR. PTMR<15> is a read-only Status ter (PTPER) is matched. The PTMR register is reset on bit, PTDIR, that indicates the present count direction of the following input clock edge and the time base will the PWM time base. If PTDIR is cleared, PTMR is continue to count upwards as long as the PTEN bit counting upwards. If PTDIR is set, PTMR is counting remains set. downwards. The PWM time base is configured via the When the PWM time base is in the Free-Running mode PTCON SFR. The time base is enabled/disabled by (PTMOD<1:0> = 00), an interrupt event is generated setting/clearing the PTEN bit in the PTCON SFR. each time a match with the PTPER register occurs and PTMR is not cleared when the PTEN bit is cleared in the PTMR register is reset to zero. The postscaler software. selection bits may be used in this mode of the timer to The PTPER SFR sets the counting period for PTMR. reduce the frequency of the interrupt events. The user must write a 15-bit value to PTPER<14:0>. 15.1.2 SINGLE-SHOT MODE When the value in PTMR<14:0> matches the value in PTPER<14:0>, the time base will either reset to ‘0’, or In the Single-Shot Counting mode, the PWM time base reverse the count direction on the next occurring clock begins counting upwards when the PTEN bit is set. cycle. The action taken depends on the operating When the value in the PTMR register matches the mode of the time base. PTPER register, the PTMR register will be reset on the following input clock edge and the PTEN bit will be Note: If the Period register is set to 0x0000, the cleared by the hardware to halt the time base. timer will stop counting, and the interrupt and the special event trigger will not be When the PWM time base is in the Single-Shot mode generated, even if the special event value (PTMOD<1:0> = 01), an interrupt event is generated is also 0x0000. The module will not update when a match with the PTPER register occurs, the the Period register, if it is already at PTMR register is reset to zero on the following input 0x0000; therefore, the user must disable clock edge, and the PTEN bit is cleared. The postscaler the module in order to update the Period selection bits have no effect in this mode of the timer. register. 15.1.3 CONTINUOUS UP/DOWN The PWM time base can be configured for four different COUNTING MODES modes of operation: In the Continuous Up/Down Counting modes, the PWM • Free-Running mode time base counts upwards until the value in the PTPER • Single-Shot mode register is matched. The timer will begin counting • Continuous Up/Down Count mode downwards on the following input clock edge. The PTDIR bit in the PTMR SFR is read-only and indicates • Continuous Up/Down Count mode with interrupts the counting direction The PTDIR bit is set when the for double updates timer counts downwards. These four modes are selected by the PTMOD<1:0> bits in the PTCON SFR. The Up/Down Counting modes In the Up/Down Counting mode (PTMOD<1:0> = 10), an interrupt event is generated each time the value of support center-aligned PWM generation. The Single- the PTMR register becomes zero and the PWM time Shot mode allows the PWM module to support pulse base begins to count upwards. The postscaler selec- control of certain Electronically Commutative Motors tion bits may be used in this mode of the timer to reduce (ECMs). the frequency of the interrupt events. The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2011 Microchip Technology Inc. DS70150E-page 99

dsPIC30F6010A/6015 15.1.4 DOUBLE UPDATE MODE EQUATION 15-1: PWM PERIOD In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR regis- TPWM =TCY • (PTPER + 1) (cid:129) PTMR Prescale Value ter is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. If the PWM time base is configured for one of the Up/ The Double Update mode provides two additional func- Down Count modes, the PWM period will be given by tions to the user. First, the control loop bandwidth is Equation15-2. doubled because the PWM duty cycles can be updated, twice per period. Second, asymmetrical cen- EQUATION 15-2: PWM PERIOD FOR UP/ ter-aligned PWM waveforms can be generated, which DOWN COUNT are useful for minimizing output waveform distortion in certain motor control applications. TPWM =TCY (cid:129) 2 (cid:129) (PTPER + 1) (cid:129) PTMR Prescale Value Note: Programming a value of 0x0001 in the Period register could generate a continu- ous interrupt pulse, and hence, must be The maximum resolution (in bits) for a given device avoided. oscillator and PWM frequency can be determined using Equation15-3: 15.1.5 PWM TIME BASE PRESCALER The input clock to PTMR (FOSC/4), has prescaler EQUATION 15-3: PWM RESOLUTION options of 1:1, 1:4, 1:16, or 1:64, selected by control bits, PTCKPS<1:0>, in the PTCON SFR. The prescaler log (2 • TPWM/TCY) Resolution = counter is cleared when any of the following occurs: log (2) • a write to the PTMR register • a write to the PTCON register • any device Reset 15.3 Edge-Aligned PWM PTMR is not cleared when PTCON is written. Edge-aligned PWM signals are produced by the module when the PWM time base is in the Free-Running or 15.1.6 PWM TIME BASE POSTSCALER Single-Shot mode. For edge-aligned PWM outputs, the The match output of PTMR can optionally be post- output has a period specified by the value in PTPER scaled through a 4-bit postscaler (which gives a 1:1 to and a duty cycle specified by the appropriate Duty Cycle 1:16 scaling). register (see Figure15-2). The PWM output is driven active at the beginning of the period (PTMR = 0) and is The postscaler counter is cleared when any of the driven inactive when the value in the Duty Cycle register following occurs: matches PTMR. • a write to the PTMR register If the value in a particular Duty Cycle register is zero, • a write to the PTCON register then the output on the corresponding PWM pin will be • any device Reset inactive for the entire PWM period. In addition, the out- PTMR is not cleared when PTCON is written. put on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is greater 15.2 PWM Period than the value held in the PTPER register. PTPER is a 15-bit, double-buffered register that sets the FIGURE 15-2: EDGE-ALIGNED PWM counting period for the PWM time base. The PTPER buf- fer is loaded into the PTPER register at these instants: New Duty Cycle Latched • Free-Running and Single-Shot modes: When the PTMR register is reset to zero after a match with PTPER the PTPER register. PTMR • Up/Down Counting modes: When the PTMR Value register is zero. The value held in the PTPER buffer is automatically 0 loaded into the PTPER register when the PWM time base is disabled (PTEN = 0). Duty Cycle The PWM period can be determined using Period Equation15-1: DS70150E-page 100 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 15.4 Center-Aligned PWM 15.5.1 DUTY CYCLE REGISTER BUFFERS Center-aligned PWM signals are produced by the mod- The four PWM Duty Cycle registers are double- ule when the PWM time base is configured in an Up/ buffered to allow glitchless updates of the PWM Down Counting mode (see Figure15-3). outputs. For each duty cycle, there is a Duty Cycle reg- ister that is accessible by the user and a second Duty The PWM compare output is driven to the active state Cycle register that holds the actual compare value when the value of the Duty Cycle register matches the used in the present PWM period. value of PTMR and the PWM time base is counting downwards (PTDIR = 1). The PWM compare output is For edge-aligned PWM output, a new duty cycle value driven to the inactive state when the PWM time base is will be updated whenever a match with the PTPER reg- counting upwards (PTDIR = 0) and the value in the ister occurs and PTMR is reset. The contents of the PTMR register matches the duty cycle value. duty cycle buffers are automatically loaded into the Duty Cycle registers when the PWM time base is dis- If the value in a particular Duty Cycle register is zero, abled (PTEN = 0) and the UDIS bit is cleared in then the output on the corresponding PWM pin will be PWMCON2. inactive for the entire PWM period. In addition, the out- put on the PWM pin will be active for the entire PWM When the PWM time base is in the Up/Down Counting period if the value in the Duty Cycle register is equal to mode, new duty cycle values are updated when the the value held in the PTPER register. value of the PTMR register is zero and the PWM time base begins to count upwards. The contents of the duty cycle buffers are automatically loaded into the Duty FIGURE 15-3: CENTER-ALIGNED PWM Cycle registers when the PWM time base is disabled Period/2 (PTEN = 0). PTPER When the PWM time base is in the Up/Down Counting PTMR mode with double updates, new duty cycle values are Value Duty updated when the value of the PTMR register is zero, Cycle and when the value of the PTMR register matches the value in the PTPER register. The contents of the duty cycle buffers are automatically loaded into the Duty 0 Cycle registers when the PWM time base is disabled (PTEN = 0). 15.5.2 DUTY CYCLE IMMEDIATE UPDATES Period When the Immediate Update Enable bit is set (IUE = 1), any write to the Duty Cycle registers will update the new duty cycle value immediately. This feature gives 15.5 PWM Duty Cycle Comparison the option to the user to allow immediate updates of the Units active PWM Duty Cycle registers instead of waiting for There are four 16-bit Special Function Registers the end of the current time base period. System stabil- (PDC1, PDC2, PDC3 and PDC4) used to specify duty ity is improved in closed loop servo applications by cycle values for the PWM module. reducing the delay between system observation and the issuance of system corrective commands when The value in each Duty Cycle register determines the immediate updates are enabled (IUE = 1). amount of time that the PWM output is in the active state. The Duty Cycle registers are 16-bits wide. The If the PWM output is active at the time the new duty LSb of a Duty Cycle register determines whether the cycle is written and the new duty cycle is less than the PWM edge occurs in the beginning. Thus, the PWM current time base value, the PWM pulse width will be resolution is effectively doubled. shortened. If the PWM output is active at the time the new duty cycle is written and the new duty cycle is greater than the current time base value, the PWM pulse width will be lengthened. If the PWM output is inactive at the time the new duty cycle is written and the new duty cycle is greater than the current time base value, the PWM output will become active immediately and will remain active for the new written duty cycle value. © 2011 Microchip Technology Inc. DS70150E-page 101

dsPIC30F6010A/6015 15.6 Complementary PWM Operation 15.7.2 DEAD-TIME ASSIGNMENT In the Complementary mode of operation, each pair of The DTCON2 SFR contains control bits that allow the PWM outputs is obtained by a complementary PWM dead times to be assigned to each of the complemen- signal. A dead time may be optionally inserted during tary outputs. Table15-1 summarizes the function of device switching, when both outputs are inactive for a each dead-time selection control bit. short period (Refer to Section15.7 “Dead-Time Generators”). TABLE 15-1: DEAD-TIME SELECTION BITS In Complementary mode, the duty cycle comparison Bit Selects units are assigned to the PWM outputs as follows: DTS1A PWM1L/PWM1H active edge dead time. • PDC1 register controls PWM1H/PWM1L outputs DTS1I PWM1L/PWM1H inactive edge dead time. • PDC2 register controls PWM2H/PWM2L outputs DTS2A PWM2L/PWM2H active edge dead time. • PDC3 register controls PWM3H/PWM3L outputs DTS2I PWM2L/PWM2H inactive edge dead time. • PDC4 register controls PWM4H/PWM4L outputs DTS3A PWM3L/PWM3H active edge dead time. The Complementary mode is selected for each PWM DTS3I PWM3L/PWM3H inactive edge dead time. I/O pin pair by clearing the appropriate PMODx bit in the DTS4A PWM4L/PWM4H active edge dead time. PWMCON1 SFR. The PWM I/O pins are set to DTS4I PWM4L/PWM4H inactive edge dead time. Complementary mode by default upon a device Reset. 15.7.3 DEAD-TIME RANGES 15.7 Dead-Time Generators The amount of dead time provided by each dead-time Dead-time generation may be provided when any of unit is selected by specifying the input clock prescaler the PWM I/O pin pairs are operating in the value and a 6-bit unsigned value. The amount of dead Complementary Output mode. The PWM outputs use time provided by each unit may be set independently. Push-Pull drive circuits. Due to the inability of the Four input clock prescaler selections have been pro- power output devices to switch instantaneously, some vided to allow a suitable range of dead times, based on amount of time must be provided between the turn off the device operating frequency. The clock prescaler event of one PWM output in a complementary pair and option may be selected independently for each of the the turn on event of the other transistor. two dead-time values. The dead-time clock prescaler The PWM module allows two different dead times to be values are selected using the DTAPS<1:0> and programmed. These two dead times may be used in DTBPS<1:0> control bits in the DTCON1 SFR. One of one of two methods described below to increase user four clock prescaler options (TCY, 2 TCY, 4 TCY or 8 TCY) flexibility: may be selected for each of the dead-time values. • The PWM output signals can be optimized for After the prescaler values are selected, the dead time different turn off times in the high side and low for each unit is adjusted by loading two 6-bit unsigned side transistors in a complementary pair of tran- values into the DTCON1 SFR. sistors. The first dead time is inserted between The dead-time unit prescalers are cleared on the the turn off event of the lower transistor of the following events: complementary pair and the turn on event of the • On a load of the down timer due to a duty cycle upper transistor. The second dead time is inserted comparison edge event. between the turn off event of the upper transistor and the turn on event of the lower transistor. • On a write to the DTCON1 or DTCON2 registers. • The two dead times can be assigned to individual • On any device Reset. PWM I/O pin pairs. This Operating mode allows Note: The user should not modify the DTCON1 the PWM module to drive different transistor/load or DTCON2 values while the PWM mod- combinations with each complementary PWM I/O ule is operating (PTEN = 1). Unexpected pin pair. results may occur. 15.7.1 DEAD-TIME GENERATORS Each complementary output pair for the PWM module has a 6-bit down counter that is used to produce the dead-time insertion. As shown in Figure15-4, each dead-time unit has a rising and falling edge detector connected to the duty cycle comparison output. DS70150E-page 102 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 15-4: DEAD-TIME TIMING DIAGRAM Duty Cycle Generator PWMxH PWMxL Time selected by DTSxA bit (A or B) Time selected by DTSxI bit (A or B) 15.8 Independent PWM Output 15.10 PWM Output Override An independent PWM Output mode is required for driv- The PWM output override bits allow the user to manu- ing certain types of loads. A particular PWM output pair ally drive the PWM I/O pins to specified logic states, is in the Independent Output mode when the corre- independent of the duty cycle comparison units. sponding PMOD bit in the PWMCON1 register is set. All control bits associated with the PWM output over- No dead-time control is implemented between adjacent ride function are contained in the OVDCON register. PWM I/O pins when the module is operating in the The upper half of the OVDCON register contains eight Independent mode and both I/O pins are allowed to be bits, POVDxH<4:1> and POVDxL<4:1>, that determine active simultaneously. which PWM I/O pins will be overridden. The lower half In the Independent mode, each duty cycle generator is of the OVDCON register contains eight bits, connected to both of the PWM I/O pins in an output POUTxH<4:1> and POUTxL<4:1>, that determine the pair. By using the associated Duty Cycle register and state of the PWM I/O pins when a particular output is the appropriate bits in the OVDCON register, the user overridden via the POVD bits. may select the following signal output options for each PWM I/O pin operating in the Independent mode: 15.10.1 COMPLEMENTARY OUTPUT MODE • I/O pin outputs PWM signal When a PWMxL pin is driven active via the OVDCON register, the output signal is forced to be the comple- • I/O pin inactive ment of the corresponding PWMxH pin in the pair. • I/O pin active Dead-time insertion is still performed when PWM channels are overridden manually. 15.9 Single-Pulse PWM Operation 15.10.2 OVERRIDE SYNCHRONIZATION The PWM module produces single pulse outputs when the PTCON control bits PTMOD<1:0> = 10. Only edge- If the OSYNC bit in the PWMCON2 register is set, all aligned outputs may be produced in the Single-Pulse output overrides performed via the OVDCON register mode. In Single-Pulse mode, the PWM I/O pin(s) are are synchronized to the PWM time base. Synchronous driven to the active state when the PTEN bit is set. output overrides occur at the following times: When a match with a Duty Cycle register occurs, the • Edge-Aligned mode, when PTMR is zero. PWM I/O pin is driven to the inactive state. When a • Center-Aligned modes, when PTMR is zero and match with the PTPER register occurs, the PTMR when the value of PTMR matches PTPER. register is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared, and an interrupt is generated. © 2011 Microchip Technology Inc. DS70150E-page 103

dsPIC30F6010A/6015 15.11 PWM Output and Polarity Control 15.12.2 FAULT STATES There are three device Configuration bits associated The FLTACON and FLTBCON Special Function Regis- with the PWM module that provide PWM output pin ters have eight bits each that determine the state of control: each PWM I/O pin when it is overridden by a Fault input. When these bits are cleared, the PWM I/O pin is • HPOL Configuration bit driven to the inactive state. If the bit is set, the PWM I/ • LPOL Configuration bit O pin will be driven to the active state. The active and • PWMPIN Configuration bit inactive states are referenced to the polarity defined for each PWM I/O pin (HPOL and LPOL polarity control These three bits in the FBORPOR Configuration regis- bits). ter (see Section21.6 “Device Configuration Regis- ters”) work in conjunction with the four PWM Enable A special case exists when a PWM module I/O pair is bits (PENxH and PENxL) located in the PWMCON1 in the Complementary mode and both pins are pro- SFR. The Configuration bits and PWM Enable bits grammed to be active on a Fault condition. The ensure that the PWM pins are in the correct states after PWMxH pin always has priority in the Complementary a device Reset occurs. The PWMPIN configuration mode, so that both I/O pins cannot be driven active fuse allows the PWM module outputs to be optionally simultaneously. enabled on a device Reset. If PWMPIN = 0, the PWM outputs will be driven to their inactive states at Reset. If 15.12.3 FAULT PIN PRIORITY PWMPIN = 1 (default), the PWM outputs will be tri- If both Fault input pins have been assigned to control a stated. The HPOL bit specifies the polarity for the particular PWM I/O pin, the Fault state programmed for PWMxH outputs, whereas the LPOL bit specifies the the Fault A input pin will take priority over the Fault B polarity for the PWMxL outputs. input pin. 15.11.1 OUTPUT PIN CONTROL 15.12.4 FAULT INPUT MODES The PENxH and PENxL control bits in the PWMCON1 Each of the Fault input pins has two modes of SFR enable each high PWM output pin and each low operation: PWM output pin, respectively. If a particular PWM out- • Latched Mode: When the Fault pin is driven low, put pin is not enabled, it is treated as a general purpose the PWM outputs will go to the states defined in I/O pin. the FLTACON/FLTBCON register. The PWM out- puts will remain in this state until the Fault pin is 15.12 PWM Fault Pins driven high and the corresponding interrupt flag There are two Fault pins (FLTA and FLTB) associated has been cleared in software. When both of these with the PWM module. When asserted, these pins can actions have occurred, the PWM outputs will optionally drive each of the PWM I/O pins to a defined return to normal operation at the beginning of the state. next PWM cycle or half-cycle boundary. If the interrupt flag is cleared before the Fault condition 15.12.1 FAULT PIN ENABLE BITS ends, the PWM module will wait until the Fault pin is no longer asserted, to restore the outputs. The FLTACON and FLTBCON SFRs each have 4 con- trol bits that determine whether a particular pair of • Cycle-by-Cycle Mode: When the Fault input pin PWM I/O pins is to be controlled by the Fault input pin. is driven low, the PWM outputs remain in the To enable a specific PWM I/O pin pair for Fault defined Fault states for as long as the Fault pin is overrides, the corresponding bit should be set in the held low. After the Fault pin is driven high, the FLTACON or FLTBCON register. PWM outputs return to normal operation at the beginning of the following PWM cycle or If all enable bits are cleared in the FLTACON or half-cycle boundary. FLTBCON registers, then the corresponding Fault input pin has no effect on the PWM module and the pin may The Operating mode for each Fault input pin is selected be used as a general purpose interrupt or I/O pin. using the FLTAM and FLTBM control bits in the FLTACON and FLTBCON Special Function Registers. Note: The Fault pin logic can operate indepen- Each of the Fault pins can be controlled manually in dent of the PWM logic. If all the enable bits software. in the FLTACON/FLTBCON register are cleared, then the Fault pin(s) could be used as general purpose interrupt pin(s). Each Fault pin has an interrupt vector, Interrupt Flag bit and Interrupt Priority bits associated with it. DS70150E-page 104 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 15.13 PWM Update Lockout 15.14.1 SPECIAL EVENT TRIGGER POSTSCALER For a complex PWM application, the user may need to write up to four Duty Cycle registers and the Time Base The PWM special event trigger has a postscaler that Period register, PTPER, at a given time. In some appli- allows a 1:1 to 1:16 postscale ratio. The postscaler is cations, it is important that all buffer registers be written configured by writing the SEVOPS<3:0> control bits in before the new duty cycle and period values are loaded the PWMCON2 SFR. for use by the module. The special event output postscaler is cleared on the The PWM update lockout feature is enabled by setting following events: the UDIS control bit in the PWMCON2 SFR. The UDIS • Any write to the SEVTCMP register bit affects all Duty Cycle Buffer registers and the PWM • Any device Reset time base period buffer, PTPER. No duty cycle changes or period value changes will have effect while 15.15 PWM Operation During CPU Sleep UDIS = 1. Mode If the IUE bit is set, any change to the Duty Cycle reg- isters will be immediately updated regardless of the The Fault A and Fault B input pins have the ability to UDIS bit state. The PWM Period register updates wake the CPU from Sleep mode. The PWM module (PTPER) are not affected by the IUE control bit. generates an interrupt if either of the Fault pins is driven low while in Sleep. 15.14 PWM Special Event Trigger 15.16 PWM Operation During CPU Idle The PWM module has a special event trigger that Mode allows A/D conversions to be synchronized to the PWM time base. The A/D sampling and conversion time may The PTCON SFR contains a PTSIDL control bit. This be programmed to occur at any point within the PWM bit determines if the PWM module will continue to period. The special event trigger allows the user to min- operate or stop when the device enters Idle mode. If imize the delay between the time when A/D conversion PTSIDL = 0, the module will continue to operate. If results are acquired and the time when the duty cycle PTSIDL = 1, the module will stop operation as long as value is updated. the CPU remains in Idle mode. The PWM special event trigger has an SFR named SEVTCMP, and five control bits to control its operation. The PTMR value for which a special event trigger should occur is loaded into the SEVTCMP register. When the PWM time base is in an Up/Down Counting mode, an additional control bit is required to specify the counting phase for the special event trigger. The count phase is selected using the SEVTDIR control bit in the SEVTCMP SFR. If the SEVTDIR bit is cleared, the spe- cial event trigger will occur on the upward counting cycle of the PWM time base. If the SEVTDIR bit is set, the special event trigger will occur on the downward count cycle of the PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down Counting mode. © 2011 Microchip Technology Inc. DS70150E-page 105

D TABLE 15-2: 8-OUTPUT PWM REGISTER MAP(1) d S 70 SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 1 5 P 0E PTCON 01C0 PTEN — PTSIDL — — — — — PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> 0000 0000 0000 0000 -p PTMR 01C2 PTDIR PWM Timer Count Value 0000 0000 0000 0000 I a C g e PTPER 01C4 — PWM Time Base Period Register 0111 1111 1111 1111 1 3 0 SEVTCMP 01C6 SEVTDIR PWM Special Event Compare Register 0000 0000 0000 0000 6 0 PWMCON1 01C8 — — — — PTMOD4 PTMOD3 PTMOD2 PTMOD1 PEN4H PEN3H PEN2H PEN1H PEN4L PEN3L PEN2L PEN1L 0000 0000 1111 1111 F PWMCON2 01CA — — — — SEVOPS<3:0> — — — — — IUE OSYNC UDIS 0000 0000 0000 0000 DTCON1 01CC DTBPS<1:0> Dead-Time B Value DTAPS<1:0> Dead-Time A Value 0000 0000 0000 0000 6 DTCON2 01CE — — — — — — — — DTS4A DTS4I DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I 0000 0000 0000 0000 0 FLTACON 01D0 FAOV4H FAOV4L FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM — — — FAEN4 FAEN3 FAEN2 FAEN1 0000 0000 0000 0000 1 FLTBCON 01D2 FBOV4H FBOV4L FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L FLTBM — — — FBEN4 FBEN3 FBEN2 FBEN1 0000 0000 0000 0000 0 OVDCON 01D4 POVD4H POVD4L POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L POUT4H POUT4L POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 1111 1111 0000 0000 A PDC1 01D6 PWM Duty Cycle 1 Register 0000 0000 0000 0000 / PDC2 01D8 PWM Duty Cycle 2 Register 0000 0000 0000 0000 6 PDC3 01DA PWM Duty Cycle 3 Register 0000 0000 0000 0000 0 PDC4 01DC PWM Duty Cycle 4 Register 0000 0000 0000 0000 1 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ 5 Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F6010A/6015 16.0 SPI MODULE Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer Note: This data sheet summarizes features of is completed, the contents of the shift register this group ofdsPIC30F devices and is not (SPIxSR) is moved to the receive buffer. If any trans- intended to be a complete reference mit data has been written to the buffer register, the source. For more information on the CPU, contents of the transmit buffer are moved to SPIxSR. peripherals, register descriptions and The received data is thus placed in SPIxBUF and the general device functionality, refer to the transmit data in SPIxSR is ready for the next transfer. “dsPIC30F Family Reference Manual” Note: Both the transmit buffer (SPIxTXB) and (DS70046). the receive buffer (SPIxRXB) are mapped The Serial Peripheral Interface (SPI) module is a to the same register address, SPIxBUF. synchronous serial interface. It is useful for communi- In Master mode, the clock is generated by prescaling cating with other peripheral devices such as the system clock. Data is transmitted as soon as a EEPROMs, shift registers, display drivers and A/D value is written to SPIxBUF. The interrupt is generated converters, or other microcontrollers. It is compatible at the middle of the transfer of the last bit. with Motorola’s SPI and SIOP interfaces. In Slave mode, data is transmitted and received as external clock pulses appear on SCK. Again, the inter- 16.1 Operating Function Description rupt is generated when the last bit is latched. If SSx Each SPI module consists of a 16-bit shift register, control is enabled, then transmission and reception SPIxSR (where x = 1 or 2), used for shifting data in are enabled only when SSx = low. The SDOx output and out, and a buffer register, SPIxBUF. A control reg- will be disabled in SSx mode with SSx high. ister, SPIxCON, configures the module. Additionally, a The clock provided to the module is (FOSC/4). This STATUS register, SPIxSTAT, indicates various status clock is then prescaled by the primary (PPRE<1:0>) conditions. and the secondary (SPRE<2:0>) prescale factors. The The serial interface consists of 4 pins: SDIx (Serial CKE bit determines whether transmit occurs on transi- Data Input), SDOx (Serial Data Output), SCKx (Shift tion from active clock state to Idle clock state, or vice Clock Input or Output) and SSx (active-low Slave versa. The CKP bit selects the Idle state (high or low) Select). for the clock. In Master mode operation, SCK is a clock output, but 16.1.1 WORD AND BYTE in Slave mode, it is a clock input. COMMUNICATION A series of eight or sixteen clock pulses shifts out bits A control bit, MODE16 (SPIxCON<10>), allows the from the SPIxSR to SDOx pin and simultaneously module to communicate in either 16-bit or 8-bit mode. shifts in data from SDIx pin. An interrupt is generated 16-bit operation is identical to 8-bit operation, except when the transfer is complete and the corresponding that the number of bits transmitted is 16 instead of 8. interrupt flag bit (SPI1IF or SPI2IF) is set. This inter- rupt can be disabled through an interrupt enable bit The user software must disable the module prior to (SPI1IE or SPI2IE). changing the MODE16 bit. The SPI module is reset when the MODE16 bit is changed by the user. The receive operation is double-buffered. When a complete byte is received, it is transferred from A basic difference between 8-bit and 16-bit operation is SPIxSR to SPIxBUF. that the data is transmitted out of bit 7 of the SPIxSR for 8-bit operation, and data is transmitted out of bit 15 of If the receive buffer is full when new data is being the SPIxSR for 16-bit operation. In both modes, data is transferred from SPIxSR to SPIxBUF, the module will shifted into bit 0 of the SPIxSR. set the SPIROV bit, indicating an overflow condition. The transfer of the data from SPIxSR to SPIxBUF will 16.1.2 SDOx DISABLE not be completed and the new data will be lost. The module will not respond to SCL transitions while SPI- A control bit, DISSDO, is provided to the SPIxCON reg- ROV is ‘1’, effectively disabling the module until SPIx- ister to allow the SDOx output to be disabled. This will BUF is read by user software. allow the SPI module to be connected in an input only configuration. SDO can also be used for general Note: The user must perform reads of SPIxBUF purpose I/O. if the module is used in a transmit only configuration to avoid a receive overflow condition. (SPIROV = 1) © 2011 Microchip Technology Inc. DS70150E-page 107

dsPIC30F6010A/6015 FIGURE 16-1: SPI BLOCK DIAGRAM Internal Data Bus Read Write SPIxBUF SPIxBUF Receive Transmit SPIxSR SDIx bit 0 SDOx Shift clock SS & FSYNC Clock Edge Control Select Control SSx Secondary Primary Prescaler Prescaler FCY 1:1-1:8 1, 4, 16, 64 SCKx Enable Master Clock Note: x = 1 or 2. FIGURE 16-2: SPI MASTER/SLAVE CONNECTION SPI Master SPI Slave SDOx SDIy Serial Input Buffer Serial Input Buffer (SPIxBUF) (SPIyBUF) SDIx SDOy Shift Register Shift Register (SPIxSR) (SPIySR) MSb LSb MSb LSb Serial Clock SCKx SCKy PROCESSOR 1 PROCESSOR 2 Note: x = 1 or 2, y = 1 or 2. DS70150E-page 108 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 16.2 Framed SPI Support 16.4 SPI Operation During CPU Sleep Mode The module supports a basic framed SPI protocol in Master or Slave mode. The control bit, FRMEN, During Sleep mode, the SPI module is shut down. If enables framed SPI support and causes the SSx pin to the CPU enters Sleep mode while an SPI transaction perform the Frame Synchronization pulse (FSYNC) is in progress, then the transmission and reception is function. The control bit SPIFSD determines whether aborted. the SSx pin is an input or an output (i.e., whether the The transmitter and receiver will stop in Sleep mode. module receives or generates the Frame Synchroniza- However, register contents are not affected by tion pulse). The frame pulse is an active-high pulse for entering or exiting Sleep mode. a single SPI clock cycle. When Frame Synchronization is enabled, the data transmission starts only on the 16.5 SPI Operation During CPU Idle subsequent transmit edge of the SPI clock. Mode 16.3 Slave Select Synchronization When the device enters Idle mode, all clock sources The SSx pin allows a Synchronous Slave mode. The remain functional. The SPISIDL bit (SPIxSTAT<13>) SPI must be configured in SPI Slave mode, with SSx selects if the SPI module will stop or continue on Idle. pin control enabled (SSEN = 1). When the SSx pin is If SPISIDL = 0, the module will continue to operate low, transmission and reception are enabled, and the when the CPU enters Idle mode. If SPISIDL = 1, the SDOx pin is driven. When SSx pin goes high, the SDOx module will stop when the CPU enters Idle mode. pin is no longer driven. Also, the SPI module is re- synchronized, and all counters/control circuitry are reset. Therefore, when the SSx pin is asserted low again, transmission/reception will begin at the MSb, even if SSx had been de-asserted in the middle of a transmit/receive. © 2011 Microchip Technology Inc. DS70150E-page 109

D TABLE 16-1: SPI1 REGISTER MAP(1) d S 70 SFR s 1 Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 5 Name P 0 E -p SPI1STAT 0220 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 0000 0000 0000 I a C g SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000 e 1 SPI1BUF 0224 Transmit and Receive Buffer 0000 0000 0000 0000 3 1 0 Legend: — = unimplemented bit, read as ‘0’ 0 Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. F TABLE 16-2: SPI2 REGISTER MAP(1) 6 0 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 SPI2STAT 0226 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 0000 0000 0000 0 SPI2CON 0228 — FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000 A SPI2BUF 022A Transmit and Receive Buffer 0000 0000 0000 0000 Legend: — = unimplemented bit, read as ‘0’ /6 Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 0 1 5 © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F6010A/6015 17.0 I2C™ MODULE 17.1.1 VARIOUS I2C MODES The following types of I2C operation are supported: Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not • I2C Slave operation with 7-bit addressing intended to be a complete reference • I2C Slave operation with 10-bit addressing source. For more information on the CPU, • I2C Master operation with 7-bit or 10-bit addressing peripherals, register descriptions and See the I2C programmer’s model in Figure17-1. general device functionality, refer to the “dsPIC30F Family Reference Manual” 17.1.2 PIN CONFIGURATION IN I2C MODE (DS70046). I2C has a 2-pin interface; pin SCL is clock and pin SDA The Inter-Integrated Circuit™ (I2C™) module provides is data. complete hardware support for both Slave and Multi- Master modes of the I2C serial communication 17.1.3 I2C REGISTERS standard, with a 16-bit interface. I2CCON and I2CSTAT are control and STATUS regis- This module offers the following key features: ters, respectively. The I2CCON register is readable and • I2C interface supporting both Master and Slave writable. The lower 6 bits of I2CSTAT are read-only. The remaining bits of the I2CSTAT are read/write. operation. • I2C Slave mode supports 7-bit and 10-bit addressing. I2CRSR is the shift register used for shifting data, • I2C Master mode supports 7-bit and 10-bit whereas I2CRCV is the buffer register to which data bytes are written, or from which data bytes are read. addressing. I2CRCV is the receive buffer, as shown in Figure 16-1. • I2C port allows bidirectional transfers between I2CTRN is the transmit register to which bytes are written master and slaves. during a transmit operation, as shown in Figure 16-2. • Serial clock synchronization for I2C port can be The I2CADD register holds the slave address. A Status used as a handshake mechanism to suspend and bit, ADD10, indicates 10-bit Address mode. The resume serial transfer (SCLREL control). I2CBRG acts as the Baud Rate Generator reload • I2C supports multi-master operation; detects bus value. collision and will arbitrate accordingly. In receive operations, I2CRSR and I2CRCV together 17.1 Operating Function Description form a double-buffered receiver. When I2CRSR receives a complete byte, it is transferred to I2CRCV and an inter- The hardware fully implements all the master and rupt pulse is generated. During transmission, the slave functions of the I2C Standard and Fast mode I2CTRN is not double-buffered. specifications, as well as 7 and 10-bit addressing. Note: Following a Restart condition in 10-bit Thus, the I2C module can operate either as a slave or mode, the user only needs to match the a master on an I2C bus. first 7-bit address. FIGURE 17-1: PROGRAMMER’S MODEL I2CRCV (8 bits) bit 7 bit 0 I2CTRN (8 bits) bit 7 bit 0 I2CBRG (9 bits) bit 8 bit 0 I2CCON (16 bits) bit 15 bit 0 I2CSTAT (16 bits) bit 15 bit 0 I2CADD (10 bits) bit 9 bit 0 © 2011 Microchip Technology Inc. DS70150E-page 111

dsPIC30F6010A/6015 FIGURE 17-2: I2C™ BLOCK DIAGRAM Internal Data Bus I2CRCV Read Shift SCL Clock I2CRSR LSB SDA Addr_Match Match Detect Write I2CADD Read Start and Stop bit Detect Write T Start, Restart, A Stop bit Generate ST C I2 Read c gi o L Collision ol Detect ntr o Write C N O C C Acknowledge 2 I Read Generation Clock Stretching Write I2CTRN LSB Shift Read Clock Reload Control Write I2CBRG BRG Down Counter Read FCY DS70150E-page 112 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 17.2 I2C Module Addresses 17.3.2 SLAVE RECEPTION The I2CADD register contains the Slave mode If the R_W bit received is a ‘0’ during an address addresses. The register is a 10-bit register. match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL. After 8 bits are If the A10M bit (I2CCON<10>) is ‘0’, the address is received, if I2CRCV is not full or I2COV is not set, interpreted by the module as a 7-bit address. When an I2CRSR is transferred to I2CRCV. ACK is sent on the address is received, it is compared to the 7 Least ninth clock. Significant bits of the I2CADD register. If the RBF flag is set, indicating that I2CRCV is still If the A10M bit is ‘1’, the address is assumed to be a holding data from a previous operation (RBF = 1), then 10-bit address. When an address is received, it will be ACK is not sent; however, the interrupt pulse is gener- compared with the binary value ‘1 1 1 1 0 A9 A8’ ated. In the case of an overflow, the contents of the (where A9, A8 are two Most Significant bits of I2CRSR are not loaded into the I2CRCV. I2CADD). If that value matches, the next address will be compared with the Least Significant 8 bits of Note: The I2CRCV will be loaded if the I2COV I2CADD, as specified in the 10-bit addressing protocol. bit = 1 and the RBF flag = 0. In this case, a read of the I2CRCV was performed, but TABLE 17-1: 7-BIT I2C™ SLAVE the user did not clear the state of the ADDRESSES SUPPORTED BY I2COV bit before the next receive occurred. The Acknowledgement is not dsPIC30F sent (ACK = 1) and the I2CRCV is Address Description updated. 0x00 General call address or start byte 17.4 I2C 10-bit Slave Mode Operation 0x01-0x03 Reserved 0x04-0x07 HS-mode master codes In 10-bit mode, the basic receive and transmit opera- 0x04-0x77 Valid 7-bit addresses tions are the same as in the 7-bit mode. However, the criteria for address match is more complex. 0x78-0x7b Valid 10-bit addresses (lower 7 bits) The I2C specification dictates that a slave must be 0x7c-0x7f Reserved addressed for a write operation, with two address bytes following a Start bit. 17.3 I2C 7-bit Slave Mode Operation The A10M bit is a control bit that signifies that the Once enabled (I2CEN = 1), the slave module will wait address in I2CADD is a 10-bit address rather than a for a Start bit to occur (i.e., the I2C module is ‘Idle’). 7-bit address. The address detection protocol for the Following the detection of a Start bit, 8 bits are shifted first byte of a message address is identical for 7-bit into I2CRSR and the address is compared against and 10-bit messages, but the bits being compared are I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0> different. are compared against I2CRSR<7:1> and I2CRSR<0> I2CADD holds the entire 10-bit address. Upon receiv- is the R_W bit. All incoming bits are sampled on the ing an address following a Start bit, I2CRSR <7:3> is rising edge of SCL. compared against a literal ‘11110’ (the default 10-bit If an address match occurs, an Acknowledgement will address) and I2CRSR<2:1> are compared against be sent, and the Slave Event Interrupt Flag (SI2CIF) is I2CADD<9:8>. If a match occurs and if R_W = 0, the set on the falling edge of the ninth (ACK) bit. The interrupt pulse is sent. The ADD10 bit will be cleared to address match does not affect the contents of the indicate a partial address match. If a match fails or I2CRCV buffer or the RBF bit. R_W = 1, the ADD10 bit is cleared and the module returns to the Idle state. 17.3.1 SLAVE TRANSMISSION The low byte of the address is then received and com- If the R_W bit received is a ‘1’, then the serial port will pared with I2CADD<7:0>. If an address match occurs, go into Transmit mode. It will send ACK on the ninth bit the interrupt pulse is generated and the ADD10 bit is and then hold SCL to ‘0’ until the CPU responds by writ- set, indicating a complete 10-bit address match. If an ing to I2CTRN. SCL is released by setting the SCLREL address match did not occur, the ADD10 bit is cleared bit, and 8 bits of data are shifted out. Data bits are and the module returns to the Idle state. shifted out on the falling edge of SCL, such that SDA is valid during SCL high (see timing diagram). The inter- rupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2011 Microchip Technology Inc. DS70150E-page 113

dsPIC30F6010A/6015 17.4.1 10-BIT MODE SLAVE 17.5.3 CLOCK STRETCHING DURING TRANSMISSION 7-BIT ADDRESSING (STREN = 1) Once a slave is addressed in this fashion, with the full When the STREN bit is set in Slave Receive mode, 10-bit address (we will refer to this state as the SCL line is held low when the buffer register is full. “PRIOR_ADDR_MATCH”), the master can begin The method for stretching the SCL output is the same sending data bytes for a slave reception operation. for both 7 and 10-bit addressing modes. Clock stretching takes place following the ninth clock of 17.4.2 10-BIT MODE SLAVE RECEPTION the receive sequence. On the falling edge of the ninth Once addressed, the master can generate a Repeated clock at the end of the ACK sequence, if the RBF bit is Start, reset the high byte of the address and set the set, the SCLREL bit is automatically cleared, forcing the R_W bit without generating a Stop bit, thus initiating a SCL output to be held low. The user’s ISR must set the slave transmit operation. SCLREL bit before reception is allowed to continue. By holding the SCL line low, the user has time to service 17.5 Automatic Clock Stretch the ISR and read the contents of the I2CRCV before the master device can initiate another receive sequence. In the slave modes, the module can synchronize buffer This will prevent buffer overruns from occurring. reads and write to the master device by clock stretching. Note1: If the user reads the contents of the I2CRCV, clearing the RBF bit before the 17.5.1 TRANSMIT CLOCK STRETCHING falling edge of the ninth clock, the Both 10-bit and 7-bit Transmit modes implement clock SCLREL bit will not be cleared and clock stretching by asserting the SCLREL bit after the falling stretching will not occur. edge of the ninth clock if the TBF bit is cleared, 2: The SCLREL bit can be set in software, indicating the buffer is empty. regardless of the state of the RBF bit. The In Slave Transmit modes, clock stretching is always user should be careful to clear the RBF performed, irrespective of the STREN bit. bit in the ISR before the next receive sequence in order to prevent an overflow Clock synchronization takes place following the ninth condition. clock of the transmit sequence. If the device samples an ACK on the falling edge of the ninth clock, and if the 17.5.4 CLOCK STRETCHING DURING TBF bit is still clear, then the SCLREL bit is auto- 10-BIT ADDRESSING (STREN = 1) matically cleared. The SCLREL being cleared to ‘0’ will assert the SCL line low. The user’s ISR must set Clock stretching takes place automatically during the the SCLREL bit before transmission is allowed to con- addressing sequence. Because this module has a tinue. By holding the SCL line low, the user has time to register for the entire address, it is not necessary for service the ISR and load the contents of the I2CTRN the protocol to wait for the address to be updated. before the master device can initiate another transmit After the address phase is complete, clock stretching sequence. will occur on each data receive or transmit sequence Note1: If the user loads the contents of I2CTRN, as was described earlier. setting the TBF bit before the falling edge of the ninth clock, the SCLREL bit will not 17.6 Software Controlled Clock be cleared and clock stretching will not Stretching (STREN = 1) occur. When the STREN bit is ‘1’, the SCLREL bit may be 2: The SCLREL bit can be set in software, cleared by software to allow software to control the regardless of the state of the TBF bit. clock stretching. The logic will synchronize writes to the SCLREL bit with the SCL clock. Clearing the 17.5.2 RECEIVE CLOCK STRETCHING SCLREL bit will not assert the SCL output until the The STREN bit in the I2CCON register can be used to module detects a falling edge on the SCL output and enable clock stretching in Slave Receive mode. When SCL is sampled low. If the SCLREL bit is cleared by the user while the SCL line has been sampled low, the the STREN bit is set, the SCL pin will be held low at SCL output will be asserted (held low). The SCL out- the end of each data receive sequence. put will remain low until the SCLREL bit is set, and all other devices on the I2C bus have de-asserted SCL. This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. DS70150E-page 114 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 17.7 Interrupts 17.12 I2C Master Operation The I2C module generates two interrupt flags, MI2CIF The master device generates all of the serial clock (I2C Master Interrupt Flag) and SI2CIF (I2C Slave Inter- pulses and the Start and Stop conditions. A transfer is rupt Flag). The MI2CIF interrupt flag is activated on ended with a Stop condition or with a Repeated Start completion of a master message event. The SI2CIF condition. Since the Repeated Start condition is also interrupt flag is activated on detection of a message the beginning of the next serial transfer, the I2C bus will directed to the slave. not be released. In Master Transmitter mode, serial data is output 17.8 Slope Control through SDA, while SCL outputs the serial clock. The The I2C standard requires slope control on the SDA first byte transmitted contains the slave address of the and SCL signals for Fast Mode (400 kHz). The control receiving device (7 bits) and the data direction bit. In bit, DISSLW, enables the user to disable slew rate con- this case, the data direction bit (R_W) is logic ‘0’. Serial trol, if desired. It is necessary to disable the slew rate data is transmitted 8 bits at a time. After each byte is control for 1 MHz mode. transmitted, an ACK bit is received. Start and Stop con- ditions are output to indicate the beginning and the end 17.9 IPMI Support of a serial transfer. In Master Receive mode, the first byte transmitted con- The control bit, IPMIEN, enables the module to support tains the slave address of the transmitting device Intelligent Peripheral Management Interface (IPMI). (7bits) and the data direction bit. In this case, the data When this bit is set, the module accepts and acts upon direction bit (R_W) is logic ‘1’. Thus, the first byte all addresses. transmitted is a 7-bit slave address, followed by a ‘1’ to indicate receive bit. Serial data is received via SDA, 17.10 General Call Address Support while SCL outputs the serial clock. Serial data is The general call address can address all devices. When received 8bits at a time. After each byte is received, an this address is used, all devices should, in theory, ACK bit is transmitted. Start and Stop conditions respond with an acknowledgement. indicate the beginning and end of transmission. The general call address is one of eight addresses 17.12.1 I2C MASTER TRANSMISSION reserved for specific purposes by the I2C protocol. It consists of all ‘0’s with R_W = 0. Transmission of a data byte, a 7-bit address, or the sec- ond half of a 10-bit address is accomplished by simply The general call address is recognized when the Gen- writing a value to I2CTRN register. The user should eral Call Enable bit (GCEN) is set (I2CCON<7> = 1). only write to I2CTRN when the module is in a WAIT Following a Start bit detection, 8 bits are shifted into state. This action will set the buffer full flag (TBF) and I2CRSR and the address is compared with I2CADD, allow the Baud Rate Generator to begin counting and and is also compared with the general call address start the next transmission. Each bit of address/data which is fixed in hardware. will be shifted out onto the SDA pin after the falling If a general call address match occurs, the I2CRSR is edge of SCL is asserted. The Transmit Status Flag, transferred to the I2CRCV after the eighth clock, the TRSTAT (I2CSTAT<14>), indicates that a master RBF flag is set, and on the falling edge of the ninth bit transmit is in progress. (ACK bit), the Master Event Interrupt Flag (MI2CIF) is set. 17.12.2 I2C MASTER RECEPTION When the interrupt is serviced, the source for the Master mode reception is enabled by programming the interrupt can be checked by reading the contents of the Receive Enable (RCEN) bit (I2CCON<3>). The I2C I2CRCV to determine if the address was device-specific, module must be idle before the RCEN bit is set, other- or a general call address. wise the RCEN bit will be disregarded. The Baud Rate Generator begins counting, and on each rollover, the 17.11 I2C Master Support state of the SCL pin toggles, and data is shifted in to the I2CRSR on the rising edge of each clock. As a Master device, six operations are supported. 17.12.3 BAUD RATE GENERATOR • Assert a Start condition on SDA and SCL. • Assert a Restart condition on SDA and SCL. In I2C Master mode, the reload value for the BRG is • Write to the I2CTRN register initiating located in the I2CBRG register. When the BRG is transmission of data/address. loaded with this value, the BRG counts down to ‘0’ and stops until another reload has taken place. If clock arbi- • Generate a Stop condition on SDA and SCL. tration is taking place, for instance, the BRG is reloaded • Configure the I2C port to receive data. when the SCL pin is sampled high. • Generate an ACK condition at the end of a received byte of data. © 2011 Microchip Technology Inc. DS70150E-page 115

dsPIC30F6010A/6015 As per the I2C standard, FSCL may be 100 kHz or The Master will continue to monitor the SDA and SCL 400kHz. However, the user can specify any baud rate pins, and if a Stop condition occurs, the MI2CIF bit will up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal. be set. A write to the I2CTRN will start the transmission of data EQUATION 17-1: SERIAL CLOCK RATE at the first data bit, regardless of where the transmitter left off when bus collision occurred. I2CBRG = ⎝⎛F--F--S-C--C--Y--L--–1---,-----1--F-1---C1---,-Y----1---1---1--⎠⎞ –1 Ionn a th Meu dltei-tMecatisotne ro ef nSvtairrotn amnedn St,t othpe c oinntedritriuopnts g aellnoewras ttiohne determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the I2CSTAT 17.12.4 CLOCK ARBITRATION register, or the bus is Idle and the S and P bits are Clock arbitration occurs when the master de-asserts cleared. the SCL pin (SCL allowed to float high) during any receive, transmit, or Restart/Stop condition. When the 17.13 I2C Module Operation During CPU SCL pin is allowed to float high, the Baud Rate Gener- Sleep and Idle Modes ator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sam- 17.13.1 I2C OPERATION DURING CPU pled high, the Baud Rate Generator is reloaded with SLEEP MODE the contents of I2CBRG and begins counting. This ensures that the SCL high time will always be at least When the device enters Sleep mode, all clock sources one BRG rollover count in the event that the clock is to the module are shutdown and stay at logic ‘0’. If held low by an external device. Sleep occurs in the middle of a transmission, and the state machine is partially into a transmission as the 17.12.5 MULTI-MASTER COMMUNICATION, clocks stop, then the transmission is aborted. Similarly, BUS COLLISION AND BUS if Sleep occurs in the middle of a reception, then the ARBITRATION reception is aborted. Multi-Master operation support is achieved by bus 17.13.2 I2C OPERATION DURING CPU IDLE arbitration. When the master outputs address/data bits MODE onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high For the I2C, the I2CSIDL bit selects if the module will while another master asserts a ‘0’. When the SCL pin stop on Idle or continue on Idle. If I2CSIDL = 0, the floats high, data should be stable. If the expected data module will continue operation on assertion of the Idle on SDA is a ‘1’ and the data sampled on the SDA mode. If I2CSIDL = 1, the module will stop on Idle. pin=0, then a bus collision has taken place. The master will set the MI2CIF pulse and reset the master portion of the I2C port to its Idle state. If a transmit was in progress when the bus collision occurred, the transmission is halted, the TBF flag is cleared, the SDA and SCL lines are de-asserted, and a value can now be written to I2CTRN. When the user services the I2C master event Interrupt Service Routine, if the I2C bus is free (i.e., the P bit is set), the user can resume communication by asserting a Start condition. If a Start, Restart, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are de- asserted, and the respective control bits in the I2CCON register are cleared to 0. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a Start condition. DS70150E-page 116 © 2011 Microchip Technology Inc.

© TABLE 17-2: I2C™ REGISTER MAP(1) 2 01 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 M I2CRCV 0200 — — — — — — — — Receive Register 0000 0000 0000 0000 ic ro I2CTRN 0202 — — — — — — — — Transmit Register 0000 0000 1111 1111 c hip I2CBRG 0204 — — — — — — — Baud Rate Generator 0000 0000 0000 0000 T I2CCON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0001 0000 0000 0000 e ch I2CSTAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 0000 0000 0000 n olo I2CADD 020A — — — — — — Address Register 0000 0000 0000 0000 gy Legend: — = unimplemented bit, read as ‘0’ In Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. c . d s P I C 3 0 F 6 0 1 0 D S A 7 0 1 / 50 6 E -p 0 a g 1 e 1 5 1 7

dsPIC30F6010A/6015 NOTES: DS70150E-page 118 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 18.0 UNIVERSAL ASYNCHRONOUS 18.1 UART Module Overview RECEIVER TRANSMITTER The key features of the UART module are: (UART) MODULE • Full-duplex, 8 or 9-bit data communication Note: This data sheet summarizes features of • Even, Odd or No Parity options (for 8-bit data) this group ofdsPIC30F devices and is not • One or two Stop bits intended to be a complete reference • Fully integrated Baud Rate Generator with 16-bit source. For more information on the CPU, prescaler peripherals, register descriptions and • Baud rates range from 38 bps to 1.875 Mbps at a general device functionality, refer to the 30 MHz instruction rate “dsPIC30F Family Reference Manual” • 4-word deep transmit data buffer (DS70046). • 4-word deep receive data buffer This section describes the Universal Asynchronous • Parity, Framing and Buffer Overrun error detection Receiver/Transmitter Communications module. • Support for Interrupt only on Address Detect (9th bit = 1) • Separate Transmit and Receive Interrupts • Loopback mode for diagnostic support FIGURE 18-1: UART TRANSMITTER BLOCK DIAGRAM Internal Data Bus Control and Status bits Write Write UTX8 UxTXREG Low Byte Transmit Control – Control TSR – Control Buffer – Generate Flags – Generate Interrupt Load TSR UxTXIF UTXBRK Data Transmit Shift Register (UxTSR) ‘0’ (Start) UxTX ‘1’ (Stop) Parity GePnaerritaytor 16 Divider 1fr6oXm B Baauudd C Rloactek Generator Control Signals Note: x = 1 or 2. © 2011 Microchip Technology Inc. DS70150E-page 119

dsPIC30F6010A/6015 FIGURE 18-2: UART RECEIVER BLOCK DIAGRAM Internal Data Bus 16 Read Write ReadRead Write UxMODE UxSTA URX8 UxRXREG Low Byte Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters LPBACK 8-9 From UxTX 1 Load RSR to Buffer Control R R UxRX 0 Receiv(eU SxRhiSft RR)egister Signals PER FER · Start bit Detect · Parity Check · Stop bit Detect 16 Divider · Shift Clock Generation · Wake Logic 16X Baud Clock from Baud Rate Generator UxRXIF DS70150E-page 120 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 18.2 Enabling and Setting Up UART 18.3 Transmitting Data 18.2.1 ENABLING THE UART 18.3.1 TRANSMITTING IN 8-BIT DATA MODE The UART module is enabled by setting the UARTEN bit in the UxMODE register (where x = 1 or 2). Once The following steps must be performed in order to enabled, the UxTX and UxRX pins are configured as an transmit 8-bit data: output and an input respectively, overriding the TRIS 1. Set up the UART: and LAT register bit settings for the corresponding I/O First, the data length, parity and number of Stop port pins. The UxTX pin is at logic ‘1’ when no bits must be selected. Then, the Transmit and transmission is taking place. Receive Interrupt Enable and Priority bits are setup in the UxMODE and UxSTA registers. 18.2.2 DISABLING THE UART Also, the appropriate baud rate value must be The UART module is disabled by clearing the written to the UxBRG register. UARTEN bit in the UxMODE register. This is the 2. Enable the UART by setting the UARTEN bit default state after any Reset. If the UART is disabled, (UxMODE<15>). all I/O pins operate as port pins under the control of 3. Set the UTXEN bit (UxSTA<10>), thereby the LAT and TRIS bits of the corresponding port pins. enabling a transmission. Disabling the UART module resets the buffers to Note: The UTXEN bit must be set after the empty states. Any data characters in the buffers are UARTEN bit is set to enable UART lost, and the baud rate counter is reset. transmissions. All error and status flags associated with the UART module are reset when the module is disabled. The 4. Write the byte to be transmitted to the lower byte URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and of UxTXREG. The value will be transferred to the UTXBF bits are cleared, whereas RIDLE and TRMT Transmit Shift Register (UxTSR) immediately are set. Other control bits, including ADDEN, and the serial bit stream will start shifting out URXISEL<1:0>, UTXISEL, as well as the UxMODE during the next rising edge of the baud clock. and UxBRG registers, are not affected. Alternatively, the data byte may be written while UTXEN = 0, following which, the user may set Clearing the UARTEN bit while the UART is active will UTXEN. This will cause the serial bit stream to abort all pending transmissions and receptions and begin immediately because the baud clock will reset the module as defined above. Re-enabling the start from a cleared state. UART will restart the UART in the same configuration. 5. A transmit interrupt will be generated depending 18.2.3 SETTING UP DATA, PARITY AND on the value of the interrupt control bit UTXISEL STOP BIT SELECTIONS (UxSTA<15>). Control bits PDSEL<1:0> in the UxMODE register are 18.3.2 TRANSMITTING IN 9-BIT DATA used to select the data length and parity used in the MODE transmission. The data length may either be 8-bits with even, odd or no parity, or 9-bits with no parity. The sequence of steps involved in the transmission of 9-bit data is similar to 8-bit transmission, except that a The STSEL bit determines whether one or two Stop bits 16-bit data word (of which the upper 7 bits are always will be used during data transmission. clear) must be written to the UxTXREG register. The default (power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented as 8, N, 1). 18.3.3 TRANSMIT BUFFER (UXTXB) The transmit buffer is 9-bits wide and 4 characters deep. Including the Transmit Shift Register (UxTSR), the user effectively has a 5-deep FIFO (First-In, First- Out) buffer. The UTXBF Status bit (UxSTA<9>) indicates whether the transmit buffer is full. If a user attempts to write to a full buffer, the new data will not be accepted into the FIFO, and no data shift will occur within the buffer. This enables recovery from a buffer overrun condition. The FIFO is reset during any device Reset, but is not affected when the device enters or wakes up from a power-saving mode. © 2011 Microchip Technology Inc. DS70150E-page 121

dsPIC30F6010A/6015 18.3.4 TRANSMIT INTERRUPT 18.4.2 RECEIVE BUFFER (UXRXB) The Transmit Interrupt Flag (U1TXIF or U2TXIF) is The receive buffer is 4 words deep. Including the located in the corresponding interrupt flag register. Receive Shift Register (UxRSR), the user effectively has a 5-word deep FIFO buffer. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends URXDA (UxSTA<0>) = 1 indicates that the receive on UTXISEL control bit: buffer has data available. URXDA = 0 means that the buffer is empty. If a user attempts to read an empty a) If UTXISEL = 0, an interrupt is generated when buffer, the old values in the buffer will be read and no a word is transferred from the transmit buffer to data shift will occur within the FIFO. the Transmit Shift Register (UxTSR). This means that the transmit buffer has at least one The FIFO is reset during any device Reset. It is not empty word. affected when the device enters or wakes up from a b) If UTXISEL = 1, an interrupt is generated when Power-Saving mode. a word is transferred from the transmit buffer to 18.4.3 RECEIVE INTERRUPT the Transmit Shift Register (UxTSR) and the transmit buffer is empty. The Receive Interrupt Flag (U1RXIF or U2RXIF) can be read from the corresponding interrupt flag register. Switching between the two interrupt modes during The interrupt flag is set by an edge generated by the operation is possible and sometimes offers more receiver. The condition for setting the receive interrupt flexibility. flag depends on the settings specified by the 18.3.5 TRANSMIT BREAK URXISEL<1:0> (UxSTA<7:6>) control bits. Setting the UTXBRK bit (UxSTA<11>) will cause the a) If URXISEL<1:0> = 00 or 01, an interrupt is UxTX line to be driven to logic ‘0’. The UTXBRK bit generated every time a data word is transferred overrides all transmission activity. Therefore, the user from the Receive Shift Register (UxRSR) to the should generally wait for the transmitter to be Idle receive buffer. There may be one or more before setting UTXBRK. characters in the receive buffer. b) If URXISEL<1:0> = 10, an interrupt is generated To send a Break character, the UTXBRK bit must be when a word is transferred from the Receive set by software and must remain set for a minimum of Shift Register (UxRSR) to the receive buffer, 13 baud clock cycles. The UTXBRK bit is then cleared which, as a result of the transfer, contains by software to generate Stop bits. The user must wait 3characters. for a duration of at least one or two baud clock cycles in order to ensure a valid Stop bit(s) before reloading c) If URXISEL<1:0> = 11, an interrupt is set when the UxTXB or starting other transmitter activity. Trans- a word is transferred from the Receive Shift mission of a Break character does not generate a Register (UxRSR) to the receive buffer, which, transmit interrupt. as a result of the transfer, contains 4 characters (i.e., becomes full). 18.4 Receiving Data Switching between the interrupt modes during opera- tion is possible, though generally not advisable during 18.4.1 RECEIVING IN 8-BIT OR 9-BIT DATA normal operation. MODE 18.5 Reception Error Handling The following steps must be performed while receiving 8-bit or 9-bit data: 18.5.1 RECEIVE BUFFER OVERRUN 1. Set up and enable the UART (see Section18.3 ERROR (OERR BIT) “Transmitting Data”). The OERR bit (UxSTA<1>) is set if all of the following 2. A receive interrupt will be generated when one conditions occur: or more data words have been received, depending on the receive interrupt settings a) The receive buffer is full. specified by the URXISEL bits (UxSTA<7:6>). b) The Receive Shift Register is full, but unable to 3. Read the OERR bit to determine if an overrun transfer the character to the receive buffer. error has occurred. The OERR bit must be reset c) The Stop bit of the character in the UxRSR is in software. detected, indicating that the UxRSR needs to 4. Read the received data from UxRXREG. The act transfer the character to the buffer. of reading UxRXREG will move the next word to Once OERR is set, no further data is shifted in UxRSR the top of the receive FIFO, and the PERR and (until the OERR bit is cleared in software or a Reset FERR values will be updated. occurs). The data held in UxRSR and UxRXREG remains valid. DS70150E-page 122 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 18.5.2 FRAMING ERROR (FERR) 18.6 Address Detect Mode The FERR bit (UxSTA<2>) is set if a ‘0’ is detected Setting the ADDEN bit (UxSTA<5>) enables this instead of a Stop bit. If two Stop bits are selected, both special mode, in which a 9th bit (URX8) value of ‘1’ Stop bits must be ‘1’, otherwise FERR will be set. The identifies the received word as an address rather than read-only FERR bit is buffered along with the received data. This mode is only applicable for 9-bit data com- data. It is cleared on any Reset. munication. The URXISEL control bit does not have any impact on interrupt generation in this mode, since 18.5.3 PARITY ERROR (PERR) an interrupt (if enabled) will be generated every time The PERR bit (UxSTA<3>) is set if the parity of the the received word has the 9th bit set. received word is incorrect. This error bit is applicable only if a Parity mode (odd or even) is selected. The 18.7 Loopback Mode read-only PERR bit is buffered along with the received data bytes. It is cleared on any Reset. Setting the LPBACK bit enables this special mode in which the UxTX pin is internally connected to the UxRX 18.5.4 IDLE STATUS pin. When configured for the Loopback mode, the UxRX pin is disconnected from the internal UART When the receiver is active (i.e., between the initial receive logic. However, the UxTX pin still functions as detection of the Start bit and the completion of the Stop in a normal operation. bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the completion of the Stop bit and detection of the next To select this mode: Start bit, the RIDLE bit is ‘1’, indicating that the UART a) Configure UART for desired mode of operation. is Idle. b) Set LPBACK = 1 to enable Loopback mode. 18.5.5 RECEIVE BREAK c) Enable transmission as defined in Section18.3 “Transmitting Data”. The receiver will count and expect a certain number of bit times based on the values programmed in the 18.8 Baud Rate Generator (BRG) PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>) bits. The UART has a 16-bit Baud Rate Generator to allow If the break is longer than 13 bit times, the reception is maximum flexibility in baud rate generation. The Baud considered complete after the number of bit times Rate Generator register (UxBRG) is readable and specified by PDSEL and STSEL. The URXDA bit is writable. The baud rate is computed as follows: set, FERR is set, zeros are loaded into the receive BRG = 16-bit value held in UxBRG register FIFO, interrupts are generated, if appropriate, and the (0 through 65535) RIDLE bit is set. FCY = Instruction Clock Rate (1/TCY) When the module receives a long break signal and the The baud rate is given by Equation18-1. receiver has detected the Start bit, the data bits and the invalid Stop bit (which sets the FERR), the receiver EQUATION 18-1: BAUD RATE must wait for a valid Stop bit before looking for the next Start bit. It cannot assume that the break condition on the line is the next Start bit. Baud Rate = FCY/(16 * (BRG + 1)) Break is regarded as a character containing all ‘0’s, with the FERR bit set. The Break character is loaded Therefore, maximum baud rate possible is into the buffer. No further reception can occur until a FCY/16 (if BRG = 0), Stop bit is received. Note that RIDLE goes high when and the minimum baud rate possible is the Stop bit has not been received yet. FCY/(16 * 65536). With a full 16-bit Baud Rate Generator, at 30 MIPS operation, the minimum baud rate achievable is 28.5bps. © 2011 Microchip Technology Inc. DS70150E-page 123

dsPIC30F6010A/6015 18.9 Auto-Baud Support 18.10.2 UART OPERATION DURING CPU IDLE MODE To allow the system to determine baud rates of received characters, the input can be optionally linked For the UART, the USIDL bit selects if the module will to a selected capture input. To enable this mode, the stop operation when the device enters Idle mode, or user must program the input capture module to detect whether the module will continue on Idle. If USIDL=0, the falling and rising edges of the Start bit. the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. 18.10 UART Operation During CPU Sleep and Idle Modes 18.10.1 UART OPERATION DURING CPU SLEEP MODE When the device enters Sleep mode, all clock sources to the module are shut down and stay at logic ‘0’. If entry into Sleep mode occurs while a transmission is in progress, then the transmission is aborted. The UxTX pin is driven to logic ‘1’. Similarly, if entry into Sleep mode occurs while a reception is in progress, then the reception is aborted. The UxSTA, UxMODE, Transmit and Receive registers and buffers, and the UxBRG register are not affected by Sleep mode. If the Wake bit (UxMODE<7>) is set before the device enters Sleep mode, then a falling edge on the UxRX pin will generate a receive interrupt. The Receive Interrupt Select Mode bit (URXISEL) has no effect for this function. If the receive interrupt is enabled, then this will wake-up the device from Sleep. The UARTEN bit must be set in order to generate a wake-up interrupt. DS70150E-page 124 © 2011 Microchip Technology Inc.

© TABLE 18-1: UART1 REGISTER MAP(1) 2 01 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 M U1MODE 020C UARTEN — USIDL — — — — — WAKE LPBACK ABAUD — — PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000 ic ro U1STA 020E UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000 c hip U1TXREG 0210 — — — — — — — UTX8 Transmit Register 0000 000u uuuu uuuu T U1RXREG 0212 — — — — — — — URX8 Receive Register 0000 0000 0000 0000 e c h U1BRG 0214 Baud Rate Generator Prescaler 0000 0000 0000 0000 n o Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ lo g Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. y In c. TABLE 18-2: UART2 REGISTER MAP(1) SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State Name U2MODE 0216 UARTEN — USIDL — — — — — WAKE LPBACK ABAUD — — PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000 U2STA 0218 UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000 U2TXREG 021A — — — — — — — UTX8 Transmit Register 0000 000u uuuu uuuu U2RXREG 021C — — — — — — — URX8 Receive Register 0000 0000 0000 0000 U2BRG 021E Baud Rate Generator Prescaler 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. d s P I C 3 0 F 6 0 1 0 D S A 7 0 1 / 50 6 E -p 0 a g 1 e 1 5 2 5

dsPIC30F6010A/6015 NOTES: DS70150E-page 126 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 19.0 CAN MODULE The CAN bus module consists of a protocol engine, and message buffering/control. The CAN protocol Note: This data sheet summarizes features of engine handles all functions for receiving and trans- this group ofdsPIC30F devices and is not mitting messages on the CAN bus. Messages are intended to be a complete reference transmitted by first loading the appropriate data regis- source. For more information on the CPU, ters. Status and errors can be checked by reading the peripherals, register descriptions and appropriate registers. Any message detected on the general device functionality, refer to the CAN bus is checked for errors and then matched “dsPIC30F Family Reference Manual” against filters to see if it should be received and stored (DS70046). in one of the receive registers. 19.1 Overview 19.2 Frame Types The Controller Area Network (CAN) module is a serial The CAN module transmits various types of frames, interface, useful for communicating with other CAN which include data messages or remote transmission modules or microcontroller devices. This interface/ requests initiated by the user as other frames that are protocol was designed to allow communications within automatically generated for control purposes. The noisy environments. The dsPIC30F6010A has two following frame types are supported: CAN modules. The dsPIC30F6015 has only one. • Standard Data Frame The CAN module is a communication controller imple- A Standard Data Frame is generated by a node when menting the CAN 2.0 A/B protocol, as defined in the the node wishes to transmit data. It includes a 11-bit BOSCH specification. The module will support Standard Identifier (SID), but not an 18-bit Extended CAN1.2, CAN 2.0A, CAN2.0B Passive and CAN 2.0B Identifier (EID). Active versions of the protocol. The module implemen- tation is a full CAN system. The CAN specification is • Extended Data Frame not covered within this data sheet. The reader may An Extended Data Frame is similar to a Standard Data refer to the BOSCH CAN specification for further Frame, but includes an Extended Identifier as well. details. • Remote Frame The module features are as follows: It is possible for a destination node to request the data • Implementation of the CAN protocol CAN1.2, from the source. For this purpose, the destination node CAN2.0A and CAN2.0B sends a Remote Frame with an identifier that matches • Standard and extended data frames the identifier of the required Data Frame. The appropri- • 0-8 bytes data length ate data source node will then send a Data Frame as a • Programmable bit rate up to 1 Mbit/sec response to this remote request. • Support for remote frames • Error Frame • Double-buffered receiver with two prioritized An Error Frame is generated by any node that detects received message storage buffers (each buffer a bus error. An error frame consists of 2 fields: an Error may contain up to 8 bytes of data) Flag field and an Error Delimiter field. • 6 full (standard/extended identifier) acceptance • Overload Frame filters, 2 associated with the high priority receive buffer, and 4 associated with the low priority An Overload Frame can be generated by a node as a receive buffer result of 2 conditions. First, the node detects a domi- • 2 full acceptance filter masks, one each associ- nant bit during lnterframe Space, which is an illegal ated with the high and low priority receive buffers condition. Second, due to internal conditions, the node is not yet able to start reception of the next message. A • Three transmit buffers with application specified node may generate a maximum of 2 sequential prioritization and abort capability (each buffer may Overload Frames to delay the start of the next contain up to 8 bytes of data) message. • Programmable wake-up functionality with integrated low-pass filter • Interframe Space • Programmable Loopback mode supports self-test Interframe Space separates a proceeding frame (of operation whatever type) from a following Data or Remote • Signaling via interrupt capabilities for all CAN Frame. receiver and transmitter error states • Programmable clock source • Programmable link to timer module for time-stamping and network synchronization • Low-Power Sleep and Idle mode © 2011 Microchip Technology Inc. DS70150E-page 127

dsPIC30F6010A/6015 FIGURE 19-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask BUFFERS RXM1 Acceptance Filter RXF2 Acceptance Mask Acceptance Filter A TXB0 TXB1 TXB2 RXM0 RXF3 c A c MSGREQTXABTTXLARBTXERRMTXBUFF MESSAGE MSGREQTXABTTXLARBTXERRMTXBUFF MESSAGE MSGREQTXABTTXLARBTXERRMTXBUFF MESSAGE ccep AAcccceeppRRttaaXXnnFFcc01ee FFiilltteerr AAcccceeppRRttaaXXnnFFcc45ee FFiilltteerr ept t R R X Identifier M Identifier X Message B A B Queue 0 B 1 Control Transmit Byte Sequencer Data Field Data Field Receive RERRCNT Error PROTOCOL Counter TERRCNT ENGINE Transmit ErrPas Error BusOff Counter Transmit Shift Receive Shift Protocol Finite CRC Generator CRC Check State Machine Bit Transmit Timing Bit Timing Logic Logic Generator CiTX(1) CiRX(1) Note 1. i = 1 or 2 refers to a particular CAN module (CAN1 or CAN2). The dsPIC30F6015 has only one CAN module. DS70150E-page 128 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 19.3 Modes of Operation The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or The CAN module can operate in one of several operation the CPU is in Sleep mode. The WAKFIL bit modes selected by the user. These modes include: (CiCFG2<14>) enables or disables the filter. • Initialization mode Note: Typically, if the CAN module is allowed to • Disable mode transmit in a particular mode of operation • Normal Operation mode and a transmission is requested immedi- • Listen-Only mode ately after the CAN module has been placed in that mode of operation, the mod- • Loopback mode ule waits for 11 consecutive recessive bits • Error Recognition mode on the bus before starting transmission. If Modes are requested by setting the REQOP<2:0> the user switches to Disable mode within bits(CiCTRL<10:8>). Entry into a mode is this 11-bit period, then this transmission is acknowledged by monitoring the OPMODE<2:0> bits aborted and the corresponding TXABT bit (CiCTRL<7:5>). The module will not change the mode is set and TXREQ bit is cleared. and the OPMODE bits until a change in mode is acceptable, generally during bus idle time which is 19.3.3 NORMAL OPERATION MODE defined as at least 11 consecutive recessive bits. Normal Operating mode is selected when 19.3.1 INITIALIZATION MODE REQOP<2:0>=000. In this mode, the module is activated, the I/O pins will assume the CAN bus In the Initialization mode, the module will not transmit or functions. The module will transmit and receive CAN receive. The error counters are cleared and the inter- bus messages via the CiTX and CiRX pins. rupt flags remain unchanged. The programmer will have access to Configuration registers that are access 19.3.4 LISTEN-ONLY MODE restricted in other modes. The module will protect the If the Listen-Only mode is activated, the module on the user from accidentally violating the CAN protocol CAN bus is passive. The transmitter buffers revert to through programming errors. All registers which control the Port I/O function. The receive pins remain inputs. the configuration of the module cannot be modified For the receiver, no error flags or acknowledge signals while the module is on-line. The CAN module will not are sent. The error counters are deactivated in this be allowed to enter the Configuration mode while a state. The Listen-Only mode can be used for detecting transmission is taking place. The Configuration mode the baud rate on the CAN bus. To use this, it is neces- serves as a lock to protect the following registers: sary that there are at least two further nodes that • All Module Control Registers communicate with each other. • Baud Rate and Interrupt Configuration Registers 19.3.5 ERROR RECOGNITION MODE • Bus Timing Registers • Identifier Acceptance Filter Registers The module can be set to ignore all errors and receive • Identifier Acceptance Mask Registers any message. The Error Recognition mode is activated by setting the RXM<1:0> bits (CiRXnCON<6:5>) to 19.3.2 DISABLE MODE ‘11’. In this mode, the data which is in the message assembly buffer until the time an error occurred, is cop- In Disable mode, the module will not transmit or ied in the receive buffer and can be read via the CPU receive. The module has the ability to set the WAKIF bit interface. due to bus activity, however any pending interrupts will remain and the error counters will retain their value. 19.3.6 LOOPBACK MODE If the REQOP<2:0> bits (CiCTRL<10:8>) = 001, the If the Loopback mode is activated, the module will con- module will enter the Module Disable mode. If the nect the internal transmit signal to the internal receive module is active, the module will wait for 11 recessive signal at the module boundary. The transmit and bits on the CAN bus, detect that condition as an idle receive pins revert to their Port I/O function. bus, then accept the module disable command. When the OPMODE<2:0> bits(CiCTRL<7:5>) =001, that indicates whether the module successfully went into Module Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. © 2011 Microchip Technology Inc. DS70150E-page 129

dsPIC30F6010A/6015 19.4 Message Reception 19.4.4 RECEIVE OVERRUN An overrun condition occurs when the message 19.4.1 RECEIVE BUFFERS assembly buffer has assembled a valid received The CAN bus module has 3 receive buffers. However, message and the message is accepted through the one of the receive buffers is always committed to mon- acceptance filters, but the receive buffer associated itoring the bus for incoming messages. This buffer is with the filter still contains unread data. called the Message Assembly Buffer (MAB). So there The overrun error flag, RXnOVR (CiINTF<15> or are 2 receive buffers visible, RXB0 and RXB1, that can CiINTF<14>) and the ERRIF bit (CiINTF<5>) will be set essentially instantaneously receive a complete and the message in the MAB will be discarded. message from the protocol engine. If the DBEN bit is clear, RXB1 and RXB0 operate inde- All messages are assembled by the MAB, and are trans- pendently. When this is the case, a message intended ferred to the RXBn buffers only if the acceptance filter for RXB0 will not be diverted into RXB1 if RXB0 criterion is met. When a message is received, the RXnIF contains an unread message and the RX0OVR bit will flag (CiINTF<0> or CiINTF<1>) will be set. This bit can be set. only be set by the module when a message is received. The bit is cleared by the CPU when it has completed If the DBEN bit is set, the overrun for RXB0 is handled processing the message in the buffer. If the RXnIE bit differently. If a valid message is received for RXB0 and (CiINTE<0> or CiINTE<1>) is set, an interrupt will be RXFUL=1 indicates that RXB0 is full and RXFUL=0 generated when a message is received. indicates that RXB1 is empty, the message for RXB0 will be loaded into RXB1. An overrun error will not be RXF0 and RXF1 filters with RXM0 mask are associated generated for RXB0. If a valid message is received for with RXB0. The filters RXF2, RXF3, RXF4, and RXF5 RXB0 and RXFUL=1, and RXFUL=1 indicating that and the mask RXM1 are associated with RXB1. both RXB0 and RXB1 are full, the message will be lost and an overrun will be indicated for RXB1. 19.4.2 MESSAGE ACCEPTANCE FILTERS The message acceptance filters and masks are used to 19.4.5 RECEIVE ERRORS determine if a message in the message assembly buf- The CAN module will detect the following receive fer should be loaded into either of the receive buffers. errors: Once a valid message has been received into the mes- sage assembly buffer, the identifier fields of the mes- • Cyclic Redundancy Check (CRC) error sage are compared to the filter values. If there is a • Bit Stuffing error match, that message will be loaded into the appropriate • Invalid message receive error receive buffer. The receive error counter is incremented by one in The acceptance filter looks at incoming messages for case one of these errors occur. The RXWAR bit the RXIDE bit (CiRXnSID<0>) to determine how to (CiINTF<9>) indicates that the Receive Error Counter compare the identifiers. If the RXIDE bit is clear, the has reached the CPU warning limit of 96 and an message is a standard frame, and only filters with the interrupt is generated. EXIDE bit (CiRXFnSID<0>) clear are compared. If the RXIDE bit is set, the message is an extended frame, 19.4.6 RECEIVE INTERRUPTS and only filters with the EXIDE bit set are compared. Receive interrupts can be divided into 3 major groups, Configuring the RXM<1:0> bits to ‘01’ or ‘10’ can each including various conditions that generate override the EXIDE bit. interrupts: 19.4.3 MESSAGE ACCEPTANCE FILTER • Receive Interrupt MASKS A message has been successfully received and loaded The mask bits essentially determine which bits to apply into one of the receive buffers. This interrupt is acti- the filter to. If any mask bit is set to a zero, then that bit vated immediately after receiving the End-of-Frame will automatically be accepted regardless of the filter (EOF) field. Reading the RXnIF flag will indicate which bit. There are 2 programmable acceptance filter masks receive buffer caused the interrupt. associated with the receive buffers, one for each buffer. • Wake-up Interrupt The CAN module has woken up from Disable mode or the device has woken up from Sleep mode. DS70150E-page 130 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 • Receive Error Interrupts Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects A receive error interrupt will be indicated by the ERRIF an available bus, it begins transmitting the message bit. This bit shows that an error condition occurred. The which has been determined to have the highest priority. source of the error can be determined by checking the bits in the CAN Interrupt STATUS register, CiINTF. If the transmission completes successfully on the first attempt, the TXREQ bit is cleared automatically and an • Invalid message received interrupt is generated if TXIE was set. If any type of error occurred during reception of the last If the message transmission fails, one of the error message, an error will be indicated by the IVRIF bit. condition flags will be set and the TXREQ bit will • Receiver overrun remain set indicating that the message is still pending The RXnOVR bit indicates that an overrun condition for transmission. If the message encountered an error occurred. condition during the transmission attempt, the TXERR bit will be set and the error condition may cause an • Receiver warning interrupt. If the message loses arbitration during the The RXWAR bit indicates that the Receive Error Coun- transmission attempt, the TXLARB bit is set. No ter (RERRCNT<7:0>) has reached the Warning limit of interrupt is generated to signal the loss of arbitration. 96. 19.5.4 ABORTING MESSAGE • Receiver error passive TRANSMISSION The RXEP bit indicates that the Receive Error Counter has exceeded the Error Passive limit of 127 and the The system can also abort a message by clearing the module has gone into Error Passive state. TXREQ bit associated with each message buffer. Setting the ABAT bit (CiCTRL<12>) will request an 19.5 Message Transmission abort of all pending messages. If the message has not yet started transmission, or if the message started but 19.5.1 TRANSMIT BUFFERS is interrupted by loss of arbitration or an error, the abort will be processed. The abort is indicated when the The CAN module has three transmit buffers. Each of module sets the TXABT bit, and the TXnIF flag is not the three buffers occupies 14 bytes of data. Eight of the automatically set. bytes are the maximum 8 bytes of the transmitted mes- sage. Five bytes hold the standard and extended 19.5.5 TRANSMISSION ERRORS identifiers and other message arbitration information. The CAN module will detect the following transmission 19.5.2 TRANSMIT MESSAGE PRIORITY errors: • Acknowledge error Transmit priority is a prioritization within each node of the pending transmittable messages. There are 4 levels of • Form error transmit priority. If TXPRI<1:0> (CiTXnCON<1:0>, where • Bit error n = 0, 1 or 2 represents a particular transmit buffer) for a These transmission errors will not necessarily generate particular message buffer is set to ‘11’, that buffer has the an interrupt, but are indicated by the transmission error highest priority. If TXPRI<1:0> for a particular message counter. However, each of these errors will cause the buffer is set to ‘10’ or ‘01’, that buffer has an intermediate transmission error counter to be incremented by one. priority. If TXPRI<1:0> for a particular message buffer is Once the value of the error counter exceeds the value ‘00’, that buffer has the lowest priority. of 96, the ERRIF (CiINTF<5>) and the TXWAR bit (CiINTF<10>) are set. Once the value of the error 19.5.3 TRANSMISSION SEQUENCE counter exceeds the value of 96, an interrupt is To initiate transmission of the message, the TXREQ bit generated and the TXWAR bit in the Error Flag register (CiTXnCON<3>) must be set. The CAN bus module is set. resolves any timing conflicts between setting of the TXREQ bit and the Start of Frame (SOF), ensuring thatif the priority was changed, it is resolved correctly before the SOF occurs. When TXREQ isset, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits are automatically cleared. © 2011 Microchip Technology Inc. DS70150E-page 131

dsPIC30F6010A/6015 19.5.6 TRANSMIT INTERRUPTS 19.6 Baud Rate Setting Transmit interrupts can be divided into 2 major groups, All nodes on any particular CAN bus must have the each including various conditions that generate same nominal bit rate. In order to set the baud rate, the interrupts: following parameters have to be initialized: • Transmit Interrupt • Synchronization jump width At least one of the three transmit buffers is empty (not • Baud rate prescaler scheduled) and can be loaded to schedule a message • Phase segments for transmission. Reading the TXnIF flags will indicate • Length determination of Phase2 Seg which transmit buffer is available and caused the • Sample point interrupt. • Propagation segment bits • Transmit Error Interrupts A transmission error interrupt will be indicated by the 19.6.1 BIT TIMING ERRIF flag. This flag shows that an error condition All controllers on the CAN bus must have the same baud occurred. The source of the error can be determined by rate and bit length. However, different controllers are not checking the error flags in the CAN Interrupt STATUS required to have the same master oscillator clock. At dif- register, CiINTF. The flags in this register are related to ferent clock frequencies of the individual controllers, the receive and transmit errors. baud rate has to be adjusted by adjusting the number of • Transmitter Warning Interrupt time quanta in each segment. The TXWAR bit indicates that the Transmit Error Counter The Nominal Bit Time can be thought of as being has reached the CPU warning limit of 96. divided into separate non-overlapping time segments. • Transmitter Error Passive These segments are shown in Figure19-2. The TXEP bit (CiINTF<12>) indicates that the Transmit • Synchronization segment (Sync Seg) Error Counter has exceeded the Error Passive limit of • Propagation time segment (Prop Seg) 127 and the module has gone to Error Passive state. • Phase segment 1 (Phase1 Seg) • Bus Off • Phase segment 2 (Phase2 Seg) The TXBO bit (CiINTF<13>) indicates that the Transmit The time segments and also the nominal bit time are Error Counter has exceeded 255 and the module has made up of integer units of time called time quanta or gone to Bus Off state. TQ. By definition, the nominal bit time has a minimum of 8TQ and a maximum of 25TQ. Also, by definition, the minimum nominal bit time is 1μsec, corresponding to a maximum bit rate of 1MHz. FIGURE 19-2: CAN BIT TIMING Input Signal Prop Phase Phase Sync Sync Segment Segment 1 Segment 2 Sample Point TQ DS70150E-page 132 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 19.6.2 PRESCALER SETTING 19.6.5 SAMPLE POINT There is a programmable prescaler, with integral The sample point is the point of time at which the bus values ranging from 1 to 64, in addition to a fixed divide- level is read and interpreted as the value of that respec- by-2 for clock generation. The Time Quantum (TQ) is a tive bit. The location is at the end of Phase1 Seg. If the fixed unit of time derived from the oscillator period, and bit timing is slow and contains many TQ, it is possible to is given by Equation19-1, where FCAN is FCY (if the specify multiple sampling of the bus line at the sample CANCKS bit is set or 4 FCY (if CANCKS is cleared). point. The level determined by the CAN bus then corre- sponds to the result from the majority decision of three Note: FCAN must not exceed 30 MHz. If values. The majority samples are taken at the sample CANCKS = 0, then FCY must not exceed point and twice before with a distance of TQ/2. The 7.5 MHz. CAN module allows the user to chose between sam- pling three times at the same point or once at the same EQUATION 19-1: TIME QUANTUM FOR point, by setting or clearing the SAM bit (CiCFG2<6>). CLOCK GENERATION Typically, the sampling of the bit should take place at about 60-70% through the bit time, depending on the TQ = 2 ( BRP<5:0> + 1 )/FCAN system parameters. 19.6.6 SYNCHRONIZATION 19.6.3 PROPAGATION SEGMENT To compensate for phase shifts between the oscillator This part of the bit time is used to compensate physical frequencies of the different bus stations, each CAN delay times within the network. These delay times con- controller must be able to synchronize to the relevant sist of the signal propagation time on the bus line and signal edge of the incoming signal. When an edge in the internal delay time of the nodes. The Propagation the transmitted data is detected, the logic will compare Segment can be programmed from 1TQ to 8TQ by the location of the edge to the expected time (Synchro- setting the PRSEG<2:0> bits (CiCFG2<2:0>). nous Segment). The circuit will then adjust the values of Phase1 Seg and Phase2 Seg. There are 2 19.6.4 PHASE SEGMENTS mechanisms used to synchronize. The phase segments are used to optimally locate the sampling of the received bit within the transmitted bit 19.6.6.1 Hard Synchronization time. The sampling point is between Phase1 Seg and Hard synchronization is only done whenever there is a Phase2 Seg. These segments are lengthened or short- recessive to dominant edge during bus Idle, indicating ened by re-synchronization. The end of the Phase1 the start of a message. After hard synchronization, the Seg determines the sampling point within a bit period. bit time counters are restarted with the Synchronous The segment is programmable from 1TQ to 8TQ. Segment. Hard synchronization forces the edge which Phase2 Seg provides delay to the next transmitted data has caused the hard synchronization to lie within the transition. The segment is programmable from 1TQ to synchronization segment of the restarted bit time. If a 8TQ, or it may be defined to be equal to the greater of hard synchronization is done, there will not be a Phase1 Seg or the Information Processing Time resynchronization within that bit time. (2TQ). The Phase1 Seg is initialized by setting bits SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is 19.6.6.2 Re-synchronization initialized by setting SEG2PH<2:0> (CiCFG2<10:8>). As a result of re-synchronization, Phase1 Seg may be The following requirement must be fulfilled while setting lengthened or Phase2 Seg may be shortened. The the lengths of the Phase Segments: amount of lengthening or shortening of the phase • Propagation Segment+Phase1 Seg >=Phase2 Seg buffer segment has an upper bound known as the synchronization jump width, and is specified by the SJW<1:0> bits (CiCFG1<7:6>). The value of the synchronization jump width will be added to Phase1 Seg or subtracted from Phase2 Seg. The re- synchronization jump width is programmable between 1TQ and 4TQ. The following requirement must be fulfilled while setting the SJW<1:0> bits: • Phase2 Seg>Synchronization Jump Width © 2011 Microchip Technology Inc. DS70150E-page 133

D TABLE 19-1: CAN1 REGISTER MAP FOR dsPIC30F6010A AND 6015 DEVICES(1) d S 70 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 1 50 C1RXF0SID 0300 — — — Receive Acceptance Filter 0 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u P E -p C1RXF0EIDH 0302 — — — — Receive Acceptance Filter 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu I a C g C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 e 1 C1RXF1SID 0308 — — — Receive Acceptance Filter 1 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u 3 3 4 C1RXF1EIDH 030A — — — — Receive Acceptance Filter 1 Extended Identifier<17:6> 0000 uuuu uuuu uuuu 0 C1RXF1EIDL 030C Receive Acceptance Filter 1 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 F C1RXF2SID 0310 — — — Receive Acceptance Filter 2 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u 6 C1RXF2EIDH 0312 — — — — Receive Acceptance Filter 2 Extended Identifier<17:6> 0000 uuuu uuuu uuuu 0 C1RXF2EIDL 0314 Receive Acceptance Filter 2 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 1 C1RXF3SID 0318 — — — Receive Acceptance Filter 3 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u 0 C1RXF3EIDH 031A — — — — Receive Acceptance Filter 3 Extended Identifier<17:6> 0000 uuuu uuuu uuuu A C1RXF3EIDL 031C Receive Acceptance Filter 3 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 C1RXF4SID 0320 — — — Receive Acceptance Filter 4 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u / 6 C1RXF4EIDH 0322 — — — — Receive Acceptance Filter 4 Extended Identifier<17:6> 0000 uuuu uuuu uuuu C1RXF4EIDL 0324 Receive Acceptance Filter 4 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 0 C1RXF5SID 0328 — — — Receive Acceptance Filter 5 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u 1 C1RXF5EIDH 032A — — — — Receive Acceptance Filter 5 Extended Identifier<17:6> 0000 uuuu uuuu uuuu 5 C1RXF5EIDL 032C Receive Acceptance Filter 5 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 C1RXM0SID 0330 — — — Receive Acceptance Mask 0 Standard Identifier<10:0> — MIDE 000u uuuu uuuu uu0u C1RXM0EIDH 0332 — — — — Receive Acceptance Mask 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu C1RXM0EIDL 0334 Receive Acceptance Mask 0 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 C1RXM1SID 0338 — — — Receive Acceptance Mask 1 Standard Identifier<10:0> — MIDE 000u uuuu uuuu uu0u C1RXM1EIDH 033A — — — — Receive Acceptance Mask 1 Extended Identifier<17:6> 0000 uuuu uuuu uuuu C1RXM1EIDL 033C Receive Acceptance Mask 1 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 C1TX2SID 0340 Transmit Buffer 2 Standard Identifier<10:6> — — — Transmit Buffer 2 Standard Identifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu C1TX2EID 0342 Transmit Buffer 2 Extended — — — — Transmit Buffer 2 Extended Identifier<13:6> uuuu 0000 uuuu uuuu Identifier<17:14> C1TX2DLC 0344 Transmit Buffer 2 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000 C1TX2B1 0346 Transmit Buffer 2 Byte 1 Transmit Buffer 2 Byte 0 uuuu uuuu uuuu uuuu © 2 C1TX2B2 0348 Transmit Buffer 2 Byte 3 Transmit Buffer 2 Byte 2 uuuu uuuu uuuu uuuu 01 C1TX2B3 034A Transmit Buffer 2 Byte 5 Transmit Buffer 2 Byte 4 uuuu uuuu uuuu uuuu 1 M C1TX2B4 034C Transmit Buffer 2 Byte 7 Transmit Buffer 2 Byte 6 uuuu uuuu uuuu uuuu icro C1TX2CON 034E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000 ch C1TX1SID 0350 Transmit Buffer 1 Standard Identifier<10:6> — — — Transmit Buffer 1 Standard Identifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu ip Te C1TX1EID 0352 TransImdeitn Btifuieffre<r1 17 :E1x4t>ended — — — — Transmit Buffer 1 Extended Identifier<13:6> uuuu 0000 uuuu uuuu c h C1TX1DLC 0354 Transmit Buffer 1 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000 n olo C1TX1B1 0356 Transmit Buffer 1 Byte 1 Transmit Buffer 1 Byte 0 uuuu uuuu uuuu uuuu gy Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ In Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. c .

© TABLE 19-1: CAN1 REGISTER MAP FOR dsPIC30F6010A AND 6015 DEVICES(1) (CONTINUED) 2 0 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 1 M C1TX1B2 0358 Transmit Buffer 1 Byte 3 Transmit Buffer 1 Byte 2 uuuu uuuu uuuu uuuu icro C1TX1B3 035A Transmit Buffer 1 Byte 5 Transmit Buffer 1 Byte 4 uuuu uuuu uuuu uuuu ch C1TX1B4 035C Transmit Buffer 1 Byte 7 Transmit Buffer 1 Byte 6 uuuu uuuu uuuu uuuu ip T C1TX1CON 035E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000 ec C1TX0SID 0360 Transmit Buffer 0 Standard Identifier<10:6> — — — Transmit Buffer 0 Standard Identifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu h n C1TX0EID 0362 Transmit Buffer 0 Extended — — — — Transmit Buffer 0 Extended Identifier<13:6> uuuu 0000 uuuu uuuu olo Identifier<17:14> g y C1TX0DLC 0364 Transmit Buffer 0 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000 Inc C1TX0B1 0366 Transmit Buffer 0 Byte 1 Transmit Buffer 0 Byte 0 uuuu uuuu uuuu uuuu . C1TX0B2 0368 Transmit Buffer 0 Byte 3 Transmit Buffer 0 Byte 2 uuuu uuuu uuuu uuuu C1TX0B3 036A Transmit Buffer 0 Byte 5 Transmit Buffer 0 Byte 4 uuuu uuuu uuuu uuuu C1TX0B4 036C Transmit Buffer 0 Byte 7 Transmit Buffer 0 Byte 6 uuuu uuuu uuuu uuuu C1TX0CON 036E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000 C1RX1SID 0370 — — — Receive Buffer 1 Standard Identifier<10:0> SRR RXIDE 000u uuuu uuuu uuuu C1RX1EID 0372 — — — — Receive Buffer 1 Extended Identifier<17:6> 0000 uuuu uuuu uuuu C1RX1DLC 0374 Receive Buffer 1 Extended Identifier<5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu C1RX1B1 0376 Receive Buffer 1 Byte 1 Receive Buffer 1 Byte 0 uuuu uuuu uuuu uuuu C1RX1B2 0378 Receive Buffer 1 Byte 3 Receive Buffer 1 Byte 2 uuuu uuuu uuuu uuuu C1RX1B3 037A Receive Buffer 1 Byte 5 Receive Buffer 1 Byte 4 uuuu uuuu uuuu uuuu C1RX1B4 037C Receive Buffer 1 Byte 7 Receive Buffer 1 Byte 6 uuuu uuuu uuuu uuuu C1RX1CON 037E — — — — — — — — RXFUL — — — RXRTRRO FILHIT<2:0> 0000 0000 0000 0000 d C1RX0SID 0380 — — — Receive Buffer 0 Standard Identifier<10:0> SRR RXIDE 000u uuuu uuuu uuuu s C1RX0EID 0382 — — — — Receive Buffer 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu P C1RX0DLC 0384 Receive Buffer 0 Extended Identifier<5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu C1RX0B1 0386 Receive Buffer 0 Byte 1 Receive Buffer 0 Byte 0 uuuu uuuu uuuu uuuu I C C1RX0B2 0388 Receive Buffer 0 Byte 3 Receive Buffer 0 Byte 2 uuuu uuuu uuuu uuuu C1RX0B3 038A Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 4 uuuu uuuu uuuu uuuu 3 C1RX0B4 038C Receive Buffer 0 Byte 7 Receive Buffer 0 Byte 6 uuuu uuuu uuuu uuuu 0 C1RX0CON 038E — — — — — — — — RXFUL — — — RXRTRRO DBEN JTOFF FILHIT0 0000 0000 0000 0000 F C1CTRL 0390 CANCAP — CSIDLE ABAT CANCKS REQOP<2:0> OPMODE<2:0> — ICODE<2:0> — 0000 0100 1000 0000 6 C1CFG1 0392 — — — — — — — — SJW<1:0> BRP<5:0> 0000 0000 0000 0000 0 C1CFG2 0394 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0u00 0uuu uuuu uuuu 1 C1INTF 0396 RX0OVR RX1OVR TXBO TXEP RXEP TXWARRXWAREWARN IVRIF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000 0000 0000 C1INTE 0398 — — — — — — — — IVRIE WAKIE ERRIE TX2IE TX1IE TX0IE RX1E RX0IE 0000 0000 0000 0000 0 D S C1EC 039A Transmit Error Count Register Receive Error Count Register 0000 0000 0000 0000 A 7 01 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ / 50 Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 6 E -p 0 a g 1 e 1 5 3 5

D TABLE 19-2: CAN2 REGISTER MAP FOR dsPIC30F6010A(1) d S 70 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 1 50 C2RXF0SID 03C0 — — — Receive Acceptance Filter 0 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u P E -p C2RXF0EIDH 03C2 — — — — Receive Acceptance Filter 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu I a C g C2RXF0EIDL 03C4 Receive Acceptance Filter 0 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 e 1 C2RXF1SID 03C8 — — — Receive Acceptance Filter 1 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u 3 3 6 C2RXF1EIDH 03CA — — — — Receive Acceptance Filter 1 Extended Identifier<17:6> 0000 uuuu uuuu uuuu 0 C2RXF1EIDL 03CC Receive Acceptance Filter 1 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 F C2RXF2SID 03D0 — — — Receive Acceptance Filter 2 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u 6 C2RXF2EIDH 03D2 — — — — Receive Acceptance Filter 2 Extended Identifier<17:6> 0000 uuuu uuuu uuuu 0 C2RXF2EIDL 03D4 Receive Acceptance Filter 2 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 1 C2RXF3SID 03D8 — — — Receive Acceptance Filter 3 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u 0 C2RXF3EIDH 03DA — — — — Receive Acceptance Filter 3 Extended Identifier<17:6> 0000 uuuu uuuu uuuu A C2RXF3EIDL 03DC Receive Acceptance Filter 3 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 C2RXF4SID 03E0 — — — Receive Acceptance Filter 4 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u / 6 C2RXF4EIDH 03E2 — — — — Receive Acceptance Filter 4 Extended Identifier<17:6> 0000 uuuu uuuu uuuu C2RXF4EIDL 03E4 Receive Acceptance Filter 4 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 0 C2RXF5SID 03E8 — — — Receive Acceptance Filter 5 Standard Identifier <10:0> — EXIDE 000u uuuu uuuu uu0u 1 C2RXF5EIDH 03EA — — — — Receive Acceptance Filter 5 Extended Identifier<17:6> 0000 uuuu uuuu uuuu 5 C2RXF5EIDL 03EC Receive Acceptance Filter 5 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 C2RXM0SID 03F0 — — — Receive Acceptance Mask 0 Standard Identifier<10:0> — MIDE 000u uuuu uuuu uu0u C2RXM0EIDH 03F2 — — — — Receive Acceptance Mask 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu C2RXM0EIDL 03F4 Receive Acceptance Mask 0 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 C2RXM1SID 03F8 — — — Receive Acceptance Mask 1 Standard Identifier<10:0> — MIDE 000u uuuu uuuu uu0u C2RXM1EIDH 03FA — — — — Receive Acceptance Mask 1 Extended Identifier<17:6> 0000 uuuu uuuu uuuu C2RXM1EIDL 03FC Receive Acceptance Mask 1 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 C2TX2SID 0400 Transmit Buffer 2 Standard Identifier<10:6> — — — Transmit Buffer 2 Standard Identifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu C2TX2EID 0402 Transmit Buffer 2 Extended Identifier<17:14> — — — — Transmit Buffer 2 Extended Identifier<13:6> uuuu 0000 uuuu uuuu C2TX2DLC 0404 Transmit Buffer 2 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000 C2TX2B1 0406 Transmit Buffer 2 Byte 1 Transmit Buffer 2 Byte 0 uuuu uuuu uuuu uuuu © C2TX2B2 0408 Transmit Buffer 2 Byte 3 Transmit Buffer 2 Byte 2 uuuu uuuu uuuu uuuu 2 C2TX2B3 040A Transmit Buffer 2 Byte 5 Transmit Buffer 2 Byte 4 uuuu uuuu uuuu uuuu 0 11 C2TX2B4 040C Transmit Buffer 2 Byte 7 Transmit Buffer 2 Byte 6 uuuu uuuu uuuu uuuu M C2TX2CON 040E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000 ic ro C2TX1SID 0410 Transmit Buffer 1 Standard Identifier<10:6> — — — Transmit Buffer 1 Standard Identifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu c h C2TX1EID 0412 Transmit Buffer 1 Extended Identifier<17:14> — — — — Transmit Buffer 1 Extended Identifier<13:6> uuuu 0000 uuuu uuuu ip T C2TX1DLC 0414 Transmit Buffer 1 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000 e c Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ h n Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. o lo g y In c .

© TABLE 19-2: CAN2 REGISTER MAP FOR dsPIC30F6010A(1) (CONTINUED) 2 0 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 1 M C2TX1B1 0416 Transmit Buffer 1 Byte 1 Transmit Buffer 1 Byte 0 uuuu uuuu uuuu uuuu icro C2TX1B2 0418 Transmit Buffer 1 Byte 3 Transmit Buffer 1 Byte 2 uuuu uuuu uuuu uuuu ch C2TX1B3 041A Transmit Buffer 1 Byte 5 Transmit Buffer 1 Byte 4 uuuu uuuu uuuu uuuu ip T C2TX1B4 041C Transmit Buffer 1 Byte 7 Transmit Buffer 1 Byte 6 uuuu uuuu uuuu uuuu ec C2TX1CON 041E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000 h n C2TX0SID 0420 Transmit Buffer 0 Standard Identifier<10:6> — — — Transmit Buffer 0 Standard Identifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu o lo C2TX0EID 0422 Transmit Buffer 0 Extended Identifier<17:14> — — — — Transmit Buffer 0 Extended Identifier<13:6> uuuu 0000 uuuu uuuu g y In C2TX0DLC 0424 Transmit Buffer 0 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000 c C2TX0B1 0426 Transmit Buffer 0 Byte 1 Transmit Buffer 0 Byte 0 uuuu uuuu uuuu uuuu . C2TX0B2 0428 Transmit Buffer 0 Byte 3 Transmit Buffer 0 Byte 2 uuuu uuuu uuuu uuuu C2TX0B3 042A Transmit Buffer 0 Byte 5 Transmit Buffer 0 Byte 4 uuuu uuuu uuuu uuuu C2TX0B4 042C Transmit Buffer 0 Byte 7 Transmit Buffer 0 Byte 6 uuuu uuuu uuuu uuuu C2TX0CON 042E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000 C2RX1SID 0430 — — — Receive Buffer 1 Standard Identifier<10:0> SRR RXIDE 000u uuuu uuuu uuuu C2RX1EID 0432 — — — — Receive Buffer 1 Extended Identifier <17:6> 0000 uuuu uuuu uuuu C2RX1DLC 0434 Receive Buffer 1 Extended Identifier<5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu C2RX1B1 0436 Receive Buffer 1 Byte 1 Receive Buffer 1 Byte 0 uuuu uuuu uuuu uuuu C2RX1B2 0438 Receive Buffer 1 Byte 3 Receive Buffer 1 Byte 2 uuuu uuuu uuuu uuuu C2RX1B3 043A Receive Buffer 1 Byte 5 Receive Buffer 1 Byte 4 uuuu uuuu uuuu uuuu C2RX1B4 043C Receive Buffer 1 Byte 7 Receive Buffer 1 Byte 6 uuuu uuuu uuuu uuuu C2RX1CON 043E — — — — — — — — RXFUL — — — RXRTRRO FILHIT<2:0> 0000 0000 0000 0000 d C2RX0SID 0440 — — — Receive Buffer 0 Standard Identifier<10:0> SRR RXIDE 000u uuuu uuuu uuuu s C2RX0EID 0442 — — — — Receive Buffer 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu P C2RX0DLC 0444 Receive Buffer 0 Extended Identifier<5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu C2RX0B1 0446 Receive Buffer 0 Byte 1 Receive Buffer 0 Byte 0 uuuu uuuu uuuu uuuu IC C2RX0B2 0448 Receive Buffer 0 Byte 3 Receive Buffer 0 Byte 2 uuuu uuuu uuuu uuuu C2RX0B3 044A Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 4 uuuu uuuu uuuu uuuu 3 C2RX0B4 044C Receive Buffer 0 Byte 7 Receive Buffer 0 Byte 6 uuuu uuuu uuuu uuuu 0 C2RX0CON 044E — — — — — — — — RXFUL — — — RXRTRRO DBEN JTOFF FILHIT00000 0000 0000 0000 F C2CTRL 0450 CANCAP — CSIDLE ABAT CANCKS REQOP<2:0> OPMODE<2:0> — ICODE<2:0> — 0000 0100 1000 0000 6 C2CFG1 0452 — — — — — — — — SJW<1:0> BRP<5:0> 0000 0000 0000 0000 0 C2CFG2 0454 WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0u00 0uuu uuuu uuuu 1 C2INTF 0456 RX0OVR RX1OVR TXBO TXEP RXEP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000 0000 0000 0 D C2INTE 0458 — — — — — — — — IVRIE WAKIE ERRIE TX2IE TX1IE TX0IE RX1E RX0IE 0000 0000 0000 0000 S7 C2EC 045A Transmit Error Count Register Receive Error Count Register 0000 0000 0000 0000 A 0 1 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ / 50 Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 6 E -p 0 a g 1 e 1 5 3 7

dsPIC30F6010A/6015 NOTES: DS70150E-page 138 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 20.0 10-BIT HIGH-SPEED ANALOG- The A/D module has six 16-bit registers: TO-DIGITAL CONVERTER • A/D Control Register 1 (ADCON1) (ADC) MODULE • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) Note: This data sheet summarizes features of • A/D Input Select Register (ADCHS) this group ofdsPIC30F devices and is not • A/D Port Configuration Register (ADPCFG) intended to be a complete reference • A/D Input Scan Selection Register (ADCSSL) source. For more information on the CPU, peripherals, register descriptions and The ADCON1, ADCON2 and ADCON3 registers general device functionality, refer to the control the operation of the A/D module. The ADCHS “dsPIC30F Family Reference Manual” register selects the input channels to be converted. The (DS70046). ADPCFG register configures the port pins as analog inputs or as digital I/O. The ADCSSL register selects The 10-bit High-Speed Analog-to-Digital Converter inputs for scanning. (ADC) allows conversion of an analog input signal to a 10-bit digital number. This module is based on a Suc- Note: The SSRC<2:0>, ASAM, SIMSAM, cessive Approximation Register (SAR) architecture, SMPI<3:0>, BUFM and ALTS bits, as well and provides a maximum sampling rate of 1 Msps. The as the ADCON3 and ADCSSL registers, A/D module has 16 analog inputs which are multi- must not be written to while ADON = 1. plexed into four sample and hold amplifiers. The output This would lead to indeterminate results. of the sample and hold is the input into the converter, The block diagram of the A/D module is shown in which generates the result. The analog reference volt- Figure20-1. ages are software selectable to either the device sup- ply voltage (AVDD/AVSS) or the voltage level on the (VREF+/VREF-) pin. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. © 2011 Microchip Technology Inc. DS70150E-page 139

dsPIC30F6010A/6015 FIGURE 20-1: 10-BIT HIGH-SPEED A/D FUNCTIONAL BLOCK DIAGRAM AVDD VREF+(1) AVSS VREF-(2) AN0 AN0 AN3 + S/H CH1 ADC AN6 - AN9 AN1 AN1 10-bit Result Conversion Logic AN4 + CH2 AN7 -S/H atamat AN10 16-word, 10-bit Dor F Dual Port Buffer AN2 AN2 ce AAANNN1581 +-S/H CH3 CCHH31,,CCHH02, Sample/Sequence Bus Interfa sample Control AN0 AN1 input AN2 switches Input MUX AN3 AN3 Control AN4 AN4 AN5 AN5 AN6 AN6 AN7 AN7 AN8 AN8 AN9 AN9 AN10 AN10 AN11 AN11 AN12 AN12 AN13 AN13 AN14 AN14 AN15 AN15 + S/H CH0 AN1 - Note 1: VREF+ is multiplexed with AN0 in the dsPIC30F6015 variant. 2: VREF- is multiplexed with AN1 in the dsPIC30F6015 variant. DS70150E-page 140 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 20.1 A/D Result Buffer The CHPS bits selects how many channels are sam- pled. This can vary from 1, 2 or 4 channels. If CHPS The module contains a 16-word dual port, read-only buf- selects 1 channel, the CH0 channel will be sampled at fer, called ADCBUF0...ADCBUFF, to buffer the A/D the sample clock and converted. The result is stored in results. The RAM is 10-bits wide, but is read into different the buffer. If CHPS selects 2 channels, the CH0 and format 16-bit words. The contents of the sixteen A/D CH1 channels will be sampled and converted. If CHPS Conversion Result Buffer registers, ADCBUF0 through selects 4 channels, the CH0, CH1, CH2 and CH3 ADCBUFF, cannot be written by user software. channels will be sampled and converted. The SMPI bits select the number of acquisition/conver- 20.2 Conversion Operation sion sequences that would be performed before an After the A/D module has been configured, the sample interrupt occurs. This can vary from 1 sample per acquisition is started by setting the SAMP bit. Various interrupt to 16 samples per interrupt. sources, such as a programmable bit, timer time-outs and The user cannot program a combination of CHPS and external events, will terminate acquisition and start a con- SMPI bits that specifies more than 16 conversions per version. When the A/D conversion is complete, the result interrupt, or 8 conversions per interrupt, depending on is loaded into ADCBUF0...ADCBUFF, and the A/D the BUFM bit. The BUFM bit, when set, will split the Interrupt Flag ADIF and the DONE bit are set after the 16-word results buffer (ADCBUF0...ADCBUFF) into number of samples specified by the SMPI bit. two 8-word groups. Writing to the 8-word buffers will be The following steps should be followed for doing an alternated on each interrupt event. Use of the BUFM bit A/D conversion: will depend on how much time is available for moving data out of the buffers after the interrupt, as determined 1. Configure the A/D module: by the application. - Configure analog pins, voltage reference If the processor can quickly unload a full buffer within and digital I/O the time it takes to acquire and convert one channel, - Select A/D input channels the BUFM bit can be ‘0’ and up to 16 conversions may - Select A/D conversion clock be done per interrupt. The processor will have one - Select A/D conversion trigger sample and conversion time to move the sixteen - Turn on A/D module conversions. 2. Configure A/D interrupt (if required): If the processor cannot unload the buffer within the acqui- - Clear ADIF bit sition and conversion time, the BUFM bit should be ‘1’. - Select A/D interrupt priority For example, if SMPI<3:0> (ADCON2<5:2>=0111), then eight conversions will be loaded into 1/2 of the buf- 3. Start sampling. fer, following which an interrupt occurs. The next eight 4. Wait the required acquisition time. conversions will be loaded into the other 1/2 of the buffer. 5. Trigger acquisition end, start conversion The processor will have the entire time between 6. Wait for A/D conversion to complete, by either: interrupts to move the eight conversions. - Waiting for the A/D interrupt The ALTS bit can be used to alternate the inputs 7. Read A/D result buffer, clear ADIF if required. selected during the sampling sequence. The input multiplexer has two sets of sample inputs: MUX A and 20.3 Selecting the Conversion MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are Sequence selected for sampling. If the ALTS bit is ‘1’ and SMPI<3:0> = 0000, on the first sample/convert Several groups of control bits select the sequence in sequence, the MUX A inputs are selected, and on the which the A/D connects inputs to the sample/hold next acquire/convert sequence, the MUX B inputs are channels, converts channels, writes the buffer memory, selected. and generates interrupts. The sequence is controlled The CSCNA bit (ADCON2<10>) will allow the CH0 by the sampling clocks. channel inputs to be alternately scanned across a The SIMSAM bit controls the acquire/convert selected number of analog inputs for the MUX A group. sequence for multiple channels. If the SIMSAM bit is The inputs are selected by the ADCSSL register. If a ‘0’, the two or four selected channels are acquired and particular bit in the ADCSSL register is ‘1’, the corre- converted sequentially, with two or four sample clocks. sponding input is selected. The inputs are always If the SIMSAM bit is ‘1’, two or four selected channels scanned from lower to higher numbered inputs, starting are acquired simultaneously, with one sample clock. after each interrupt. If the number of inputs selected is The channels are then converted sequentially. Obvi- greater than the number of samples taken per interrupt, ously, if there is only 1 channel selected, the SIMSAM the higher numbered inputs are unused. bit is not applicable. © 2011 Microchip Technology Inc. DS70150E-page 141

dsPIC30F6010A/6015 20.4 Programming the Start of 20.6 Selecting the A/D Conversion Conversion Trigger Clock The conversion trigger will terminate acquisition and The A/D conversion requires 12 TAD. The source of the start the requested conversions. A/D conversion clock is software selected using a 6-bit The SSRC<2:0> bits select the source of the counter. There are 64 possible options for TAD. conversion trigger. EQUATION 20-1: A/D CONVERSION CLOCK The SSRC bits provide for up to five alternate sources of conversion trigger. TAD = TCY * (0.5 * (ADCS<5:0> + 1)) When SSRC<2:0> = 000, the conversion trigger is TAD ADCS<5:0> = 2 – 1 under software control. Clearing the SAMP bit will TCY cause the conversion trigger. The internal RC oscillator is selected by setting the When SSRC<2:0> = 111 (Auto-Start mode), the con- ADRC bit. version trigger is under A/D clock control. The SAMC bits select the number of A/D clocks between the start For correct A/D conversions, the A/D conversion clock of acquisition and the start of conversion. This provides (TAD) must be selected to ensure a minimum TAD time the fastest conversion rates on multiple channels. of 83.33 nsec (for VDD = 5V). Refer to Section24.0 SAMC must always be at least one clock cycle. “Electrical Characteristics” for minimum TAD under other operating conditions. Other trigger sources can come from timer modules, motor control PWM module, or external interrupts. Example20-1 shows a sample calculation for the ADCS<5:0> bits, assuming a device operating speed Note: To operate the A/D at the maximum speci- of 30 MIPS. fied conversion speed, the Auto-Convert Trigger option should be selected EXAMPLE 20-1: A/D CONVERSION CLOCK (SSRC=111) and the Auto-Sample Time CALCULATION bits should be set to 1 TAD (SAMC=00001). This configuration will give a total conversion period (sample + TAD = 84 nsec convert) of 13 TAD. TCY = 33 nsec (30 MIPS) The use of any other conversion trigger TAD will result in additional TAD cycles to ADCS<5:0> = 2 T C Y – 1 synchronize the external event to the A/D. 84 nsec = 2 • – 1 33 nsec 20.5 Aborting a Conversion = 4.09 Clearing the ADON bit during a conversion will abort Therefore, the current conversion and stop the sampling sequenc- Set ADCS<5:0> = 9 ing. The ADCBUF will not be updated with the partially completed A/D conversion sample. That is, the TCY Actual TAD = (ADCS<5:0> + 1) ADCBUF will continue to contain the value of the last 2 completed conversion (or the last value written to the 33 nsec = (9 + 1) ADCBUF register). 2 If the clearing of the ADON bit coincides with an = 99 nsec auto-start, the clearing has a higher priority. After the A/D conversion is aborted, a 2 TAD wait is required before the next sampling may be started by setting the SAMP bit. If sequential sampling is specified, the A/D will continue at the next sample pulse which corresponds with the next channel converted. If simultaneous sampling is specified, the A/D will continue with the next multichannel group conversion sequence. DS70150E-page 142 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 20.7 A/D Conversion Speeds The dsPIC30F 10-bit A/D converter specifications permit a maximum 1 Msps sampling rate. Table20-1 summarizes the conversion speeds for the dsPIC30F 10-bit A/D converter and the required operating conditions. TABLE 20-1: 10-BIT A/D CONVERSION RATE PARAMETERS dsPIC30F 10-bit A/D Converter Conversion Rates A/D TAD Sampling RS Max VDD Temperature A/D Channels Configuration Speed Minimum Time Min Up to 83.33 ns 12 TAD 500Ω 4.5V -40°C to +85°C 1 Msps(1) to VREF-VREF+ 5.5V CH1, 2 or 3 ANx S/H ADC CH0 S/H Up to 95.24 ns 2 TAD 500Ω 4.5V -40°C to +85°C 750 to ksps(1) 5.5V VREF-VREF+ ANx CHX S/H ADC Up to 138.89 ns 12 TAD 500Ω 3.0V -40°C to +125°C 600 to VREF-VREF+ ksps(1) 5.5V CH1, 2 or 3 ANx S/H ADC CH0 S/H Up to 153.85 ns 1 TAD 5.0 kΩ 4.5V -40°C to +125°C 500 ksps to VREF-VREF+ 5.5V or or AVSS AVDD ANx CHX S/H ADC ANx or VREF- Up to 256.41 ns 1 TAD 5.0 kΩ 3.0V -40°C to +125°C 300 ksps to VREF-VREF+ or or 5.5V AVSS AVDD ANx CHX S/H ADC ANx or VREF- Note1: External VREF- and VREF+ pins must be used for correct operation. See Figure20-2 for recommended circuit. © 2011 Microchip Technology Inc. DS70150E-page 143

dsPIC30F6010A/6015 The configuration guidelines give the required setup values for the conversion speeds above 500 ksps, since they require external VREF pins usage and there are some differences in the configuration procedure. Configuration details that are not critical to the conversion speed have been omitted. Figure20-2 depicts the recommended circuit for the conversion rates above 500 ksps. FIGURE 20-2: A/D CONVERTER VOLTAGE REFERENCE SCHEMATIC VDD DDSS VDD VDD VDD VV C8 C7 C6 1 μF 0.1 μF 0.01 μF VDD VSS dsPIC30F6010A VSS VDD VDD VDD VDD VDD VDD C5 C4 C3 1 μF 0.1 μF 0.01 μF VDD R2 -EF+EFDDSS SD RRVV SD 10 VVAA VV R1 VDD C2 C1 10 0.1 μF 0.01 μF VDD 20.7.1 1 Msps CONFIGURATION 20.7.1.2 Multiple Analog Inputs GUIDELINE The A/D converter can also be used to sample multiple The configuration for 1 Msps operation is dependent on analog inputs using multiple sample and hold channels. whether a single input pin is to be sampled or whether In this case, the total 1 Msps conversion rate is divided multiple pins will be sampled. among the different input signals. For example, four inputs can be sampled at a rate of 250 ksps for each 20.7.1.1 Single Analog Input signal or two inputs could be sampled at a rate of 500ksps for each signal. Sequential sampling must be For conversions at 1 Msps for a single analog input, at used in this configuration to allow adequate sampling least two sample and hold channels must be enabled. time on each input. The analog input multiplexer must be configured so that the same input pin is connected to both sample and hold channels. The A/D converts the value held on one S/H channel, while the second S/H channel acquires a new input sample. DS70150E-page 144 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 20.7.1.3 1 Msps Configuration Items to the ADCHS register The following configuration items are required to 20.7.3 600 ksps CONFIGURATION achieve a 1 Msps conversion rate. GUIDELINE • Comply with conditions provided in Figure20-1 The configuration for 600 ksps operation is dependent • Connect external VREF+ and VREF- pins following on whether a single input pin is to be sampled or the recommended circuit shown in Figure20-2 whether multiple pins will be sampled. • Set SSRC<2:0> = 111 in the ADCON1 register to enable the auto-convert option 20.7.3.1 Single Analog Input • Enable automatic sampling by setting the ASAM When performing conversions at 600 ksps for a single control bit in the ADCON1 register analog input, at least two sample and hold channels • Enable sequential sampling by clearing the must be enabled. The analog input multiplexer must be SIMSAM bit in the ADCON1 register configured so that the same input pin is connected to • Enable at least two sample and hold channels by both sample and hold channels. The A/D converts the writing the CHPS<1:0> control bits in the value held on one S/H channel, while the second S/H ADCON2 register channel acquires a new input sample. • Write the SMPI<3:0> control bits in the ADCON2 20.7.3.2 Multiple Analog Input register for the desired number of conversions between interrupts. At a minimum, set The A/D converter can also be used to sample multiple SMPI<3:0> = 0001 since at least two sample and analog inputs using multiple sample and hold channels. hold channels should be enabled In this case, the total 600 ksps conversion rate is • Configure the A/D clock period to be: divided among the different input signals. For example, 1 four inputs can be sampled at a rate of 150 ksps for = 83.33 ns each signal or two inputs can be sampled at a rate of 12 x 1,000,000 300 ksps for each signal. Sequential sampling must be by writing to the ADCS<5:0> control bits in the used in this configuration to allow adequate sampling ADCON3 register time on each input. • Configure the sampling time to be 2 TAD by 20.7.3.3 600 ksps Configuration Items writing: SAMC<4:0> = 00010 • Select at least two channels per analog input pin The following configuration items are required to achieve a 600 ksps conversion rate. by writing to the ADCHS register • Comply with conditions provided in Figure20-1 20.7.2 750 ksps CONFIGURATION • Connect external VREF+ and VREF- pins following GUIDELINE the recommended circuit shown in Figure20-2 The following configuration items are required to achieve • Set SSRC<2:0> = 111 in the ADCON1 register to a 750 ksps conversion rate. This configuration assumes enable the auto-convert option that a single analog input is to be sampled. • Enable automatic sampling by setting the ASAM control bit in the ADCON1 register • Comply with conditions provided in Figure20-1 • Enable sequential sampling by clearing the • Connect external VREF+ and VREF- pins following SIMSAM bit in the ADCON1 register the recommended circuit shown in Figure20-2 • Enable at least two sample and hold channels by • Set SSRC<2:0> = 111 in the ADCON1 register to writing the CHPS<1:0> control bits in the ADCON2 enable the auto-convert option register • Enable automatic sampling by setting the ASAM • Write the SMPI<3:0> control bits in the ADCON2 control bit in the ADCON1 register register for the desired number of conversions • Enable one sample and hold channel by setting between interrupts. At a minimum, set CHPS<1:0> = 00 in the ADCON2 register SMPI<3:0> = 0001 since at least two sample and • Write the SMPI<3:0> control bits in the ADCON2 hold channels should be enabled register for the desired number of conversions • Configure the A/D clock period to be: between interrupts 1 • Configure the A/D clock period to be: = 138.89 ns 1 12 x 600,000 = 95.24 ns (12 + 2) X 750,000 by writing to the ADCS<5:0> control bits in the ADCON3 register by writing to the ADCS<5:0> control bits in the ADCON3 register • Configure the sampling time to be 2 TAD by • Configure the sampling time to be 2 TAD by writing: writing: SAMC<4:0> = 00010 SAMC<4:0> = 00010 • Select at least two channels per analog input pin • Select one channel per analog input pin by writing by writing to the ADCHS register © 2011 Microchip Technology Inc. DS70150E-page 145

dsPIC30F6010A/6015 20.8 A/D Acquisition Requirements The user must allow at least 1 TAD period of sampling time, TSAMP, between conversions to allow each sam- The analog input model of the 10-bit A/D converter is ple to be acquired. This sample time may be controlled shown in Figure20-3. The total sampling time for the manually in software by setting/clearing the SAMP bit, A/D is a function of the internal amplifier settling time, or it may be automatically controlled by the A/D con- device VDD and the holding capacitor charge time. verter. In an automatic configuration, the user must For the A/D converter to meet its specified accuracy, allow enough time between conversion triggers so that the charge holding capacitor (CHOLD) must be allowed the minimum sample time can be satisfied. Refer to to fully charge to the voltage level on the analog input Section24.0 “Electrical Characteristics” for TAD and pin. The analog output source impedance (RS), the sample time requirements. interconnect impedance (RIC), and the internal sam- pling switch (RSS) impedance combine to directly affect the time required to charge the capacitor CHOLD. The combined impedance must therefore be small enough to fully charge the holding capacitor within the chosen sample time. To minimize the effects of pin leakage currents on the accuracy of the A/D converter, the max- imum recommended source impedance, RS, is 5 kΩ for conversion rates up to 500 ksps and a maximum of 500Ω for conversion rates up to 1 Msps. After the analog input channel is selected (changed), this sam- pling function must be completed prior to starting the conversion. The internal holding capacitor will be in a discharged state prior to each sample operation. FIGURE 20-3: A/D CONVERTER ANALOG INPUT MODEL VDD RIC ≤ 250Ω Sampling RSS ≤ 3 kΩ Switch VT = 0.6V Rs ANx RSS CHOLD VA CPIN I leakage = DAC capacitance VT = 0.6V ± 500 nA = 4.4 pF VSS Legend:CPIN = input capacitance VT = threshold voltage I leakage = leakage current at the pin due to various junctions RIC = interconnect resistance RSS = sampling switch resistance CHOLD = sample/hold capacitance (from DAC) Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ. DS70150E-page 146 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 20.9 Module Power-Down Modes If the A/D interrupt is enabled, the device will wake-up from Sleep. If the A/D interrupt is not enabled, the A/D The module has 3 internal power modes. When the module will then be turned off, although the ADON bit ADON bit is ‘1’, the module is in Active mode; it is fully will remain set. powered and functional. When ADON is ‘0’, the module is in Off mode. The digital and analog portions of the 20.10.2 A/D OPERATION DURING CPU IDLE circuit are disabled for maximum current savings. In MODE order to return to the Active mode from Off mode, the The ADSIDL bit selects if the module will stop on Idle or user must wait for the ADC circuitry to stabilize. continue on Idle. If ADSIDL = 0, the module will continue operation on assertion of Idle mode. If ADSIDL = 1, the 20.10 A/D Operation During CPU Sleep module will stop on Idle. and Idle Modes 20.11 Effects of a Reset 20.10.1 A/D OPERATION DURING CPU SLEEP MODE A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off, and any When the device enters Sleep mode, all clock sources conversion and acquisition sequence is aborted. The to the module are shutdown and stay at logic ‘0’. values that are in the ADCBUF registers are not modi- If Sleep occurs in the middle of a conversion, the con- fied. The A/D Result register will contain unknown data version is aborted. The converter will not continue with after a Power-on Reset. a partially completed conversion on exit from Sleep mode. 20.12 Output Formats Register contents are not affected by the device The A/D result is 10 bits wide. The data buffer RAM is entering or leaving Sleep mode. also 10 bits wide. The 10-bit data can be read in one of The A/D module can operate during Sleep mode if the four different formats. The FORM<1:0> bits select the A/D clock source is set to RC (ADRC = 1). When the format. Each of the output formats translates to a 16-bit RC clock source is selected, the A/D module waits one result on the data bus. instruction cycle before starting the conversion. This Write data will always be in right justified (integer) allows the SLEEP instruction to be executed, which format. eliminates all digital switching noise from the conver- sion. When the conversion is complete, the DONE bit will be set and the result loaded into the ADCBUF register. FIGURE 20-4: A/D OUTPUT DATA FORMATS RAM Contents: d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Read to Bus: Signed Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0 Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0 Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Integer 0 0 0 0 0 0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 © 2011 Microchip Technology Inc. DS70150E-page 147

dsPIC30F6010A/6015 20.13 Configuring Analog Port Pins 20.14 Connection Considerations The use of the ADPCFG and TRIS registers control the The analog inputs have diodes to VDD and VSS as ESD operation of the A/D port pins. The port pins that are protection. This requires that the analog input be desired as analog inputs must have their correspond- between VDD and VSS. If the input voltage exceeds this ing TRIS bit set (input). If the TRIS bit is cleared (out- range by greater than 0.3V (either direction), one of the put), the digital output level (VOH or VOL) will be diodes becomes forward biased and it may damage the converted. device if the input current specification is exceeded. The A/D operation is independent of the state of the An external RC filter is sometimes added for anti- CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits. aliasing of the input signal. The R component should be selected to ensure that the sampling time requirements When reading the PORT register, all pins configured as are satisfied. Any external components connected (via analog input channels will read as cleared. high-impedance) to an analog input pin (capacitor, Pins configured as digital inputs will not convert an Zener diode, etc.) should have very little leakage analog input. Analog levels on any pin that is defined as current at the pin. a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. DS70150E-page 148 © 2011 Microchip Technology Inc.

© TABLE 20-2: ADC REGISTER MAP(1) 2 01 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 M ADCBUF0 0280 — — — — — — ADC Data Buffer 0 0000 00uu uuuu uuuu ic ro ADCBUF1 0282 — — — — — — ADC Data Buffer 1 0000 00uu uuuu uuuu c hip ADCBUF2 0284 — — — — — — ADC Data Buffer 2 0000 00uu uuuu uuuu T ADCBUF3 0286 — — — — — — ADC Data Buffer 3 0000 00uu uuuu uuuu e c h ADCBUF4 0288 — — — — — — ADC Data Buffer 4 0000 00uu uuuu uuuu n olo ADCBUF5 028A — — — — — — ADC Data Buffer 5 0000 00uu uuuu uuuu g y ADCBUF6 028C — — — — — — ADC Data Buffer 6 0000 00uu uuuu uuuu Inc ADCBUF7 028E — — — — — — ADC Data Buffer 7 0000 00uu uuuu uuuu . ADCBUF8 0290 — — — — — — ADC Data Buffer 8 0000 00uu uuuu uuuu ADCBUF9 0292 — — — — — — ADC Data Buffer 9 0000 00uu uuuu uuuu ADCBUFA 0294 — — — — — — ADC Data Buffer 10 0000 00uu uuuu uuuu ADCBUFB 0296 — — — — — — ADC Data Buffer 11 0000 00uu uuuu uuuu ADCBUFC 0298 — — — — — — ADC Data Buffer 12 0000 00uu uuuu uuuu ADCBUFD 029A — — — — — — ADC Data Buffer 13 0000 00uu uuuu uuuu ADCBUFE 029C — — — — — — ADC Data Buffer 14 0000 00uu uuuu uuuu ADCBUFF 029E — — — — — — ADC Data Buffer 15 0000 00uu uuuu uuuu ADCON1 02A0 ADON — ADSIDL — — — FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000 0000 0000 0000 ADCON2 02A2 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000 0000 0000 0000 ADCON3 02A4 — — — SAMC<4:0> ADRC — ADCS<5:0> 0000 0000 0000 0000 d ADCHS 02A6 CH123NB<1:0> CH123SB CH0NB CH0SB<3:0> CH123NA<1:0> CH123SA CH0NA CH0SA<3:0> 0000 0000 0000 0000 s ADPCFG 02A8 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000 P ADCSSL 02AA CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ I C Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 3 0 F 6 0 1 0 D S A 7 0 1 / 50 6 E -p 0 a g 1 e 1 5 4 9

dsPIC30F6010A/6015 NOTES: DS70150E-page 150 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 21.0 SYSTEM INTEGRATION 21.1 Oscillator System Overview The dsPIC30F oscillator system has the following Note: This data sheet summarizes features of modules and features: this group ofdsPIC30F devices and is not intended to be a complete reference • Various external and internal oscillator options as source. For more information on the CPU, clock sources peripherals, register descriptions and • An on-chip PLL to boost internal operating general device functionality, refer to the frequency “dsPIC30F Family Reference Manual” • A clock switching mechanism between various (DS70046). For more information on the clock sources device instruction set and programming, • Programmable clock postscaler for system power refer to the “16-bit MCU and DSC Pro- savings grammer’s Reference Manual” (DS70157). • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and takes fail-safe measures There are several features intended to maximize • Clock Control register (OSCCON) system reliability, minimize cost through elimination of • Configuration bits for main oscillator selection external components, provide power-saving operating modes and offer code protection: Configuration bits determine the clock source upon Power-on Reset (POR) and Brown-out Reset (BOR). • Oscillator Selection Thereafter, the clock source can be changed between • Reset permissible clock sources. The OSCCON register con- - Power-on Reset (POR) trols the clock switching and reflects system clock - Power-up Timer (PWRT) related Status bits. - Oscillator Start-up Timer (OST) Table21-1 provides a summary of the dsPIC30F - Programmable Brown-out Reset (BOR) oscillator operating modes. A simplified diagram of the • Watchdog Timer (WDT) oscillator system is shown in Figure21-1. • Power-Saving modes (Sleep and Idle) • Code Protection • Unit ID Locations • In-Circuit Serial Programming (ICSP) dsPIC30F devices have a Watchdog Timer, which is permanently enabled via the Configuration bits or can be software controlled. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a delay on power-up only, designed to keep the part in Reset while the power supply stabilizes. With these two tim- ers on-chip, most applications need no external Reset circuitry. Sleep mode is designed to offer a very low-current Power-Down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer Wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit a wide variety of applications. In the Idle mode, the clock sources are still active, but the CPU is shut-off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2011 Microchip Technology Inc. DS70150E-page 151

dsPIC30F6010A/6015 TABLE 21-1: OSCILLATOR OPERATING MODES Oscillator Mode Description XTL 200 kHz-4 MHz crystal on OSC1:OSC2 XT 4 MHz-10 MHz crystal on OSC1:OSC2 XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled XT w/PLL 16x 4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled(1) LP 32 kHz crystal on SOSCO:SOSCI(2) HS 10 MHz-25 MHz crystal. HS/2 w/PLL 4x 10 MHz-20 MHz crystal, divide by 2, 4x PLL enabled(3) HS/2 w/PLL 8x 10 MHz-20 MHz crystal, divide by 2, 8x PLL enabled(3) HS/2 w/PLL 16x 10 MHz-15 MHz crystal, divide by 2, 16x PLL enabled(1) HS/3 w/PLL 4x 12 MHz-25 MHz crystal, divide by 3, 4x PLL enabled(4) HS/3 w/PLL 8x 12 MHz-25 MHz crystal, divide by 3, 8x PLL enabled(4) HS/3 w/PLL 16x 12 MHz-22.5 MHz crystal, divide by 3, 16x PLL enabled(1)(4) EC External clock input (0-40 MHz) ECIO External clock input (0-40 MHz), OSC2 pin is I/O EC w/PLL 4x External clock input (4-10 MHz), OSC2 pin is I/O, 4x PLL enabled EC w/PLL 8x External clock input (4-10 MHz), OSC2 pin is I/O, 8x PLL enabled EC w/PLL 16x External clock input (4-7.5 MHz), OSC2 pin is I/O, 16x PLL enabled(1) ERC External RC oscillator, OSC2 pin is FOSC/4 output(5) ERCIO External RC oscillator, OSC2 pin is I/O(5) FRC 7.37 MHz internal RC oscillator FRC w/PLL 4x 7.37 MHz internal RC oscillator, 4x PLL enabled FRC w/PLL 8x 7.37 MHz internal RC oscillator, 8x PLL enabled FRC w/PLL 16x 7.37 MHz internal RC oscillator, 16x PLL enabled LPRC 512 kHz internal RC oscillator Note 1: Any higher will violate device operating frequency range. 2: LP oscillator can be conveniently shared as system clock, as well as Real-Time Clock for Timer1. 3: Any higher will violate PLL input range. 4: Any lower will violate PLL input range. 5: Requires external R and C. Frequency operation up to 4 MHz. DS70150E-page 152 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 21-1: OSCILLATOR SYSTEM BLOCK DIAGRAM Oscillator Configuration bits PWRSAV Instruction Wake-up Request FPLL OSC1 Primary PLL Oscillator x4, x8, x16 PLL OSC2 Lock COSC<2:0> Primary Osc TUN<5:0> NOSC<2:0> 6 Primary OSWEN Oscillator Stability Detector Internal Fast RC Oscillator (FRC) Oscillator POR Done Start-up Clock Timer Switching Programmable and Control Secondary Osc Clock Divider System Block Clock SOSCO Secondary 32 kHz LP 2 Oscillator Oscillator SOSCI Stability Detector POST<1:0> Internal Low- LPRC Power RC Oscillator (LPRC) CF Fail-Safe Clock FCKSM<1:0> Monitor (FSCM) 2 Oscillator Trap to Timer1 © 2011 Microchip Technology Inc. DS70150E-page 153

dsPIC30F6010A/6015 21.2 Oscillator Configurations 21.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<2:0> Configuration bits that select one of four oscillator groups, b) and FPR<4:0> Configuration bits that select one of 16 oscillator choices within the primary group. The selection is as shown in Table21-2. TABLE 21-2: .CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Oscillator Mode FOS<2:0> FPR<4:0> OSC2 Function Source ECIO w/PLL 4x PLL 1 1 1 0 1 1 0 1 I/O ECIO w/PLL 8x PLL 1 1 1 0 1 1 1 0 I/O ECIO w/PLL 16x PLL 1 1 1 0 1 1 1 1 I/O FRC w/PLL 4x PLL 1 1 1 0 0 0 0 1 I/O FRC w/PLL 8x PLL 1 1 1 0 1 0 1 0 I/O FRC w/PLL 16x PLL 1 1 1 0 0 0 1 1 I/O XT w/PLL 4x PLL 1 1 1 0 0 1 0 1 OSC2 XT w/PLL 8x PLL 1 1 1 0 0 1 1 0 OSC2 XT w/PLL 16x PLL 1 1 1 0 0 1 1 1 OSC2 HS/2 w/PLL 4x PLL 1 1 1 1 0 0 0 1 OSC2 HS/2 w/PLL 8x PLL 1 1 1 1 0 0 1 0 OSC2 HS/2 w/PLL 16x PLL 1 1 1 1 0 0 1 1 OSC2 HS/3 w/PLL 4x PLL 1 1 1 1 0 1 0 1 OSC2 HS/3 w/PLL 8x PLL 1 1 1 1 0 1 1 0 OSC2 HS/3 w/PLL 16x PLL 1 1 1 1 0 1 1 1 OSC2 ECIO External 0 1 1 0 1 1 0 0 I/O XT External 0 1 1 0 0 1 0 0 OSC2 HS External 0 1 1 0 0 0 1 0 OSC2 EC External 0 1 1 0 1 0 1 1 CLKO ERC External 0 1 1 0 1 0 0 1 CLKO ERCIO External 0 1 1 0 1 0 0 0 I/O XTL External 0 1 1 0 0 0 0 0 OSC2 LP Secondary 0 0 0 x x x x x (Note 1, 2) FRC Internal FRC 0 0 1 x x x x x (Note 1, 2) LPRC Internal LPRC 0 1 0 x x x x x (Note 1, 2) Note 1: OSC2 pin function is determined by FPR<4:0>. 2: OSC1 pin cannot be used as an I/O pin even if the secondary oscillator or an internal clock source is selected at all times. DS70150E-page 154 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 21.2.2 OSCILLATOR START-UP TIMER 21.2.5 FAST RC OSCILLATOR (FRC) (OST) The FRC oscillator is a fast (7.37 MHz nominal) internal In order to ensure that a crystal oscillator (or ceramic RC oscillator. This oscillator is intended to provide rea- resonator) has started and stabilized, an Oscillator sonable device operating speeds without the use of an Start-up Timer is included. It is a simple 10-bit counter external crystal, ceramic resonator or RC network. The that counts 1024 TOSC cycles before releasing the FRC oscillator can be used with the PLL to obtain oscillator clock to the rest of the system. The time-out higher clock frequencies. period is designated as TOST. The TOST time is involved The dsPIC30F operates from the FRC oscillator when- every time the oscillator has to restart (i.e., on POR, ever the current oscillator selection control bits in the BOR and wake-up from Sleep). The Oscillator Start-up OSCCON register (OSCCON<14:12>) are set to ‘001’. Timer is applied to the LP, XT, XTL and HS Oscillator The 6-bit field specified by TUN<5:0> (OSCTUN<5:0>) modes (upon wake-up from Sleep, POR and BOR) for allows the user to tune the internal fast RC oscillator the primary oscillator. (nominal 7.37 MHz). The user can tune the FRC oscil- 21.2.3 LP OSCILLATOR CONTROL lator within a range of +12.6% (930 kHz) and -13% (960 kHz) in steps of 0.4% around the factory-calibrated set- Enabling the LP oscillator is controlled with two ting, see Table21-4. elements: Note: OSCTUN functionality has been provided • The current oscillator group bits COSC<2:0> to help customers compensate for • The LPOSCEN bit (OSCCON register) temperature effects on the FRC frequency The LP oscillator is ON (even during Sleep mode) if over a wide range of temperatures. The LPOSCEN = 1. The LP oscillator is the device clock if: tuning step size is an approximation and is neither characterized nor tested. • COSC<2:0> = 000 (LP selected as main oscillator) and If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are • LPOSCEN = 1 set to ‘00101’, ‘00110’ or ‘00111’, then a PLL multiplier of 4, 8 or 16 (respectively) is applied. Keeping the LP oscillator ON at all times allows for a fast switch to the 32 kHz system clock for lower power Note: When a 16x PLL is used, the FRC oscilla- operation. Returning to the faster main oscillator will tor must not be tuned to a frequency still require a start-up time. greater than 7.5 MHz. 21.2.4 PHASE-LOCKED LOOP (PLL) TABLE 21-4: FRC TUNING The PLL multiplies the clock which is generated by the TUN<5:0> primary oscillator. The PLL is selectable to have either FRC Frequency Bits gains of x4, x8 and x16. Input and output frequency 01 1111 +12.6% ranges are summarized in Table21-3. 01 1110 +12.2% TABLE 21-3: PLL FREQUENCY RANGE 01 1101 +11.8% PLL ... ... Fin Fout Multiplier 00 0100 +1.6% 4 MHz-10 MHz x4 16 MHz-40 MHz 00 0011 +1.2% 00 0010 +0.8% 4 MHz-10 MHz x8 32 MHz-80 MHz 00 0001 +0.4% 4 MHz-7.5 MHz x16 64 MHz-120 MHz 00 0000 Center Frequency (oscillator is The PLL features a lock output, which is asserted when running at calibrated frequency) the PLL enters a phase locked state. Should the loop 11 1111 -0.4% fall out of lock (e.g., due to noise), the lock signal will be 11 1110 -0.8% rescinded. The state of this signal is reflected in the read-only LOCK bit in the OSCCON register. 11 1101 -1.2% 11 1100 -1.6% ... ... 10 0011 -11.8% 10 0010 -12.2% 10 0001 -12.6% 10 0000 -13.0% © 2011 Microchip Technology Inc. DS70150E-page 155

dsPIC30F6010A/6015 21.2.6 LOW-POWER RC OSCILLATOR COSC<2:0> bits are loaded with FRC oscillator selec- (LPRC) tion. This will effectively shut-off the original oscillator that was trying to start. The LPRC oscillator is a component of the Watchdog Timer (WDT) and oscillates at a nominal frequency of The user may detect this situation and restart the 512 kHz. The LPRC oscillator is the clock source for oscillator in the clock fail trap ISR. the Power-up Timer (PWRT) circuit, WDT and clock Upon a clock failure detection, the FSCM module will monitor circuits. It may also be used to provide a low initiate a clock switch to the FRC oscillator as follows: frequency clock source option for applications where 1. The COSC bits (OSCCON<14:12>) are loaded power consumption is critical, and timing accuracy is with the FRC oscillator selection value. not required. 2. CF bit is set (OSCCON<3>). The LPRC oscillator is always enabled at a Power-on 3. OSWEN control bit (OSCCON<0>) is cleared. Reset, because it is the clock source for the PWRT. After the PWRT expires, the LPRC oscillator will remain For the purpose of clock switching, the clock sources ON if one of the following is TRUE: are sectioned into four groups: • The Fail-Safe Clock Monitor is enabled • Primary • The WDT is enabled • Secondary • The LPRC oscillator is selected as the system • Internal FRC clock via the COSC<2:0> control bits in the • Internal LPRC OSCCON register The user can switch between these functional groups, If one of the above conditions is not true, the LPRC will but cannot switch between options within a group. If the shut-off after the PWRT expires. primary group is selected, then the choice within the group is always determined by the FPR<4:0> Note1: OSC2 pin function is determined by the Configuration bits. Primary Oscillator mode selection (FPR<4:0>). The OSCCON register holds the control and Status bits related to clock switching. 2: Note that OSC1 pin cannot be used as an I/O pin, even if the secondary oscillator or • COSC<2:0>: Read-only Status bits always reflect an internal clock source is selected at all the current oscillator group in effect. times. • NOSC<2:0>: Control bits which are written to indicate the new oscillator group of choice. 21.2.7 FAIL-SAFE CLOCK MONITOR - On POR and BOR, COSC<2:0> and The Fail-Safe Clock Monitor (FSCM) allows the device NOSC<2:0> are both loaded with the to continue to operate even in the event of an oscillator Configuration bit values FOS<2:0>. failure. The FSCM function is enabled by appropriately • LOCK: The LOCK Status bit indicates a PLL lock. programming the FCKSM Configuration bits (Clock • CF: Read-only Status bit indicating if a clock fail Switch and Monitor Selection bits) in the FOSC device detect has occurred. Configuration register. If the FSCM function is • OSWEN: Control bit changes from a ‘0’ to a ‘1’ enabled, the LPRC internal oscillator will run at all when a clock transition sequence is initiated. times (except during Sleep mode) and will not be Clearing the OSWEN control bit will abort a clock subject to control by the SWDTEN bit. transition in progress (used for hang-up situations). In the event of an oscillator failure, the FSCM will If Configuration bits FCKSM<1:0> = 1x, then the clock generate a clock failure trap event and will switch the sys- switching and Fail-Safe Clock Monitor functions are tem clock over to the FRC oscillator. The user will then disabled. This is the default Configuration bit setting. have the option to either attempt to restart the oscillator or execute a controlled shutdown. The user may decide If clock switching is disabled, then the FOS<2:0> and to treat the trap as a warm Reset by simply loading the FPR<4:0> bits directly control the oscillator selection Reset address into the oscillator fail trap vector. In this and the COSC<2:0> bits do not control the clock event, the CF (Clock Fail) Status bit (OSCCON<3>) is selection. However, these bits will reflect the clock also set whenever a clock failure is recognized. source selection. In the event of a clock failure, the WDT is unaffected Note: The application should not attempt to and continues to run on the LPRC clock. switch to a clock of frequency lower than 100 kHz when the Fail-Safe Clock Monitor If the oscillator has a very slow start-up time coming is enabled. If clock switching is performed, out of POR, BOR or Sleep, it is possible that the the device may generate an oscillator fail PWRT timer will expire before the oscillator has trap and switch to the fast RC oscillator. started. In such cases, the FSCM will be activated and the FSCM will initiate a clock failure trap, and the DS70150E-page 156 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 21.2.8 PROTECTION AGAINST Different registers are affected in different ways by ACCIDENTAL WRITES TO OSCCON various Reset conditions. Most registers are not affected by a WDT wake-up, since this is viewed as the A write to the OSCCON register is intentionally made resumption of normal operation. Status bits from the difficult because it controls clock switching and clock RCON register are set or cleared differently in different scaling. Reset situations, as indicated in Table21-5. These bits To write to the OSCCON low byte, the following code are used in software to determine the nature of the sequence must be executed without any other Reset. instructions in between: A block diagram of the on-chip Reset circuit is shown in Byte Write 0x46 to OSCCON low Figure21-2. Byte Write 0x57 to OSCCON low A MCLR noise filter is provided in the MCLR Reset Byte write is allowed for one instruction cycle. Write the path. The filter detects and ignores small pulses. desired value or use bit manipulation instruction. Internally generated Resets do not drive MCLR pin low. To write to the OSCCON high byte, the following instructions must be executed without any other 21.3.1 POR: POWER-ON RESET instructions in between: A power-on event will generate an internal POR pulse Byte Write 0x78 to OSCCON high when a VDD rise is detected. The Reset pulse will occur Byte Write 0x9A to OSCCON high at the POR circuit threshold voltage (VPOR), which is nominally 1.85V. The device supply voltage character- Byte write is allowed for one instruction cycle. Write the istics must meet specified starting voltage and rise rate desired value or use bit manipulation instruction. requirements. The POR pulse will reset a POR timer and place the device in the Reset state. The POR also 21.3 Reset selects the device clock source identified by the The dsPIC30F differentiates between various kinds of oscillator configuration fuses. Reset: The POR circuit inserts a small delay, TPOR, which is a) Power-on Reset (POR) nominally 10 μs and ensures that the device bias circuits are stable. Furthermore, a user selected power- b) MCLR Reset during normal operation up time-out (TPWRT) is applied. The TPWRT parameter c) MCLR Reset during Sleep is based on device Configuration bits and can be 0 ms d) Watchdog Timer (WDT) Reset (during normal (no delay), 4 ms, 16 ms or 64 ms. The total delay is at operation) device power-up TPOR + TPWRT. When these delays e) Programmable Brown-out Reset (BOR) have expired, SYSRST will be negated on the next f) RESET Instruction leading edge of the Q1 clock, and the PC will jump to the Reset vector. g) Reset caused by trap lockup (TRAPR) h) Reset caused by illegal opcode, or by using an The timing for the SYSRST signal is shown in uninitialized W register as an Address Pointer Figure21-3 through Figure21-5. (IOPUWR) FIGURE 21-2: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Digital Glitch Filter MCLR Sleep or Idle WDT Module VDD Rise POR S Detect VDD Brown-out BOR Reset BOREN Trap Conflict R Q SYSRST Illegal Opcode/ Uninitialized W Register © 2011 Microchip Technology Inc. DS70150E-page 157

dsPIC30F6010A/6015 FIGURE 21-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR Internal POR TOST OST Time-out TPWRT PWRT Time-out Internal Reset FIGURE 21-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR Internal POR TOST OST Time-out TPWRT PWRT Time-out Internal Reset FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR Internal POR TOST OST Time-out TPWRT PWRT Time-out Internal Reset DS70150E-page 158 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 21.3.1.1 POR with Long Crystal Start-up Time A BOR will generate a Reset pulse which will reset the (with FSCM Enabled) device. The BOR will select the clock source, based on the device Configuration bit values (FOS<2:0> and The oscillator start-up circuitry is not linked to the POR FPR<4:0>). Furthermore, if an oscillator mode is circuitry. Some crystal circuits (especially low frequency selected, the BOR will activate the Oscillator Start-up crystals) will have a relatively long start-up time. There- Timer (OST). The system clock is held until OST fore, one or more of the following conditions is possible expires. If the PLL is used, then the clock will be held after the POR timer and the PWRT have expired: until the LOCK bit (OSCCON<5>) is ‘1’. • The oscillator circuit has not begun to oscillate. Concurrently, the POR time-out (TPOR) and the PWRT • The Oscillator Start-up Timer has NOT expired (if time-out (TPWRT) will be applied before the internal a crystal oscillator is used). Reset is released. If TPWRT = 0 and a crystal oscillator • The PLL has not achieved a LOCK (if PLL is is being used, then a nominal delay of TFSCM = 100 μs used). is applied. The total delay in this case is If the FSCM is enabled and one of the above conditions (TPOR+TFSCM). is true, then a clock failure trap will occur. The device The BOR Status bit (RCON<1>) will be set to indicate will automatically switch to the FRC oscillator and the that a BOR has occurred. The BOR circuit, if enabled, user can switch to the desired crystal oscillator in the will continue to operate while in Sleep or Idle modes trap ISR. and will reset the device should VDD fall below the BOR threshold voltage. 21.3.1.2 Operating without FSCM and PWRT If the FSCM is disabled and the Power-up Timer FIGURE 21-6: EXTERNAL POWER-ON (PWRT) is also disabled, then the device will exit rapidly RESET CIRCUIT (FOR from Reset on power-up. If the clock source is FRC, SLOW VDD POWER-UP) LPRC, EXTRC or EC, it will be active immediately. VDD If the FSCM is disabled and the system clock has not started, the device will be in a frozen state at the Reset D R vector until the system clock starts. From the user’s R1 MCLR perspective, the device will appear to be in Reset until a system clock is available. C dsPIC30F 21.3.2 BOR: PROGRAMMABLE BROWN-OUT RESET Note1: External Power-on Reset circuit is required only if the VDD power-up slope The BOR (Brown-out Reset) module is based on an is too slow. The diode D helps discharge internal voltage reference circuit. The main purpose of the capacitor quickly when VDD powers the BOR module is to generate a device Reset when a down. brown-out condition occurs. Brown-out conditions are generally caused by glitches on the AC mains (i.e., 2: R should be suitably chosen so as to missing portions of the AC cycle waveform due to bad make sure that the voltage drop across power transmission lines or voltage sags due to exces- R does not violate the device’s electrical sive current draw when a large inductive load is turned specification. on). 3: R1 should be suitably chosen so as to The BOR module allows selection of one of the limit any current flowing into MCLR from external capacitor C, in the event of following voltage trip points: MCLR/VPP pin breakdown due to Elec- • 2.6V-2.71V trostatic Discharge (ESD) or Electrical • 4.1V-4.4V Overstress (EOS). • 4.58V-4.73V Note: The BOR voltage trip points indicated here Note: Dedicated supervisory devices, such as are nominal values provided for design the MCP1XX and MCP8XX, may also be guidance only. used as an external Power-on Reset circuit. © 2011 Microchip Technology Inc. DS70150E-page 159

dsPIC30F6010A/6015 Table21-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table means that all the bits are negated prior to the action specified in the condition column. TABLE 21-5: INITIALIZATION CONDITION FOR RCON REGISTER CASE 1 Program Condition TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR Counter Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1 Brown-out Reset 0x000000 0 0 0 0 0 0 0 0 1 MCLR Reset during normal 0x000000 0 0 1 0 0 0 0 0 0 operation Software Reset during 0x000000 0 0 0 1 0 0 0 0 0 normal operation MCLR Reset during Sleep 0x000000 0 0 1 0 0 0 1 0 0 MCLR Reset during Idle 0x000000 0 0 1 0 0 1 0 0 0 WDT Time-out Reset 0x000000 0 0 0 0 1 0 0 0 0 WDT Wake-up PC + 2 0 0 0 0 1 0 1 0 0 Interrupt Wake-up from Sleep PC + 2(1) 0 0 0 0 0 0 1 0 0 Clock Failure Trap 0x000004 0 0 0 0 0 0 0 0 0 Trap Reset 0x000000 1 0 0 0 0 0 0 0 0 Illegal Operation Trap 0x000000 0 1 0 0 0 0 0 0 0 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. Table21-6 shows a second example of the bit conditions for the RCON register. In this case, it is not assumed the user has set/cleared specific bits prior to action specified in the condition column. TABLE 21-6: INITIALIZATION CONDITION FOR RCON REGISTER CASE 2 Program Condition TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR Counter Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1 Brown-out Reset 0x000000 u u u u u u u 0 1 MCLR Reset during normal 0x000000 u u 1 0 0 0 0 u u operation Software Reset during 0x000000 u u 0 1 0 0 0 u u normal operation MCLR Reset during Sleep 0x000000 u u 1 u 0 0 1 u u MCLR Reset during Idle 0x000000 u u 1 u 0 1 0 u u WDT Time-out Reset 0x000000 u u 0 0 1 0 0 u u WDT Wake-up PC + 2 u u u u 1 u 1 u u Interrupt Wake-up from PC + 2(1) u u u u u u 1 u u Sleep Clock Failure Trap 0x000004 u u u u u u u u u Trap Reset 0x000000 1 u u u u u u u u Illegal Operation Reset 0x000000 u 1 u u u u u u u Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70150E-page 160 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 21.4 Watchdog Timer (WDT) The processor wakes up from Sleep if at least one of the following conditions has occurred: 21.4.1 WATCHDOG TIMER OPERATION • any interrupt that is individually enabled and The primary function of the Watchdog Timer (WDT) is meets the required priority level to reset the processor in the event of a software • any Reset (POR, BOR and MCLR) malfunction. The WDT is a free running timer, which • WDT time-out runs off an on-chip RC oscillator, requiring no external On waking up from Sleep mode, the processor will component. Therefore, the WDT timer will continue to restart the same clock that was active prior to entry operate even if the main processor clock (e.g., the into Sleep mode. When clock switching is enabled, crystal oscillator) fails. bits COSC<2:0> will determine the oscillator source that will be used on wake-up. If clock switch is 21.4.2 ENABLING AND DISABLING THE disabled, then there is only one system clock. WDT Note: If a POR or BOR occurred, the selection of The Watchdog Timer can be “Enabled” or “Disabled” the oscillator is based on the FOS<2:0> only through a Configuration bit (FWDTEN) in the and FPR<4:0> Configuration bits. Configuration register FWDT. If the clock source is an oscillator, the clock to the Setting FWDTEN = 1 enables the Watchdog Timer. device is held off until OST times out (indicating a The enabling is done when programming the device. stable oscillator). If PLL is used, the system clock is By default, after chip-erase, FWDTEN bit = 1. Any held off until LOCK = 1 (indicating that the PLL is device programmer capable of programming dsPIC30F devices allows programming of this and stable). Either way, TPOR, TLOCK and TPWRT delays are applied. other Configuration bits. If EC, FRC, LPRC or ERC oscillators are used, then a If enabled, the WDT will increment until it overflows or “times out”. A WDT time-out will force a device Reset delay of TPOR (~ 10 μs) is applied. This is the smallest delay possible on wake-up from Sleep. (except during Sleep). To prevent a WDT time-out, the user must clear the Watchdog Timer using a CLRWDT Moreover, if LP oscillator was active during Sleep, and instruction. LP is the oscillator used on wake-up, then the start-up If a WDT times out during Sleep, the device will wake- delay will be equal to TPOR. PWRT delay and OST timer delay are not applied. In order to have the small- up. The WDTO bit in the RCON register will be cleared est possible start-up delay when waking up from Sleep, to indicate a wake-up resulting from a WDT time-out. one of these faster wake-up options should be selected Setting FWDTEN = 0 allows user software to enable/ before entering Sleep. disable the Watchdog Timer via the SWDTEN Any interrupt that is individually enabled (using the (RCON<5>) control bit. corresponding IE bit) and meets the prevailing priority 21.5 Power-Saving Modes level will be able to wake-up the processor. The proces- sor will process the interrupt and branch to the ISR. The There are two power-saving states that can be entered Sleep Status bit in RCON register is set upon wake-up. through the execution of a special instruction, PWRSAV. Note: In spite of various delays applied (TPOR, These are: Sleep and Idle. TLOCK and TPWRT), the crystal oscillator The format of the PWRSAV instruction is as follows: (and PLL) may not be active at the end of the time-out (e.g., for low-frequency crys- PWRSAV <parameter>, where ‘parameter’ defines tals). In such cases, if FSCM is enabled, Idle or Sleep mode. then the device will detect this as a clock 21.5.1 SLEEP MODE failure and process the clock failure trap, the FRC oscillator will be enabled, and the In Sleep mode, the clock to the CPU and peripherals is user will have to re-enable the crystal oscil- shut down. If an on-chip oscillator is being used, it is lator. If FSCM is not enabled, then the shut down. device will simply suspend execution of The Fail-Safe Clock Monitor is not functional during code until the clock is stable, and will Sleep, since there is no clock to monitor. However, remain in Sleep until the oscillator clock has LPRC clock remains active if WDT is operational during started. Sleep. All Resets will wake-up the processor from Sleep The Brown-out protection circuit, if enabled, will remain mode. Any Reset, other than POR, will set the Sleep functional during Sleep. Status bit. In a POR, the Sleep bit is cleared. If Watchdog Timer is enabled, then the processor will wake-up from Sleep mode upon WDT time-out. The Sleep and WDTO Status bits are both set. © 2011 Microchip Technology Inc. DS70150E-page 161

dsPIC30F6010A/6015 21.5.2 IDLE MODE 21.6 Device Configuration Registers In Idle mode, the clock to the CPU is shutdown while The Configuration bits in each device Configuration peripherals keep running. Unlike Sleep mode, the clock register specify some of the device modes and are source remains active. programmed by a device programmer, or by using the Several peripherals have a control bit in each module, In-Circuit Serial Programming™ (ICSP™) feature of the that allows them to operate during Idle. device. Each device Configuration register is a 24-bit register, but only the lower 16 bits of each register are LPRC fail-safe clock remains active if clock failure used to hold configuration data. There are seven device detect is enabled. Configuration registers available to the user: The processor wakes up from Idle if at least one of the 1. FOSC (0xF80000): Oscillator Configuration following conditions is true: register • on any interrupt that is individually enabled (IE bit 2. FWDT (0xF80002): Watchdog Timer is ‘1’) and meets the required priority level Configuration register • on any Reset (POR, BOR, MCLR) 3. FBORPOR (0xF80004): BOR and POR • on WDT time-out Configuration register Upon wake-up from Idle mode, the clock is re-applied 4. FBS (0xF80006): Boot Code Segment to the CPU and instruction execution begins immedi- Configuration register ately, starting with the instruction following the PWRSAV 5. FSS (0xF80008): Secure Code Segment instruction. Configuration register Any interrupt that is individually enabled (using IE bit) 6. FGS (0xF8000A): General Code Segment and meets the prevailing priority level will be able to Configuration register wake-up the processor. The processor will process the 7. FICD (0xF8000C): Debug Configuration interrupt and branch to the ISR. The Idle Status bit in register RCON register is set upon wake-up. The placement of the Configuration bits is automatically Any Reset, other than POR, will set the Idle Status bit. handled when you select the device in your device pro- On a POR, the Idle bit is cleared. grammer. The desired state of the Configuration bits may If Watchdog Timer is enabled, then the processor will be specified in the source code (dependent on the lan- wake-up from Idle mode upon WDT time-out. The Idle guage tool used), or through the programming interface. and WDTO Status bits are both set. After the device has been programmed, the application software may read the Configuration bit values through Unlike wake-up from Sleep, there are no time delays the table read instructions. For additional information, involved in wake-up from Idle. please refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157) and the “dsPIC30F Family Reference Manual” (DS70046). Note1: If the code protection Configuration Fuse bits (FBS(BSS<2:0>), FSS(SSS<2:0>), FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages VDD ≥ 4.5V. 2: This device supports an Advanced imple- mentation of CodeGuard™ Security. Please refer to the “CodeGuard Security” chapter (DS70180) for information on how CodeGuard Security may be used in your application. DS70150E-page 162 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 21.7 Peripheral Module Disable (PMD) 21.8 In-Circuit Debugger Registers When MPLAB® ICD 2 is selected as a debugger, the The Peripheral Module Disable (PMD) registers pro- In-Circuit Debugging functionality is enabled. This vide a method to disable a peripheral module by stop- function allows simple debugging functions when used ping all clock sources supplied to that module. When a with MPLAB IDE. When the device has this feature peripheral is disabled via the appropriate PMD control enabled, some of the resources are not available for bit, the peripheral is in a minimum power consumption general use. These resources include the first 80 bytes state. The control and STATUS registers associated of data RAM and two I/O pins. with the peripheral will also be disabled so writes to One of four pairs of debug I/O pins may be selected by those registers will have no effect and read values will the user using configuration options in MPLAB IDE. be invalid. These pin pairs are named EMUD/EMUC, EMUD1/ A peripheral module will only be enabled if both the EMUC1, EMUD2/EMUC2 and MUD3/EMUC3. associated bit in the PMD register is cleared and the In each case, the selected EMUD pin is the Emulation/ peripheral is supported by the specific dsPIC DSC vari- Debug Data line, and the EMUC pin is the Emulation/ ant. If the peripheral is present in the device, it is Debug Clock line. These pins will interface to the enabled in the PMD register by default. MPLAB ICD 2 module available from Microchip. The selected pair of debug I/O pins is used by MPLAB Note: If a PMD bit is set, the corresponding ICD2 to send commands and receive responses, as module is disabled after a delay of 1 well as to send and receive data. To use the In-Circuit instruction cycle. Similarly, if a PMD bit is Debugger function of the device, the design must cleared, the corresponding module is enabled after a delay of 1 instruction cycle implement ICSP connections to MCLR, VDD, VSS, PGC, PGD and the selected EMUDx/EMUCx pin pair. (assuming the module control registers are already configured to enable module This gives rise to two possibilities: operation). 1. If EMUD/EMUC is selected as the debug I/O pin pair, then only a 5-pin interface is required, as the EMUD and EMUC pin functions are multi- plexed with the PGD and PGC pin functions in all dsPIC30F devices. 2. If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/ EMUC3 is selected as the debug I/O pin pair, then a 7-pin interface is required, as the EMUDx/EMUCx pin functions (x = 1, 2 or 3) are not multiplexed with the PGD and PGC pin functions. © 2011 Microchip Technology Inc. DS70150E-page 163

D TABLE 21-7: SYSTEM INTEGRATION REGISTER MAP FOR dsPIC30F6010A DEVICES(1) d S 70 SFR s 1 Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 5 Name P 0 E -p RCON 0740 TRAPR IOPUWR BGST — — — — — EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Depends on type of Reset. I a C g OSCCON 0742 — COSC<2:0> — NOSC<2:0> POST<1:0> LOCK — CF — LPOSCEN OSWEN Depends on Configuration bits. e 1 OSCTUN 0744 — — — — — — — — — — TUN<5:0> 0000 0000 0000 0000 3 6 4 PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEIMD PWMMD — I2CMD U2MD U1MD SPI2MD SPI1MD C2MD C1MD ADCMD 0000 0000 0000 0000 0 PMD2 0772 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 0000 0000 0000 F Legend: — = unimplemented bit, read as ‘0’ 6 Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 0 TABLE 21-8: SYSTEM INTEGRATION REGISTER MAP FOR dsPIC30F6015 DEVICES(1) 1 0 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State A RCON 0740 TRAPR IOPUWR BGST — — — — — EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Depends on type of Reset. / 6 OSCCON 0742 — COSC<2:0> — NOSC<2:0> POST<1:0> LOCK — CF — LPOSCEN OSWEN Depends on Configuration bits. 0 OSCTUN 0744 — — — — — — — — — — TUN<5:0> 0000 0000 0000 0000 1 PMD1 0770 T5MD T4MD T3MD T2MD T1MD QEIMD PWMMD — I2CMD U2MD U1MD SPI2MD SPI1MD — C1MD ADCMD 0000 0000 0000 0000 5 PMD2 0772 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 0000 0000 0000 Legend: — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 21-9: DEVICE CONFIGURATION REGISTER MAP(1) Address Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0xF80000 FOSC FCKSM<1:0> — — — FOS<2:0> — — — FPR<4:0> 0xF80002 FWDT FWDTEN — — — — — — — — — FWPSA<1:0> FWPSB<3:0> 0xF80004 FBORPOR MCLREN — — — — PWMPIN HPOL LPOL BOREN — BORV<1:0> — — FPWRT<1:0> 0xF80006 FBS — — RBS<1:0> — — — EBS — — — — BSS<2:0> BWRP 0xF80008 FSS — — RSS<1:0> — — ESS<1:0> — — — — SSS<2:0> SWRP © 0xF8000A FGS — — — — — — — — — — — — — GSS<1:0> GWRP 2 0 0xF8000C FICD BKBUG COE — — — — — — — — — — — — ICS<1:0> 1 1 M Legend: — = unimplemented bit, read as ‘0’ ic Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. ro c h ip T e c h n o lo g y In c .

dsPIC30F6010A/6015 22.0 INSTRUCTION SET SUMMARY Most bit oriented instructions (including simple rotate/ shift instructions) have two operands: Note: This data sheet summarizes features of • The W register (with or without an address modi- this group ofdsPIC30F devices and is not fier) or file register (specified by the value of ‘Ws’ intended to be a complete reference or ‘f’) source. For more information on the CPU, • The bit in the W register or file register peripherals, register descriptions and (specified by a literal value, or indirectly by the general device functionality, refer to the contents of register ‘Wb’) “dsPIC30F Family Reference Manual” (DS70046). For more information on the The literal instructions that involve data movement may device instruction set and programming, use some of the following operands: refer to the “16-bit MCU and DSC • A literal value to be loaded into a W register or file Programmer’s Reference Manual” register (specified by the value of ‘k’) (DS70157). • The W register or file register where the literal The dsPIC30F instruction set adds many enhance- value is to be loaded (specified by ‘Wb’ or ‘f’) ments to the previous PIC® Microcontroller (MCU) However, literal instructions that involve arithmetic or instruction sets, while maintaining an easy migration logical operations use some of the following operands: from PIC MCU instruction sets. • The first source operand, which is a register ‘Wb’ Most instructions are a single program memory word without any address modifier (24-bits). Only three instructions require two program • The second source operand, which is a literal memory locations. value Each single-word instruction is a 24-bit word divided • The destination of the result (only if not the same into an 8-bit opcode which specifies the instruction as the first source operand), which is typically a type, and one or more operands which further specify register ‘Wd’ with or without an address modifier the operation of the instruction. The MAC class of DSP instructions may use some of the The instruction set is highly orthogonal and is grouped following operands: into five basic categories: • The accumulator (A or B) to be used (required • Word or byte-oriented operations operand) • Bit-oriented operations • The W registers to be used as the two operands • Literal operations • The X and Y address space prefetch operations • DSP operations • The X and Y address space prefetch destinations • Control operations • The accumulator write-back destination Table22-1 shows the general symbols used in The other DSP instructions do not involve any describing the instructions. multiplication, and may include: The dsPIC30F instruction set summary in Table22-2 • The accumulator to be used (required) lists all the instructions along with the Status flags • The source or destination operand (designated as affected by each instruction. Wso or Wdo, respectively) with or without an Most word or byte-oriented W register instructions address modifier (including barrel shift instructions) have three • The amount of shift, specified by a W register ‘Wn’ operands: or a literal value • The first source operand, which is typically a The control instructions may use some of the following register ‘Wb’ without any address modifier operands: • The second source operand, which is typically a • A program memory address register ‘Ws’ with or without an address modifier • The mode of the table read and table write • The destination of the result, which is typically a instructions register ‘Wd’ with or without an address modifier All instructions are a single word, except for certain However, word or byte-oriented file register instructions double word instructions, which were made double have two operands: word instructions so that all the required information is • The file register specified by the value ‘f’ available in these 48 bits. In the second word, the • The destination, which could either be the file 8MSbs are ‘0’s. If this second word is executed as an register ‘f’ or the W0 register, which is denoted as instruction (by itself), it will execute as a NOP. ‘WREG’ © 2011 Microchip Technology Inc. DS70150E-page 165

dsPIC30F6010A/6015 Most single-word instructions are executed in a single three cycles if the skip is performed, depending on instruction cycle, unless a conditional test is true or the whether the instruction being skipped is a single-word program counter is changed as a result of the instruc- or two-word instruction. Moreover, double word moves tion. In these cases, the execution takes two instruction require two cycles. The double word instructions cycles with the additional instruction cycle(s) executed execute in two instruction cycles. as a NOP. Notable exceptions are the BRA (uncondi- Note: For more details on the instruction set, tional/computed branch), indirect CALL/GOTO, all table refer to the “16-bit MCU and DSC Pro- reads and writes and RETURN/RETFIE instructions, grammer’s Reference Manual” which are single-word instructions, but take two or (DS70157). three cycles. Certain instructions that involve skipping over the subsequent instruction, require either two or TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double Word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator Write-Back Destination Address register ∈ {W13, [W13]+ = 2} bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Zero Expr Absolute address, label or expression (resolved by the linker) f File register address ∈ {0x0000...0x1FFF} lit1 1-bit unsigned literal ∈ {0,1} lit4 4-bit unsigned literal ∈ {0...15} lit5 5-bit unsigned literal ∈ {0...31} lit8 8-bit unsigned literal ∈ {0...255} lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal ∈ {0...16384} lit16 16-bit unsigned literal ∈ {0...65535} lit23 23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’ None Field does not require an entry, may be blank OA, OB, SA, SB DSP Status bits: AccA Overflow, AccB Overflow, AccA Saturate, AccB Saturate PC Program Counter Slit10 10-bit signed literal ∈ {-512...511} Slit16 16-bit signed literal ∈ {-32768...32767} Slit6 6-bit signed literal ∈ {-16...16} DS70150E-page 166 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wb Base W register ∈ {W0..W15} Wd Destination W register ∈ {Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd]} Wdo Destination W register ∈ {Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb]} Wm,Wn Dividend, Divisor working register pair (direct addressing) Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈ {W4*W4,W5*W5,W6*W6,W7*W7} Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈ {W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7} Wn One of 16 working registers ∈ {W0..W15} Wnd One of 16 destination working registers ∈ {W0..W15} Wns One of 16 source working registers ∈ {W0..W15} WREG W0 (working register used in file register instructions) Ws Source W register ∈ {Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws]} Wso Source W register ∈ {Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb]} Wx X data space prefetch address register for DSP instructions ∈ {[W8]+ = 6, [W8]+ = 4, [W8]+ = 2, [W8], [W8]- = 6, [W8]- = 4, [W8]- = 2, [W9]+ = 6, [W9]+ = 4, [W9]+ = 2, [W9], [W9]- = 6, [W9]- = 4, [W9]- = 2, [W9+W12], none} Wxd X data space prefetch destination register for DSP instructions ∈ {W4..W7} Wy Y data space prefetch address register for DSP instructions ∈ {[W10]+ = 6, [W10]+ = 4, [W10]+ = 2, [W10], [W10]- = 6, [W10]- = 4, [W10]- = 2, [W11]+ = 6, [W11]+ = 4, [W11]+ = 2, [W11], [W11]- = 6, [W11]- = 4, [W11]- = 2, [W11+W12], none} Wyd Y data space prefetch destination register for DSP instructions ∈ {W4..W7} © 2011 Microchip Technology Inc. DS70150E-page 167

dsPIC30F6010A/6015 T A BLE 22-2: INSTRUCTION SET OVERVIEW Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic words cycles Affected # 1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB 2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z 3 AND AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z 4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z 5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None 6 BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if greater than or equal 1 1 (2) None BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None BRA GT,Expr Branch if greater than 1 1 (2) None BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None BRA LE,Expr Branch if less than or equal 1 1 (2) None BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None BRA LT,Expr Branch if less than 1 1 (2) None BRA LTU,Expr Branch if unsigned less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OA,Expr Branch if Accumulator A overflow 1 1 (2) None BRA OB,Expr Branch if Accumulator B overflow 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA SA,Expr Branch if Accumulator A saturated 1 1 (2) None BRA SB,Expr Branch if Accumulator B saturated 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None 7 BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None 8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None 9 BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None 10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3) DS70150E-page 168 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic words cycles Affected # 11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) 12 BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z 13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z 14 CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call indirect Subroutine 1 2 None 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB 16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep 17 COM COM f f = f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z 18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z 19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z 20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z (Wb – Ws – C) 21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1 None (2 or 3) 22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1 None (2 or 3) 23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1 None (2 or 3) 24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if ≠ 1 1 None (2 or 3) 25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C 26 DEC DEC f f = f –1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f –1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z 27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z 28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None 29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C, OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C, OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C, OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C, OV 30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C, OV 31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 None DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None © 2011 Microchip Technology Inc. DS70150E-page 169

dsPIC30F6010A/6015 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic words cycles Affected # 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indirect 1 2 None 39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z 41 IOR IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 43 LNK LNK #lit14 Link Frame Pointer 1 1 None 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z 45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd, Multiply and Accumulate 1 1 OA,OB,OAB, AWB SA,SB,SAB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB 46 MOV MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 None MOV f,WREG Move f to WREG 1 1 None MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 None MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None 47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store Accumulator 1 1 None 48 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd, Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, AWB SA,SB,SAB 51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None DS70150E-page 170 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic words cycles Affected # 52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f = f + 1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 53 NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None 54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None W(nd):W(nd+1) POP.S Pop Shadow Registers 1 1 All 55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns +1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None 56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep 57 RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None 58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None 59 RESET RESET Software device Reset 1 1 None 60 RETFIE RETFIE Return from interrupt 1 3 (2) None 61 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None 62 RETURN RETURN Return from Subroutine 1 3 (2) None 63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z 64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z 65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z 66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None 68 SE SE Ws,Wnd Wnd = sign extended Ws 1 1 C,N,Z 69 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None 70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB 71 SL SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z © 2011 Microchip Technology Inc. DS70150E-page 171

dsPIC30F6010A/6015 TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic words cycles Affected # 72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f – WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z 73 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn – lit10 - (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z 74 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 - Wb 1 1 C,DC,N,OV,Z 75 SUBBR SUBBR f f = WREG – f - (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z 76 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None SWAP Wn Wn = byte swap Wn 1 1 None 77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None 78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None 79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 81 ULNK ULNK Unlink Frame Pointer 1 1 None 82 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z 83 ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C,Z,N DS70150E-page 172 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 23.0 DEVELOPMENT SUPPORT 23.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® • Integrated Development Environment operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2011 Microchip Technology Inc. DS70150E-page 173

dsPIC30F6010A/6015 23.2 MPLAB C Compilers for Various 23.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 23.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 23.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 23.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS70150E-page 174 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 23.7 MPLAB SIM Software Simulator 23.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 23.10 PICkit 3 In-Circuit Debugger/ Programmer and 23.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2011 Microchip Technology Inc. DS70150E-page 175

dsPIC30F6010A/6015 23.11 PICkit 2 Development 23.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 23.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS70150E-page 176 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 24.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. For detailed information about the dsPIC30F architecture and core, refer to the “dsPIC30F Family Reference Manual” (DS70046). Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR) (Note 1).....................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V Voltage on MCLR with respect to VSS........................................................................................................0V to +13.25V Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin (Note 2)................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports (Note 2)....................................................................................................200 mA Note1: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. 2: Maximum allowable current is a function of device maximum power dissipation. See Table24-6. †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2011 Microchip Technology Inc. DS70150E-page 177

dsPIC30F6010A/6015 24.1 DC Characteristics TABLE 24-1: OPERATING MIPS VS. VOLTAGE FOR dsPIC30F6010A Max MIPS VDD Range Temp Range (in Volts) (in °C) dsPIC30F6010A-30I dsPIC30F6010A-20E 4.5-5.5 -40 to +85 30 — 4.5-5.5 -40 to +125 — 20 3.0-3.6 -40 to +85 20 — 3.0-3.6 -40 to +125 — 15 2.5-3.0 -40 to +85 10 — TABLE 24-2: OPERATING MIPS VS. VOLTAGE FOR dsPIC30F6015 Max MIPS VDD Range Temp Range (in Volts) (in °C) dsPIC30F6015-30I dsPIC30F6015-20E 4.5-5.5 -40 to +85 30 — 4.5-5.5 -40 to +125 — 20 3.0-3.6 -40 to +85 20 — 3.0-3.6 -40 to +125 — 15 2.5-3.0 -40 to +85 10 — TABLE 24-3: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit dsPIC30F6010A-30I/dsPIC30F6015-30I Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C dsPIC30F6010A-20E/dsPIC30F6015-20E Operating Junction Temperature Range TJ -40 — +150 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal chip power dissipation: PINT = VDD× ⎝⎛IDD–∑IOH⎠⎞ PD PINT + PI/O W I/O Pin Power Dissipation: PI/O= ∑({VDD–VOH}× IOH)+∑(VOL× IOL) θ Maximum Allowed Power Dissipation PDMAX (TJ – TA)/ JA W TABLE 24-4: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes θ Package Thermal Resistance, 80-pin TQFP (14x14x1mm) JA 36 — °C/W 1 θ Package Thermal Resistance, 80-pin TQFP (12x12x1mm) JA 39 — °C/W 1 θ Package Thermal Resistance, 64-pin TQFP (10x10x1mm) JA 39 — °C/W 1 θ Note 1: Junction to ambient thermal resistance, Theta-ja ( JA) numbers are achieved by package simulations. DS70150E-page 178 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 T ABLE 24-5: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Operating Voltage(2) DC10 VDD Supply Voltage 2.5 — 5.5 V Industrial temperature DC11 VDD Supply Voltage 3.0 — 5.5 V Extended temperature DC12 VDR RAM Data Retention Voltage(3) 1.75 — — V — DC16 VPOR VDD Start Voltage — VSS — V — to ensure internal Power-on Reset signal DC17 SVDD VDD Rise Rate 0.05 — — V/ms 0-5V in 0.1 sec to ensure internal 0-3V in 60 ms Power-on Reset signal Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which VDD can be lowered without losing RAM data. © 2011 Microchip Technology Inc. DS70150E-page 179

dsPIC30F6010A/6015 T ABLE 24-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Parameter Typical(1) Max Units Conditions No. Operating Current (IDD)(2) DC31a 9.5 15 mA 25°C DC31b 9.5 15 mA 85°C 3.3V DC31c 9.4 15 mA 125°C 0.128 MIPS DC31e 18 27 mA 25°C LPRC (512 kHz) DC31f 17 27 mA 85°C 5V DC31g 17 27 mA 125°C DC30a 15 23 mA 25°C DC30b 15 23 mA 85°C 3.3V DC30c 14 23 mA 125°C (1.8 MIPS) DC30e 30 45 mA 25°C FRC (7.37 MHz) DC30f 29 45 mA 85°C 5V DC30g 27 45 mA 125°C DC23a 40 50 mA 25°C DC23b 40 50 mA 85°C 3.3V DC23c 36 50 mA 125°C 4 MIPS DC23e 44 64 mA 25°C DC23f 43 64 mA 85°C 5V DC23g 43 64 mA 125°C DC24a 50 75 mA 25°C DC24b 51 75 mA 85°C 3.3V DC24c 51 75 mA 125°C 10 MIPS DC24e 85 125 mA 25°C DC24f 84 125 mA 85°C 5V DC24g 84 125 mA 125°C DC27a 89 115 mA 25°C 3.3V DC27b 89 115 mA 85°C DC27d 147 185 mA 25°C 20 MIPS DC27e 146 185 mA 85°C 5V DC27f 145 185 mA 125°C DC29a 206 255 mA 25°C 5V 30 MIPS DC29b 205 255 mA 85°C Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail-to-rail. All I/O pins are configured as Inputs and pulled to VDD. MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating. DS70150E-page 180 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 T ABLE 24-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Parameter Typical(1,2) Max Units Conditions No. Operating Current (IDD)(3) DC51a 9.0 14 mA 25°C DC51b 9.0 14 mA 85°C 3.3V DC51c 9.0 14 mA 125°C 0.128 MIPS DC51e 17 26 mA 25°C LPRC (512 kHz) DC51f 16 26 mA 85°C 5V DC51g 16 26 mA 125°C DC50a 11 18 mA 25°C DC50b 12 18 mA 85°C 3.3V DC50c 11 18 mA 125°C (1.8 MIPS) DC50e 25 38 mA 25°C FRC (7.37 MHz) DC50f 24 38 mA 85°C 5V DC50g 23 38 mA 125°C DC43a 19 30 mA 25°C DC43b 20 30 mA 85°C 3.3V DC43c 20 30 mA 125°C 4 MIPS DC43e 34 51 mA 25°C DC43f 33 51 mA 85°C 5V DC43g 33 51 mA 125°C DC44a 34 53 mA 25°C DC44b 35 53 mA 85°C 3.3V DC44c 35 53 mA 125°C 10 MIPS DC44e 59 89 mA 25°C DC44f 59 89 mA 85°C 5V DC44g 59 89 mA 125°C DC47a 59 70 mA 25°C 3.3V DC47b 60 70 mA 85°C DC47d 99 115 mA 25°C 20 MIPS DC47e 99 115 mA 85°C 5V DC47f 100 115 mA 125°C DC49a 138 155 mA 25°C 5V 30 MIPS DC49b 139 155 mA 85°C Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base IIDLE current is measured with Core off, Clock on and all modules turned off. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail-to-rail. All I/O pins are configured as Inputs and pulled to VDD. MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating. © 2011 Microchip Technology Inc. DS70150E-page 181

dsPIC30F6010A/6015 TABLE 24-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Parameter Typical(1) Max Units Conditions No. Power-Down Current (IPD)(2) DC60a 0.2 — μA 25°C DC60b 1.2 40 μA 85°C 3.3V DC60c 12 65 μA 125°C Base Power-Down Current(3) DC60e 0.4 — μA 25°C DC60f 1.7 55 μA 85°C 5V DC60g 15 90 μA 125°C DC61a 9 15 μA 25°C DC61b 9 15 μA 85°C 3.3V DC61c 9 15 μA 125°C Watchdog Timer Current: ΔIWDT(3) DC61e 18 30 μA 25°C DC61f 17 30 μA 85°C 5V DC61g 16 30 μA 125°C DC62a 4 10 μA 25°C DC62b 5 10 μA 85°C 3.3V DC62c 4 10 μA 125°C Timer1 w/32 kHz Crystal: ΔITI32(3) DC62e 4 15 μA 25°C DC62f 6 15 μA 85°C 5V DC62g 5 15 μA 125°C DC63a 29 52 μA 25°C 3.3V DC63b 32 52 μA 85°C DC63c 33 52 μA 125°C BOR On: ΔIBOR(3) DC63e 34 60 μA 25°C DC63f 39 60 μA 85°C 5V DC63g 38 60 μA 125°C Note 1: Data in the “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. BOR, WDT, etc. are all switched off. 3: The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. DS70150E-page 182 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VIL Input Low Voltage(2) DI10 I/O pins: with Schmitt Trigger buffer VSS — 0.2VDD V DI15 MCLR VSS — 0.2VDD V DI16 OSC1 (in XT, HS and LP modes) VSS — 0.2VDD V DI17 OSC1 (in RC mode)(3) VSS — 0.3VDD V DI18 SDA, SCL VSS — 0.3VDD V SMBus disabled DI19 SDA, SCL VSS — 0.8 V SMBus enabled VIH Input High Voltage(2) DI20 I/O pins: with Schmitt Trigger buffer 0.8VDD — VDD V DI25 MCLR 0.8VDD — VDD V DI26 OSC1 (in XT, HS and LP modes) 0.7VDD — VDD V DI27 OSC1 (in RC mode)(3) 0.9VDD — VDD V DI28 SDA, SCL 0.7VDD — VDD V SMBus disabled DI29 SDA, SCL 2.1 — VDD V SMBus enabled ICNPU CNXX Pull-up Current(2) DI30 50 250 400 μA VDD = 5V, VPIN = VSS IIL Input Leakage Current(2)(4)(5) DI50 I/O ports — 0.01 ±1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance DI51 Analog Input Pins — 0.50 — μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance DI55 MCLR — 0.05 ±5 μA VSS ≤ VPIN ≤ VDD DI56 OSC1 — 0.05 ±5 μA VSS ≤ VPIN ≤ VDD, XT, HS and LP Osc mode Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that the dsPIC30F device be driven with an external clock while in RC mode. 4: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2011 Microchip Technology Inc. DS70150E-page 183

dsPIC30F6010A/6015 TABLE 24-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VOL Output Low Voltage(2) DO10 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 5V — — 0.15 V IOL = 2.0 mA, VDD = 3V DO16 OSC2/CLKO — — 0.6 V IOL = 1.6 mA, VDD = 5V (RC or EC Osc mode) — — 0.72 V IOL = 2.0 mA, VDD = 3V VOH Output High Voltage(2) DO20 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 5V VDD – 0.2 — — V IOH = -2.0 mA, VDD = 3V DO26 OSC2/CLKO VDD – 0.7 — — V IOH = -1.3 mA, VDD = 5V (RC or EC Osc mode) VDD – 0.1 — — V IOH = -2.0 mA, VDD = 3V Capacitive Loading Specs on Output Pins(2) DO50 COSC2 OSC2/SOSC2 pin — — 15 pF In XTL, XT, HS and LP modes when external clock is used to drive OSC1. DO56 CIO All I/O pins and OSC2 — — 50 pF RC or EC Osc mode DO58 CB SCL, SDA — — 400 pF In I2C™ mode Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. FIGURE 24-1: BROWN-OUT RESET CHARACTERISTICS VDD (Device not in Brown-out Reset) BO15 BO10 (Device in Brown-out Reset) Reset (due to BOR) Power-up Time-out DS70150E-page 184 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 T ABLE 24-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. BO10 VBOR BOR Voltage(2) on BORV = 11(3) — — — V Not in operating VDD transition range high-to-low BORV = 10 2.6 — 2.71 V — BORV = 01 4.1 — 4.4 V — BORV = 00 4.58 — 4.73 V — BO15 VBHYS BOR Hysteresis — 5 — mV — Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: ‘11’ values not in usable operating range. TABLE 24-12: DC CHARACTERISTICS: PROGRAM AND EEPROM Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Data EEPROM Memory(2) D120 ED Byte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time 0.8 2 2.6 ms RTSP D123 TRETD Characteristic Retention 40 100 — Year Provided no other specifications are violated D124 IDEW IDD During Programming — 10 30 mA Row Erase Program FLASH Memory(2) D130 EP Cell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VEB VDD for Bulk Erase 4.5 — 5.5 V D133 VPEW VDD for Erase/Write 3.0 — 5.5 V D134 TPEW Erase/Write Cycle Time 0.8 2 2.6 ms RTSP D135 TRETD Characteristic Retention 40 100 — Year Provided no other specifica- tions are violated D137 IPEW IDD During Programming — 10 30 mA Row Erase D138 IEB IDD During Programming — 10 30 mA Bulk Erase Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2011 Microchip Technology Inc. DS70150E-page 185

dsPIC30F6010A/6015 24.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 24-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Operating voltage VDD range as described in Table24-1 and Table24-2. FIGURE 24-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS Legend: CL Pin RL = 464Ω CL = 50 pF for all pins except OSC2 VSS 5 pF for OSC2 output FIGURE 24-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS40 OS41 DS70150E-page 186 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 TABLE 24-14: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symb Characteristic Min Typ(1) Max Units Conditions No. ol OS10 FOSC External CLKN Frequency(2) DC — 40 MHz EC (External clocks allowed only 4 — 10 MHz EC with 4x PLL in EC mode) 4 — 10 MHz EC with 8x PLL 4 — 7.5(3) MHz EC with 16x PLL Oscillator Frequency(2) DC — 4 MHz RC 0.4 — 4 MHz XTL 4 — 10 MHz XT 4 — 10 MHz XT with 4x PLL 4 — 10 MHz XT with 8x PLL 4 — 7.5(3) MHz XT with 16x PLL 10 — 25 MHz HS 10 — 20(4) MHz HS/2 with 4x PLL 10 — 20(4) MHz HS/2 with 8x PLL 10 — 15(3) MHz HS/2 with 16x PLL 12(4) — 25 MHz HS/3 with 4x PLL 12(4) — 25 MHz HS/3 with 8x PLL 12(4) — 22.5(3) MHz HS/3 with 16x PLL — 32.768 — kHz LP OS20 TOSC TOSC = 1/FOSC — — — — See parameter OS10 for FOSC value OS25 TCY Instruction Cycle Time(2)(5) 33 — DC ns See Table24-16 OS30 TosL, External Clock(2) in (OSC1) .45 x TOSC — — ns EC TosH High or Low Time OS31 TosR, External Clock(2) in (OSC1) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(2)(6) — — — ns See parameter DO31 OS41 TckF CLKO Fall Time(2)(6) — — — ns See parameter DO32 Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: Limited by the PLL output frequency range. 4: Limited by the PLL input frequency range. 5: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. 6: Measurements are taken in EC or ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). © 2011 Microchip Technology Inc. DS70150E-page 187

dsPIC30F6010A/6015 TABLE 24-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5V) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. OS50 FPLLI PLL Input Frequency Range(2) 4 — 10 MHz EC with 4x PLL 4 — 10 MHz EC with 8x PLL 4 — 7.5(4) MHz EC with 16x PLL 4 — 10 MHz XT with 4x PLL 4 — 10 MHz XT with 8x PLL 4 — 7.5(4) MHz XT with 16x PLL 5(3) — 10 MHz HS/2 with 4x PLL 5(3) — 10 MHz HS/2 with 8x PLL 5(3) — 7.5(4) MHz HS/2 with 16x PLL 4 — 8.33(3) MHz HS/3 with 4x PLL 4 — 8.33(3) MHz HS/3 with 8x PLL 4 — 7.5(4) MHz HS/3 with 16x PLL OS51 FSYS On-Chip PLL Output(2) 16 — 120 MHz EC, XT, HS/2, HS/3 modes with PLL OS52 TLOC PLL Start-up Time (Lock Time) — 20 50 μs — Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Limited by oscillator frequency range. 4: Limited by device operating frequency range. TABLE 24-16: PLL JITTER Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Characteristic Min Typ(1) Max Units Conditions No. OS61 x4 PLL — 0.251 0.413 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V — 0.251 0.413 % -40°C ≤ TA ≤ +125°C VDD = 3.0 to 3.6V — 0.256 0.47 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V — 0.256 0.47 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V x8 PLL — 0.355 0.584 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V — 0.355 0.584 % -40°C ≤ TA ≤ +125°C VDD = 3.0 to 3.6V — 0.362 0.664 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V — 0.362 0.664 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V x16 PLL — 0.67 0.92 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V — 0.632 0.956 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V — 0.632 0.956 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V Note 1: These parameters are characterized but not tested in manufacturing. DS70150E-page 188 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 T ABLE 24-17: INTERNAL CLOCK TIMING EXAMPLES Clock Oscillator (MFHOzS)C(1 ) TCY (μsec)(2) wM/IoP PSL(3L) wM/PIPLSL( 3x)4 wM/PIPLSL( 3x)8 wM/PILPLS (x31)6 Mode 0.200 20.0 0.05 — — — 4 1.0 1.0 4.0 8.0 16.0 EC 10 0.4 2.5 10.0 20.0 — 25 0.16 6.25 — — — XT 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 — Note 1: Assumption: Oscillator Postscaler is divide by 1. 2: Instruction Execution Cycle Time: TCY = 1/MIPS. 3: Instruction Execution Frequency: MIPS = (FOSC * PLLx)/4 [since there are 4 Q clocks per instruction cycle]. © 2011 Microchip Technology Inc. DS70150E-page 189

dsPIC30F6010A/6015 T ABLE 24-18: AC CHARACTERISTICS: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. Internal FRC Accuracy @ FRC Freq. = 7.37 MHz(1) OS63 FRC — — ±2.00 % -40°C ≤ TA ≤ +85°C VDD = 3.0-5.5V — — ±5.00 % -40°C ≤ TA ≤ +125°C VDD = 3.0-5.5V Note 1: Frequency is calibrated to 7.37 MHz (±2%) at 25°C and 5V. TUN bits can be used to compensate for temperature drift. TABLE 24-19: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. OS65A -50 — +50 % VDD = 5.0V, ±10% OS65B LPRC @ Freq. = 512 kHz(1) -60 — +60 % VDD = 3.3V, ±10% OS65C -70 — +70 % VDD = 2.5V Note 1: Change of LPRC frequency as VDD changes. DS70150E-page 190 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 24-4: CLKOUT AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure24-2 for load conditions. TABLE 24-20: CLKOUT AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1)(2)(3) Min Typ(4) Max Units Conditions No. DO31 TIOR Port output rise time — 7 20 ns — DO32 TIOF Port output fall time — 7 20 ns — DI35 TINP INTx pin high or low time (output) 20 — — ns — DI40 TRBP CNx high or low time (input) 2 TCY — — — — Note 1: These parameters are asynchronous events not related to any internal clock edges. 2: Measurements are taken in RC mode and EC mode where CLKO output is 4 x TOSC. 3: These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2011 Microchip Technology Inc. DS70150E-page 191

dsPIC30F6010A/6015 FIGURE 24-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD SY12 MCLR Internal SY10 POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure24-2 for load conditions. DS70150E-page 192 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 T A B LE 24-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SY10 TmcL MCLR Pulse Width (low) 2 — — μs -40°C to +85°C SY11 TPWRT Power-up Timer Period 2 4 6 ms -40°C to +85°C, VDD = 8 16 24 5V 32 64 96 User programmable SY12 TPOR Power-on Reset Delay(4) 3 10 30 μs -40°C to +85°C SY13 TIOZ I/O High-impedance from MCLR — 0.8 1.0 μs — Low or Watchdog Timer Reset SY20 TWDT1 Watchdog Timer Time-out Period 0.6 2.0 3.4 ms VDD = 2.5V TWDT2 (No Prescaler) 0.8 2.0 3.2 ms VDD = 3.3V, ±10% TWDT3 1.0 2.0 3.0 ms VDD = 5V, ±10% SY25 TBOR Brown-out Reset Pulse Width(3) 100 — — μs VDD ≤ VBOR (D034) SY30 TOST Oscillator Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 900 μs -40°C to +85°C Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure24-1 and Table24-11 for BOR. 4: Characterized by design but not tested. FIGURE 24-6: BAND GAP START-UP TIME CHARACTERISTICS VBGAP 0V Enable Band Gap (see Note) Band Gap SY40 Stable Note: Set FBORPOR<7>. TABLE 24-22: BAND GAP START-UP TIME REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. SY40 TBGAP Band Gap Start-up Time — 40 65 μs Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable (RCON<13>Status bit). Note 1: These parameters are characterized but not tested in manufacturing. © 2011 Microchip Technology Inc. DS70150E-page 193

dsPIC30F6010A/6015 FIGURE 24-7: TIMER1, 2, 3, 4 AND 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRX Note: Refer to Figure24-2 for load conditions. TABLE 24-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TA10 TTXH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TA15 Synchronous, 10 — — ns with prescaler Asynchronous 10 — — ns TA11 TTXL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TA15 Synchronous, 10 — — ns with prescaler Asynchronous 10 — — ns TA15 TTXP TxCK Input Period Synchronous, TCY + 10 — — ns — no prescaler Synchronous, Greater of: — — — N = prescale with prescaler 20 ns or value (TCY + 40)/N (1, 8, 64, 256) Asynchronous 20 — — ns — OS60 Ft1 SOSC1/T1CK oscillator input DC — 50 kHz — frequency range (oscillator enabled by setting bit TCS (T1CON, bit 1)) TA20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — — Edge to Timer Increment Note: Timer1 is a Type A. DS70150E-page 194 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 T ABLE 24-24: TIMER2 AND TIMER4 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TB10 TtxH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TB15 Synchronous, 10 — — ns with prescaler TB11 TtxL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TB15 Synchronous, 10 — — ns with prescaler TB15 TtxP TxCK Input Period Synchronous, TCY + 10 — — ns N = prescale no prescaler value Synchronous, Greater of: (1, 8, 64, 256) with prescaler 20 ns or (TCY + 40)/N TB20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — — Edge to Timer Increment TABLE 24-25: TIMER3 AND TIMER5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet parameter TC15 TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet parameter TC15 TC15 TtxP TxCK Input Period Synchronous, TCY + 10 — — ns N = prescale no prescaler value Synchronous, Greater of: (1, 8, 64, 256) with prescaler 20 ns or (TCY + 40)/N TC20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 — — Edge to Timer Increment TCY © 2011 Microchip Technology Inc. DS70150E-page 195

dsPIC30F6010A/6015 FIGURE 24-8: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEB TQ10 TQ11 TQ15 TQ20 POSCNT TABLE 24-26: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. TQ10 TtQH TQCK High Time Synchronous, TCY + 20 — — ns Must also meet with prescaler parameter TQ15 TQ11 TtQL TQCK Low Time Synchronous, TCY + 20 — — ns Must also meet with prescaler parameter TQ15 TQ15 TtQP TQCP Input Synchronous, 2 * TCY + 40 — — ns — Period with prescaler TQ20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — — Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing. DS70150E-page 196 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 24-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICX IC10 IC11 IC15 Note: Refer to Figure24-2 for load conditions. TABLE 24-27: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Max Units Conditions No. IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns — With Prescaler 10 — ns IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns — With Prescaler 10 — ns IC15 TccP ICx Input Period (2 TCY + 40)/N — ns N = prescale value (1, 4, 16) Note 1: These parameters are characterized but not tested in manufacturing. FIGURE 24-10: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure24-2 for load conditions. TABLE 24-28: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. OC10 TccF OCx Output Fall Time — — — ns See parameter DO32 OC11 TccR OCx Output Rise Time — — — ns See parameter DO31 Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2011 Microchip Technology Inc. DS70150E-page 197

dsPIC30F6010A/6015 FIGURE 24-11: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 24-29: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. OC15 TFD Fault Input to PWM I/O — — 50 ns — Change OC20 TFLT Fault Input Pulse Width 50 — — ns — Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70150E-page 198 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 24-12: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTA/B MP20 PWMx FIGURE 24-13: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure24-2 for load conditions. TABLE 24-30: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. MP10 TFPWM PWM Output Fall Time — — — ns See parameter DO32 MP11 TRPWM PWM Output Rise Time — — — ns See parameter DO31 TFD Fault Input ↓ to PWM — — 50 ns — MP20 I/O Change MP30 TFH Minimum Pulse Width 50 — — ns — Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2011 Microchip Technology Inc. DS70150E-page 199

dsPIC30F6010A/6015 FIGURE 24-14: QEA/QEB INPUT CHARACTERISTICS TQ36 QEA (input) TQ31 TQ30 TQ35 QEB (input) TQ41 TQ40 TQ31 TQ30 TQ35 QEB Internal TABLE 24-31: QUADRATURE DECODER TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Typ(2) Max Units Conditions No. TQ30 TQUL Quadrature Input Low Time 6 TCY — ns — TQ31 TQUH Quadrature Input High Time 6 TCY — ns — TQ35 TQUIN Quadrature Input Period 12 TCY — ns — TQ36 TQUP Quadrature Phase Period 3 TCY — ns — TQ40 TQUFL Filter Time to Recognize Low, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) TQ41 TQUFH Filter Time to Recognize High, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) Note 1: These parameters are characterized but not tested in manufacturing. 2: N = Index Channel Digital Filter Clock Divide Select Bits. Refer to Section 16. “Quadrature Encoder Interface (QEI)” (DS70046) in the “dsPIC30F Family Reference Manual” . DS70150E-page 200 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 24-15: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ50 TQ51 Index Internal TQ55 Position Coun- TABLE 24-32: QEI INDEX PULSE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Max Units Conditions No. TQ50 TqIL Filter Time to Recognize Low, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) TQ51 TqiH Filter Time to Recognize High, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) TQ55 Tqidxr Index Pulse Recognized to Position 3 TCY — ns — Counter Reset (Ungated Index) Note 1: These parameters are characterized but not tested in manufacturing. 2: Alignment of index pulses to QEA and QEB is shown for position counter reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but index pulse recognition occurs on falling edge. © 2011 Microchip Technology Inc. DS70150E-page 201

dsPIC30F6010A/6015 FIGURE 24-16: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb BIT14 - - - - - -1 LSb SP31 SP30 SDIx MSb IN BIT14 - - - -1 LSb IN SP40 SP41 Note: Refer to Figure24-2 for load conditions. TABLE 24-33: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscL SCKX Output Low Time(3) TCY/2 — — ns — SP11 TscH SCKX Output High Time(3) TCY/2 — — ns — SP20 TscF SCKX Output Fall Time(4) — — — ns See parameter DO32 SP21 TscR SCKX Output Rise Time(4) — — — ns See parameter DO31 SP30 TdoF SDOX Data Output Fall Time(4) — — — ns See parameter DO32 SP31 TdoR SDOX Data Output Rise Time(4) — — — ns See parameter DO31 SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns — TscL2doV SCKX Edge SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns — TdiV2scL to SCKX Edge SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns — TscL2diL to SCKX Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. DS70150E-page 202 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 24-17: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SCKX (CKP = 1) SP35 SP20 SP21 SDOX MSb BIT14 - - - - - -1 LSb SP40 SP30,SP31 SDIX MSb IN BIT14 - - - -1 LSb IN SP41 Note: Refer to Figure24-2 for load conditions. TABLE 24-34: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscL SCKX output low time(3) TCY/2 — — ns — SP11 TscH SCKX output high time(3) TCY/2 — — ns — SP20 TscF SCKX output fall time(4) — — — ns See parameter DO32 SP21 TscR SCKX output rise time(4) — — — ns See parameter DO31 SP30 TdoF SDOX data output fall time(4) — — — ns See parameter DO32 SP31 TdoR SDOX data output rise time(4) — — — ns See parameter DO31 SP35 TscH2doV, SDOX data output valid after — — — ns — TscL2doV SCKX edge SP36 TdoV2sc, SDOX data output setup to 30 — — ns — TdoV2scL first SCKX edge SP40 TdiV2scH, Setup time of SDIX data input 20 — — ns — TdiV2scL to SCKX edge SP41 TscH2diL, Hold time of SDIX data input 20 — — ns — TscL2diL to SCKX edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2011 Microchip Technology Inc. DS70150E-page 203

dsPIC30F6010A/6015 FIGURE 24-18: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOX MSb BIT14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIX MSb IN BIT14 - - - -1 LSb IN SP41 SP40 Note: Refer to Figure24-2 for load conditions. TABLE 24-35: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscL SCKX Input Low Time 30 — — ns — SP71 TscH SCKX Input High Time 30 — — ns — SP72 TscF SCKX Input Fall Time(3) — 10 25 ns — SP73 TscR SCKX Input Rise Time(3) — 10 25 ns — SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parameter DO32 SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parameter DO31 SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns — TscL2doV SCKX Edge SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns — TdiV2scL to SCKX Edge SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns — TscL2diL to SCKX Edge SP50 TssL2scH, SSX↓ to SCKX↑ or SCKX↓ Input 120 — — ns — TssL2scL SP51 TssH2doZ SSX↑ to SDOX Output 10 — 50 ns — High-impedance(3) SP52 TscH2ssH SSX after SCK Edge 1.5 TCY +40 — — ns — TscL2ssH Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. DS70150E-page 204 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 24-19: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SCKX (CKP = 1) SP35 SP72 SP73 SP52 SDOX MSb BIT14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIX MSb IN BIT14 - - - -1 LSb IN SP41 SP40 Note: Refer to Figure24-2 for load conditions. © 2011 Microchip Technology Inc. DS70150E-page 205

dsPIC30F6010A/6015 TABLE 24-36: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscL SCKX Input Low Time 30 — — ns — SP71 TscH SCKX Input High Time 30 — — ns — SP72 TscF SCKX Input Fall Time(3) — 10 25 ns — SP73 TscR SCKX Input Rise Time(3) — 10 25 ns — SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parameter DO32 SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parameter DO31 SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns — TscL2doV SCKX Edge SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns — TdiV2scL to SCKX Edge SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns — TscL2diL to SCKX Edge SP50 TssL2scH, SSX↓ to SCKX↓ or SCKX↑ input 120 — — ns — TssL2scL SP51 TssH2doZ SS↑ to SDOX Output 10 — 50 ns — High-impedance(4) SP52 TscH2ssH SSX↑ after SCKX Edge 1.5 TCY + — — ns — TscL2ssH 40 SP60 TssL2doV SDOX Data Output Valid after — — 50 ns — SSX Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. DS70150E-page 206 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 24-20: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM34 IM30 IM33 SDA Start Stop Condition Condition Note: Refer to Figure24-2 for load conditions. FIGURE 24-21: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM21 IM10 SCL IM11 IM26 IM10 IM25 IM33 SDA In IM40 IM40 IM45 SDA Out Note: Refer to Figure24-2 for load conditions. © 2011 Microchip Technology Inc. DS70150E-page 207

dsPIC30F6010A/6015 T ABLE 24-37: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min(1) Max Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — μs — 400 kHz mode TCY/2 (BRG + 1) — μs — 1 MHz mode(2) TCY/2 (BRG + 1) — μs — IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — μs — 400 kHz mode TCY/2 (BRG + 1) — μs — 1 MHz mode(2) TCY/2 (BRG + 1) — μs — IM20 TF:SCL SDA and SCL 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 100 ns IM21 TR:SCL SDA and SCL 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns — 1 MHz mode(2) — — ns IM26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 μs — 1 MHz mode(2) — — ns IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — μs Only relevant for Setup Time 400 kHz mode TCY/2 (BRG + 1) — μs Repeated Start condition 1 MHz mode(2) TCY/2 (BRG + 1) — μs IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — μs After this period the Hold Time 400 kHz mode TCY/2 (BRG + 1) — μs first clock pulse is generated 1 MHz mode(2) TCY/2 (BRG + 1) — μs IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — μs Setup Time 400 kHz mode TCY/2 (BRG + 1) — μs — 1 MHz mode(2) TCY/2 (BRG + 1) — μs IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns — 1 MHz mode(2) TCY/2 (BRG + 1) — ns IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns — From Clock 400 kHz mode — 1000 ns — 1 MHz mode(2) — — ns — IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be 400 kHz mode 1.3 — μs free before a new transmission can start 1 MHz mode(2) — — μs IM50 CB Bus Capacitive Loading — 400 pF — Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit (I2C™)” (DS70046) in the “dsPIC30F Family Reference Manual”. 2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only). DS70150E-page 208 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 24-22: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS31 IS34 IS30 IS33 SDA Start Stop Condition Condition FIGURE 24-23: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS10 SCL IS30 IS26 IS31 IS25 IS33 SDA In IS40 IS40 IS45 SDA Out © 2011 Microchip Technology Inc. DS70150E-page 209

dsPIC30F6010A/6015 T ABLE 24-38: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Max Units Conditions No. IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — µs — IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — µs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — µs Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — µs — IS20 TF:SCL SDA and SCL 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns — 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 μs — 1 MHz mode(1) 0 0.3 μs IS30 TSU:STA Start Condition 100 kHz mode 4.7 — μs Only relevant for Repeated Setup Time 400 kHz mode 0.6 — μs Start condition 1 MHz mode(1) 0.25 — μs IS31 THD:STA Start Condition 100 kHz mode 4.0 — μs After this period, the first Hold Time 400 kHz mode 0.6 — μs clock pulse is generated 1 MHz mode(1) 0.25 — μs IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — μs Setup Time 400 kHz mode 0.6 — μs — 1 MHz mode(1) 0.6 — μs IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — ns — 1 MHz mode(1) 250 ns IS40 TAA:SCL Output Valid from 100 kHz mode 0 3500 ns Clock 400 kHz mode 0 1000 ns — 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode 1.3 — μs before a new transmission 1 MHz mode(1) 0.5 — μs can start IS50 CB Bus Capacitive Loading — 400 pF — Note 1: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only). DS70150E-page 210 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 24-24: CAN MODULE I/O TIMING CHARACTERISTICS CXTX Pin Old Value New Value (output) CA10 CA11 CXRX Pin (input) CA20 TABLE 24-39: CAN MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. CA10 TioF Port Output Fall Time — — — ns See parameter DO32 CA11 TioR Port Output Rise Time — — — ns See parameter DO31 CA20 Tcwf Pulse Width to Trigger 500 — — ns — CAN Wake-up Filter Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2011 Microchip Technology Inc. DS70150E-page 211

dsPIC30F6010A/6015 TABLE 24-40: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS(1) Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of — Lesser of V — VDD – 0.3 VDD + 0.3 or 2.7 or 5.5 AD02 AVSS Module VSS Supply Vss - 0.3 — VSS + 0.3 V — Reference Inputs AD05 VREFH Reference Voltage High AVss + 2.7 — AVDD V — AD06 VREFL Reference Voltage Low AVss — AVDD – 2.7 V — AD07 VREF Absolute Reference Voltage AVss – 0.3 — AVDD + 0.3 V — AD08 IREF Current Drain — 200 300 μA A/D operating .001 3 μA A/D off Analog Input AD10 VINH-VINL Full-Scale Input Span VREFL VREFH V — AD11 Vin Absolute Input Voltage AVSS - 0.3 — AVDD + 0.3 V — AD12 — Leakage Current — ±0.001 ±0.244 μA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V Source Impedance = 5kΩ AD13 — Leakage Current — ±0.001 ±0.244 μA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Source Impedance = 5kΩ AD17 RIN Recommended Impedance — — — Ω See Table20-2 of Analog Voltage Source DC Accuracy AD20 Nr Resolution 10 data bits bits — AD21 INL Integral Nonlinearity(2) — ±1 ±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD21A INL Integral Nonlinearity(2) — ±1 ±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD22 DNL Differential Nonlinearity(2) — ±1 ±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD22A DNL Differential Nonlinearity(2) — ±1 ±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD23 GERR Gain Error(2) +1 ±5 ±6 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD23A GERR Gain Error(2) +1 ±5 ±6 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Note 1: These parameters are characterized but not tested in manufacturing. 2: Measurements taken with external VREF+ and VREF- used as the ADC voltage references. 3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. DS70150E-page 212 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 TABLE 24-40: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS(1) (CONTINUED) Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. AD24 EOFF Offset Error(2) ±1 ±2 ±3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD24A EOFF Offset Error(2) ±1 ±2 ±3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD25 — Monotonicity(3) — — — — Guaranteed Dynamic Performance AD30 THD Total Harmonic Distortion — -64 -67 dB — AD31 SINAD Signal to Noise and — 57 58 dB — Distortion AD32 SFDR Spurious Free Dynamic — 67 71 dB — Range AD33 FNYQ Input Signal Bandwidth — — 500 kHz — AD34 ENOB Effective Number of Bits 9.29 9.41 — bits — Note 1: These parameters are characterized but not tested in manufacturing. 2: Measurements taken with external VREF+ and VREF- used as the ADC voltage references. 3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. © 2011 Microchip Technology Inc. DS70150E-page 213

dsPIC30F6010A/6015 FIGURE 24-25: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) AD50 ADCLK Instruction ExecutionSET SAMP CLEAR SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 TSAMP AD55 AD55 DONE ADIF ADRES(0) ADRES(1) 1 2 3 4 5 6 8 9 5 6 8 9 1 - Software sets ADCON. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in Section 17. “10-bit A/D Converter” (DS70046) of the “dsPIC30F Family Reference Manual”. 3 - Software clears ADCON. SAMP to start conversion. 4 - Sampling ends, conversion sequence starts. 5 - Convert bit 9. 6 - Convert bit 8. 8 - Convert bit 0. 9 - One TAD for end of conversion. DS70150E-page 214 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 FIGURE 24-26: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS (CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001) AD50 ADCLK Instruction Execution SET ADON SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc TSAMP TSAMP AD55 AD55 TCONV DONE ADIF ADRES(0) ADRES(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 - Software sets ADCON. ADON to start AD operation. 5 - Convert bit 0. 2 - Sampling starts after discharge period. 6 - One TAD for end of conversion. TSAMP is described in Section 17. “10-bit A/D Converter” (DS70046) of the “dsPIC30F Family Reference Manual”. 7 - Begin conversion of next channel. 3 - Convert bit 9. 8 - Sample for time specified by SAMC. TSAMP is described in Section 17. “10-bit A/D Converter” 4 - Convert bit 8. (DS70046) of the “dsPIC30F Family Reference Manual”. © 2011 Microchip Technology Inc. DS70150E-page 215

dsPIC30F6010A/6015 T ABLE 24-41: 10-BIT HIGH-SPEED A/D CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min. Typ(1) Max. Units Conditions No. Clock Parameters AD50 TAD A/D Clock Period — 84 — ns See Table20-2(2) AD51 tRC A/D Internal RC Oscillator Period 700 900 1100 ns — Conversion Rate AD55 tCONV Conversion Time — 12 TAD — — — AD56 FCNV Throughput Rate — 1.0 — Msps See Table20-2(2) AD57 TSAMP Sample Time — 1 TAD — — See Table20-2(2) Timing Parameters AD60 tPCS Conversion Start from Sample — 1.0 TAD — — Auto-Convert Trigger Trigger(3) (SSRC = 111) not selected AD61 tPSS Sample Start from Setting 0.5 TAD — 1.5 TAD — — Sample (SAMP) Bit AD62 tCSS Conversion Completion to — 0.5 TAD — — — Sample Start (ASAM = 1)(3) AD63 tDPU(4) Time to Stabilize Analog Stage — — 20 μs — from A/D Off to A/D On(3) Note 1: These parameters are characterized but not tested in manufacturing. 2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 3: Characterized by design but not tested. 4: tDPU is the time required for the ADC module to stabilize when it is turned on (ADCON1<ADON> = 1). During this time the ADC result is indeterminate. DS70150E-page 216 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 25.0 PACKAGING INFORMATION 25.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXXXX dsPIC30F6015 XXXXXXXXXXXX -30I/PTe3 YYWWNNN 0712XXX 80-Lead TQFP Example XXXXXXXXXXXX dsPIC30F6010 XXXXXXXXXXXX A-30I/PTe3 YYWWNNN 0712XXX Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011 Microchip Technology Inc. DS70150E-page 217

dsPIC30F6010A/6015 64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 123 NOTE 2 α A c φ A2 β A1 L L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 64 Lead Pitch e 0.50 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.17 0.22 0.27 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-085B DS70150E-page 218 © 2011 Microchip Technology Inc.

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dsPIC30F6010A/6015 80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 b N NOTE 1 123 NOTE 2 α A c φ β A1 A2 L L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 80 Lead Pitch e 0.50 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 14.00 BSC Overall Length D 14.00 BSC Molded Package Width E1 12.00 BSC Molded Package Length D1 12.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.17 0.22 0.27 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-092B DS70150E-page 220 © 2011 Microchip Technology Inc.

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dsPIC30F6010A/6015 80-Lead Plastic Thin Quad Flatpack (PF) – 14x14x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e E E1 b N NOTE 1 123 α NOTE 2 c φ A β L A1 L1 A2 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 80 Lead Pitch e 0.65 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 16.00 BSC Overall Length D 16.00 BSC Molded Package Width E1 14.00 BSC Molded Package Length D1 14.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.22 0.32 0.38 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-116B DS70150E-page 222 © 2011 Microchip Technology Inc.

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dsPIC30F6010A/6015 NOTES: DS70150E-page 224 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 APPENDIX A: REVISION HISTORY Revision D (March 2008) This revision reflects these updates: Revision A (July 2005) • Changed the location of the input reference in the Original data sheet for dsPIC30F6010A/6015 devices. 10-bit High-Speed ADC Functional Block Diagram (see Figure20-1) Revision B (September 2006) • Added FUSE Configuration Register (FICD) details (see Section21.6 “Device Configuration This revision reflects updates in these areas: Registers” and Table21-8) • Data Ram protection feature enables segments of • Removed erroneous statement regarding genera- RAM to be protected when used in conjunction tion of CAN receive errors (see Section19.4.5 with Boot and Secure Code Segment Security “Receive Errors”) (see Section3.2.7 “Data Ram Protection Fea- • Electrical Specifications: ture”) - Resolved TBD values for parameters DO10, • BSRAM and SSRAM SFRs added to support DO16, DO20, and DO26 (see Table24-10) Data Ram Protection (see Table3-3) - 10-bit High-Speed ADC tPDU timing parame- • Base Instruction CP1 removed (see Table22-2) ter (time to stabilize) has been updated from • Supported I2C Slave addresses (see Table17-2) 20 µs typical to 20 µs maximum (see • Revised Electrical Characteristics: Table24-41) - Operating current (IDD) specifications (see - Parameter OS65 (Internal RC Accuracy) has Table24-6) been expanded to reflect multiple Min and - Idle current (IIDLE) specifications (see Max values for different temperatures (see Table24-7) Table24-19) - Power-down current (IPD) specifications (see - Parameter DC12 (RAM Data Retention Volt- Table24-8) age) Min and Max values have been updated (see Table24-5) - I/O Pin input specifications (see Table24-9) - Parameter D134 (Erase/Write Cycle Time) - BOR voltage limits (see Table24-11) has been updated to include Min and Max - Watchdog Timer time-out limits (see values and the Typ value has been removed Table24-21) (see Table24-12) • Added note to package drawings. - Removed parameters OS62 (Internal FRC Jitter) and OS64 (Internal FRC Drift) and Revision C (January 2007) Note 2 from AC Characteristics (see Table24-18) This revision includes updates to the packaging diagrams. - Parameter OS63 (Internal FRC Accuracy) has been expanded to reflect multiple Min and Max values for different temperatures (see Table24-18) - Updated Min and Max values and Conditions for parameter SY11 and updated Min, Typ, and Max values and Conditions for parame- ter SY20 (see Table24-21) • Additional minor corrections throughout the document © 2011 Microchip Technology Inc. DS70150E-page 225

dsPIC30F6010A/6015 Revision E (March 2011) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in TableA-1. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description Section15.0 “Motor Control Updated the PWM Period equations (see Equation15-1 and Equation15-2). PWM Module” Section21.0 “System Added a shaded note on OSCTUN functionality in Section21.2.5 “Fast RC Integration” Oscillator (FRC)”. Section24.0 “Electrical Updated the maximum value for parameter DI19 and the minimum value for Characteristics” parameter DI29 in the I/O Pin Input Specifications (see Table24-9). Removed parameter D136 and updated the minimum, typical, maximum, and conditions for parameters D122 and D134 in the Program and EEPROM specifications (see Table24-12). Updated Note 1 in the Internal FRC Accuracy specifications (see Table24-18). Added parameter AD11 to the 10-bit High-Speed A/D Module Specifications (see Table24-40). DS70150E-page 226 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 INDEX A Oscillator System .....................................................154 Output Compare Mode ..............................................85 A/D PWM Module .............................................................98 Aborting a Conversion .............................................143 Quadrature Encoder Interface ...................................91 Acquisition Requirements ........................................147 Reset System ..........................................................158 ADCHS ....................................................................140 Shared Port Structure ................................................60 ADCON1 ..................................................................140 SPI ...........................................................................109 ADCON2 ..................................................................140 SPI Master/Slave Connection ..................................109 ADCON3 ..................................................................140 UART Receiver ........................................................121 ADCSSL ...................................................................140 UART Transmitter ....................................................120 ADPCFG ..................................................................140 10-bit High-Speed A/D Functional ...........................141 Configuring Analog Port Pins ...................................149 16-bit Timer1 Module (Type A Timer) ........................65 Connection Considerations ......................................149 16-bit Timer2 (Type B Timer) for dsPIC30F6010A ....72 Conversion Operation ..............................................142 16-bit Timer2 (Type B Timer) for dsPIC30F6015 ......72 Conversion Rate Parameters ...................................144 16-bit Timer3 (Type C Timer) ....................................73 Conversion Speeds ..................................................144 16-bit Timer4 (Type B Timer) ....................................78 Effects of a Reset .....................................................148 16-bit Timer5 (Type C Timer) ....................................78 Operation During CPU Idle Mode ............................148 32-bit Timer2/3 for dsPIC30F6010A ..........................70 Operation During CPU Sleep Mode .........................148 32-bit Timer2/3 for dsPIC30F6015 ............................71 Output Formats ........................................................148 32-bit Timer4/5 ..........................................................77 Power-Down Modes .................................................148 BOR. See Brown-out Reset. Programming the Start of Conversion Trigger .........143 Brown-out Reset (BOR) ...................................................152 Register Map ............................................................150 Result Buffer ............................................................142 C Selecting the Conversion Clock ...............................143 C Compilers Selecting the Conversion Sequence ........................142 MPLAB C18 .............................................................176 Voltage Reference Schematic .................................145 CAN 1 Msps Configuration Guideline ...............................145 Baud Rate Setting ...................................................133 10-bit High-Speed Analog-to-Digital Bit Timing .........................................................133 Converter Module ............................................140 Phase Segments .............................................134 600 ksps Configuration Guideline ............................146 Prescaler .........................................................134 750 ksps Configuration Guideline ............................146 Propagation Segment ......................................134 AC Characteristics ...........................................................188 Sample Point ...................................................134 Internal FRC Jitter, Accuracy and Drift ....................192 Synchronization ...............................................134 Internal LPRC Accuracy ...........................................192 CAN1 Register Map for dsPIC30F6010A/6015 .......135 Load Conditions .......................................................188 CAN2 Register Map for dsPIC30F6010A ................137 Temperature and Voltage Specifications .................188 Frame Types ...........................................................128 Address Generator Units ...................................................35 Message Reception .................................................131 Alternate Vector Table .......................................................45 Acceptance Filter Masks .................................131 Alternate 16-bit Timer/Counter ...........................................93 Acceptance Filters ...........................................131 Assembler Receive Buffers ...............................................131 MPASM Assembler ..................................................176 Receive Errors .................................................131 Automatic Clock Stretch ...................................................115 Receive Interrupts ...........................................131 During 10-bit Addressing (STREN = 1) ....................115 Receive Overrun ..............................................131 During 7-bit Addressing (STREN = 1) ......................115 Message Transmission ............................................132 Receive Mode ..........................................................115 Aborting ...........................................................132 Transmit Mode .........................................................115 Errors ...............................................................132 B Priority .............................................................132 Sequence ........................................................132 Barrel Shifter ......................................................................22 Transmit Buffers ..............................................132 Bit-Reversed Addressing ...................................................38 Transmit Interrupts ..........................................133 Example .....................................................................38 Operation Modes .....................................................130 Implementation ..........................................................38 Disable ............................................................130 Modifier Values (table) ...............................................39 Error Recognition .............................................130 Sequence Table (16-Entry) ........................................39 Initialization ......................................................130 Block Diagrams Listen-Only ......................................................130 CAN Buffers and Protocol Engine ............................129 Loopback .........................................................130 Dedicated Port Structure ............................................59 Normal .............................................................130 DSP Engine ...............................................................19 Overview ..................................................................128 dsPIC30F6010A .........................................................10 CAN Module ....................................................................128 dsPIC30F6015 ...........................................................11 Center-Aligned PWM .......................................................101 External Power-on Reset Circuit ..............................160 Code Examples Input Capture Mode ...................................................81 I2C ............................................................................113 Data EEPROM Block Erase ......................................56 Data EEPROM Block Write .......................................58 © 2011 Microchip Technology Inc. DS70150E-page 227

dsPIC30F6010A/6015 Data EEPROM Read .................................................55 FGS .........................................................................163 Data EEPROM Word Erase .......................................56 FOSC .......................................................................163 Data EEPROM Word Write ........................................57 FWDT ......................................................................163 Erasing a Row of Program Memory ...........................51 Device Overview ..................................................................9 Initiating a Programming Sequence ...........................52 Divide Support ...................................................................18 Loading Write Latches ...............................................52 DSP Engine .......................................................................18 Port Write/Read Example ..........................................60 Multiplier ....................................................................20 Code Protection ...............................................................152 dsPIC30F6010A Port Register Map ..................................61 Complementary PWM Operation .....................................102 dsPIC30F6015 Port Register Map .....................................62 Configuring Analog Port Pins .............................................60 Dual Output Compare Match Mode ...................................86 Core Overview ...................................................................15 Continuous Pulse Mode .............................................86 CPU Architecture Overview ...............................................15 Single Pulse Mode .....................................................86 Customer Change Notification Service ............................231 E Customer Notification Service ..........................................231 Customer Support ............................................................231 Edge-Aligned PWM .........................................................100 Electrical Characteristics .................................................179 D Absolute Maximum Ratings .....................................179 Data Access from Program Memory Using Program BOR .........................................................................187 Space Visibility ...........................................................26 Equations Data Accumulators and Adder/Subtracter ..........................20 A/D Conversion Clock ..............................................143 Data Space Write Saturation .....................................22 Baud Rate ................................................................124 Write Back ..................................................................21 PWM Period .............................................................100 Data Accumulators and Adder/Subtractor PWM Resolution ......................................................100 Overflow and Saturation ............................................20 Serial Clock Rate .....................................................117 Round Logic ...............................................................21 Time Quantum for Clock Generation .......................134 Data Address Space ..........................................................27 Errata ...................................................................................7 Alignment ...................................................................30 External Interrupt Requests ...............................................45 Alignment (Figure) .....................................................30 F Effect of Invalid Memory Accesses ............................30 MCU and DSP (MAC Class) Instructions Example ....29 Fast Context Saving ..........................................................45 Memory Map ........................................................27, 28 Flash Program Memory .....................................................49 Near Data Space .......................................................31 In-Circuit Serial Programming (ICSP) ........................49 Software Stack ...........................................................31 Run-Time Self-Programming (RTSP) ........................49 Spaces .......................................................................30 Table Instruction Operation Summary .......................49 Width ..........................................................................30 I Data EEPROM Memory .....................................................55 Erasing .......................................................................56 I/O Ports .............................................................................59 Erasing, Block ............................................................56 Parallel I/O (PIO) .......................................................59 Erasing, Word ............................................................56 Idle Current (IIDLE) ...........................................................183 Protection Against Spurious Write .............................58 In-Circuit Debugger (ICD 2) .............................................164 Reading ......................................................................55 In-Circuit Serial Programming (ICSP) ..............................152 Write Verify ................................................................58 Independent PWM Output ...............................................103 Writing ........................................................................57 Initialization Condition for RCON Register Case 1 ..........161 Writing, Block .............................................................58 Initialization Condition for RCON Register Case 2 ..........161 Writing, Word .............................................................57 Input Capture Module ........................................................81 DC Characteristics ...........................................................180 Interrupts ...................................................................82 Brown-out Reset ......................................................186 Operation During Sleep and Idle Modes ....................82 I/O Pin Output Specifications ...................................186 Register Map .............................................................83 Idle Current (IIDLE) ...................................................183 Simple Capture Event Mode ......................................81 Operating Current (IDD) ............................................182 Input Change Notification Module ......................................63 Operating MIPS vs. Voltage for dsPIC30F6010A ....180 Register Map (bits 15-8) ............................................63 Operating MIPS vs. Voltage for dsPIC30F6015 ......180 Register Map (bits 7-0 for dsPIC30F6010A) ..............63 Power-Down Current (IPD) .......................................184 Register Map (bits 7-0 for dsPIC30F6015) ................63 Program and EEPROM ............................................187 Instruction Addressing Modes ...........................................35 Thermal Operating Conditions for File Register Instructions ...........................................35 dsPIC30F6010A/6015 ......................................180 Fundamental Modes Supported ................................35 Thermal Packaging Characteristics .........................180 MAC Instructions .......................................................36 Dead-Time Generators ....................................................102 MCU Instructions .......................................................35 Assignment ..............................................................103 Move and Accumulator Instructions ...........................36 Ranges .....................................................................103 Other Instructions ......................................................36 Selection Bits ...........................................................103 Instruction Set Development Support ......................................................175 Overview ..................................................................169 Device Configuration Summary .................................................................166 Register Map ............................................................165 Internet Address ..............................................................231 Device Configuration Registers ........................................163 Interrupt Controller FBORPOR ...............................................................163 Register Map (dsPIC30F6010A) ................................46 DS70150E-page 228 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 Register Map (dsPIC30F6015) ..................................47 Oscillator Selection ..........................................................152 Interrupt Priority .................................................................42 Output Compare Module ...................................................85 Interrupt Sequence ............................................................45 Interrupts ...................................................................88 Interrupt Stack Frame ................................................45 Operation During CPU Idle Mode ..............................88 Interrupts ............................................................................41 Operation During CPU Sleep Mode ..........................88 I2C Master Operation Register Map .............................................................89 Baud Rate Generator ...............................................116 P Clock Arbitration .......................................................117 Multi-Master Communication, Bus Collision and Bus Ar- Packaging Information .....................................................219 bitration ............................................................117 Marking ....................................................................219 Reception .................................................................116 Peripheral Module Disable (PMD) Registers ...................164 Transmission ............................................................116 Pin Diagrams ...................................................................5–6 I2C Module Pinout Descriptions ............................................................12 Addresses ................................................................114 POR. See Power-on Reset. General Call Address Support .................................116 Position Measurement Mode .............................................92 Interrupts ..................................................................116 Power Saving Modes IPMI Support ............................................................116 Idle ...........................................................................163 Master Operation .....................................................116 Sleep .......................................................................162 Master Support ........................................................116 Power-on Reset (POR) ....................................................152 Operating Function Description ...............................112 Oscillator Start-up Timer (OST) ...............................152 Operation During CPU Sleep and Idle Modes .........117 Power-up Timer (PWRT) .........................................152 Pin Configuration .....................................................112 Power-Saving Modes .......................................................162 Programmer’s Model ................................................112 Power-Saving Modes (Sleep and Idle) ............................152 Register Map ............................................................118 Program Address Space ....................................................23 Registers ..................................................................112 Construction ..............................................................24 Slope Control ...........................................................116 Data Access from Program Memory Using Software Controlled Clock Stretching (STREN = 1) .115 Table Instructions ..............................................25 Various Modes .........................................................112 Data Access from, Address Generation ....................24 I2C 10-bit Slave Mode Operation .....................................114 Memory Map ..............................................................23 10-bit Mode Slave Reception ...................................115 Table Instructions 10-bit Mode Slave Transmission ..............................115 TBLRDH ............................................................25 I2C 7-bit Slave Mode Operation .......................................114 TBLRDL .............................................................25 Reception .................................................................114 TBLWTH ............................................................25 Transmission ............................................................114 TBLWTL ............................................................25 I2C™ Module ...................................................................112 Program Counter ...............................................................16 Program Data Table Access ..............................................26 M Program Space Visibility Memory Organization .........................................................23 Window into Program Space Operation ....................27 Core Register Map .....................................................32 Programmable .................................................................152 Microchip Internet Web Site .............................................231 Programmable Digital Noise Filters ...................................93 Modulo Addressing ............................................................36 Programmer’s Model .........................................................16 Applicability ................................................................38 Diagram .....................................................................17 Operation Example ....................................................37 Programming Operations ...................................................51 Start and End Address ...............................................37 Algorithm for Program Flash ......................................51 W Address Register Selection ...................................37 Erasing a Row of Program Memory ..........................51 Motor Control PWM Module ...............................................97 Initiating the Programming Sequence .......................52 8-Output Register Map .............................................107 Loading Write Latches ...............................................52 MPLAB ASM30 Assembler, Linker, Librarian ..................176 Protection Against Accidental Writes to OSCCON ..........158 MPLAB Integrated Development Environment Software .175 PWM Duty Cycle Comparison Units ................................101 MPLAB PM3 Device Programmer ...................................178 Duty Cycle Immediate Updates ...............................102 MPLAB REAL ICE In-Circuit Emulator System ................177 Duty Cycle Register Buffers ....................................102 MPLINK Object Linker/MPLIB Object Librarian ...............176 PWM Fault Pins ...............................................................105 Enable Bits ..............................................................105 O Fault States .............................................................105 Operating Current (IDD) ....................................................182 Input Modes .............................................................105 Oscillator Cycle-by-Cycle ................................................105 Operating Modes (Table) .........................................153 Latched ............................................................105 System Overview .....................................................152 Priority .....................................................................105 Oscillator Configurations ..................................................155 PWM Operation During CPU Idle Mode ..........................106 Fail-Safe Clock Monitor ............................................157 PWM Operation During CPU Sleep Mode .......................106 Fast RC (FRC) .........................................................156 PWM Output and Polarity Control ....................................105 Initial Clock Source Selection ..................................155 Output Pin Control ...................................................105 Low-Power RC (LPRC) ............................................157 PWM Output Override .....................................................104 LP Oscillator Control ................................................156 Complementary Output Mode .................................104 Phase Locked Loop (PLL) .......................................156 Synchronization .......................................................104 Start-up Timer (OST) ...............................................156 PWM Period .....................................................................100 © 2011 Microchip Technology Inc. DS70150E-page 229

dsPIC30F6010A/6015 PWM Special Event Trigger .............................................106 Word and Byte Communication ...............................108 Postscaler ................................................................106 STATUS Register ..............................................................16 PWM Time Base ................................................................99 Symbols Used in Opcode Descriptions ...........................167 Continuous Up/Down Counting Modes ......................99 System Integration ...........................................................152 Double Update Mode ...............................................100 Register Map for dsPIC30F6010A ...........................165 Free-Running Mode ...................................................99 Register Map for dsPIC30F6015 .............................165 Postscaler ................................................................100 T Prescaler ..................................................................100 Single-Shot Mode ......................................................99 Timer1 Module ...................................................................65 PWM Update Lockout ......................................................106 Gate Operation ..........................................................66 Interrupt .....................................................................66 Q Operation During Sleep Mode ...................................66 QEI Prescaler ...................................................................66 16-bit Up/Down Position Counter Mode .....................92 Real-Time Clock ........................................................66 Count Direction Status .......................................92 Interrupts ...........................................................67 Error Checking ...................................................92 Oscillator Operation ...........................................67 Quadrature Encoder Interface (QEI) Module .....................91 Register Map .............................................................68 Interrupts ....................................................................94 16-bit Asynchronous Counter Mode ..........................65 Logic ..........................................................................92 16-bit Synchronous Counter Mode ............................65 Operation During CPU Idle Mode ..............................93 16-bit Timer Mode ......................................................65 Operation During CPU Sleep Mode ...........................93 Timer2 and Timer3 Selection Mode ...................................86 Register Map ..............................................................95 Timer2/3 Module ................................................................69 Timer Operation During CPU Idle Mode ....................94 ADC Event Trigger .....................................................74 Timer Operation During CPU Sleep Mode .................93 Gate Operation ..........................................................74 Interrupt .....................................................................74 R Operation During Sleep Mode ...................................74 Reader Response ............................................................232 Register Map .............................................................75 Reset ........................................................................152, 158 Timer Prescaler .........................................................74 Reset Sequence .................................................................43 32-bit Synchronous Counter Mode ............................69 Reset Sources ...........................................................43 32-bit Timer Mode ......................................................69 Resets Timer4/5 Module ................................................................77 Brown-out Rest (BOR), Programmable ...................160 Register Map .............................................................79 POR with Long Crystal Start-up Time ......................160 Timing Diagrams POR, Operating without FSCM and PWRT .............160 Band Gap Start-up Time ..........................................195 Power-on Reset (POR) ............................................158 CAN Bit ....................................................................133 Revision History ...............................................................223 CAN I/O ...................................................................213 RTSP Control Registers .....................................................50 Center-Aligned PWM ...............................................101 NVMADR ...................................................................50 Dead-Time ...............................................................103 NVMADRU .................................................................50 Edge-Aligned PWM .................................................101 NVMCON ...................................................................50 External Clock ..........................................................188 NVMKEY ....................................................................50 Input Capture (CAPx) ..............................................199 I2C Bus Data (Master Mode) ...................................209 S I2C Bus Data (Slave Mode) .....................................211 Simple Capture Event Mode I2C Bus Start/Stop Bits (Master Mode) ....................209 Capture Buffer Operation ...........................................82 I2C Bus Start/Stop Bits (Slave Mode) ......................211 Capture Prescaler ......................................................81 Motor Control PWM .................................................201 Hall Sensor Mode ......................................................82 Motor Control PWM Fault ........................................201 Timer2 and Timer3 Selection Mode ...........................82 OC/PWM ..................................................................200 Simple Output Compare Match Mode ................................86 Output Compare (OCx) ............................................199 Simple PWM Mode ............................................................86 PWM Output ..............................................................87 Input Pin Fault Protection ...........................................86 QEA/QEB Input .......................................................202 Period .........................................................................87 QEI Module Index Pulse ..........................................203 Single-Pulse PWM Operation ..........................................103 Reset, Watchdog Timer, Oscillator Start-up Timer Software Controlled Clock Stretching (STREN = 1) .........115 and Power-up Timer ........................................194 Software Simulator (MPLAB SIM) ....................................177 SPI Master Mode (CKE = 0) ....................................204 Software Stack Pointer, Frame Pointer ..............................16 SPI Master Mode (CKE = 1) ....................................205 CALL Stack Frame .....................................................31 SPI Slave Mode (CKE = 0) ......................................206 SPI Module .......................................................................108 SPI Slave Mode (CKE = 1) ......................................207 Framed SPI Support ................................................110 Time-out Sequence on Power-up Operating Function Description ...............................108 (MCLR Not Tied to VDD), Case 1 ....................159 Operation During CPU Idle Mode ............................110 Time-out Sequence on Power-up Operation During CPU Sleep Mode .........................110 (MCLR Not Tied to VDD), Case 2 ....................159 SDOx Disable ..........................................................108 Time-out Sequence on Power-up Slave Select Synchronization ..................................110 (MCLR Tied to VDD) .................................................159 SPI1 Register Map ...................................................111 TimerQ (QEI Module) External Clock ......................198 SPI2 Register Map ...................................................111 Timer1, 2, 3, 4, 5 External Clock .............................196 DS70150E-page 230 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 10-bit High-Speed A/D Conversion (CHPS = 01, Transmit Break ................................................123 SIMSAM = 0, ASAM = 0, SSRC = 000) ...........216 Transmit Buffer (UxTXB) .................................122 10-bit High-Speed A/D Conversion (CHPS = 01, UART1 Register Map ..............................................126 SIMSAM = 0, ASAM = 1, SSRC = 111, UART2 Register Map ..............................................126 SAMC = 00001) ...............................................217 Unit ID Locations .............................................................152 Timing Requirements Universal Asynchronous Receiver Transmitter Input Capture ...........................................................199 Module (UART) ........................................................120 Timing Specifications W Band Gap Start-up Time Requirements ...................195 CAN I/O Requirements ............................................213 Wake-up from Sleep ........................................................152 CLKOUT and I/O Characteristics .............................193 Wake-up from Sleep and Idle ............................................45 CLKOUT and I/O Requirements ..............................193 Watchdog Timer (WDT) ...........................................152, 162 External Clock Requirements ..................................189 Enabling and Disabling ............................................162 Internal Clock Examples ..........................................191 Operation .................................................................162 I2C Bus Data Requirements (Master Mode) ............210 WWW Address ................................................................231 I2C Bus Data Requirements (Slave Mode) ..............212 WWW, On-Line Support ......................................................7 Motor Control PWM Requirements ..........................201 Output Compare Requirements ...............................199 PLL Clock .................................................................190 PLL Jitter ..................................................................190 QEI External Clock Requirements ...........................198 QEI Index Pulse Requirements ................................203 Quadrature Decoder Requirements .........................202 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ..................................................195 Simple OC/PWM Mode Requirements ....................200 SPI Master Mode (CKE = 0) Requirements .............204 SPI Master Mode (CKE = 1) Requirements .............205 SPI Slave Mode (CKE = 0) Requirements ...............206 SPI Slave Mode (CKE = 1) Requirements ...............207 Timer1 External Clock Requirements ......................196 Timer2 and Timer4 External Clock Requirements ...197 Timer3 and Timer5 External Clock Requirements ...197 10-bit High-Speed A/D .............................................214 10-bit High-Speed A/D Conversion Requirements ..218 Traps ..................................................................................43 Hard and Soft .............................................................44 Sources ......................................................................43 Vectors .......................................................................44 U UART Address Detect Mode ..............................................124 Auto-Baud Support ..................................................125 Baud Rate Generator (BRG) ....................................124 Disabling ..................................................................122 Enabling and Setup ..................................................122 Loopback Mode .......................................................124 Module Overview .....................................................120 Operation During CPU Sleep and Idle Modes .........125 Receiving Data .........................................................123 In 8-bit or 9-bit Data Mode ...............................123 Interrupt ...........................................................123 Receive Buffer (UxRXB) ..................................123 Reception Error Handling .........................................123 Framing Error (FERR) .....................................124 Idle Status ........................................................124 Parity Error (PERR) .........................................124 Receive Break .................................................124 Receive Buffer Overrun Error (OERR Bit) .......123 Setting Up Data, Parity and Stop Bit Selections ......122 Transmitting Data .....................................................122 In 8-bit Data Mode ...........................................122 In 9-bit Data Mode ...........................................122 Interrupt ...........................................................123 © 2011 Microchip Technology Inc. DS70150E-page 231

dsPIC30F6010A/6015 NOTES: DS70150E-page 232 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design • Development Systems Information Line resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQs), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. © 2011 Microchip Technology Inc. DS70150E-page 233

dsPIC30F6010A/6015 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: dsPIC30F6010A/6015 Literature Number: DS70150E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70150E-page 234 © 2011 Microchip Technology Inc.

dsPIC30F6010A/6015 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC30F6010AT-30I/PF-000 Custom ID (3 digits) or Trademark Engineering Sample (ES) Architecture Package Flash PF = TQFP 14x14 PT = TQFP 12x12 PT = TQFP 10x10 Memory Size in Bytes S = Die (Waffle Pack) 0 = ROMless W = Die (Wafers) 1 = 1K to 6K 2 = 7K to 12K 3 = 13K to 24K 4 = 25K to 48K Temperature 5 = 49K to 96K I = Industrial -40°C to +85°C 6 = 97K to 192K E = Extended High Temp -40°C to +125°C 7 = 193K to 384K 8 = 385K to 768K 9 = 769K and Up Speed 20 = 20 MIPS 30 = 30 MIPS Device ID T = Tape and Reel A,B,C… = Revision Level Example: dsPIC30F6010AT-30I/PF = 30 MIPS, Industrial temp., TQFP package, Rev. A © 2011 Microchip Technology Inc. DS70150E-page 235

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: DSPIC30F6010A-20E/PF DSPIC30F6010A-20E/PT DSPIC30F6010A-30I/PF DSPIC30F6010A-30I/PT DSPIC30F6010AT-20E/PT DSPIC30F6010AT-30I/PT DSPIC30F6015-20E/PT DSPIC30F6015-30I/PT DSPIC30F6015T-20E/PT DSPIC30F6015T-30I/PT DSPIC30F6010AT-30I/PF