dsPIC30F3014/4013 Data Sheet High-Performance, 16-bit Digital Signal Controllers  2010 Microchip Technology Inc. DS70138G

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-666-1 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70138G-page 2  2010 Microchip Technology Inc.

dsPIC30F3014/4013 High-Performance, 16-Bit Digital Signal Controllers Peripheral Features: Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not • High-Current Sink/Source I/O Pins: 25mA/25mA intended to be a complete reference • Up to Five 16-Bit Timers/Counters; Optionally Pair source. For more information on the CPU, Up peripherals, register descriptions and 16-Bit Timers into 32-Bit Timer modules general device functionality, refer to the • Up to Four 16-Bit Capture Input Functions “dsPIC30F Family Reference Manual” • Up to Four 16-Bit Compare/PWM Output Functions (DS70046). For more information on the • Data Converter Interface (DCI) Supports Common device instruction set and programming, refer to the “16-bit MCU and DSC Pro- Audio Codec Protocols, Including I2S and AC’97 grammer’s Reference Manual” • 3-Wire SPI module (supports 4 Frame modes) (DS70157). • I2C™ module Supports Multi-Master/Slave mode and 7-Bit/10-Bit Addressing High-Performance Modified RISC CPU: • Up to Two Addressable UART modules with FIFO Buffers • Modified Harvard Architecture • CAN bus module Compliant with CAN 2.0B • C Compiler Optimized Instruction Set Architecture Standard • Flexible Addressing modes • 83 Base Instructions Analog Features: • 24-Bit Wide Instructions, 16-Bit Wide Data Path • 12-Bit Analog-to-Digital Converter (ADC) with: • Up to 48 Kbytes On-Chip Flash Program Space - 200 ksps conversion rate • 2 Kbytes of On-Chip Data RAM - Up to 13 input channels • 1 Kbyte of Nonvolatile Data EEPROM - Conversion available during Sleep and Idle • 16 x 16-Bit Working Register Array • Programmable Low-Voltage Detection (PLVD) • Up to 30 MIPS Operation: • Programmable Brown-out Reset - DC to 40MHz External Clock Input - 4MHz-10MHz Oscillator Input with Special Microcontroller Features: PLL Active (4x, 8x, 16x) • Up to 33 Interrupt Sources: • Enhanced Flash Program Memory: - 8 user-selectable priority levels - 10,000 erase/write cycle (min.) for - 3 external interrupt sources industrial temperature range, 100K (typical) - 4 processor traps • Data EEPROM Memory: - 100,000 erase/write cycle (min.) for DSP Features: industrial temperature range, 1M (typical) • Self-Reprogrammable under Software Control • Dual Data Fetch • Power-on Reset (POR), Power-up Timer (PWRT) • Modulo and Bit-Reversed modes and Oscillator Start-up Timer (OST) • Two 40-Bit Wide Accumulators with Optional • Flexible Watchdog Timer (WDT) with On-Chip saturation Logic Low-Power RC Oscillator for Reliable Operation • 17-Bit x 17-Bit Single-Cycle Hardware • Fail-Safe Clock Monitor Operation: Fractional/Integer Multiplier - Detects clock failure and switches to on-chip • All DSP Instructions are Single Cycle low-power RC oscillator - Multiply-Accumulate (MAC) Operation • Programmable Code Protection • Single-Cycle ±16 Shift • In-Circuit Serial Programming™ (ICSP™) • Selectable Power Management modes: - Sleep, Idle and Alternate Clock modes  2010 Microchip Technology Inc. DS70138G-page 3

dsPIC30F3014/4013 CMOS Technology: • Low-Power, High-Speed Flash Technology • Wide Operating Voltage Range (2.5V to 5.5V) • Industrial and Extended Temperature Ranges • Low-Power Consumption dsPIC30F3014/4013 Controller Family Device Pins BPyrtoegsraImns Mtruecmtioornys SBRyAteMs EEBPyRteOsM 1T6im-Beirt ICnpaupt SOCtduo PtmpWpu/tM InCteordfeacce A2/0D0 1K2s-Bpsit UART SPI 2™CI CAN dsPIC30F3014 40/44 24K 8K 2048 1024 3 2 2 — 13 ch 2 1 1 0 dsPIC30F4013 40/44 48K 16K 2048 1024 5 4 4 AC’97, I2S 13 ch 2 1 1 1 Pin Diagrams 40-Pin PDIP MCLR 1 40 AVDD AN0/VREF+/CN2/RB0 2 39 AVss AN1/VREF-/CN3/RB1 3 38 AN9/RB9 AN2/SS1/LVDIN/CN4/RB2 4 37 AN10/RB10 AN3/CN5/RB3 5 36 AN11/RB11 AN4/CN6/RB4 6 35 AN12/RB12 AN5/CN7/RB5 7 4 34 EMUC2/OC1/RD0 PGC/EMUC/AN6/OCFA/RB6 8 01 33 EMUD2/OC2/RD1 PGD/EMUD/AN7/RB7 9 3 32 VDD F AN8/RB8 10 0 31 Vss VDD 11 3 30 RF0 Vss 12 C 29 RF1 OSC1/CLKI 13 PI 28 U2RX/CN17/RF4 OSC2/CLKO/RC15 14 ds 27 U2TX/CN18/RF5 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 15 26 U1RX/SDI1/SDA/RF2 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 16 25 EMUD3/U1TX/SDO1/SCL/RF3 INT0/RA11 17 24 EMUC3/SCK1/RF6 IC2/INT2/RD9 18 23 IC1/INT1/RD8 RD3 19 22 RD2 Vss 20 21 VDD 40-Pin PDIP MCLR 1 40 AVDD AN0/VREF+/CN2/RB0 2 39 AVSS AN1/VREF-/CN3/RB1 3 38 AN9/CSCK/RB9 AN2/SS1/LVDIN/CN4/RB2 4 37 AN10/CSDI/RB10 AN3/CN5/RB3 5 36 AN11/CSDO/RB11 AN4/IC7/CN6/RB4 6 35 AN12/COFS/RB12 AN5/IC8/CN7/RB5 7 13 34 EMUC2/OC1/RD0 PGC/EMUC/AN6/OCFA/RB6 8 0 33 EMUD2/OC2/RD1 PGD/EMUD/AN7/RB7 9 F4 32 VDD AN8/RB8 10 0 31 VSS VDD 11 3 30 C1RX/RF0 OSC1/CVLSKSI 1123 PIC 2298 CU12TRXX//RCFN117/RF4 OSC2/CLKO/RC15 14 ds 27 U2TX/CN18/RF5 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 15 26 U1RX/SDI1/SDA/RF2 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 16 25 EMUD3/U1TX/SDO1/SCL/RF3 INT0/RA11 17 24 EMUC3/SCK1/RF6 IC2/INT2/RD9 18 23 IC1/INT1/RD8 OC4/RD3 19 22 OC3/RD2 VSS 20 21 VDD DS70138G-page 4  2010 Microchip Technology Inc.

dsPIC30F3014/4013 Pin Diagrams (Continued) 44-Pin TQFP 4 1 C R 0/ N C 3 X/ F R R A CL/ U1 S K/ 1/ C SDORF6 O/T1 EMUD3/U1TX/EMUC3/SCK1/IC1/NT1/RD8RD2VDDVSSRD3IC2/INT2/RD9INT0/RA11EMUC1/SOSCNC 43210987654 44444333333 U1RX/SDI1/SDA/RF2 1 33 NC U2TX/CN18/RF5 2 32 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 U2RX/CN17/RF4 3 31 OSC2/CLKO/RC15 RF1 4 30 OSC1/CLKI RF0 5 29 VSS VSS 6 dsPIC30F3014 28 VDD VDD 7 27 AN8/RB8 EMUD2/OC2/RD1 8 26 PGD/EMUD/AN7/RB7 EMUC2/OC1/RD0 9 25 PGC/EMUC/AN6/OCFA/RB6 AN12/RB12 10 24 AN5/CN7/RB5 AN11/RB11 11 23 AN4/CN6/RB4 23456789012 11111111222 CC09SDR0123 NN0/RB1N9/RBAVSAVDMCLN2/RBN3/RBN4/RBN5/RB AN1A AN0/V+/CREFAN1/V-/CREFSS1/LVDIN/CAN3/C 2/ N A  2010 Microchip Technology Inc. DS70138G-page 5

dsPIC30F3014/4013 Pin Diagrams (Continued) 44-Pin QFN(1) 4 13 C1 RC N0/1/R CN F3 RX/X/C R AT TX/SDO1/SCL/K1/RF6D8 D9 SCO/T1CK/U1SCI/T2CK/U1A EMUD3/U1EMUC3/SCIC1/INT1/RRD2VDDVSSRD3IC2/INT2/RINT0/RA11EMUC1/SOEMUD1/SO 43210987654 44444333333 U1RX/SDI1/SDA/RF2 1 33 OSC2/CLKO/RC15 U2TX/CN18/RF5 2 32 OSC1/CLKI U2RX/CN17/RF4 3 31 VSS RF1 4 30 VSS RF0 5 29 VDD VSS 6 dsPIC30F3014 28 VDD VDD 7 27 AN8/RB8 VDD 8 26 PGD/EMUD/AN7/RB7 EMUD2/OC2/RD1 9 25 PGC/EMUC/AN6/OCFA/RB6 EMUC2/OC1/RD0 10 24 AN5/CN7/RB5 AN12/RB12 11 23 AN4/CN6/RB4 23456789012 11111111222 AN11/RB11NCAN10/RB10AN9/RB9AVSSAVDDMCLRAN0/V+/CN2/RB0REFAN1/V-/CN3/RB1REFSS1/LVDIN/CN4/RB2 AN3/CN5/RB3 2/ N A Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70138G-page 6  2010 Microchip Technology Inc.

dsPIC30F3014/4013 Pin Diagrams (Continued) 44-Pin TQFP 4 1 C R 0/ N C 3 X/ F R R A CL/ U1 S K/ 1/ C SDORF6 O/T1 TX/K1/D8 D9 SC EMUD3/U1EMUC3/SCIC1/INT1/ROC3/RD2VDDVSSOC4/RD3IC2/INT2/RINT0/RA11EMUC1/SONC 43210987654 44444333333 U1RX/SDI1/SDA/RF2 1 33 NC U2TX/CN18/RF5 2 32 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 U2RX/CN17/RF4 3 31 OSC2/CLKO/RC15 C1TX/RF1 4 30 OSC1/CLKI C1RX/RF0 5 29 VSS VSS 6 dsPIC30F4013 28 VDD VDD 7 27 AN8/RB8 EMUD2/OC2/RD1 8 26 PGD/EMUD/AN7/RB7 EMUC2/OC1/RD0 9 25 PGC/EMUC/AN6/OCFA/RB6 AN12/COFS/RB12 10 24 AN5/IC8/CN7/RB5 AN11/CSDO/RB11 11 23 AN4/IC7/CN6/RB4 23456789012 11111111222 CC09SDR0123 NNDI/RB1CK/RBAVSAVDMCLN2/RBN3/RBN4/RBN5/RB SS CCCC AN10/CAN9/C AN0/V+/REFAN1/V-/REFSS1/LVDIN/AN3/ 2/ N A  2010 Microchip Technology Inc. DS70138G-page 7

dsPIC30F3014/4013 Pin Diagrams (Continued) 44-Pin QFN(1) 4 13 C1 RC N0/1/R CN F3 RX/X/C R AT EMUD3/U1TX/SDO1/SCL/EMUC3/SCK1/RF6IC1/NT1/RD8OC3/RD2VDDVSSOC4/RD3IC2/INT2/RD9INT0/RA11EMUC1/SOSCO/T1CK/U1EMUD1/SOSCI/T2CK/U1A 43210987654 44444333333 U1RX/SDI1/SDA/RF2 1 33 OSC2/CLKO/RC15 U2TX/CN18/RF5 2 32 OSC1/CLKI U2RX/CN17/RF4 3 31 VSS C1TX/RF1 4 30 VSS C1RX/RF0 5 29 VDD VSS 6 dsPIC30F4013 28 VDD VDD 7 27 AN8/RB8 VDD 8 26 PGD/EMUD/AN7/RB7 EMUD2/OC2/RD1 9 25 PGC/EMUC/AN6/OCFA/RB6 EMUC2/OC1/RD0 10 24 AN5/IC8/CN7/RB5 AN12/COFS/RB12 11 23 AN4/IC7/CN6/RB4 23456789012 11111111222 AN11/CSDO/RB11NCAN10/CSDI/RB10AN9/CSCK/RB9AVSSAVDDMCLRAN0/V+/CN2/RB0REFAN1/V-/CN3/RB1REFSS1/LVDIN/CN4/RB2AN3/CN5/RB3 2/ N A Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70138G-page 8  2010 Microchip Technology Inc.

dsPIC30F3014/4013 Table of Contents 1.0 Device Overview........................................................................................................................................................................11 2.0 CPU Architecture Overview........................................................................................................................................................15 3.0 Memory Organization.................................................................................................................................................................25 4.0 Address Generator Units............................................................................................................................................................37 5.0 Flash Program Memory..............................................................................................................................................................43 6.0 Data EEPROM Memory.............................................................................................................................................................49 7.0 I/O Ports.....................................................................................................................................................................................53 8.0 Interrupts....................................................................................................................................................................................59 9.0 Timer1 Module...........................................................................................................................................................................67 10.0 Timer2/3 Module........................................................................................................................................................................71 11.0 Timer4/5 Module .......................................................................................................................................................................77 12.0 Input Capture Module.................................................................................................................................................................81 13.0 Output Compare Module............................................................................................................................................................85 14.0 I2C™ Module.............................................................................................................................................................................91 15.0 SPI Module.................................................................................................................................................................................99 16.0 Universal Asynchronous Receiver Transmitter (UART) Module..............................................................................................103 17.0 CAN Module.............................................................................................................................................................................111 18.0 Data Converter Interface (DCI) Module....................................................................................................................................121 19.0 12-bit Analog-to-Digital Converter (ADC) Module....................................................................................................................131 20.0 System Integration...................................................................................................................................................................141 21.0 Instruction Set Summary..........................................................................................................................................................159 22.0 Development Support...............................................................................................................................................................167 23.0 Electrical Characteristics..........................................................................................................................................................171 24.0 Packaging Information..............................................................................................................................................................211 Index................................................................................................................................................................................................. 219 The Microchip Web Site.....................................................................................................................................................................225 Customer Change Notification Service..............................................................................................................................................225 Customer Support..............................................................................................................................................................................225 Reader Response..............................................................................................................................................................................226 Product Identification System............................................................................................................................................................227 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2010 Microchip Technology Inc. DS70138G-page 9

dsPIC30F3014/4013 NOTES: DS70138G-page 10  2010 Microchip Technology Inc.

dsPIC30F3014/4013 1.0 DEVICE OVERVIEW This document contains specific information for the dsPIC30F3014/4013 Digital Signal Controller (DSC) Note: This data sheet summarizes features of devices. The dsPIC30F3014/4013 devices contain this group ofdsPIC30F devices and is not extensive Digital Signal Processor (DSP) functionality intended to be a complete reference within a high-performance, 16-bit microcontroller source. For more information on the CPU, (MCU) architecture. Figure1-1 and Figure1-2 show peripherals, register descriptions and device block diagrams for dsPIC30F3014 and general device functionality, refer to the dsPIC30F4013, respectively. “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Pro- grammer’s Reference Manual” (DS70157). FIGURE 1-1: dsPIC30F3014 BLOCK DIAGRAM Y Data Bus X Data Bus 16 16 16 16 CInotnetrrroulpletr DPaStVa A& cTcaebslse DaYt aD Laatatc h DaXt aD Laatatc h INT0/RA11 24Control Block 8 16 RAM RAM (1 Kbyte) (1 Kbyte) Address Address PORTA 24 Latch Latch 16 16 16 24 Y AGU X RAGU AN0/VREF+/CN2/RB0 PCU PCH PCL X WAGU AN1/VREF-/CN3/RB1 Program Counter AN2/SS1/LVDIN/CN4/RB2 Address Latch Stack Loop 16 AN3/CN5/RB3 Control Control Program Memory Logic Logic AN4/CN6/RB4 (24 Kbytes) AN5/CN7/RB5 PGC/EMUC/AN6/OCFA/RB6 Data EEPROM PGD/EMUD/AN7/RB7 (1 Kbyte) Effective Address AN8/RB8 Data Latch 16 AN9/RB9 AN10/RB10 AN11/RB11 ROM Latch 16 AN12/RB12 24 PORTB IR 16 16 EMUD1/SOSCI/T2CK/U1ATX/ 16 x 16 CN1/RC13 Decode W Reg Array EMUC1/SOSCO/T1CK/U1ARX/ CN0/RC14 Instruction Decode and 16 16 OSC2/CLKO/RC15 Control PORTC Control Signals DSP Divide to Various Blocks Power-up Engine Unit Timer OSC1/CLKI Timing Oscillator EMUC2/OC1/RD0 Generation Start-up Timer EMUD2/OC2/RD1 POR/BOR ALU<16> RD2 Reset RD3 MCLR Watchdog 16 16 IICC12//IINNTT12//RRDD89 Timer Low-Voltage VDD, VSS Detect PORTD AVDD, AVSS Input Output RF0 12-Bit ADC Capture Compare I2C™ RF1 Module Module U1RX/SDI1/SDA/RF2 EMUD3/U1TX/SDO1/SCL/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/RF6 UART1, Timers SPI1 UART2 PORTF  2010 Microchip Technology Inc. DS70138G-page 11

dsPIC30F3014/4013 FIGURE 1-2: dsPIC30F4013 BLOCK DIAGRAM Y Data Bus X Data Bus 16 16 16 16 CInotnetrrroulpletr DPaStVa &A cTcaebslse DaYt aD Laatatc h DaXt aD Laatatc h INT0/RA11 24Control Block 8 16 RAM RAM (1 Kbyte) (1 Kbyte) Address Address PORTA 24 Latch Latch 16 16 16 24 Y AGU X RAGU AN0/VREF+/CN2/RB0 PCU PCH PCL X WAGU AN1/VREF-/CN3/RB1 Program Counter AN2/SS1/LVDIN/CN4/RB2 Address Latch Stack Loop 16 AN3/CN5/RB3 Control Control Program Memory Logic Logic AN4/IC7/CN6/RB4 (48 Kbytes) AN5/IC8/CN7/RB5 PGC/EMUC/AN6/OCFA/RB6 Data EEPROM PGD/EMUD/AN7/RB7 (1 Kbyte) Effective Address AN8/RB8 Data Latch 16 AN9/CSCK/RB9 AN10/CSDI/RB10 AN11/CSDO/RB11 ROM Latch 16 AN12/COFS/RB12 24 PORTB IR 16 16 EMUD1/SOSCI/T2CK/U1ATX/ 16 x 16 CN1/RC13 Decode W Reg Array EMUC1/SOSCO/T1CK/U1ARX/ CN0/RC14 Instruction Decode & 16 16 OSC2/CLKO/RC15 Control PORTC Control Signals DSP Divide to Various Blocks Power-up Engine Unit Timer EMUC2/OC1/RD0 OSC1/CLKI Timing Oscillator EMUD2/OC2/RD1 Generation Start-up Timer OC3/RD2 POR/BOR ALU<16> OC4/RD3 Reset IC1/INT1/RD8 MCLR Watchdog 16 16 IC2/INT2/RD9 Timer Low-Voltage PORTD VDD, VSS Detect AVDD, AVSS Input Output C1RX/RF0 CAN1 12-Bit ADC Capture Compare I2C™ C1TX/RF1 Module Module U1RX/SDI1/SDA/RF2 EMUD3/U1TX/SDO1/SCL/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 EMUC3/SCK1/RF6 UART1, Timers DCI SPI1 UART2 PORTF DS70138G-page 12  2010 Microchip Technology Inc.

dsPIC30F3014/4013 Table1-1 provides a brief description of device I/O pin- outs and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name Description Type Type AN0-AN12 I Analog Analog input channels. AN6 and AN7 are also used for device programming data and clock inputs, respectively. AVDD P P Positive supply for analog module. This pin must be connected at all times. AVSS P P Ground reference for analog module. This pin must be connected at all times. CLKI I ST/CMOS External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. CLKO O — Always associated with OSC2 pin function. CN0-CN7, I ST Input change notification inputs. Can be software programmed for internal CN17-CN18 weak pull-ups on all inputs. COFS I/O ST Data Converter Interface Frame Synchronization pin. CSCK I/O ST Data Converter Interface Serial Clock input/output pin. CSDI I ST Data Converter Interface Serial data input pin. CSDO O — Data Converter Interface Serial data output pin. C1RX I ST CAN1 bus receive pin. C1TX O — CAN1 bus transmit pin. EMUD I/O ST ICD Primary Communication Channel data input/output pin. EMUC I/O ST ICD Primary Communication Channel clock input/output pin. EMUD1 I/O ST ICD Secondary Communication Channel data input/output pin. EMUC1 I/O ST ICD Secondary Communication Channel clock input/output pin. EMUD2 I/O ST ICD Tertiary Communication Channel data input/output pin. EMUC2 I/O ST ICD Tertiary Communication Channel clock input/output pin. EMUD3 I/O ST ICD Quaternary Communication Channel data input/output pin. EMUC3 I/O ST ICD Quaternary Communication Channel clock input/output pin. IC1, IC2, IC7, I ST Capture inputs 1,2, 7 and 8. IC8 INT0 I ST External interrupt 0. INT1 I ST External interrupt 1. INT2 I ST External interrupt 2. LVDIN I Analog Low-Voltage Detect Reference Voltage Input pin. MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active-low Reset to the device. OCFA I ST Compare Fault A input (for Compare channels 1, 2, 3 and 4). OC1-OC4 O — Compare outputs 1 through 4. OSC1 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. OSC2 I/O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. PGD I/O ST In-Circuit Serial Programming data input/output pin. PGC I ST In-Circuit Serial Programming clock input pin. Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power  2010 Microchip Technology Inc. DS70138G-page 13

dsPIC30F3014/4013 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Description Type Type RA11 I/O ST PORTA is a bidirectional I/O port. RB0-RB12 I/O ST PORTB is a bidirectional I/O port. RC13-RC15 I/O ST PORTC is a bidirectional I/O port. RD0-RD3, I/O ST PORTD is a bidirectional I/O port. RD8, RD9 RF0-RF5 I/O ST PORTF is a bidirectional I/O port. SCK1 I/O ST Synchronous serial clock input/output for SPI1. SDI1 I ST SPI1 data in. SDO1 O — SPI1 data out. SS1 I ST SPI1 slave synchronization. SCL I/O ST Synchronous serial clock input/output for I2C™. SDA I/O ST Synchronous serial data input/output for I2C. SOSCO O — 32 kHz low-power oscillator crystal output. SOSCI I ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. T1CK I ST Timer1 external clock input. T2CK I ST Timer2 external clock input. U1RX I ST UART1 receive. U1TX O — UART1 transmit. U1ARX I ST UART1 alternate receive. U1ATX O — UART1 alternate transmit. VDD P — Positive supply for logic and I/O pins. VSS P — Ground reference for logic and I/O pins. VREF+ I Analog Analog voltage reference (high) input. VREF- I Analog Analog voltage reference (low) input. Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power DS70138G-page 14  2010 Microchip Technology Inc.

dsPIC30F3014/4013 2.0 CPU ARCHITECTURE There are two methods of accessing data stored in OVERVIEW program memory: • The upper 32 Kbytes of data space memory can Note: This data sheet summarizes features of be mapped into the lower half (user space) of pro- this group ofdsPIC30F devices and is not gram space at any 16K program word boundary, intended to be a complete reference defined by the 8-bit Program Space Visibility Page source. For more information on the CPU, (PSVPAG) register. This lets any instruction peripherals, register descriptions and access program space as if it were data space, general device functionality, refer to the with a limitation that the access requires an addi- “dsPIC30F Family Reference Manual” tional cycle. Moreover, only the lower 16 bits of (DS70046). For more information on the each instruction word can be accessed using this device instruction set and programming, method. refer to the “16-bit MCU and DSC Pro- • Linear indirect access of 32K word pages within grammer’s Reference Manual” program space is also possible using any working (DS70157). register, via table read and write instructions. Table read and write instructions can be used to 2.1 Core Overview access all 24 bits of an instruction word. Overhead-free circular buffers (Modulo Addressing) This section contains a brief overview of the CPU are supported in both X and Y address spaces. This is architecture of the dsPIC30F. primarily intended to remove the loop overhead for The core has a 24-bit instruction word. The Program DSP algorithms. Counter (PC) is 23 bits wide with the Least Significant The X AGU also supports Bit-Reversed Addressing on bit (LSb) always clear (refer to Section3.1 “Program destination effective addresses to greatly simplify input Address Space”), and the Most Significant bit (MSb) or output data reordering for radix-2 FFT algorithms. is ignored during normal program execution, except for Refer to Section4.0 “Address Generator Units” for certain specialized instructions. Thus, the PC can details on Modulo and Bit-Reversed Addressing. address up to 4M instruction words of user program space. An instruction prefetch mechanism is used to The core supports Inherent (no operand), Relative, help maintain throughput. Program loop constructs, Literal, Memory Direct, Register Direct, Register free from loop count management overhead, are Indirect, Register Offset and Literal Offset Addressing supported using the DO and REPEAT instructions, both modes. Instructions are associated with predefined of which are interruptible at any point. addressing modes, depending upon their functional requirements. The working register array consists of 16-bit x 16-bit registers, each of which can act as data, address or off- For most instructions, the core is capable of executing set registers. One working register (W15) operates as a data (or program data) memory read, a working reg- a Software Stack Pointer for interrupts and calls. ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a The data space is 64 Kbytes (32K words) and is split result, 3-operand instructions are supported, allowing into two blocks, referred to as X and Y data memory. C=A+B operations to be executed in a single cycle. Each block has its own independent Address Genera- tion Unit (AGU). Most instructions operate solely A DSP engine has been included to significantly through the X memory, AGU, which provides the enhance the core arithmetic capability and throughput. It appearance of a single, unified data space. The features a high-speed, 17-bit x 17-bit multiplier, a 40-bit Multiply-Accumulate (MAC) class of dual source DSP ALU, two 40-bit saturating accumulators and a 40-bit instructions operate through both the X and Y AGUs, bidirectional barrel shifter. Data in the accumulator, or splitting the data address space into two parts (see any working register, can be shifted up to 15 bits right, or Section3.2 “Data Address Space”). The X and Y 16 bits left in a single cycle. The DSP instructions oper- data space boundary is device-specific and cannot be ate seamlessly with all other instructions and have been altered by the user. Each data word consists of 2 bytes, designed for optimal real-time performance. The MAC and most instructions can address data either as words class of instructions can concurrently fetch two data or bytes. operands from memory while multiplying two W registers. To enable this concurrent fetching of data operands, the data space has been split for these instructions and linear is for all others. This has been achieved in a transparent and flexible manner by dedicating certain working registers to each address space for the MAC class of instructions.  2010 Microchip Technology Inc. DS70138G-page 15

dsPIC30F3014/4013 The core does not support a multi-stage instruction 2.2.1 SOFTWARE STACK POINTER/ pipeline. However, a single-stage instruction prefetch FRAME POINTER mechanism is used, which accesses and partially The dsPIC® DSC devices contain a software stack. decodes instructions a cycle ahead of execution, in W15 is the dedicated Software Stack Pointer (SP) and order to maximize available execution time. Most is automatically modified by exception processing and instructions execute in a single cycle with certain subroutine calls and returns. However, W15 can be ref- exceptions. erenced by any instruction in the same manner as all The core features a vectored exception processing other W registers. This simplifies the reading, writing structure for traps and interrupts, with 62 independent and manipulation of the Stack Pointer (e.g., creating vectors. The exceptions consist of up to 8 traps (of Stack Frames). which 4 are reserved) and 54 interrupts. Each interrupt Note: In order to protect against misaligned is prioritized based on a user-assigned priority between stack accesses, W15<0> is always clear. 1 and 7 (1 being the lowest priority and 7 being the highest), in conjunction with a predetermined ‘natural W15 is initialized to 0x0800 during a Reset. The user order’. Traps have fixed priorities ranging from 8 to 15. may reprogram the SP during initialization to any location within data space. 2.2 Programmer’s Model W14 has been dedicated as a Stack Frame Pointer, as The programmer’s model is shown in Figure2-1 and defined by the LNK and ULNK instructions. However, consists of 16 x 16-bit working registers (W0 through W14 can be referenced by any instruction in the same W15), 2 x 40-bit accumulators (AccA and AccB), manner as all other W registers. STATUS register (SR), Data Table Page register 2.2.2 STATUS REGISTER (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, The dsPIC DSC core has a 16-bit STATUS register DOEND, DCOUNT and RCOUNT) and Program Coun- (SR), the Least Significant Byte (LSB) of which is ter (PC). The working registers can act as data, referred to as the SR Low byte (SRL) and the Most address or offset registers. All registers are memory Significant Byte (MSB) as the SR High byte (SRH). See mapped. W0 acts as the W register for file register Figure 2-1 for SR layout. addressing. SRL contains all the MCU ALU operation status flags Some of these registers have a shadow register asso- (including the Z bit), as well as the CPU Interrupt Prior- ciated with each of them, as shown in Figure2-1. The ity Level Status bits, IPL<2:0> and the Repeat Active shadow register is used as a temporary holding register Status bit, RA. During exception processing, SRL is and can transfer its contents to or from its host register concatenated with the MSB of the PC to form a upon the occurrence of an event. None of the shadow complete word value which is then stacked. registers are accessible directly. The following rules The upper byte of the STATUS register contains the apply for transfer of registers into and out of shadows. DSP adder/subtracter Status bits, the DO Loop Active • PUSH.S and POP.S bit (DA) and the Digit Carry (DC) Status bit. W0, W1, W2, W3, SR (DC, N, OV, Z and C bits only) are transferred. 2.2.3 PROGRAM COUNTER • DO instruction The program counter is 23 bits wide; bit 0 is always DOSTART, DOEND, DCOUNT shadows are clear. Therefore, the PC can address up to 4M pushed on loop start and popped on loop end. instruction words. When a byte operation is performed on a working register, only the Least Significant Byte of the target register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes can be manipulated through byte-wide data memory space accesses. DS70138G-page 16  2010 Microchip Technology Inc.

dsPIC30F3014/4013 FIGURE 2-1: PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 DSP Operand W5 Registers W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP Offset W13/DSP Write-Back W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register AD39 AD31 AD15 AD0 DSP AccA Accumulators AccB PC22 PC0 0 Program Counter 7 0 TTBALBPPAAGG Data Table Page Address 7 0 PPSSVVPPAAGG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address 22 DOEND DO Loop End Address 15 0 CORCON Core Configuration Register OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRH SRL  2010 Microchip Technology Inc. DS70138G-page 17

dsPIC30F3014/4013 2.3 Divide Support The divide instructions must be executed within a REPEAT loop. Any other form of execution (e.g., a The dsPIC DSC devices feature a 16/16-bit signed series of discrete divide instructions) will not function fractional divide operation, as well as 32/16-bit and 16/ correctly because the instruction flow depends on 16-bit signed and unsigned integer divide operations, in RCOUNT. The divide instruction does not automatically the form of single instruction iterative divides. The set up the RCOUNT value and it must, therefore, be following instructions and data sizes are supported: explicitly and correctly specified in the REPEAT instruc- 1. DIVF – 16/16 signed fractional divide tion, as shown in Table2-1 (REPEAT will execute the 2. DIV.sd – 32/16 signed divide target instruction {operand value+1} times). The REPEAT loop count must be setup for 18 iterations of 3. DIV.ud – 32/16 unsigned divide the DIV/DIVF instruction. Thus, a complete divide 4. DIV.s – 16/16 signed divide operation requires 19 cycles. 5. DIV.u – 16/16 unsigned divide Note: The divide flow is interruptible. However, The 16/16 divides are similar to the 32/16 (same number the user needs to save the context as of iterations), but the dividend is either zero-extended or appropriate. sign-extended during the first iteration. TABLE 2-1: DIVIDE INSTRUCTIONS Instruction Function DIVF Signed fractional divide: Wm/Wn W0; Rem W1 DIV.sd Signed divide: (Wm+1:Wm)/Wn W0; Rem W1 DIV.s Signed divide: Wm/Wn W0; Rem W1 DIV.ud Unsigned divide: (Wm+1:Wm)/Wn W0; Rem W1 DIV.u Unsigned divide: Wm/Wn W0; Rem W1 DS70138G-page 18  2010 Microchip Technology Inc.

dsPIC30F3014/4013 2.4 DSP Engine The DSP engine has various options selected through various bits in the CPU Core Configuration register The DSP engine consists of a high-speed, 17-bit x (CORCON), as listed below: 17-bit multiplier, a barrel shifter and a 40-bit adder/ 1. Fractional or integer DSP multiply (IF). subtracter (with two target accumulators, round and saturation logic). 2. Signed or unsigned DSP multiply (US). 3. Conventional or convergent rounding (RND). The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, 4. Automatic saturation on/off for AccA (SATA). which require no additional data. These instructions are 5. Automatic saturation on/off for AccB (SATB). ADD, SUB and NEG. 6. Automatic saturation on/off for writes to data The dsPIC30F is a single-cycle instruction flow archi- memory (SATDW). tecture, therefore, concurrent operation of the DSP 7. Accumulator Saturation mode selection engine with MCU instruction flow is not possible. (ACCSAT). However, some MCU ALU and DSP engine resources Note: For CORCON layout, see Table3-3. may be used concurrently by the same instruction (e.g., ED, EDAC). (See Table2-2 for DSP instructions.) A block diagram of the DSP engine is shown in Figure2-2. TABLE 2-2: DSP INSTRUCTION SUMMARY Algebraic Instruction ACC WB? Operation CLR A = 0 Yes ED A = (x – y)2 No EDAC A = A + (x – y)2 No MAC A = A + (x * y) Yes MAC A = A + x2 No MOVSAC No change in A Yes MPY A = x * y No MPY.N A = – x * y No MSC A = A – x * y Yes  2010 Microchip Technology Inc. DS70138G-page 19

dsPIC30F3014/4013 FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM S a 40 40-Bit Accumulator A 40 Round t 16 40-Bit Accumulator B u Logic r a Carry/Borrow Out t Saturate e Adder Carry/Borrow In Negate 40 40 40 Barrel 16 Shifter 40 us B a at D Sign-Extend X s u B a 32 16 at Zero Backfill D Y 32 33 17-Bit Multiplier/Scaler 16 16 To/From W Array DS70138G-page 20  2010 Microchip Technology Inc.

dsPIC30F3014/4013 2.4.1 MULTIPLIER 2.4.2.1 Adder/Subtracter, Overflow and Saturation The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a The adder/subtracter is a 40-bit adder with an optional scaler to support either 1.31 fractional (Q31) or 32-bit zero input into one side and either true or complement integer results. Unsigned operands are zero-extended data into the other input. In the case of addition, the into the 17th bit of the multiplier input value. Signed carry/borrow input is active-high and the other input is operands are sign-extended into the 17th bit of the true data (not complemented), whereas in the case of multiplier input value. The output of the 17-bit x 17-bit subtraction, the carry/borrow input is active-low and the multiplier/scaler is a 33-bit value, which is sign- other input is complemented. The adder/subtracter extended to 40 bits. Integer data is inherently generates overflow Status bits, SA/SB and OA/OB, represented as a signed two’s complement value, which are latched and reflected in the STATUS register: where the MSB is defined as a sign bit. Generally • Overflow from bit 39: this is a catastrophic speaking, the range of an N-bit two’s complement inte- overflow in which the sign of the accumulator is ger is -2N-1 to 2N-1 – 1. For a 16-bit integer, the data destroyed. range is -32768 (0x8000) to 32767 (0x7FFF) including • Overflow into guard bits 32 through 39: this is a ‘0’. For a 32-bit integer, the data range is - recoverable overflow. This bit is set whenever all 2,147,483,648 (0x80000000) to 2,147,483,645 the guard bits are not identical to each other. (0x7FFF FFFF). The adder has an additional saturation block which When the multiplier is configured for fractional multipli- controls accumulator data saturation if selected. It uses cation, the data is represented as a two’s complement the result of the adder, the overflow Status bits fraction, where the MSB is defined as a sign bit and the described above, and the SATA/B (CORCON<7:6>) radix point is implied to lie just after the sign bit (QX for- and ACCSAT (CORCON<4>) mode control bits to mat). The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to (1 – 21-N). For a determine when and to what value to saturate. 16-bit fraction, the Q15 data range is -1.0 (0x8000) to Six STATUS register bits have been provided to 0.999969482 (0x7FFF) including ‘0’ and has a preci- support saturation and overflow. They are: sion of 3.01518x10-5. In Fractional mode, the 16x16 1. OA: multiply operation generates a 1.31 product, which has AccA overflowed into guard bits a precision of 4.65661 x 10-10. 2. OB: The same multiplier is used to support the MCU multi- AccB overflowed into guard bits ply instructions, which includes integer 16-bit signed, 3. SA: unsigned and mixed sign multiplies. AccA saturated (bit 31 overflow and saturation) The MUL instruction can be directed to use byte or or word-sized operands. Byte operands direct a 16-bit AccA overflowed into guard bits and saturated result, and word operands direct a 32-bit result to the (bit 39 overflow and saturation) specified register(s) in the W array. 4. SB: AccB saturated (bit 31 overflow and saturation) 2.4.2 DATA ACCUMULATORS AND or ADDER/SUBTRACTER AccB overflowed into guard bits and saturated The data accumulator consists of a 40-bit adder/ (bit 39 overflow and saturation) subtracter with automatic sign extension logic. It can 5. OAB: select one of two accumulators (A or B) as its pre- Logical OR of OA and OB accumulation source and post-accumulation 6. SAB: destination. For the ADD and LAC instructions, the data Logical OR of SA and SB to be accumulated or loaded can be optionally scaled The OA and OB bits are modified each time data via the barrel shifter prior to accumulation. passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the correspond- ing overflow trap flag enable bit (OVATE, OVBTE) in the INTCON1 register (refer to Section8.0 “Inter- rupts”) is set. This allows the user to take immediate action, for example, to correct system gain.  2010 Microchip Technology Inc. DS70138G-page 21

dsPIC30F3014/4013 The SA and SB bits are modified each time data 2.4.2.2 Accumulator ‘Write-Back’ passes through the adder/subtracter but can only be The MAC class of instructions (with the exception of cleared by the user. When set, they indicate that the MPY, MPY.N, ED and EDAC) can optionally write a accumulator has overflowed its maximum range (bit 31 rounded version of the high word (bits 31 through 16) for 32-bit saturation or bit 39 for 40-bit saturation) and of the accumulator that is not targeted by the instruction will be saturated if saturation is enabled. When into data space memory. The write is performed across saturation is not enabled, SA and SB default to bit 39 the X bus into combined X and Y address space. The overflow and, thus, indicate that a catastrophic over- following addressing modes are supported: flow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits generate an arithmetic 1. W13, Register Direct: warning trap when saturation is disabled. The rounded contents of the non-target accumulator are written into W13 as a The overflow and saturation Status bits can optionally 1.15fraction. be viewed in the STATUS register (SR) as the logical 2. [W13]+=2, Register Indirect with Post-Increment: OR of OA and OB (in bit OAB) and the logical OR of SA The rounded contents of the non-target accumu- and SB (in bit SAB). This allows programmers to check lator are written into the address pointed to by one bit in the STATUS register to determine if either W13 as a 1.15 fraction. W13 is then accumulator has overflowed, or one bit to determine if incremented by 2 (for a word write). either accumulator has saturated. This would be useful for complex number arithmetic which typically uses 2.4.2.3 Round Logic both the accumulators. The round logic is a combinational block which performs The device supports three saturation and overflow a conventional (biased) or convergent (unbiased) round modes: function during an accumulator write (store). The Round 1. Bit 39 Overflow and Saturation: mode is determined by the state of the RND bit in the When bit 39 overflow and saturation occurs, the CORCON register. It generates a 16-bit, 1.15 data value, saturation logic loads the maximally positive 9.31 which is passed to the data space write saturation logic. (0x7FFFFFFFFF), or maximally negative 9.31 If rounding is not indicated by the instruction, a truncated value (0x8000000000) into the target accumula- 1.15 data value is stored and the least significant word tor. The SA or SB bit is set and remains set until (lsw) is simply discarded. cleared by the user. This is referred to as ‘super Conventional rounding takes bit 15 of the accumulator, saturation’ and provides protection against erro- zero-extends it and adds it to the ACCxH word (bits 16 neous data or unexpected algorithm problems through 31 of the accumulator). If the ACCxL word (e.g., gain calculations). (bits0 through 15 of the accumulator) is between 2. Bit 31 Overflow and Saturation: 0x8000 and 0xFFFF (0x8000 included), ACCxH is When bit 31 overflow and saturation occurs, the incremented. If ACCxL is between 0x0000 and 0x7FFF, saturation logic then loads the maximally posi- ACCxH is left unchanged. A consequence of this algo- tive 1.31 value (0x007FFFFFFF), or maximally rithm is that over a succession of random rounding negative 1.31 value (0x0080000000) into the operations, the value tends to be biased slightly target accumulator. The SA or SB bit is set and positive. remains set until cleared by the user. When this Convergent (or unbiased) rounding operates in the Saturation mode is in effect, the guard bits are same manner as conventional rounding, except when not used, so the OA, OB or OAB bits are never ACCxL equals 0x8000. If this is the case, the Least Sig- set. nificant bit (LSb) (bit16 of the accumulator) of ACCxH 3. Bit 39 Catastrophic Overflow: is examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’, The bit 39 overflow Status bit from the adder is ACCxH is not modified. Assuming that bit 16 is used to set the SA or SB bit which remain set effectively random in nature, this scheme removes any until cleared by the user. No saturation operation rounding bias that may accumulate. is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in The SAC and SAC.R instructions store either a trun- the INTCON1 register is set, a catastrophic cated (SAC) or rounded (SAC.R) version of the contents overflow can initiate a trap exception. of the target accumulator to data memory via the X bus (subject to data saturation, see Section2.4.2.4 “Data Space Write Saturation”). Note that for the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. DS70138G-page 22  2010 Microchip Technology Inc.

dsPIC30F3014/4013 2.4.2.4 Data Space Write Saturation 2.4.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data The barrel shifter is capable of performing up to 16-bit space may also be saturated but without affecting the arithmetic or logic right shifts, or up to 16-bit left shifts contents of the source accumulator. The data space in a single cycle. The source can be either of the two write saturation logic block accepts a 16-bit, DSP accumulators, or the X bus (to support multi-bit 1.15fractional value from the round logic block as its shifts of register or memory data). input, together with overflow status from the original The shifter requires a signed binary value to determine source (accumulator) and the 16-bit round adder. both the magnitude (number of bits) and direction of the These are combined and used to select the appropriate shift operation. A positive value shifts the operand right. 1.15 fractional value as output to write to data space A negative value shifts the operand left. A value of ‘0’ memory. does not modify the operand. If the SATDW bit in the CORCON register is set, data The barrel shifter is 40 bits wide, thereby obtaining a (after rounding or truncation) is tested for overflow and 40-bit result for DSP shift operations and a 16-bit result adjusted accordingly. For input data greater than for MCU shift operations. Data from the X bus is 0x007FFF, data written to memory is forced to the presented to the barrel shifter between bit positions 16 maximum positive 1.15 value, 0x7FFF. For input data to 31 for right shifts, and bit positions 0 to 16 for left less than 0xFF8000, data written to memory is forced shifts. to the maximum negative 1.15 value, 0x8000. The Most Significant bit (MSb) of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions.  2010 Microchip Technology Inc. DS70138G-page 23

dsPIC30F3014/4013 NOTES: DS70138G-page 24  2010 Microchip Technology Inc.

dsPIC30F3014/4013 3.0 MEMORY ORGANIZATION User program space access is restricted to the lower 4M instruction word address range (0x000000 to Note: This data sheet summarizes features of 0x7FFFFE) for all accesses other than TBLRD/TBLWT, this group ofdsPIC30F devices and is not which use TBLPAG<7> to determine user or configura- intended to be a complete reference tion space access. In Table3-1, bit23 allows access to source. For more information on the CPU, the Device ID, the User ID and the Configuration bits; peripherals, register descriptions and otherwise, bit 23 is always clear. general device functionality, refer to the “dsPIC30F Family Reference Manual” FIGURE 3-2: dsPIC30F4013 PROGRAM (DS70046). For more information on the SPACE MEMORY MAP device instruction set and programming, refer to the “16-bit MCU and DSC Pro- Reset – GOTO Instruction 000000 grammer’s Reference Manual” Reset – Target Address 000002 (DS70157). 000004 Interrupt Vector Table s 3.1 Program Address Space 00007E able T The program address space is 4M instruction words. It Reserved 000080 or is addressable by a 24-bit value from either the 23-bit 000084 ect y V PC, table instruction Effective Address (EA) or data or Alternate Vector Table me space EA, when program space is mapped into data Meac 0000FE space as defined by Table3-1. Note that the program er Sp 000100 space address is incremented by two between succes- Us User Flash sive program words in order to provide compatibility Program Memory (16K instructions) with data space addressing. 007FFE 008000 FIGURE 3-1: dsPIC30F3014 PROGRAM Reserved (Read ‘0’s) SPACE MEMORY MAP 7FFBFE 7FFC00 Reset – GOTO Instruction 000000 Data EEPROM (1 Kbyte) Reset – Target Address 000002 000004 7FFFFE Interrupt Vector Table es 800000 00007E abl Reserved T Reserved 000080 or 8005BE ct 000084 Ve 8005C0 Alternate Vector Table ory UNITID (32 instr.) morye 00000001F00E Mem 88000056F00E User MeSpac P(8roKUg irsnaesmrt rF uMlcaetsimohnosr)y guration Space Reserved 003FFE nfi o F7FFFE 004000 C Reserved Device Configuration F80000 (Read ‘0’s) Registers F8000E 7FFBFE F80010 7FFC00 Data EEPROM Reserved (1 Kbyte) 7FFFFE FEFFFE 800000 DEVID (2) FF0000 FF0002 Reserved 8005BE 8005C0 ory UNITID (32 instr.) m 8005FE Me 800600 guration Space DeviceR Cesoenrfvigeudration FF780F0F0F0E nfi Registers F8000E o C F80010 Reserved FEFFFE FF0000 DEVID (2) FF0002  2010 Microchip Technology Inc. DS70138G-page 25

dsPIC30F3014/4013 TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (TBLPAG<7> = 0) TBLRD/TBLWT Configuration TBLPAG<7:0> Data EA<15:0> (TBLPAG<7> = 1) Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0> FIGURE 3-3: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 23 bits Using Program 0 Program Counter 0 Counter Select 1 EA Using Program 0 PSVPAG Reg Space Visibility 8 bits 15 bits EA Using 1/0 TBLPAG Reg Table Instruction 8 bits 16 bits User/ Configuration Byte 24-bit EA Space Select Select Note: Program space visibility cannot be used to access bits<23:16> of a word in program memory. DS70138G-page 26  2010 Microchip Technology Inc.

dsPIC30F3014/4013 3.1.1 DATA ACCESS FROM PROGRAM A set of table instructions are provided to move byte or MEMORY USING TABLE word-sized data to and from program space. (See INSTRUCTIONS Figure3-4 and Figure3-5.) This architecture fetches 24-bit wide program memory. 1. TBLRDL: Table Read Low Consequently, instructions are always aligned. Word: Read the lsw of the program address; However, as the architecture is modified Harvard, data P<15:0> maps to D<15:0>. can also be present in program space. Byte: Read one of the LSBs of the program address; There are two methods by which program space can P<7:0> maps to the destination byte when byte be accessed: via special table instructions, or through select = 0; the remapping of a 16K word program space page into P<15:8> maps to the destination byte when byte the upper half of data space (see Section3.1.2 “Data select = 1. Access from Program Memory Using Program 2. TBLWTL: Table Write Low (refer to Section5.0 Space Visibility”). The TBLRDL and TBLWTL instruc- “Flash Program Memory” for details on Flash tions offer a direct method of reading or writing the lsw programming) of any address within program space, without going through data space. The TBLRDH and TBLWTH instruc- 3. TBLRDH: Table Read High tions are the only method whereby the upper 8 bits of a Word: Read the most significant word (msw) of program space word can be accessed as data. the program address; P<23:16> maps to D<7:0>; D<15:8> will always be = 0. The PC is incremented by two for each successive Byte: Read one of the MSBs of the program 24-bit program word. This allows program memory address; addresses to directly map to data space addresses. P<23:16> maps to the destination byte when Program memory can thus be regarded as two 16-bit byte select = 0; word-wide address spaces, residing side by side, each The destination byte will always be = 0 when with the same address range. TBLRDL and TBLWTL byte select = 1. access the space which contains the least significant 4. TBLWTH: Table Write High (refer to Section5.0 data word, and TBLRDH and TBLWTH access the space “Flash Program Memory” for details on Flash which contains the MS Data Byte. Programming) Figure3-3 shows how the EA is created for table oper- ations and data space accesses (PSV = 1). Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word. FIGURE 3-4: PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD) PC Address 23 16 8 0 0x000000 00000000 0x000002 00000000 0x000004 00000000 0x000006 00000000 TBLRDL.B (Wn<0> = 0) TBLRDL.W Program Memory ‘Phantom’ Byte TBLRDL.B (Wn<0> = 1) (read as ‘0’)  2010 Microchip Technology Inc. DS70138G-page 27

dsPIC30F3014/4013 FIGURE 3-5: PROGRAM DATA TABLE ACCESS (MSB) TBLRDH.W PC Address 23 16 8 0 0x000000 00000000 0x000002 00000000 0x000004 00000000 0x000006 00000000 TBLRDH.B (Wn<0> = 0) Program Memory ‘Phantom’ Byte (read as ‘0’) TBLRDH.B (Wn<0> = 1) 3.1.2 DATA ACCESS FROM PROGRAM Note that by incrementing the PC by 2 for each MEMORY USING PROGRAM SPACE program memory word, the 15 LSbs of data space VISIBILITY addresses directly map to the 15 LSbs in the corre- sponding program space addresses. The remaining The upper 32 Kbytes of data space may optionally be bits are provided by the Program Space Visibility Page mapped into any 16K word program space page. This register, PSVPAG<7:0>, as shown in Figure3-6. provides transparent access of stored constant data from X data space without the need to use special Note: PSV access is temporarily disabled during instructions (i.e., TBLRDL/H, TBLWTL/H instructions). table reads/writes. Program space access through the data space occurs For instructions that use PSV which are executed if the MSb of the data space, EA, is set and program outside a REPEAT loop: space visibility is enabled by setting the PSV bit in the • The following instructions require one instruction Core Control register (CORCON). The functions of cycle in addition to the specified execution time: CORCON are discussed in Section2.4 “DSP - MAC class of instructions with data operand Engine”. prefetch Data accesses to this area add an additional cycle to - MOV instructions the instruction being executed, since two program - MOV.D instructions memory fetches are required. • All other instructions require two instruction cycles Note that the upper half of addressable data space is in addition to the specified execution time of the always part of the X data space. Therefore, when a instruction. DSP operation uses program space mapping to access this memory region, Y data space should typically con- For instructions that use PSV which are executed tain state (variable) data for DSP operations, whereas inside a REPEAT loop: X data space should typically contain coefficient • The following instances require two instruction (constant) data. cycles in addition to the specified execution time Although each data space address, 0x8000 and higher, of the instruction: maps directly into a corresponding program memory - Execution in the first iteration address (see Figure3-6), only the lower 16bits of the - Execution in the last iteration 24-bit program word are used to contain the data. The - Execution prior to exiting the loop due to an upper 8 bits should be programmed to force an illegal interrupt instruction to maintain machine robustness. Refer to - Execution upon re-entering the loop after an the “16-bit MCU and DSC Programmer’s Reference interrupt is serviced Manual” (DS70157) for details on instruction encoding. • Any other iteration of the REPEAT loop allows the instruction accessing data, using PSV, to execute in a single cycle. DS70138G-page 28  2010 Microchip Technology Inc.

dsPIC30F3014/4013 FIGURE 3-6: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space Program Space 0x0000 0x000100 15 PSVPAG(1) EA<15> = 0 0x00 8 Data 16 Space 0x8000 EA 15 23 15 0 Address EA<15> = 1 0x000200 15 Concatenation 23 Upper Half of Data Space is Mapped into Program Space 0xFFFF 0x007FFF BSET CORCON,#2 ; PSV bit set MOV #0x00, W0 ; Set PSVPAG register MOV W0, PSVPAG MOV 0x8200, W0 ; Access program memory location ; using a data space access Data Read Note: PSVPAG is an 8-bit register, containing bits<22:15> of the program space address (i.e., it defines the page in program space to which the upper half of data space is being mapped). The memory map shown here is for a dsPIC30F4013 device.  2010 Microchip Technology Inc. DS70138G-page 29

dsPIC30F3014/4013 3.2 Data Address Space When executing any instruction other than one of theMAC class of instructions, the X block consists of the The core has two data spaces. The data spaces can be 64-Kbyte data address space (including all Y addresses). considered either separate (for some DSP instructions), When executing one of the MAC class of instructions, the or as one unified linear address range (for MCU instruc- X block consists of the 64-Kbyte data address space tions). The data spaces are accessed using two Address excluding the Y address block (for data reads only). In Generation Units (AGUs) and separate data paths. other words, all other instructions regard the entire data memory as one composite address space. The MAC 3.2.1 DATA SPACE MEMORY MAP class instructions extract the Y address space from data The data space memory is split into two blocks, X and space and address it using EAs sourced from W10 and Y data space. A key element of this architecture is that W11. The remaining X data space is addressed using W8 Y space is a subset of X space, and is fully contained and W9. Both address spaces are concurrently accessed within X space. In order to provide an apparent Linear only with the MAC class instructions. Addressing space, X and Y spaces have contiguous The data space memory map is shown in Figure3-7. addresses. FIGURE 3-7: dsPIC30F3014/dsPIC30F4013 DATA SPACE MEMORY MAP LSB MSB 16 bits Address Address MSB LSB 0x0001 0x0000 2 Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 8 Kbyte X Data RAM (X) Near 2 Kbyte 0x0BFF 0x0BFE Data 0x0C01 0x0C00 Space SRAM Space Y Data RAM (Y) 0x0FFF 0x0FFE 0x1001 0x1000 0x1FFF 0x1FFE 0x8001 0x8000 Optionally X Data Mapped Unimplemented (X) into Program Memory 0xFFFF 0xFFFE DS70138G-page 30  2010 Microchip Technology Inc.

dsPIC30F3014/4013 FIGURE 3-8: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE SFR SPACE E C UNUSED A P S X (Y SPACE) Y SPACE UNUSED E C A P S X E C UNUSED A P S X Non-MAC Class Ops (Read/Write) MAC Class Ops (Read) MAC Class Ops (Write) Indirect EA using any W Indirect EA using W8, W9 Indirect EA using W10, W11  2010 Microchip Technology Inc. DS70138G-page 31

dsPIC30F3014/4013 3.2.2 DATA SPACES 3.2.3 DATA SPACE WIDTH The X data space is used by all instructions and sup- The core data width is 16 bits. All internal registers are ports all addressing modes. There are separate read organized as 16-bit wide words. Data space memory is and write data buses. The X read data bus is the return organized in byte addressable, 16-bit wide blocks. data path for all instructions that view data space as combined X and Y address space. It is also the X 3.2.4 DATA ALIGNMENT address space data path for the dual operand read To help maintain backward compatibility with PIC® instructions (MAC class). The X write data bus is the MCU devices and improve data space memory usage only write path to data space for all instructions. efficiency, the dsPIC30F instruction set supports both The X data space also supports Modulo Addressing for word and byte operations. Data is aligned in data mem- all instructions, subject to addressing mode restric- ory and registers as words, but all data space EAs tions. Bit-Reversed Addressing is only supported for resolve to bytes. Data byte reads read the complete writes to X data space. word which contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is The Y data space is used in concert with the X data placed onto the LSB of the X data path (no byte space by the MAC class of instructions (CLR, ED, accesses are possible from the Y data path as the MAC EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to class of instruction can only fetch words). That is, data provide two concurrent data read paths. No writes memory and registers are organized as two parallel occur across the Y bus. This class of instructions dedi- byte-wide entities with shared (word) address decode cates two W register pointers, W10 and W11, to always but separate write lines. Data byte writes only write to address Y data space, independent of X data space, the corresponding side of the array or register which whereas W8 and W9 always address X data space. matches the byte address. Note that during accumulator write-back, the data address space is considered a combination of X and Y As a consequence of this byte accessibility, all effective data spaces, so the write occurs across the X bus. address calculations (including those generated by the Consequently, the write can be to any address in the DSP operations which are restricted to word-sized entire data space. data) are internally scaled to step through word-aligned memory. For example, the core would recognize that The Y data space can only be used for the data Post-Modified Register Indirect Addressing mode prefetch operation associated with the MAC class of [Ws++] will result in a value of Ws + 1 for byte instructions. It also supports Modulo Addressing for operations and Ws + 2 for word operations. automated circular buffers. Of course, all other instruc- tions can access the Y data address space through the All word accesses must be aligned to an even address. X data path as part of the composite linear space. Misaligned word data fetches are not supported so care must be taken when mixing byte and word The boundary between the X and Y data spaces is operations, or translating from 8-bit MCU code. Should defined as shown in Figure3-7 and is not user- a misaligned read or write be attempted, an address programmable. Should an EA point to data outside its error trap is generated. If the error occurred on a read, own assigned address space, or to a location outside the instruction underway is completed, whereas if it physical memory, an all zero word/byte is returned. For occurred on a write, the instruction is executed but the example, although Y address space is visible by all write does not occur. In either case, a trap is then exe- non-MAC instructions using any addressing mode, an cuted, allowing the system and/or user to examine the attempt by a MAC instruction to fetch data from that machine state prior to execution of the address Fault. space using W8 or W9 (X Space Pointers) returns 0x0000. FIGURE 3-9: DATA ALIGNMENT TABLE 3-2: EFFECT OF INVALID MSB LSB 15 8 7 0 MEMORY ACCESSES 0001 Byte 1 Byte 0 0000 Attempted Operation Data Returned 0003 Byte 3 Byte 2 0002 EA = an unimplemented address 0x0000 W8 or W9 used to access Y data 0x0000 0005 Byte 5 Byte 4 0004 space in a MAC instruction W10 or W11 used to access X 0x0000 data space in a MAC instruction All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes or 32K words. DS70138G-page 32  2010 Microchip Technology Inc.

dsPIC30F3014/4013 All byte loads into any W register are loaded into the There is a Stack Pointer Limit register (SPLIM) associ- LSB. The MSB is not modified. ated with the Stack Pointer. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> A Sign-Extend (SE) instruction is provided to allow is forced to ‘0’ because all stack operations must be users to translate 8-bit signed data to 16-bit signed word-aligned. Whenever an Effective Address (EA) is values. Alternatively, for 16-bit unsigned data, users generated, using W15 as a source or destination can clear the MSB of any W register by executing a pointer, the address thus generated is compared with Zero-Extend (ZE) instruction on the appropriate the value in SPLIM. If the contents of the Stack Pointer address. (W15) and the SPLIM register are equal and a push Although most instructions are capable of operating on operation is performed, a stack error trap does not word or byte data sizes, it should be noted that some occur. The stack error trap occurs on a subsequent instructions, including the DSP instructions, operate push operation. Thus, for example, if it is desirable to only on words. cause a stack error trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the 3.2.5 NEAR DATA SPACE value, 0x1FFE. An 8-Kbyte ‘near’ data space is reserved in X address Similarly, a Stack Pointer underflow (stack error) trap is memory space between 0x0000 and 0x1FFF, which is generated when the Stack Pointer address is found to directly addressable via a 13-bit absolute address field be less than 0x0800, thus preventing the stack from within all memory direct instructions. The remaining X interfering with the Special Function Register (SFR) address space and all of the Y address space is space. addressable indirectly. Additionally, the whole of X data space is addressable using MOV instructions, which A write to the SPLIM register should not be immediately support memory direct addressing with a 16-bit followed by an indirect read operation using W15. address field. FIGURE 3-10: CALL STACK FRAME 3.2.6 SOFTWARE STACK 0x0000 15 0 The dsPIC DSC devices contain a software stack. W15 is used as the Stack Pointer. s The Stack Pointer always points to the first available d free word and grows from lower addresses towards waress higher addresses. It pre-decrements for stack pops s ToAddr andpost-increments for stack pushes as shown in ower PC<15:0> W15 (before CALL) Finisgtururect3io-n1,0 t.h Neo MteS tBh aotf ftohre a P PCC is p zuesrho -deuxrtienngd aendy b CeAfoLrLe ack GrHigh 0000<0F0r0ee0 0WPorCd<>22:16> W15 (after CALL) St the push, ensuring that the MSB is always clear. POP : [--W15] Note: A PC push during exception processing PUSH: [W15++] concatenates the SRL register to the MSB of the PC prior to the push.  2010 Microchip Technology Inc. DS70138G-page 33

D TABLE 3-3: CORE REGISTER MAP(1) d S 70 Address s 1 SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 3 (Home) P 8 G -p W0 0000 W0/WREG 0000 0000 0000 0000 I a C g W1 0002 W1 0000 0000 0000 0000 e 3 W2 0004 W2 0000 0000 0000 0000 3 4 W3 0006 W3 0000 0000 0000 0000 0 W4 0008 W4 0000 0000 0000 0000 F W5 000A W5 0000 0000 0000 0000 3 W6 000C W6 0000 0000 0000 0000 0 W7 000E W7 0000 0000 0000 0000 1 W8 0010 W8 0000 0000 0000 0000 4 W9 0012 W9 0000 0000 0000 0000 / W10 0014 W10 0000 0000 0000 0000 4 W11 0016 W11 0000 0000 0000 0000 0 W12 0018 W12 0000 0000 0000 0000 1 W13 001A W13 0000 0000 0000 0000 3 W14 001C W14 0000 0000 0000 0000 W15 001E W15 0000 1000 0000 0000 SPLIM 0020 SPLIM 0000 0000 0000 0000 ACCAL 0022 ACCAL 0000 0000 0000 0000 ACCAH 0024 ACCAH 0000 0000 0000 0000 ACCAU 0026 Sign Extension (ACCA<39>) ACCAU 0000 0000 0000 0000 ACCBL 0028 ACCBL 0000 0000 0000 0000 ACCBH 002A ACCBH 0000 0000 0000 0000 ACCBU 002C Sign Extension (ACCB<39>) ACCBU 0000 0000 0000 0000 PCL 002E PCL 0000 0000 0000 0000 PCH 0030 — — — — — — — — — PCH 0000 0000 0000 0000 TBLPAG 0032 — — — — — — — — TBLPAG 0000 0000 0000 0000  2 PSVPAG 0034 — — — — — — — — PSVPAG 0000 0000 0000 0000 01 RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu 0 M DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu icro DOSTARTL 003A DOSTARTL 0 uuuu uuuu uuuu uuu0 c h DOSTARTH 003C — — — — — — — — — DOSTARTH 0000 0000 0uuu uuuu ip T DOENDL 003E DOENDL 0 uuuu uuuu uuuu uuu0 e ch DOENDH 0040 — — — — — — — — — DOENDH 0000 0000 0uuu uuuu n o SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000 lo gy Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ In 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. c .

 TABLE 3-3: CORE REGISTER MAP(1) (CONTINUED) 2 010 SFR Name A(Hddormees)s Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State M icro CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000 ch MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000 ip T XMODSRT 0048 XS<15:1> 0 uuuu uuuu uuuu uuu0 e c XMODEND 004A XE<15:1> 1 uuuu uuuu uuuu uuu1 h n o YMODSRT 004C YS<15:1> 0 uuuu uuuu uuuu uuu0 lo g YMODEND 004E YE<15:1> 1 uuuu uuuu uuuu uuu1 y In XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu c . DISICNT 0052 — — DISICNT<13:0> 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. d s P I C 3 0 F 3 0 1 D S 4 7 0 / 13 4 8 G 0 -p a 1 g e 3 3 5

dsPIC30F3014/4013 NOTES: DS70138G-page 36  2010 Microchip Technology Inc.

dsPIC30F3014/4013 4.0 ADDRESS GENERATOR UNITS 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field Note: This data sheet summarizes features of (f) to directly address data present in the first this group ofdsPIC30F devices and is not 8192bytes of data memory (near data space). Most file intended to be a complete reference register instructions employ a working register, W0, source. For more information on the CPU, which is denoted as WREG in these instructions. The peripherals, register descriptions and destination is typically either the same file register or general device functionality, refer to the WREG (with the exception of the MUL instruction), “dsPIC30F Family Reference Manual” which writes the result to a register or register pair. The (DS70046). For more information on the MOV instruction allows additional flexibility and can device instruction set and programming, access the entire data space during file register refer to the “16-bit MCU and DSC Pro- operation. grammer’s Reference Manual” (DS70157). 4.1.2 MCU INSTRUCTIONS The dsPIC DSC core contains two independent The three-operand MCU instructions are of the form: address generator units: the X AGU and Y AGU. The Y Operand 3 = Operand 1 <function> Operand 2 AGU supports word-sized data reads for the DSP MAC class of instructions only. The dsPIC DSC AGUs where Operand 1 is always a working register (i.e., the support three types of data addressing: addressing mode can only be Register Direct), which is referred to as Wb. Operand 2 can be a W register, • Linear Addressing fetched from data memory or a 5-bit literal. The result • Modulo (Circular) Addressing location can be either a W register or an address • Bit-Reversed Addressing location. The following addressing modes are supported by MCU instructions: Linear and Modulo Data Addressing modes can be applied to data space or program space. Bit-Reversed • Register Direct Addressing is only applicable to data space addresses. • Register Indirect • Register Indirect Post-Modified 4.1 Instruction Addressing Modes • Register Indirect Pre-Modified The addressing modes in Table4-1 form the basis of • 5-bit or 10-bit Literal the addressing modes optimized to support the specific Note: Not all instructions support all the features of individual instructions. The addressing addressing modes given above. Individual modes provided in the MAC class of instructions are instructions may support different subsets somewhat different from those in the other instruction of these addressing modes. types. TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the File register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the EA. Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.  2010 Microchip Technology Inc. DS70138G-page 37

dsPIC30F3014/4013 4.1.3 MOVE AND ACCUMULATOR In summary, the following addressing modes are INSTRUCTIONS supported by the MAC class of instructions: Move instructions and the DSP accumulator class of • Register Indirect instructions provide a greater degree of addressing • Register Indirect Post-Modified by 2 flexibility than other instructions. In addition to the • Register Indirect Post-Modified by 4 addressing modes supported by most MCU instruc- • Register Indirect Post-Modified by 6 tions, move and accumulator instructions also support • Register Indirect with Register Offset (Indexed) Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. 4.1.5 OTHER INSTRUCTIONS Note: For the MOV instructions, the addressing Besides the various addressing modes outlined above, mode specified in the instruction can differ some instructions use literal constants of various sizes. for the source and destination EA. For example, BRA (branch) instructions use 16-bit However, the 4-bit Wb (register offset) signed literals to specify the branch destination directly, field is shared between both source and whereas the DISI instruction uses a 14-bit unsigned destination (but typically only used by literal field. In some instructions, such as ADD Acc, the one). source of an operand or result is implied by the opcode In summary, the following addressing modes are itself. Certain operations, such as NOP, do not have any supported by move and accumulator instructions: operands. • Register Direct 4.2 Modulo Addressing • Register Indirect • Register Indirect Post-Modified Modulo Addressing is a method of providing an automated means to support circular data buffers using • Register Indirect Pre-Modified hardware. The objective is to remove the need for • Register Indirect with Register Offset (Indexed) software to perform data address boundary checks • Register Indirect with Literal Offset when executing tightly looped code, as is typical in • 8-bit Literal many DSP algorithms. • 16-bit Literal Modulo Addressing can operate in either data or Note: Not all instructions support all the program space (since the data pointer mechanism is addressing modes given above. Individual essentially the same for both). One circular buffer can instructions may support different subsets be supported in each of the X (which also provides the of these addressing modes. pointers into program space) and Y data spaces. Modulo Addressing can operate on any W register 4.1.4 MAC INSTRUCTIONS pointer. However, it is not advisable to use W14 or W15 for Modulo Addressing since these two registers are The dual source operand DSP instructions (CLR, ED, used as the Stack Frame Pointer and Stack Pointer, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also respectively. referred to as MAC instructions, utilize a simplified set of addressing modes to allow the user to effectively In general, any particular circular buffer can only be manipulate the Data Pointers through register indirect configured to operate in one direction, as there are tables. certain restrictions on the buffer start address (for incre- menting buffers), or end address (for decrementing The two source operand prefetch registers must be a buffers) based upon the direction of the buffer. member of the set {W8, W9, W10, W11}. For data reads, W8 and W9 is always directed to the X RAGU, The only exception to the usage restrictions is for and W10 and W11 are always directed to the Y AGU. buffers that have a power-of-2 length. As these buffers The Effective Addresses generated (before and after satisfy the start and end address criteria, they may modification) must, therefore, be valid addresses within operate in a Bidirectional mode (i.e., address boundary X data space for W8 and W9 and Y data space for W10 checks are performed on both the lower and upper and W11. address boundaries). Note: Register Indirect with Register Offset addressing is only available for W9 (in X space) and W11 (in Y space). DS70138G-page 38  2010 Microchip Technology Inc.

dsPIC30F3014/4013 4.2.1 START AND END ADDRESS 4.2.2 W ADDRESS REGISTER SELECTION The Modulo Addressing scheme requires that a start- ing and an ending address be specified and loaded The Modulo and Bit-Reversed Addressing Control reg- intothe16-bit Modulo Buffer Address registers: ister MODCON<15:0> contains enable flags as well as XMODSRT, XMODEND, YMODSRT and YMODEND a W register field to specify the W address registers. (see Table3-3). The XWM and YWM fields select which registers oper- ate with Modulo Addressing. If XWM = 15, X RAGU Note: Y space Modulo Addressing EA calcula- and X WAGU Modulo Addressing is disabled. Similarly, tions assume word-sized data (LSb of if YWM = 15, Y AGU Modulo Addressing is disabled. every EA is always clear). The X Address Space Pointer W register (XWM), to The length of a circular buffer is not directly specified. It which Modulo Addressing is to be applied, is stored in is determined by the difference between the MODCON<3:0> (see Table3-3). Modulo Addressing is corresponding start and end addresses. The maximum enabled for X data space when XWM is set to any value possible length of the circular buffer is 32K words other than ‘15’ and the XMODEN bit is set at (64Kbytes). MODCON<15>. The Y Address Space Pointer W register (YWM), to which Modulo Addressing is to be applied, is stored in MODCON<7:4>. Modulo Addressing is enabled for Y data space when YWM is set to any value other than ‘15’ and the YMODEN bit is set at MODCON<14>. FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE Byte Address MOV #0x800,W0 MOV W0,XMODSRT ;set modulo start address MOV #0x863,W0 MOV W0,MODEND ;set modulo end address 0x0800 MOV #0x8001,W0 MOV W0,MODCON ;enable W1, X AGU for modulo MOV #0x0000,W0 ;W0 holds buffer fill value MOV #0x800,W1 ;point W1 to buffer DO AGAIN,#0x31 ;fill the 50 buffer locations MOV W0,[W1++] ;fill the next location AGAIN: INC W0,W0 ;increment the fill value 0x0863 Start Addr = 0x0800 End Addr = 0x0863 Length = 0x0032 words  2010 Microchip Technology Inc. DS70138G-page 39

dsPIC30F3014/4013 4.2.3 MODULO ADDRESSING If the length of a bit-reversed buffer is M = 2N bytes, APPLICABILITY then the last ‘N’ bits of the data buffer start address must be zeros. Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W XB<14:0> is the bit-reversed address modifier or ‘pivot register. It is important to realize that the address point’ which is typically a constant. In the case of an boundaries check for addresses less than or greater FFT computation, its value is equal to half of the FFT than the upper (for incrementing buffers) and lower (for data buffer size. decrementing buffers) boundary addresses (not just Note: All bit-reversed EA calculations assume equal to). Address changes may, therefore, jump word-sized data (LSb of every EA is beyond boundaries and still be adjusted correctly. always clear). The XB value is scaled Note: The modulo corrected effective address is accordingly to generate compatible (byte) written back to the register only when Pre- addresses. Modify or Post-Modify Addressing mode is When enabled, Bit-Reversed Addressing is only used to compute the effective address. executed for Register Indirect with Pre-Increment or When an address offset (e.g., [W7+W2]) Post-Increment Addressing and word-sized data is used, Modulo Addressing correction is writes. It does not function for any other addressing performed but the contents of the register mode or for byte sized data. Normal addresses are remain unchanged. generated instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the 4.3 Bit-Reversed Addressing address modifier (XB) and the offset associated with the Register Indirect Addressing mode is ignored. In Bit-Reversed Addressing is intended to simplify data addition, as word-sized data is a requirement, the LSb re-ordering for radix-2 FFT algorithms. It is supported of the EA is ignored (and always clear). by the X AGU for data writes only. Note: Modulo Addressing and Bit-Reversed The modifier, which may be a constant value or register Addressing should not be enabled contents, is regarded as having its bit order reversed. The together. In the event that the user address source and destination are kept in normal order. attempts to do this, Bit-Reversed Address- Thus, the only operand requiring reversal is the modifier. ing assumes priority when active for the X 4.3.1 BIT-REVERSED ADDRESSING WAGU, and X WAGU Modulo Addressing is disabled. However, Modulo Addressing IMPLEMENTATION continues to function in the X RAGU. Bit-Reversed Addressing is enabled when: If Bit-Reversed Addressing has already been enabled 1. BWM (W register selection) in the MODCON by setting the BREN (XBREV<15>) bit, then a write to register is any value other than ‘15’ (the stack the XBREV register should not be immediately followed cannot be accessed using Bit-Reversed by an indirect read operation using the W register that Addressing) and has been designated as the Bit-Reversed Pointer. 2. the BREN bit is set in the XBREV register and 3. the addressing mode used is Register Indirect with Pre-Increment or Post-Increment. FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer DS70138G-page 40  2010 Microchip Technology Inc.

dsPIC30F3014/4013 TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value 1024 0x0200 512 0x0100 256 0x0080 128 0x0040 64 0x0020 32 0x0010 16 0x0008 8 0x0004 4 0x0002 2 0x0001  2010 Microchip Technology Inc. DS70138G-page 41

dsPIC30F3014/4013 NOTES: DS70138G-page 42  2010 Microchip Technology Inc.

dsPIC30F3014/4013 5.0 FLASH PROGRAM MEMORY 5.2 Run-Time Self-Programming (RTSP) Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not RTSP is accomplished using TBLRD (table read) and intended to be a complete reference TBLWT (table write) instructions. source. For more information on the CPU, With RTSP, the user may erase program memory, peripherals, register descriptions and 32instructions (96 bytes) at a time and can write general device functionality, refer to the program memory data, 32 instructions (96 bytes) at a “dsPIC30F Family Reference Manual” time. (DS70046). For more information on the device instruction set and programming, 5.3 Table Instruction Operation refer to the “16-bit MCU and DSC Pro- Summary grammer’s Reference Manual” (DS70157). The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. The dsPIC30F family of devices contains internal TBLRDL and TBLWTL can access program memory in program Flash memory for executing user code. There Word or Byte mode. are two methods by which the user can program this memory: The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH 1. Run-Time Self-Programming (RTSP) and TBLWTH can access program memory in Word or 2. In-Circuit Serial Programming™ (ICSP™) Byte mode. A 24-bit program memory address is formed using 5.1 In-Circuit Serial Programming bits<7:0> of the TBLPAG register and the Effective (ICSP) Address (EA) from a W register specified in the table dsPIC30F devices can be serially programmed while in instruction, as shown in Figure5-1. the end application circuit. This is simply done with two lines for Programming Clock and Programming Data (which are named PGC and PGD, respectively), and three other lines for Power (VDD), Ground (VSS) and Master Clear (MCLR). This allows customers to manu- facture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. FIGURE 5-1: ADDRESSING FOR TABLE AND NVM REGISTERS 24 bits Using Program 0 Program Counter 0 Counter NVMADR Reg EA Using NVMADR 1/0 NVMADRU Reg Addressing 8 bits 16 bits Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 bits 16 bits Byte User/Configuration Select Space Select 24-bit EA  2010 Microchip Technology Inc. DS70138G-page 43

dsPIC30F3014/4013 5.4 RTSP Operation 5.5 Control Registers The dsPIC30F Flash program memory is organized The four SFRs used to read and write the program into rows and panels. Each row consists of 32 instruc- Flash memory are: tions or 96 bytes. Each panel consists of 128 rows or • NVMCON 4K x 24 instructions. RTSP allows the user to erase one • NVMADR row (32 instructions) at a time and to program four • NVMADRU instructions at one time. RTSP may be used to program multiple program memory panels, but the Table Pointer • NVMKEY must be changed at each panel boundary. 5.5.1 NVMCON REGISTER Each panel of program memory contains write latches that hold 32 instructions of programming data. Prior to The NVMCON register controls which blocks are to be the actual programming operation, the write data must erased, which memory type is to be programmed and be loaded into the panel write latches. The data to be the start of the programming cycle. programmed into the panel is loaded in sequential 5.5.2 NVMADR REGISTER order into the write latches; instruction 0, instruction 1, etc. The instruction words loaded must always be from The NVMADR register is used to hold the lower two a 32 address boundary. bytes of the Effective Address. The NVMADR register captures the EA<15:0> of the last table instruction that The basic sequence for RTSP programming is to set up has been executed and selects the row to write. a Table Pointer, then do a series of TBLWT instructions to load the write latches. Programming is performed by 5.5.3 NVMADRU REGISTER setting the special bits in the NVMCON register. 32TBLWTL and four TBLWTH instructions are The NVMADRU register is used to hold the upper byte required to load the 32 instructions. If multiple panel of the Effective Address. The NVMADRU register cap- programming is required, the Table Pointer needs to be tures the EA<23:16> of the last table instruction that changed and the next set of multiple write latches has been executed. written. 5.5.4 NVMKEY REGISTER All of the table write operations are single-word writes (2 instruction cycles), because only the table latches NVMKEY is a write-only register that is used for write are written. A programming cycle is required for protection. To start a programming or erase programming each row. sequence, the user must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section5.6 The Flash program memory is readable, writable and “Programming Operations” for further details. erasable during normal operation over the entire VDD range. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. DS70138G-page 44  2010 Microchip Technology Inc.

dsPIC30F3014/4013 5.6 Programming Operations 4. Write 32 instruction words of data from data RAM “image” into the program Flash write A complete programming sequence is necessary for latches. programming or erasing the internal Flash in RTSP 5. Program 32 instruction words into program mode. A programming operation is nominally 2 msec in Flash. duration and the processor stalls (waits) until the oper- a) Set up NVMCON register for multi-word, ation is finished. Setting the WR bit (NVMCON<15>) program Flash, program, and set WREN starts the operation and the WR bit is automatically bit. cleared when the operation is finished. b) Write 0x55 to NVMKEY. 5.6.1 PROGRAMMING ALGORITHM FOR c) Write 0xAA to NVMKEY. PROGRAM FLASH d) Set the WR bit. This begins program cycle. The user can erase or program one row of program e) CPU stalls for duration of the program cycle. Flash memory at a time. The general process is: f) The WR bit is cleared by the hardware 1. Read one row of program Flash (32 instruction when program cycle ends. words) and store into data RAM as a data 6. Repeat steps 1 through 5 as needed to program “image”. desired amount of program Flash memory. 2. Update the data image with the desired new 5.6.2 ERASING A ROW OF PROGRAM data. MEMORY 3. Erase program Flash row. a) Set up NVMCON register for multi-word, Example5-1 shows a code sequence that can be used program Flash, erase, and set WREN bit. to erase a row (32 instructions) of program memory. b) Write address of row to be erased into NVMADRU/NVMDR. c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. e) Set the WR bit. This begins erase cycle. f) CPU stalls for the duration of the erase cycle. g) The WR bit is cleared when erase cycle ends. EXAMPLE 5-1: ERASING A ROW OF PROGRAM MEMORY ; Setup NVMCON for erase operation, multi word write ; program memory selected, and writes enabled MOV #0x4041,W0 ; MOV W0 NVMCON ; Init NVMCON SFR , ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR),W0 ; MOV W0 NVMADRU ; Initialize PM Page Boundary SFR , MOV #tbloffset(PROG_ADDR),W0 ; Intialize in-page EA[15:0] pointer MOV W0, NVMADR ; Initialize NVMADR SFR DISI #5 ; Block all interrupts with priority <7 for ; next 5 instructions MOV #0x55,W0 MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted  2010 Microchip Technology Inc. DS70138G-page 45

dsPIC30F3014/4013 5.6.3 LOADING WRITE LATCHES 5.6.4 INITIATING THE PROGRAMMING SEQUENCE Example5-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. For protection, the write initiate sequence for NVMKEY 32TBLWTL and 32 TBLWTH instructions are needed to must be used to allow any erase or program operation load the write latches selected by the Table Pointer. to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs as shown in Example5-3. EXAMPLE 5-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000,W0 ; MOV W0 TBLPAG ; Initialize PM Page Boundary SFR , MOV #0x6000,W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0,W2 ; MOV #HIGH_BYTE_0,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , ; 1st_program_word MOV #LOW_WORD_1,W2 ; MOV #HIGH_BYTE_1,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , ; 2nd_program_word MOV #LOW_WORD_2,W2 ; MOV #HIGH_BYTE_2,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , • • • ; 31st_program_word MOV #LOW_WORD_31,W2 ; MOV #HIGH_BYTE_31,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , Note: In Example5-2, the contents of the upper byte of W3 has no effect. EXAMPLE 5-3: INITIATING A PROGRAMMING SEQUENCE DISI #5 ; Block all interrupts with priority <7 for ; next 5 instructions MOV #0x55,W0 ; MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted DS70138G-page 46  2010 Microchip Technology Inc.

 TABLE 5-1: NVM REGISTER MAP(1) 2 0 1 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0 M NVMCON 0760 WR WREN WRERR — — — — TWRI — PROGOP<6:0> 0000 0000 0000 0000 ic ro NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu c h ip NVMADRU 0764 — — — — — — — — NVMADR<23:16> 0000 0000 uuuu uuuu Te NVMKEY 0766 — — — — — — — — KEY<7:0> 0000 0000 0000 0000 c hn Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ o Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. lo g y In c . d s P I C 3 0 F 3 0 1 D S 4 7 0 / 13 4 8 G 0 -p a 1 g e 4 3 7

dsPIC30F3014/4013 NOTES: DS70138G-page 48  2010 Microchip Technology Inc.

dsPIC30F3014/4013 6.0 DATA EEPROM MEMORY A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- Note: This data sheet summarizes features of sible for waiting for the appropriate duration of time this group ofdsPIC30F devices and is not before initiating another data EEPROM write/erase intended to be a complete reference operation. Attempting to read the data EEPROM while source. For more information on the CPU, a programming or erase operation is in progress results peripherals, register descriptions and in unspecified data. general device functionality, refer to the Control bit, WR, initiates write operations similar to “dsPIC30F Family Reference Manual” program Flash writes. This bit cannot be cleared, only (DS70046). For more information on the set, in software. They are cleared in hardware at the device instruction set and programming, completion of the write operation. The inability to clear refer to the “16-bit MCU and DSC Pro- the WR bit in software prevents the accidental or grammer’s Reference Manual” premature termination of a write operation. (DS70157). The WREN bit, when set, allows a write operation. On The data EEPROM memory is readable and writable power-up, the WREN bit is clear. The WRERR bit is set during normal operation over the entire VDD range. The when a write operation is interrupted by a MCLR Reset data EEPROM memory is directly mapped in the or a WDT Time-out Reset during normal operation. In program memory address space. these situations, following Reset, the user can check the WRERR bit and rewrite the location. The address The four SFRs used to read and write the program register, NVMADR, remains unchanged. Flash memory are used to access data EEPROM memory as well. As described in Section5.5 “Control Note: Interrupt flag bit, NVMIF in the IFS0 regis- Registers”, these registers are: ter, is set when the write is complete. It • NVMCON must be cleared in software. • NVMADR 6.1 Reading the Data EEPROM • NVMADRU • NVMKEY A TBLRD instruction reads a word at the current The EEPROM data memory allows read and write of program word address. This example uses W0 as a single words and 16-word blocks. When interfacing to pointer to data EEPROM. The result is placed in data memory, NVMADR, in conjunction with the register W4 as shown in Example6-1. NVMADRU register, are used to address the EEPROM location being accessed. TBLRDL and EXAMPLE 6-1: DATA EEPROM READ TBLWTL instructions are used to read and write data MOV #LOW_ADDR_WORD,W0 ; Init Pointer EEPROM. The dsPIC30F devices have up to 8 Kbytes MOV #HIGH_ADDR_WORD,W1 (4K words) of data EEPROM with an address range MOV W1 TBLPAG from 0x7FF000 to 0x7FFFFE. , TBLRDL [ W0 ], W4 ; read data EEPROM A word write operation should be preceded by an erase of the corresponding memory location(s). The write typically requires 2 ms to complete, but the write time varies with voltage and temperature.  2010 Microchip Technology Inc. DS70138G-page 49

dsPIC30F3014/4013 6.2 Erasing Data EEPROM 6.2.2 ERASING A WORD OF DATA EEPROM 6.2.1 ERASING A BLOCK OF DATA The NVMADRU and NVMADR registers must point to EEPROM the block. Select a block of data Flash and set the WR In order to erase a block of data EEPROM, the and WREN bits in the NVMCON register. Setting the NVMADRU and NVMADR registers must initially point WR bit initiates the erase, as shown in Example6-3. to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM and set the WR and WREN bits in the NVMCON register. Setting the WR bit initiates the erase, as shown in Example6-2. EXAMPLE 6-2: DATA EEPROM BLOCK ERASE ; Select data EEPROM block, WR, WREN bits MOV #4045,W0 MOV W0 NVMCON ; Initialize NVMCON SFR , ; Start erase cycle by setting WR after writing key sequence DISI #5 ; Block all interrupts with priority <7 for ; next 5 instructions MOV #0x55,W0 ; MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Initiate erase sequence NOP NOP ; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete EXAMPLE 6-3: DATA EEPROM WORD ERASE ; Select data EEPROM word, WR, WREN bits MOV #4044,W0 MOV W0 NVMCON , ; Start erase cycle by setting WR after writing key sequence DISI #5 ; Block all interrupts with priority <7 for ; next 5 instructions MOV #0x55,W0 ; MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Initiate erase sequence NOP NOP ; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete DS70138G-page 50  2010 Microchip Technology Inc.

dsPIC30F3014/4013 6.3 Writing to the Data EEPROM The write does not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to To write an EEPROM data location, the following NVMCON, then set WR bit) for each word. It is strongly sequence must be followed: recommended that interrupts be disabled during this 1. Erase the data EEPROM word. codesegment. a) Select the word, data EEPROM erase and Additionally, the WREN bit in NVMCON must be set to set the WREN bit in the NVMCON register. enable writes. This mechanism prevents accidental b) Write the address of word to be erased into writes to data EEPROM due to unexpected code exe- NVMADR. cution. The WREN bit should be kept clear at all times except when updating the EEPROM. The WREN bit is c) Enable the NVM interrupt (optional). not cleared byhardware. d) Write 0x55 to NVMKEY. After a write sequence has been initiated, clearing the e) Write 0xAA to NVMKEY. WREN bit does not affect the current write cycle. The f) Set the WR bit. This begins the erase cycle. WR bit is inhibited from being set unless the WREN bit g) Either poll the NVMIF bit or wait for the is set. The WREN bit must be set on a previous instruc- NVMIF interrupt. tion. Both WR and WREN cannot be set with the same h) The WR bit is cleared when the erase cycle instruction. ends. At the completion of the write cycle, the WR bit is 2. Write the data word into data the EEPROM write cleared in hardware and the Nonvolatile Memory Write latches. Complete Interrupt Flag bit (NVMIF) is set. The user 3. Program 1 data word into the data EEPROM. may either enable this interrupt or poll this bit. NVMIF a) Select the word, data EEPROM program and must be cleared by software. set the WREN bit in the NVMCON register. 6.3.1 WRITING A WORD OF DATA b) Enable the NVM write done interrupt EEPROM (optional). c) Write 0x55 to NVMKEY. Once the user has erased the word to be programmed, d) Write 0xAA to NVMKEY. then a table write instruction is used to write one write latch, as shown in Example6-4. e) Set the WR bit. This begins the program cycle. 6.3.2 WRITING A BLOCK OF DATA f) Either poll the NVMIF bit or wait for the EEPROM NVM interrupt. To write a block of data EEPROM, write to all sixteen g) The WR bit is cleared when the write cycle latches first, then set the NVMCON register and ends. program the block, as shown in Example6-5. EXAMPLE 6-4: DATA EEPROM WORD WRITE ; Point to data memory MOV #LOW_ADDR_WORD,W0 ; Init pointer MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #LOW(WORD),W2 ; Get data TBLWTL W2 [ W0] ; Write data , ; The NVMADR captures last table access address ; Select data EEPROM for 1 word op MOV #0x4004,W0 MOV W0 NVMCON , ; Operate key to allow write operation DISI #5 ; Block all interrupts with priority <7 for ; next 5 instructions MOV #0x55,W0 MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Initiate program sequence NOP NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete  2010 Microchip Technology Inc. DS70138G-page 51

dsPIC30F3014/4013 EXAMPLE 6-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 ; Init pointer MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 ; Get 1st data TBLWTL W2 [ W0]++ ; write data , MOV #data2,W2 ; Get 2nd data TBLWTL W2 [ W0]++ ; write data , MOV #data3,W2 ; Get 3rd data TBLWTL W2 [ W0]++ ; write data , MOV #data4,W2 ; Get 4th data TBLWTL W2 [ W0]++ ; write data , MOV #data5,W2 ; Get 5th data TBLWTL W2 [ W0]++ ; write data , MOV #data6,W2 ; Get 6th data TBLWTL W2 [ W0]++ ; write data , MOV #data7,W2 ; Get 7th data TBLWTL W2 [ W0]++ ; write data , MOV #data8,W2 ; Get 8th data TBLWTL W2 [ W0]++ ; write data , MOV #data9,W2 ; Get 9th data TBLWTL W2 [ W0]++ ; write data , MOV #data10,W2 ; Get 10th data TBLWTL W2 [ W0]++ ; write data , MOV #data11,W2 ; Get 11th data TBLWTL W2 [ W0]++ ; write data , MOV #data12,W2 ; Get 12th data TBLWTL W2 [ W0]++ ; write data , MOV #data13,W2 ; Get 13th data TBLWTL W2 [ W0]++ ; write data , MOV #data14,W2 ; Get 14th data TBLWTL W2 [ W0]++ ; write data , MOV #data15,W2 ; Get 15th data TBLWTL W2 [ W0]++ ; write data , MOV #data16,W2 ; Get 16th data TBLWTL W2 [ W0]++ ; write data. The NVMADR captures last table access address. , MOV #0x400A,W0 ; Select data EEPROM for multi word op MOV W0 NVMCON ; Operate Key to allow program operation , DISI #5 ; Block all interrupts with priority <7 for ; next 5 instructions MOV #0x55,W0 MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Start write cycle NOP NOP 6.4 Write Verify 6.5 Protection Against Spurious Write Depending on the application, good programming There are conditions when the device may not want to practice may dictate that the value written to the mem- write to the data EEPROM memory. To protect against ory should be verified against the original value. This spurious EEPROM writes, various mechanisms have should be used in applications where excessive writes been built-in. On power-up, the WREN bit is cleared; can stress bits near the specification limit. also, the Power-up Timer prevents EEPROMwrite. The write initiate sequence, and the WREN bit together, help prevent an accidental write during brown-out, power glitch or software malfunction. DS70138G-page 52  2010 Microchip Technology Inc.

dsPIC30F3014/4013 7.0 I/O PORTS Reads from the latch (LATx), read the latch. Writes to the latch, write the latch (LATx). Reads from the port Note: This data sheet summarizes features of (PORTx), read the port pins and writes to the port pins, this group ofdsPIC30F devices and is not write the latch (LATx). intended to be a complete reference Any bit and its associated data and control registers source. For more information on the CPU, that are not valid for a particular device are disabled, peripherals, register descriptions and which means the corresponding LATx and TRISx general device functionality, refer to the registers and the port pin read as zeros. “dsPIC30F Family Reference Manual” (DS70046). When a pin is shared with another peripheral or func- tion that is defined as an input only, it is nevertheless All of the device pins (except VDD, VSS, MCLR and regarded as a dedicated port because there is no OSC1/CLKI) are shared between the peripherals and other competing source of outputs. An example is the the parallel I/O ports. INT4 pin. All I/O input ports feature Schmitt Trigger inputs for A Parallel I/O (PIO) port that shares a pin with a periph- improved noise immunity. eral is, in general, subservient to the peripheral. The peripheral’s output buffer data and control signals are 7.1 Parallel I/O (PIO) Ports provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port When a peripheral is enabled and the peripheral is has ownership of the output data and control signals of actively driving an associated pin, the use of the pin as the I/O pad cell. Figure7-2 shows how ports are shared a general purpose output pin is disabled. The I/O pin with other peripherals and the associated I/O cell (pad) can be read, but the output driver for the parallel port bit to which they are connected. Table7-1 shows the is disabled. If a peripheral is enabled but the peripheral formats of the registers for the shared ports, PORTB is not actively driving a pin, that pin can be driven by a through PORTF. port. Note: The actual bits in use vary between All port pins have three registers directly associated devices. with the operation of the port pin. The Data Direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. FIGURE 7-1: BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE Dedicated Port Module Read TRIS I/O Cell TRIS Latch Data Bus D Q WR TRIS CK Data Latch D Q I/O Pad WR LAT + CK WR PORT Read LAT Read PORT  2010 Microchip Technology Inc. DS70138G-page 53

dsPIC30F3014/4013 FIGURE 7-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Cell Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data 0 Read TRIS I/O Pad Data Bus D Q WR TRIS CK TRIS Latch D Q WR LAT + CK WR PORT Data Latch Read LAT Input Data Read PORT 7.2 Configuring Analog Port Pins 7.2.1 I/O PORT WRITE/READ TIMING The use of the ADPCFG and TRIS registers control the One instruction cycle is required between a port operation of the A/D port pins. The port pins that are direction change or port write operation and a read desired as analog inputs must have their correspond- operation of the same port. Typically, this instruction ing TRIS bit set (input). If the TRIS bit is cleared would be a NOP. (output), the digital output level (VOH or VOL) is converted. EXAMPLE 7-1: PORT WRITE/READ EXAMPLE When the PORT register is read, all pins configured as analog input channels are read as cleared (a low level). MOV 0xFF00, W0 ; Configure PORTB<15:8> Pins configured as digital inputs will not convert an ; as inputs analog input. Analog levels on any pin that is defined as MOV W0, TRISB ; and PORTB<7:0> as outputs NOP ; additional instruction a digital input (including the ANx pins) may cause the cycle input buffer to consume current that exceeds the BTSS PORTB, #11 ; bit test RB11 and skip if set device specifications. DS70138G-page 54  2010 Microchip Technology Inc.

 TABLE 7-1: dsPIC30F3014/4013 PORT REGISTER MAP(1) 2 0 1 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 0 M TRISA 02C0 — — — — TRISA11 — — — — — — — — — — — 0000 1000 0000 0000 ic ro PORTA 02C2 — — — — RA11 — — — — — — — — — — — 0000 0000 0000 0000 c h ip LATA 02C4 — — — — LATA11 — — — — — — — — — — — 0000 0000 0000 0000 Te TRISB 02C6 — — — TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0001 1111 1111 1111 c hn PORTB 02C8 — — — RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000 o lo LATB 02CB — — — LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000 g y In TRISC 02CC TRISC15 TRISC14 TRISC13 — — — — — — — — — — — — — 1110 0000 0000 0000 c PORTC 02CE RC15 RC14 RC13 — — — — — — — — — — — — — 0000 0000 0000 0000 . LATC 02D0 LATC15 LATC14 LATC13 — — — — — — — — — — — — — 0000 0000 0000 0000 TRISD 02D2 — — — — — — TRISD9 TRISD8 — — — — TRISD3 TRISD2 TRISD1 TRISD0 0000 0011 0000 1111 PORTD 02D4 — — — — — — RD9 RD8 — — — — RD3 RD2 RD1 RD0 0000 0000 0000 0000 LATD 02D6 — — — — — — LATD9 LATD8 — — — — LATD3 LATD2 LATD1 LATD0 0000 0000 0000 0000 TRISF 02DE — — — — — — — — — TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 0000 0000 0111 1111 PORTF 02E0 — — — — — — — — — RF6 RF5 RF4 RF3 RF2 RF1 RF0 0000 0000 0000 0000 LATF 02E2 — — — — — — — — — LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 0000 0000 0000 0000 Legend: — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. d s P I C 3 0 F 3 0 1 D S 4 7 0 / 13 4 8 G 0 -p a 1 g e 5 3 5

dsPIC30F3014/4013 7.3 Input Change Notification Module The input change notification module provides the dsPIC30F devices the ability to generate interrupt requests to the processor, in response to a Change-Of- State (COS) on selected input pins. This module is capable of detecting input Change-Of-States, even in Sleep mode, when the clocks are disabled. There are up to 10 external signals (CN0 through CN9, CN17 and CN18) that may be selected (enabled) for generating an interrupt request on a Change-Of-State. DS70138G-page 56  2010 Microchip Technology Inc.

 TABLE 7-2: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F3014/4013 DEVICES (BITS 15-0)(1) 2 0 10 M NSaFmRe Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State icro CNEN1 00C0 — — — — — — — — CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000 c h CNEN2 00C2 — — — — — — — — — — — — — CN18IE CN17IE — 0000 0000 0000 0000 ip T CNPU1 00C4 — — — — — — — — CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000 e ch CNPU2 00C6 — — — — — — — — — — — — — CN18PUE CN17PUE — 0000 0000 0000 0000 n o Legend: — = unimplemented bit, read as ‘0’ log Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. y In c . d s P I C 3 0 F 3 0 1 D S 4 7 0 / 13 4 8 G 0 -p a 1 g e 5 3 7

dsPIC30F3014/4013 NOTES: DS70138G-page 58  2010 Microchip Technology Inc.

dsPIC30F3014/4013 8.0 INTERRUPTS • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from Note: This data sheet summarizes features of these two registers. INTCON1 contains the con- this group ofdsPIC30F devices and is not trol and status flags for the processor exceptions. intended to be a complete reference The INTCON2 register controls the external source. For more information on the CPU, interrupt request signal behavior and the use of peripherals, register descriptions and the alternate vector table. general device functionality, refer to the Note: Interrupt flag bits get set when an interrupt “dsPIC30F Family Reference Manual” condition occurs, regardless of the state of (DS70046). For more information on the its corresponding enable bit. User soft- device instruction set and programming, ware should ensure the appropriate inter- refer to the “16-bit MCU and DSC Pro- rupt flag bits are clear prior to enabling an grammer’s Reference Manual” interrupt. (DS70157). All interrupt sources can be user-assigned to one of The dsPIC30F sensor and general purpose families 7priority levels, 1 through 7, via the IPCx registers. have up to 41 interrupt sources and 4 processor excep- Each interrupt source is associated with an interrupt tions (traps) which must be arbitrated based on a vector, as shown in Table8-1. Levels 7 and 1 represent priority scheme. the highest and lowest maskable priorities, The CPU is responsible for reading the Interrupt Vector respectively. Table (IVT) and transferring the address contained in Note: Assigning a priority level of ‘0’ to an inter- the interrupt vector to the program counter. The inter- rupt source is equivalent to disabling that rupt vector is transferred from the program data bus interrupt. into the program counter via a 24-bit wide multiplexer on the input of the program counter. If the NSTDIS bit (INTCON1<15>) is set, nesting of interrupts is prevented. Thus, if an interrupt is currently The Interrupt Vector Table (IVT) and Alternate Interrupt being serviced, processing of a new interrupt is pre- Vector Table (AIVT) are placed near the beginning of vented even if the new interrupt is of higher priority than program memory (0x000004). The IVT and AIVT are the one currently being serviced. shown in Figure8-1. Note: The IPL bits become read-only whenever The interrupt controller is responsible for pre- processing the interrupts and processor exceptions the NSTDIS bit has been set to ‘1’. prior to them being presented to the processor core. Certain interrupts have specialized control bits for The peripheral interrupts and traps are enabled, features like edge or level triggered interrupts, inter- prioritized and controlled using centralized Special rupt-on-change, etc. Control of these features remains Function Registers: within the peripheral module which generates the • IFS0<15:0>, IFS1<15:0>, IFS2<15:0> interrupt. All interrupt request flags are maintained in these The DISI instruction can be used to disable the three registers. The flags are set by their respec- processing of interrupts of priorities 6 and lower for a tive peripherals or external signals and they are certain number of instructions, during which the DISI bit cleared via software. (INTCON2<14>) remains set. • IEC0<15:0>, IEC1<15:0>, IEC2<15:0> When an interrupt is serviced, the PC is loaded with the All interrupt enable control bits are maintained in address stored in the vector location in program these three registers. These control bits are used memory that corresponds to the interrupt. There are to individually enable interrupts from the 63different vectors within the IVT (refer to Table8-1) peripherals or external signals. These vectors are contained in locations 0x000004 • IPC0<15:0>... IPC10<7:0> through 0x0000FE of program memory (refer to The user-assignable priority level associated with Table8-1). These locations contain 24-bit addresses. each of these 41 interrupts is held centrally in In order to preserve robustness, an address error trap these eleven registers. takes place should the PC attempt to fetch any of these • IPL<3:0> words during normal execution. This prevents execu- The current CPU priority level is explicitly stored tion of random data as a result of accidentally in the IPL bits. IPL<3> is present in the CORCON decrementing a PC into vector space, accidentally register, whereas IPL<2:0> are present in the mapping a data space address into vector space or the STATUS register (SR) in the processor core. PC rolling over to 0x000000 after reaching the end of implemented program memory space. Execution of a GOTO instruction to this vector space also generates an address error trap.  2010 Microchip Technology Inc. DS70138G-page 59

dsPIC30F3014/4013 8.1 Interrupt Priority TABLE 8-1: dsPIC30F3014 INTERRUPT VECTOR TABLE The user-assignable interrupt priority (IP<2:0>) bits for each individual interrupt source are located in the INT Vector Interrupt Source 3LSbs of each nibble within the IPCx register(s). Bit 3 Number Number of each nibble is not used and is read as a ‘0’. These Highest Natural Order Priority bits define the priority level assigned to a particular 0 8 INT0 – External Interrupt 0 interrupt by the user. 1 9 IC1 – Input Capture 1 Note: The user-assignable priority levels start at 2 10 OC1 – Output Compare 1 0 as the lowest priority and Level 7 as the highest priority. 3 11 T1 – Timer1 4 12 IC2 – Input Capture 2 Since more than one interrupt request source may be assigned to a specific user-assigned priority level, a 5 13 OC2 – Output Compare 2 means is provided to assign priority within a given level. 6 14 T2 – Timer2 This method is called “Natural Order Priority” and is 7 15 T3 – Timer3 final. 8 16 SPI1 Natural Order Priority is determined by the position of 9 17 U1RX – UART1 Receiver an interrupt in the vector table, and only affects interrupt operation when multiple interrupts with the 10 18 U1TX – UART1 Transmitter same user-assigned priority become pending at the 11 19 ADC – ADC Convert Done same time. 12 20 NVM – NVM Write Complete Table8-1 and Table8-2 list the interrupt numbers, 13 21 SI2C – I2C™ Slave Interrupt corresponding interrupt sources and associated vector 14 22 MI2C – I2C Master Interrupt numbers for the dsPIC30F3014 and dsPIC30F4013 devices, respectively. 15 23 Input Change Interrupt 16 24 INT1 – External Interrupt 1 Note1: The natural order priority scheme has 0 as the highest priority and 53 as the 17-22 25-30 Reserved lowest priority. 23 31 INT2 – External Interrupt 2 2: The natural order priority number is the 24 32 U2RX – UART2 Receiver same as the INT number. 25 33 U2TX – UART2 Transmitter The ability for the user to assign every interrupt to one 26 34 Reserved of seven priority levels means that the user can assign 27 35 C1 – Combined IRQ for CAN1 a very high overall priority level to an interrupt with a 28-41 36-49 Reserved low natural order priority. For example, the PLVD (Pro- grammable Low-Voltage Detect) can be given a priority 42 50 LVD – Low-Voltage Detect of 7. The INT0 (External Interrupt 0) may be assigned 43-53 51-61 Reserved to priority Level 1, thus giving it a very low effective Lowest Natural Order Priority priority. DS70138G-page 60  2010 Microchip Technology Inc.

dsPIC30F3014/4013 TABLE 8-2: dsPIC30F4013 INTERRUPT 8.2 Reset Sequence VECTOR TABLE A Reset is not a true exception because the interrupt Interrupt Vector controller is not involved in the Reset process. The pro- Interrupt Source Number Number cessor initializes its registers in response to a Reset which forces the PC to zero. The processor then begins Highest Natural Order Priority program execution at location 0x000000. A GOTO 0 8 INT0 – External Interrupt 0 instruction is stored in the first program memory loca- 1 9 IC1 – Input Capture 1 tion immediately followed by the address target for the 2 10 OC1 – Output Compare 1 GOTO instruction. The processor executes the GOTO to the specified address and then begins operation at the 3 11 T1 – Timer1 specified target (start) address. 4 12 IC2 – Input Capture 2 5 13 OC2 – Output Compare 2 8.2.1 RESET SOURCES 6 14 T2 V Timer2 In addition to external Reset and Power-on Reset (POR), these sources of error conditions ‘trap’ to the 7 15 T3 – Timer3 Reset vector: 8 16 SPI1 • Watchdog Time-out: 9 17 U1RX – UART1 Receiver The watchdog has timed out, indicating that the 10 18 U1TX – UART1 Transmitter processor is no longer executing the correct flow 11 19 ADC – ADC Convert Done of code. 12 20 NVM – NVM Write Complete • Uninitialized W Register Trap: 13 21 SI2C – I2C™ Slave Interrupt An attempt to use an uninitialized W register as an Address Pointer causes a Reset. 14 22 MI2C – I2C Master Interrupt • Illegal Instruction Trap: 15 23 Input Change Interrupt Attempted execution of any unused opcodes 16 24 INT1 – External Interrupt 1 results in an illegal instruction trap. Note that a 17 25 IC7 – Input Capture 7 fetch of an illegal instruction does not result in an illegal instruction trap if that instruction is flushed 18 26 IC8 – Input Capture 8 prior to execution due to a flow change. 19 27 OC3 – Output Compare 3 • Brown-out Reset (BOR): 20 28 OC4 – Output Compare 4 A momentary dip in the power supply to the 21 29 T4 – Timer4 device has been detected which may result in malfunction. 22 30 T5 – Timer5 • Trap Lockout: 23 31 INT2 – External Interrupt 2 Occurrence of multiple trap conditions 24 32 U2RX – UART2 Receiver simultaneously causes a Reset. 25 33 U2TX – UART2 Transmitter 26 34 Reserved 27 35 C1 – Combined IRQ for CAN1 28-40 36-48 Reserved 41 49 DCI – CODEC Transfer Done 42 50 LVD – Low-Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority  2010 Microchip Technology Inc. DS70138G-page 61

dsPIC30F3014/4013 8.3 Traps Address Error Trap: Traps can be considered as non-maskable interrupts, This trap is initiated when any of the following indicating a software or hardware error, which adhere circumstances occurs: to a predefined priority as shown in Figure8-1. They 1. A misaligned data word access is attempted. are intended to provide the user a means to correct 2. A data fetch from our unimplemented data erroneous operation during debug and when operating memory location is attempted. within the application. 3. A data access of an unimplemented program Note: If the user does not intend to take correc- memory location is attempted. tive action in the event of a trap error 4. An instruction fetch from vector space is condition, these vectors must be loaded attempted. with the address of a default handler that Note: In the MAC class of instructions, wherein simply contains the RESET instruction. If, the data space is split into X and Y data on the other hand, one of the vectors space, unimplemented X space includes containing an invalid address is called, an all of Y space, and unimplemented Y address error trap is generated. space includes all of X space. Note that many of these trap conditions can only be 5. Execution of a “BRA #literal” instruction or a detected when they occur. Consequently, the question- “GOTO #literal” instruction, where literal able instruction is allowed to complete prior to trap is an unimplemented program memory address. exception processing. If the user chooses to recover 6. Executing instructions after modifying the PC to from the error, the result of the erroneous action that point to unimplemented program memory caused the trap may have to be corrected. addresses. The PC may be modified by loading There are 8 fixed priority levels for traps: Level 8 a value into the stack and executing a RETURN through Level 15, which means that the IPL3 is always instruction. set during processing of a trap. Stack Error Trap: If the user is not currently executing a trap, and he sets the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all This trap is initiated under the following conditions: interrupts are disabled, but traps can still be processed. 1. The Stack Pointer is loaded with a value which 8.3.1 TRAP SOURCES is greater than the (user-programmable) limit value written into the SPLIM register (stack The following traps are provided with increasing prior- overflow). ity. However, since all traps can be nested, priority has 2. The Stack Pointer is loaded with a value which little effect. is less than 0x0800 (simple stack underflow). Math Error Trap: Oscillator Fail Trap: The math error trap executes under these This trap is initiated if the external oscillator fails and circumstances: operation becomes reliant on an internal RC backup. 1. Should an attempt be made to divide by zero, the divide operation aborts on a cycle boundary 8.3.2 HARD AND SOFT TRAPS and the trap is taken. It is possible that multiple traps can become active 2. If enabled, a math error trap is taken when an within the same cycle (e.g., a misaligned word stack arithmetic operation on either accumulator A or write to an overflowed address). In such a case, the B causes an overflow from bit 31 and the fixed priority shown in Figure8-2 is implemented, accumulator guard bits are not utilized. which may require the user to check if other traps are 3. If enabled, a math error trap is taken when an pending, in order to completely correct the Fault. arithmetic operation on either accumulator A or ‘Soft’ traps include exceptions of priority Level 8 B causes a catastrophic overflow from bit 39 and through Level 11, inclusive. The arithmetic error trap all saturation is disabled. (Level 11) falls into this category of traps. 4. If the shift amount specified in a shift instruction ‘Hard’ traps include exceptions of priority Level 12 is greater than the maximum allowed shift through Level 15, inclusive. The address error amount, a trap occurs. (Level12), stack error (Level 13) and oscillator error (Level 14) traps fall into this category. DS70138G-page 62  2010 Microchip Technology Inc.

dsPIC30F3014/4013 Each hard trap that occurs must be Acknowledged 8.4 Interrupt Sequence before code execution of any type may continue. If a All interrupt event flags are sampled in the beginning of lower priority hard trap occurs while a higher priority each instruction cycle by the IFSx registers. A pending trap is pending, Acknowledged, or is being processed, Interrupt Request (IRQ) is indicated by the flag bit a hard trap conflict occurs. being equal to a ‘1’ in an IFSx register. The IRQ causes The device is automatically Reset in a hard trap conflict an interrupt to occur if the corresponding bit in the Inter- condition. The TRAPR status bit (RCON<15>) is set rupt Enable (IECx) register is set. For the remainder of when the Reset occurs so that the condition may be the instruction cycle, the priorities of all pending detected in software. interrupt requests are evaluated. If there is a pending IRQ with a priority level greater FIGURE 8-1: TRAP VECTORS than the current processor priority level in the IPL bits, the processor is interrupted. Reset – GOTO Instruction 0x000000 The processor then stacks the current program counter Reset – GOTO Address 0x000002 Reserved 0x000004 and the low byte of the processor STATUS register (SRL), as shown in Figure8-2. The low byte of the Oscillator Fail Trap Vector STATUS register contains the processor priority level at Address Error Trap Vector the time prior to the beginning of the interrupt cycle. g Stack Error Trap Vector DecreasinPriority IVT MaRRthee sEseerrrrovvere ddT rVVaeepcc Vttooerrctor Tianlhlt eelor rwpurpeotr c inpetrsoiso otrhirte y tShineTtnAe rTrlUuopaStd srs e ugtnihsteitle trph. reTio hcriiosty ma cpletlievoteniol dnfi osora fb tthlheiess Reserved Vector Interrupt Service Routine. Interrupt 0 Vector 0x000014 Interrupt 1 Vector FIGURE 8-2: INTERRUPT STACK FRAME — — 0x0000 15 0 — Interrupt 52 Vector Interrupt 53 Vector 0x00007E ds Reserved 0x000080 warss Reserved 0x000082 Todre s d Reserved 0x000084 wA PC<15:0> W15 (before CALL) Oscillator Fail Trap Vector Groher SRL IPL3 PC<22:16> AIVT Stack Error Trap Vector ck Hig <Free Word> W15 (after CALL) Address Error Trap Vector Sta Math Error Trap Vector POP :[--W15] Reserved Vector PUSH:[W15++] Reserved Vector Reserved Vector Interrupt 0 Vector 0x000094 Interrupt 1 Vector Note1: The user can always lower the priority — level by writing a new value into SR. The — Interrupt Service Routine must clear the — interrupt flag bits in the IFSx register Interrupt 52 Vector before lowering the processor interrupt Interrupt 53 Vector 0x0000FE priority, in order to avoid recursive interrupts. 2: The IPL3 bit (CORCON<3>) is always clear when interrupts are being pro- cessed. It is set only during execution of traps. The RETFIE (return from interrupt) instruction unstacks the program counter and STATUS registers to return the processor to its state prior to the interrupt sequence.  2010 Microchip Technology Inc. DS70138G-page 63

dsPIC30F3014/4013 8.5 Alternate Vector Table 8.7 External Interrupt Requests In program memory, the Interrupt Vector Table (IVT) is The interrupt controller supports up to five external followed by the Alternate Interrupt Vector Table (AIVT), interrupt request signals, INT0-INT4. These inputs are as shown in Figure8-1. Access to the alternate vector edge sensitive; they require a low-to-high or a high-to- table is provided by the ALTIVT bit in the INTCON2 reg- low transition to generate an interrupt request. The ister. If the ALTIVT bit is set, all interrupt and exception INTCON2 register has three bits, INT0EP-INT2EP, that processes use the alternate vectors instead of the select the polarity of the edge detection circuitry. default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT sup- 8.8 Wake-up from Sleep and Idle ports emulation and debugging efforts by providing a means to switch between an application and a support The interrupt controller may be used to wake-up the environment without requiring the interrupt vectors to processor from either Sleep or Idle mode, if Sleep or be reprogrammed. This feature also enables switching Idle mode is active when the interrupt is generated. between applications for evaluation of different If an enabled interrupt request of sufficient priority is software algorithms at run time. received by the interrupt controller, then the standard If the AIVT is not required, the program memory interrupt request is presented to the processor. At the allocated to the AIVT may be used for other purposes. same time, the processor wakes up from Sleep or Idle AIVT is not a protected section and may be freely and begins execution of the Interrupt Service Routine programmed by the user. (ISR) needed to process the interrupt request. 8.6 Fast Context Saving A context saving option is available using shadow reg- isters. Shadow registers are provided for the DC, N, OV, Z and C bits in SR, and the registers, W0 through W3. The shadows are only one level deep. The shadow registers are accessible using the PUSH.S and POP.S instructions only. When the processor vectors to an interrupt, the PUSH.S instruction can be used to store the current value of the aforementioned registers into their respective shadow registers. If an ISR of a certain priority uses the PUSH.S and POP.S instructions for fast context saving, then a higher priority ISR should not include the same instruc- tions. Users must save the key registers in software during a lower priority interrupt if the higher priority ISR uses fast context saving. DS70138G-page 64  2010 Microchip Technology Inc.

 TABLE 8-3: dsPIC30F3014 INTERRUPT CONTROLLER REGISTER MAP(1) 2 0 10 M NSaFmRe ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State icro INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 0000 0000 0000 c h INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 0000 0000 0000 ip T IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000 e ch IFS1 0086 — — — — C1IF — U2TXIF U2RXIF INT2IF — — — — — — INT1IF 0000 0000 0000 0000 n o IFS2 0088 — — — — — LVDIF — — — — — — — — — — 0000 0000 0000 0000 lo gy IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000 In IEC1 008E — — — — C1IE — U2TXIE U2RXIE INT2IE — — — — — — INT1IE 0000 0000 0000 0000 c . IEC2 0090 — — — — — LVDIE — — — — — — — — — — 0000 0000 0000 0000 IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100 IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100 IPC2 0098 — ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100 IPC3 009A — CNIP<2:0> — MI2CIP<2:0> — SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100 IPC4 009C — — — — — — — — — — — — — INT1IP<2:0> 0100 0100 0100 0100 IPC5 009E — INT2IP<2:0> — — — — — — — — — — — — 0100 0100 0100 0100 IPC6 00A0 — C1IP<2:0> — — — — — U2TXIP<2:0> — U2RXIP<2:0> 0100 0100 0100 0100 IPC7 00A2 — — — — — — — — — — — — — — — — 0100 0100 0100 0100 IPC8 00A4 — — — — — — — — — — — — — — — — 0100 0100 0100 0100 IPC9 00A6 — — — — — — — — — — — — — — — — 0000 0100 0100 0100 IPC10 00A8 — — — — — LVDIP<2:0> — DCIIP<2:0> — — — — 0000 0100 0100 0000 d Legend: — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. s P I C 3 0 F 3 0 1 D S 4 7 0 / 13 4 8 G 0 -p a 1 g e 6 3 5

D TABLE 8-4: dsPIC30F4013 INTERRUPT CONTROLLER REGISTER MAP(1) d S 70 SFR s 1 ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 3 Name P 8 G -p INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 0000 0000 0000 I a C g INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 0000 0000 0000 e 6 IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000 3 6 IFS1 0086 — — — — C1IF — U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF 0000 0000 0000 0000 0 IFS2 0088 — — — — — LVDIF DCIIF — — — — — — — — — 0000 0000 0000 0000 F IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000 3 IEC1 008E — — — — C1IE — U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE 0000 0000 0000 0000 0 IEC2 0090 — — — — — LVDIE DCIIE — — — — — — — — — 0000 0000 0000 0000 1 IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100 4 IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100 / 4 IPC2 0098 — ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100 0 IPC3 009A — CNIP<2:0> — MI2CIP<2:0> — SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100 1 IPC4 009C — OC3IP<2:0> — IC8IP<2:0> — IC7IP<2:0> — INT1IP<2:0> 0100 0100 0100 0100 3 IPC5 009E — INT2IP<2:0> — T5IP<2:0> — T4IP<2:0> — OC4IP<2:0> 0100 0100 0100 0100 IPC6 00A0 — C1IP<2:0> — SPI2IP<2:0> — U2TXIP<2:0> — U2RXIP<2:0> 0100 0100 0100 0100 IPC7 00A2 — — — — — — — — — — — — — — — — 0100 0100 0100 0100 IPC8 00A4 — — — — — — — — — — — — — — — — 0100 0100 0100 0100 IPC9 00A6 — — — — — — — — — — — — — — — — 0000 0100 0100 0100 IPC10 00A8 — — — — — LVDIP<2:0> — DCIIP<2:0> — — — — 0000 0100 0100 0000 Legend: — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.  2 0 1 0 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F3014/4013 9.0 TIMER1 MODULE These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure9-1 Note: This data sheet summarizes features of presents a block diagram of the 16-bit timer module. this group ofdsPIC30F devices and is not 16-Bit Timer Mode: In the 16-Bit Timer mode, the intended to be a complete reference timer increments on every instruction cycle up to a source. For more information on the CPU, match value preloaded into the Period register, PR1, peripherals, register descriptions and then resets to ‘0’ and continues to count. general device functionality, refer to the “dsPIC30F Family Reference Manual” When the CPU goes into the Idle mode, the timer stops (DS70046). incrementing unless the TSIDL (T1CON<13>) bit=0. If TSIDL = 1, the timer module logic resumes the incre- This section describes the 16-bit general purpose menting sequence upon termination of the CPU Idle Timer1 module and associated operational modes. mode. Figure9-1 depicts the simplified block diagram of the 16-Bit Synchronous Counter Mode: In the 16-Bit 16-bit Timer1 module. Synchronous Counter mode, the timer increments on The following sections provide a detailed description the rising edge of the applied external clock signal including setup and control registers, along with which is synchronized with the internal phase clocks. associated block diagrams for the operational modes of The timer counts up to a match value preloaded in PR1, the timers. then resets to ‘0’ and continues. The Timer1 module is a 16-bit timer which can serve as When the CPU goes into the Idle mode, the timer stops the time counter for the Real-Time Clock (RTC), or incrementing unless the respective TSIDL bit = 0. If operate as a free-running interval timer/counter. The TSIDL = 1, the timer module logic resumes the incre- 16-bit timer has the following modes: menting sequence upon termination of the CPU Idle • 16-bit Timer mode. • 16-bit Synchronous Counter 16-Bit Asynchronous Counter Mode: In the 16-Bit • 16-bit Asynchronous Counter Asynchronous Counter mode, the timer increments on Further, the following operational characteristics are every rising edge of the applied external clock signal. supported: The timer counts up to a match value preloaded in PR1, • Timer gate operation then resets to ‘0’ and continues. • Selectable prescaler settings When the timer is configured for the Asynchronous • Timer operation during CPU Idle and Sleep mode of operation and the CPU goes into the Idle modes mode, the timer stops incrementing if TSIDL = 1. • Interrupt on 16-bit Period register match or falling edge of external gate signal FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM PR1 Equal Comparator x 16 TSYNC 1 Sync TMR1 Reset 0 0 T1IF Event Flag 1 Q D TGATE Q CK E T TGATE CS GA T T TCKPS<1:0> TON 2 SOSCO/ T1CK 1 x Gate Prescaler LPOSCEN Sync 0 1 1, 8, 64, 256 SOSCI TCY 0 0  2010 Microchip Technology Inc. DS70138G-page 67

dsPIC30F3014/4013 9.1 Timer Gate Operation Enabling an interrupt is accomplished via the respec- tive timer interrupt enable bit, T1IE. The timer interrupt The 16-bit timer can be placed in the Gated Time Accu- enable bit is located in the IEC0 Control register in the mulation mode. This mode allows the internal TCY to interrupt controller. increment the respective timer when the gate input sig- nal (T1CK pin) is asserted high. Control bit, TGATE 9.5 Real-Time Clock (T1CON<6>), must be set to enable this mode. The timer must be enabled (TON = 1) and the timer clock Timer1, when operating in Real-Time Clock (RTC) source set to internal (TCS = 0). mode, provides time of day and event time-stamping When the CPU goes into the Idle mode, the timer stops capabilities. Key operational features of the RTC are: incrementing unless TSIDL = 0. If TSIDL = 1, the timer • Operation from 32kHz LP oscillator resumes the incrementing sequence upon termination • 8-bit prescaler of the CPU Idle mode. • Low power • Real-Time Clock interrupts 9.2 Timer Prescaler These operating modes are determined by setting the The input clock (FOSC/4 or external clock) to the 16-bit appropriate bit(s) in the T1CON Control register. Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256, selected by control bits, TCKPS<1:0> (T1CON<5:4>). FIGURE 9-2: RECOMMENDED The prescaler counter is cleared when any of the COMPONENTS FOR following occurs: TIMER1 LP OSCILLATOR RTC • a write to the TMR1 register • a write to the T1CON register C1 • device Reset, such as POR and BOR SOSCI However, if the timer is disabled (TON = 0), then the timer prescaler cannot be reset since the prescaler 32.768 kHz dsPIC30FXXXX clock is halted. XTAL TMR1 is not cleared when T1CON is written. It is SOSCO cleared by writing to the TMR1 register. C2 R 9.3 Timer Operation During Sleep C1 = C2 = 18 pF; R = 100K Mode 9.5.1 RTC OSCILLATOR OPERATION During CPU Sleep mode, the timer operates if: When the TON = 1, TCS = 1 and TGATE = 0, the timer • The timer module is enabled (TON = 1) and increments on the rising edge of the 32 kHz LP oscilla- • The timer clock source is selected as external tor output signal, up to the value specified in the Period (TCS = 1) and register and is then reset to ‘0’. • The TSYNC bit (T1CON<2>) is asserted to a logic The TSYNC bit must be asserted to a logic ‘0’ ‘0’ which defines the external clock source as (Asynchronous mode) for correct operation. asynchronous. Enabling LPOSCEN (OSCCON<1>) disables the nor- When all three conditions are true, the timer continues mal Timer and Counter modes and enable a timer to count up to the Period register and is reset to carry-out wake-up event. 0x0000. When the CPU enters Sleep mode, the RTC continues When a match between the timer and the Period to operate, provided the 32kHz external crystal oscilla- register occurs, an interrupt can be generated if the tor is active and the control bits have not been respective timer interrupt enable bit is asserted. changed. The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. 9.4 Timer Interrupt 9.5.2 RTC INTERRUPTS The 16-bit timer has the ability to generate an interrupt- on-period match. When the timer count matches the When an interrupt event occurs, the respective interrupt Period register, the T1IF bit is asserted and an interrupt flag, T1IF, is asserted and an interrupt is generated, if is generated, if enabled. The T1IF bit must be cleared in enabled. The T1IF bit must be cleared in software. The software. The Timer Interrupt Flag, T1IF, is located in the respective Timer Interrupt Flag, T1IF, is located in the IFS0 Control register in the interrupt controller. IFS0 register in the interrupt controller. When the Gated Time Accumulation mode is enabled, Enabling an interrupt is accomplished via the respec- an interrupt is also generated on the falling edge of the tive timer interrupt enable bit, T1IE. The timer interrupt gate signal (at the end of the accumulation cycle). enable bit is located in the IEC0 Control register in the interrupt controller. DS70138G-page 68  2010 Microchip Technology Inc.

 TABLE 9-1: dsPIC30F3014/4013 TIMER1 REGISTER MAP(1) 2 0 1 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 0 M ic TMR1 0100 Timer1 Register uuuu uuuu uuuu uuuu ro PR1 0102 Period Register 1 1111 1111 1111 1111 c h ip T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 0000 0000 0000 T e Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ ch Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. n o lo g y In c . d s P I C 3 0 F 3 0 1 D S 4 7 0 / 13 4 8 G 0 -p a 1 g e 6 3 9

dsPIC30F3014/4013 NOTES: DS70138G-page 70  2010 Microchip Technology Inc.

dsPIC30F3014/4013 10.0 TIMER2/3 MODULE For 32-bit timer/counter operation, Timer2 is the lsw and Timer3 is the msw of the 32-bit timer. Note: This data sheet summarizes features of Note: For 32-bit timer operation, T3CON control this group ofdsPIC30F devices and is not bits are ignored. Only T2CON control bits intended to be a complete reference are used for setup and control. Timer2 source. For more information on the CPU, clock and gate inputs are utilized for the peripherals, register descriptions and 32-bit timer module, but an interrupt is general device functionality, refer to the generated with the Timer3 Interrupt Flag “dsPIC30F Family Reference Manual” (T3IF) and the interrupt is enabled with the (DS70046). Timer3 interrupt enable bit (T3IE). This section describes the 32-bit general purpose timer 16-Bit Timer Mode: In the 16-bit mode, Timer2 and module (Timer2/3) and associated operational modes. Timer3 can be configured as two independent 16-bit Figure10-1 depicts the simplified block diagram of the timers. Each timer can be set up in either 16-bit Timer 32-bit Timer2/3 module. Figure10-2 and Figure10-3 mode or 16-bit Synchronous Counter mode. See show Timer2/3 configured as two independent 16-bit Section9.0 “Timer1 Module” for details on these two timers, Timer2 and Timer3, respectively. operating modes. The Timer2/3 module is a 32-bit timer (which can be The only functional difference between Timer2 and configured as two 16-bit timers) with selectable Timer3 is that Timer2 provides synchronization of the operating modes. These timers are utilized by other clock prescaler output. This is useful for high-frequency peripheral modules, such as: external clock inputs. • Input Capture 32-Bit Timer Mode: In the 32-Bit Timer mode, the • Output Compare/Simple PWM timer increments on every instruction cycle, up to a The following sections provide a detailed description, match value preloaded into the combined 32-bit Period including setup and control registers, along with register, PR3/PR2, then resets to ‘0’ and continues to associated block diagrams for the operational modes of count. the timers. For synchronous 32-bit reads of the Timer2/Timer3 The 32-bit timer has the following modes: pair, reading the lsw (TMR2 register) causes the msw to be read and latched into a 16-bit holding register, • Two independent 16-bit timers (Timer2 and termed TMR3HLD. Timer3) with all 16-bit operating modes (except Asynchronous Counter mode) For synchronous 32-bit writes, the holding register (TMR3HLD) must first be written to. When followed by • Single 32-bit timer operation a write to the TMR2 register, the contents of TMR3HLD • Single 32-bit synchronous counter is transferred and latched into the MSB of the 32-bit Further, the following operational characteristics are timer (TMR3). supported: 32-Bit Synchronous Counter Mode: In the 32-Bit • ADC event trigger Synchronous Counter mode, the timer increments on • Timer gate operation the rising edge of the applied external clock signal • Selectable prescaler settings which is synchronized with the internal phase clocks. The timer counts up to a match value preloaded in the • Timer operation during Idle and Sleep modes combined 32-bit Period register, PR3/PR2, then resets • Interrupt on a 32-bit Period register match to ‘0’ and continues. These operating modes are determined by setting the When the timer is configured for the Synchronous appropriate bit(s) in the 16-bit T2CON and T3CON Counter mode of operation and the CPU goes into the SFRs. Idle mode, the timer stops incrementing unless the TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer module logic resumes the incrementing sequence upon termination of the CPU Idle mode.  2010 Microchip Technology Inc. DS70138G-page 71

dsPIC30F3014/4013 FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 16 Write TMR2 Read TMR2 16 Reset TMR3 TMR2 Sync MSB LSB ADC Event Trigger Comparator x 32 Equal PR3 PR2 0 T3IF Event Flag 1 Q D TGATE (T2CON<6>) Q CK TGATE (T2CON<6>) E S AT C G T T TCKPS<1:0> TON 2 T2CK 1 x Gate Prescaler Sync 0 1 1, 8, 64, 256 TCY 0 0 Note: Timer Configuration bit, T32 (T2CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70138G-page 72  2010 Microchip Technology Inc.

dsPIC30F3014/4013 FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM PR2 Equal Comparator x 16 TMR2 Sync Reset 0 T2IF Event Flag 1 Q D TGATE Q CK TGATE E SAT CG TT TCKPS<1:0> TON 2 T2CK 1 x Gate Prescaler Sync 0 1 1, 8, 64, 256 TCY 0 0 FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM PR3 ADC Event Trigger Equal Comparator x 16 TMR3 Reset 0 T3IF Event Flag 1 Q D TGATE Q CK TGATE E S AT C G T T TCKPS<1:0> TON 2 T3CK Sync 1 x Prescaler 0 1 1, 8, 64, 256 TCY 0 0 Note: T3CK pin does not exist on dsPIC30F3014/4013 devices. The block diagram shown here illustrates the schematic of Timer3 as implemented on the dsPIC30F6014 device.  2010 Microchip Technology Inc. DS70138G-page 73

dsPIC30F3014/4013 10.1 Timer Gate Operation 10.4 Timer Operation During Sleep Mode The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal TCY to During CPU Sleep mode, the timer does not operate increment the respective timer when the gate input because the internal clocks are disabled. signal (T2CK pin) is asserted high. Control bit, TGATE (T2CON<6>), must be set to enable this mode. When 10.5 Timer Interrupt in this mode, Timer2 is the originating clock source. The TGATE setting is ignored for Timer3. The timer The 32-bit timer module can generate an interrupt-on- must be enabled (TON = 1) and the timer clock source period match or on the falling edge of the external gate set to internal (TCS = 0). signal. When the 32-bit timer count matches the respective 32-bit Period register, or the falling edge of The falling edge of the external signal terminates the the external “gate” signal is detected, the T3IF bit count operation but does not reset the timer. The user (IFS0<7>) is asserted and an interrupt is generated, if must reset the timer in order to start counting from zero. enabled. In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be 10.2 ADC Event Trigger cleared in software. When a match occurs between the 32-bit timer (TMR3/ Enabling an interrupt is accomplished via the TMR2) and the 32-bit combined Period register (PR3/ respective timer interrupt enable bit, T3IE (IEC0<7>). PR2), a special ADC trigger event signal is generated by Timer3. 10.3 Timer Prescaler The input clock (FOSC/4 or external clock) to the timer has a prescale option of 1:1, 1:8, 1:64 and 1:256, selected by control bits, TCKPS<1:0> (T2CON<5:4> and T3CON<5:4>). For the 32-bit timer operation, the originating clock source is Timer2. The prescaler oper- ation for Timer3 is not applicable in this mode. The prescaler counter is cleared when any of the following occurs: • a write to the TMR2/TMR3 register • a write to the T2CON/T3CON register • device Reset, such as POR and BOR However, if the timer is disabled (TON = 0), then the Timer2 prescaler cannot be reset since the prescaler clock is halted. TMR2/TMR3 is not cleared when T2CON/T3CON is written. DS70138G-page 74  2010 Microchip Technology Inc.

 TABLE 10-1: dsPIC30F3014/4013 TIMER2/3 REGISTER MAP(1) 2 0 1 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 0 M TMR2 0106 Timer2 Register uuuu uuuu uuuu uuuu ic ro TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) uuuu uuuu uuuu uuuu c h ip TMR3 010A Timer3 Register uuuu uuuu uuuu uuuu Te PR2 010C Period Register 2 1111 1111 1111 1111 c hn PR3 010E Period Register 3 1111 1111 1111 1111 o lo T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 0000 0000 0000 g y In T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 0000 0000 0000 c Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ . Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. d s P I C 3 0 F 3 0 1 D S 4 7 0 / 13 4 8 G 0 -p a 1 g e 7 3 5

dsPIC30F3014/4013 NOTES: DS70138G-page 76  2010 Microchip Technology Inc.

dsPIC30F3014/4013 11.0 TIMER4/5 MODULE The Timer4/5 module is similar in operation to the Timer2/3 module. However, there are some Note: This data sheet summarizes features of differences: this group ofdsPIC30F devices and is not • The Timer4/5 module does not support the ADC intended to be a complete reference event trigger feature source. For more information on the CPU, • Timer4/5 can not be utilized by other peripheral peripherals, register descriptions and modules, such as input capture and output compare general device functionality, refer to the dsPIC30F Family Reference Manual The operating modes of the Timer4/5 module are deter- (DS70046). mined by setting the appropriate bit(s) in the 16-bit T4CON and T5CON SFRs. This section describes the second 32-bit general For 32-bit timer/counter operation, Timer4 is the lsw purpose timer module (Timer4/5) and associated and Timer5 is the msw of the 32-bit timer. operational modes. Figure11-1 depicts the simplified block diagram of the 32-bit Timer4/5 module. Note: For 32-bit timer operation, T5CON control Figure11-2 and Figure11-3 show Timer4/5 configured bits are ignored. Only T4CON control bits as two independent 16-bit timers, Timer4 and Timer5, are used for setup and control. Timer4 respectively. clock and gate inputs are utilized for the 32-bit timer module but an interrupt is generated with the Timer5 Interrupt Flag (T5IF) and the interrupt is enabled with the Timer5 interrupt enable bit (T5IE). FIGURE 11-1: 32-BIT TIMER4/5 BLOCK DIAGRAM Data Bus<15:0> TMR5HLD 16 16 Write TMR4 Read TMR4 16 Reset TMR5 TMR4 Sync MSB LSB Comparator x 32 Equal PR5 PR4 0 T5IF Event Flag 1 Q D TGATE (T4CON<6>) Q CK TGATE (T4CON<6>) E SAT CG TT TCKPS<1:0> TON 2 T4CK 1 x Prescaler Gate Sync 0 1 1, 8, 64, 256 TCY 0 0 Note: Timer Configuration bit, T32 (T4CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T4CON register.  2010 Microchip Technology Inc. DS70138G-page 77

dsPIC30F3014/4013 FIGURE 11-2: 16-BIT TIMER4 BLOCK DIAGRAM PR4 Equal Comparator x 16 TMR4 Sync Reset 0 T4IF Event Flag 1 Q D TGATE Q CK TGATE E S AT C G T T TCKPS<1:0> TON 2 T4CK 1 x Gate Prescaler Sync 0 1 1, 8, 64, 256 TCY 0 0 FIGURE 11-3: 16-BIT TIMER5 BLOCK DIAGRAM PR5 ADC Event Trigger Equal Comparator x 16 TMR5 Reset 0 T5IF Event Flag 1 Q D TGATE Q CK TGATE E T S A C G T T TCKPS<1:0> TON 2 T5CK Sync 1 x Prescaler 0 1 1, 8, 64, 256 TCY 0 0 Note: In the dsPIC30F3014 device, there is no T5CK pin. Therefore, in this device the following modes should not be used for Timer5: 2: TCS = 1 (16-bit counter) 3: TCS = 0, TGATE = 1 (gated time accumulation) DS70138G-page 78  2010 Microchip Technology Inc.

 TABLE 11-1: dsPIC30F4013 TIMER4/5 REGISTER MAP(1) 2 0 1 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 0 M TMR4 0114 Timer4 Register uuuu uuuu uuuu uuuu ic ro TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) uuuu uuuu uuuu uuuu c h ip TMR5 0118 Timer5 Register uuuu uuuu uuuu uuuu Te PR4 011A Period Register 4 1111 1111 1111 1111 c hn PR5 011C Period Register 5 1111 1111 1111 1111 o lo T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 0000 0000 0000 g y In T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 0000 0000 0000 c Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ . Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. d s P I C 3 0 F 3 0 1 D S 4 7 0 / 13 4 8 G 0 -p a 1 g e 7 3 9

dsPIC30F3014/4013 NOTES: DS70138G-page 80  2010 Microchip Technology Inc.

dsPIC30F3014/4013 12.0 INPUT CAPTURE MODULE These operating modes are determined by setting the appropriate bits in the ICxCON register (where Note: This data sheet summarizes features of x=1,2,...,N). The dsPIC DSC devices contain up to 8 this group ofdsPIC30F devices and is not capture channels (i.e., the maximum value of N is 8). intended to be a complete reference The dsPIC30F3014 device contains 2 capture source. For more information on the CPU, channels while the dsPIC30F4013 device contains peripherals, register descriptions and 4capture channels. general device functionality, refer to the “dsPIC30F Family Reference Manual” 12.1 Simple Capture Event Mode (DS70046). The simple capture events in the dsPIC30F product This section describes the input capture module and family are: associated operational modes. The features provided • Capture every falling edge by this module are useful in applications requiring fre- • Capture every rising edge quency (period) and pulse measurement. Figure12-1 depicts a block diagram of the input capture module. • Capture every 4th rising edge Input capture is useful for such modes as: • Capture every 16th rising edge • Frequency/Period/Pulse Measurements • Capture every rising and falling edge • Additional Sources of External Interrupts These simple Input Capture modes are configured by setting the appropriate bits, ICM<2:0> (ICxCON<2:0>). The key operational features of the input capture module are: 12.1.1 CAPTURE PRESCALER • Simple Capture Event mode There are four input capture prescaler settings speci- • Timer2 and Timer3 mode selection fied by bits, ICM<2:0> (ICxCON<2:0>). Whenever the • Interrupt on input capture event capture channel is turned off, the prescaler counter is cleared. In addition, any Reset clears the prescaler counter. FIGURE 12-1: INPUT CAPTURE MODE BLOCK DIAGRAM From GP Timer Module T2_CNT T3_CNT 16 16 ICTMR ICx pin 1 0 Prescaler Clock Edge FIFO 1, 4, 16 Synchronizer Detection R/W Logic Logic 3 ICM<2:0> ICxBUF Mode Select ICBNE, ICOV ICI<1:0> Interrupt ICxCON Logic Data Bus SSeett FFllaagg IICCxxIIFF Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels, 1 through N.  2010 Microchip Technology Inc. DS70138G-page 81

dsPIC30F3014/4013 12.1.2 CAPTURE BUFFER OPERATION 12.2 Input Capture Operation During Sleep and Idle Modes Each capture channel has an associated FIFO buffer which is four 16-bit words deep. There are two status An input capture event generates a device wake-up or flags which provide status on the FIFO buffer: interrupt, if enabled, if the device is in CPU Idle or Sleep • ICBNE – Input Capture Buffer Not Empty mode. • ICOV – Input Capture Overflow Independent of the timer being enabled, the input cap- The ICBFNE is set on the first input capture event and ture module wakes up from the CPU Sleep or Idle mode remain set until all capture events have been read from when a capture event occurs if ICM<2:0> = 111 and the the FIFO. As each word is read from the FIFO, the interrupt enable bit is asserted. The same wake-up can remaining words are advanced by one position within generate an interrupt if the conditions for processing the the buffer. interrupt have been satisfied. The wake-up feature is useful as a method of adding extra external pin In the event that the FIFO is full with four capture interrupts. events and a fifth capture event occurs prior to a read of the FIFO, an overflow condition occurs and the ICOV 12.2.1 INPUT CAPTURE IN CPU SLEEP bit is set to a logic ‘1’. The fifth capture event is lost and MODE is not stored in the FIFO. No additional events are captured until all four events have been read from the CPU Sleep mode allows input capture module opera- buffer. tion with reduced functionality. In the CPU Sleep mode, the ICI<1:0> bits are not applicable and the input cap- If a FIFO read is performed after the last read and no ture module can only function as an external interrupt new capture event has been received, the read will source. yield indeterminate results. The capture module must be configured for interrupt 12.1.3 TIMER2 AND TIMER3 SELECTION only on rising edge (ICM<2:0> = 111) in order for the MODE input capture module to be used while the device is in Sleep mode. The prescale settings of 4:1 or 16:1 are The input capture module consists of up to 8 input cap- not applicable in this mode. ture channels. Each channel can select between one of two timers for the time base, Timer2 or Timer3. 12.2.2 INPUT CAPTURE IN CPU IDLE Selection of the timer resource is accomplished MODE through SFR bit, ICTMR (ICxCON<7>). Timer3 is the CPU Idle mode allows input capture module operation default timer resource available for the input capture with full functionality. In the CPU Idle mode, the Inter- module. rupt mode selected by the ICI<1:0> bits is applicable, 12.1.4 HALL SENSOR MODE as well as the 4:1 and 16:1 capture prescale settings which are defined by control bits, ICM<2:0>. This mode When the input capture module is set for capture on requires the selected timer to be enabled. Moreover, every edge, rising and falling, ICM<2:0> = 001, the the ICSIDL bit must be asserted to a logic ‘0’. following operations are performed by the input capture If the input capture module is defined as logic: ICM<2:0>=111 in CPU Idle mode, the input capture • The input capture interrupt flag is set on every pin serves only as an external interrupt pin. edge, rising and falling. • The interrupt on Capture mode setting bits, 12.3 Input Capture Interrupts ICI<1:0>, is ignored since every capture generates an interrupt. The input capture channels have the ability to generate an interrupt based upon the selected number of • A capture overflow condition is not generated in capture events. The selection number is set by control this mode. bits, ICI<1:0> (ICxCON<6:5>). Each channel provides an interrupt flag (ICxIF) bit. The respective capture channel interrupt flag is located in the corresponding IFSx register. Enabling an interrupt is accomplished via the respec- tive Input Capture Channel Interrupt Enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC Control register. DS70138G-page 82  2010 Microchip Technology Inc.

 TABLE 12-1: dsPIC30F3014 INPUT CAPTURE REGISTER MAP(1) 2 0 1 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 0 M IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu ic ro IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 c h ip IC2BUF 0144 Input 2 Capture Register uuuu uuuu uuuu uuuu Te IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 c hn Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ o Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. lo g y In TABLE 12-2: dsPIC30F4013 INPUT CAPTURE REGISTER MAP(1) c . SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 IC2BUF 0144 Input 2 Capture Register uuuu uuuu uuuu uuuu IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 IC7BUF 0158 Input 7 Capture Register uuuu uuuu uuuu uuuu IC7CON 015A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 IC8BUF 015C Input 8 Capture Register uuuu uuuu uuuu uuuu IC8CON 015E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. d s P I C 3 0 F 3 0 1 D S 4 7 0 / 13 4 8 G 0 -p a 1 g e 8 3 3

dsPIC30F3014/4013 NOTES: DS70138G-page 84  2010 Microchip Technology Inc.

dsPIC30F3014/4013 13.0 OUTPUT COMPARE MODULE These operating modes are determined by setting the appropriate bits in the 16-bit OCxCON SFR (where Note: This data sheet summarizes features of x=1,2,3,...,N). The dsPIC DSC devices contain up to this group ofdsPIC30F devices and is not 8 compare channels (i.e., the maximum value of N is 8). intended to be a complete reference The dsPIC30F3014 device contains 2 compare source. For more information on the CPU, channels while the dsPIC30F4013 device contains peripherals, register descriptions and 4compare channels. general device functionality, refer to the OCxRS and OCxR in Figure13-1 represent the Dual “dsPIC30F Family Reference Manual” Compare registers. In the Dual Compare mode, the (DS70046). OCxR register is used for the first compare and OCxRS is used for the second compare. This section describes the output compare module and associated operational modes. The features provided 13.1 Timer2 and Timer3 Selection Mode by this module are useful in applications requiring operational modes, such as: Each output compare channel can select between one • Generation of Variable Width Output Pulses of two 16-bit timers: Timer2 or Timer3. • Power Factor Correction The selection of the timers is controlled by the OCTSEL Figure13-1 depicts a block diagram of the output bit (OCxCON<3>). Timer2 is the default timer resource compare module. for the output compare module. The key operational features of the output compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • Dual Output Compare Match mode • Simple PWM mode • Output Compare During Sleep and Idle modes • Interrupt on Output Compare/PWM Event FIGURE 13-1: OUTPUT COMPARE MODE BLOCK DIAGRAM Set Flag bit OCxIF OCxRS OCxR Output S Q Logic R OCx Output 3 Enable OCM<2:0> Mode Select Comparator OCTSEL OCFA 0 1 0 1 (for x = 1, 2, 3 or 4) or OCFB (for x = 5, 6, 7 or 8) From GP Timer Module TMR2<15:0 TMR3<15:0> T2P2_MATCH T3P3_MATCH Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels, 1 through N.  2010 Microchip Technology Inc. DS70138G-page 85

dsPIC30F3014/4013 13.2 Simple Output Compare Match 13.3.2 CONTINUOUS PULSE MODE Mode For the user to configure the module for the generation of a continuous stream of output pulses, the following When control bits, OCM<2:0> (OCxCON<2:0>) = 001, steps are required: 010 or 011, the selected output compare channel is configured for one of three simple Output Compare • Determine instruction cycle time, TCY. Match modes: • Calculate desired pulse value based on TCY. • Compare forces I/O pin low • Calculate timer to Start pulse width from timer • Compare forces I/O pin high start value of 0x0000. • Compare toggles I/O pin • Write pulse-width Start and Stop times into OCxR and OCxRS (x denotes channel 1, 2, ...,N) The OCxR register is used in these modes. The OCxR Compare registers, respectively. register is loaded with a value and is compared to the • Set Timer Period register to value equal to or selected incrementing timer count. When a compare greater than value in OCxRS Compare register. occurs, one of these Compare Match modes occurs. If the counter resets to zero before reaching the value in • Set OCM<2:0> = 101. OCxR, the state of the OCx pin remains unchanged. • Enable timer, TON (TxCON<15>) = 1. 13.3 Dual Output Compare Match Mode 13.4 Simple PWM Mode When control bits, OCM<2:0> (OCxCON<2:0>) = 100 When control bits, OCM<2:0> (OCxCON<2:0>) = 110 or 101, the selected output compare channel is config- or 111, the selected output compare channel is config- ured for one of two Dual Output Compare modes, ured for the PWM mode of operation. When configured which are: for the PWM mode of operation, OCxR is the main latch (read-only) and OCxRS is the secondary latch. This • Single Output Pulse mode enables glitchless PWM transitions. • Continuous Output Pulse mode The user must perform the following steps in order to 13.3.1 SINGLE PULSE MODE configure the output compare module for PWM operation: For the user to configure the module for the generation of a single output pulse, the following steps are 1. Set the PWM period by writing to the appropriate required (assuming timer is off): Period register. 2. Set the PWM duty cycle by writing to the OCxRS • Determine instruction cycle time, TCY. register. • Calculate desired pulse width value based on TCY. 3. Configure the output compare module for PWM • Calculate time to Start pulse from timer start value operation. of 0x0000. 4. Set the TMRx prescale value and enable the • Write pulse-width start and stop times into OCxR timer, TON (TxCON<15>) = 1. and OCxRS Compare registers (x denotes channel 1, 2, ...,N). 13.4.1 INPUT PIN FAULT PROTECTION • Set Timer Period register to value equal to or FOR PWM greater than value in OCxRS Compare register. When control bits, OCM<2:0> (OCxCON<2:0>) = 111, • Set OCM<2:0> = 100. the selected output compare channel is again config- • Enable timer, TON (TxCON<15>) = 1. ured for the PWM mode of operation with the additional To initiate another single pulse, issue another write to feature of input Fault protection. While in this mode, if set OCM<2:0> = 100. a logic ‘0’ is detected on the OCFA/B pin, the respective PWM output pin is placed in the high-impedance input state. The OCFLT bit (OCxCON<4>) indicates whether a Fault condition has occurred. This state is maintained until both of the following events have occurred: • The external Fault condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits. DS70138G-page 86  2010 Microchip Technology Inc.

dsPIC30F3014/4013 13.4.2 PWM PERIOD The PWM period is specified by writing to the PRx register. The PWM period can be calculated using Equation13-1. EQUATION 13-1: PWM period = [(PRx) + 1] • 4 • TOSC • (TMRx prescale value) PWM frequency is defined as 1/[PWM period]. When the selected TMRx is equal to its respective Period register, PRx, the following four events occur on the next increment cycle: • TMRx is cleared. • The OCx pin is set. - Exception 1: If PWM duty cycle is 0x0000, the OCx pin remains low. - Exception 2: If duty cycle is greater than PRx, the pin remains high. • The PWM duty cycle is latched from OCxRS into OCxR. • The corresponding timer interrupt flag is set. See Figure13-2 for key PWM period comparisons. Timer3 is referred to in Figure13-2 for clarity. FIGURE 13-2: PWM OUTPUT TIMING Period Duty Cycle TMR3 = PR3 TMR3 = PR3 T3IF = 1 T3IF = 1 (Interrupt Flag) (Interrupt Flag) OCxR = OCxRS OCxR = OCxRS TMR3 = Duty Cycle TMR3 = Duty Cycle (OCxR) (OCxR)  2010 Microchip Technology Inc. DS70138G-page 87

dsPIC30F3014/4013 13.5 Output Compare Operation During 13.7 Output Compare Interrupts CPU Sleep Mode The output compare channels have the ability to gener- When the CPU enters Sleep mode, all internal clocks ate an interrupt on a compare match for whichever are stopped. Therefore, when the CPU enters the Match mode has been selected. Sleep state, the output compare channel drives the pin For all modes, except the PWM mode, when a com- to the active state that was observed prior to entering pare event occurs, the respective interrupt flag (OCxIF) the CPU Sleep state. is asserted and an interrupt is generated, if enabled. For example, if the pin was high when the CPU entered The OCxIF bit is located in the corresponding IFSx reg- the Sleep state, the pin remains high. Likewise, if the ister and must be cleared in software. The interrupt is pin was low when the CPU entered the Sleep state, the enabled via the respective compare interrupt enable pin remains low. In either case, the output compare (OCxIE) bit located in the corresponding IEC register. module resumes operation when the device wakes up. For the PWM mode, when an event occurs, the respec- tive Timer Interrupt Flag (T2IF or T3IF) is asserted and 13.6 Output Compare Operation During an interrupt is generated, if enabled. The TxIF bit is CPU Idle Mode located in the IFS0 register and must be cleared in soft- ware. The interrupt is enabled via the respective timer When the CPU enters the Idle mode, the output interrupt enable bit (T2IE or T3IE) located in the IEC0 compare module can operate with full functionality. register. The output compare interrupt flag is never set The output compare channel operates during the CPU during the PWM mode of operation. Idle mode if the OCSIDL bit (OCxCON<13>) is at logic ‘0’ and the selected time base (Timer2 or Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. DS70138G-page 88  2010 Microchip Technology Inc.

 TABLE 13-1: dsPIC30F3014 OUTPUT COMPARE REGISTER MAP(1) 2 0 1 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 0 M OC1RS 0180 Output Compare 1 Secondary Register 0000 0000 0000 0000 ic ro OC1R 0182 Output Compare 1 Main Register 0000 0000 0000 0000 c h ip OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000 Te OC2RS 0186 Output Compare 2 Secondary Register 0000 0000 0000 0000 c hn OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000 o lo OC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSE OCM<2:0> 0000 0000 0000 0000 g y Inc NLeogteend:1: R—e f=e ru ntoim thpele “mdsePnItCed3 0bFit ,F raemadil ya sR e‘0f’erence Manual” (DS70046) for descriptions of register bit fields. . TABLE 13-2: dsPIC30F4013 OUTPUT COMPARE REGISTER MAP(1) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State OC1RS 0180 Output Compare 1 Secondary Register 0000 0000 0000 0000 OC1R 0182 Output Compare 1 Main Register 0000 0000 0000 0000 OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000 OC2RS 0186 Output Compare 2 Secondary Register 0000 0000 0000 0000 OC2R 0188 Output Compare 2 Main Register 0000 0000 0000 0000 OC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSE OCM<2:0> 0000 0000 0000 0000 OC3RS 018C Output Compare 3 Secondary Register 0000 0000 0000 0000 OC3R 018E Output Compare 3 Main Register 0000 0000 0000 0000 OC3CON 0190 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000 d OC4RS 0192 Output Compare 4 Secondary Register 0000 0000 0000 0000 s OC4R 0194 Output Compare 4 Main Register 0000 0000 0000 0000 P OC4CON 0196 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0000 0000 0000 I Legend: — = unimplemented bit, read as ‘0’ C Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 3 0 F 3 0 1 D S 4 7 0 / 13 4 8 G 0 -p a 1 g e 8 3 9

dsPIC30F3014/4013 NOTES: DS70138G-page 90  2010 Microchip Technology Inc.

dsPIC30F3014/4013 14.0 I2C™ MODULE 14.1.1 VARIOUS I2C MODES The following types of I2C operation are supported: Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not • I2C slave operation with 7-bit addressing intended to be a complete reference • I2C slave operation with 10-bit addressing source. For more information on the CPU, • I2C master operation with 7-bit or 10-bit addressing peripherals, register descriptions and See the I2C programmer’s model in Figure14-1. general device functionality, refer to the 'dsPIC30F Family Reference Manual' 14.1.2 PIN CONFIGURATION IN I2C MODE (DS70046). I2C has a 2-pin interface: the SCL pin is clock and the The Inter-Integrated Circuit (I2CTM) module provides SDA pin is data. complete hardware support for both Slave and Multi- Master modes of the I2C serial communication 14.1.3 I2C REGISTERS standard with a 16-bit interface. I2CCON and I2CSTAT are control and status registers, This module offers the following key features: respectively. The I2CCON register is readable and writ- • I2C interface supporting both master and slave able. The lower 6 bits of I2CSTAT are read-only. The remaining bits of the I2CSTAT are read/write. operation. • I2C Slave mode supports 7-bit and 10-bit address- I2CRSR is the shift register used for shifting data, ing. whereas I2CRCV is the buffer register to which data • I2C Master mode supports 7-bit and 10-bit bytes are written, or from which data bytes are read. I2CRCV is the receive buffer as shown in Figure14-1. addressing. I2CTRN is the transmit register to which bytes are • I2C port allows bidirectional transfers between written during a transmit operation, as shown in master and slaves. Figure14-2. • Serial clock synchronization for I2C port can be The I2CADD register holds the slave address. A status used as a handshake mechanism to suspend and bit, ADD10, indicates 10-Bit Addressing mode. The resume serial transfer (SCLREL control). I2CBRG acts as the Baud Rate Generator reload • I2C supports multi-master operation; detects bus value. collision and arbitrates accordingly. In receive operations, I2CRSR and I2CRCV together 14.1 Operating Function Description form a double-buffered receiver. When I2CRSR receives a complete byte, it is transferred to I2CRCV The hardware fully implements all the master and slave and an interrupt pulse is generated. During functions of the I2C Standard and Fast mode transmission, the I2CTRN is not double-buffered. specifications, as well as 7 and 10-bit addressing. Note: Following a Restart condition in 10-bit Thus, the I2C module can operate either as a slave or mode, the user only needs to match the a master on an I2C bus. first 7-bit address. FIGURE 14-1: PROGRAMMER’S MODEL I2CRCV (8 bits) Bit 7 Bit 0 I2CTRN (8 bits) Bit 7 Bit 0 I2CBRG (9 bits) Bit 8 Bit 0 I2CCON (16 bits) Bit 15 Bit 0 I2CSTAT (16 bits) Bit 15 Bit 0 I2CADD (10 bits) Bit 9 Bit 0  2010 Microchip Technology Inc. DS70138G-page 91

dsPIC30F3014/4013 FIGURE 14-2: I2C™ BLOCK DIAGRAM Internal Data Bus I2CRCV Read Shift SCL Clock I2CRSR LSB SDA Addr_Match Match Detect Write I2CADD Read Start and Stop bit Detect Write T Start, Restart, A Stop bit Generate ST C I2 Read c gi o L Collision ol Detect ntr o Write C N O C C Acknowledge 2 I Read Generation Clock Stretching Write I2CTRN LSB Shift Read Clock Reload Control Write BRG Down I2CBRG Counter Read FCY DS70138G-page 92  2010 Microchip Technology Inc.

dsPIC30F3014/4013 14.2 I2C Module Addresses 14.3.2 SLAVE RECEPTION The I2CADD register contains the Slave mode If the R_W bit received is a ‘0’ during an address addresses. The register is a 10-bit register. match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL. After 8 bits are If the A10M bit (I2CCON<10>) is ‘0’, the address is received, if I2CRCV is not full or I2COV is not set, interpreted by the module as a 7-bit address. When an I2CRSR is transferred to I2CRCV. ACK is sent on the address is received, it is compared to the 7 LSbs of the ninth clock. I2CADD register. If the RBF flag is set, indicating that I2CRCV is still If the A10M bit is ‘1’, the address is assumed to be a holding data from a previous operation (RBF = 1), then 10-bit address. When an address is received, it is com- ACK is not sent; however, the interrupt pulse is gener- pared with the binary value, ‘11110 A9 A8’ (where A9 ated. In the case of an overflow, the contents of the and A8 are two Most Significant bits of I2CADD). If that I2CRSR are not loaded into the I2CRCV. value matches, the next address is compared with the Least Significant 8 bits of I2CADD, as specified in the Note: The I2CRCV is loaded if the I2COV bit = 1 10-bit addressing protocol. and the RBF flag = 0. In this case, a read TABLE 14-1: 7-BIT I2C™ SLAVE of the I2CRCV was performed but the ADDRESSES SUPPORTED BY user did not clear the state of the I2COV dsPIC30F bit before the next receive occurred. The acknowledgement is not sent (ACK = 1) 0x00 General Call Address or Start Byte and the I2CRCV is updated. 0x01-0x03 Reserved 0x04-0x07 HS mode Master Codes 14.4 I2C 10-Bit Slave Mode Operation 0x08-0x77 Valid 7-Bit Addresses In 10-bit mode, the basic receive and transmit opera- 0x78-0x7b Valid 10-Bit Addresses (lower 7 bits) tions are the same as in the 7-bit mode. However, the 0x7c-0x7f Reserved criteria for address match is more complex. 14.3 I2C 7-Bit Slave Mode Operation The I2C specification dictates that a slave must be addressed for a write operation with two address bytes Once enabled (I2CEN = 1), the slave module waits for following a Start bit. a Start bit to occur (i.e., the I2C module is ‘Idle’). Follow- The A10M bit is a control bit that signifies that the ing the detection of a Start bit, 8 bits are shifted into address in I2CADD is a 10-bit address rather than a 7-bit I2CRSR, and the address is compared against address. The address detection protocol for the first byte I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0> of a message address is identical for 7-bit and 10-bit are compared against I2CRSR<7:1> and I2CRSR<0> messages, but the bits being compared are different. is the R_W bit. All incoming bits are sampled on the I2CADD holds the entire 10-bit address. Upon receiv- rising edge of SCL. ing an address following a Start bit, I2CRSR <7:3> is If an address match occurs, an Acknowledgement is compared against a literal ‘11110’ (the default 10-bit sent and the Slave Event Interrupt Flag (SI2CIF) is set address) and I2CRSR<2:1> are compared against on the falling edge of the ninth (ACK) bit. The address I2CADD<9:8>. If a match occurs and if R_W = 0, the match does not affect the contents of the I2CRCV buf- interrupt pulse is sent. The ADD10 bit is cleared to indi- fer or the RBF bit. cate a partial address match. If a match fails or R_W=1, the ADD10 bit is cleared and the module 14.3.1 SLAVE TRANSMISSION returns to the Idle state. If the R_W bit received is a ‘1’, the serial port goes into The low byte of the address is then received and com- Transmit mode. It sends an ACK on the ninth bit and pared with I2CADD<7:0>. If an address match occurs, then holds SCL to ‘0’ until the CPU responds by writing the interrupt pulse is generated and the ADD10 bit is to I2CTRN. SCL is released by setting the SCLREL bit, set, indicating a complete 10-bit address match. If an and 8 bits of data are shifted out. Data bits are shifted address match did not occur, the ADD10 bit is cleared out on the falling edge of SCL, such that SDA is valid and the module returns to the Idle state. during SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the 14.4.1 10-BIT MODE SLAVE TRANSMISSION status of the ACK received from the master. Once a slave is addressed in this fashion with the full 10-bit address (we refer to this state as “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation.  2010 Microchip Technology Inc. DS70138G-page 93

dsPIC30F3014/4013 14.4.2 10-BIT MODE SLAVE RECEPTION Clock stretching takes place following the ninth clock of the receive sequence. On the falling edge of the ninth Once addressed, the master can generate a Repeated clock at the end of the ACK sequence, if the RBF bit is Start, reset the high byte of the address and set the set, the SCLREL bit is automatically cleared, forcing R_W bit without generating a Stop bit, thus initiating a the SCL output to be held low. The user’s ISR must set slave transmit operation. the SCLREL bit before reception is allowed to continue. By holding the SCL line low, the user has time to ser- 14.5 Automatic Clock Stretch vice the ISR and read the contents of the I2CRCV In the Slave modes, the module can synchronize buffer before the master device can initiate another receive reads and write to the master device by clock stretching. sequence. This prevents buffer overruns from occurring. 14.5.1 TRANSMIT CLOCK STRETCHING Note1: If the user reads the contents of the Both 10-Bit and 7-Bit Transmit modes implement clock I2CRCV, clearing the RBF bit before the stretching by asserting the SCLREL bit after the falling falling edge of the ninth clock, the edge of the ninth clock, if the TBF bit is cleared, SCLREL bit is not cleared and clock indicating the buffer is empty. stretching does not occur. In Slave Transmit modes, clock stretching is always 2: The SCLREL bit can be set in software performed irrespective of the STREN bit. regardless of the state of the RBF bit. The Clock synchronization takes place following the ninth user should be careful to clear the RBF clock of the transmit sequence. If the device samples bit in the ISR before the next receive an ACK on the falling edge of the ninth clock and if the sequence in order to prevent an overflow TBF bit is still clear, then the SCLREL bit is automati- condition. cally cleared. The SCLREL being cleared to ‘0’ asserts the SCL line low. The user’s ISR must set the SCLREL 14.5.4 CLOCK STRETCHING DURING bit before transmission is allowed to continue. By hold- 10-BIT ADDRESSING (STREN = 1) ing the SCL line low, the user has time to service the ISR and load the contents of the I2CTRN before the Clock stretching takes place automatically during the addressing sequence. Because this module has a master device can initiate another transmit sequence. register for the entire address, it is not necessary for Note1: If the user loads the contents of I2CTRN, the protocol to wait for the address to be updated. setting the TBF bit before the falling edge After the address phase is complete, clock stretching of the ninth clock, the SCLREL bit is not occurs on each data receive or transmit sequence, as be cleared and clock stretching does not described earlier. occur. 2: The SCLREL bit can be set in software, 14.6 Software Controlled Clock regardless of the state of the TBF bit. Stretching (STREN = 1) 14.5.2 RECEIVE CLOCK STRETCHING When the STREN bit is ‘1’, the SCLREL bit can be cleared by software to allow software to control the The STREN bit in the I2CCON register can be used to enable clock stretching in Slave Receive mode. When clock stretching. Program logic synchronizes writes to the STREN bit is set, the SCL pin is held low at the end the SCLREL bit with the SCL clock. Clearing the of each data receive sequence. SCLREL bit does not assert the SCL output until the module detects a falling edge on the SCL output and 14.5.3 CLOCK STRETCHING DURING SCL is sampled low. If the SCLREL bit is cleared by the 7-BIT ADDRESSING (STREN = 1) user while the SCL line has been sampled low, the SCL output is asserted (held low). The SCL output remains When the STREN bit is set in Slave Receive mode, the low until the SCLREL bit is set and all other devices on SCL line is held low when the buffer register is full. The the I2C bus have deasserted SCL. This ensures that a method for stretching the SCL output is the same for write to the SCLREL bit does not violate the minimum both 7 and 10-Bit Addressing modes. high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit is disregarded and has no effect on the SCLREL bit. DS70138G-page 94  2010 Microchip Technology Inc.

dsPIC30F3014/4013 14.7 Interrupts 14.11 I2C Master Support The I2C module generates two interrupt flags, MI2CIF As a master device, six operations are supported: (I2C Master Interrupt Flag) and SI2CIF (I2C Slave Inter- • Assert a Start condition on SDA and SCL. rupt Flag). The MI2CIF interrupt flag is activated on • Assert a Restart condition on SDA and SCL. completion of a master message event. The SI2CIF interrupt flag is activated on detection of a message • Write to the I2CTRN register initiating directed to the slave. transmission of data/address. • Generate a Stop condition on SDA and SCL. 14.8 Slope Control • Configure the I2C port to receive data. • Generate an ACK condition at the end of a The I2C standard requires slope control on the SDA received byte of data. and SCL signals for Fast mode (400 kHz). The control bit, DISSLW, enables the user to disable slew rate 14.12 I2C Master Operation control if desired. It is necessary to disable the slew rate control for 1 MHz mode. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is 14.9 IPMI Support ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also The control bit, IPMIEN, enables the module to support the beginning of the next serial transfer, the I2C bus is Intelligent Peripheral Management Interface (IPMI). not released. When this bit is set, the module accepts and acts upon all addresses. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The 14.10 General Call Address Support first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In The general call address can address all devices. this case, the data direction bit (R_W) is logic ‘0’. Serial When this address is used, all devices should, in data is transmitted 8 bits at a time. After each byte is theory, respond with an Acknowledgement. transmitted, an ACK bit is received. Start and Stop conditions are output to indicate the beginning and the The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It end of a serial transfer. consists of all ‘0’s with R_W = 0. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device The general call address is recognized when the Gen- (7bits) and the data direction bit. In this case, the data eral Call Enable (GCEN) bit is set (I2CCON<7> = 1). direction bit (R_W) is logic ‘1’. Thus, the first byte Following a Start bit detection, 8 bits are shifted into transmitted is a 7-bit slave address, followed by a ‘1’ to I2CRSR and the address is compared with I2CADD, indicate the receive bit. Serial data is received via SDA and is also compared with the general call address while SCL outputs the serial clock. Serial data is which is fixed in hardware. received 8bits at a time. After each byte is received, an If a general call address match occurs, the I2CRSR is ACK bit is transmitted. Start and Stop conditions indi- transferred to the I2CRCV after the eighth clock, the cate the beginning and end of transmission. RBF flag is set and on the falling edge of the ninth bit (ACK bit), the Master Event Interrupt Flag (MI2CIF) is 14.12.1 I2C MASTER TRANSMISSION set. Transmission of a data byte, a 7-bit address or the When the interrupt is serviced, the source for the second half of a 10-bit address, is accomplished by interrupt can be checked by reading the contents of the simply writing a value to I2CTRN register. The user I2CRCV to determine if the address was device-specific should only write to I2CTRN when the module is in a or a general call address. Wait state. This action sets the Buffer Full Flag (TBF) and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/ data is shifted out onto the SDA pin after the falling edge of SCL is asserted. The Transmit Status Flag, TRSTAT (I2CSTAT<14>), indicates that a master transmit is in progress.  2010 Microchip Technology Inc. DS70138G-page 95

dsPIC30F3014/4013 14.12.2 I2C MASTER RECEPTION If a transmit was in progress when the bus collision occurred, the transmission is halted, the TBF flag is Master mode reception is enabled by programming the Receive Enable bit, RCEN (I2CCON<3>). The I2C cleared, the SDA and SCL lines are deasserted and a value can now be written to I2CTRN. When the user module must be Idle before the RCEN bit is set; other- services the I2C master event Interrupt Service wise, the RCEN bit is disregarded. The Baud Rate Routine, if the I2C bus is free (i.e., the P bit is set), the Generator begins counting and on each rollover, the user can resume communication by asserting a Start state of the SCL pin ACK and data are shifted into the condition. I2CRSR on the rising edge of each clock. If a Start, Restart, Stop or Acknowledge condition was 14.12.3 BAUD RATE GENERATOR in progress when the bus collision occurred, the condi- In I2C Master mode, the reload value for the BRG is tion is aborted, the SDA and SCL lines are deasserted and the respective control bits in the I2CCON register located in the I2CBRG register. When the BRG is are cleared to ‘0’. When the user services the bus loaded with this value, the BRG counts down to ‘0’ and collision Interrupt Service Routine, and if the I2C bus is stops until another reload has taken place. If clock free, the user can resume communication by asserting arbitration is taking place, for instance, the BRG is a Start condition. reloaded when the SCL pin is sampled high. As per the I2C standard, FSCK may be 100 kHz or The master continues to monitor the SDA and SCL pins, and if a Stop condition occurs, the MI2CIF bit is 400kHz. However, the user can specify any baud rate set. up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal. A write to the I2CTRN starts the transmission of data at EQUATION 14-1: SERIAL CLOCK RATE the first data bit, regardless of where the transmitter left off when bus collision occurred. I2CBRG = ( FCY – FCY ) – 1 In a multi-master environment, the interrupt generation FSCK 1,111,111 on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the I2CSTAT 14.12.4 CLOCK ARBITRATION register, or the bus is Idle and the S and P bits are Clock arbitration occurs when the master deasserts the cleared. SCL pin (SCL allowed to float high) during any receive, transmit, or Restart/Stop condition. When the SCL pin 14.13 I2C Module Operation During CPU is allowed to float high, the Baud Rate Generator Sleep and Idle Modes (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled 14.13.1 I2C OPERATION DURING CPU high, the Baud Rate Generator is reloaded with the SLEEP MODE contents of I2CBRG and begins counting. This ensures When the device enters Sleep mode, all clock sources that the SCL high time is always at least one BRG roll- to the module are shut down and stay at logic‘0’. If over count in the event that the clock is held low by an Sleep occurs in the middle of a transmission and the external device. state machine is partially into a transmission as the 14.12.5 MULTI-MASTER COMMUNICATION, clocks stop, then the transmission is aborted. Similarly, BUS COLLISION AND BUS if Sleep occurs in the middle of a reception, then the reception is aborted. ARBITRATION Multi-master operation support is achieved by bus arbi- 14.13.2 I2C OPERATION DURING CPU IDLE tration. When the master outputs address/data bits MODE onto the SDA pin, arbitration takes place when the For the I2C, the I2CSIDL bit determines if the module master outputs a ‘1’ on SDA by letting SDA float high stops or continues on Idle. If I2CSIDL = 0, the module while another master asserts a ‘0’. When the SCL pin continues operation on assertion of the Idle mode. If floats high, data should be stable. If the expected data I2CSIDL = 1, the module stops on Idle. on SDA is a ‘1’ and the data sampled on the SDA pin=0, then a bus collision has taken place. The master sets the MI2CIF pulse and resetS the master portion of the I2C port to its Idle state. DS70138G-page 96  2010 Microchip Technology Inc.

 TABLE 14-2: dsPIC30F3014/4013 I2C REGISTER MAP(1) 2 0 1 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 0 M I2CRCV 0200 — — — — — — — — Receive Register 0000 0000 0000 0000 ic ro I2CTRN 0202 — — — — — — — — Transmit Register 0000 0000 1111 1111 c h ip I2CBRG 0204 — — — — — — — Baud Rate Generator 0000 0000 0000 0000 Te I2CCON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0001 0000 0000 0000 c hn I2CSTAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 0000 0000 0000 o lo I2CADD 020A — — — — — — Address Register 0000 0000 0000 0000 g y Inc LNeogteend:1: —Re f=e ru ntoim thpele “mdsePnItCed3 0bFit ,F raemadil ya sR e‘0f’erence Manual” (DS70046) for descriptions of register bit fields. . d s P I C 3 0 F 3 0 1 D S 4 7 0 / 13 4 8 G 0 -p a 1 g e 9 3 7

dsPIC30F3014/4013 NOTES: DS70138G-page 98  2010 Microchip Technology Inc.

dsPIC30F3014/4013 15.0 SPI MODULE Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer Note: This data sheet summarizes features of is completed, the contents of the shift register (SPIxSR) this group ofdsPIC30F devices and is not are moved to the receive buffer. If any transmit data has intended to be a complete reference been written to the buffer register, the contents of the source. For more information on the CPU, transmit buffer are moved to SPIxSR. The received peripherals, register descriptions and data is thus placed in SPIxBUF and the transmit data in general device functionality, refer to the SPIxSR is ready for the next transfer. “dsPIC30F Family Reference Manual” Note: Both the transmit buffer (SPIxTXB) and (DS70046). the receive buffer (SPIxRXB) are mapped The Serial Peripheral Interface (SPI) module is a syn- to the same register address, SPIxBUF. chronous serial interface. It is useful for communicating In Master mode, the clock is generated by prescaling with other peripheral devices, such as EEPROMs, shift the system clock. Data is transmitted as soon as a registers, display drivers and A/D converters, or other value is written to SPIxBUF. The interrupt is generated microcontrollers. It is compatible with Motorola’s SPI at the middle of the transfer of the last bit. and SIOP interfaces. The dsPIC30F3014 and dsPIC30F4013 devices feature one SPI module, SPI1. In Slave mode, data is transmitted and received as external clock pulses appear on SCKx. Again, the inter- rupt is generated when the last bit is latched. If SSx 15.1 Operating Function Description control is enabled, then transmission and reception are Each SPI module consists of a 16-bit shift register, enabled only when SSx = low. The SDOx output is SPIxSR (where x = 1 or 2), used for shifting data in and disabled in SSx mode with SSx high. out, and a buffer register, SPIxBUF. A control register, The clock provided to the module is (FOSC/4). This SPIxCON, configures the module. Additionally, a status clock is then prescaled by the primary (PPRE<1:0>) register, SPIxSTAT, indicates various status conditions. and the secondary (SPRE<2:0>) prescale factors. The The serial interface consists of 4 pins: SDIx (Serial CKE bit determines whether transmit occurs on transi- Data Input), SDOx (Serial Data Output), SCKx (Shift tion from active clock state to Idle clock state, or vice Clock Input or Output), and SSx (Active-Low Slave versa. The CKP bit selects the Idle state (high or low) Select). for the clock. In Master mode operation, SCKx is a clock output but 15.1.1 WORD AND BYTE in Slave mode, it is a clock input. COMMUNICATION A series of eight (8) or sixteen (16) clock pulses shift A control bit, MODE16 (SPIxCON<10>), allows the out bits from the SPIxSR to SDOx pin and module to communicate in either 16-bit or 8-bit mode. simultaneously shift in data from SDIx pin. An interrupt 16-bit operation is identical to 8-bit operation except is generated when the transfer is complete and the cor- that the number of bits transmitted is 16 instead of 8. responding interrupt flag bit (SPI1IF or SPI2IF) is set. This interrupt can be disabled through an interrupt The user software must disable the module prior to enable bit (SPI1IE or SPI2IE). changing the MODE16 bit. The SPI module is reset when the MODE16 bit is changed by the user. The receive operation is double-buffered. When a com- plete byte is received, it is transferred from SPIxSR to A basic difference between 8-bit and 16-bit operation is SPIxBUF. that the data is transmitted out of bit 7 of the SPIxSR for 8-bit operation, and data is transmitted out of bit 15 of If the receive buffer is full when new data is being trans- the SPIxSR for 16-bit operation. In both modes, data is ferred from SPIxSR to SPIxBUF, the module sets the shifted into bit 0 of the SPIxSR. SPIROV bit, indicating an overflow condition. The transfer of the data from SPIxSR to SPIxBUF is not 15.1.2 SDOx DISABLE completed and new data is lost. The module does not respond to SCL transitions while SPIROV is ‘1’, A control bit, DISSDO, is provided to the SPIxCON reg- effectively disabling the module until SPIxBUF is read ister to allow the SDOx output to be disabled. This by user software. allows the SPI module to be connected in an input-only configuration. SDOx can also be used for general purpose I/O.  2010 Microchip Technology Inc. DS70138G-page 99

dsPIC30F3014/4013 15.2 Framed SPI Support the SSx pin is an input or an output (i.e., whether the module receives or generates the Frame Synchroniza- The module supports a basic framed SPI protocol in tion pulse). The frame pulse is an active-high pulse for Master or Slave mode. The control bit, FRMEN, a single SPI clock cycle. When Frame Synchronization enables framed SPI support and causes the SSx pin to is enabled, the data transmission starts only on the perform the Frame Synchronization pulse (FSYNC) subsequent transmit edge of the SPI clock. function. The control bit, SPIFSD, determines whether FIGURE 15-1: SPI BLOCK DIAGRAM Internal Data Bus Read Write SPIxBUF SPIxBUF Receive Transmit SPIxSR SDIx bit 0 SDOx Shift Clock SSx and Clock Edge FSYNC Control Select Control SSx Primary Secondary Prescaler Prescaler FCY 1:1-1:8 1:1, 1:4, SCKx 1:16, 1:64 Enable Master Clock Note: x = 1 or 2. FIGURE 15-2: SPI MASTER/SLAVE CONNECTION SPI Master SPI Slave SDOx SDIy Serial Input Buffer Serial Input Buffer (SPIxBUF) (SPIyBUF) SDIx SDOy Shift Register Shift Register (SPIxSR) (SPIySR) MSb LSb MSb LSb Serial Clock SCKx SCKy PROCESSOR 1 PROCESSOR 2 Note: x = 1 or 2, y = 1 or 2. DS70138G-page 100  2010 Microchip Technology Inc.

dsPIC30F3014/4013 15.3 Slave Select Synchronization 15.5 SPI Operation During CPU Idle Mode The SSx pin allows a Synchronous Slave mode. The SPI must be configured in SPI Slave mode with SSx pin When the device enters Idle mode, all clock sources control enabled (SSEN = 1). When the SSx pin is low, remain functional. The SPISIDL bit (SPIxSTAT<13>) transmission and reception are enabled and the SDOx determines if the SPI module stops or continues on pin is driven. When SSx pin goes high, the SDOx pin is Idle. If SPISIDL = 0, the module continues to operate no longer driven. Also, the SPI module is resynchro- when the CPU enters Idle mode. If SPISIDL = 1, the nized, and all counters/control circuitry are reset. module stops when the CPU enters Idle mode. Therefore, when the SSx pin is asserted low again, transmission/reception begins at the MSb even if SSx had been deasserted in the middle of a transmit/ receive. 15.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut down. If the CPU enters Sleep mode while an SPI transaction is in progress, then the transmission and reception is aborted. The transmitter and receiver stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode.  2010 Microchip Technology Inc. DS70138G-page 101

D TABLE 15-1: dsPIC30F3014/4013 SPI1 REGISTER MAP d S 70 SFR s 1 Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 3 Name P 8 G -p SPI1STAT 0220 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 0000 0000 0000 I a C g SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000 e 1 SPI1BUF 0224 Transmit and Receive Buffer 0000 0000 0000 0000 3 0 2 Legend: — = unimplemented bit, read as ‘0’ 0 Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. F 3 0 1 4 / 4 0 1 3  2 0 1 0 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F3014/4013 16.0 UNIVERSAL ASYNCHRONOUS 16.1 UART Module Overview RECEIVER TRANSMITTER The key features of the UART module are: (UART) MODULE • Full-duplex, 8 or 9-bit data communication Note: This data sheet summarizes features of • Even, odd or no parity options (for 8-bit data) this group ofdsPIC30F devices and is not • One or two Stop bits intended to be a complete reference • Fully integrated Baud Rate Generator with 16-bit source. For more information on the CPU, prescaler peripherals, register descriptions and • Baud rates range from 38 bps to 1.875 Mbps at a general device functionality, refer to the 30 MHz instruction rate “dsPIC30F Family Reference Manual” • 4-word deep transmit data buffer (DS70046). • 4-word deep receive data buffer This section describes the Universal Asynchronous • Parity, framing and buffer overrun error detection Receiver/Transmitter Communications module. • Support for interrupt only on address detect (9th bit = 1) • Separate transmit and receive interrupts • Loopback mode for diagnostic support • Two choices of TX/RX pins on UART1 module FIGURE 16-1: UART TRANSMITTER BLOCK DIAGRAM Internal Data Bus Control and Status bits Write Write UTX8 UxTXREG Low Byte Transmit Control – Control TSR – Control Buffer – Generate Flags – Generate Interrupt Load TSR UxTXIF UTXBRK Data Transmit Shift Register (UxTSR) ‘0’ (Start) UxTX or UxATX ‘1’ (Stop) if ALTIO = 1 Parity GePnaerritaytor 16 Divider 1fr6oxm B Baauudd C Rloactek Generator Control Signals Note: x = 1 or 2.  2010 Microchip Technology Inc. DS70138G-page 103

dsPIC30F3014/4013 FIGURE 16-2: UART RECEIVER BLOCK DIAGRAM Internal Data Bus 16 Read Write Read Read Write UxMODE UxSTA URX8 UxRXREG Low Byte Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters LPBACK 8-9 From UxTX 1 Load RSR to Buffer Control R R Receive Shift Register Signals ER ER 0 (UxRSR) P F UxRX · Start bit Detect or UxARX · Parity Check if ALTIO = 1 · Stop bit Detect 16 Divider · Shift Clock Generation · Wake Logic 16x Baud Clock from Baud Rate Generator UxRXIF DS70138G-page 104  2010 Microchip Technology Inc.

dsPIC30F3014/4013 16.2 Enabling and Setting Up UART 16.3 Transmitting Data 16.2.1 ENABLING THE UART 16.3.1 TRANSMITTING IN 8-BIT DATA MODE The UART module is enabled by setting the UARTEN bit in the UxMODE register (where x = 1 or 2). Once The following steps must be performed in order to enabled, the UxTX and UxRX pins are configured as an transmit 8-bit data: output and an input, respectively, overriding the TRIS 1. Set up the UART: and LAT register bit settings for the corresponding I/O First, the data length, parity and number of Stop port pins. The UxTX pin is at logic ‘1’ when no bits must be selected. Then, the transmit and transmission is taking place. receive interrupt enable and priority bits are set up in the UxMODE and UxSTA registers. Also, 16.2.2 DISABLING THE UART the appropriate baud rate value must be written The UART module is disabled by clearing the UARTEN to the UxBRG register. bit in the UxMODE register. This is the default state 2. Enable the UART by setting the UARTEN bit after any Reset. If the UART is disabled, all I/O pins (UxMODE<15>). operate as port pins under the control of the LAT and 3. Set the UTXEN bit (UxSTA<10>), thereby TRIS bits of the corresponding port pins. enabling a transmission. Disabling the UART module resets the buffers to empty 4. Write the byte to be transmitted to the lower byte states. Any data characters in the buffers are lost and of UxTXREG. The value is transferred to the the baud rate counter is reset. Transmit Shift register (UxTSR) immediately, All error and status flags associated with the UART and the serial bit stream starts shifting out during module are reset when the module is disabled. The the next rising edge of the baud clock. Alterna- URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and tively, the data byte can be written while UTXEN UTXBF bits are cleared, whereas RIDLE and TRMT = 0, following which, the user can set UTXEN. are set. Other control bits, including ADDEN, This causes the serial bit stream to begin imme- URXISEL<1:0>, UTXISEL, as well as the UxMODE diately because the baud clock starts from a and UxBRG registers, are not affected. cleared state. Clearing the UARTEN bit while the UART is active 5. A transmit interrupt is generated, depending on aborts all pending transmissions and receptions and the value of the interrupt control bit, UTXISEL resets the module, as defined above. Re-enabling the (UxSTA<15>). UART restarts the UART in the same configuration. 16.3.2 TRANSMITTING IN 9-BIT DATA 16.2.3 ALTERNATE I/O MODE The alternate I/O function is enabled by setting the The sequence of steps involved in the transmission of ALTIO bit (UxMODE<10>). If ALTIO = 1, the UxATX 9-bit data is similar to 8-bit transmission, except that a and UxARX pins (alternate transmit and alternate 16-bit data word (of which the upper 7 bits are always receive pins, respectively) are used by the UART mod- clear) must be written to the UxTXREG register. ule instead of the UxTX and UxRX pins. If ALTIO = 0, the UxTX and UxRX pins are used by the UART 16.3.3 TRANSMIT BUFFER (UXTXB) module. The transmit buffer is 9 bits wide and 4 characters deep. Including the Transmit Shift register (UxTSR), 16.2.4 SETTING UP DATA, PARITY AND the user effectively has a 5-deep FIFO (First-In, First- STOP BIT SELECTIONS Out) buffer. The UTXBF status bit (UxSTA<9>) Control bits, PDSEL<1:0> in the UxMODE register, are indicates whether the transmit buffer is full. used to select the data length and parity used in the If a user attempts to write to a full buffer, the new data transmission. The data length may either be 8 bits with is not accepted into the FIFO, and no data shift occurs even, odd or no parity, or 9 bits with no parity. within the buffer. This enables recovery from a buffer The STSEL bit determines whether one or two Stop bits overrun condition. are used during data transmission. The FIFO is reset during any device Reset but is not The default (power-on) setting of the UART is 8 bits, no affected when the device enters or wakes up from a parity and 1 Stop bit (typically represented as 8, N, 1). power-saving mode.  2010 Microchip Technology Inc. DS70138G-page 105

dsPIC30F3014/4013 16.3.4 TRANSMIT INTERRUPT 16.4.2 RECEIVE BUFFER (UXRXB) The transmit interrupt flag (U1TXIF or U2TXIF) is The receive buffer is 4 words deep. Including the located in the corresponding interrupt flag register. Receive Shift register (UxRSR), the user effectively has a 5-word deep FIFO buffer. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends URXDA (UxSTA<0>) = 1 indicates that the receive on the UTXISEL control bit: buffer has data available. URXDA = 0 means that the buffer is empty. If a user attempts to read an empty buf- a) If UTXISEL = 0, an interrupt is generated when fer, the old values in the buffer are read and no data a word is transferred from the transmit buffer to shift occurs within the FIFO. the Transmit Shift register (UxTSR). This means that the transmit buffer has at least one empty The FIFO is reset during any device Reset. It is not word. affected when the device enters or wakes up from a b) If UTXISEL = 1, an interrupt is generated when power-saving mode. a word is transferred from the transmit buffer to 16.4.3 RECEIVE INTERRUPT the Transmit Shift register (UxTSR) and the transmit buffer is empty. The receive interrupt flag (U1RXIF or U2RXIF) can be read from the corresponding interrupt flag register. The Switching between the two Interrupt modes during interrupt flag is set by an edge generated by the operation is possible and sometimes offers more receiver. The condition for setting the receive interrupt flexibility. flag depends on the settings specified by the 16.3.5 TRANSMIT BREAK URXISEL<1:0> (UxSTA<7:6>) control bits. Setting the UTXBRK bit (UxSTA<11>) causes the a) If URXISEL<1:0> = 00 or 01, an interrupt is gen- UxTX line to be driven to logic ‘0’. The UTXBRK bit erated every time a data word is transferred overrides all transmission activity. Therefore, the user from the Receive Shift register (UxRSR) to the should generally wait for the transmitter to be Idle receive buffer. There may be one or more before setting UTXBRK. characters in the receive buffer. b) If URXISEL<1:0> = 10, an interrupt is generated To send a Break character, the UTXBRK bit must be set when a word is transferred from the Receive Shift by software and must remain set for a minimum of register (UxRSR) to the receive buffer, which as a 13baud clock cycles. The UTXBRK bit is then cleared result of the transfer, contains 3 characters. by software to generate Stop bits. The user must wait for a duration of at least one or two baud clock cycles c) If URXISEL<1:0> = 11, an interrupt is set when in order to ensure a valid Stop bit(s) before reloading a word is transferred from the Receive Shift the UxTXB, or starting other transmitter activity. Trans- register (UxRSR) to the receive buffer, which as mission of a Break character does not generate a a result of the transfer, contains 4 characters transmit interrupt. (i.e., becomes full). Switching between the Interrupt modes during opera- 16.4 Receiving Data tion is possible, though generally not advisable during normal operation. 16.4.1 RECEIVING IN 8-BIT OR 9-BIT DATA MODE 16.5 Reception Error Handling The following steps must be performed while receiving 16.5.1 RECEIVE BUFFER OVERRUN 8-bit or 9-bit data: ERROR (OERR BIT) 1. Set up the UART (see Section 16.3.1 “Transmitting in 8-Bit Data Mode”). The OERR bit (UxSTA<1>) is set if all of the following conditions occur: 2. Enable the UART (see Section 16.3.1 “Transmitting in 8-Bit Data Mode”). a) The receive buffer is full. 3. A receive interrupt is generated when one or b) The Receive Shift register is full, but unable to more data words have been received, depend- transfer the character to the receive buffer. ing on the receive interrupt settings specified by c) The Stop bit of the character in the UxRSR is the URXISEL bits (UxSTA<7:6>). detected, indicating that the UxRSR needs to 4. Read the OERR bit to determine if an overrun transfer the character to the buffer. error has occurred. The OERR bit must be reset Once OERR is set, no further data is shifted in UxRSR in software. (until the OERR bit is cleared in software or a Reset 5. Read the received data from UxRXREG. The act occurs). The data held in UxRSR and UxRXREG of reading UxRXREG moves the next word to remains valid. the top of the receive FIFO, and the PERR and FERR values are updated. DS70138G-page 106  2010 Microchip Technology Inc.

dsPIC30F3014/4013 16.5.2 FRAMING ERROR (FERR) 16.6 Address Detect Mode The FERR bit (UxSTA<2>) is set if a ‘0’ is detected Setting the ADDEN bit (UxSTA<5>) enables this instead of a Stop bit. If two Stop bits are selected, both special mode in which a 9th bit (URX8) value of ‘1’ Stop bits must be ‘1’; otherwise, FERR is set. The read- identifies the received word as an address, rather than only FERR bit is buffered along with the received data; data. This mode is only applicable for 9-bit data it is cleared on any Reset. communication. The URXISEL control bit does not have any impact on interrupt generation in this mode 16.5.3 PARITY ERROR (PERR) since an interrupt (if enabled) is generated every time The PERR bit (UxSTA<3>) is set if the parity of the the received word has the 9th bit set. received word is incorrect. This error bit is applicable only if a Parity mode (odd or even) is selected. The 16.7 Loopback Mode read-only PERR bit is buffered along with the received data bytes; it is cleared on any Reset. Setting the LPBACK bit enables this special mode in which the UxTX pin is internally connected to the UxRX 16.5.4 IDLE STATUS pin. When configured for the Loopback mode, the UxRX pin is disconnected from the internal UART When the receiver is active (i.e., between the initial receive logic. However, the UxTX pin still functions as detection of the Start bit and the completion of the Stop in a normal operation. bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the com- pletion of the Stop bit and detection of the next Start bit, To select this mode: the RIDLE bit is ‘1’, indicating that the UART is Idle. a) Configure UART for desired mode of operation. b) Set LPBACK = 1 to enable Loopback mode. 16.5.5 RECEIVE BREAK c) Enable transmission as defined in Section16.3 The receiver counts and expects a certain number of bit “Transmitting Data”. times based on the values programmed in the PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>) bits. 16.8 Baud Rate Generator If the break is longer than 13 bit times, the reception is considered complete after the number of bit times The UART has a 16-bit Baud Rate Generator to allow specified by PDSEL and STSEL. The URXDA bit is set, maximum flexibility in baud rate generation. The Baud FERR is set, zeros are loaded into the receive FIFO, Rate Generator register (UxBRG) is readable and interrupts are generated if appropriate, and the RIDLE writable. The baud rate is computed as follows: bit is set. BRG = 16-bit value held in UxBRG register When the module receives a long Break signal and the (0 through 65535) receiver has detected the Start bit, the data bits and the FCY = Instruction Clock Rate (1/TCY) invalid Stop bit (which sets the FERR), the receiver The Baud Rate is given by Equation16-1. must wait for a valid Stop bit before looking for the next Start bit. It cannot assume that the Break condition on EQUATION 16-1: BAUD RATE the line is the next Start bit. Break is regarded as a character containing all ‘0’s with Baud Rate = FCY/(16*(BRG+1)) the FERR bit set. The Break character is loaded into the buffer. No further reception can occur until a Stop bit Therefore, the maximum baud rate possible is: is received. Note that RIDLE goes high when the Stop FCY/16 (if BRG = 0), bit has not yet been received. and the minimum baud rate possible is: FCY/(16 * 65536). With a full 16-bit Baud Rate Generator at 30 MIPS operation, the minimum baud rate achievable is 28.5bps.  2010 Microchip Technology Inc. DS70138G-page 107

dsPIC30F3014/4013 16.9 Auto-Baud Support 16.10.2 UART OPERATION DURING CPU IDLE MODE To allow the system to determine baud rates of received characters, the input can be optionally linked For the UART, the USIDL bit determines if the module to a capture input (IC1 for UART1, IC2 for UART2). To stops or continues operation when the device enters enable this mode, the user must program the input Idle mode. If USIDL=0, the module continues capture module to detect the falling and rising edges of operation during Idle mode. If USIDL = 1, the module the Start bit. stops on Idle. 16.10 UART Operation During CPU Sleep and Idle Modes 16.10.1 UART OPERATION DURING CPU SLEEP MODE When the device enters Sleep mode, all clock sources to the module are shut down and stay at logic ‘0’. If entry into Sleep mode occurs while a transmission is in progress, then the transmission is aborted. The UxTX pin is driven to logic ‘1’. Similarly, if entry into Sleep mode occurs while a reception is in progress, then the reception is aborted. The UxSTA, UxMODE, transmit and receive registers and buffers, and the UxBRG register are not affected by Sleep mode. If the WAKE bit (UxMODE<7>) is set before the device enters Sleep mode, a falling edge on the UxRX pin generates a receive interrupt. The Receive Interrupt Select mode bit (URXISEL) has no effect for this func- tion. If the receive interrupt is enabled, this wakes the device up from Sleep. The UARTEN bit must be set in order to generate a wake-up interrupt. DS70138G-page 108  2010 Microchip Technology Inc.

 TABLE 16-1: dsPIC30F3014/4013 UART1 REGISTER MAP(1) 2 0 1 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 0 M U1MODE 020C UARTEN — USIDL — — ALTIO — — WAKE LPBACK ABAUD — — PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000 ic ro U1STA 020E UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000 c h ip U1TXREG 0210 — — — — — — — UTX8 Transmit Register 0000 000u uuuu uuuu Te U1RXREG 0212 — — — — — — — URX8 Receive Register 0000 0000 0000 0000 c hn U1BRG 0214 Baud Rate Generator Prescaler 0000 0000 0000 0000 o lo Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ gy Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. In c . TABLE 16-2: dsPIC30F3014/4013 UART2 REGISTER MAP(1) SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State Name U2MODE 0216 UARTEN — USIDL — — — — — WAKE LPBACK ABAUD — — PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000 U2STA 0218 UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000 U2TXREG 021A — — — — — — — UTX8 Transmit Register 0000 000u uuuu uuuu U2RXREG 021C — — — — — — — URX8 Receive Register 0000 0000 0000 0000 U2BRG 021E Baud Rate Generator Prescaler 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. d s P I C 3 0 F 3 0 1 D S 7 4 0 1 / 38 4 G -p 0 a g 1 e 1 3 0 9

dsPIC30F3014/4013 NOTES: DS70138G-page 110  2010 Microchip Technology Inc.

dsPIC30F3014/4013 17.0 CAN MODULE The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine Note: This data sheet summarizes features of handles all functions for receiving and transmitting this group ofdsPIC30F devices and is not messages on the CAN bus. Messages are transmitted intended to be a complete reference by first loading the appropriate data registers. Status source. For more information on the CPU, and errors can be checked by reading the appropriate peripherals, register descriptions and registers. Any message detected on the CAN bus is general device functionality, refer to the checked for errors and then matched against filters to “dsPIC30F Family Reference Manual” see if it should be received and stored in one of the (DS70046). receive registers. 17.1 Overview 17.2 Frame Types The Controller Area Network (CAN) module is a serial The CAN module transmits various types of frames interface, useful for communicating with other CAN which include data messages or remote transmission modules or microcontroller devices. This interface/ requests, initiated by the user, as other frames that are protocol was designed to allow communications within automatically generated for control purposes. The noisy environments. following frame types are supported: The CAN module is a communication controller imple- • Standard Data Frame: menting the CAN 2.0 A/B protocol, as defined in the A standard data frame is generated by a node BOSCH specification. The module supports CAN1.2, when the node wishes to transmit data. It includes CAN 2.0A, CAN 2.0B Passive, and CAN 2.0B Active an 11-bit Standard Identifier (SID) but not an 18-bit versions of the protocol. The module implementation is Extended Identifier (EID). a full CAN system. The CAN specification is not cov- ered within this data sheet. The reader may refer to the • Extended Data Frame: BOSCH CAN specification for further details. An extended data frame is similar to a standard The module features are as follows: data frame but includes an extended identifier as well. • Implementation of the CAN protocol CAN1.2, CAN2.0A and CAN2.0B • Remote Frame: • Standard and extended data frames It is possible for a destination node to request the • 0-8 bytes data length data from the source. For this purpose, the • Programmable bit rate up to 1 Mbit/sec destination node sends a remote frame with an identifier that matches the identifier of the required • Support for remote frames data frame. The appropriate data source node • Double-buffered receiver with two prioritized then sends a data frame as a response to this received message storage buffers (each buffer remote request. may contain up to 8 bytes of data) • 6 full (standard/extended identifier), acceptance • Error Frame: filters, 2 associated with the high-priority receive An error frame is generated by any node that buffer and 4 associated with the low-priority detects a bus error. An error frame consists of receive buffer 2fields: an error flag field and an error delimiter • 2 full, acceptance filter masks, one each field. associated with the high and low-priority receive • Overload Frame: buffers An overload frame can be generated by a node as • Three transmit buffers with application specified a result of 2 conditions. First, the node detects a prioritization and abort capability (each buffer may dominant bit during interframe space which is an contain up to 8 bytes of data) illegal condition. Second, due to internal condi- • Programmable wake-up functionality with tions, the node is not yet able to start reception of integrated low-pass filter the next message. A node may generate a • Programmable Loopback mode supports self-test maximum of 2 sequential overload frames to operation delay the start of the next message. • Signaling via interrupt capabilities for all CAN receiver and transmitter error states • Interframe Space: • Programmable clock source Interframe space separates a proceeding frame (of whatever type) from a following data or remote • Programmable link to input capture module (IC2, frame. for both CAN1 and CAN2) for time-stamping and network synchronization • Low-power Sleep and Idle mode  2010 Microchip Technology Inc. DS70138G-page 111

dsPIC30F3014/4013 FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask BUFFERS RXM1(2) Acceptance Filter RXF2(2) Acceptance Mask Acceptance Filter A TXB0(2) TXB1(2) TXB2(2) RXM0(2) RXF3(2) c A c E E E c Acceptance Filter Acceptance Filter e TXREQTXABTTXLARBTXERRMESSAG TXREQTXABTTXLARBTXERRMESSAG TXREQTXABTTXLARBTXERRMESSAG cep AcceRRptXXaFFn01c(e(22 ))Filter AcceRRptXXaFFn45c((e22 ))Filter pt t R(2) R(2) X Identifier M Identifier X Message B A B Queue 0 B 1 Control Transmit Byte Sequencer Data Field Data Field Receive RERRCNT Error PROTOCOL Counter TERRCNT ENGINE Transmit Err Pas Error Bus Off Counter Transmit Shift Receive Shift Protocol Finite CRC Generator CRC Check State Machine Bit Transmit Timing Bit Timing Logic Logic Generator CiTX(1) CiRX(1) Note 1: i = 1 or 2 refers to a particular CAN module (CAN1 or CAN2). 2: These are conceptual groups of registers, not SFR names by themselves. DS70138G-page 112  2010 Microchip Technology Inc.

dsPIC30F3014/4013 17.3 Modes of Operation The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or The CAN module can operate in one of several operation the CPU is in Sleep mode. The WAKFIL bit modes selected by the user. These modes include: (CiCFG2<14>) enables or disables the filter. • Initialization mode Note: Typically, if the CAN module is allowed to • Disable mode transmit in a particular mode of operation • Normal Operation mode and a transmission is requested immedi- • Listen Only mode ately after the CAN module has been • Loopback mode placed in that mode of operation, the mod- • Error Recognition mode ule waits for 11 consecutive recessive bits Modes are requested by setting the REQOP<2:0> bits on the bus before starting transmission. If (CiCTRL<10:8>). Entry into a mode is Acknowledged the user switches to Disable mode within by monitoring the OPMODE<2:0> bits (CiCTRL<7:5>). this 11-bit period, then this transmission is The module does not change the mode and the aborted and the corresponding TXABT bit OPMODE bits until a change in mode is acceptable, is set and TXREQ bit is cleared. generally during bus Idle time which is defined as at 17.3.3 NORMAL OPERATION MODE least 11 consecutive recessive bits. Normal Operating mode is selected when 17.3.1 INITIALIZATION MODE REQOP<2:0>=000. In this mode, the module is acti- In the Initialization mode, the module does not transmit vated and the I/O pins assume the CAN bus functions. or receive. The error counters are cleared and the inter- The module transmits and receives CAN bus rupt flags remain unchanged. The programmer has messages via the CxTX and CxRX pins. access to Configuration registers that are access 17.3.4 LISTEN ONLY MODE restricted in other modes. The module protects the user from accidentally violating the CAN protocol through If the Listen Only mode is activated, the module on the programming errors. All registers that control the con- CAN bus is passive. The transmitter buffers revert to figuration of the module can not be modified while the the port I/O function. The receive pins remain inputs. module is on-line. The CAN module is not allowed to For the receiver, no error flags or Acknowledge signals enter the Configuration mode while a transmission is are sent. The error counters are deactivated in this taking place. The Configuration mode serves as a lock state. The Listen Only mode can be used for detecting to protect the following registers. the baud rate on the CAN bus. To use this, it is neces- • All Module Control registers sary that there are at least two further nodes that • Baud Rate and Interrupt Configuration registers communicate with each other. • Bus Timing registers 17.3.5 LISTEN ALL MESSAGES MODE • Identifier Acceptance Filter registers The module can be set to ignore all errors and receive • Identifier Acceptance Mask registers any message. The Listen All Messages mode is acti- 17.3.2 DISABLE MODE vated by setting the REQOP<2:0> bits to ‘111’. In this mode, the data which is in the message assembly buf- In Disable mode, the module does not transmit or fer until the time an error occurred, is copied in the receive. The module has the ability to set the WAKIF bit receive buffer and can be read via the CPU interface. due to bus activity, however, any pending interrupts remain and the error counters retain their value. 17.3.6 LOOPBACK MODE If the REQOP<2:0> bits (CiCTRL<10:8>) = 001, the If the Loopback mode is activated, the module module enters the Module Disable mode. If the module is connects the internal transmit signal to the internal active, the module waits for 11 recessive bits on the CAN receive signal at the module boundary. The transmit bus, detects that condition as an Idle bus, and then and receive pins revert to their port I/O function. accepts the module disable command. When the OPMODE<2:0> bits (CiCTRL<7:5>)=001, that indicates whether the module successfully went into Module Disable mode. The I/O pins revert to normal I/O function when the module is in the Module Disable mode.  2010 Microchip Technology Inc. DS70138G-page 113

dsPIC30F3014/4013 17.4 Message Reception 17.4.4 RECEIVE OVERRUN An overrun condition occurs when the Message 17.4.1 RECEIVE BUFFERS Assembly Buffer (MAB) has assembled a valid The CAN bus module has 3 receive buffers. However, received message, the message is accepted through one of the receive buffers is always committed to mon- the acceptance filters, and when the receive buffer itoring the bus for incoming messages. This buffer is associated with the filter has not been designated as called the Message Assembly Buffer (MAB). So there clear of the previous message. are 2 receive buffers visible, denoted as RXB0 and The overrun error flag, RXnOVR (CiINTF<15> or RXB1, that can essentially instantaneously receive a CiINTF<14>), and the ERRIF bit (CiINTF<5>) are set complete message from the protocol engine. and the message in the MAB is discarded. All messages are assembled by the MAB and are trans- If the DBEN bit is clear, RXB1 and RXB0 operate inde- ferred to the RXBn buffers only if the acceptance filter pendently. When this is the case, a message intended criterion are met. When a message is received, the for RXB0 is not diverted into RXB1 if RXB0 contains an RXnIF flag (CiINRF<0> or CiINRF<1>) is set. This bit unread message, and the RX0OVR bit is set. can only be set by the module when a message is received. The bit is cleared by the CPU when it has com- If the DBEN bit is set, the overrun for RXB0 is handled pleted processing the message in the buffer. If the differently. If a valid message is received for RXB0 and RXnIE bit (CiINTE<0> or CiINTE<1>) is set, an interrupt RXFUL=1 it indicates that RXB0 is full and is generated when a message is received. RXFUL=0 indicates that RXB1 is empty, the message for RXB0 is loaded into RXB1. An overrun error is not RXF0 and RXF1 filters with RXM0 mask are associated generated for RXB0. If a valid message is received for with RXB0. The filters RXF2, RXF3, RXF4 and RXF5, RXB0 and RXFUL=1, indicates that both RXB0 and and the mask RXM1 are associated with RXB1. RXB1 are full, the message is lost and an overrun is indicated for RXB1. 17.4.2 MESSAGE ACCEPTANCE FILTERS The message acceptance filters and masks are used to 17.4.5 RECEIVE ERRORS determine if a message in the message assembly buf- The CAN module detects the following receive errors: fer should be loaded into either of the receive buffers. Once a valid message has been received into the Mes- • Cyclic Redundancy Check (CRC) error sage Assembly Buffer (MAB), the identifier fields of the • Bit Stuffing error message are compared to the filter values. If there is a • Invalid Message Receive Error match, that message is loaded into the appropriate The receive error counter is incremented by one in receive buffer. case one of these errors occur. The RXWAR bit The acceptance filter looks at incoming messages for (CiINTF<9>) indicates that the receive error counter the RXIDE bit (CiRXnSID<0>) to determine how to has reached the CPU warning limit of 96 and an compare the identifiers. If the RXIDE bit is clear, the interrupt is generated. message is a standard frame and only filters with the EXIDE bit (CiRXFnSID<0>) clear are compared. If the 17.4.6 RECEIVE INTERRUPTS RXIDE bit is set, the message is an extended frame Receive interrupts can be divided into 3 major groups, and only filters with the EXIDE bit set are compared. each including various conditions that generate interrupts: 17.4.3 MESSAGE ACCEPTANCE FILTER MASKS • Receive Interrupt: A message has been successfully received and The mask bits essentially determine which bits to apply loaded into one of the receive buffers. This inter- the filter to. If any mask bit is set to a zero, that bit is rupt is activated immediately after receiving the automatically accepted regardless of the filter bit. End-of-Frame (EOF) field. Reading the RXnIF flag There are two programmable acceptance filter masks indicates which receive buffer caused the associated with the receive buffers, one for each buffer. interrupt. • Wake-up Interrupt: The CAN module has woken up from Disable mode or the device has woken up from Sleep mode. DS70138G-page 114  2010 Microchip Technology Inc.

dsPIC30F3014/4013 • Receive Error Interrupts: Setting TXREQ bit simply flags a message buffer as A receive error interrupt is indicated by the ERRIF enqueued for transmission. When the module detects bit. This bit shows that an error condition an available bus, it begins transmitting the message occurred. The source of the error can be deter- which has been determined to have the highest priority. mined by checking the bits in the CAN Interrupt If the transmission completes successfully on the first register, CiINTF. attempt, the TXREQ bit is cleared automatically and an interrupt is generated if TX1IE was set. - Invalid Message Received: If any type of error occurred during reception of If the message transmission fails, one of the error the last message, an error is indicated by the condition flags is set, and the TXREQ bit remains set, IVRIF bit. indicating that the message is still pending for transmis- sion. If the message encountered an error condition - Receiver Overrun: during the transmission attempt, the TXERR bit is set, The RXnOVR bit indicates that an overrun and the error condition may cause an interrupt. If the condition occurred. message loses arbitration during the transmission attempt, the TXLARB bit is set. No interrupt is - Receiver Warning: generated to signal the loss of arbitration. The RXWAR bit indicates that the Receive Error Counter (RERRCNT<7:0>) has reached the 17.5.4 ABORTING MESSAGE warning limit of 96. TRANSMISSION - Receiver Error Passive: The system can also abort a message by clearing the The RXEP bit indicates that the Receive Error TXREQ bit associated with each message buffer. Counter has exceeded the error passive limit of Setting the ABAT bit (CiCTRL<12>) requests an abort 127 and the module has gone into error passive of all pending messages. If the message has not yet state. started transmission, or if the message started but is interrupted by loss of arbitration or an error, the abort is 17.5 Message Transmission processed. The abort is indicated when the module sets the TXABT bit and the TXnIF flag is not 17.5.1 TRANSMIT BUFFERS automatically set. The CAN module has three transmit buffers. Each of 17.5.5 TRANSMISSION ERRORS the three buffers occupies 14 bytes of data. Eight of the bytes are the maximum 8 bytes of the transmitted mes- The CAN module detects the following transmission errors: sage. Five bytes hold the standard and extended identifiers and other message arbitration information. • Acknowledge error • Form error 17.5.2 TRANSMIT MESSAGE PRIORITY • Bit error Transmit priority is a prioritization within each node of These transmission errors do not necessarily generate the pending transmittable messages. There are an interrupt but are indicated by the transmission error 4levels of transmit priority. If TXPRI<1:0> counter. However, each of these errors causes the (CiTXnCON<1:0>, where n = 0, 1 or 2, represents a transmission error counter to be incremented by one. particular transmit buffer) for a particular message buf- Once the value of the error counter exceeds the value fer is set to ‘11’, that buffer has the highest priority. If of 96, the ERRIF (CiINTF<5>) and the TXWAR bit TXPRI<1:0> for a particular message buffer is set to (CiINTF<10>) are set. Once the value of the error ‘10’ or ‘01’, that buffer has an intermediate priority. If counter exceeds the value of 96, an interrupt is TXPRI<1:0> for a particular message buffer is ‘00’, that generated and the TXWAR bit in the Error Flag register buffer has the lowest priority. is set. 17.5.3 TRANSMISSION SEQUENCE To initiate transmission of the message, the TXREQ bit (CiTXnCON<3>) must be set. The CAN bus module resolves any timing conflicts between setting of the TXREQ bit and the Start-of-Frame (SOF), ensuring that if the priority was changed, it is resolved correctly before the SOF occurs. When TXREQ is set, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits are automatically cleared.  2010 Microchip Technology Inc. DS70138G-page 115

dsPIC30F3014/4013 17.5.6 TRANSMIT INTERRUPTS 17.6 Baud Rate Setting Transmit interrupts can be divided into 2 major groups, All nodes on any particular CAN bus must have the each including various conditions that generate same nominal bit rate. In order to set the baud rate, the interrupts: following parameters have to be initialized: • Transmit Interrupt: • Synchronization Jump Width At least one of the three transmit buffers is empty • Baud Rate Prescaler (not scheduled) and can be loaded to schedule a • Phase Segments message for transmission. The TXnIF flags are • Length determination of Phase Segment 2 read to determine which transmit buffer is available and caused the interrupt. • Sample Point • Propagation Segment bits • Transmit Error Interrupts: A transmission error interrupt is indicated by the 17.6.1 BIT TIMING ERRIF flag. This flag shows that an error condition All controllers on the CAN bus must have the same occurred. The source of the error can be baud rate and bit length. However, different controllers determined by checking the error flags in the CAN are not required to have the same master oscillator Interrupt register, CiINTF. The flags in this register clock. At different clock frequencies of the individual are related to receive and transmit errors. controllers, the baud rate has to be adjusted by - Transmitter Warning Interrupt: adjusting the number of time quanta in each segment. The TXWAR bit indicates that the Transmit Error The nominal bit time can be thought of as being divided Counter has reached the CPU warning limit of into separate non-overlapping time segments. These 96. segments are shown in Figure17-2. - Transmitter Error Passive: • Synchronization Segment (Sync Seg) The TXEP bit (CiINTF<12>) indicates that the • Propagation Time Segment (Prop Seg) Transmit Error Counter has exceeded the error • Phase Segment 1 (Phase1 Seg) passive limit of 127 and the module has gone to • Phase Segment 2 (Phase2 Seg) error passive state. The time segments and also the nominal bit time are - Bus Off: made up of integer units of time called time quanta or The TXBO bit (CiINTF<13>) indicates that the TQ. By definition, the nominal bit time has a minimum Transmit Error Counter (TERRCNT<7:0>) has of 8TQ and a maximum of 25TQ. Also, by definition, exceeded 255 and the module has gone to the the minimum nominal bit time is 1sec corresponding bus off state. to a maximum bit rate of 1MHz. FIGURE 17-2: CAN BIT TIMING Input Signal Prop Phase Phase Sync Sync Segment Segment 1 Segment 2 Sample Point TQ DS70138G-page 116  2010 Microchip Technology Inc.

dsPIC30F3014/4013 17.6.2 PRESCALER SETTING 17.6.5 SAMPLE POINT There is a programmable prescaler with integral values The sample point is the point of time at which the bus ranging from 1 to 64 in addition to a fixed divide-by-2 for level is read and interpreted as the value of that respec- clock generation. The Time Quantum (TQ) is a fixed tive bit. The location is at the end of Phase1 Seg. If the unit of time derived from the oscillator period, shown in bit timing is slow and contains many TQ, it is possible to Equation17-1, where FCAN is FCY (if the CANCKS bit specify multiple sampling of the bus line at the sample is set) or 4FCY (if CANCKS is clear). point. The level determined by the CAN bus then corre- sponds to the result from the majority decision of three Note: FCAN must not exceed 30 MHz. If values. The majority samples are taken at the sample CANCKS = 0, then FCY must not exceed point and twice before with a distance of TQ/2. The 7.5 MHz. CAN module allows the user to choose between sampling three times at the same point, or once at the EQUATION 17-1: TIME QUANTUM FOR same point by setting or clearing the SAM bit CLOCK GENERATION (CiCFG2<6>). Typically, the sampling of the bit should take place at TQ = 2 (BRP<5:0> + 1)/FCAN about 60-70% through the bit time depending on the system parameters. 17.6.3 PROPAGATION SEGMENT 17.6.6 SYNCHRONIZATION This part of the bit time is used to compensate physical To compensate for phase shifts between the oscillator delay times within the network. These delay times con- frequencies of the different bus stations, each CAN sist of the signal propagation time on the bus line and controller must be able to synchronize to the relevant the internal delay time of the nodes. The propagation signal edge of the incoming signal. When an edge in segment can be programmed from 1TQ to 8TQ by the transmitted data is detected, the logic compares the setting the PRSEG<2:0> bits (CiCFG2<2:0>). location of the edge to the expected time (synchronous segment). The circuit then adjusts the values of 17.6.4 PHASE SEGMENTS Phase1 Seg and Phase2 Seg. There are two The phase segments are used to optimally locate the mechanisms used to synchronize. sampling of the received bit within the transmitted bit time. The sampling point is between Phase1 Seg and 17.6.6.1 Hard Synchronization Phase2 Seg. These segments are lengthened or short- Hard synchronization is only done when there is a ened by resynchronization. The end of the Phase1 Seg recessive to dominant edge during bus Idle, indicating determines the sampling point within a bit period. The the start of a message. After hard synchronization, the segment is programmable from 1TQ to 8TQ. Phase2 bit-time counters are restarted with the synchronous Seg provides delay to the next transmitted data transi- segment. Hard synchronization forces the edge which tion. The segment is programmable from 1TQ to 8TQ, has caused the hard synchronization to lie within the or it may be defined to be equal to the greater of synchronization segment of the restarted bit time. If a Phase1 Seg or the information processing time (2TQ). hard synchronization is done, there will not be a The Phase1 Seg is initialized by setting bits resynchronization within that bit time. SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is initialized by setting SEG2PH<2:0> (CiCFG2<10:8>). 17.6.6.2 Resynchronization The following requirement must be fulfilled while setting As a result of resynchronization, Phase1 Seg may be the lengths of the phase segments: lengthened or Phase2 Seg may be shortened. The Prop Seg + Phase1 Seg > = Phase2 Seg amount of lengthening or shortening of the phase buf- fer segment has an upper bound known as the syn- chronization jump width, and is specified by the SJW<1:0> bits (CiCFG1<7:6>). The value of the synchronization jump width is added to Phase1 Seg or subtracted from Phase2 Seg. The resynchronization jump width is programmable between 1TQ and 4TQ. The following requirement must be fulfilled while setting the SJW<1:0> bits: Phase2 Seg>Synchronization Jump Width  2010 Microchip Technology Inc. DS70138G-page 117

D TABLE 17-1: dsPIC30F4013 CAN1 REGISTER MAP(1) d S 70 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 1 3 P 8 C1RXF0SID 0300 — — — Receive Acceptance Filter 0 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u G -p C1RXF0EIDH 0302 — — — — Receive Acceptance Filter 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu I a C ge C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 11 C1RXF1SID 0308 — — — Receive Acceptance Filter 1 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u 3 8 C1RXF1EIDH 030A — — — — Receive Acceptance Filter 1 Extended Identifier<17:6> 0000 uuuu uuuu uuuu 0 C1RXF1EIDL 030C Receive Acceptance Filter 1 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 F C1RXF2SID 0310 — — — Receive Acceptance Filter 2 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u 3 C1RXF2EIDH 0312 — — — — Receive Acceptance Filter 2 Extended Identifier<17:6> 0000 uuuu uuuu uuuu 0 C1RXF2EIDL 0314 Receive Acceptance Filter 2 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 1 C1RXF3SID 0318 — — — Receive Acceptance Filter 3 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u 4 C1RXF3EIDH 031A — — — — Receive Acceptance Filter 3 Extended Identifier<17:6> 0000 uuuu uuuu uuuu / 4 C1RXF3EIDL 031C Receive Acceptance Filter 3 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 C1RXF4SID 0320 — — — Receive Acceptance Filter 4 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u 0 C1RXF4EIDH 0322 — — — — Receive Acceptance Filter 4 Extended Identifier<17:6> 0000 uuuu uuuu uuuu 1 C1RXF4EIDL 0324 Receive Acceptance Filter 4 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 3 C1RXF5SID 0328 — — — Receive Acceptance Filter 5 Standard Identifier<10:0> — EXIDE 000u uuuu uuuu uu0u C1RXF5EIDH 032A — — — — Receive Acceptance Filter 5 Extended Identifier<17:6> 0000 uuuu uuuu uuuu C1RXF5EIDL 032C Receive Acceptance Filter 5 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 C1RXM0SID 0330 — — — Receive Acceptance Mask 0 Standard Identifier<10:0> — MIDE 000u uuuu uuuu uu0u C1RXM0EIDH 0332 — — — — Receive Acceptance Mask 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu C1RXM0EIDL 0334 Receive Acceptance Mask 0 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 C1RXM1SID 0338 — — — Receive Acceptance Mask 1 Standard Identifier<10:0> — MIDE 000u uuuu uuuu uu0u C1RXM1EIDH 033A — — — — Receive Acceptance Mask 1 Extended Identifier<17:6> 0000 uuuu uuuu uuuu C1RXM1EIDL 033C Receive Acceptance Mask 1 Extended Identifier<5:0> — — — — — — — — — — uuuu uu00 0000 0000 C1TX2SID 0340 Transmit Buffer 2 Standard Identifier<10:6> — — — Transmit Buffer 2 Standard Identifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu C1TX2EID 0342 Transmit Buffer 2 Extended Identifier<17:14> — — — — Transmit Buffer 2 Extended Identifier<13:6> uuuu 0000 uuuu uuuu C1TX2DLC 0344 Transmit Buffer 2 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000  C1TX2B1 0346 Transmit Buffer 2 Byte 1 Transmit Buffer 2 Byte 0 uuuu uuuu uuuu uuuu 20 C1TX2B2 0348 Transmit Buffer 2 Byte 3 Transmit Buffer 2 Byte 2 uuuu uuuu uuuu uuuu 1 0 M C1TX2B3 034A Transmit Buffer 2 Byte 5 Transmit Buffer 2 Byte 4 uuuu uuuu uuuu uuuu ic C1TX2B4 034C Transmit Buffer 2 Byte 7 Transmit Buffer 2 Byte 6 uuuu uuuu uuuu uuuu roc C1TX2CON 034E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000 h ip C1TX1SID 0350 Transmit Buffer 1 Standard Identifier<10:6> — — — Transmit Buffer 1 Standard Identifier<5:0> SRR TXIDE uuuu u000 uuuu uuuu T e C1TX1EID 0352 Transmit Buffer 1 Extended Identifier<17:14> — — — — Transmit Buffer 1 Extended Identifier<13:6> uuuu 0000 uuuu uuuu c h n C1TX1DLC 0354 Transmit Buffer 1 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000 o lo Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ g y Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. In c .

TABLE 17-1: dsPIC30F4013 CAN1 REGISTER MAP(1) (CONTINUED)  2 0 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 0 M C1TX1B1 0356 Transmit Buffer 1 Byte 1 Transmit Buffer 1 Byte 0 uuuu uuuu uuuu uuuu icro C1TX1B2 0358 Transmit Buffer 1 Byte 3 Transmit Buffer 1 Byte 2 uuuu uuuu uuuu uuuu ch C1TX1B3 035A Transmit Buffer 1 Byte 5 Transmit Buffer 1 Byte 4 uuuu uuuu uuuu uuuu ip T C1TX1B4 035C Transmit Buffer 1 Byte 7 Transmit Buffer 1 Byte 6 uuuu uuuu uuuu uuuu e c C1TX1CON 035E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000 h no C1TX0SID 0360 Transmit Buffer 0 Standard Identifier<10:6> — — — Transmit Buffer 0 Standard Identifier <5:0> SRR TXIDE uuuu u000 uuuu uuuu lo g C1TX0EID 0362 Transmit Buffer 0 Extended Identifier <17:14> — — — — Transmit Buffer 0 Extended Identifier<13:6> uuuu 0000 uuuu uuuu y In C1TX0DLC 0364 Transmit Buffer 0 Extended Identifier<5:0> TXRTR TXRB1 TXRB0 DLC<3:0> — — — uuuu uuuu uuuu u000 c . C1TX0B1 0366 Transmit Buffer 0 Byte 1 Transmit Buffer 0 Byte 0 uuuu uuuu uuuu uuuu C1TX0B2 0368 Transmit Buffer 0 Byte 3 Transmit Buffer 0 Byte 2 uuuu uuuu uuuu uuuu C1TX0B3 036A Transmit Buffer 0 Byte 5 Transmit Buffer 0 Byte 4 uuuu uuuu uuuu uuuu C1TX0B4 036C Transmit Buffer 0 Byte 7 Transmit Buffer 0 Byte 6 uuuu uuuu uuuu uuuu C1TX0CON 036E — — — — — — — — — TXABT TXLARB TXERR TXREQ — TXPRI<1:0> 0000 0000 0000 0000 C1RX1SID 0370 — — — Receive Buffer 1 Standard Identifier<10:0> SRR RXIDE 000u uuuu uuuu uuuu C1RX1EID 0372 — — — — Receive Buffer 1 Extended Identifier <17:6> 0000 uuuu uuuu uuuu C1RX1DLC 0374 Receive Buffer 1 Extended Identifier<5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu C1RX1B1 0376 Receive Buffer 1 Byte 1 Receive Buffer 1 Byte 0 uuuu uuuu uuuu uuuu C1RX1B2 0378 Receive Buffer 1 Byte 3 Receive Buffer 1 Byte 2 uuuu uuuu uuuu uuuu C1RX1B3 037A Receive Buffer 1 Byte 5 Receive Buffer 1 Byte 4 uuuu uuuu uuuu uuuu C1RX1B4 037C Receive Buffer 1 Byte 7 Receive Buffer 1 Byte 6 uuuu uuuu uuuu uuuu C1RX1CON 037E — — — — — — — — RXFUL — — — RXRTRRO FILHIT<2:0> 0000 0000 0000 0000 d C1RX0SID 0380 — — — Receive Buffer 0 Standard Identifier<10:0> SRR RXIDE 000u uuuu uuuu uuuu s C1RX0EID 0382 — — — — Receive Buffer 0 Extended Identifier<17:6> 0000 uuuu uuuu uuuu P C1RX0DLC 0384 Receive Buffer 0 Extended Identifier<5:0> RXRTR RXRB1 — — — RXRB0 DLC<3:0> uuuu uuuu 000u uuuu I C1RX0B1 0386 Receive Buffer 0 Byte 1 Receive Buffer 0 Byte 0 uuuu uuuu uuuu uuuu C C1RX0B2 0388 Receive Buffer 0 Byte 3 Receive Buffer 0 Byte 2 uuuu uuuu uuuu uuuu 3 C1RX0B3 038A Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 4 uuuu uuuu uuuu uuuu 0 C1RX0B4 038C Receive Buffer 0 Byte 7 Receive Buffer 0 Byte 6 uuuu uuuu uuuu uuuu F C1RX0CON 038E — — — — — — — — RXFUL — — — RXRTRRO DBEN JTOFF FILHIT0 0000 0000 0000 0000 C1CTRL 0390 CANCAP — CSIDL ABAT CANCKS REQOP<2:0> OPMODE<2:0> — ICODE<2:0> — 0000 0100 1000 0000 3 C1CFG1 0392 — — — — — — — — SJW<1:0> BRP<5:0> 0000 0000 0000 0000 0 D C1CFG2 0394 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0u00 0uuu uuuu uuuu 1 S 7 C1INTF 0396 RX0OVR RX1OVR TXBO TXEP RXEP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000 0000 0000 4 0 138 C1INTE 0398 — — — — — — — — IVRIE WAKIE ERRIE TX2IE TX1IE TX0IE RX1IE RX0IE 0000 0000 0000 0000 /4 G C1EC 039A TERRCNT<7:0> RERRCNT<7:0> 0000 0000 0000 0000 -p 0 a Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ g 1 e Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 1 3 1 9

dsPIC30F3014/4013 NOTES: DS70138G-page 120  2010 Microchip Technology Inc.

dsPIC30F3014/4013 18.0 DATA CONVERTER 18.2.3 CSDI PIN INTERFACE (DCI) MODULE The serial data input (CSDI) pin is configured as an input only pin when the module is enabled. Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not 18.2.3.1 COFS PIN intended to be a complete reference The Codec Frame Synchronization (COFS) pin is used source. For more information on the CPU, to synchronize data transfers that occur on the CSDO peripherals, register descriptions and and CSDI pins. The COFS pin may be configured as an general device functionality, refer to the input or an output. The data direction for the COFS pin “dsPIC30F Family Reference Manual” is determined by the COFSD control bit in the (DS70046). DCICON1 register. The DCI module accesses the shadow registers while 18.1 Module Introduction the CPU is in the process of accessing the memory The dsPIC30F Data Converter Interface (DCI) module mapped buffer registers. allows simple interfacing of devices, such as audio 18.2.4 BUFFER DATA ALIGNMENT coder/decoders (Codecs), A/D converters and D/A converters. The following interfaces are supported: Data values are always stored left justified in the buf- fers since most Codec data is represented as a signed • Framed Synchronous Serial Transfer (single or 2’s complement fractional number. If the received word multichannel) • Inter-IC Sound (I2S) Interface length is less than 16 bits, the unused LSbs in the receive buffer registers are set to ‘0’ by the module. If • AC-Link Compliant mode the transmitted word length is less than 16 bits, the The DCI module provides the following general unused LSbs in the transmit buffer register are ignored features: by the module. The word length setup is described in subsequent sections of this document. • Programmable word size up to 16 bits • Support for up to 16 time slots, for a maximum 18.2.5 TRANSMIT/RECEIVE SHIFT frame size of 256 bits REGISTER • Data buffering for up to 4 samples without CPU The DCI module has a 16-bit shift register for shifting overhead serial data in and out of the module. Data is shifted in/ out of the shift register MSb first, since audio PCM data 18.2 Module I/O Pins is transmitted in signed 2’s complement format. There are four I/O pins associated with the module. 18.2.6 DCI BUFFER CONTROL When enabled, the module controls the data direction of each of the four pins. The DCI module contains a buffer control unit for trans- ferring data between the shadow buffer memory and 18.2.1 CSCK PIN the serial shift register. The buffer control unit is a sim- The CSCK pin provides the serial clock for the DCI ple 2-bit address counter that points to word locations module. The CSCK pin may be configured as an input in the shadow buffer memory. For the receive memory or output using the CSCKD control bit in the DCICON1 space (high address portion of DCI buffer memory), the SFR. When configured as an output, the serial clock is address counter is concatenated with a ‘0’ in the MSb provided by the dsPIC30F. When configured as an location to form a 3-bit address. For the transmit mem- input, the serial clock must be provided by an external ory space (high portion of DCI buffer memory), the device. address counter is concatenated with a ‘1’ in the MSb location. 18.2.2 CSDO PIN Note: The DCI buffer control unit always The serial data output (CSDO) pin is configured as an accesses the same relative location in the output only pin when the module is enabled. The transmit and receive buffers, so only one CSDO pin drives the serial bus whenever data is to be address counter is provided. transmitted. The CSDO pin is tri-stated or driven to ‘0’ during CSCK periods when data is not transmitted, depending on the state of the CSDOM control bit. This allows other devices to place data on the serial bus during transmission periods not used by the DCI module.  2010 Microchip Technology Inc. DS70138G-page 121

dsPIC30F3014/4013 FIGURE 18-1: DCI MODULE BLOCK DIAGRAM BCG Control bits SCKD Sample Rate FOSC/4 CSCK Generator FSD Word-Size Selection bits Frame Frame Length Selection bits Synchronization COFS DCI Mode Selection bits Generator s u B a at D Bit RReegceisitveer sB wuf/fSehr adow 6- 1 DCI Buffer Control Unit 15 0 Transmit Buffer DCI Shift Register CSDI Registers w/Shadow CSDO DS70138G-page 122  2010 Microchip Technology Inc.

dsPIC30F3014/4013 18.3 DCI Module Operation Frame lengths, up to 16 data words, may be selected. The frame length in CSCK periods can vary up to a 18.3.1 MODULE ENABLE maximum of 256 depending on the word size that is selected. The DCI module is enabled or disabled by setting/ clearing the DCIEN control bit in the DCICON1 SFR. Note: The COFSG control bits have no effect in Clearing the DCIEN control bit has the effect of reset- AC-Link mode since the frame length is ting the module. In particular, all counters associated set to 256 CSCK periods by the protocol. with CSCK generation, Frame Sync, and the DCI buffer control unit are reset. 18.3.4 FRAME SYNC MODE The DCI clocks are shut down when the DCIEN bit is CONTROL BITS cleared. The type of Frame Sync signal is selected using the When enabled, the DCI controls the data direction for Frame Synchronization mode control bits the four I/O pins associated with the module. The port, (COFSM<1:0>) in the DCICON1 SFR. The following LAT and TRIS register values for these I/O pins are operating modes can be selected: overridden by the DCI module when the DCIEN bit is set. • Multichannel mode It is also possible to override the CSCK pin separately • I2S mode when the bit clock generator is enabled. This permits • AC-Link mode (16-bit) the bit clock generator to operate without enabling the • AC-Link mode (20-bit) rest of the DCI module. The operation of the COFSM control bits depends on 18.3.2 WORD-SIZE SELECTION BITS whether the DCI module generates the Frame Sync signal as a master device, or receives the Frame Sync The WS<3:0> word-size selection bits in the DCICON2 signal as a slave device. SFR determine the number of bits in each DCI data word. Essentially, the WS<3:0> bits determine the The master device in a DSP/Codec pair is the device counting period for a 4-bit counter clocked from the that generates the Frame Sync signal. The Frame Sync CSCK signal. signal initiates data transfers on the CSDI and CSDO pins and usually has the same frequency as the data Any data length, up to 16 bits, may be selected. The sample rate (COFS). value loaded into the WS<3:0> bits is one less the desired word length. For example, a 16-bit data word The DCI module is a Frame Sync master if the COFSD size is selected when WS<3:0> = 1111. control bit is cleared and is a Frame Sync slave if the COFSD control bit is set. Note: These WS<3:0> control bits are used only in the Multichannel and I2S modes. These 18.3.5 MASTER FRAME SYNC bits have no effect in AC-Link mode since OPERATION the data slot sizes are fixed by the protocol. When the DCI module is operating as a Frame Sync 18.3.3 FRAME SYNC GENERATOR master device (COFSD = 0), the COFSM mode bits determine the type of Frame Sync pulse that is The Frame Sync generator (COFSG) is a 4-bit counter generated by the Frame Sync generator logic. that sets the frame length in data words. The Frame A new COFS signal is generated when the Frame Sync Sync generator is incremented each time the word-size generator resets to ‘0’. counter is reset (refer to Section18.3.2 “Word-Size Selection Bits”). The period for the Frame Synchroni- In the Multichannel mode, the Frame Sync pulse is zation generator is set by writing the COFSG<3:0> driven high for the CSCK period to initiate a data trans- control bits in the DCICON2 SFR. The COFSG period fer. The number of CSCK cycles between successive in clock cycles is determined by the following formula: Frame Sync pulses depends on the word size and Frame Sync generator control bits. A timing diagram for EQUATION 18-1: COFSG PERIOD the Frame Sync signal in Multichannel mode is shown in Figure18-2. Frame Length = Word Length • (FSG Value + 1) In the AC-Link mode of operation, the Frame Sync signal has a fixed period and duty cycle. The AC-Link Frame Sync signal is high for 16 CSCK cycles and is low for 240 CSCK cycles. A timing diagram with the timing details at the start of an AC-Link frame is shown in Figure18-3. In the I2S mode, a Frame Sync signal having a 50% duty cycle is generated. The period of the I2S Frame Sync signal in CSCK cycles is determined by the word  2010 Microchip Technology Inc. DS70138G-page 123

dsPIC30F3014/4013 size and Frame Sync generator control bits. A new I2S In the I2S mode, a new data word is transferred one data transfer boundary is marked by a high-to-low or a CSCK cycle after a low-to-high or a high-to-low transi- low-to-high transition edge on the COFS pin. tion is sampled on the COFS pin. A rising or falling edge on the COFS pin resets the Frame Sync 18.3.6 SLAVE FRAME SYNC OPERATION generator logic. When the DCI module is operating as a Frame Sync In the AC-Link mode, the tag slot and subsequent data slave (COFSD = 1), data transfers are controlled by the slots for the next frame is transferred one CSCK cycle Codec device attached to the DCI module. The after the COFS pin is sampled high. COFSM control bits control how the DCI module The COFSG and WS bits must be configured to responds to incoming COFS signals. provide the proper frame length when the module is In the Multichannel mode, a new data frame transfer operating in the Slave mode. Once a valid Frame Sync begins one CSCK cycle after the COFS pin is sampled pulse has been sampled by the module on the COFS high (see Figure18-2). The pulse on the COFS pin pin, an entire data frame transfer takes place. The resets the Frame Sync generator logic. module will not respond to further Frame Sync pulses until the data frame transfer has completed. FIGURE 18-2: FRAME SYNC TIMING, MULTICHANNEL MODE CSCK COFS CSDI/CSDO MSB LSB FIGURE 18-3: FRAME SYNC TIMING, AC-LINK START-OF-FRAME BIT_CLK CSDO or CSDI S12 S12 S12 Tag Tag Tag bit 2 bit 1 LSb MSb bit 14 bit 13 SYNC FIGURE 18-4: I2S INTERFACE FRAME SYNC TIMING CSCK CSDI or CSDO MSB LSB MSB LSB WS Note: A 5-bit transfer is shown here for illustration purposes. The I2S protocol does not specify word length – this will be system dependent. DS70138G-page 124  2010 Microchip Technology Inc.

dsPIC30F3014/4013 18.3.7 BIT CLOCK GENERATOR EQUATION 18-2: BIT CLOCK FREQUENCY The DCI module has a dedicated 12-bit time base that produces the bit clock. The bit clock rate (period) is set FCY FBCK = by writing a non-zero 12-bit value to the BCG<11:0> 2 • (BCG + 1) control bits in the DCICON3 SFR. When the BCG<11:0> bits are set to zero, the bit clock The required bit clock frequency is determined by the is disabled. If the BCG<11:0> bits are set to a non-zero system sampling rate and frame size. Typical bit clock value, the bit clock generator is enabled. These bits frequencies range from 16x to 512x the converter should be set to ‘0’ and the CSCKD bit set to ‘1’ if the sample rate depending on the data converter and the serial clock for the DCI is received from an external communication protocol that is used. device. To achieve bit clock frequencies associated with The formula for the bit clock frequency is given in common audio sampling rates, the user needs to select Equation18-2. a crystal frequency that has an ‘even’ binary value. Examples of such crystal frequencies are listed in Table18-1. TABLE 18-1: DEVICE FREQUENCIES FOR COMMON CODEC CSCK FREQUENCIES FS (kHz) FCSCK/FS FCSCK (MHz)(1) FOSC (MHZ) PLL FCY (MIPS) BCG(2) 8 256 2.048 8.192 4 8.192 1 12 256 3.072 6.144 8 12.288 1 32 32 1.024 8.192 8 16.384 7 44.1 32 1.4112 5.6448 8 11.2896 3 48 64 3.072 6.144 16 24.576 3 Note 1: When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the operation of the DCI module. 2: When the CSCK signal is applied externally (CSCKD = 1), the external clock high and low times must meet the device timing requirements.  2010 Microchip Technology Inc. DS70138G-page 125

dsPIC30F3014/4013 18.3.8 SAMPLE CLOCK EDGE 18.3.11 RECEIVE SLOT ENABLE BITS CONTROL BIT The RSCON SFR contains control bits that are used to The sample clock edge (CSCKE) control bit determines enable up to 16 time slots for reception. These control the sampling edge for the CSCK signal. If the CSCK bit bits are the RSE<15:0> bits. The size of each receive is cleared (default), data is sampled on the falling edge time slot is determined by the WS<3:0> word-size of the CSCK signal. The AC-Link protocols and most selection bits and can vary from 1 to 16 bits. multichannel formats require that data be sampled on If a receive time slot is enabled via one of the RSE bits the falling edge of the CSCK signal. If the CSCK bit is (RSEx = 1), the shift register contents are written to the set, data is sampled on the rising edge of CSCK. The current DCI receive shadow buffer location and the buf- I2S protocol requires that data be sampled on the rising fer control unit is incremented to point to the next buffer edge of the CSCK signal. location. 18.3.9 DATA JUSTIFICATION Data is not packed in the receive memory buffer loca- CONTROL BIT tions if the selected word size is less than 16 bits. Each received slot data word is stored in a separate 16-bit In most applications, the data transfer begins one buffer location. Data is always stored in a left justified CSCK cycle after the COFS signal is sampled active. format in the receive memory buffer. This is the default configuration of the DCI module. An alternate data alignment can be selected by setting the 18.3.12 SLOT ENABLE BITS OPERATION DJST control bit in the DCICON1 SFR. When DJST = 1, WITH FRAME SYNC data transfers begin during the same CSCK cycle when The TSE and RSE control bits operate in concert with the COFS signal is sampled active. the DCI Frame Sync generator. In the Master mode, a 18.3.10 TRANSMIT SLOT ENABLE BITS COFS signal is generated whenever the Frame Sync generator is reset. In the Slave mode, the Frame Sync The TSCON SFR has control bits that are used to generator is reset whenever a COFS pulse is received. enable up to 16 time slots for transmission. These con- trol bits are the TSE<15:0> bits. The size of each time The TSE and RSE control bits allow up to 16 consecu- slot is determined by the WS<3:0> word-size selection tive time slots to be enabled for transmit or receive. bits and can vary up to 16 bits. After the last enabled time slot has been transmitted/ received, the DCI stops buffering data until the next If a transmit time slot is enabled via one of the TSE bits occurring COFS pulse. (TSEx = 1), the contents of the current transmit shadow buffer location is loaded into the CSDO Shift register 18.3.13 SYNCHRONOUS DATA and the DCI buffer control unit is incremented to point TRANSFERS to the next location. The DCI buffer control unit is incremented by one word During an unused transmit time slot, the CSDO pin location whenever a given time slot has been enabled drives ‘0’s or is tri-stated during all disabled time slots for transmission or reception. In most cases, data input depending on the state of the CSDOM bit in the and output transfers are synchronized, which means DCICON1 SFR. that a data sample is received for a given channel at the The data frame size in bits is determined by the chosen same time a data sample is transmitted. Therefore, the data word size and the number of data word elements transmit and receive buffers are filled with equal in the frame. If the chosen frame size has less than amounts of data when a DCI interrupt is generated. 16elements, the additional slot enable bits have no In some cases, the amount of data transmitted and effect. received during a data frame may not be equal. As an Each transmit data word is written to the 16-bit transmit example, assume a two-word data frame is used. buffer as left justified data. If the selected word size is Furthermore, assume that data is only received during less than 16 bits, then the LSbs of the transmit buffer slot#0 but is transmitted during slot #0 and slot #1. In memory have no effect on the transmitted data. The this case, the buffer control unit counter would be user should write ‘0’s to the unused LSbs of each incremented twice during a data frame but only one transmit buffer location. receive register location would be filled with data. DS70138G-page 126  2010 Microchip Technology Inc.

dsPIC30F3014/4013 18.3.14 BUFFER LENGTH CONTROL 18.3.16 TRANSMIT STATUS BITS The amount of data that is buffered between interrupts There are two transmit status bits in the DCISTAT SFR. is determined by the buffer length (BLEN<1:0>) control The TMPTY bit is set when the contents of the transmit bits in the DCICON2 SFR. The size of the transmit and buffer registers are transferred to the transmit shadow receive buffers may be varied from 1 to 4 data words registers. The TMPTY bit may be polled in software to using the BLEN control bits. The BLEN control bits are determine when the transmit buffer registers may be compared to the current value of the DCI buffer control written. The TMPTY bit is cleared automatically by the unit address counter. When the two LSbs of the DCI hardware when a write to one of the four transmit address counter match the BLEN<1:0> value, the buf- buffers occurs. fer control unit is reset to ‘0’. In addition, the contents of the receive shadow registers are transferred to the The TUNF bit is read-only and indicates that a transmit receive buffer registers and the contents of the transmit underflow has occurred for at least one of the transmit buffer registers are transferred to the transmit shadow buffer registers that is in use. The TUNF bit is set at the registers. time the transmit buffer registers are transferred to the transmit shadow registers. The TUNF status bit is 18.3.15 BUFFER ALIGNMENT WITH DATA cleared automatically when the buffer register that FRAMES underflowed is written by the CPU. There is no direct coupling between the position of the Note: The transmit status bits only indicate AGU Address Pointer and the data frame boundaries. status for buffer locations that are used by This means that there is an implied assignment of each the module. If the buffer length is set to transmit and receive buffer that is a function of the less than four words, for example, the BLEN control bits and the number of enabled data slots unused buffer locations do not affect the via the TSE and RSE control bits. transmit status bits. As an example, assume that a 4-word data frame is 18.3.17 RECEIVE STATUS BITS chosen and that we want to transmit on all four time slots in the frame. This configuration would be estab- There are two receive status bits in the DCISTAT SFR. lished by setting the TSE0, TSE1, TSE2, and TSE3 The RFUL status bit is read-only and indicates that new control bits in the TSCON SFR. With this module setup, data is available in the receive buffers. The RFUL bit is the TXBUF0 register would be naturally assigned to cleared automatically when all receive buffers in use slot #0, the TXBUF1 register would be naturally have been read by the CPU. assigned to slot #1, and so on. The ROV status bit is read-only and indicates that a Note: When more than four time slots are active receive overflow has occurred for at least one of the within a data frame, the user code must receive buffer locations. A receive overflow occurs keep track of which time slots are to be when the buffer location is not read by the CPU before read/written at each interrupt. In some new data is transferred from the shadow registers. The cases, the alignment between transmit/ ROV status bit is cleared automatically when the buffer receive buffers and their respective slot register that caused the overflow is read by the CPU. assignments could be lost. Examples of When a receive overflow occurs for a specific buffer such cases include an emulation location, the old contents of the buffer are overwritten. breakpoint or a hardware trap. In these situations, the user should poll the SLOT Note: The receive status bits only indicate status status bits to determine what data should for buffer locations that are used by the be loaded into the buffer registers to module. If the buffer length is set to less resynchronize the software with the DCI than four words, for example, the unused module. buffer locations do not affect the transmit status bits.  2010 Microchip Technology Inc. DS70138G-page 127

dsPIC30F3014/4013 18.3.18 SLOT STATUS BITS 18.4 DCI Module Interrupts The SLOT<3:0> status bits in the DCISTAT SFR indi- The frequency of DCI module interrupts is dependent cate the current active time slot. These bits correspond on the BLEN<1:0> control bits in the DCICON2 SFR. to the value of the Frame Sync generator counter. The An interrupt to the CPU is generated each time the set user may poll these status bits in software when a DCI buffer length has been reached and a shadow register interrupt occurs to determine what time slot data was transfer takes place. A shadow register transfer is last received and which time slot data should be loaded defined as the time when the previously written TXBUF into the TXBUF registers. values are transferred to the transmit shadow registers and new received values in the receive shadow 18.3.19 CSDO MODE BIT registers are transferred into the RXBUF registers. The CSDOM control bit controls the behavior of the CSDO pin during unused transmit slots. A given trans- 18.5 DCI Module Operation During CPU mit time slot is unused if it’s corresponding TSEx bit in Sleep and Idle Modes the TSCON SFR is cleared. If the CSDOM bit is cleared (default), the CSDO pin is 18.5.1 DCI MODULE OPERATION DURING low during unused time slot periods. This mode is used CPU SLEEP MODE when there are only two devices attached to the serial The DCI module has the ability to operate while in bus. Sleep mode and wake the CPU when the CSCK signal If the CSDOM bit is set, the CSDO pin is tri-stated dur- is supplied by an external device (CSCKD = 1). The ing unused time slot periods. This mode allows multiple DCI module generates an asynchronous interrupt devices to share the same CSDO line in a multichannel when a DCI buffer transfer has completed and the CPU application. Each device on the CSDO line is config- is in Sleep mode. ured so that it only transmits data during specific time slots. No two devices transmit data during the same 18.5.2 DCI MODULE OPERATION DURING time slot. CPU IDLE MODE If the DCISIDL control bit is cleared (default), the mod- 18.3.20 DIGITAL LOOPBACK MODE ule continues to operate normally even in Idle mode. If Digital Loopback mode is enabled by setting the the DCISIDL bit is set, the module halts when Idle DLOOP control bit in the DCICON1 SFR. When the mode is asserted. DLOOP bit is set, the module internally connects the CSDO signal to CSDI. The actual data input on the 18.6 AC-Link Mode Operation CSDI I/O pin is ignored in Digital Loopback mode. The AC-Link protocol is a 256-bit frame with one 16-bit 18.3.21 UNDERFLOW MODE CONTROL BIT data slot, followed by twelve 20-bit data slots. The DCI When an underflow occurs, one of two actions may module has two operating modes for the AC-Link pro- occur depending on the state of the Underflow mode tocol. These operating modes are selected by the (UNFM) control bit in the DCICON1 SFR. If the UNFM COFSM<1:0> control bits in the DCICON1 SFR. The bit is cleared (default), the module transmits ‘0’s on the first AC-Link mode is called ‘16-bit AC-Link mode’ and CSDO pin during the active time slot for the buffer loca- is selected by setting COFSM<1:0> = 10. The second tion. In this operating mode, the Codec device attached AC-Link mode is called ‘20-bit AC-Link mode’ and is to the DCI module is simply fed digital ‘silence’. If the selected by setting COFSM<1:0> = 11. UNFM control bit is set, the module transmits the last 18.6.1 16-BIT AC-LINK MODE data written to the buffer location. This operating mode permits the user to send continuous data to the Codec In the 16-bit AC-Link mode, data word lengths are device without consuming CPU overhead. restricted to 16 bits. Note that this restriction only affects the 20-bit data time slots of the AC-Link proto- col. For received time slots, the incoming data is simply truncated to 16 bits. For outgoing time slots, the 4 LSbs of the data word are set to ‘0’ by the module. This trun- cation of the time slots limits the A/D and DAC data to 16 bits but permits proper data alignment in the TXBUF and RXBUF registers. Each RXBUF and TXBUF register contains one data time slot value. DS70138G-page 128  2010 Microchip Technology Inc.

dsPIC30F3014/4013 18.6.2 20-BIT AC-LINK MODE 18.7.1 I2S FRAME AND DATA WORD LENGTH SELECTION The 20-bit AC-Link mode allows all bits in the data time slots to be transmitted and received but does not main- The WS and COFSG control bits are set to produce the tain data alignment in the TXBUF and RXBUF period for one half of an I2S data frame. That is, the registers. frame length is the total number of CSCK cycles The 20-bit AC-Link mode functions similar to the Multi- required for a left or a right data word transfer. channel mode of the DCI module, except for the duty The BLEN bits must be set for the desired buffer length. cycle of the Frame Synchronization signal. The AC- Setting BLEN<1:0> = 01 produces a CPU interrupt, Link Frame Synchronization signal should remain high once per I2S frame. for 16 CSCK cycles and should be low for the following 240cycles. 18.7.2 I2S DATA JUSTIFICATION The 20-bit mode treats each 256-bit AC-Link frame as As per the I2S specification, a data word transfer, by sixteen, 16-bit time slots. In the 20-bit AC-Link mode, default, begins one CSCK cycle after a transition of the the module operates as if COFSG<3:0> = 1111 and WS signal. A ‘MSb left justified’ option can be selected WS<3:0> = 1111. The data alignment for 20-bit data using the DJST control bit in the DCICON1 SFR. slots is ignored. For example, an entire AC-Link data If DJST = 1, the I2S data transfers are MSb left justified. frame can be transmitted and received in a packed The MSb of the data word is presented on the CSDO fashion by setting all bits in the TSCON and RSCON pin during the same CSCK cycle as the rising or falling SFRs. Since the total available buffer length is 64 bits, edge of the COFS signal. The CSDO pin is tri-stated it would take 4 consecutive interrupts to transfer the after the data word has been sent. AC-Link frame. The application software must keep track of the current AC-Link frame segment. 18.7 I2S Mode Operation The DCI module is configured for I2S mode by writing a value of ‘01’ to the COFSM<1:0> control bits in the DCICON1 SFR. When operating in the I2S mode, the DCI module generates Frame Synchronization signals with a 50% duty cycle. Each edge of the Frame Synchronization signal marks the boundary of a new data word transfer. The user must also select the frame length and data word size using the COFSG and WS control bits in the DCICON2 SFR.  2010 Microchip Technology Inc. DS70138G-page 129

D TABLE 18-2: dsPIC30F3014/4013 DCI REGISTER MAP(1) d S 70 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 1 3 P 8G DCICON1 0240 DCIEN — DCISIDL — DLOOP CSCKD CSCKE COFSD UNFM CSDOM DJST — — — COFSM1 COFSM0 0000 0000 0000 0000 -pa DCICON2 0242 — — — — BLEN1 BLEN0 — COFSG<3:0> — WS<3:0> 0000 0000 0000 0000 IC g e DCICON3 0244 — — — — BCG<11:0> 0000 0000 0000 0000 1 3 3 DCISTAT 0246 — — — — SLOT3 SLOT2 SLOT1 SLOT0 — — — — ROV RFUL TUNF TMPTY 0000 0000 0000 0000 0 0 TSCON 0248 TSE15 TSE14 TSE13 TSE12 TSE11 TSE10 TSE9 TSE8 TSE7 TSE6 TSE5 TSE4 TSE3 TSE2 TSE1 TSE0 0000 0000 0000 0000 F RSCON 024C RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 0000 0000 0000 0000 RXBUF0 0250 Receive Buffer 0 Data Register 0000 0000 0000 0000 3 RXBUF1 0252 Receive Buffer 1 Data Register 0000 0000 0000 0000 0 RXBUF2 0254 Receive Buffer 2 Data Register 0000 0000 0000 0000 1 RXBUF3 0256 Receive Buffer 3 Data Register 0000 0000 0000 0000 4 TXBUF0 0258 Transmit Buffer 0 Data Register 0000 0000 0000 0000 / 4 TXBUF1 025A Transmit Buffer 1 Data Register 0000 0000 0000 0000 0 TXBUF2 025C Transmit Buffer 2 Data Register 0000 0000 0000 0000 1 TXBUF3 025E Transmit Buffer 3 Data Register 0000 0000 0000 0000 3 Legend: — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.  2 0 1 0 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F3014/4013 19.0 12-BIT ANALOG-TO-DIGITAL The A/D module has six 16-bit registers: CONVERTER (ADC) MODULE • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) Note: This data sheet summarizes features of • A/D Control Register 3 (ADCON3) this group ofdsPIC30F devices and is not • A/D Input Select Register (ADCHS) intended to be a complete reference source. For more information on the CPU, • A/D Port Configuration Register (ADPCFG) peripherals, register descriptions and • A/D Input Scan Selection Register (ADCSSL) general device functionality, refer to the The ADCON1, ADCON2 and ADCON3 registers “dsPIC30F Family Reference Manual” control the operation of the A/D module. The ADCHS (DS70046). register selects the input channels to be converted. The ADPCFG register configures the port pins as analog The 12-bit Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 12-bit digital inputs or as digital I/O. The ADCSSL register selects number. This module is based on a Successive inputs for scanning. Approximation Register (SAR) architecture and pro- Note: The SSRC<2:0>, ASAM, SMPI<3:0>, vides a maximum sampling rate of 200ksps. The A/D BUFM and ALTS bits, as well as the module has up to 16 analog inputs which are multi- ADCON3 and ADCSSL registers, must plexed into a sample and hold amplifier. The output of not be written to while ADON = 1. This the sample and hold is the input into the converter would lead to indeterminate results. which generates the result. The analog reference volt- age is software selectable to either the device supply The block diagram of the 12-bit A/D module is shown in voltage (AVDD/AVSS) or the voltage level on the Figure19-1. (VREF+/VREF-) pin. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode with RC oscillator selection. FIGURE 19-1: 12-BIT A/D FUNCTIONAL BLOCK DIAGRAM AVDD AVSS VREF+ VREF- 0000 Comparator AN0 DAC 0001 AN1 0010 AN2 0011 12-Bit SAR Conversion Logic AN3 0100 AANN45 0101 16-WDuoardl ,P 1o2r-tBit DataFormat RAM AN6 0110 ace erf AN7 0111 s Int AN8 1000 Sample SampCleo/Snetrqoulence Bu 1001 AN9 1010 Input AN10 Switches Input MUX 1011 Control AN11 1100 AN12 VREF- S/H CH0 AN1 Note: The ADCHS, ADPCFG and ADCSSL registers allow the application to configure AN13-AN15 as analog input pins. Since these pins are not physically present on the device, conversion results from these pins will read ‘0’.  2010 Microchip Technology Inc. DS70138G-page 131

dsPIC30F3014/4013 19.1 A/D Result Buffer 19.3 Selecting the Conversion Sequence The module contains a 16-word, dual port read-only Several groups of control bits select the sequence in buffer, called ADCBUF0...ADCBUFF, to buffer the A/D which the A/D connects inputs to the sample/hold results. The RAM is 12 bits wide but the data obtained channel, converts a channel, writes the buffer memory is represented in one of four different 16-bit data for- and generates interrupts. mats. The contents of the sixteen A/D Conversion The sequence is controlled by the sampling clocks. Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software. The SMPI bits select the number of acquisition/ conversion sequences that would be performed before an interrupt occurs. This can vary from 1 sample per 19.2 Conversion Operation interrupt to 16 samples per interrupt. After the A/D module has been configured, the sample The BUFM bit splits the 16-word results buffer into two acquisition is started by setting the SAMP bit. Various 8-word groups. Writing to the 8-word buffers is sources, such as a programmable bit, timer time-outs alternated on each interrupt event. and external events, terminate acquisition and start a Use of the BUFM bit depends on how much time is conversion. When the A/D conversion is complete, the available for moving the buffers after the interrupt. result is loaded into ADCBUF0...ADCBUFF, and the DONE bit and the A/D Interrupt Flag, ADIF, are set after If the processor can quickly unload a full buffer within the number of samples specified by the SMPI bit. The the time it takes to acquire and convert one channel, ADC module can be configured for different interrupt the BUFM bit can be ‘0’ and up to 16 conversions (cor- rates as described in Section19.3 “Selecting the responding to the 16 input channels) may be done per Conversion Sequence”. interrupt. The processor has one acquisition and conversion time to move the sixteen conversions. The following steps should be followed for doing an A/D conversion: If the processor cannot unload the buffer within the acquisition and conversion time, the BUFM bit should be 1. Configure the A/D module: ‘1’. For example, if SMPI<3:0> (ADCON2<5:2>) = 0111, • Configure analog pins, voltage reference and then eight conversions are loaded into 1/2 of the buffer, digital I/O following which an interrupt occurs. The next eight con- • Select A/D input channels versions are loaded into the other 1/2 of the buffer. The • Select A/D conversion clock processor has the entire time between interrupts to • Select A/D conversion trigger move the eight conversions. • Turn on A/D module The ALTS bit can be used to alternate the inputs 2. Configure A/D interrupt (if required): selected during the sampling sequence. The input • Clear ADIF bit multiplexer has two sets of sample inputs: MUX A and MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are • Select A/D interrupt priority selected for sampling. If the ALTS bit is ‘1’ and • Set ADIE bit (for ISR processing) SMPI<3:0> = 0000 on the first sample/convert 3. Start sampling sequence, the MUX A inputs are selected and on the 4. Wait the required acquisition time next acquire/convert sequence, the MUX B inputs are 5. Trigger acquisition end, start conversion: selected. 6. Wait for A/D conversion to complete, by either: The CSCNA bit (ADCON2<10>) allows the S/H input to • Waiting for the A/D interrupt, or be sequentially scanned across a selected number of analog inputs for the MUX A group. The inputs are • Waiting for the DONE bit to get set. selected by the ADCSSL register. If a particular bit in 7. Read A/D result buffer, clear ADIF if required the ADCSSL register is ‘1’, the corresponding input is selected. The inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. If the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. Note: The ADCHS, ADPCFG and ADCSSL reg- isters allow the application to configure AN13-AN15 as analog input pins. Since these pins are not physically present on the device, conversion results from these pins read ‘0’. DS70138G-page 132  2010 Microchip Technology Inc.

dsPIC30F3014/4013 19.4 Programming the Start of The internal RC oscillator is selected by setting the Conversion Trigger ADRC bit. For correct ADC conversions, the ADC conversion The conversion trigger terminates acquisition and clock (TAD) must be selected to ensure a minimum TAD starts the requested conversions. time of 334 nsec (for VDD = 5V). Refer to Section23.0 The SSRC<2:0> bits select the source of the conver- “Electrical Characteristics” for minimum TAD under sion trigger. The SSRC bits provide for up to 4 alternate other operating conditions. sources of conversion trigger. Example19-1 shows a sample calculation for the When SSRC<2:0> = 000, the conversion trigger is ADCS<5:0> bits, assuming a device operating speed under software control. Clearing the SAMP bit causes of 30 MIPS. the conversion trigger. When SSRC<2:0> = 111 (Auto-Convert mode), the EXAMPLE 19-1: ADC CONVERSION conversion trigger is under A/D clock control. The CLOCK AND SAMPLING SAMC bits select the number of A/D clocks between RATE CALCULATION the start of acquisition and the start of conversion. This provides the fastest conversion rates on multiple Minimum TAD = 334 nsec channels. The SAMC bits must always be at least one TCY = 33.33 nsec (30 MIPS) clock cycle. TAD ADCS<5:0> = 2 – 1 Other trigger sources can come from timer modules or TCY external interrupts. = 2 • 3 3 4 n s e c – 1 33.33 nsec 19.5 Aborting a Conversion = 19 Therefore, Clearing the ADON bit during a conversion aborts the Set ADCS<5:0> = 19 current conversion and stops the sampling sequencing until the next sampling trigger. The ADCBUF is not TCY Actual TAD = (ADCS<5:0> + 1) updated with the partially completed A/D conversion 2 sample. That is, the ADCBUF will continue to contain 33.33 nsec = (19 + 1) the value of the last completed conversion (or the last 2 value written to the ADCBUF register). = 334 nsec If clearing of the ADON bit coincides with an auto-start, the clearing has a higher priority and a new conversion If SSRC<2:0> = 111 and SAMC<4:0> = 00001 does not start. Since, Sampling Time = Acquisition Time + Conversion Time 19.6 Selecting the ADC Conversion = 1 TAD + 14 TAD Clock = 15 x 334 nsec The ADC conversion requires 14 TAD. The source of Therefore, 1 the ADC conversion clock is software selected, using a Sampling Rate = 6-bit counter. There are 64 possible options for TAD. (15 x 334 nsec) = ~200 kHz EQUATION 19-1: ADC CONVERSION CLOCK TAD = TCY * (0.5*(ADCS<5:0> + 1))  2010 Microchip Technology Inc. DS70138G-page 133

dsPIC30F3014/4013 19.7 ADC Speeds The dsPIC30F 12-bit ADC specifications permit a maximum of 200 ksps sampling rate. The table below summarizes the conversion speeds for the dsPIC30F 12-bit ADC and the required operating conditions. TABLE 19-1: 12-BIT ADC EXTENDED CONVERSION RATES dsPIC30F 12-Bit ADC Conversion Rates TAD Sampling Speed Minimum Time Min Rs Max VDD Temperature Channels Configuration Up to 200 334 ns 1 TAD 2.5 k 4.5V to -40°C to +85°C ksps(1) 5.5V VREF-VREF+ ANx CHX S/H ADC Up to 100 668 ns 1 TAD 2.5 k 3.0V to -40°C to +125°C ksps 5.5V VREF-VREF+ or or AVSSAVDD ANx CHX S/H ADC ANx or VREF- Note 1: External VREF- and VREF+ pins must be used for correct operation. See Figure19-2 for recommended circuit. DS70138G-page 134  2010 Microchip Technology Inc.

dsPIC30F3014/4013 Figure19-2 depicts the recommended circuit for the conversion rates above 200 ksps. The dsPIC30F3014 is shown as an example. FIGURE 19-2: ADC VOLTAGE REFERENCE SCHEMATIC See Note 1 4 3 21 0 9 8 7 6 5 4 4 4 44 4 3 3 3 3 3 3 1 33 VDD VDD VDD 2 32 C8 C7 C6 3 VSS31 1 F 0.1 F 0.01 F 4 VSS30 5 VDD29 VDD dsPIC30F3014 6 VSS VDD28 VDD 7 VDD 27 8 VDD 26 9 25 AVDD AVDD AVDD 10 S D +F -F 24 S D E E C5 C4 C3 11 AV AV VR VR 23 1 F 0.1 F 0.01 F 2 3 4 5 6 7 8 9 0 1 2 1 1 1 1 1 1 1 1 2 2 2 VDD R2 R1 10 VDD 10 C2 C1 0.1 F 0.01 F Note 1: Ensure adequate bypass capacitors are provided on each VDD pin. The configuration procedures below give the required • Configure the ADC clock period to be: setup values for the conversion speeds above 1 100ksps. = 334 ns (14 + 1) x 200,000 19.7.1 200 ksps CONFIGURATION by writing to the ADCS<5:0> control bits in the GUIDELINE ADCON3 register. The following configuration items are required to • Configure the sampling time to be 1 TAD by achieve a 200 ksps conversion rate. writing: SAMC<4:0> = 00001. • Comply with conditions provided in Table19-2. The following figure shows the timing diagram of the • Connect external VREF+ and VREF- pins following ADC running at 200 ksps. The TAD selection in conjunc- tion with the guidelines described above allows a con- the recommended circuit shown in Figure19-2. version speed of 200 ksps. See Example19-1 for code • Set SSRC<2.0> = 111 in the ADCON1 register to example. enable the auto-convert option. • Enable automatic sampling by setting the ASAM control bit in the ADCON1 register. • Write the SMPI<3.0> control bits in the ADCON2 register for the desired number of conversions between interrupts.  2010 Microchip Technology Inc. DS70138G-page 135

dsPIC30F3014/4013 FIGURE 19-3: CONVERTING 1 CHANNEL AT 200 ksps, AUTO-SAMPLE START, 1 TAD SAMPLING TIME TSAMP TSAMP = 1 TAD = 1 TAD ADCLK TCONV TCONV = 14 TAD = 14 TAD SAMP DONE ADCBUF0 ADCBUF1 Instruction Execution BSET ADCON1, ASAM 19.8 A/D Acquisition Requirements affect the time required to charge the capacitor, CHOLD. The combined impedance of the analog sources must The analog input model of the 12-bit A/D converter is therefore be small enough to fully charge the holding shown in Figure19-4. The total sampling time for the capacitor within the chosen sample time. To minimize A/D is a function of the internal amplifier settling time the effects of pin leakage currents on the accuracy of and the holding capacitor charge time. the A/D converter, the maximum recommended source For the A/D converter to meet its specified accuracy, impedance, RS, is 2.5 k. After the analog input chan- the Charge Holding Capacitor (CHOLD) must be nel is selected (changed), this sampling function must allowed to fully charge to the voltage level on the be completed prior to starting the conversion. The inter- analog input pin. The Source Impedance (RS), the nal holding capacitor will be in a discharged state prior Interconnect Impedance (RIC) and the Internal Sam- to each sample operation. pling Switch (RSS) Impedance combine to directly FIGURE 19-4: 12-BIT A/D CONVERTER ANALOG INPUT MODEL VDD RIC  250 Sampling RSS  3 k Switch VT = 0.6V Rs ANx RSS CHOLD VA CPIN VT = 0.6V IL E5A0K0A nGAE == D18A CpF capacitance VSS Legend:CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RSS = Sampling Switch Resistance CHOLD = Sample/Hold Capacitance (from DAC) Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs  2.5 k. DS70138G-page 136  2010 Microchip Technology Inc.

dsPIC30F3014/4013 19.9 Module Power-Down Modes If the A/D interrupt is enabled, the device wakes up from Sleep. If the A/D interrupt is not enabled, the A/D The module has two internal power modes. module is then turned off, although the ADON bit When the ADON bit is ‘1’, the module is in Active mode; remains set. it is fully powered and functional. 19.10.2 A/D OPERATION DURING CPU IDLE When ADON is ‘0’, the module is in Off mode. The MODE digital and analog portions of the circuit are disabled for maximum current savings. The ADSIDL bit determines if the module stops or continues on Idle. If ADSIDL = 0, the module continues In order to return to the Active mode from Off mode, the operation on assertion of Idle mode. If ADSIDL = 1, the user must wait for the ADC circuitry to stabilize. The module stops on Idle. time required to stabilize is specified in Section23.0 “Electrical Characteristics”. 19.11 Effects of a Reset 19.10 A/D Operation During CPU Sleep A device Reset forces all registers to their Reset state. and Idle Modes This forces the A/D module to be turned off, and any conversion and sampling sequence is aborted. The val- 19.10.1 A/D OPERATION DURING CPU ues that are in the ADCBUF registers are not modified. SLEEP MODE The A/D Result register contains unknown data after a Power-on Reset. When the device enters Sleep mode, all clock sources to the module are shut down and stay at logic ‘0’. 19.12 Output Formats If Sleep occurs in the middle of a conversion, the conversion is aborted. The converter does not continue The A/D result is 12 bits wide. The data buffer RAM is with a partially completed conversion on exit from also 12 bits wide. The 12-bit data can be read in one Sleep mode. of four different formats. The FORM<1:0> bits select the format. Each of the output formats translates to a Register contents are not affected by the device 16-bit result on the data bus. Write data is always in entering or leaving Sleep mode. right-justified (integer) format. The A/D module can operate during Sleep mode if the A/D clock source is set to RC (ADRC = 1). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed which eliminates all digital switching noise from the conver- sion. (When the conversion sequence is complete, the DONE bit is set.) FIGURE 19-5: A/D OUTPUT DATA FORMATS RAM Contents: d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Read to Bus: Signed Fractional d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 Fractional d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 Signed Integer d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Integer 0 0 0 0 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00  2010 Microchip Technology Inc. DS70138G-page 137

dsPIC30F3014/4013 19.13 Configuring Analog Port Pins 19.14 Connection Considerations The use of the ADPCFG and TRIS registers control the The analog inputs have diodes to VDD and VSS as ESD operation of the A/D port pins. The port pins that are protection. This requires that the analog input be desired as analog inputs must have their correspond- between VDD and VSS. If the input voltage exceeds this ing TRIS bit set (input). If the TRIS bit is cleared range by greater than 0.3V (either direction), one of the (output), the digital output level (VOH or VOL) is diodes becomes forward biased and it may damage the converted. device if the input current specification is exceeded. The A/D operation is independent of the state of the An external RC filter is sometimes added for anti- CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits. aliasing of the input signal. The R component should be selected to ensure that the sampling time requirements When reading the PORT register, all pins configured as are satisfied. Any external components connected (via analog input channels are read as cleared. high-impedance) to an analog input pin (capacitor, Pins configured as digital inputs will not convert an Zener diode, etc.) should have very little leakage analog input. Analog levels on any pin that is defined as current at the pin. a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. DS70138G-page 138  2010 Microchip Technology Inc.

 TABLE 19-2: A/D CONVERTER REGISTER MAP(1) 2 0 10 M NSaFmRe Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State icro ADCBUF0 0280 — — — — ADC Data Buffer 0 0000 uuuu uuuu uuuu c h ADCBUF1 0282 — — — — ADC Data Buffer 1 0000 uuuu uuuu uuuu ip T ADCBUF2 0284 — — — — ADC Data Buffer 2 0000 uuuu uuuu uuuu e ch ADCBUF3 0286 — — — — ADC Data Buffer 3 0000 uuuu uuuu uuuu n o ADCBUF4 0288 — — — — ADC Data Buffer 4 0000 uuuu uuuu uuuu lo gy ADCBUF5 028A — — — — ADC Data Buffer 5 0000 uuuu uuuu uuuu In ADCBUF6 028C — — — — ADC Data Buffer 6 0000 uuuu uuuu uuuu c . ADCBUF7 028E — — — — ADC Data Buffer 7 0000 uuuu uuuu uuuu ADCBUF8 0290 — — — — ADC Data Buffer 8 0000 uuuu uuuu uuuu ADCBUF9 0292 — — — — ADC Data Buffer 9 0000 uuuu uuuu uuuu ADCBUFA 0294 — — — — ADC Data Buffer 10 0000 uuuu uuuu uuuu ADCBUFB 0296 — — — — ADC Data Buffer 11 0000 uuuu uuuu uuuu ADCBUFC 0298 — — — — ADC Data Buffer 12 0000 uuuu uuuu uuuu ADCBUFD 029A — — — — ADC Data Buffer 13 0000 uuuu uuuu uuuu ADCBUFE 029C — — — — ADC Data Buffer 14 0000 uuuu uuuu uuuu ADCBUFF 029E — — — — ADC Data Buffer 15 0000 uuuu uuuu uuuu ADCON1 02A0 ADON — ADSIDL — — — FORM<1:0> SSRC<2:0> — — ASAM SAMP DONE 0000 0000 0000 0000 ADCON2 02A2 VCFG<2:0> — — CSCNA — — BUFS — SMPI<3:0> BUFM ALTS 0000 0000 0000 0000 ADCON3 02A4 — — — SAMC<4:0> ADRC — ADCS<5:0> 0000 0000 0000 0000 d ADCHS 02A6 — — — CH0NB CH0SB<3:0> — — — CH0NA CH0SA<3:0> 0000 0000 0000 0000 ADPCFG 02A8 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000 s ADCSSL 02AA CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 0000 0000 0000 P Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ I Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. C 3 0 F 3 0 1 D S 7 4 0 1 / 38 4 G -p 0 a g 1 e 1 3 3 9

dsPIC30F3014/4013 NOTES: DS70138G-page 140  2010 Microchip Technology Inc.

dsPIC30F3014/4013 20.0 SYSTEM INTEGRATION 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following Note: This data sheet summarizes features of modules and features: this group ofdsPIC30F devices and is not intended to be a complete reference • Various external and internal oscillator options as source. For more information on the CPU, clock sources peripherals, register descriptions and • An on-chip PLL to boost internal operating general device functionality, refer to the frequency “dsPIC30F Family Reference Manual” • A clock switching mechanism between various (DS70046). For more information on the clock sources device instruction set and programming, • Programmable clock postscaler for system power refer to the “16-bit MCU and DSC Pro- savings grammer’s Reference Manual” (DS70157). • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and takes fail-safe measures There are several features intended to maximize • Clock Control register (OSCCON) system reliability, minimize cost through elimination of • Configuration bits for main oscillator selection external components, provide power-saving operating modes and offer code protection: Configuration bits determine the clock source upon Power-on Reset (POR) and Brown-out Reset (BOR). • Oscillator Selection Thereafter, the clock source can be changed between • Reset permissible clock sources. The OSCCON register - Power-on Reset (POR) controls the clock switching and reflects system clock - Power-up Timer (PWRT) related status bits. - Oscillator Start-up Timer (OST) Table20-1 provides a summary of the dsPIC30F - Programmable Brown-out Reset (BOR) oscillator operating modes. A simplified diagram of the • Watchdog Timer (WDT) oscillator system is shown in Figure20-1. • Low-Voltage Detect • Power-Saving modes (Sleep and Idle) • Code Protection • Unit ID Locations • In-Circuit Serial Programming (ICSP) dsPIC30F devices have a Watchdog Timer which is permanently enabled via the Configuration bits or can be software controlled. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT) which provides a delay on power-up only, designed to keep the part in Reset while the power supply stabilizes. With these two timers on- chip, most applications need no external Reset circuitry. Sleep mode is designed to offer a very low-current Power-Down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit a wide variety of applications. In the Idle mode, the clock sources are still active but the CPU is shut off. The RC oscillator option saves system cost while the LP crystal option saves power.  2010 Microchip Technology Inc. DS70138G-page 141

dsPIC30F3014/4013 TABLE 20-1: OSCILLATOR OPERATING MODES Oscillator Mode Description XTL 400 kHz-4 MHz crystal on OSC1:OSC2 XT 4 MHz-10 MHz crystal on OSC1:OSC2 XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled XT w/PLL 16x 4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled(1) LP 32 kHz crystal on SOSCO:SOSCI(2) HS 10 MHz-25 MHz crystal HS/2 w/PLL 4x 10 MHz-20 MHz crystal, divide by 2, 4x PLL enabled HS/2 w/PLL 8x 10 MHz-20 MHz crystal, divide by 2, 8x PLL enabled HS/2 w/PLL 16x 10 MHz-15 MHz crystal, divide by 2, 16x PLL enabled HS/3 w/PLL 4x 12 MHz-25 MHz crystal, divide by 3, 4x PLL enabled HS/3 w/PLL 8x 12 MHz-25 MHz crystal, divide by 3, 8x PLL enabled HS/3 w/PLL 16x 12 MHz-22.5 MHz crystal, divide by 3, 16x PLL enabled EC External clock input (0-40 MHz) ECIO External clock input (0-40 MHz), OSC2 pin is I/O EC w/PLL 4x External clock input (4-10 MHz), OSC2 pin is I/O, 4x PLL enabled(1) EC w/PLL 8x External clock input (4-10 MHz), OSC2 pin is I/O, 8x PLL enabled(1) EC w/PLL 16x External clock input (4-7.5 MHz), OSC2 pin is I/O, 16x PLL enabled(1) ERC External RC oscillator, OSC2 pin is FOSC/4 output(3) ERCIO External RC oscillator, OSC2 pin is I/O(3) FRC 7.37 MHz internal RC oscillator FRC w/PLL 4x 7.37 MHz Internal RC oscillator, 4x PLL enabled FRC w/PLL 8x 7.37 MHz Internal RC oscillator, 8x PLL enabled FRC w/PLL 16x 7.37 MHz Internal RC oscillator, 16x PLL enabled LPRC 512 kHz internal RC oscillator Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met. 2: LP oscillator can be conveniently shared as system clock, as well as Real-Time Clock for Timer1. 3: Requires external R and C. Frequency operation up to 4 MHz. DS70138G-page 142  2010 Microchip Technology Inc.

dsPIC30F3014/4013 FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM Oscillator Configuration bits PWRSAV Instruction Wake-up Request FPLL OSC1 Primary PLL Oscillator x4, x8, x16 PLL OSC2 Lock COSC<2:0> Primary Osc NOSC<2:0> Primary OSWEN Oscillator Stability Detector Oscillator POR Done Start-up Timer Clock Programmable Switching Secondary Osc Clock Divider System and Control Clock SOSCO Block Secondary 32 kHz LP Oscillator 2 Oscillator SOSCI Stability Detector POST<1:0> 4 TUN<3:0> Internal Fast RC Oscillator (FRC) Internal LPRC Low-Power RC Oscillator (LPRC) CF Fail-Safe Clock FCKSM<1:0> Monitor (FSCM) 2 Oscillator Trap To Timer1  2010 Microchip Technology Inc. DS70138G-page 143

dsPIC30F3014/4013 20.2 Oscillator Configurations 20.2.2 OSCILLATOR START-UP TIMER (OST) 20.2.1 INITIAL CLOCK SOURCE In order to ensure that a crystal oscillator (or ceramic SELECTION resonator) has started and stabilized, an Oscillator While coming out of Power-on Reset or Brown-out Start-up Timer is included. It is a simple 10-bit counter Reset, the device selects its clock source based on: that counts 1024 TOSC cycles before releasing the oscillator clock to the rest of the system. The time-out a) FOS<2:0> Configuration bits that select one of four oscillator groups, period is designated as TOST. The TOST time is involved every time the oscillator has to restart (i.e., on POR, b) and FPR<4:0> Configuration bits that select one BOR and wake-up from Sleep). The Oscillator Start-up of 13 oscillator choices within the primary group. Timer is applied to the LP, XT, XTL and HS Oscillator The selection is as shown in Table20-2. modes (upon wake-up from Sleep, POR and BOR) for the primary oscillator. TABLE 20-2: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator OSC2 Oscillator Mode FOS<2:0> FPR<4:0> Source Function ECIO w/PLL 4x PLL 1 1 1 0 1 1 0 1 I/O ECIO w/PLL 8x PLL 1 1 1 0 1 1 1 0 I/O ECIO w/PLL 16x PLL 1 1 1 0 1 1 1 1 I/O FRC w/PLL 4x PLL 1 1 1 0 0 0 0 1 I/O FRC w/PLL 8x PLL 1 1 1 0 1 0 1 0 I/O FRC w/PLL 16x PLL 1 1 1 0 0 0 1 1 I/O XT w/PLL 4x PLL 1 1 1 0 0 1 0 1 OSC2 XT w/PLL 8x PLL 1 1 1 0 0 1 1 0 OSC2 XT w/PLL 16x PLL 1 1 1 0 0 1 1 1 OSC2 HS2 w/PLL 4x PLL 1 1 1 1 0 0 0 1 OSC2 HS2 w/PLL 8x PLL 1 1 1 1 0 0 1 0 OSC2 HS2 w/PLL 16x PLL 1 1 1 1 0 0 1 1 OSC2 HS3 w/PLL 4x PLL 1 1 1 1 0 1 0 1 OSC2 HS3 w/PLL 8x PLL 1 1 1 1 0 1 1 0 OSC2 HS3 w/PLL 16x PLL 1 1 1 1 0 1 1 1 OSC2 ECIO External 0 1 1 0 1 1 0 0 I/O XT External 0 1 1 0 0 1 0 0 OSC2 HS External 0 1 1 0 0 0 1 0 OSC2 EXT External 0 1 1 0 1 0 1 1 CLKO ERC External 0 1 1 0 1 0 0 1 CLKO ERCIO External 0 1 1 0 1 0 0 0 I/O XTL External 0 1 1 0 0 0 0 0 OSC2 LP Secondary 0 0 0 X X X X X (Notes 1, 2) FRC Internal FRC 0 0 1 X X X X X (Notes 1, 2) LPRC Internal LPRC 0 1 0 X X X X X (Notes 1, 2) Note 1: The OSC2 pin is either usable as a general purpose I/O pin functionality only depending on the Primary Oscillator mode selection (FPR<4:0>). 2: Note that OSC1 pin cannot be used as an I/O pin even if the secondary oscillator or an internal clock source is selected at all times. DS70138G-page 144  2010 Microchip Technology Inc.

dsPIC30F3014/4013 20.2.3 LP OSCILLATOR CONTROL If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00101’, ‘00110’ or ‘00111’, then a PLL Enabling the LP oscillator is controlled with two multiplier of 4, 8 or 16 (respectively) is applied. elements: • The current oscillator group bits, COSC<2:0>. Note: When a 16x PLL is used, the FRC frequency must not be tuned to a • The LPOSCEN bit (OSCCON register). frequency greater than 7.5 MHz. The LP oscillator is on (even during Sleep mode) if LPOSCEN = 1. The LP oscillator is the device clock if: TABLE 20-4: FRC TUNING • COSC<2:0> = 00 (LP selected as main osc.) and TUN<3:0> • LPOSCEN = 1 FRC Frequency Bits Keeping the LP oscillator on at all times allows for a fast 0111 +10.5% switch to the 32 kHz system clock for lower power 0110 +9.0% operation. Returning to the faster main oscillator still requires a start-up time 0101 +7.5% 0100 +6.0% 20.2.4 PHASE LOCKED LOOP (PLL) 0011 +4.5% The PLL multiplies the clock which is generated by the 0010 +3.0% primary oscillator. The PLL is selectable to have either 0001 +1.5% gains of x4, x8 and x16. Input and output frequency 0000 Center Frequency (oscillator is ranges are summarized in Table20-3. running at calibrated frequency) TABLE 20-3: PLL FREQUENCY RANGE 1111 -1.5% 1110 -3.0% PLL FIN FOUT 1101 -4.5% Multiplier 1100 -6.0% 4 MHz-10 MHz x4 16 MHz-40 MHz 1011 -7.5% 4 MHz-10 MHz x8 32 MHz-80 MHz 1010 -9.0% 4 MHz-7.5 MHz x16 64 MHz-120 MHz 1001 -10.5% The PLL features a lock output which is asserted when 1000 -12.0% the PLL enters a phase locked state. Should the loop 20.2.6 LOW-POWER RC OSCILLATOR (LPRC) fall out of lock (e.g., due to noise), the lock signal is rescinded. The state of this signal is reflected in the The LPRC oscillator is a component of the Watchdog read-only LOCK bit in the OSCCON register. Timer (WDT) and oscillates at a nominal frequency of 512 kHz. The LPRC oscillator is the clock source for 20.2.5 FAST RC OSCILLATOR (FRC) the Power-up Timer (PWRT) circuit, WDT and clock The FRC oscillator is a fast (7.37 MHz ±2% nominal) monitor circuits. It may also be used to provide a low- internal RC oscillator. This oscillator is intended to pro- frequency clock source option for applications where vide reasonable device operating speeds without the power consumption is critical and timing accuracy is use of an external crystal, ceramic resonator, or RC not required. network. The FRC oscillator can be used with the PLL The LPRC oscillator is always enabled at a Power-on to obtain higher clock frequencies. Reset because it is the clock source for the PWRT. The dsPIC30F operates from the FRC oscillator when- After the PWRT expires, the LPRC oscillator remains ever the current oscillator selection control bits in the on if one of the following is TRUE: OSCCON register (OSCCON<14:12>) are set to ‘001’. • The Fail-Safe Clock Monitor is enabled The four-bit field specified by TUN<3:0> • The WDT is enabled (OSCTUN<3:0>) allows the user to tune the internal • The LPRC oscillator is selected as the system fast RC oscillator (nominal 7.37 MHz). The user can clock via the COSC<2:0> control bits in the tune the FRC oscillator within a range of +10.5% OSCCON register (840kHz) and -12% (960 kHz) in steps of 1.50% around the factory-calibrated setting (see Table20-4). If one of the above conditions is not true, the LPRC shuts off after the PWRT expires. Note: OSCTUN functionality has been provided to help customers compensate for Note1: OSC2 pin function is determined by the temperature effects on the FRC frequency Primary Oscillator mode selection (FPR<4:0>). over a wide range of temperatures. The tuning step size is an approximation and is 2: OSC1 pin cannot be used as an I/O pin neither characterized nor tested. even if the secondary oscillator or an internal clock source is selected at all times.  2010 Microchip Technology Inc. DS70138G-page 145

dsPIC30F3014/4013 20.2.7 FAIL-SAFE CLOCK MONITOR • NOSC<2:0>: Control bits which are written to indicate the new oscillator group of choice. The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator - On POR and BOR, COSC<2:0> and failure. The FSCM function is enabled by appropriately NOSC<2:0> are both loaded with the programming the FCKSM Configuration bits (clock Configuration bit values, FOS<2:0>. switch and monitor selection bits) in the FOSC Device • LOCK: The LOCK status bit indicates a PLL lock. Configuration register. If the FSCM function is enabled, • CF: Read-only status bit indicating if a clock fail the LPRC internal oscillator runs at all times (except detect has occurred. during Sleep mode) and is not subject to control by the • OSWEN: Control bit changes from a ‘0’ to a ‘1’ SWDTEN bit. when a clock transition sequence is initiated. In the event of an oscillator failure, the FSCM Clearing the OSWEN control bit aborts a clock generates a clock failure trap event and switches the transition in progress (used for hang-up system clock over to the FRC oscillator. The user then situations). has the option to either attempt to restart the oscillator If Configuration bits, FCKSM<1:0> = 1x, then the clock or execute a controlled shutdown. The user may decide switching and Fail-Safe Clock Monitor functions are to treat the trap as a warm Reset by simply loading the disabled. This is the default Configuration bit setting. Reset address into the oscillator fail trap vector. In this If clock switching is disabled, then the FOS<2:0> and event, the CF (Clock Fail) status bit (OSCCON<3>) is FPR<4:0> bits directly control the oscillator selection also set whenever a clock failure is recognized. and the COSC<2:0> bits do not control the clock In the event of a clock failure, the WDT is unaffected selection. However, these bits reflect the clock source and continues to run on the LPRC clock. selection. If the oscillator has a very slow start-up time coming out Note: The application should not attempt to of POR, BOR or Sleep, it is possible that the PWRT switch to a clock of frequency lower than timer will expire before the oscillator has started. In 100 kHz when the Fail-Safe Clock Monitor such cases, the FSCM is activated and the FSCM initi- is enabled. If such clock switching is ates a clock failure trap, and the COSC<2:0> bits are performed, the device may generate an loaded with FRC oscillator selection. This effectively oscillator fail trap and switch to the Fast shuts off the original oscillator that was trying to start. RC oscillator. The user may detect this situation and restart the oscillator in the clock fail trap ISR. 20.2.8 PROTECTION AGAINST Upon a clock failure detection, the FSCM module ACCIDENTAL WRITES TO OSCCON initiates a clock switch to the FRC oscillator as follows: A write to the OSCCON register is intentionally made 1. The COSC bits (OSCCON<14:12>) are loaded difficult because it controls clock switching and clock with the FRC oscillator selection value. scaling. 2. CF bit is set (OSCCON<3>). To write to the OSCCON low byte, the following code 3. OSWEN control bit (OSCCON<0>) is cleared. sequence must be executed without any other instructions in between: For the purpose of clock switching, the clock sources are sectioned into four groups: Byte Write 0x46 to OSCCON low Byte Write 0x57 to OSCCON low • Primary Byte write is allowed for one instruction cycle. Write the • Secondary desired value or use bit manipulation instruction. • Internal FRC To write to the OSCCON high byte, the following • Internal LPRC instructions must be executed without any other The user can switch between these functional groups instructions in between: but cannot switch between options within a group. If the primary group is selected, then the choice within the Byte Write 0x78 to OSCCON high group is always determined by the FPR<4:0> Byte Write 0x9A to OSCCON high Configuration bits. Byte write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. The OSCCON register holds the control and status bits related to clock switching. • COSC<2:0>: Read-only status bits always reflect the current oscillator group in effect. DS70138G-page 146  2010 Microchip Technology Inc.

dsPIC30F3014/4013 20.3 Oscillator Control Registers The oscillators are controlled with two SFRs, OSCCON and OSCTUN and one Configuration register, FOSC. Note: The description of the OSCCON and OSCTUN SFRs, as well as the FOSC Configuration register provided in this section are applicable only to the dsPIC30F3014 and dsPIC30F4013 devices in the dsPIC30F product family. REGISTER 20-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-y R-y R-y U-0 R/W-y R/W-y R/W-y — COSC<2:0> — NOSC<2:0> bit 15 bit 8 R/W-0 R/W-0 R-0 U-0 R/W-0 U-0 R/W-0 R/W-0 POST<1:0> LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Group Selection bits (read-only) 111 = PLL oscillator; PLL source selected by FPR<4:0> bits 011 = External oscillator; OSC1/OSC2 pins; external oscillator configuration selected by FPR<4:0> bits 010 = LPRC internal low-power RC 001 = FRC internal fast RC 000 = LP crystal oscillator; SOSCI/SOSCO pins Set to FOS<2:0> values on POR or BOR. Loaded with NOSC<2:0> at the completion of a successful clock switch. Set to FRC value when FSCM detects a failure and switches clock to FRC. bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Group Selection bits 111 = PLL Oscillator; PLL source selected by FPR<4:0> bits 011 = External oscillator; OSC1/OSC2 pins; external oscillator configuration selected by FPR<4:0> bits 010 = LPRC internal low-power RC 001 = FRC internal fast RC 000 = LP crystal oscillator; SOSCI/SOSCO pins Set to FOS<2:0> values on POR or BOR. bit 7-6 POST<1:0>: Oscillator Postscaler Selection bits 11 = Oscillator postscaler divides clock by 64 10 = Oscillator postscaler divides clock by 16 01 = Oscillator postscaler divides clock by 4 00 = Oscillator postscaler does not alter clock  2010 Microchip Technology Inc. DS70138G-page 147

dsPIC30F3014/4013 REGISTER 20-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock 0 = Indicates that PLL is out of lock (or disabled) Reset on POR or BOR. Reset when a valid clock switching sequence is initiated. Set when PLL lock is achieved after a PLL start. Reset when lock is lost. Read zero when PLL is not selected as a system clock bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit (read/clearable by application) 1 = FSCM has detected clock failure 0 = FSCM has NOT detected clock failure Reset on POR or BOR. Reset when a valid clock switching sequence is initiated. Set when clock fail detected bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: 32 kHz Secondary (LP) Oscillator Enable bit 1 = Secondary oscillator is enabled 0 = Secondary oscillator is disabled Reset on POR or BOR. bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Reset on POR or BOR. Reset after a successful clock switch. Reset after a redundant clock switch. Reset after FSCM switches the oscillator to (Group 1) FRC. DS70138G-page 148  2010 Microchip Technology Inc.

dsPIC30F3014/4013 R EGISTER 20-2: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — TUN<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3-0 TUN<3:0>: TUN Field Lower Two bits The four-bit field specified by TUN<3:0> specifies the user tuning capability for the internal fast RC oscillator (nominal 7.37 MHz). 0111 = Maximum frequency 0110 = 0101 = 0100 = 0011 = 0010 = 0001 = 0000 = Center frequency, oscillator is running at calibrated frequency 1111 = 1110 = 1101 = 1100 = 1011 = 1010 = 1001 = 1000 = Minimum frequency  2010 Microchip Technology Inc. DS70138G-page 149

dsPIC30F3014/4013 REGISTER 20-3: FOSC: OSCILLATOR CONFIGURATION REGISTER U U U U U U U U — — — — — — — — bit 23 bit 16 R/P R/P U U U R/P R/P R/P FCKSM<1:0> — — — FOS<2:0> bit 15 bit 8 U U U R/P R/P R/P R/P R/P — — — FPR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘0’ bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 13-11 Unimplemented: Read as ‘0’ bit 10-8 FOS<2:0>: Oscillator Group Selection on POR bits 111 = PLL oscillator; PLL source selected by FPR<4:0> bits (see Table20-2) 011 = EXT: External Oscillator; OSC1/OSC2 pins; external oscillator configuration selected by FPR<4:0> bits 010 = LPRC: Internal Low-Power RC 001 = FRC: Internal Fast RC 000 = LPOSC: Low-Power Crystal Oscillator; SOSCI/SOSCO pins bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 FPR<4:0>: Oscillator Selection within Primary Group bits (see Table20-2) DS70138G-page 150  2010 Microchip Technology Inc.

dsPIC30F3014/4013 20.4 Reset Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected The dsPIC30F3014/4013 differentiates between by a WDT wake-up since this is viewed as the resump- various kinds of Reset: tion of normal operation. Status bits from the RCON a) Power-on Reset (POR) register are set or cleared differently in different Reset b) MCLR Reset during normal operation situations, as indicated in Table20-5. These bits are used in software to determine the nature of the Reset. c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal A block diagram of the On-Chip Reset Circuit is shown operation) in Figure20-2. e) Programmable Brown-out Reset (BOR) A MCLR noise filter is provided in the MCLR Reset path. The filter detects and ignores small pulses. f) RESET Instruction g) Reset caused by trap lockup (TRAPR) Internally generated Resets do not drive MCLR pin low. h) Reset caused by illegal opcode or by using an uninitialized W register as an Address Pointer (IOPUWR) FIGURE 20-2: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Digital Glitch Filter MCLR Sleep or Idle WDT Module VDD Rise POR S Detect VDD Brown-out BOR Reset BOREN R Q SYSRST Trap Conflict Illegal Opcode/ Uninitialized W Register 20.4.1 POR: POWER-ON RESET The POR circuit inserts a small delay, TPOR, which is nominally 10s and ensures that the device bias A power-on event generates an internal POR pulse circuits are stable. Furthermore, a user-selected when a VDD rise is detected. The Reset pulse occurs at power-up time-out (TPWRT) is applied. The TPWRT the POR circuit threshold voltage (VPOR) which is nom- parameter is based on device Configuration bits and inally 1.85V. The device supply voltage characteristics can be 0 ms (no delay), 4 ms, 16 ms, or 64 ms. The must meet specified starting voltage and rise rate total delay is at device power-up, TPOR + TPWRT. When requirements. The POR pulse resets a POR timer and these delays have expired, SYSRST is negated on the places the device in the Reset state. The POR also next leading edge of the Q1 clock and the PC jumps to selects the device clock source identified by the the Reset vector. oscillator configuration fuses. The timing for the SYSRST signal is shown in Figure20-3 through Figure20-5.  2010 Microchip Technology Inc. DS70138G-page 151

dsPIC30F3014/4013 FIGURE 20-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset FIGURE 20-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset DS70138G-page 152  2010 Microchip Technology Inc.

dsPIC30F3014/4013 20.4.1.1 POR with Long Crystal Start-up Time A BOR generates a Reset pulse, which resets the (with FSCM Enabled) device. The BOR selects the clock source based on the device Configuration bit values (FOS<2:0> and The oscillator start-up circuitry is not linked to the POR FPR<4:0>). Furthermore, if an oscillator mode is circuitry. Some crystal circuits (especially low- selected, the BOR activates the Oscillator Start-up frequency crystals) have a relatively long start-up time. Timer (OST). The system clock is held until OST Therefore, one or more of the following conditions is expires. If the PLL is used, then the clock is held until possible after the POR timer and the PWRT have the LOCK bit (OSCCON<5>) is ‘1’. expired: Concurrently, the POR time-out (TPOR) and the PWRT • The oscillator circuit has not begun to oscillate. time-out (TPWRT) are applied before the internal Reset is • The Oscillator Start-up Timer has not expired (if a released. If TPWRT = 0 and a crystal oscillator is being crystal oscillator is used). used, then a nominal delay of TFSCM = 100 s is applied. • The PLL has not achieved a LOCK (if PLL is The total delay in this case is (TPOR+ TFSCM). used). The BOR status bit (RCON<1>) is set to indicate that a If the FSCM is enabled and one of the above conditions BOR has occurred. The BOR circuit, if enabled, contin- is true, a clock failure trap occurs. The device automat- ues to operate while in Sleep or Idle modes and resets ically switches to the FRC oscillator and the user can the device should VDD fall below the BOR threshold switch to the desired crystal oscillator in the trap ISR. voltage. 20.4.1.2 Operating without FSCM and PWRT FIGURE 20-6: EXTERNAL POWER-ON If the FSCM is disabled and the Power-up Timer RESET CIRCUIT (FOR (PWRT) is also disabled, then the device exits rapidly SLOW VDD POWER-UP) from Reset on power-up. If the clock source is FRC, LPRC, ERC or EC, it will be active immediately. VDD If the FSCM is disabled and the system clock has not started, the device will be in a frozen state at the Reset D R R1 vector until the system clock starts. From the user’s MCLR perspective, the device appears to be in Reset until a system clock is available. C dsPIC30F 20.4.2 BOR: PROGRAMMABLE BROWN-OUT RESET Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The BOR (Brown-out Reset) module is based on an The diode D helps discharge the capacitor internal voltage reference circuit. The main purpose of quickly when VDD powers down. the BOR module is to generate a device Reset when a 2: R should be suitably chosen so as to make brown-out condition occurs. Brown-out conditions are sure that the voltage drop across R does not generally caused by glitches on the AC mains (i.e., violate the device’s electrical specifications. missing portions of the AC cycle waveform due to bad 3: R1 should be suitably chosen so as to limit power transmission lines, or voltage sags due to exces- any current flowing into MCLR from external sive current draw when a large inductive load is turned capacitor C, in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge on). (ESD), or Electrical Overstress (EOS). The BOR module allows selection of one of the following voltage trip points (see Table23-11): • 2.6V-2.71V Note: Dedicated supervisory devices, such as the MCP1XX and MCP8XX, may also be • 4.1V-4.4V used as an external Power-on Reset • 4.58V-4.73V circuit. Note: The BOR voltage trip points indicated here are nominal values provided for design guidance only. Refer to the Electrical Specifications in the specific device data sheet for BOR voltage limit specifications.  2010 Microchip Technology Inc. DS70138G-page 153

dsPIC30F3014/4013 Table20-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table means that all the bits are negated prior to the action specified in the condition column. TABLE 20-5: INITIALIZATION CONDITION FOR RCON REGISTER: CASE 1 Program Condition TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR Counter Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1 Brown-out Reset 0x000000 0 0 0 0 0 0 0 0 1 MCLR Reset during normal 0x000000 0 0 1 0 0 0 0 0 0 operation Software Reset during 0x000000 0 0 0 1 0 0 0 0 0 normal operation MCLR Reset during Sleep 0x000000 0 0 1 0 0 0 1 0 0 MCLR Reset during Idle 0x000000 0 0 1 0 0 1 0 0 0 WDT Time-out Reset 0x000000 0 0 0 0 1 0 0 0 0 WDT Wake-up PC + 2 0 0 0 0 1 0 1 0 0 Interrupt Wake-up from Sleep PC + 2(1) 0 0 0 0 0 0 1 0 0 Clock Failure Trap 0x000004 0 0 0 0 0 0 0 0 0 Trap Reset 0x000000 1 0 0 0 0 0 0 0 0 Illegal Operation Trap 0x000000 0 1 0 0 0 0 0 0 0 Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. Table20-6 shows a second example of the bit conditions for the RCON register. In this case, it is not assumed the user has set/cleared specific bits prior to action specified in the condition column. TABLE 20-6: INITIALIZATION CONDITION FOR RCON REGISTER: CASE 2 Program Condition TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR Counter Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1 Brown-out Reset 0x000000 u u u u u u u 0 1 MCLR Reset during normal 0x000000 u u 1 0 0 0 0 u u operation Software Reset during 0x000000 u u 0 1 0 0 0 u u normal operation MCLR Reset during Sleep 0x000000 u u 1 u 0 0 1 u u MCLR Reset during Idle 0x000000 u u 1 u 0 1 0 u u WDT Time-out Reset 0x000000 u u 0 0 1 0 0 u u WDT Wake-up PC + 2 u u u u 1 u 1 u u Interrupt Wake-up from Sleep PC + 2(1) u u u u u u 1 u u Clock Failure Trap 0x000004 u u u u u u u u u Trap Reset 0x000000 1 u u u u u u u u Illegal Operation Reset 0x000000 u 1 u u u u u u u Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70138G-page 154  2010 Microchip Technology Inc.

dsPIC30F3014/4013 20.5 Watchdog Timer (WDT) 20.7 Power-Saving Modes 20.5.1 WATCHDOG TIMER OPERATION There are two power-saving states that can be entered through the execution of a special instruction, PWRSAV; The primary function of the Watchdog Timer (WDT) is these are Sleep and Idle. to reset the processor in the event of a software mal- The format of the PWRSAV instruction is as follows: function. The WDT is a free-running timer that runs off an on-chip RC oscillator, requiring no external compo- PWRSAV <parameter>, where ‘parameter’ defines nent. Therefore, the WDT timer continues to operate Idle or Sleep mode. even if the main processor clock (e.g., the crystal oscillator) fails. 20.7.1 SLEEP MODE In Sleep mode, the clock to the CPU and peripherals is 20.5.2 ENABLING AND DISABLING shut down. If an on-chip oscillator is being used, it is THE WDT shut down. The Watchdog Timer can be “Enabled” or “Disabled” The Fail-Safe Clock Monitor is not functional during only through a Configuration bit (FWDTEN) in the Sleep since there is no clock to monitor. However, the Configuration register, FWDT. LPRC clock remains active if WDT is operational during Setting FWDTEN = 1 enables the Watchdog Timer. The Sleep. enabling is done when programming the device. By The brown-out protection circuit and the Low-Voltage default, after chip erase, FWDTEN bit = 1. Any device Detect (LVD) circuit, if enabled, remains functional programmer capable of programming dsPIC30F during Sleep. devices allows programming of this and other The processor wakes up from Sleep if at least one of Configuration bits. the following conditions has occurred: If enabled, the WDT increments until it overflows or • any interrupt that is individually enabled and “times out”. A WDT time-out forces a device Reset meets the required priority level (except during Sleep). To prevent a WDT time-out, the user must clear the Watchdog Timer using a CLRWDT • any Reset (POR, BOR and MCLR) instruction. • WDT time-out If a WDT times out during Sleep, the device wakes up. On waking up from Sleep mode, the processor restarts The WDTO bit in the RCON register is cleared to the same clock that was active prior to entry into Sleep indicate a wake-up resulting from a WDT time-out. mode. When clock switching is enabled, bits, COSC<2:0>, determine the oscillator source to be Setting FWDTEN = 0 allows user software to enable/ used on wake-up. If clock switch is disabled, then there disable the Watchdog Timer via the SWDTEN is only one system clock. (RCON<5>) control bit. Note: If a POR or BOR occurred, the selection of 20.6 Low-Voltage Detect the oscillator is based on the FOS<2:0> and FPR<4:0> Configuration bits. The Low-Voltage Detect (LVD) module is used to detect when the VDD of the device drops below a If the clock source is an oscillator, the clock to the threshold value, VLVD, which is determined by the device is held off until OST times out (indicating a LVDL<3:0> bits (RCON<11:8>) and is thus user pro- stable oscillator). If PLL is used, the system clock is grammable. The internal voltage reference circuitry held off until LOCK = 1 (indicating that the PLL is requires a nominal amount of time to stabilize, and the stable). In either case, TPOR, TLOCK and TPWRT delays BGST bit (RCON<13>) indicates when the voltage are applied. reference has stabilized. If EC, FRC, LPRC or ERC oscillators are used, then a In some devices, the LVD threshold voltage may be delay of TPOR (~ 10 s) is applied. This is the smallest applied externally on the LVDIN pin. delay possible on wake-up from Sleep. The LVD module is enabled by setting the LVDEN bit Moreover, if the LP oscillator was active during Sleep (RCON<12>). and LP is the oscillator used on wake-up, then the start- up delay is equal to TPOR. PWRT delay and OST timer delay are not applied. In order to have the smallest possible start-up delay when waking up from Sleep, one of these faster wake-up options should be selected before entering Sleep.  2010 Microchip Technology Inc. DS70138G-page 155

dsPIC30F3014/4013 Any interrupt that is individually enabled (using the cor- Any interrupt that is individually enabled (using the IE responding IE bit) and meets the prevailing priority level bit) and meets the prevailing priority level is able to can wake-up the processor. The processor processes wake up the processor. The processor processes the the interrupt and branch to the ISR. The SLEEP status interrupt and branches to the ISR. The IDLE status bit bit in the RCON register is set upon wake-up. in the RCON register is set upon wake-up. Note: In spite of various delays applied (TPOR, Any Reset other than POR sets the IDLE status bit. On TLOCK and TPWRT), the crystal oscillator a POR, the IDLE bit is cleared. (and PLL) may not be active at the end of If Watchdog Timer is enabled, the processor wakes up the time-out (e.g., for low-frequency crys- from Idle mode upon WDT time-out. The Idle and tals). In such cases, if FSCM is enabled, the WDTO status bits are both set. device detects this as a clock failure and Unlike wake-up from Sleep, there are no time delays processes the clock failure trap, the FRC involved in wake-up from Idle. oscillator is enabled and the user will have to re-enable the crystal oscillator. If FSCM 20.8 Device Configuration Registers is not enabled, the device simply suspends execution of code until the clock is stable The Configuration bits in each device Configuration and remain in Sleep until the oscillator clock register specify some of the device modes and are has started. programmed by a device programmer, or by using the All Resets wake up the processor from Sleep mode. In-Circuit Serial Programming™ (ICSP™) feature of Any Reset, other than POR, sets the Sleep status bit. the device. Each device Configuration register is a In a POR, the SLEEP bit is cleared. 24-bit register, but only the lower 16 bits of each regis- ter are used to hold configuration data. There are five If the Watchdog Timer is enabled, the processor wakes device Configuration registers available to the user: up from Sleep mode upon WDT time-out. The SLEEP and WDTO status bits are both set. 1. FOSC (0xF80000): Oscillator Configuration Register 20.7.2 IDLE MODE 2. FWDT (0xF80002): Watchdog Timer In Idle mode, the clock to the CPU is shut down while Configuration Register peripherals keep running. Unlike Sleep mode, the clock 3. FBORPOR (0xF80004): BOR and POR source remains active. Configuration Register Several peripherals have a control bit in each module 4. FGS (0xF8000A): General Code Segment that allows them to operate during Idle. Configuration Register 5. FICD (0xF8000C): Debug Configuration The LPRC fail-safe clock remains active if clock failure Register detect is enabled. The placement of the Configuration bits is automati- The processor wakes up from Idle if at least one of the cally handled when you select the device in your device following conditions has occurred: programmer. The desired state of the Configuration bits • any interrupt that is individually enabled (IE bit is may be specified in the source code (dependent on the ‘1’) and meets the required priority level language tool used), or through the programming • any Reset (POR, BOR, MCLR) interface. After the device has been programmed, the • WDT time-out application software may read the Configuration bit values through the table read instructions. For Upon wake-up from Idle mode, the clock is re-applied additional information, please refer to the Programming to the CPU and instruction execution begins immedi- Specifications of the device. ately, starting with the instruction following the PWRSAV instruction. Note: If the code protection Configuration fuse bits (FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages VDD  4.5V. DS70138G-page 156  2010 Microchip Technology Inc.

dsPIC30F3014/4013 20.9 Peripheral Module Disable (PMD) 20.10 In-Circuit Debugger Registers When MPLAB® ICD 2 is selected as a debugger, the in- The Peripheral Module Disable (PMD) registers circuit debugging functionality is enabled. This function provide a method to disable a peripheral module by allows simple debugging functions when used with stopping all clock sources supplied to that module. MPLAB IDE. When the device has this feature enabled, When a peripheral is disabled via the appropriate PMD some of the resources are not available for general control bit, the peripheral is in a minimum power use. These resources include the first 80 bytes of data consumption state. The control and status registers RAM and two I/O pins. associated with the peripheral are also disabled so One of four pairs of debug I/O pins may be selected by writes to those registers have no effect and read values the user using configuration options in MPLAB IDE. are invalid. These pin pairs are named EMUD/EMUC, EMUD1/ A peripheral module is only enabled if both the EMUC1, EMUD2/EMUC2 and MUD3/EMUC3. associated bit in the PMD register is cleared and the In each case, the selected EMUD pin is the Emulation/ peripheral is supported by the specific dsPIC DSC vari- Debug Data line, and the EMUC pin is the Emulation/ ant. If the peripheral is present in the device, it is Debug Clock line. These pins interface to the MPLAB enabled in the PMD register by default. ICD 2 module available from Microchip. The selected pair of debug I/O pins is used by MPLAB ICD2 to send Note1: If a PMD bit is set, the corresponding commands and receive responses, as well as to send module is disabled after a delay of 1 and receive data. To use the in-circuit debugger instruction cycle. Similarly, if a PMD bit is function of the device, the design must implement ICSP cleared, the corresponding module is enabled after a delay of 1 instruction connections to MCLR, VDD, VSS, PGC, PGD and the selected EMUDx/EMUCx pin pair. cycle (assuming the module control reg- isters are already configured to enable This gives rise to two possibilities: module operation). 1. If EMUD/EMUC is selected as the debug I/O pin 2: In the dsPIC30F3014 device, the T4MD, pair, then only a 5-pin interface is required, as T5MD, IC7MD, IC8MD, OC3MD, the EMUD and EMUC pin functions are multi- OC4MD and DCIMD are readable and plexed with the PGD and PGC pin functions in writable, and are read as “1” when set. all dsPIC30F devices. 2. If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/ EMUC3 is selected as the debug I/O pin pair, then a 7-pin interface is required, as the EMUDx/EMUCx pin functions (x = 1, 2 or 3) are not multiplexed with the PGD and PGC pin functions.  2010 Microchip Technology Inc. DS70138G-page 157

D TABLE 20-7: SYSTEM INTEGRATION REGISTER MAP(1) d S 70 SFR s 1 Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 3 Name P 8 G -p RCON 0740 TRAPR IOPUWR BGST LVDEN LVDL<3:0> EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR (Note 2) I a C g OSCCON 0742 — COSC<2:0> — NOSC<2:0> POST<1:0> LOCK — CF — LPOSCEN OSWEN (Note 3) e 1 OSCTUN 0744 — — — — — — — — — — — — TUN3 TUN2 TUN1 TUN0 0000 0000 0000 0000 3 5 8 PMD1 0770 T5MD(4) T4MD(4) T3MD T2MD T1MD — — DCIMD(4) I2CMD U2MD U1MD — SPI1MD — C1MD ADCMD 0000 0000 0000 0000 0 PMD2 0772 IC8MD(4) IC7MD(4) — — — — IC2MD IC1MD — — — — OC4MD(4) OC3MD(4) OC2MD OC1MD 0000 0000 0000 0000 F Legend: — = unimplemented bit, read as ‘0’ 3 Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 0 2: Reset state depends on type of Reset. 3: Reset state depends on Configuration bits. 1 4: These bits are not available in dsPIC30F3014 devices. 4 / TABLE 20-8: DEVICE CONFIGURATION REGISTER MAP(1) 4 0 Name Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 FOSC F80000 FCKSM<1:0> — — — FOS<2:0> — — — FPR<4:0> 3 FWDT F80002 FWDTEN — — — — — — — — — FWPSA<1:0> FWPSB<3:0> FBORPOR F80004 MCLREN — — — — PWMPIN(2) HPOL(2) LPOL(2) BOREN — BORV<1:0> — — FPWRT<1:0> FBS F80006 — — Reserved(3) — — — Reserved(3) — — — — Reserved(3) FSS F80008 — — Reserved(3) — — Reserved(3) — — — — Reserved(3) FGS F8000A — — — — — — — — — — — — — Reserved(4) GCP GWRP FICD F8000C BKBUG COE — — — — — — — — — — — — ICS<1:0> Legend: — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 2: These bits are reserved (read as ‘1’ and must be programmed as ‘1’). 3: Reserved bits read as ‘1’ and must be programmed as ‘1’. 4: The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).  2 0 1 0 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F3014/4013 21.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: Note: This data sheet summarizes features of • The W register (with or without an address this group ofdsPIC30F devices and is not modifier) or file register (specified by the value of intended to be a complete reference ‘Ws’ or ‘f’) source. For more information on the CPU, • The bit in the W register or file register peripherals, register descriptions and (specified by a literal value or indirectly by the general device functionality, refer to the contents of register ‘Wb’) “dsPIC30F Family Reference Manual” (DS70046). For more information on the The literal instructions that involve data movement may device instruction set and programming, use some of the following operands: refer to the “16-bit MCU and DSC Pro- • A literal value to be loaded into a W register or file grammer’s Reference Manual” register (specified by the value of ‘k’) (DS70157). • The W register or file register where the literal The dsPIC30F instruction set adds many value is to be loaded (specified by ‘Wb’ or ‘f’) enhancements to the previous PIC® MCU instruction However, literal instructions that involve arithmetic or sets, while maintaining an easy migration from PIC logical operations use some of the following operands: MCU instruction sets. • The first source operand which is a register ‘Wb’ Most instructions are a single program memory word without any address modifier (24 bits). Only three instructions require two program • The second source operand which is a literal memory locations. value Each single-word instruction is a 24-bit word divided • The destination of the result (only if not the same into an 8-bit opcode which specifies the instruction as the first source operand) which is typically a type, and one or more operands which further specify register ‘Wd’ with or without an address modifier the operation of the instruction. The MAC class of DSP instructions may use some of the The instruction set is highly orthogonal and is grouped following operands: into five basic categories: • The accumulator (A or B) to be used (required • Word or byte-oriented operations operand) • Bit-oriented operations • The W registers to be used as the two operands • Literal operations • The X and Y address space prefetch operations • DSP operations • The X and Y address space prefetch destinations • Control operations • The accumulator write-back destination Table21-1 shows the general symbols used in The other DSP instructions do not involve any describing the instructions. multiplication, and may include: The dsPIC30F instruction set summary in Table21-2 • The accumulator to be used (required) lists all the instructions, along with the status flags • The source or destination operand (designated as affected by each instruction. Wso or Wdo, respectively) with or without an Most word or byte-oriented W register instructions address modifier (including barrel shift instructions) have three • The amount of shift specified by a W register ‘Wn’ operands: or a literal value • The first source operand which is typically a The control instructions may use some of the following register ‘Wb’ without any address modifier operands: • The second source operand which is typically a • A program memory address register ‘Ws’ with or without an address modifier • The mode of the table read and table write • The destination of the result which is typically a instructions register ‘Wd’ with or without an address modifier All instructions are a single word, except for certain However, word or byte-oriented file register instructions double word instructions, which were made double have two operands: word instructions so that all the required information is • The file register specified by the value ‘f’ available in these 48 bits. In the second word, the • The destination, which could either be the file 8MSbs are ‘0’s. If this second word is executed as an register ‘f’ or the W0 register, which is denoted as instruction (by itself), it executes as a NOP. ‘WREG’  2010 Microchip Technology Inc. DS70138G-page 159

dsPIC30F3014/4013 Most single-word instructions are executed in a single two or three cycles if the skip is performed, depending instruction cycle, unless a conditional test is true or on whether the instruction being skipped is a single- theprogram counter is changed as a result of the word or two-word instruction. Moreover, double-word instruction. In these cases, the execution takes two moves require two cycles. The double-word instruction cycles with the additional instruction instructions execute in two instruction cycles. cycle(s) executed as a NOP. Notable exceptions are the Note: For more details on the instruction set, BRA (unconditional/computed branch), indirect CALL/ refer to the “16-bit DSC and MCU Pro- GOTO, all table reads and writes, and RETURN/RETFIE grammer’s Reference Manual” instructions, which are single-word instructions but take (DS70157). two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator Write-Back Destination Address register {W13, [W13]+=2} bit4 4-bit bit selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0x0000...0x1FFF} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; LSB must be 0 None Field does not require an entry, may be blank OA, OB, SA, SB DSP Status bits: AccA Overflow, AccB Overflow, AccA Saturate, AccB Saturate PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} DS70138G-page 160  2010 Microchip Technology Inc.

dsPIC30F3014/4013 TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor Working register pair (direct addressing) Wm*Wm Multiplicand and Multiplier working register pair for Square instructions  {W4*W4,W5*W5,W6*W6,W7*W7} Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions  {W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7} Wn One of 16 working registers {W0..W15} Wnd One of 16 destination working registers {W0..W15} Wns One of 16 source working registers {W0..W15} WREG W0 (working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register  { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wx X data space prefetch address register for DSP instructions {[W8]+=6, [W8]+=4, [W8]+=2, [W8], [W8]-=6, [W8]-=4, [W8]-=2, [W9]+=6, [W9]+=4, [W9]+=2, [W9], [W9]-=6, [W9]-=4, [W9]-=2, [W9+W12],none} Wxd X data space prefetch destination register for DSP instructions {W4..W7} Wy Y data space prefetch address register for DSP instructions {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Wyd Y data space prefetch destination register for DSP instructions {W4..W7}  2010 Microchip Technology Inc. DS70138G-page 161

dsPIC30F3014/4013 TABLE 21-2: INSTRUCTION SET OVERVIEW Base Assembly # of # of Status Flags Instr Mnemoni Assembly Syntax Description Words Cycles Affected # c 1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB 2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z 3 AND AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z 4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z 5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None 6 BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None BRA LE,Expr Branch if Less than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None BRA LT,Expr Branch if Less than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OA,Expr Branch if Accumulator A Overflow 1 1 (2) None BRA OB,Expr Branch if Accumulator B Overflow 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA SA,Expr Branch if Accumulator A Saturated 1 1 (2) None BRA SB,Expr Branch if Accumulator B Saturated 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None 7 BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None 8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None DS70138G-page 162  2010 Microchip Technology Inc.

dsPIC30F3014/4013 TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemoni Assembly Syntax Description Words Cycles Affected # c 9 BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None 10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3) 11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) 12 BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z 13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z 14 CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB 16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO, Sleep 17 COM COM f f = f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z 18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z 19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z 20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z (Wb – Ws – C) 21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, Skip if = 1 1 None (2 or 3) 22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, Skip if > 1 1 None (2 or 3) 23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, Skip if < 1 1 None (2 or 3) 24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, Skip if  1 1 None (2 or 3) 25 DAW DAW Wn Wn = Decimal Adjust Wn 1 1 C 26 DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z 27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z 28 DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None  2010 Microchip Technology Inc. DS70138G-page 163

dsPIC30F3014/4013 TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemoni Assembly Syntax Description Words Cycles Affected # c 29 DIV DIV.S Wm,Wn Signed 16/16-Bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-Bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-Bit Integer Divide 1 18 N,Z,C,OV DIV.UD Wm,Wn Unsigned 32/16-Bit Integer Divide 1 18 N,Z,C,OV 30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV 31 DO DO #lit14,Expr Do Code to PC+Expr, lit14 + 1 Times 2 2 None DO Wn,Expr Do Code to PC+Expr, (Wn) + 1 Times 2 2 None 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indirect 1 2 None 39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z 41 IOR IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 43 LNK LNK #lit14 Link Frame Pointer 1 1 None 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z 45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply and Accumulate 1 1 OA,OB,OAB, , SA,SB,SAB AWB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB 46 MOV MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 N,Z MOV f,WREG Move f to WREG 1 1 N,Z MOV #lit16,Wn Move 16-Bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-Bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N,Z MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None 47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and Store Accumulator 1 1 None DS70138G-page 164  2010 Microchip Technology Inc.

dsPIC30F3014/4013 TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemoni Assembly Syntax Description Words Cycles Affected # c 48 MPY MPY Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, Wm*Wn,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB MPY Square Wm to Accumulator 1 1 OA,OB,OAB, Wm*Wm,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB 49 MPY.N MPY.N -(Multiply Wm by Wn) to Accumulator 1 1 None Wm*Wn,Acc,Wx,Wxd,Wy,Wyd 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, , SA,SB,SAB AWB 51 MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * 1 1 None Unsigned(Ws) MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * 1 1 None Signed(Ws) MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * 1 1 None Unsigned(Ws) MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * 1 1 None Unsigned(lit5) MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * 1 1 None Unsigned(lit5) MUL f W3:W2 = f * WREG 1 1 None 52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f = f + 1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 53 NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None 54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None W(nd):W(nd+1) POP.S Pop Shadow Registers 1 1 All 55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None 56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep 57 RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None 58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14+1 Times 1 1 None REPEAT Wn Repeat Next Instruction (Wn)+1 Times 1 1 None 59 RESET RESET Software Device Reset 1 1 None 60 RETFIE RETFIE Return from Interrupt 1 3 (2) None 61 RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None 62 RETURN RETURN Return from Subroutine 1 3 (2) None 63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z 64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z 65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z  2010 Microchip Technology Inc. DS70138G-page 165

dsPIC30F3014/4013 TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Mnemoni Assembly Syntax Description Words Cycles Affected # c 66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None 68 SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C,N,Z 69 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None 70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB 71 SL SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z 72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f – WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z 73 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z 74 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG– f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z 75 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z 76 SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None 77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None 78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None 79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 81 ULNK ULNK Unlink Frame Pointer 1 1 None 82 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z 83 ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C,Z,N DS70138G-page 166  2010 Microchip Technology Inc.

dsPIC30F3014/4013 22.0 DEVELOPMENT SUPPORT 22.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2010 Microchip Technology Inc. DS70138G-page 167

dsPIC30F3014/4013 22.2 MPLAB C Compilers for Various 22.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 22.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 22.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 22.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS70138G-page 168  2010 Microchip Technology Inc.

dsPIC30F3014/4013 22.7 MPLAB SIM Software Simulator 22.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 22.10 PICkit 3 In-Circuit Debugger/ Programmer and 22.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.  2010 Microchip Technology Inc. DS70138G-page 169

dsPIC30F3014/4013 22.11 PICkit 2 Development 22.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 22.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS70138G-page 170  2010 Microchip Technology Inc.

dsPIC30F3014/4013 23.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. For detailed information about the dsPIC30F architecture and core, refer to the “dsPIC30F Family Reference Manual” (DS70046). Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR) (Note 1).....................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V Voltage on MCLR with respect to VSS .......................................................................................................0V to +13.25V Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin (Note 2)................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports (Note 2)....................................................................................................200 mA Note1: Voltage spikes below Vss at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100W should be used when applying a “low” level to the MCLR/VPP pin, rather than pulling this pin directly to Vss. 2: Maximum allowable current is a function of device maximum power dissipation. See Table23-4 †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific devices, please refer to the dsPIC30F3014/4013 Controller Family table.  2010 Microchip Technology Inc. DS70138G-page 171

dsPIC30F3014/4013 23.1 DC Characteristics TABLE 23-1: OPERATING MIPS vs. VOLTAGE Max MIPS VDD Range Temp Range dsPIC30FXXX-30I dsPIC30FXXX-20E 4.5-5.5V -40°C to 85°C 30 — 4.5-5.5V -40°C to 125°C — 20 3.0-3.6V -40°C to 85°C 15 — 3.0-3.6V -40°C to 125°C — 10 2.5-3.0V -40°C to 85°C 10 — TABLE 23-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit dsPIC30F3014-30I dsPIC30F4013-30I Operating Junction Temperature Range T -40 — +125 °C J Operating Ambient Temperature Range T -40 — +85 °C A dsPIC30F3014-20E dsPIC30F4013-20E Operating Junction Temperature Range T -40 — +150 °C J Operating Ambient Temperature Range T -40 — +125 °C A Power Dissipation: Internal chip power dissipation: PINT = VDDIDD– IOH PD PINT + PI/O W I/O Pin power dissipation: PI/O=  VDD–VOHIOH+ VOLIOL Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W TABLE 23-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes Package Thermal Resistance, 40-pin DIP (P) JA — 47 °C/W 1 Package Thermal Resistance, 44-pin TQFP (10x10x1mm) JA — 39.3 °C/W 1 Package Thermal Resistance, 44-pin QFN JA — 27.8 °C/W 1 Note 1: Junction to ambient thermal resistance, Theta-ja (JA) numbers are achieved by package simulations. DS70138G-page 172  2010 Microchip Technology Inc.

dsPIC30F3014/4013 T ABLE 23-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Operating Voltage(2) DC10 VDD Supply Voltage 2.5 — 5.5 V Industrial temperature DC11 VDD Supply Voltage 3.0 — 5.5 V Extended temperature DC12 VDR RAM Data Retention Voltage(3) 1.75 — — V DC16 VPOR VDD Start Voltage — — VSS V to Ensure Internal Power-on Reset Signal DC17 SVDD VDD Rise Rate 0.05 — — V/ms 0-5V in 0.1 sec to Ensure Internal 0-3V in 60 ms Power-on Reset Signal Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which VDD can be lowered without losing RAM data.  2010 Microchip Technology Inc. DS70138G-page 173

dsPIC30F3014/4013 T ABLE 23-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Typical Max Units Conditions No. Operating Current (IDD)(1) DC31a 2 4 mA 25°C DC31b 2 4 mA 85°C 3.3V DC31c 2 4 mA 125°C 0.128 MIPS DC31e 4 6 mA 25°C LPRC (512 kHz) DC31f 4 6 mA 85°C 5V DC31g 4 6 mA 125°C DC30a 6 11 mA 25°C DC30b 6 11 mA 85°C 3.3V DC30c 7 11 mA 125°C 1.8 MIPS DC30e 11 16 mA 25°C FRC (7.37 MHz) DC30f 11 16 mA 85°C 5V DC30g 11 16 mA 125°C DC23a 13 20 mA 25°C DC23b 13 20 mA 85°C 3.3V DC23c 14 20 mA 125°C 4 MIPS DC23e 22 31 mA 25°C DC23f 22 31 mA 85°C 5V DC23g 22 31 mA 125°C DC24a 27 39 mA 25°C DC24b 28 39 mA 85°C 3.3V DC24c 28 39 mA 125°C 10 MIPS DC24e 46 64 mA 25°C DC24f 46 64 mA 85°C 5V DC24g 46 64 mA 125°C DC27d 86 120 mA 25°C DC27e 85 120 mA 85°C 5V 20 MIPS DC27f 85 120 mA 125°C DC29a 123 170 mA 25°C 5V 30 MIPS DC29b 122 170 mA 85°C Note 1: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail-to-rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating. DS70138G-page 174  2010 Microchip Technology Inc.

dsPIC30F3014/4013 T ABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Typical Max Units Conditions No. Operating Current (IDD)(1) DC51a 1.4 3 mA 25°C DC51b 1.5 3 mA 85°C 3.3V DC51c 1.5 3 mA 125°C 0.128 MIPS DC51e 3 5 mA 25°C LPRC (512 kHz) DC51f 3 5 mA 85°C 5V DC51g 3 5 mA 125°C DC50a 4 6 mA 25°C DC50b 4 6 mA 85°C 3.3V DC50c 4 6 mA 125°C 1.8 MIPS DC50e 8 11 mA 25°C FRC (7.37 MHz) DC50f 8 11 mA 85°C 5V DC50g 8 11 mA 125°C DC43a 7 11 mA 25°C DC43b 7 11 mA 85°C 3.3V DC43c 8 11 mA 125°C 4 MIPS DC43e 13 17 mA 25°C DC43f 13 17 mA 85°C 5V DC43g 13 17 mA 125°C DC44a 16 22 mA 25°C DC44b 16 22 mA 85°C 3.3V DC44c 17 22 mA 125°C 10 MIPS DC44e 27 36 mA 25°C DC44f 27 36 mA 85°C 5V DC44g 28 36 mA 125°C DC47d 50 65 mA 25°C DC47e 51 65 mA 85°C 5V 20 MIPS DC47f 52 65 mA 125°C DC49a 74 95 mA 25°C 5V 30 MIPS DC49b 75 95 mA 85°C Note 1: Base IIDLE current is measured with core off, clock on and all modules turned off.  2010 Microchip Technology Inc. DS70138G-page 175

dsPIC30F3014/4013 TABLE 23-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Typical Max Units Conditions No. Power-Down Current (IPD)(1) DC60a 1 — A 25°C DC60b 3 30 A 85°C 3.3V DC60c 30 60 A 125°C Base Power-Down Current(2) DC60e 2 — A 25°C DC60f 6 45 A 85°C 5V DC60g 55 90 A 125°C DC61a 7 11 A 25°C DC61b 7 11 A 85°C 3.3V DC61c 7 11 A 125°C Watchdog Timer Current: IWDT(2) DC61e 14 21 A 25°C DC61f 14 21 A 85°C 5V DC61g 14 21 A 125°C DC62a — — A 25°C DC62b — — A 85°C 3.3V DC62c — — A 125°C Timer1 w/32 kHz Crystal: ITI32(2) DC62e — — A 25°C DC62f — — A 85°C 5V DC62g 30 45 A 125°C DC63a 30 45 A 25°C DC63b 33 50 A 85°C 3.3V DC63c 34 51 A 125°C BOR on: IBOR(2) DC63e 34 51 A 25°C DC63f 37 56 A 85°C 5V DC63g 37 56 A 125°C DC66a 18 27 A 25°C DC66b 20 30 A 85°C 3.3V DC66c 21 32 A 125°C Low-Voltage Detect: ILVD(2) DC66e 22 33 A 25°C DC66f 23 35 A 85°C 5V DC66g 24 36 A 125°C Note 1: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. LVD, BOR, WDT, etc. are all switched off. 2: The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. DS70138G-page 176  2010 Microchip Technology Inc.

dsPIC30F3014/4013 TABLE 23-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VIL Input Low Voltage(2) DI10 I/O Pins: with Schmitt Trigger Buffer VSS — 0.2VDD V DI15 MCLR VSS — 0.2VDD V DI16 OSC1 (in XT, HS and LP modes) VSS — 0.2VDD V DI17 OSC1 (in RC mode)(3) VSS — 0.3VDD V DI18 SDA, SCL VSS — 0.3VDD V SM bus disabled DI19 SDA, SCL VSS — 0.8 V SM bus enabled VIH Input High Voltage(2) DI20 I/O Pins: with Schmitt Trigger Buffer 0.8VDD — VDD V DI25 MCLR 0.8VDD — VDD V DI26 OSC1 (in XT, HS and LP modes) 0.7VDD — VDD V DI27 OSC1 (in RC mode)(3) 0.9VDD — VDD V DI28 SDA, SCL 0.7VDD — VDD V SM bus disabled DI29 SDA, SCL 2.1 — VDD V SM bus enabled ICNPU CNXX Pull-up Current(2) DI30 50 250 400 A VDD = 5V, VPIN = VSS IIL Input Leakage Current(2,4,5) DI50 I/O Ports — 0.01 ±1 A VSS  VPIN  VDD, Pin at high-impedance DI51 Analog Input Pins — 0.50 — A VSS  VPIN  VDD, Pin at high-impedance DI55 MCLR — 0.05 ±5 A VSS VPIN VDD DI56 OSC1 — 0.05 ±5 A VSS VPIN VDD, XT, HS and LP Osc mode Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that the dsPIC30F device be driven with an external clock while in RC mode. 4: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin.  2010 Microchip Technology Inc. DS70138G-page 177

dsPIC30F3014/4013 TABLE 23-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VOL Output Low Voltage(2) DO10 I/O Ports — — 0.6 V IOL = 8.5 mA, VDD = 5V — — 0.15 V IOL = 2.0 mA, VDD = 3V DO16 OSC2/CLKO — — 0.6 V IOL = 1.6 mA, VDD = 5V (RC or EC Oscillator mode) — — 0.72 V IOL = 2.0 mA, VDD = 3V VOH Output High Voltage(2) DO20 I/O Ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 5V VDD – 0.2 — — V IOH = -2.0 mA, VDD = 3V DO26 OSC2/CLKO VDD – 0.7 — — V IOH = -1.3 mA, VDD = 5V (RC or EC Oscillator mode) VDD – 0.1 — — V IOH = -2.0 mA, VDD = 3V Capacitive Loading Specs on Output Pins(2) DO50 COSC2 OSC2/SOSC2 Pin — — 15 pF In XTL, XT, HS and LP modes when external clock is used to drive OSC1. DO56 CIO All I/O Pins and OSC2 — — 50 pF RC or EC Oscillator mode DO58 CB SCL, SDA — — 400 pF In I2C mode Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. FIGURE 23-1: LOW-VOLTAGE DETECT CHARACTERISTICS VDD LV10 LVDIF (LVDIF set by hardware) DS70138G-page 178  2010 Microchip Technology Inc.

dsPIC30F3014/4013 TABLE 23-10: ELECTRICAL CHARACTERISTICS: LVDL Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. LV10 VPLVD LVDL Voltage on VDD LVDL = 0000(2) — — — V Transition High-to-Low LVDL = 0001(2) — — — V LVDL = 0010(2) — — — V LVDL = 0011(2) — — — V LVDL = 0100 2.50 — 2.65 V LVDL = 0101 2.70 — 2.86 V LVDL = 0110 2.80 — 2.97 V LVDL = 0111 3.00 — 3.18 V LVDL = 1000 3.30 — 3.50 V LVDL = 1001 3.50 — 3.71 V LVDL = 1010 3.60 — 3.82 V LVDL = 1011 3.80 — 4.03 V LVDL = 1100 4.00 — 4.24 V LVDL = 1101 4.20 — 4.45 V LVDL = 1110 4.50 — 4.77 V LV15 VLVDIN External LVD Input Pin LVDL = 1111 — — — V Threshold Voltage Note 1: These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. FIGURE 23-2: BROWN-OUT RESET CHARACTERISTICS VDD (Device not in Brown-out Reset) BO15 BO10 (Device in Brown-out Reset) RESET (due to BOR) Power-up Time-out  2010 Microchip Technology Inc. DS70138G-page 179

dsPIC30F3014/4013 TABLE 23-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. BO10 VBOR BOR Voltage on VDD BORV = 11(3) — — — V Not in operating Transition range High-to-Low(2) BORV = 10 2.6 — 2.71 V BORV = 01 4.1 — 4.4 V BORV = 00 4.58 — 4.73 V BO15 VBHYS — 5 — mV Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: ‘11’ values not in usable operating range. TABLE 23-12: DC CHARACTERISTICS: PROGRAM AND EEPROM Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Data EEPROM Memory(2) D120 ED Byte Endurance 100K 1M — E/W -40C  TA +85°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time 0.8 2 2.6 ms RTSP D123 TRETD Characteristic Retention 40 100 — Year Provided no other specifications are violated D124 IDEW IDD During Programming — 10 30 mA Row Erase Program Flash Memory(2) D130 EP Cell Endurance 10K 100K — E/W -40C  TA +85°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VEB VDD for Bulk Erase 4.5 — 5.5 V D133 VPEW VDD for Erase/Write 3.0 — 5.5 V D134 TPEW Erase/Write Cycle Time 0.8 2 2.6 ms RTSP D135 TRETD Characteristic Retention 40 100 — Year Provided no other specifications are violated D137 IPEW IDD During Programming — 10 30 mA Row Erase D138 IEB IDD During Programming — 10 30 mA Bulk Erase Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. 23.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. DS70138G-page 180  2010 Microchip Technology Inc.

dsPIC30F3014/4013 TABLE 23-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Operating voltage VDD range as described in Table23-1. FIGURE 23-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 RL Pin CL VSS Legend: CL Pin RL = 464 CL = 50 pF for all pins except OSC2 VSS 5 pF for OSC2 output FIGURE 23-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS40 OS41  2010 Microchip Technology Inc. DS70138G-page 181

dsPIC30F3014/4013 T ABLE 23-14: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS10 FOSC External CLKI Frequency DC — 40 MHz EC (external clocks allowed 4 — 10 MHz EC with 4x PLL only in EC mode)(2) 4 — 10 MHz EC with 8x PLL 4 — 7.5(3) MHz EC with 16x PLL Oscillator Frequency(2) DC — 4 MHz RC 0.4 — 4 MHz XTL 4 — 10 MHz XT 4 — 10 MHz XT with 4x PLL 4 — 10 MHz XT with 8x PLL 4 — 7.5(3) MHz XT with 16x PLL 10 — 25 MHz HS 10 — 20(4) MHz HS/2 with 4x PLL 10 — 20(4) MHz HS/2 with 8x PLL 10 — 15(3) MHz HS/2 with 16x PLL 12(4) — 25 MHz HS/3 with 4x PLL 12(4) — 25 MHz HS/3 with 8x PLL 12(4) — 22.5(3) MHz HS/3 with 16x PLL — 32.768 — kHz LP OS20 TOSC TOSC = 1/FOSC — — — — See parameter OS10 for FOSC value OS25 TCY Instruction Cycle Time(2,5) 33 — DC ns See Table23-16 OS30 TosL, External Clock in (OSC1) .45 x TOSC — — ns EC TosH High or Low Time(2) OS31 TosR, External Clock in (OSC1) — — 20 ns EC TosF Rise or Fall Time(2) OS40 TckR CLKO Rise Time(2,6) — — — ns See parameter DO31 OS41 TckF CLKO Fall Time(2,6) — — — ns See parameter DO32 Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: Limited by the PLL output frequency range. 4: Limited by the PLL input frequency range. 5: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. 6: Measurements are taken in EC or ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). DS70138G-page 182  2010 Microchip Technology Inc.

dsPIC30F3014/4013 TABLE 23-15: PLL JITTER Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA +85°C for Industrial -40°C  TA +125°C for Extended Param Characteristic Min Typ(1) Max Units Conditions No. OS61 x4 PLL — 0.251 0.413 % -40°C  TA +85°C VDD = 3.0 to 3.6V — 0.251 0.413 % -40°C  TA +125°C VDD = 3.0 to 3.6V — 0.256 0.47 % -40°C  TA +85°C VDD = 4.5 to 5.5V — 0.256 0.47 % -40°C  TA +125°C VDD = 4.5 to 5.5V x8 PLL — 0.355 0.584 % -40°C  TA +85°C VDD = 3.0 to 3.6V — 0.355 0.584 % -40°C  TA +125°C VDD = 3.0 to 3.6V — 0.362 0.664 % -40°C  TA +85°C VDD = 4.5 to 5.5V — 0.362 0.664 % -40°C  TA +125°C VDD = 4.5 to 5.5V x16 PLL — 0.67 0.92 % -40°C  TA +85°C VDD = 3.0 to 3.6V — 0.632 0.956 % -40°C  TA +85°C VDD = 4.5 to 5.5V — 0.632 0.956 % -40°C  TA +125°C VDD = 4.5 to 5.5V Note 1: These parameters are characterized but not tested in manufacturing. TABLE 23-16: INTERNAL CLOCK TIMING EXAMPLES Clock Oscillator (MFHOzS)C(1 ) TCY (sec)(2) w/oM PIPLSL(3) w/PMLILP Sx4(3) w/PMLILP Sx8(3) w/PMLLIP xS16(3) Mode EC 0.200 20.0 0.05 — — — 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 — 25 0.16 6.25 — — — XT 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 — Note 1: Assumption: Oscillator Postscaler is divide by 1. 2: Instruction Execution Cycle Time: TCY = 1/MIPS. 3: Instruction Execution Frequency: MIPS = (FOSC * PLLx)/4 [since there are 4 Q clocks per instruction cycle].  2010 Microchip Technology Inc. DS70138G-page 183

dsPIC30F3014/4013 T ABLE 23-17: AC CHARACTERISTICS: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA +85°C for Industrial -40°C  TA +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. Internal FRC Accuracy @ FRC Freq. = 7.37 MHz(1) OS63 FRC — — ±2.00 % -40°C  TA +85°C VDD = 3.0-5.5V — — ±5.00 % -40°C  TA +125°C VDD = 3.0-5.5V Note 1: Frequency calibrated at 7.372 MHz ±2%, 25°C and 5V. TUN bits (OSCCON<3:0>) can be used to compensate for temperature drift. TABLE 23-18: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. LPRC @ Freq. = 512 kHz(1) OS65A -50 — +50 % VDD = 5.0V, ±10% OS65B -60 — +60 % VDD = 3.3V, ±10% OS65C -70 — +70 % VDD = 2.5V Note 1: Change of LPRC frequency as VDD changes. DS70138G-page 184  2010 Microchip Technology Inc.

dsPIC30F3014/4013 FIGURE 23-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure23-3 for load conditions. TABLE 23-19: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1,2,3) Min Typ(4) Max Units Conditions No. DO31 TIOR Port Output Rise Time — 7 20 ns DO32 TIOF Port Output Fall Time — 7 20 ns DI35 TINP INTx Pin High or Low Time (output) 20 — — ns DI40 TRBP CNx High or Low Time (input) 2 TCY — — ns Note 1: These parameters are asynchronous events not related to any internal clock edges 2: Measurements are taken in RC mode and EC mode where CLKO output is 4 x TOSC. 3: These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated.  2010 Microchip Technology Inc. DS70138G-page 185

dsPIC30F3014/4013 FIGURE 23-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD SY12 MCLR Internal SY10 POR SY11 PWRT Time-out SY30 Oscillator Time-out Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure23-3 for load conditions. DS70138G-page 186  2010 Microchip Technology Inc.

dsPIC30F3014/4013 T ABLE 23-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SY10 TmcL MCLR Pulse Width (low) 2 — — s -40°C to +85°C SY11 TPWRT Power-up Timer Period 2 4 8 ms -40°C to +85°C, 10 16 32 VDD = 5V 43 64 128 User programmable SY12 TPOR Power-on Reset Delay 3 10 30 s -40°C to +85°C SY13 TIOZ I/O High-Impedance from MCLR — 0.8 1.0 s Low or Watchdog Timer Reset SY20 TWDT1 Watchdog Timer Time-out Period 1.1 2.0 6.6 ms VDD = 2.5V TWDT2 (no prescaler) 1.2 2.0 5.0 ms VDD = 3.3V, ±10% TWDT3 1.3 2.0 4.0 ms VDD = 5V, ±10% SY25 TBOR Brown-out Reset Pulse Width(3) 100 — — s VDD VBOR (D034) SY30 TOST Oscillator Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 900 s -40°C to +85°C Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure23-2 and Table23-11 for BOR. FIGURE 23-7: BAND GAP START-UP TIME CHARACTERISTICS VBGAP 0V Enable Band Gap(1) Band Gap SY40 Stable Note 1: Note: Set LVDEN bit (RCON<12>) or FBORPOR<7>set. TABLE 23-21: BAND GAP START-UP TIME REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SY40 TBGAP Band Gap Start-up Time — 40 65 s Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable (RCON<13> status bit) Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.  2010 Microchip Technology Inc. DS70138G-page 187

dsPIC30F3014/4013 FIGURE 23-8: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRX Note: Refer to Figure23-3 for load conditions. TABLE 23-22: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TA10 TTXH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TA15 Synchronous, 10 — — ns with prescaler Asynchronous 10 — — ns TA11 TTXL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TA15 Synchronous, 10 — — ns with prescaler Asynchronous 10 — — ns TA15 TTXP TxCK Input Period Synchronous, TCY + 10 — — ns no prescaler Synchronous, Greater of: — — — N = prescale with prescaler 20 ns or value (TCY + 40)/N (1, 8, 64, 256) Asynchronous 20 — — ns OS60 Ft1 SOSC1/T1CK Oscillator Input DC — 50 kHz Frequency Range (oscillator enabled by setting bit, TCS (T1CON<1>) TA20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — Edge to Timer Increment Note 1: Timer1 is a Type A. DS70138G-page 188  2010 Microchip Technology Inc.

dsPIC30F3014/4013 T ABLE 23-23: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TB10 TtxH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TB15 Synchronous, 10 — — ns with prescaler TB11 TtxL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TB15 Synchronous, 10 — — ns with prescaler TB15 TtxP TxCK Input Period Synchronous, TCY + 10 — — ns N = prescale no prescaler value Synchronous, Greater of: (1, 8, 64, 256) with prescaler 20 ns or (TCY + 40)/N TB20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — Edge to Timer Increment Note 1: Timer2 and Timer4 are Type B. TABLE 23-24: TYPE C TIMER (TIMER3 AND TIMER5) EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet parameter TC15 TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet parameter TC15 TC15 TtxP TxCK Input Period Synchronous, TCY + 10 — — ns N = prescale no prescaler value Synchronous, Greater of: (1, 8, 64, 256) with prescaler 20 ns or (TCY + 40)/N TC20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 — Edge to Timer Increment TCY Note 1: Timer3 and Timer5 are Type C.  2010 Microchip Technology Inc. DS70138G-page 189

dsPIC30F3014/4013 FIGURE 23-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICX IC10 IC11 IC15 Note: Refer to Figure23-3 for load conditions. TABLE 23-25: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Max Units Conditions No. IC10 TccL ICx Input Low Time No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns IC11 TccH ICx Input High Time No prescaler 0.5 TCY + 20 — ns With prescaler 10 — ns IC15 TccP ICx Input Period (2 TCY + 40)/N — ns N = prescale value (1, 4, 16) Note 1: These parameters are characterized but not tested in manufacturing. FIGURE 23-10: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure23-3 for load conditions. TABLE 23-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. OC10 TccF OCx Output Fall Time — — — ns See Parameter DO32 OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31 Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70138G-page 190  2010 Microchip Technology Inc.

dsPIC30F3014/4013 FIGURE 23-11: OCx/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 23-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. OC15 TFD Fault Input to PWM I/O — — 50 ns Change OC20 TFLT Fault Input Pulse Width 50 — — ns Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc. DS70138G-page 191

dsPIC30F3014/4013 FIGURE 23-12: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING CHARACTERISTICS CSCK (SCKE = 0) CS11 CS10 CS21 CS20 CSCK (SCKE = 1) CS20 CS21 COFS CS55CS56 CS35 CS51 CS50 70 HIGH-Z MSb LSb HIGH-Z CSDO CS30 CS31 CSDI MSb IN LSb IN CS40 CS41 Note: Refer to Figure23-3 for load conditions. DS70138G-page 192  2010 Microchip Technology Inc.

dsPIC30F3014/4013 TABLE 23-28: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. CS10 TcSCKL CSCK Input Low Time TCY/2 + 20 — — ns (CSCK pin is an input) CSCK Output Low Time 30 — — ns (CSCK pin is an output)(3) CS11 TcSCKH CSCK Input High Time TCY/2 + 20 — — ns (CSCK pin is an input) CSCK Output High Time 30 — — ns (CSCK pin is an output)(3) CS20 TcSCKF CSCK Output Fall Time — 10 25 ns (CSCK pin is an output)(4) CS21 TcSCKR CSCK Output Rise Time — 10 25 ns (CSCK pin is an output)(4) CS30 TcSDOF CSDO Data Output Fall Time(4) — 10 25 ns CS31 TcSDOR CSDO Data Output Rise Time(4) — 10 25 ns CS35 TDV Clock Edge to CSDO Data Valid — — 10 ns CS36 TDIV Clock Edge to CSDO Tri-Stated 10 — 20 ns CS40 TCSDI Setup Time of CSDI Data Input 20 — — ns to CSCK Edge (CSCK pin is input or output) CS41 THCSDI Hold Time of CSDI Data Input to 20 — — ns CSCK Edge (CSCK pin is input or output) CS50 TcoFSF COFS Fall Time — 10 25 ns Note 1 (COFS pin is output) CS51 TcoFSR COFS Rise Time — 10 25 ns Note 1 (COFS pin is output) CS55 TscoFS Setup Time of COFS Data Input 20 — — ns to CSCK edge (COFS pin is input) CS56 THCOFS Hold Time of COFS Data Input to 20 — — ns CSCK Edge (COFS pin is input) CS57 TPCSCK CSCK Clock Period 100 — — ns Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all DCI pins.  2010 Microchip Technology Inc. DS70138G-page 193

dsPIC30F3014/4013 FIGURE 23-13: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 CS62 CS21 CS20 CS71 CS70 CS72 SYNC (COFS) CS76 CS75 CS80 LSb MSb LSb SDOx (CSDO) CS76 CS75 SDIx MSb In (CSDI) CS65 CS66 DS70138G-page 194  2010 Microchip Technology Inc.

dsPIC30F3014/4013 T ABLE 23-29: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1,2) Min Typ(3) Max Units Conditions No. CS60 TBCLKL BIT_CLK Low Time 36 40.7 45 ns CS61 TBCLKH BIT_CLK High Time 36 40.7 45 ns CS62 TBCLK BIT_CLK Period — 81.4 — ns Bit clock is input CS65 TSACL Input Setup Time to — — 10 ns Falling Edge of BIT_CLK CS66 THACL Input Hold Time from — — 10 ns Falling Edge of BIT_CLK CS70 TSYNCLO SYNC Data Output Low Time — 19.5 — s Note 1 CS71 TSYNCHI SYNC Data Output High Time — 1.3 — s Note 1 CS72 TSYNC SYNC Data Output Period — 20.8 — s Note 1 CS75 TRACL Rise Time, SYNC, SDATA_OUT — 10 25 ns CLOAD = 50 pF, VDD = 5V CS76 TFACL Fall Time, SYNC, SDATA_OUT — 10 25 ns CLOAD = 50 pF, VDD = 5V CS80 TOVDACL Output Valid Delay from Rising — — 15 ns Edge of BIT_CLK Note 1: These parameters are characterized but not tested in manufacturing. 2: These values assume BIT_CLK frequency is 12.288 MHz. 3: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 23-14: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP31 SP30 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure23-3 for load conditions.  2010 Microchip Technology Inc. DS70138G-page 195

dsPIC30F3014/4013 TABLE 23-30: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscL SCKX Output Low Time(3) TCY/2 — — ns SP11 TscH SCKX Output High Time(3) TCY/2 — — ns SP20 TscF SCKX Output Fall Time(4 — — — ns See parameter DO32 SP21 TscR SCKX Output Rise Time(4) — — — ns See parameter DO31 SP30 TdoF SDOX Data Output Fall Time(4) — — — ns See parameter DO32 SP31 TdoR SDOX Data Output Rise Time(4) — — — ns See parameter DO31 SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns TscL2doV SCKX Edge SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns TdiV2scL to SCKX Edge SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns TscL2diL to SCKX Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. FIGURE 23-15: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SCKX (CKP = 1) SP35 SP20 SP21 SDOX MSb Bit 14 - - - - - -1 LSb SP40 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure23-3 for load conditions. DS70138G-page 196  2010 Microchip Technology Inc.

dsPIC30F3014/4013 TABLE 23-31: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscL SCKX Output Low Time(3) TCY/2 — — ns SP11 TscH SCKX Output High Time(3) TCY/2 — — ns SP20 TscF SCKX Output Fall Time(4) — — — ns See parameter DO32 SP21 TscR SCKX Output Rise Time(4) — — — ns See parameter DO31 SP30 TdoF SDOX Data Output Fall — — — ns See parameter Time(4) DO32 SP31 TdoR SDOX Data Output Rise — — — ns See parameter Time(4) DO31 SP35 TscH2do, SDOX Data Output Valid after — — 30 ns TscL2doV SCKX Edge SP36 TdoV2sc, SDOX Data Output Setup to 30 — — ns TdoV2scL First SCKX Edge SP40 TdiV2scH, Setup Time of SDIX Data 20 — — ns TdiV2scL Input to SCKX Edge SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns TscL2diL to SCKX Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. FIGURE 23-16: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIX MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure23-3 for load conditions. SP40  2010 Microchip Technology Inc. DS70138G-page 197

dsPIC30F3014/4013 TABLE 23-32: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscL SCKX Input Low Time 30 — — ns SP71 TscH SCKX Input High Time 30 — — ns SP72 TscF SCKX Input Fall Time(3) — — 25 ns SP73 TscR SCKX Input Rise Time(3) — — 25 ns SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parameter DO32 SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parameter DO31 SP35 TscH2do, SDOX Data Output Valid after — — 30 ns TscL2doV SCKX Edge SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns TdiV2scL to SCKX Edge SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns TscL2diL to SCKX Edge SP50 TssL2scH, SSX to SCKX or SCKX Input 120 — — ns TssL2scL SP51 TssH2doZ SSX to SDOX Output 10 — 50 ns High-impedance(3) SP52 TscH2ssH SSX after SCKx Edge 1.5 TCY + 40 — — ns TscL2ssH Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. DS70138G-page 198  2010 Microchip Technology Inc.

dsPIC30F3014/4013 FIGURE 23-17: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SCKX (CKP = 1) SP35 SP72 SP73 SP52 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure23-3 for load conditions.  2010 Microchip Technology Inc. DS70138G-page 199

dsPIC30F3014/4013 TABLE 23-33: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscL SCKX Input Low Time 30 — — ns SP71 TscH SCKX Input High Time 30 — — ns SP72 TscF SCKX Input Fall Time(3) — — 25 ns SP73 TscR SCKX Input Rise Time(3) — — 25 ns SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parameter DO32 SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parameter DO31 SP35 TscH2do, SDOX Data Output Valid after — — 30 ns TscL2doV SCKX Edge SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns TdiV2scL to SCKX Edge SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns TscL2diL to SCKX Edge SP50 TssL2scH, SSX to SCKX or SCKX Input 120 — — ns TssL2scL SP51 TssH2doZ SSx to SDOX Output 10 — 50 ns High-Impedance(4) SP52 TscH2ssH SSX after SCKX Edge 1.5 TCY + 40 — — ns TscL2ssH SP60 TssL2doV SDOX Data Output Valid after — — 50 ns SCKX Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. DS70138G-page 200  2010 Microchip Technology Inc.

dsPIC30F3014/4013 FIGURE 23-18: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM34 IM30 IM33 SDA Start Stop Condition Condition Note: Refer to Figure23-3 for load conditions. FIGURE 23-19: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM21 IM10 SCL IM11 IM26 IM10 IM25 IM33 SDA In IM40 IM40 IM45 SDA Out Note: Refer to Figure23-3 for load conditions. TABLE 23-34: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min(1) Max Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM20 TF:SCL SDA and SCL 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 100 ns Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit™ (I2C)” in the “dsPIC30F Family Reference Manual” (DS70046). 2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).  2010 Microchip Technology Inc. DS70138G-page 201

dsPIC30F3014/4013 TABLE 23-34: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min(1) Max Units Conditions No. IM21 TR:SCL SDA and SCL 100 kHz mode — 1000 ns CB is specified to be Rise Time from 10 to 400 pF 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) — — ns IM26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(2) — — ns IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — s Only relevant for Setup Time 400 kHz mode TCY/2 (BRG + 1) — s Repeated Start condition 1 MHz mode(2) TCY/2 (BRG + 1) — s IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — s After this period, the Hold Time 400 kHz mode TCY/2 (BRG + 1) — s first clock pulse is generated 1 MHz mode(2) TCY/2 (BRG + 1) — s IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — s Setup Time 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns 1 MHz mode(2) TCY/2 (BRG + 1) — ns IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns From Clock 400 kHz mode — 1000 ns 1 MHz mode(2) — — ns IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be 400 kHz mode 1.3 — s free before a new transmission can start 1 MHz mode(2) — — s IM50 CB Bus Capacitive Loading — 400 pF Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit™ (I2C)” in the “dsPIC30F Family Reference Manual” (DS70046). 2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only). DS70138G-page 202  2010 Microchip Technology Inc.

dsPIC30F3014/4013 FIGURE 23-20: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS31 IS34 IS30 IS33 SDA Start Stop Condition Condition FIGURE 23-21: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS10 SCL IS30 IS26 IS31 IS25 IS33 SDA In IS40 IS40 IS45 SDA Out  2010 Microchip Technology Inc. DS70138G-page 203

dsPIC30F3014/4013 TABLE 23-35: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Max Units Conditions No. IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz. 1 MHz mode(1) 0.5 — s IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s IS20 TF:SCL SDA and SCL 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(1) 0 0.3 s IS30 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated Setup Time 400 kHz mode 0.6 — s Start condition 1 MHz mode(1) 0.25 — s IS31 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first Hold Time 400 kHz mode 0.6 — s clock pulse is generated 1 MHz mode(1) 0.25 — s IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — s Setup Time 400 kHz mode 0.6 — s 1 MHz mode(1) 0.6 — s IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — ns 1 MHz mode(1) 250 ns IS40 TAA:SCL Output Valid From 100 kHz mode 0 3500 ns Clock 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission 1 MHz mode(1) 0.5 — s can start IS50 CB Bus Capacitive — 400 pF Loading Note 1: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only). DS70138G-page 204  2010 Microchip Technology Inc.

dsPIC30F3014/4013 FIGURE 23-22: CAN MODULE I/O TIMING CHARACTERISTICS CXTX Pin Old Value New Value (output) CA10 CA11 CXRX Pin (input) CA20 TABLE 23-36: CAN MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. CA10 TioF Port Output Fall Time — 10 25 ns CA11 TioR Port Output Rise Time — 10 25 ns CA20 Tcwf Pulse Width to Trigger 500 — — ns CAN Wake-up Filter Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc. DS70138G-page 205

dsPIC30F3014/4013 TABLE 23-37: 12-BIT A/D MODULE SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of — Lesser of V VDD – 0.3 VDD + 0.3 or 2.7 or 5.5 AD02 AVSS Module VSS Supply VSS - 0.3 — VSS + 0.3 V Reference Inputs AD05 VREFH Reference Voltage High AVSS + 2.7 — AVDD V AD06 VREFL Reference Voltage Low AVSS — AVDD – 2.7 V AD07 VREF Absolute Reference AVSS – 0.3 — AVDD + 0.3 V Voltage AD08 IREF Current Drain — 200 300 A A/D operating .001 2 A A/D off Analog Input AD10 VINH-VINL Full-Scale Input Span VREFL — VREFH V Note 1 AD11 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V AD12 — Leakage Current — ±0.001 ±0.610 A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V Source Impedance = 2.5 k AD13 — Leakage Current — ±0.001 ±0.610 A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Source Impedance = 2.5 k AD15 RSS Switch Resistance — 3.2K —  AD16 CSAMPLE Sample Capacitor — 18 pF AD17 RIN Recommended Impedance — — 2.5K  of Analog Voltage Source DC Accuracy AD20 Nr Resolution 12 data bits bits AD21 INL Integral Nonlinearity — — <±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD21A INL Integral Nonlinearity — — <±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD22 DNL Differential Nonlinearity — — <±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD22A DNL Differential Nonlinearity — — <±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD23 GERR Gain Error +1.25 +1.5 +3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD23A GERR Gain Error +1.25 +1.5 +3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. DS70138G-page 206  2010 Microchip Technology Inc.

dsPIC30F3014/4013 TABLE 23-37: 12-BIT A/D MODULE SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. AD24 EOFF Offset Error -2 -1.5 -1.25 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD24A EOFF Offset Error -2 -1.5 -1.25 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD25 — Monotonicity(1) — — — — Guaranteed Dynamic Performance AD30 THD Total Harmonic Distortion — -71 — dB AD31 SINAD Signal to Noise and — 68 — dB Distortion AD32 SFDR Spurious Free Dynamic — 83 — dB Range AD33 FNYQ Input Signal Bandwidth — — 100 kHz AD34 ENOB Effective Number of Bits 10.95 11.1 — bits Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes.  2010 Microchip Technology Inc. DS70138G-page 207

dsPIC30F3014/4013 FIGURE 23-23: 12-BIT A/D CONVERSION TIMING CHARACTERISTICS (ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 TSAMP AD55 DONE ADIF ADRES(0) 1 2 3 4 5 6 7 8 9 1 - Software sets ADCON. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in Section 18. “12-bit A/D Converter” of the dsPIC30F Family Reference Manual (DS70046). 3 - Software clears ADCON. SAMP to start conversion. 4 - Sampling ends, conversion sequence starts. 5 - Convert bit 11. 6 - Convert bit 10. 7 - Convert bit 1. 8 - Convert bit 0. 9 - One TAD for end of conversion. DS70138G-page 208  2010 Microchip Technology Inc.

dsPIC30F3014/4013 TABLE 23-38: 12-BIT A/D CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Clock Parameters AD50 TAD A/D Clock Period 334 — — ns VDD = 3-5.5V (Note 1) AD51 tRC A/D Internal RC Oscillator Period 1.2 1.5 1.8 s Conversion Rate AD55 tCONV Conversion Time — 14 TAD ns AD56 FCNV Throughput Rate — 200 — ksps VDD = VREF = 5V AD57 TSAMP Sampling Time 1 TAD — — ns VDD = 3-5.5V source resistance RS = 0-2.5 k Timing Parameters AD60 tPCS Conversion Start from Sample — 1 TAD — ns Trigger AD61 tPSS Sample Start from Setting 0.5 TAD — 1.5 ns Sample (SAMP) Bit TAD AD62 tCSS Conversion Completion to — 0.5 TAD — ns Sample Start (ASAM = 1) AD63 tDPU(2) Time to Stabilize Analog Stage — — 20 s from A/D Off to A/D On Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 2: tDPU is the time required for the ADC module to stabilize when it is turned on (ADCON1<ADON> = 1). During this time the ADC result is indeterminate.  2010 Microchip Technology Inc. DS70138G-page 209

dsPIC30F3014/4013 NOTES: DS70138G-page 210  2010 Microchip Technology Inc.

dsPIC30F3014/4013 24.0 PACKAGING INFORMATION 24.1 Package Marking Information 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX dsPIC30F4013 XXXXXXXXXXXXXXXXXX -30I/Pe3 XXXXXXXXXXXXXXXXXX YYWWNNN 0810017 Example 44-Lead TQFP XXXXXXXXXX dsPIC XXXXXXXXXX 30F4013 XXXXXXXXXX -301/PT e3 YYWWNNN 0810017 44-Lead QFN Example XXXXXXXXXX dsPIC XXXXXXXXXX 30F4013 XXXXXXXXXX -30I/ML e3 YYWWNNN 0810017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010 Microchip Technology Inc. DS70138G-page 211

dsPIC30F3014/4013 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:11)(cid:9)(cid:18)(cid:19)(cid:4)(cid:5)(cid:14)(cid:19)(cid:6)(cid:9)(cid:20)(cid:10)(cid:21)(cid:9)(cid:22)(cid:9)(cid:23)(cid:3)(cid:3)(cid:9)(cid:24)(cid:14)(cid:11)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)(cid:9)(cid:28)(cid:10)(cid:16)(cid:18)(cid:10)(cid:29) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 4(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)366***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’6(cid:12)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c b1 A1 b e eB 7(cid:15)(cid:7)&! (cid:19)8,9.(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2):(cid:7)’(cid:7)&! (cid:6)(cid:19)8 8;(cid:6) (cid:6)(cid:25)< 8"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 8 (cid:23)(cid:4) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2)2(cid:22), (cid:13)(cid:10)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) = = (cid:20)(cid:3)1(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)5(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:20)(cid:30)(cid:3)1 = (cid:20)(cid:30)(cid:24)1 2(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)1 = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)1(cid:24)(cid:4) = (cid:20)(cid:29)(cid:3)1 (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:23)?1 = (cid:20)1?(cid:4) ; (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:20)(cid:24)?(cid:4) = (cid:3)(cid:20)(cid:4)(cid:24)1 (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) : (cid:20)(cid:30)(cid:30)1 = (cid:20)(cid:3)(cid:4)(cid:4) :(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)5(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)? = (cid:20)(cid:4)(cid:30)1 7(cid:12)(cid:12)(cid:14)(cid:9)(cid:2):(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)-(cid:4) = (cid:20)(cid:4)(cid:5)(cid:4) :(cid:10)*(cid:14)(cid:9)(cid:2):(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) = (cid:20)(cid:4)(cid:3)- ; (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)2 = = (cid:20)(cid:5)(cid:4)(cid:4) (cid:30)(cid:26)(cid:13)(cid:6)(cid:12)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)1(cid:6)(cid:20) 2(cid:22),3 2(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)(cid:29)2 DS70138G-page 212  2010 Microchip Technology Inc.

dsPIC30F3014/4013 (cid:2)(cid:2)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9) !(cid:14)(cid:19)(cid:9)"(cid:17)(cid:7)(cid:8)(cid:9)#(cid:11)(cid:7)(cid:13)$(cid:7)(cid:15)%(cid:9)(cid:20)(cid:10) (cid:21)(cid:9)(cid:22)(cid:9)&(cid:3)’&(cid:3)’&(cid:9)(cid:24)(cid:24)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)((cid:9))*(cid:3)(cid:3)(cid:9)(cid:24)(cid:24)(cid:9)(cid:28) "#(cid:10)(cid:29) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 4(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)366***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’6(cid:12)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D1 E e E1 N b NOTE1 1 2 3 NOTE2 α A c φ β A1 A2 L L1 7(cid:15)(cid:7)&! (cid:6)(cid:19)::(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2):(cid:7)’(cid:7)&! (cid:6)(cid:19)8 8;(cid:6) (cid:6)(cid:25)< 8"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2):(cid:14)(cid:28)#! 8 (cid:23)(cid:23) :(cid:14)(cid:28)#(cid:2)(cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)?(cid:4)(cid:2)2(cid:22), ; (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)5(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:4)(cid:20)(cid:24)1 (cid:30)(cid:20)(cid:4)(cid:4) (cid:30)(cid:20)(cid:4)1 (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)1 = (cid:4)(cid:20)(cid:30)1 4(cid:10)(cid:10)&(cid:2):(cid:14)(cid:15)(cid:17)&(cid:11) : (cid:4)(cid:20)(cid:23)1 (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)(cid:5)1 4(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& :(cid:30) (cid:30)(cid:20)(cid:4)(cid:4)(cid:2)(cid:26).4 4(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B -(cid:20)1B (cid:5)B ; (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)2(cid:22), ; (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:30)(cid:3)(cid:20)(cid:4)(cid:4)(cid:2)2(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)2(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:14)(cid:2):(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:30) (cid:30)(cid:4)(cid:20)(cid:4)(cid:4)(cid:2)2(cid:22), :(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)5(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) = (cid:4)(cid:20)(cid:3)(cid:4) :(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-(cid:5) (cid:4)(cid:20)(cid:23)1 (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:30)(cid:30)B (cid:30)(cid:3)B (cid:30)-B (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)2(cid:10)&&(cid:10)’ (cid:5) (cid:30)(cid:30)B (cid:30)(cid:3)B (cid:30)-B (cid:30)(cid:26)(cid:13)(cid:6)(cid:12)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) ,(cid:11)(cid:28)’%(cid:14)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:8)(cid:10)(cid:9)(cid:15)(cid:14)(cid:9)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:2)(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)@(cid:2)!(cid:7)A(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:30)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:3)1(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)1(cid:6)(cid:20) 2(cid:22),3 2(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).43 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:29)2  2010 Microchip Technology Inc. DS70138G-page 213

dsPIC30F3014/4013 (cid:2)(cid:2)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9) !(cid:14)(cid:19)(cid:9)"(cid:17)(cid:7)(cid:8)(cid:9)#(cid:11)(cid:7)(cid:13)$(cid:7)(cid:15)%(cid:9)(cid:20)(cid:10) (cid:21)(cid:9)(cid:22)(cid:9)&(cid:3)’&(cid:3)’&(cid:9)(cid:24)(cid:24)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)((cid:9))*(cid:3)(cid:3)(cid:9)(cid:24)(cid:24)(cid:9)(cid:28) "#(cid:10)(cid:29) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 4(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)366***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’6(cid:12)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS70138G-page 214  2010 Microchip Technology Inc.

dsPIC30F3014/4013 (cid:2)(cid:2)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)"(cid:17)(cid:7)(cid:8)(cid:9)#(cid:11)(cid:7)(cid:13)((cid:9)(cid:30)(cid:26)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)%(cid:7)+(cid:6)(cid:9)(cid:20),(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)-’-(cid:9)(cid:24)(cid:24)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)(cid:9)(cid:28)"#(cid:30)(cid:29) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 4(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)366***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’6(cid:12)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D D2 EXPOSED PAD e E E2 b 2 2 1 1 N NOTE1 N L K TOPVIEW BOTTOMVIEW A A3 A1 7(cid:15)(cid:7)&! (cid:6)(cid:19)::(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2):(cid:7)’(cid:7)&! (cid:6)(cid:19)8 8;(cid:6) (cid:6)(cid:25)< 8"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 8 (cid:23)(cid:23) (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)(cid:29)1(cid:2)2(cid:22), ; (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)1 ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)5(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).4 ; (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)2(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)(cid:23)1 (cid:29)(cid:20)?(cid:4) ; (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) ?(cid:20)(cid:4)(cid:4)(cid:2)2(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2):(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) (cid:29)(cid:20)-(cid:4) (cid:29)(cid:20)(cid:23)1 (cid:29)(cid:20)?(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)(cid:3)1 (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)-? ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2):(cid:14)(cid:15)(cid:17)&(cid:11) : (cid:4)(cid:20)-(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)1(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# C (cid:4)(cid:20)(cid:3)(cid:4) = = (cid:30)(cid:26)(cid:13)(cid:6)(cid:12)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)1(cid:6)(cid:20) 2(cid:22),3 2(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).43 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:4)-2  2010 Microchip Technology Inc. DS70138G-page 215

dsPIC30F3014/4013 (cid:2)(cid:2)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)"(cid:17)(cid:7)(cid:8)(cid:9)#(cid:11)(cid:7)(cid:13)((cid:9)(cid:30)(cid:26)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)%(cid:7)+(cid:6)(cid:9)(cid:20),(cid:5)(cid:21)(cid:9)(cid:22)(cid:9)-’-(cid:9)(cid:24)(cid:24)(cid:9)(cid:25)(cid:26)(cid:8)(cid:27)(cid:9)(cid:28)"#(cid:30)(cid:29) (cid:30)(cid:26)(cid:13)(cid:6)(cid:31) 4(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)366***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’6(cid:12)(cid:28)(cid:8)5(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS70138G-page 216  2010 Microchip Technology Inc.

dsPIC30F3014/4013 APPENDIX A: REVISION HISTORY • Electrical Specifications: - Resolved TBD values for parameters DO10, Revision D (June 2006) DO16, DO20, and DO26 (see Table23-9) - 10-bit High-Speed ADC tPDU timing parame- Previous versions of this data sheet contained ter (time to stabilize) has been updated from Advance or Preliminary Information. They were 20 µs typical to 20 µs maximum (see distributed with incomplete characterization data. Table23-38) This revision reflects these changes: - Parameter OS65 (Internal RC Accuracy) has • Revised I2C Slave Addresses been expanded to reflect multiple Min and (see Table14-1) Max values for different temperatures (see Table23-18) • Updated example for ADC Conversion Clock selection (see Section19.0 “12-bit Analog-to- - Parameter DC12 (RAM Data Retention Volt- Digital Converter (ADC) Module”) age) has been updated to include a Min value (see Table23-4) • Base instruction CP1 eliminated from instruction set (seeTable21-2) - Parameter D134 (Erase/Write Cycle Time) has been updated to include Min and Max • Revised electrical characteristics: values and the Typ value has been removed - Operating Current (IDD) Specifications (see Table23-12) (see Table23-5) - Removed parameters OS62 (Internal FRC - Idle Current (IIDLE) Specifications Jitter) and OS64 (Internal FRC Drift) and (see Table23-6) Note 2 from AC Characteristics (see - Power-down Current (IPD) Specifications Table23-17) (see Table23-7) - Parameter OS63 (Internal FRC Accuracy) - I/O pin Input Specifications has been expanded to reflect multiple Min (see Table23-8) and Max values for different temperatures - Brown Out Reset (BOR) Specifications (see Table23-17) (see Table23-11) - Removed parameters DC27a, DC27b, - Watchdog Timer time-out limits DC47a, and DC47b (references to IDD, (see Table23-20) 20 MIPs @ 3.3V) in Table23-5 and Table23-6 Revision E (January 2007) - Removed parameters CS77 and CS78 (references to TRACL and TFACL @ 3.3V) in This revision includes updates to the packaging Table23-29 diagrams. - Updated Min and Max values and Conditions for parameter SY11 and updated Min, Typ, Revision F (April 2008) and Max values and Conditions for This revision reflects these updates: parameter SY20 (see Table23-20) • Additional minor corrections throughout the • Added FUSE Configuration Register (FICD) document details (see Section20.8 “Device Configuration Registers” and Table20-8) • Added Note 2 in Device Configuration Registers table (Table20-8) • Removed erroneous statement regarding genera- tion of CAN receive errors (see Section17.4.5 “Receive Errors”) • Updated ADC Conversion Clock and Sampling Rate Calculation (see Example19-1). Minimum TAD is 334 nsec. • Updated details related to the Input Change Notification module: - Updated last sentence in the first paragraph of Section7.3 “Input Change Notification Module” - Updated Table7-2 - Removed Table 7-3, Table 7-4, and Table 7-5  2010 Microchip Technology Inc. DS70138G-page 217

dsPIC30F3014/4013 Revision G (November 2010) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in TableA-1. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-Bit Digital Added Note 1 to all QFN pin diagrams (see “Pin Diagrams”). Signal Controllers” Section1.0 “Device Overview” Removed the “DCI” peripheral block from the dsPIC30F3014 Block Diagram (see Figure1-1). Updated the Pinout I/O Descriptions for AVDD and AVSS (see Table1-1). Section20.0 “System Integration” Added a note on OSCTUN functionality in Section20.2.5 “Fast RC Oscillator (FRC)”. Updated the operating frequencies for the following Oscillator Operating Modes (see Table20-1): • XTL • XT w/PLL 16x • HS/2 w/PLL 4x, 8x, and 16x • HS/3 w/PLL 4x, 8x, and 16x • EC w/PLL 4x, 8x, and 16x Section23.0 “Electrical Updated the maximum value for parameter DI19 and the minimum value for Characteristics” parameter DI29 in the I/O Pin Input Specifications (see Table23-8). Removed parameter D136 and updated the minimum, typical, maximum, and conditions for parameters D122 and D134 in the Program and EEPROM specifications (see Table23-12). DS70138G-page 218  2010 Microchip Technology Inc.

dsPIC30F3014/4013 INDEX Numerics CAN Buffers and Protocol Engine............................112 DCI Module...............................................................122 12-Bit Analog-to-Digital Converter (A/D) Module..............131 Dedicated Port Structure............................................53 A DSP Engine................................................................20 A/D....................................................................................131 dsPIC30F3014............................................................11 Aborting a Conversion..............................................133 dsPIC30F4013............................................................12 ADCHS Register.......................................................131 External Power-on Reset Circuit..............................153 ADCON1 Register.....................................................131 I2C..............................................................................92 ADCON2 Register.....................................................131 Input Capture Mode....................................................81 ADCON3 Register.....................................................131 Oscillator System......................................................143 ADCSSL Register.....................................................131 Output Compare Mode...............................................85 ADPCFG Register.....................................................131 Reset System...........................................................151 Configuring Analog Port Pins..............................54, 138 Shared Port Structure.................................................54 Connection Considerations.......................................138 SPI............................................................................100 Conversion Operation...............................................132 SPI Master/Slave Connection...................................100 Effects of a Reset......................................................137 UART Receiver.........................................................104 Operation During CPU Idle Mode.............................137 UART Transmitter.....................................................103 Operation During CPU Sleep Mode..........................137 BOR Characteristics.........................................................180 Output Formats.........................................................137 BOR. See Brown-out Reset. Brown-out Reset Power-Down Modes..................................................137 Programming the Sample Trigger.............................133 Timing Requirements...............................................187 Register Map.............................................................139 C Result Buffer.............................................................132 C Compilers Sampling Requirements............................................136 MPLAB C18..............................................................168 Selecting the Conversion Sequence.........................132 CAN Module.....................................................................111 AC Characteristics............................................................180 Baud Rate Setting....................................................116 Load Conditions........................................................181 CAN1 Register Map..................................................118 AC Temperature and Voltage Specifications....................181 Frame Types............................................................111 AC-Link Mode Operation..................................................128 I/O Timing Requirements..........................................205 16-Bit Mode...............................................................128 Message Reception..................................................114 20-Bit Mode...............................................................129 Message Transmission.............................................115 ADC Modes of Operation..................................................113 Selecting the Conversion Clock................................133 Overview...................................................................111 ADC Conversion Speeds..................................................134 CLKOUT and I/O Timing Address Generator Units....................................................37 Requirements...........................................................185 Alternate Vector Table........................................................64 Code Examples Analog-to-Digital Converter. See A/D. Data EEPROM Block Erase.......................................50 Assembler Data EEPROM Block Write........................................52 MPASM Assembler...................................................168 Data EEPROM Read..................................................49 Automatic Clock Stretch......................................................94 Data EEPROM Word Erase.......................................50 During 10-Bit Addressing (STREN = 1)......................94 Data EEPROM Word Write........................................51 During 7-Bit Addressing (STREN = 1)........................94 Erasing a Row of Program Memory...........................45 Receive Mode.............................................................94 Initiating a Programming Sequence...........................46 Transmit Mode............................................................94 Loading Write Latches................................................46 B Port Write/Read..........................................................54 Band Gap Start-up Time Code Protection................................................................141 Requirements............................................................187 Control Registers................................................................44 Barrel Shifter.......................................................................23 NVMADR....................................................................44 Bit-Reversed Addressing....................................................40 NVMADRU.................................................................44 Example......................................................................40 NVMCON....................................................................44 Implementation...........................................................40 NVMKEY....................................................................44 Modifier Values Table.................................................41 Core Architecture Sequence Table (16-Entry).........................................41 Overview.....................................................................15 Block Diagrams CPU Architecture Overview................................................15 12-Bit A/D Functional................................................131 Customer Change Notification Service.............................225 16-Bit Timer1 Module..................................................67 Customer Notification Service..........................................225 16-Bit Timer2..............................................................73 Customer Support.............................................................225 16-Bit Timer3..............................................................73 D 16-Bit Timer4..............................................................78 Data Accumulators and Adder/Subtracter..........................21 16-Bit Timer5..............................................................78 Data Accumulators and Adder/Subtractor 32-Bit Timer2/3...........................................................72 Data Space Write Saturation......................................23 32-Bit Timer4/5...........................................................77 Overflow and Saturation.............................................21  2010 Microchip Technology Inc. DS70138G-page 219

dsPIC30F3014/4013 Round Logic................................................................22 Synchronous Data Transfers....................................126 Write-Back..................................................................22 Timing Requirements Data Address Space...........................................................30 AC-Link Mode...................................................195 Alignment....................................................................32 Multichannel, I2S Modes...................................193 Alignment (Figure)......................................................32 Transmit Slot Enable Bits.........................................126 Effect of Invalid Memory Accesses (Table).................32 Transmit Status Bits..................................................127 MCU and DSP (MAC Class) Instructions Example.....31 Transmit/Receive Shift Register...............................121 Memory Map...............................................................30 Underflow Mode Control Bit......................................128 Near Data Space........................................................33 Word-Size Selection Bits..........................................123 Software Stack............................................................33 Development Support.......................................................167 Spaces........................................................................32 Device Configuration Width...........................................................................32 Register Map............................................................158 Data Converter Interface (DCI) Module............................121 Device Configuration Registers Data EEPROM Memory......................................................49 FBORPOR................................................................156 Erasing........................................................................50 FGS..........................................................................156 Erasing, Block.............................................................50 FOSC........................................................................156 Erasing, Word.............................................................50 FWDT.......................................................................156 Protection Against Spurious Write..............................52 Device Overview.................................................................11 Reading.......................................................................49 Disabling the UART..........................................................105 Write Verify.................................................................52 Divide Support....................................................................18 Writing.........................................................................51 Instructions (Table).....................................................18 Writing, Block..............................................................51 DSP Engine........................................................................19 Writing, Word..............................................................51 Multiplier.....................................................................21 DC Characteristics............................................................172 Dual Output Compare Match Mode....................................86 BOR..........................................................................180 Continuous Pulse Mode..............................................86 I/O Pin Input Specifications.......................................178 Single Pulse Mode......................................................86 I/O Pin Output Specifications....................................178 E Idle Current (IIDLE)....................................................175 LVDL.........................................................................179 Electrical Characteristics..................................................171 Operating Current (IDD).............................................174 AC.............................................................................180 Power-Down Current (IPD)........................................176 DC............................................................................172 Program and EEPROM.............................................180 Enabling and Setting Up UART Temperature and Voltage Specifications..................172 Alternate I/O.............................................................105 DCI Module Enabling and Setting up UART Bit Clock Generator...................................................125 Setting up Data, Parity and Stop Bit Selections........105 Buffer Alignment with Data Frames..........................127 Enabling the UART...........................................................105 Buffer Control............................................................121 Equations Buffer Data Alignment...............................................121 ADC Conversion Clock.............................................133 Buffer Length Control................................................127 Baud Rate.................................................................107 COFS Pin..................................................................121 Bit Clock Frequency..................................................125 CSCK Pin..................................................................121 COFSG Period..........................................................123 CSDI Pin...................................................................121 Serial Clock Rate........................................................96 CSDO Mode Bit........................................................128 Time Quantum for Clock Generation........................117 CSDO Pin.................................................................121 Errata....................................................................................9 Data Justification Control Bit.....................................126 Exception Sequence Device Frequencies for Common Codec CSCK Frequen- Trap Sources..............................................................62 cies (Table).......................................................125 External Clock Timing Requirements...............................182 Digital Loopback Mode.............................................128 Type A Timer............................................................188 Enable.......................................................................123 Type B Timer............................................................189 Frame Sync Generator.............................................123 Type C Timer............................................................189 Frame Sync Mode Control Bits.................................123 External Interrupt Requests................................................64 I/O Pins.....................................................................121 F Interrupts...................................................................128 Introduction...............................................................121 Fast Context Saving...........................................................64 Master Frame Sync Operation..................................123 Flash Program Memory......................................................43 Operation..................................................................123 I Operation During CPU Idle Mode.............................128 I/0 Ports Operation During CPU Sleep Mode..........................128 Register Map..............................................................55 Receive Slot Enable Bits...........................................126 I/O Pin Specifications Receive Status Bits...................................................127 Input..........................................................................178 Register Map.............................................................130 Output.......................................................................178 Sample Clock Edge Control Bit.................................126 I/O Ports..............................................................................53 Slave Frame Sync Operation....................................124 Parallel (PIO)..............................................................53 Slot Enable Bits Operation with Frame Sync............126 I2C 10-Bit Slave Mode Operation.......................................93 Slot Status Bits..........................................................128 Reception...................................................................94 DS70138G-page 220  2010 Microchip Technology Inc.

dsPIC30F3014/4013 Transmission...............................................................93 LVDL Characteristics........................................................179 I2C 7-Bit Slave Mode Operation..........................................93 M Reception....................................................................93 Transmission...............................................................93 Memory Organization.........................................................25 I2C Master Mode Operation................................................95 Core Register Map.....................................................33 Baud Rate Generator..................................................96 Microchip Internet Web Site..............................................225 Clock Arbitration..........................................................96 Modes of Operation Multi-Master Communication, Disable......................................................................113 Bus Collision and Bus Arbitration.......................96 Initialization...............................................................113 Reception....................................................................96 Listen All Messages..................................................113 Transmission...............................................................95 Listen Only................................................................113 I2C Master Mode Support...................................................95 Loopback..................................................................113 I2C Module..........................................................................91 Normal Operation.....................................................113 Addresses...................................................................93 Modulo Addressing.............................................................38 Bus Data Timing Requirements Applicability.................................................................40 Master Mode.....................................................201 Incrementing Buffer Operation Example....................39 Slave Mode.......................................................204 Start and End Address...............................................39 General Call Address Support....................................95 W Address Register Selection....................................39 Interrupts.....................................................................95 MPLAB ASM30 Assembler, Linker, Librarian...................168 IPMI Support...............................................................95 MPLAB Integrated Development Environment Software..167 Operating Function Description..................................91 MPLAB PM3 Device Programmer....................................170 Operation During CPU Sleep and Idle Modes............96 MPLAB REAL ICE In-Circuit Emulator System................169 Pin Configuration........................................................91 MPLINK Object Linker/MPLIB Object Librarian................168 Programmer’s Model...................................................91 N Register Map...............................................................97 Registers.....................................................................91 NVM Slope Control..............................................................95 Register Map..............................................................47 Software Controlled Clock Stretching (STREN = 1)....94 O Various Modes............................................................91 I2S Mode Operation..........................................................129 Operating Current (IDD)....................................................174 Data Justification.......................................................129 Operating Frequency vs Voltage Frame and Data Word Length Selection...................129 dsPIC30FXXXX-20 (Extended)................................172 Idle Current (IIDLE)............................................................175 Oscillator In-Circuit Serial Programming (ICSP).........................43, 141 Configurations..........................................................144 Input Capture Module.........................................................81 Fail-Safe Clock Monitor....................................146 Interrupts.....................................................................82 Fast RC (FRC)..................................................145 Register Map...............................................................83 Initial Clock Source Selection...........................144 Input Capture Operation During Sleep and Idle Modes......82 Low-Power RC (LPRC)....................................145 CPU Idle Mode............................................................82 LP Oscillator Control.........................................145 CPU Sleep Mode........................................................82 Phase Locked Loop (PLL)................................145 Input Capture Timing Requirements.................................190 Start-up Timer (OST)........................................144 Input Change Notification Module.......................................56 Control Registers......................................................147 Register Map...............................................................57 Operating Modes (Table)..........................................142 Instruction Addressing Modes.............................................37 System Overview......................................................141 File Register Instructions............................................37 Oscillator Selection...........................................................141 Fundamental Modes Supported..................................37 Oscillator Start-up Timer MAC Instructions.........................................................38 Timing Requirements...............................................187 MCU Instructions........................................................37 Output Compare Interrupts.................................................88 Move and Accumulator Instructions............................38 Output Compare Module....................................................85 Other Instructions........................................................38 Register Map dsPIC30F3014.....................................89 Instruction Set Register Map dsPIC30F4013.....................................89 Overview...................................................................162 Timing Requirements...............................................190 Summary...................................................................159 Output Compare Operation During CPU Idle Mode...........88 Internal Clock Timing Examples.......................................183 Output Compare Sleep Mode Operation............................88 Internet Address................................................................225 P Interrupt Controller Packaging Information......................................................211 Register Map...............................................................66 Marking.....................................................................211 Interrupt Priority..................................................................60 Peripheral Module Disable (PMD) Registers....................157 Traps...........................................................................62 Pinout Descriptions.............................................................13 Interrupt Sequence.............................................................63 POR. See Power-on Reset. Interrupt Stack Frame.................................................63 Power Saving Modes Interrupts.............................................................................59 Sleep and Idle...........................................................141 L Power-Down Current (IPD)................................................176 Load Conditions................................................................181 Power-Saving Modes........................................................155 Low-Voltage Detect (LVD)................................................155 Idle............................................................................156  2010 Microchip Technology Inc. DS70138G-page 221

dsPIC30F3014/4013 Sleep.........................................................................155 Simple Output Compare Match Mode................................86 Power-up Timer Simple PWM Mode.............................................................86 Timing Requirements................................................187 Input Pin Fault Protection...........................................86 Program Address Space.....................................................25 Period.........................................................................87 Construction................................................................26 Software Simulator (MPLAB SIM)....................................169 Data Access from Program Memory Software Stack Pointer, Frame Pointer..............................16 Using Program Space Visibility...........................28 CALL Stack Frame.....................................................33 Data Access From Program Memory SPI Module.........................................................................99 Using Table Instructions.....................................27 Framed SPI Support.................................................100 Data Access from, Address Generation......................26 Operating Function Description..................................99 Data Space Window into Operation............................29 Operation During CPU Idle Mode.............................101 Data Table Access (lsw).............................................27 Operation During CPU Sleep Mode..........................101 Data Table Access (MSB)...........................................28 SDOx Disable.............................................................99 dsPIC30F3014 Memory Map......................................25 Slave Select Synchronization...................................101 dsPIC30F4013 Memory Map......................................25 SPI1 Register Map....................................................102 Table Instructions Timing Requirements TBLRDH..............................................................27 Master Mode (CKE = 0)....................................196 TBLRDL..............................................................27 Master Mode (CKE = 1)....................................197 TBLWTH.............................................................27 Slave Mode (CKE = 0)......................................198 TBLWTL..............................................................27 Slave Mode (CKE = 1)......................................200 Program and EEPROM Characteristics............................180 Word and Byte Communication..................................99 Program Counter.................................................................16 Status Bits, Their Significance and the Initialization Condition Programmable...................................................................141 for RCON Register, Case 1......................................154 Programmer’s Model...........................................................16 Status Bits, Their Significance and the Initialization Condition Diagram......................................................................17 for RCON Register, Case 2......................................154 Programming Operations....................................................45 STATUS Register...............................................................16 Algorithm for Program Flash.......................................45 Symbols Used in Opcode Descriptions............................160 Erasing a Row of Program Memory............................45 System Integration............................................................141 Initiating the Programming Sequence.........................46 Register Map............................................................158 Loading Write Latches................................................46 T Protection Against Accidental Writes to OSCCON...........146 Table Instruction Operation Summary................................43 R Temperature and Voltage Specifications Reader Response.............................................................226 AC.............................................................................181 Registers DC............................................................................172 OSCCON (Oscillator Control)...................................147 Timer1 Module....................................................................67 OSCTUN (Oscillator Tuning)....................................149 16-Bit Asynchronous Counter Mode...........................67 Reset.........................................................................141, 151 16-Bit Synchronous Counter Mode.............................67 BOR, Programmable.................................................153 16-Bit Timer Mode......................................................67 Brown-out Reset (BOR)............................................141 Gate Operation...........................................................68 Oscillator Start-up Timer (OST)................................141 Interrupt......................................................................68 POR Operation During Sleep Mode....................................68 Operating without FSCM and PWRT................153 Prescaler....................................................................68 With Long Crystal Start-up Time.......................153 Real-Time Clock.........................................................68 POR (Power-on Reset).............................................151 Interrupts............................................................68 Power-on Reset (POR).............................................141 Oscillator Operation............................................68 Power-up Timer (PWRT)..........................................141 Register Map..............................................................69 Reset Sequence..................................................................61 Timer2 and Timer3 Selection Mode....................................85 Reset Sources............................................................61 Timer2/3 Module.................................................................71 Reset Sources 16-Bit Timer Mode......................................................71 Brown-out Reset (BOR)..............................................61 32-Bit Synchronous Counter Mode.............................71 Illegal Instruction Trap.................................................61 32-Bit Timer Mode......................................................71 Trap Lockout...............................................................61 ADC Event Trigger......................................................74 Uninitialized W Register Trap.....................................61 Gate Operation...........................................................74 Watchdog Time-out.....................................................61 Interrupt......................................................................74 Reset Timing Requirements..............................................187 Operation During Sleep Mode....................................74 Revision History................................................................217 Register Map..............................................................75 Run-Time Self-Programming (RTSP).................................43 Timer Prescaler..........................................................74 Timer4/5 Module.................................................................77 S Register Map..............................................................79 Simple Capture Event Mode...............................................81 Timing Diagrams Buffer Operation..........................................................82 A/D Conversion Hall Sensor Mode.......................................................82 Low-Speed (ASAM = 0, SSRC = 000)..............208 Prescaler.....................................................................81 Band Gap Start-up Time...........................................187 Timer2 and Timer3 Selection Mode............................82 Brown-out Reset Characteristics..............................179 Simple OCx/PWM Mode Timing Requirements................191 CAN Bit.....................................................................116 DS70138G-page 222  2010 Microchip Technology Inc.

dsPIC30F3014/4013 CAN Module I/O........................................................205 Type C Timer External Clock....................................189 CLKOUT and I/O.......................................................185 Watchdog Timer.......................................................187 DCI Module Trap Vectors.......................................................................63 AC-Link Mode...................................................194 U Multichannel, I2S Modes...................................192 External Clock...........................................................181 UART Module Frame Sync, AC-Link Start-Of-Frame.......................124 Address Detect Mode...............................................107 Frame Sync, Multichannel Mode..............................124 Auto-Baud Support...................................................108 I2C Bus Data Baud Rate Generator...............................................107 Master Mode.....................................................201 Enabling and Setting Up...........................................105 Slave Mode.......................................................203 Framing Error (FERR)..............................................107 I2C Bus Start/Stop Bits Idle Status.................................................................107 Master Mode.....................................................201 Loopback Mode........................................................107 Slave Mode.......................................................203 Operation During CPU Sleep and Idle Modes..........108 I2S Interface Frame Sync..........................................124 Overview...................................................................103 Input Capture (CAPx)................................................190 Parity Error (PERR)..................................................107 Low-Voltage Detect...................................................178 Receive Break..........................................................107 OCx/PWM Module....................................................191 Receive Buffer (UxRXB)...........................................106 Oscillator Start-up Timer...........................................186 Receive Buffer Overrun Error (OERR Bit)................106 Output Compare Module...........................................190 Receive Interrupt......................................................106 Power-up Timer........................................................186 Receiving Data.........................................................106 PWM Output...............................................................87 Receiving in 8-Bit or 9-Bit Data Mode......................106 Reset.........................................................................186 Reception Error Handling.........................................106 SPI Module Transmit Break.........................................................106 Master Mode (CKE = 0)....................................195 Transmit Buffer (UxTXB)..........................................105 Master Mode (CKE = 1)....................................196 Transmit Interrupt.....................................................106 Slave Mode (CKE = 0)......................................197 Transmitting Data.....................................................105 Slave Mode (CKE = 1)......................................199 Transmitting in 8-Bit Data Mode...............................105 Time-out Sequence on Power-up Transmitting in 9-Bit Data Mode...............................105 (MCLR Not Tied to VDD), Case 1......................152 UART1 Register Map...............................................109 Time-out Sequence on Power-up UART2 Register Map...............................................109 (MCLR Not Tied to VDD), Case 2......................152 UART Operation Time-out Sequence on Power-up Idle Mode..................................................................108 (MCLR Tied to VDD)..........................................152 Sleep Mode..............................................................108 Type A, B and C Timer External Clock.....................188 Unit ID Locations..............................................................141 Watchdog Timer........................................................186 Universal Asynchronous Receiver Transmitter Timing Diagrams and Specifications (UART) Module.........................................................103 DC Characteristics - Internal RC Accuracy...............183 W Timing Diagrams.See Timing Characteristics Timing Requirements Wake-up from Sleep.........................................................141 A/D Conversion Wake-up from Sleep and Idle.............................................64 Low-Speed........................................................209 Watchdog Timer Band Gap Start-up Time...........................................187 Timing Requirements...............................................187 Brown-out Reset.......................................................187 Watchdog Timer (WDT)............................................141, 155 CAN Module I/O........................................................205 Enabling and Disabling.............................................155 CLKOUT and I/O.......................................................185 Operation..................................................................155 DCI Module WWW Address.................................................................225 AC-Link Mode...................................................195 WWW, On-Line Support.......................................................9 Multichannel, I2S Modes...................................193 External Clock...........................................................182 I2C Bus Data (Master Mode).....................................201 I2C Bus Data (Slave Mode).......................................204 Input Capture............................................................190 Oscillator Start-up Timer...........................................187 Output Compare Module...........................................190 Power-up Timer........................................................187 Reset.........................................................................187 Simple OCx/PWM Mode...........................................191 SPI Module Master Mode (CKE = 0)....................................196 Master Mode (CKE = 1)....................................197 Slave Mode (CKE = 0)......................................198 Slave Mode (CKE = 1)......................................200 Type A Timer External Clock....................................188 Type B Timer External Clock....................................189  2010 Microchip Technology Inc. DS70138G-page 223

dsPIC30F3014/4013 NOTES: DS70138G-page 224  2010 Microchip Technology Inc.

dsPIC30F3014/4013 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2010 Microchip Technology Inc. DS70138G-page 225

dsPIC30F3014/4013 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: dsPIC30F3014/4013 Literature Number: DS70138G Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70138G-page 226  2010 Microchip Technology Inc.

dsPIC30F3014/4013 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC30F4013AT-30I/PT-ES Custom ID (3 digits) or Trademark Engineering Sample (ES) Architecture Package P = 40-pin PDIP Flash PT = 44-pin TQFP (10x10) ML = 44-pin QFN (8x8) Memory Size in Bytes S = Die (Waffle Pack) W = Die (Wafers) 0 = ROMless 1 = 1K to 6K 2 = 7K to 12K 3 = 13K to 24K 4 = 25K to 48K Temperature 5 = 49K to 96K I = Industrial -40°C to +85°C 6 = 97K to 192K E = Extended High Temp -40°C to +125°C 7 = 193K to 384K 8 = 385K to 768K Speed 9 = 769K and Up 20 = 20 MIPS 30 = 30 MIPS Device ID T = Tape and Reel A,B,C… = Revision Level Example: dsPIC30F4013AT-30I/PT = 30 MIPS, Industrial temp., TQFP package, Rev. A  2010 Microchip Technology Inc. DS70138G-page 227

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: DSPIC30F3014-30I/PT DSPIC30F3014-30I/ML DSPIC30F4013-30I/P DSPIC30F4013-30I/PT DSPIC30F4013- 30I/ML DSPIC30F3014-30I/P DSPIC30F3014-30I/PT DSPIC30F3014-30I/ML DSPIC30F4013-30I/P DSPIC30F4013- 30I/PT DSPIC30F4013-30I/ML DSPIC30F3014-30I/P DSPIC30F3014-20E/ML DSPIC30F3014-20E/P DSPIC30F3014-20E/PT DSPIC30F3014-20I/ML DSPIC30F3014-20I/P DSPIC30F3014-20I/PT DSPIC30F3014T- 20E/ML DSPIC30F3014T-20E/PT DSPIC30F3014T-30I/ML DSPIC30F3014T-30I/PT DSPIC30F4013-20E/ML DSPIC30F4013-20E/P DSPIC30F4013-20E/PT DSPIC30F4013-20I/ML DSPIC30F4013-20I/P DSPIC30F4013-20I/PT DSPIC30F4013T-20E/ML DSPIC30F4013T-20E/PT DSPIC30F4013T-30I/ML DSPIC30F4013T-30I/PT