dsPIC30F2010 Data Sheet High-Performance, 16-bit Digital Signal Controllers © 2011 Microchip Technology Inc. DS70118J

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-889-4 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70118J-page 2 © 2011 Microchip Technology Inc.

PIC30F2010 ds High-Performance, 16-bit Digital Signal Controller Peripheral Features: Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not • High current sink/source I/O pins: 25 mA/25 mA intended to be a complete reference • Three 16-bit timers/counters; optionally pair up source. For more information on the CPU, 16-bit timers into 32-bit timer modules peripherals, register descriptions and • Four 16-bit capture input functions general device functionality, refer to the • Two 16-bit compare/PWM output functions “dsPIC30F Family Reference Manual” (DS70046). For more information on the - Dual Compare mode available device instruction set and programming, • 3-wire SPI modules (supports 4 Frame modes) refer to the “16-bit MCU and DSC Pro- • I2CTM module supports Multi-Master/Slave mode grammer’s Reference Manual” and 7-bit/10-bit addressing (DS70157). • Addressable UART modules with FIFO buffers High-Performance Modified RISC CPU: Motor Control PWM Module Features: • Modified Harvard architecture • Six PWM output channels • C compiler optimized instruction set architecture - Complementary or Independent Output • 83 base instructions with flexible addressing modes modes - Edge and Center-Aligned modes • 24-bit wide instructions, 16-bit wide data path • Four duty cycle generators • 12 Kbytes on-chip Flash program space • Dedicated time base with four modes • 512 bytes on-chip data RAM • Programmable output polarity • 1 Kbyte nonvolatile data EEPROM • Dead-time control for Complementary mode • 16 x 16-bit working register array • Manual output control • Up to 30 MIPs operation: • Trigger for synchronized A/D conversions - DC to 40 MHz external clock input - 4 MHz-10 MHz oscillator input with Quadrature Encoder Interface Module PLL active (4x, 8x, 16x) Features: • 27 interrupt sources • Phase A, Phase B and Index Pulse input • Three external interrupt sources • 16-bit up/down position counter • Eight user-selectable priority levels for each interrupt • Count direction status • Four processor exceptions and software traps • Position Measurement (x2 and x4) mode DSP Engine Features: • Programmable digital noise filters on inputs • Alternate 16-bit Timer/Counter mode • Modulo and Bit-Reversed modes • Interrupt on position counter rollover/underflow • Two 40-bit wide accumulators with optional saturation logic Analog Features: • 17-bit x 17-bit single-cycle hardware fractional/ integer multiplier • 10-bit Analog-to-Digital Converter (ADC) with: • Single-cycle Multiply-Accumulate (MAC) - 1 Msps (for 10-bit A/D) conversion rate operation - Six input channels • 40-stage Barrel Shifter - Conversion available during Sleep and Idle • Dual data fetch • Programmable Brown-out Reset © 2011 Microchip Technology Inc. DS70118J-page 3

dsPIC30F2010 Special Digital Signal Controller CMOS Technology: Features: • Low-power, high-speed Flash technology • Enhanced Flash program memory: • Wide operating voltage range (2.5V to 5.5V) - 10,000 erase/write cycle (min.) for • Industrial and Extended temperature ranges industrial temperature range, 100K (typical) • Low power consumption • Data EEPROM memory: - 100,000 erase/write cycle (min.) for industrial temperature range, 1M (typical) • Self-reprogrammable under software control • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Flexible Watchdog Timer (WDT) with on-chip low-power RC oscillator for reliable operation • Fail-Safe Clock Monitor (FSCM) operation • Detects clock failure and switches to on-chip Low-Power RC (LPRC) oscillator • Programmable code protection • In-Circuit Serial Programming™ (ICSP™) programming capability • Selectable Power Management modes - Sleep, Idle and Alternate Clock modes dsPIC30F Motor Control and Power Conversion Family Device Pins MInePsmtrrou.g cBrtayiomten ss/ SBRytAeMs EEBPyRteOsM T16im-beirt InCpaupt COoPmuWtppM/uSttd CMPooWnttoMror l A1/D M 1s0p-bsit QEI UART SPI 2TMIC dsPIC30F2010 28 12K/4K 512 1024 3 4 2 6 ch 6 ch Yes 1 1 1 DS70118J-page 4 © 2011 Microchip Technology Inc.

dsPIC30F2010 Pin Diagrams 28-Pin SDIP and SOIC MCLR 1 28 AVDD EMUD3/AN0/VREF+/CN2/RB0 2 27 AVSS EMUC3/AN1/VREF-/CN3/RB1 3 26 PWM1L/RE0 AN2/SS1/CN4/RB2 4 25 PWM1H/RE1 AN3/INDX/CN5/RB3 5 ds 24 PWM2L/RE2 AN4/QEA/IC7/CN6/RB4 6 P 23 PWM2H/RE3 AN5/QEB/IC8/CN7/RB5 7 IC 22 PWM3L/RE4 3 VSS 8 0 21 PWM3H/RE5 OSC1/CLKI 9 F2 20 VDD OSC2/CLKO/RC15 10 01 19 VSS EMUD1/SOSCI/T2CK/U1ATX/CN1//RC13 11 0 18 PGC/EMUC/U1RX/SDI1/SDA/RF2 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 12 17 PGD/EMUD/U1TX/SDO1/SCL/RF3 VDD 13 16 FLTA/INT0/SCK1/OCFA/RE8 EMUD2/OC2/IC2/INT2/RD1 14 15 EMUC2/OC1/IC1/INT1/RD0 28-Pin QFN-S(1) 10 BB RR 3/2/ NN CC F- /F+/ EE RR VV MUC3/AN1/MUD3/AN0/CLRVDDVSSWM1L/RE0WM1H/RE1 EEMAAPP 8765432 2222222 AN2/SS1/CN4/RB2 1 21 PWM2L/RE2 AN3/INDX/CN5 RB3 2 20 PWM2H/RE3 AN4/QEA/IC7/CN6/RB4 3 19 PWM3L/RE4 AN5/QEB/IC8/CN7/RB5 4 dsPIC30F2010 18 PWM3H/RE5 VSS 5 17 VDD OSC1/CLKI 6 16 VSS OSC2/CLKO/RC15 7 15 PGC/EMUC/U1RX/SDI1/SDA/RF2 891011121314 SOSCI/T2CK/U1ATX/CN1/RC13OSCO/T1CK/U1ARX/CN0/RC14VDDEMUD2/OC2/IC2/INT2/RD1EMUC2/OC1/IC1/INT1/RD0FLTA/INT0/SCK1/OCFA/RE8D/EMUD/U1TX/SDO1/SCL/RF3 D1/1/S PG UC MU EM E Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. © 2011 Microchip Technology Inc. DS70118J-page 5

dsPIC30F2010 Table of Contents 1.0 Device Overview..........................................................................................................................................................................7 2.0 CPU Architecture Overview........................................................................................................................................................11 3.0 Memory Organization.................................................................................................................................................................19 4.0 Address Generator Units............................................................................................................................................................31 5.0 Interrupts....................................................................................................................................................................................37 6.0 Flash Program Memory..............................................................................................................................................................43 7.0 Data EEPROM Memory.............................................................................................................................................................49 8.0 I/O Ports.....................................................................................................................................................................................53 9.0 Timer1 Module...........................................................................................................................................................................57 10.0 Timer2/3 Module........................................................................................................................................................................61 11.0 Input Capture Module.................................................................................................................................................................67 12.0 Output Compare Module............................................................................................................................................................71 13.0 Quadrature Encoder Interface (QEI) Module.............................................................................................................................75 14.0 Motor Control PWM Module.......................................................................................................................................................81 15.0 SPI Module.................................................................................................................................................................................91 16.0 I2C™ Module.............................................................................................................................................................................95 17.0 Universal Asynchronous Receiver Transmitter (UART) Module..............................................................................................103 18.0 10-bit High-Speed Analog-to-Digital Converter (ADC) Module................................................................................................111 19.0 System Integration...................................................................................................................................................................121 20.0 Instruction Set Summary..........................................................................................................................................................135 21.0 Development Support...............................................................................................................................................................143 22.0 Electrical Characteristics..........................................................................................................................................................147 23.0 Packaging Information..............................................................................................................................................................185 The Microchip Web Site.....................................................................................................................................................................199 Customer Change Notification Service..............................................................................................................................................199 Customer Support..............................................................................................................................................................................199 Reader Response..............................................................................................................................................................................200 Product Identification System.............................................................................................................................................................201 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70118J-page 6 © 2011 Microchip Technology Inc.

dsPIC30F2010 1.0 DEVICE OVERVIEW Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Pro- grammer’s Reference Manual” (DS70157). This document contains device specific information for the dsPIC30F2010 device. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure1-1 shows a device block diagram for the dsPIC30F2010 device. © 2011 Microchip Technology Inc. DS70118J-page 7

dsPIC30F2010 FIGURE 1-1: dsPIC30F2010 BLOCK DIAGRAM Y Data Bus X Data Bus 16 16 16 16 16 Interrupt Data Latch Data Latch Controller PSV and Table Y Data X Data Data Access 24Control Block 8 16 RAM RAM (256 bytes) (256 bytes) Address Address 24 Latch Latch 16 16 16 24 X RAGU Y AGU PCU PCH PCL X WAGU EMUD3/AN0/VREF+/CN2/RB0 Program Counter EMUC3/AN1/VREF-/CN3/RB1 Address Latch Stack Loop AN2/SS1/CN4/RB2 Control Control Program Memory Logic Logic AN3/INDX/CN5/RB3 (12 Kbytes) AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 Data EEPROM (1 Kbyte) Effective Address PORTB Data Latch 16 ROM Latch 16 24 IR EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 16 16 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 16 x 16 W Reg Array PORTC Decode Instruction Decode and 16 16 Control Ctoo Vnatrroiol uSsig Bnlaolcsk s Power-up E DngSiPne D Uivnidite Timer OSC1/CLKI Timing Oscillator EMUC2/OC1/IC1/INT1/RD0 Generation Start-up Timer EMUD2/OC2/IC2/INT2/RD1 POR/BOR ALU<16> PORTD Reset MCLR Watchdog 16 16 Timer Input O utput 10-bit ADC Capture Com pare I2C™ PWM1L/RE0 Module Module PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 Motor Control FLTA/INT0/SCK1/OCFA/RE8 SPI1 Timers QEI UART1 PWM PORTE PGC/EMUC/U1RX/SDI1/SDA/RF2 PGD/EMUD/U1TX/SDO1/SCL/RF3 PORTF DS70118J-page 8 © 2011 Microchip Technology Inc.

dsPIC30F2010 Table1-1 provides a brief description of device I/O pin- outs and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name Description Type Type AN0-AN5 I Analog Analog input channels. AVDD P P Positive supply for analog module. This pin must be connected at all times. AVSS P P Ground reference for analog module. This pin must be connected at all times. CLKI I ST/CMOS External clock source input. Always associated with OSC1 pin function. CLKO O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. CN0-CN7 I ST Input change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. EMUD I/O ST ICD Primary Communication Channel data input/output pin. EMUC I/O ST ICD Primary Communication Channel clock input/output pin. EMUD1 I/O ST ICD Secondary Communication Channel data input/output pin. EMUC1 I/O ST ICD Secondary Communication Channel clock input/output pin. EMUD2 I/O ST ICD Tertiary Communication Channel data input/output pin. EMUC2 I/O ST ICD Tertiary Communication Channel clock input/output pin. EMUD3 I/O ST ICD Quaternary Communication Channel data input/output pin. EMUC3 I/O ST ICD Quaternary Communication Channel clock input/output pin. IC1, IC2, IC7, I ST Capture inputs. The dsPIC30F2010 has four capture inputs. The inputs are IC8 numbered for consistency with the inputs on larger device variants. INDX I ST Quadrature Encoder Index Pulse input. QEA I ST Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. QEB I ST Quadrature Encoder Phase B input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. INT0 I ST External interrupt 0 INT1 I ST External interrupt 1 INT2 I ST External interrupt 2 FLTA I ST PWM Fault A input PWM1L O — PWM 1 Low output PWM1H O — PWM 1 High output PWM2L O — PWM 2 Low output PWM2H O — PWM 2 High output PWM3L O — PWM 3 Low output PWM3H O — PWM 3 High output MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active-low Reset to the device. OCFA I ST Compare Fault A input (for Compare channels 1, 2, 3 and 4). OC1-OC2 O — Compare outputs. OSC1 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. OSC2 I/O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power © 2011 Microchip Technology Inc. DS70118J-page 9

dsPIC30F2010 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Description Type Type PGD I/O ST In-Circuit Serial Programming™ (ICSP™) data input/output pin. PGC I ST In-Circuit Serial Programming clock input pin. RB0-RB5 I/O ST PORTB is a bidirectional I/O port. RC13-RC14 I/O ST PORTC is a bidirectional I/O port. RD0-RD1 I/O ST PORTD is a bidirectional I/O port. RE0-RE5, I/O ST PORTE is a bidirectional I/O port. RE8 RF2, RF3 I/O ST PORTF is a bidirectional I/O port. SCK1 I/O ST Synchronous serial clock input/output for SPI1. SDI1 I ST SPI1 Data In. SDO1 O — SPI1 Data Out. SS1 I ST SPI1 Slave Synchronization. SCL I/O ST Synchronous serial clock input/output for I2C™. SDA I/O ST Synchronous serial data input/output for I2C. SOSCO O — 32 kHz low-power oscillator crystal output. SOSCI I ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. T1CK I ST Timer1 external clock input. T2CK I ST Timer2 external clock input. U1RX I ST UART1 Receive. U1TX O — UART1 Transmit. U1ARX I ST UART1 Alternate Receive. U1ATX O — UART1 Alternate Transmit. VDD P — Positive supply for logic and I/O pins. VSS P — Ground reference for logic and I/O pins. VREF+ I Analog Analog Voltage Reference (High) input. VREF- I Analog Analog Voltage Reference (Low) input. Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power DS70118J-page 10 © 2011 Microchip Technology Inc.

dsPIC30F2010 2.0 CPU ARCHITECTURE • Linear indirect access of 32K word pages within program space is also possible using any working OVERVIEW register, via table read and write instructions. Table read and write instructions can be used to Note: This data sheet summarizes features of access all 24 bits of an instruction word. this group ofdsPIC30F devices and is not intended to be a complete reference Overhead-free circular buffers (Modulo Addressing) source. For more information on the CPU, are supported in both X and Y address spaces. This is peripherals, register descriptions and primarily intended to remove the loop overhead for general device functionality, refer to the DSP algorithms. “dsPIC30F Family Reference Manual” The X AGU also supports Bit-Reversed Addressing on (DS70046). For more information on the destination effective addresses, to greatly simplify input device instruction set and programming, or output data reordering for radix-2 FFT algorithms. refer to the “16-bit MCU and DSC Pro- Refer to Section4.0 “Address Generator Units” for grammer’s Reference Manual” (DS70157). details on Modulo and Bit-Reversed Addressing. The core supports Inherent (no operand), Relative, Lit- 2.1 Core Overview eral, Memory Direct, Register Direct, Register Indirect, Register Offset and Literal Offset Addressing modes. The core has a 24-bit instruction word. The Program Instructions are associated with predefined Addressing Counter (PC) is 23 bits wide with the Least Significant modes, depending upon their functional requirements. bit (LSb) always clear (see Section3.1 “Program For most instructions, the core is capable of executing Address Space”), and the Most Significant bit (MSb) a data (or program data) memory read, a working reg- is ignored during normal program execution, except for ister (data) read, a data memory write and a program certain specialized instructions. Thus, the PC can (instruction) memory read per instruction cycle. As a address up to 4M instruction words of user program result, 3-operand instructions are supported, allowing space. An instruction prefetch mechanism is used to C=A + B operations to be executed in a single cycle. help maintain throughput. Program loop constructs, free from loop count management overhead, are sup- A DSP engine has been included to significantly ported using the DO and REPEAT instructions, both of enhance the core arithmetic capability and throughput. which are interruptible at any point. It features a high-speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a The working register array consists of 16x16-bit regis- 40-bit bidirectional barrel shifter. Data in the accumula- ters, each of which can act as data, address or offset tor or any working register can be shifted up to 15 bits registers. One working register (W15) operates as a right or 16 bits left in a single cycle. The DSP instruc- software Stack Pointer for interrupts and calls. tions operate seamlessly with all other instructions and The data space is 64 Kbytes (32K words) and is split have been designed for optimal real-time performance. into two blocks, referred to as X and Y data memory. The MAC class of instructions can concurrently fetch Each block has its own independent Address Genera- two data operands from memory, while multiplying two tion Unit (AGU). Most instructions operate solely W registers. To enable this concurrent fetching of data through the X memory AGU, which provides the operands, the data space has been split for these appearance of a single unified data space. The instructions and linear for all others. This has been Multiply-Accumulate (MAC) class of dual source DSP achieved in a transparent and flexible manner, by instructions operate through both the X and Y AGUs, dedicating certain working registers to each address splitting the data address space into two parts (see space for the MAC class of instructions. Section3.2 “Data Address Space”). The X and Y The core does not support a multi-stage instruction data space boundary is device specific and cannot be pipeline. However, a single stage instruction prefetch altered by the user. Each data word consists of 2 bytes, mechanism is used, which accesses and partially and most instructions can address data either as words decodes instructions a cycle ahead of execution, in or bytes. order to maximize available execution time. Most There are two methods of accessing data stored in instructions execute in a single cycle, with certain program memory: exceptions. • The upper 32 Kbytes of data space memory can be The core features a vectored exception processing mapped into the lower half (user space) of program structure for traps and interrupts, with 62 independent space at any 16K program word boundary, defined by vectors. The exceptions consist of up to 8 traps (of the 8-bit Program Space Visibility Page (PSVPAG) which 4 are reserved) and 54 interrupts. Each interrupt register. This lets any instruction access program is prioritized based on a user-assigned priority between space as if it were data space, with a limitation that 1 and 7 (1 being the lowest priority and 7 being the the access requires an additional cycle. Moreover, highest) in conjunction with a predetermined ‘natural only the lower 16 bits of each instruction word can be order’. Traps have fixed priorities, ranging from 8 to 15. accessed using this method. © 2011 Microchip Technology Inc. DS70118J-page 11

dsPIC30F2010 2.2 Programmer’s Model 2.2.1 SOFTWARE STACK POINTER/ FRAME POINTER The programmer’s model is shown in Figure2-1 and consists of 16 x 16-bit working registers (W0 through The dsPIC® DSC devices contain a software stack. W15), 2 x 40-bit accumulators (ACCA and ACCB), W15 is the dedicated software Stack Pointer (SP), and STATUS Register (SR), Data Table Page register will be automatically modified by exception processing (TBLPAG), Program Space Visibility Page register and subroutine calls and returns. However, W15 can be (PSVPAG), DO and REPEAT registers (DOSTART, referenced by any instruction in the same manner as all DOEND, DCOUNT and RCOUNT) and Program Coun- other W registers. This simplifies the reading, writing ter (PC). The working registers can act as data, and manipulation of the Stack Pointer (e.g., creating address or offset registers. All registers are memory stack frames). mapped. W0 acts as the W register for file register Note: In order to protect against misaligned addressing. stack accesses, W15<0> is always clear. Some of these registers have a shadow register asso- W15 is initialized to 0x0800 during a Reset. The user ciated with each of them, as shown in Figure2-1. The may reprogram the SP during initialization to any shadow register is used as a temporary holding register location within data space. and can transfer its contents to or from its host register upon the occurrence of an event. None of the shadow W14 has been dedicated as a Stack Frame Pointer as registers are accessible directly. The following rules defined by the LNK and ULNK instructions. However, apply for transfer of registers into and out of shadows. W14 can be referenced by any instruction in the same manner as all other W registers. • PUSH.S and POP.S W0, W1, W2, W3, SR (DC, N, OV, Z and C bits 2.2.2 STATUS REGISTER only) are transferred. The dsPIC DSC core has a 16-bit STATUS Register • DO instruction (SR), the LSB of which is referred to as the SR Low DOSTART, DOEND, DCOUNT shadows are Byte (SRL) and the MSB as the SR High Byte (SRH). pushed on loop start, and popped on loop end. See Figure 2-1 for SR layout. When a byte operation is performed on a working reg- SRL contains all the MCU ALU operation status flags ister, only the Least Significant Byte (LSB) of the target (including the Z bit), as well as the CPU Interrupt Prior- register is affected. However, a benefit of memory ity Level status bits, IPL<2:0>, and the REPEAT active mapped working registers is that both the Least and status bit, RA. During exception processing, SRL is Most Significant Bytes can be manipulated through concatenated with the MSB of the PC to form a byte wide data memory space accesses. complete word value which is then stacked. The upper byte of the STATUS register contains the DSP adder/subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address up to 4M instruction words. DS70118J-page 12 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 2-1: PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 DSP Operand W5 Registers W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP Offset W13/DSP Write-Back W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register AD39 AD31 AD15 AD0 DSP ACCA Accumulators ACCB PC22 PC0 0 Program Counter 7 0 TTBALBPPAAGG Data Table Page Address 7 0 PPSSVVPPAAGG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address 22 DOEND DO Loop End Address 15 0 CORCON Core Configuration Register OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRH SRL © 2011 Microchip Technology Inc. DS70118J-page 13

dsPIC30F2010 2.3 Divide Support 2.4 DSP Engine The dsPIC DSC devices feature a 16/16-bit signed The DSP engine consists of a high-speed 17-bit x fractional divide operation, as well as 32/16-bit and 16/ 17-bit multiplier, a barrel shifter, and a 40-bit adder/sub- 16-bit signed and unsigned integer divide operations, in tracter (with two target accumulators, round and the form of single instruction iterative divides. The saturation logic). following instructions and data sizes are supported: The DSP engine also has the capability to perform inher- • DIVF – 16/16 signed fractional divide ent accumulator-to-accumulator operations, which • DIV.sd – 32/16 signed divide require no additional data. These instructions are ADD, SUB, and NEG. • DIV.ud – 32/16 unsigned divide • DIV.sw – 16/16 signed divide The DSP engine has various options selected through various bits in the CPU Core Configuration Register • DIV.uw – 16/16 unsigned divide (CORCON), as listed below: The 16/16 divides are similar to the 32/16 (same number • Fractional or integer DSP multiply (IF). of iterations), but the dividend is either zero-extended or sign-extended during the first iteration. • Signed or unsigned DSP multiply (US). • Conventional or convergent rounding (RND). The divide instructions must be executed within a REPEAT loop. Any other form of execution (e.g., a • Automatic saturation on/off for ACCA (SATA). series of discrete divide instructions) will not function • Automatic saturation on/off for ACCB (SATB). correctly because the instruction flow depends on • Automatic saturation on/off for writes to data RCOUNT. The divide instruction does not automatically memory (SATDW). set up the RCOUNT value, and it must, therefore, be • Accumulator Saturation mode selection (ACC- explicitly and correctly specified in the REPEAT instruc- SAT). tion, as shown in Table2-2 (REPEAT will execute the Note: For CORCON layout, see Table3-3. target instruction {operand value + 1} times). The REPEAT loop count must be set up for 18 iterations of A block diagram of the DSP engine is shown in the DIV/DIVF instruction. Thus, a complete divide Figure2-2. operation requires 19 cycles. TABLE 2-1: DSP INSTRUCTION Note: The Divide flow is interruptible; however, SUMMARY the user needs to save the context as Algebraic appropriate. Instruction ACC WB? Operation CLR A = 0 Yes ED A = (x – y)2 No EDAC A = A + (x – y)2 No MAC A = A + (x•y) Yes MAC A = A + x2 No MOVSAC No change in A Yes MPY A = x•y No MPY.N A = – x•y No MSC A = A – x•y Yes TABLE 2-2: DIVIDE INSTRUCTIONS Instruction Function DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1 DIV.sd Signed divide: (Wm + 1:Wm)/Wn → W0; Rem → W1 DIV.ud Unsigned divide: (Wm + 1:Wm)/Wn → W0; Rem → W1 DIV.sw (or DIV.s) Signed divide: Wm/Wn → W0; Rem → W1 DIV.uw (or DIV.u) Unsigned divide: Wm/Wn → W0; Rem → W1 DS70118J-page 14 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM S a 40 40-bit Accumulator A 40 Round t 16 u 40-bit Accumulator B Logic r a Carry/Borrow Out t Saturate e Adder Carry/Borrow In Negate 40 40 40 Barrel 16 Shifter 40 s u B a at D Sign-Extend X s u B a 32 16 at Zero Backfill D Y 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array © 2011 Microchip Technology Inc. DS70118J-page 15

dsPIC30F2010 2.4.1 MULTIPLIER 2.4.2.1 Adder/Subtracter, Overflow and Saturation The 17 x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output The adder/subtracter is a 40-bit adder with an optional using a scaler to support either 1.31 fractional (Q31) zero input into one side and either true or complement or 32-bit integer results. Unsigned operands are data into the other input. In the case of addition, the zero-extended into the 17th bit of the multiplier input carry/borrow input is active high and the other input is value. Signed operands are sign-extended into the true data (not complemented), whereas in the case of 17th bit of the multiplier input value. The output of subtraction, the carry/borrow input is active low and the the 17 x 17-bit multiplier/scaler is a 33-bit value, other input is complemented. The adder/subtracter which is sign-extended to 40 bits. Integer data is generates overflow status bits SA/SB and OA/OB, inherently represented as a signed two’s complement which are latched and reflected in the STATUS value, where the MSB is defined as a sign bit. Register. Generally speaking, the range of an N-bit two’s • Overflow from bit 39: this is a catastrophic complement integer is -2N-1 to 2N-1 – 1. For a 16-bit overflow in which the sign of the accumulator is integer, the data range is -32768 (0x8000) to 32767 destroyed. (0x7FFF), including ‘0’. For a 32-bit integer, the data • Overflow into guard bits 32 through 39: this is a range is -2,147,483,648 (0x80000000) to recoverable overflow. This bit is set whenever all 2,147,483,645 (0x7FFF FFFF). the guard bits are not identical to each other. When the multiplier is configured for fractional The adder has an additional saturation block which multiplication, the data is represented as a two’s controls accumulator data saturation, if selected. It complement fraction, where the MSB is defined as a uses the result of the adder, the overflow status bits sign bit and the radix point is implied to lie just after the described above, and the SATA/B (CORCON<7:6>) sign bit (QX format). The range of an N-bit two’s and ACCSAT (CORCON<4>) mode control bits to complement fraction with this implied radix point is -1.0 to (1-21-N). For a 16-bit fraction, the Q15 data range is determine when and to what value to saturate. -1.0 (0x8000) to 0.999969482 (0x7FFF), including ‘0’ Six STATUS register bits have been provided to and has a precision of 3.01518x10-5. In Fractional support saturation and overflow; they are: mode, a 16x16 multiply operation generates a 1.31 1. OA: product, which has a precision of 4.65661x10-10. ACCA overflowed into guard bits The same multiplier is used to support the MCU multi- 2. OB: ply instructions, which include integer 16-bit signed, ACCB overflowed into guard bits unsigned and mixed sign multiplies. 3. SA: The MUL instruction may be directed to use byte or ACCA saturated (bit 31 overflow and saturation) word-sized operands. Byte operands will direct a 16-bit or result, and word operands will direct a 32-bit result to ACCA overflowed into guard bits and saturated the specified register(s) in the W array. (bit 39 overflow and saturation) 4. SB: 2.4.2 DATA ACCUMULATORS AND ACCB saturated (bit 31 overflow and saturation) ADDER/SUBTRACTER or The data accumulator consists of a 40-bit adder/ ACCB overflowed into guard bits and saturated subtracter with automatic sign extension logic. It can (bit 39 overflow and saturation) select one of two accumulators (A or B) as its pre- 5. OAB: accumulation source and post-accumulation Logical OR of OA and OB destination. For the ADD and LAC instructions, the data 6. SAB: to be accumulated or loaded can be optionally scaled Logical OR of SA and SB via the barrel shifter, prior to accumulation. The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the correspond- ing overflow trap flag enable bit (OVATE, OVBTE) in the INTCON1 register (refer to Section5.0 “Inter- rupts”) is set. This allows the user to take immediate action, for example, to correct system gain. DS70118J-page 16 © 2011 Microchip Technology Inc.

dsPIC30F2010 The SA and SB bits are modified each time data passes 2.4.2.2 Accumulator ‘Write-Back’ through the adder/subtracter, but can only be cleared by The MAC class of instructions (with the exception of the user. When set, they indicate that the accumulator MPY, MPY.N, ED and EDAC) can optionally write a has overflowed its maximum range (bit 31 for 32-bit rounded version of the high word (bits 31 through 16) saturation, or bit 39 for 40-bit saturation) and will be of the accumulator that is not targeted by the instruction saturated (if saturation is enabled). When saturation is into data space memory. The write is performed across not enabled, SA and SB default to bit 39 overflow and the X bus into combined X and Y address space. The thus indicate that a catastrophic overflow has occurred. following addressing modes are supported: If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when 1. W13, Register Direct: saturation is disabled. The rounded contents of the non-target accumulator are written into W13 as a 1.15 The overflow and saturation status bits can optionally fraction. be viewed in the Status Register (SR) as the logical OR 2. [W13]+=2, Register Indirect with Post-Increment: of OA and OB (in bit OAB), and the logical OR of SA The rounded contents of the non-target accumu- and SB (in bit SAB). This allows programmers to check lator are written into the address pointed to by one bit in the STATUS register to determine if either W13 as a 1.15 fraction. W13 is then accumulator has overflowed, or one bit to determine if incremented by 2 (for a word write). either accumulator has saturated. This would be useful for complex number arithmetic which typically uses 2.4.2.3 Round Logic both the accumulators. The round logic is a combinational block, which The device supports three Saturation and Overflow performs a conventional (biased) or convergent modes. (unbiased) round function during an accumulator write 1. Bit 39 Overflow and Saturation: (store). The Round mode is determined by the state of When bit 39 overflow and saturation occurs, the the RND bit in the CORCON register. It generates a 16- saturation logic loads the maximally positive 9.31 bit, 1.15 data value which is passed to the data space (0x7FFFFFFFFF) or maximally negative 9.31 write saturation logic. If rounding is not indicated by the value (0x8000000000) into the target accumula- instruction, a truncated 1.15 data value is stored and the tor. The SA or SB bit is set and remains set until least significant word (lsw) is simply discarded. cleared by the user. This is referred to as ‘super Conventional rounding takes bit 15 of the accumulator, saturation’ and provides protection against erro- zero-extends it and adds it to the ACCxH word (bits 16 neous data or unexpected algorithm problems through 31 of the accumulator). If the ACCxL word (bits (e.g., gain calculations). 0 through 15 of the accumulator) is between 0x8000 2. Bit 31 Overflow and Saturation: and 0xFFFF (0x8000 included), ACCxH is incre- When bit 31 overflow and saturation occurs, the mented. If ACCxL is between 0x0000 and 0x7FFF, saturation logic then loads the maximally positive ACCxH is left unchanged. A consequence of this 1.31 value (0x007FFFFFFF) or maximally nega- algorithm is that over a succession of random rounding tive 1.31 value (0x0080000000) into the target operations, the value will tend to be biased slightly accumulator. The SA or SB bit is set and remains positive. set until cleared by the user. When this Saturation Convergent (or unbiased) rounding operates in the mode is in effect, the guard bits are not used (so same manner as conventional rounding, except when the OA, OB or OAB bits are never set). ACCxL equals 0x8000. If this is the case, the Least Sig- 3. Bit 39 Catastrophic Overflow nificant bit (bit 16 of the accumulator) of ACCxH is The bit 39 overflow status bit from the adder is examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’, used to set the SA or SB bit, which remain set ACCxH is not modified. Assuming that bit 16 is effec- until cleared by the user. No saturation operation tively random in nature, this scheme will remove any is performed and the accumulator is allowed to rounding bias that may accumulate. overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic The SAC and SAC.R instructions store either a trun- overflow can initiate a trap exception. cated (SAC) or rounded (SAC.R) version of the contents of the target accumulator to data memory, via the X bus (subject to data saturation, see Section2.4.2.4 “Data Space Write Saturation”). Note that for the MAC class of instructions, the accumulator write-back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. © 2011 Microchip Technology Inc. DS70118J-page 17

dsPIC30F2010 2.4.2.4 Data Space Write Saturation 2.4.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data The barrel shifter is capable of performing up to 15-bit space may also be saturated, but without affecting the arithmetic or logic right shifts, or up to 16-bit left shifts contents of the source accumulator. The data space in a single cycle. The source can be either of the two write saturation logic block accepts a 16-bit, 1.15 DSP accumulators or the X bus (to support multi-bit fractional value from the round logic block as its input, shifts of register or memory data). together with overflow status from the original source The shifter requires a signed binary value to determine (accumulator) and the 16-bit round adder. These are both the magnitude (number of bits) and direction of the combined and used to select the appropriate 1.15 shift operation. A positive value will shift the operand fractional value as output to write to data space right. A negative value will shift the operand left. A memory. value of 0 will not modify the operand. If the SATDW bit in the CORCON register is set, data The barrel shifter is 40 bits wide, thereby obtaining a (after rounding or truncation) is tested for overflow and 40-bit result for DSP shift operations and a 16-bit result adjusted accordingly. For input data greater than for MCU shift operations. Data from the X bus is pre- 0x007FFF, data written to memory is forced to the sented to the barrel shifter between bit positions 16 to maximum positive 1.15 value, 0x7FFF. For input data 31 for right shifts, and bit positions 0 to 15 for left shifts. less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. DS70118J-page 18 © 2011 Microchip Technology Inc.

dsPIC30F2010 3.0 MEMORY ORGANIZATION FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F2010 Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not Reset - GOTO Instruction 000000 intended to be a complete reference Reset - Target Address 000002 Reserved 000004 source. For more information on the CPU, Ext. Osc. Fail Trap peripherals, register descriptions and Address Error Trap Stack Error Trap general device functionality, refer to the Arithmetic Warn. Trap “dsPIC30F Family Reference Manual” Reserved Vector Tables Reserved (DS70046). For more information on the Reserved device instruction set and programming, Vector 0 000014 Vector 1 refer to the “16-bit MCU and DSC Pro- grammer’s Reference Manual” (DS70157). Vector 52 Vector 53 00007E y Alternate Vector Table 000080 3.1 Program Address Space or 0000FE me 000100 ec The program address space is 4M instruction words. It er MSpa ProUgrsaemr F Mlaesmhory is addressable by a 24-bit value from either the 23-bit Us (4K instructions) PC, table instruction Effective Address (EA), or data 001FFE space EA, when program space is mapped into data 002000 Reserved space, as defined by Table3-1. Note that the program (Read 0’s) space address is incremented by two between succes- 7FFBFE 7FFC00 sive program words, in order to provide compatibility Data EEPROM with data space addressing. (1 Kbyte) 7FFFFE User program space access is restricted to the lower 800000 4M instruction word address range (0x000000 to 0x7FFFFE), for all accesses other than TBLRD/TBLWT, which use TBLPAG<7> to determine user or configura- tion space access. In Table3-1, Read/Write instruc- tions, bit23 allows access to the Device ID, the User ID and the Configuration bits. Otherwise, bit 23 is always clear. Reserved Note: The address map shown in Figure3-1 is conceptual, and the actual memory con- figuration may vary across individual devices depending on available memory. y or m e M 8005BE uration Space UNITID (32 instr.) 88000055FCE0 nfig 800600 o Reserved C F7FFFE Device Configuration F80000 Registers F8000E F80010 Reserved FEFFFE DEVID (2) FF0000 FFFFFE © 2011 Microchip Technology Inc. DS70118J-page 19

dsPIC30F2010 TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 TBLRD/TBLWT User (TBLPAG<7> = 0) TBLPAG<7:0> Data EA <15:0> TBLRD/TBLWT Configuration (TBLPAG<7> = 1) TBLPAG<7:0> Data EA <15:0> Program Space Visibility User 0 PSVPAG<7:0> Data EA <14:0> FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 23 bits Using Program 0 Program Counter 0 Counter Select 1 EA Using Program 0 PSVPAG Reg Space Visibility 8 bits 15 bits EA Using 1/0 TBLPAG Reg Table Instruction 8 bits 16 bits User/ Byte Configuration 24-bit EA Select Space Select Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory. DS70118J-page 20 © 2011 Microchip Technology Inc.

dsPIC30F2010 3.1.1 DATA ACCESS FROM PROGRAM A set of Table Instructions are provided to move byte or MEMORY USING TABLE word-sized data to and from program space. INSTRUCTIONS 1. TBLRDL: Table Read Low This architecture fetches 24-bit wide program memory. Word: Read the least significant word of the Consequently, instructions are always aligned. How- program address; ever, as the architecture is modified Harvard, data can P<15:0> maps to D<15:0>. also be present in program space. Byte: Read one of the LSBs of the program address; There are two methods by which program space can P<7:0> maps to the destination byte when byte be accessed: via special table instructions, or through select = 0; the remapping of a 16K word program space page into P<15:8> maps to the destination byte when byte the upper half of data space (see Section3.1.2 “Data select = 1. Access from Program Memory Using Program 2. TBLWTL: Table Write Low (refer to Section6.0 Space Visibility”). The TBLRDL and TBLWTL instruc- “Flash Program Memory” for details on Flash tions offer a direct method of reading or writing the lsw Programming). of any address within program space, without going through data space. The TBLRDH and TBLWTH instruc- 3. TBLRDH: Table Read High tions are the only method whereby the upper 8 bits of a Word: Read the most significant word of the program space word can be accessed as data. program address; P<23:16> maps to D<7:0>; D<15:8> always The PC is incremented by two for each successive be = 0. 24-bit program word. This allows program memory Byte: Read one of the MSBs of the program addresses to directly map to data space addresses. address; Program memory can thus be regarded as two 16-bit P<23:16> maps to the destination byte when word wide address spaces, residing side by side, each byte select = 0; with the same address range. TBLRDL and TBLWTL The destination byte will always be = 0 when access the space which contains the least significant byte select = 1. data word, and TBLRDH and TBLWTH access the space 4. TBLWTH: Table Write High (refer to Section6.0 which contains the Most Significant data Byte. “Flash Program Memory” for details on Flash Figure3-2 shows how the EA is created for table oper- Programming). ations and data space accesses (PSV = 1). Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word. FIGURE 3-3: PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD) PC Address 23 16 8 0 0x000000 00000000 0x000002 00000000 0x000004 00000000 0x000006 00000000 TBLRDL.B (Wn<0> = 0) TBLRDL.W Program Memory ‘Phantom’ Byte TBLRDL.B (Wn<0> = 1) (Read as ‘0’) © 2011 Microchip Technology Inc. DS70118J-page 21

dsPIC30F2010 FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE) TBLRDH.W PC Address 23 16 8 0 0x000000 00000000 0x000002 00000000 0x000004 00000000 0x000006 00000000 TBLRDH.B (Wn<0> = 0) Program Memory ‘Phantom’ Byte (Read as ‘0’) TBLRDH.B (Wn<0> = 1) 3.1.2 DATA ACCESS FROM PROGRAM Note that by incrementing the PC by 2 for each pro- MEMORY USING PROGRAM SPACE gram memory word, the Least Significant 15 bits of VISIBILITY data space addresses directly map to the Least Signif- icant 15 bits in the corresponding program space The upper 32 Kbytes of data space may optionally be addresses. The remaining bits are provided by the Pro- mapped into any 16K word program space page. This gram Space Visibility Page register, PSVPAG<7:0>, as provides transparent access of stored constant data shown in Figure3-5. from X data space, without the need to use special instructions (i.e., TBLRDL/H, TBLWTL/H instructions). Note: PSV access is temporarily disabled during table reads/writes. Program space access through the data space occurs if the MSb of the data space EA is set and program For instructions that use PSV which are executed space visibility is enabled, by setting the PSV bit in the outside a REPEAT loop: Core Control register (CORCON). The functions of • The following instructions will require one instruc- CORCON are discussed in Section2.4 “DSP tion cycle in addition to the specified execution Engine”. time: Data accesses to this area add an additional cycle to - MAC class of instructions with data operand the instruction being executed, since two program prefetch memory fetches are required. - MOV instructions Note that the upper half of addressable data space is - MOV.D instructions always part of the X data space. Therefore, when a • All other instructions will require two instruction DSP operation uses program space mapping to access cycles in addition to the specified execution time this memory region, Y data space should typically con- of the instruction. tain state (variable) data for DSP operations, whereas X data space should typically contain coefficient For instructions that use PSV which are executed (constant) data. inside a REPEAT loop: Although each data space address, 0x8000 and higher, • The following instances will require two instruction maps directly into a corresponding program memory cycles in addition to the specified execution time address (see Figure3-5), only the lower 16-bits of the of the instruction: 24-bit program word are used to contain the data. The - Execution in the first iteration upper 8 bits should be programmed to force an illegal - Execution in the last iteration instruction to maintain machine robustness. Refer to - Execution prior to exiting the loop due to an the “16-bit MCU and DSC Programmer’s Reference interrupt Manual” (DS70157) for details on instruction encoding. - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction, accessing data using PSV, to execute in a single cycle. DS70118J-page 22 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space Program Space 0x100100 0x0000 15 PSVPAG(1) EA<15> = 0 0x00 8 Data 16 Space 0x8000 EA 15 23 15 0 Address EA<15> = 1 0x001200 15 Concatenation 23 Upper half of Data Space is mapped into Program Space 0xFFFF 0x001FFE BSET CORCON,#2 ; PSV bit set MOV #0x00, W0 ; Set PSVPAG register MOV W0, PSVPAG MOV 0x9200, W0 ; Access program memory location ; using a data space access Data Read Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines the page in program space to which the upper half of data space is being mapped). 3.2 Data Address Space When executing any instruction other than one of the MAC class of instructions, the X block consists of the The core has two data spaces. The data spaces can be 256 byte data address space (including all Y considered either separate (for some DSP instruc- addresses). When executing one of the MAC class of tions), or as one unified linear address range (for MCU instructions, the X block consists of the 256 bytes data instructions). The data spaces are accessed using two address space excluding the Y address block (for data Address Generation Units (AGUs) and separate data reads only). In other words, all other instructions regard paths. the entire data memory as one composite address space. The MAC class instructions extract the Y 3.2.1 DATA SPACE MEMORY MAP address space from data space and address it using The data space memory is split into two blocks, X and EAs sourced from W10 and W11. The remaining X data Y data space. A key element of this architecture is that space is addressed using W8 and W9. Both address Y space is a subset of X space, and is fully contained spaces are concurrently accessed only with the MAC within X space. In order to provide an apparent linear class instructions. addressing space, X and Y spaces have contiguous A data space memory map is shown in Figure3-6. addresses. © 2011 Microchip Technology Inc. DS70118J-page 23

dsPIC30F2010 FIGURE 3-6: DATA SPACE MEMORY MAP LSB MSB 16 bits Address Address MSB LSB 0x0001 0x0000 SFR Space SFR Space (See Note) 0x07FF 0x07FE 0x0801 0x0800 2560 bytes Near X Data RAM (X) Data 256 bytes Space 512 bytes 0x08FF 0x08FE SRAM Space 0x0901 0x0900 Y Data RAM (Y) 256 bytes 0x09FF 0x0A00 (See Note) 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE Note: Unimplemented SFR or SRAM locations read as ‘0’. DS70118J-page 24 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS SFR Space SFR Space e c Unused a p S X (Y Space) Y Space Unused e c a p S X e Unused c a p S X Non-MAC Class Ops (Read/Write) MAC Class Ops Read-Only MAC Class Ops (Write) Indirect EA using any W Indirect EA using W8, W9 Indirect EA using W10, W11 © 2011 Microchip Technology Inc. DS70118J-page 25

dsPIC30F2010 3.2.2 DATA SPACES 3.2.3 DATA SPACE WIDTH The X data space is used by all instructions and sup- The core data width is 16 bits. All internal registers are ports all addressing modes. There are separate read organized as 16-bit wide words. Data space memory is and write data buses. The X read data bus is the return organized in byte addressable, 16-bit wide blocks. data path for all instructions that view data space as combined X and Y address space. It is also the X 3.2.4 DATA ALIGNMENT address space data path for the dual operand read To help maintain backward compatibility with PIC® instructions (MAC class). The X write data bus is the MCU devices and improve data space memory usage only write path to data space for all instructions. efficiency, the dsPIC30F instruction set supports both The X data space also supports Modulo Addressing for word and byte operations. Data is aligned in data mem- all instructions, subject to addressing mode restric- ory and registers as words, but all data space EAs tions. Bit-Reversed addressing is only supported for resolve to bytes. Data byte reads will read the complete writes to X data space. word, which contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is The Y data space is used in concert with the X data placed onto the LSB of the X data path (no byte space by the MAC class of instructions (CLR, ED, EDAC, accesses are possible from the Y data path as the MAC MAC, MOVSAC, MPY, MPY.N and MSC) to provide two class of instruction can only fetch words). That is, data concurrent data read paths. No writes occur across the memory and registers are organized as two parallel Y bus. This class of instructions dedicates two W reg- byte wide entities with shared (word) address decode, ister pointers, W10 and W11, to always address Y data but separate write lines. Data byte writes only write to space, independent of X data space, whereas W8 and the corresponding side of the array or register which W9 always address X data space. Note that during matches the byte address. accumulator write-back, the data address space is con- sidered a combination of X and Y data spaces, so the As a consequence of this byte accessibility, all effec- write occurs across the X bus. Consequently, the write tive address calculations (including those generated can be to any address in the entire data space. by the DSP operations, which are restricted to word- sized data) are internally scaled to step through The Y data space can only be used for the data word-aligned memory. For example, the core would prefetch operation associated with the MAC class of recognize that Post-Modified Register Indirect instructions. It also supports Modulo Addressing for Addressing mode, [Ws ++], will result in a value of automated circular buffers. Of course, all other instruc- Ws + 1 for byte operations and Ws + 2 for word tions can access the Y data address space through the operations. X data path, as part of the composite linear space. All word accesses must be aligned to an even address. The boundary between the X and Y data spaces is Misaligned word data fetches are not supported, so defined as shown in Figure3-6 and is not user pro- care must be taken when mixing byte and word opera- grammable. Should an EA point to data outside its own tions, or translating from 8-bit MCU code. Should a mis- assigned address space, or to a location outside phys- aligned read or write be attempted, an address error ical memory, an all-zero word/byte will be returned. For trap will be generated. If the error occurred on a read, example, although Y address space is visible by all the instruction underway is completed, whereas if it non-MAC instructions using any Addressing mode, an occurred on a write, the instruction will be executed but attempt by a MAC instruction to fetch data from that the write will not occur. In either case, a trap will then space, using W8 or W9 (X space pointers), will return be executed, allowing the system and/or user to exam- 0x0000. ine the machine state prior to execution of the address fault. TABLE 3-2: EFFECT OF INVALID MEMORY ACCESSES FIGURE 3-8: DATA ALIGNMENT Attempted Operation Data Returned MSB LSB 15 8 7 0 EA = an unimplemented address 0x0000 0001 Byte 1 Byte 0 0000 W8 or W9 used to access Y data 0x0000 space in a MAC instruction 0003 Byte 3 Byte 2 0002 W10 or W11 used to access X 0x0000 data space in a MAC instruction 0005 Byte 5 Byte 4 0004 All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes or 32K words. DS70118J-page 26 © 2011 Microchip Technology Inc.

dsPIC30F2010 All byte loads into any W register are loaded into the There is a Stack Pointer Limit register (SPLIM) associ- LSB. The MSB is not modified. ated with the Stack Pointer. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> A sign-extend (SE) instruction is provided to allow is forced to ‘0’, because all stack operations must be users to translate 8-bit signed data to 16-bit signed word-aligned. Whenever an EA is generated using values. Alternatively, for 16-bit unsigned data, users W15 as a source or destination pointer, the address can clear the MSB of any W register by executing a thus generated is compared with the value in SPLIM. If zero-extend (ZE) instruction on the appropriate the contents of the Stack Pointer (W15) and the SPLIM address. register are equal and a push operation is performed, a Although most instructions are capable of operating on stack error trap will not occur. The stack error trap will word or byte data sizes, it should be noted that some occur on a subsequent push operation. Thus, for exam- instructions, including the DSP instructions, operate ple, if it is desirable to cause a stack error trap when the only on words. stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value, 0x1FFE. 3.2.5 NEAR DATA SPACE Similarly, a stack pointer underflow (stack error) trap is An 8 Kbyte ‘near’ data space is reserved in X address generated when the Stack Pointer address is found to memory space between 0x0000 and 0x1FFF, which is be less than 0x0800, thus preventing the stack from directly addressable via a 13-bit absolute address field interfering with the Special Function Register (SFR) within all memory direct instructions. The remaining X space. address space and all of the Y address space is addressable indirectly. Additionally, the whole of X data A write to the SPLIM register should not be immediately space is addressable using MOV instructions, which followed by an indirect read operation using W15. support memory direct addressing with a 16-bit address field. FIGURE 3-9: CALL STACK FRAME 3.2.6 SOFTWARE STACK 0x0000 15 0 The dsPIC DSC device contains a software stack. W15 is used as the Stack Pointer. s d The Stack Pointer always points to the first available waress free word, and grows from lower addresses towards Todr higher addresses. It pre-decrements for stack pops, ows er Ad PC<15:0> W15 (before CALL) and post-increments for stack pushes, as shown in Grgh 000000000 PC<22:16> Figure3-9. Note that for a PC push during any CALL ck Hi <Free Word> W15 (after CALL) a instruction, the MSB of the PC is zero-extended before St the push, ensuring that the MSB is always clear. POP: [--W15] PUSH: [W15++] Note: A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2011 Microchip Technology Inc. DS70118J-page 27

D d S TABLE 3-3: CORE REGISTER MAP 70 s 1 Address 1 SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State P 8 (Home) J -pag W0 0000 W0 / WREG 0000 0000 0000 0000 IC e W1 0002 W1 0000 0000 0000 0000 28 W2 0004 W2 0000 0000 0000 0000 3 0 W3 0006 W3 0000 0000 0000 0000 W4 0008 W4 0000 0000 0000 0000 F W5 000A W5 0000 0000 0000 0000 2 W6 000C W6 0000 0000 0000 0000 0 W7 000E W7 0000 0000 0000 0000 1 W8 0010 W8 0000 0000 0000 0000 0 W9 0012 W9 0000 0000 0000 0000 W10 0014 W10 0000 0000 0000 0000 W11 0016 W11 0000 0000 0000 0000 W12 0018 W12 0000 0000 0000 0000 W13 001A W13 0000 0000 0000 0000 W14 001C W14 0000 0000 0000 0000 W15 001E W15 0000 1000 0000 0000 SPLIM 0020 SPLIM 0000 0000 0000 0000 ACCAL 0022 ACCAL 0000 0000 0000 0000 ACCAH 0024 ACCAH 0000 0000 0000 0000 ACCAU 0026 Sign Extension (ACCA<39>) ACCAU 0000 0000 0000 0000 ACCBL 0028 ACCBL 0000 0000 0000 0000 ACCBH 002A ACCBH 0000 0000 0000 0000 ACCBU 002C Sign Extension (ACCB<39>) ACCBU 0000 0000 0000 0000 PCL 002E PCL 0000 0000 0000 0000 PCH 0030 — — — — — — — — — PCH 0000 0000 0000 0000 TBLPAG 0032 — — — — — — — — TBLPAG 0000 0000 0000 0000 © 2 PSVPAG 0034 — — — — — — — — PSVPAG 0000 0000 0000 0000 0 1 RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu 1 M DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu ic ro DOSTARTL 003A DOSTARTL 0 uuuu uuuu uuuu uuu0 c h DOSTARTH 003C — — — — — — — — — DOSTARTH 0000 0000 0uuu uuuu ip T DOENDL 003E DOENDL 0 uuuu uuuu uuuu uuu0 e ch DOENDH 0040 — — — — — — — — — DOENDH 0000 0000 0uuu uuuu n olo SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000 gy Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ In Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. c .

© TABLE 3-3: CORE REGISTER MAP (CONTINUED) 2 0 Address 11 SFR Name (Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State M ic CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000 ro MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000 c h ip XMODSRT 0048 XS<15:1> 0 uuuu uuuu uuuu uuu0 T e XMODEND 004A XE<15:1> 1 uuuu uuuu uuuu uuu1 c hn YMODSRT 004C YS<15:1> 0 uuuu uuuu uuuu uuu0 o lo YMODEND 004E YE<15:1> 1 uuuu uuuu uuuu uuu1 g y In XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu c. DISICNT 0052 — — DISICNT<13:0> 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. d s P I C 3 0 D S F 7 0 1 2 1 8 J 0 -p a 1 g e 2 0 9

dsPIC30F2010 NOTES: DS70118J-page 30 © 2011 Microchip Technology Inc.

dsPIC30F2010 4.0 ADDRESS GENERATOR UNITS 4.1 Instruction Addressing Modes Note: This data sheet summarizes features of The Addressing modes in Table4-1 form the basis of this group ofdsPIC30F devices and is not the Addressing modes optimized to support the specific intended to be a complete reference features of individual instructions. The Addressing source. For more information on the CPU, modes provided in the MAC class of instructions are peripherals, register descriptions and somewhat different from those in the other instruction general device functionality, refer to the types. “dsPIC30F Family Reference Manual” 4.1.1 FILE REGISTER INSTRUCTIONS (DS70046). For more information on the device instruction set and programming, Most file register instructions use a 13-bit address field refer to the “16-bit MCU and DSC Pro- (f) to directly address data present in the first 8192 grammer’s Reference Manual” bytes of data memory (near data space). Most file (DS70157). register instructions employ a working register W0, which is denoted as WREG in these instructions. The The dsPIC DSC core contains two independent destination is typically either the same file register, or address generator units: the X AGU and Y AGU. The Y WREG (with the exception of the MUL instruction), AGU supports word-sized data reads for the DSP MAC which writes the result to a register or register pair. The class of instructions only. The dsPIC DSC AGUs MOV instruction allows additional flexibility and can support three types of data addressing: access the entire data space. • Linear Addressing • Modulo (Circular) Addressing • Bit-Reversed Addressing Linear and Modulo Data Addressing modes can be applied to data space or program space. Bit-Reversed Addressing is only applicable to data space addresses. TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. © 2011 Microchip Technology Inc. DS70118J-page 31

dsPIC30F2010 4.1.2 MCU INSTRUCTIONS 4.1.4 MAC INSTRUCTIONS The three-operand MCU instructions are of the form: The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also Operand 3 = Operand 1 <function> Operand 2 referred to as MAC instructions, utilize a simplified set of where Operand 1 is always a working register (i.e., the Addressing modes to allow the user to effectively Addressing mode can only be register direct), which is manipulate the data pointers through register indirect referred to as Wb. Operand 2 can be a W register, tables. fetched from data memory, or 5-bit literal. The result The two source operand prefetch registers must be a location can be either a W register or an address member of the set {W8, W9, W10, W11}. For data location. The following Addressing modes are reads, W8 and W9 will always be directed to the X supported by MCU instructions: RAGU and W10 and W11 will always be directed to the • Register Direct Y AGU. The effective addresses generated (before and • Register Indirect after modification) must, therefore, be valid addresses • Register Indirect Post-modified within X data space for W8 and W9 and Y data space • Register Indirect Pre-modified for W10 and W11. • 5-bit or 10-bit Literal Note: Register Indirect with Register Offset Addressing is only available for W9 (in X Note: Not all instructions support all the space) and W11 (in Y space). Addressing modes given above. Individ- ual instructions may support different In summary, the following Addressing modes are subsets of these Addressing modes. supported by the MAC class of instructions: • Register Indirect 4.1.3 MOVE AND ACCUMULATOR INSTRUCTIONS • Register Indirect Post-modified by 2 • Register Indirect Post-modified by 4 Move instructions and the DSP Accumulator class of • Register Indirect Post-modified by 6 instructions provide a greater degree of addressing flexibility than other instructions. In addition to the • Register Indirect with Register Offset (Indexed) Addressing modes supported by most MCU instruc- 4.1.5 OTHER INSTRUCTIONS tions, Move and Accumulator instructions also support Register Indirect with Register Offset Addressing Besides the various Addressing modes outlined above, mode, also referred to as Register Indexed mode. some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit Note: For the MOV instructions, the Addressing signed literals to specify the branch destination directly, mode specified in the instruction can differ whereas the DISI instruction uses a 14-bit unsigned for the source and destination EA. How- literal field. In some instructions, such as ADD Acc, the ever, the 4-bit Wb (Register Offset) field is source of an operand or result is implied by the opcode shared between both source and itself. Certain operations, such as NOP, do not have any destination (but typically only used by operands. one). In summary, the following Addressing modes are supported by Move and Accumulator instructions: • Register Direct • Register Indirect • Register Indirect Post-modified • Register Indirect Pre-modified • Register Indirect with Register Offset (Indexed) • Register Indirect with Literal Offset • 8-bit Literal • 16-bit Literal Note: Not all instructions support all the Addressing modes given above. Individ- ual instructions may support different subsets of these Addressing modes. DS70118J-page 32 © 2011 Microchip Technology Inc.

dsPIC30F2010 4.2 Modulo Addressing 4.2.1 START AND END ADDRESS Modulo addressing is a method of providing an auto- The Modulo Addressing scheme requires that a mated means to support circular data buffers using startingand an end address be specified and loaded hardware. The objective is to remove the need for soft- into the 16-bit modulo buffer address registers: ware to perform data address boundary checks when XMODSRT,XMODEND, YMODSRT and YMODEND executing tightly looped code, as is typical in many (see Table3-3). DSP algorithms. Note: Y space Modulo Addressing EA calcula- Modulo addressing can operate in either data or tions assume word-sized data (LSb of program space (since the data pointer mechanism is every EA is always clear). essentially the same for both). One circular buffer can The length of a circular buffer is not directly specified. It be supported in each of the X (which also provides the is determined by the difference between the corre- pointers into Program space) and Y data spaces. sponding start and end addresses. The maximum Modulo addressing can operate on any W register possible length of the circular buffer is 32K words pointer. However, it is not advisable to use W14 or W15 (64Kbytes). for Modulo Addressing, since these two registers are used as the Stack Frame Pointer and Stack Pointer, 4.2.2 W ADDRESS REGISTER respectively. SELECTION In general, any particular circular buffer can only be The Modulo and Bit-Reversed Addressing Control reg- configured to operate in one direction, as there are ister MODCON<15:0> contains enable flags as well as certain restrictions on the buffer start address (for a W register field to specify the W address registers. incrementing buffers) or end address (for decrementing The XWM and YWM fields select which registers will buffers) based upon the direction of the buffer. operate with Modulo Addressing. If XWM = 15, X The only exception to the usage restrictions is for RAGU and X WAGU Modulo Addressing are disabled. buffers which have a power-of-2 length. As these Similarly, if YWM = 15, Y AGU Modulo Addressing is buffers satisfy the start and end address criteria, they disabled. may operate in a Bidirectional mode, (i.e., address The X Address Space Pointer W register (XWM) to boundary checks will be performed on both the lower which Modulo Addressing is to be applied, is stored in and upper address boundaries). MODCON<3:0> (see Table3-3). Modulo addressing is enabled for X data space when XWM is set to any value other than 15 and the XMODEN bit is set at MODCON<15>. The Y Address Space Pointer W register (YWM) to which Modulo Addressing is to be applied, is stored in MODCON<7:4>. Modulo addressing is enabled for Y data space when YWM is set to any value other than 15 and the YMODEN bit is set at MODCON<14>. © 2011 Microchip Technology Inc. DS70118J-page 33

dsPIC30F2010 FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE Byte Address MOV #0x1100,W0 MOV W0, XMODSRT ;set modulo start address MOV #0x1163,W0 MOV W0,MODEND ;set modulo end address 0x1100 MOV #0x8001,W0 MOV W0,MODCON ;enable W1, X AGU for modulo MOV #0x0000,W0 ;W0 holds buffer fill value MOV #0x1110,W1 ;point W1 to buffer DO AGAIN,#0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0,W0 ;increment the fill value 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words DS70118J-page 34 © 2011 Microchip Technology Inc.

dsPIC30F2010 4.2.3 MODULO ADDRESSING If the length of a bit-reversed buffer is M = 2N bytes, APPLICABILITY then the last ‘N’ bits of the data buffer start address must be zeros. Modulo addressing can be applied to the effective address calculation associated with any W register. It is XB<14:0> is the bit-reversed address modifier or ‘pivot important to realize that the address boundaries check point’ which is typically a constant. In the case of an for addresses less than or greater than the upper (for FFT computation, its value is equal to half of the FFT incrementing buffers) and lower (for decrementing buf- data buffer size. fers) boundary addresses (not just equal to). Address Note: All Bit-Reversed EA calculations assume changes may, therefore, jump beyond boundaries and word-sized data (LSb of every EA is still be adjusted correctly. always clear). The XB value is scaled Note: The modulo corrected effective address is accordingly to generate compatible (byte) written back to the register only when Pre- addresses. Modify or Post-Modify Addressing mode is When enabled, Bit-Reversed Addressing will only be used to compute the effective address. executed for register indirect with pre-increment or When an address offset (e.g., [W7 + W2]) post-increment addressing and word-sized data writes. is used, modulo address correction is per- It will not function for any other addressing mode or for formed, but the contents of the register byte-sized data, and normal addresses will be gener- remains unchanged. ated instead. When Bit-Reversed Addressing is active, the W Address Pointer will always be added to the 4.3 Bit-Reversed Addressing address modifier (XB) and the offset associated with the register Indirect Addressing mode will be ignored. Bit-Reversed Addressing is intended to simplify data In addition, as word-sized data is a requirement, the reordering for radix-2 FFT algorithms. It is supported by LSb of the EA is ignored (and always clear). the X AGU for data writes only. Note: Modulo addressing and Bit-Reversed The modifier, which may be a constant value or register Addressing should not be enabled contents, is regarded as having its bit order reversed. together. In the event that the user The address source and destination are kept in normal attempts to do this, bit reversed address- order. Thus, the only operand requiring reversal is the ing will assume priority when active for the modifier. X WAGU, and X WAGU Modulo Address- 4.3.1 BIT-REVERSED ADDRESSING ing will be disabled. However, Modulo Addressing will continue to function in the IMPLEMENTATION X RAGU. Bit-Reversed Addressing is enabled when: If Bit-Reversed Addressing has already been enabled 1. BWM (W register selection) in the MODCON by setting the BREN (XBREV<15>) bit, then a write to register is any value other than 15 (the stack can the XBREV register should not be immediately followed not be accessed using Bit-Reversed by an indirect read operation using the W register that Addressing) and has been designated as the bit-reversed pointer. 2. the BREN bit is set in the XBREV register and 3. the Addressing mode used is Register Indirect with Pre-Increment or Post-Increment. FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer © 2011 Microchip Technology Inc. DS70118J-page 35

dsPIC30F2010 TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Bit-Reversed Address Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value(1) 32768 0x4000 16384 0x2000 8192 0x1000 4096 0x0800 2048 0x0400 1024 0x0200 512 0x0100 256 0x0080 128 0x0040 64 0x0020 32 0x0010 16 0x0008 8 0x0004 4 0x0002 2 0x0001 Note 1: Modifier values greater than 256 words exceed the data memory available on the dsPIC30F2010 device. DS70118J-page 36 © 2011 Microchip Technology Inc.

dsPIC30F2010 5.0 INTERRUPTS Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of Note: This data sheet summarizes features of its corresponding enable bit. User soft- this group ofdsPIC30F devices and is not ware should ensure the appropriate inter- intended to be a complete reference rupt flag bits are clear prior to enabling an source. For more information on the CPU, peripherals, register descriptions and interrupt. general device functionality, refer to the All interrupt sources can be user-assigned to one of “dsPIC30F Family Reference Manual” seven priority levels, 1 through 7, via the IPCx (DS70046). For more information on the registers. Each interrupt source is associated with an device instruction set and programming, interrupt vector, as shown in Figure5-1. Levels 7 and refer to the “16-bit MCU and DSC Pro- 1 represent the highest and lowest maskable priorities, grammer’s Reference Manual” respectively. (DS70157). Note: Assigning a priority level of 0 to an inter- The dsPIC30F2010 has 24 interrupt sources and four rupt source is equivalent to disabling that processor exceptions (traps), which must be arbitrated interrupt. based on a priority scheme. If the NSTDIS bit (INTCON1<15>) is set, nesting of The CPU is responsible for reading the Interrupt Vec- interrupts is prevented. Thus, if an interrupt is currently tor Table (IVT) and transferring the address contained being serviced, processing of a new interrupt is in the interrupt vector to the program counter. The prevented, even if the new interrupt is of higher priority interrupt vector is transferred from the program data than the one currently being serviced. bus into the program counter, via a 24-bit wide multiplexer on the input of the program counter. Note: The IPL bits become read-only whenever The Interrupt Vector Table (IVT) and Alternate Inter- the NSTDIS bit has been set to ‘1’. rupt Vector Table (AIVT) are placed near the beginning Certain interrupts have specialized control bits for of program memory (0x000004). The IVT and AIVT features like edge or level triggered interrupts, inter- are shown in Figure5-1. rupt-on-change, etc. Control of these features remains The interrupt controller is responsible for pre- within the peripheral module which generates the processing the interrupts and processor exceptions, interrupt. prior to their being presented to the processor core. The DISI instruction can be used to disable the The peripheral interrupts and traps are enabled, priori- processing of interrupts of priorities 6 and lower for a tized and controlled using centralized special function certain number of instructions, during which the DISI bit registers: (INTCON2<14>) remains set. • IFS0<15:0>, IFS1<15:0>, IFS2<15:0> When an interrupt is serviced, the PC is loaded with the All interrupt request flags are maintained in these address stored in the vector location in Program Mem- three registers. The flags are set by their respective ory that corresponds to the interrupt. There are 63 dif- peripherals or external signals, and they are cleared via software. ferent vectors within the IVT (refer to Figure5-1). These vectors are contained in locations 0x000004 through • IEC0<15:0>, IEC1<15:0>, IEC2<15:0> 0x0000FE of program memory (refer to Figure5-1). All interrupt enable control bits are maintained in These locations contain 24-bit addresses, and in order these three registers. These control bits are used to to preserve robustness, an address error trap will take individually enable interrupts from the peripherals or place should the PC attempt to fetch any of these external signals. words during normal execution. This prevents execu- • IPC0<15:0>... IPC11<7:0> tion of random data as a result of accidentally decre- The user-assignable priority level associated with menting a PC into vector space, accidentally mapping each of these interrupts is held centrally in these a data space address into vector space or the PC roll- twelve registers. ing over to 0x000000 after reaching the end of imple- • IPL<3:0> The current CPU priority level is explicitly mented program memory space. Execution of a GOTO stored in the IPL bits. IPL<3> is present in the instruction to this vector space will also generate an CORCON register, whereas IPL<2:0> are present in address error trap. the STATUS Register (SR) in the processor core. • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers. INTCON1 contains the control and status flags for the processor exceptions. The INTCON2 register controls the external interrupt request signal behavior and the use of the alternate vector table. © 2011 Microchip Technology Inc. DS70118J-page 37

dsPIC30F2010 5.1 Interrupt Priority TABLE 5-1: dsPIC30F2010 INTERRUPT VECTOR TABLE The user-assignable Interrupt Priority (IP<2:0>) bits for each individual interrupt source are located in the Least INT Vector Interrupt Source Significant 3 bits of each nibble, within the IPCx regis- Number Number ter(s). Bit 3 of each nibble is not used and is read as a Highest Natural Order Priority ‘0’. These bits define the priority level assigned to a 0 8 INT0 – External Interrupt 0 particular interrupt by the user. 1 9 IC1 – Input Capture 1 Note: The user-assigned priority levels are from 2 10 OC1 – Output Compare 1 0, as the lowest priority, to level 7, as the 3 11 T1 – Timer1 highest priority. 4 12 IC2 – Input Capture 2 Since more than one interrupt request source may be 5 13 OC2 – Output Compare 2 assigned to a specific user-assigned priority level, a 6 14 T2 – Timer2 means is provided to assign priority within a given level. 7 15 T3 – Timer3 This method is called “Natural Order Priority” and is 8 16 SPI1 final. 9 17 U1RX – UART1 Receiver Natural Order Priority is determined by the position of 10 18 U1TX – UART1 Transmitter an interrupt in the vector table, and only affects 11 19 ADC – ADC Convert Done interrupt operation when multiple interrupts with the 12 20 NVM – NVM Write Complete same user-assigned priority become pending at the 13 21 SI2C – I2C™ Slave Interrupt same time. 14 22 MI2C – I2C Master Interrupt Table5-1 lists the interrupt numbers and interrupt 15 23 Input Change Interrupt sources for the dsPIC DSC devices and their 16 24 INT1 – External Interrupt 1 associated vector numbers. 17 25 IC7 – Input Capture 7 Note1: The natural order priority scheme has 0 18 26 IC8 – Input Capture 8 as the highest priority and 53 as the 19 27 Reserved lowest priority. 20 28 Reserved 2: The natural order priority number is the 21 29 Reserved same as the INT number. 22 30 Reserved The ability for the user to assign every interrupt to one 23 31 INT2 - External Interrupt 2 of seven priority levels means that the user can assign 24 32 Reserved a very high overall priority level to an interrupt with a 25 33 Reserved low natural order priority. For example, the PLVD (Low- 26 34 Reserved Voltage Detect) can be given a priority of 7. The INT0 (external interrupt 0) may be assigned to priority 27 35 Reserved level1, thus giving it a very low effective priority. 28 36 Reserved 29 37 Reserved 30 38 Reserved 31 39 Reserved 32 40 Reserved 33 41 Reserved 34 42 Reserved 35 43 Reserved 36 44 INT3 – External Interrupt 3 37 45 Reserved 38 46 Reserved 39 47 PWM – PWM Period Match 40 48 QEI – QEI Interrupt 41 49 Reserved 42 50 Reserved 43 51 FLTA – PWM Fault A 44 52 Reserved 45-53 53-61 Reserved Lowest Natural Order Priority DS70118J-page 38 © 2011 Microchip Technology Inc.

dsPIC30F2010 5.2 Reset Sequence 5.3 Traps A Reset is not a true exception, because the interrupt Traps can be considered as non-maskable interrupts controller is not involved in the Reset process. The pro- indicating a software or hardware error, which adhere cessor initializes its registers in response to a Reset, to a predefined priority as shown in Figure5-1. They which forces the PC to zero. The processor then begins are intended to provide the user a means to correct program execution at location 0x000000. A GOTO erroneous operation during debug and when operating instruction is stored in the first program memory loca- within the application. tion, immediately followed by the address target for the Note: If the user does not intend to take correc- GOTO instruction. The processor executes the GOTO to tive action in the event of a trap error con- the specified address and then begins operation at the dition, these vectors must be loaded with specified target (start) address. the address of a default handler that sim- 5.2.1 RESET SOURCES ply contains the RESET instruction. If, on the other hand, one of the vectors contain- In addition to External Reset and Power-on Reset ing an invalid address is called, an (POR), there are 6 sources of error conditions which address error trap is generated. ‘trap’ to the Reset vector. Note that many of these trap conditions can only be • Watchdog Time-out: detected when they occur. Consequently, the question- The watchdog has timed out, indicating that the able instruction is allowed to complete prior to trap processor is no longer executing the correct flow exception processing. If the user chooses to recover of code. from the error, the result of the erroneous action that • Uninitialized W Register Trap: caused the trap may have to be corrected. An attempt to use an uninitialized W register as There are 8 fixed priority levels for traps: Level 8 an Address Pointer will cause a Reset. through Level 15, which means that the IPL3 is always • Illegal Instruction Trap: set during processing of a trap. Attempted execution of any unused opcodes will result in an illegal instruction trap. Note that a If the user is not currently executing a trap, and he sets fetch of an illegal instruction does not result in an the IPL<3:0> bits to a value of ‘0111’ (Level 7), then all illegal instruction trap if that instruction is flushed interrupts are disabled, but traps can still be processed. prior to execution due to a flow change. 5.3.1 TRAP SOURCES • Brown-out Reset (BOR): A momentary dip in the power supply to the The following traps are provided with increasing prior- device has been detected, which may result in ity. However, since all traps can be nested, priority has malfunction. little effect. • Trap Lockout: Math Error Trap: Occurrence of multiple trap conditions simultaneously will cause a Reset. The math error trap executes under the following four circumstances: 1. Should an attempt be made to divide by zero, the divide operation will be aborted on a cycle boundary and the trap taken. 2. If enabled, a math error trap will be taken when an arithmetic operation on either accumulator A or B causes an overflow from bit 31 and the accumulator guard bits are not utilized. 3. If enabled, a math error trap will be taken when an arithmetic operation on either accumulator A or B causes a catastrophic overflow from bit 39 and all saturation is disabled. 4. If the shift amount specified in a shift instruction is greater than the maximum allowed shift amount, a trap will occur. © 2011 Microchip Technology Inc. DS70118J-page 39

dsPIC30F2010 Address Error Trap: 5.3.2 HARD AND SOFT TRAPS This trap is initiated when any of the following It is possible that multiple traps can become active circumstances occurs: within the same cycle (e.g., a misaligned word stack write to an overflowed address). In such a case, the 1. A misaligned data word access is attempted. fixed priority shown in Figure5-1 is implemented, 2. A data fetch from an unimplemented data which may require the user to check if other traps are memory location is attempted. pending, in order to completely correct the fault. 3. A data access of an unimplemented program ‘Soft’ traps include exceptions of priority level 8 through memory location is attempted. level 11, inclusive. The arithmetic error trap (level 11) 4. An instruction fetch from vector space is falls into this category of traps. attempted. ‘Hard’ traps include exceptions of priority level 12 Note: In the MAC class of instructions, wherein through level 15, inclusive. The address error (level the data space is split into X and Y data 12), stack error (level 13) and oscillator error (level 14) space, unimplemented X space includes traps fall into this category. all of Y space, and unimplemented Y space includes all of X space. Each hard trap that occurs must be acknowledged before code execution of any type may continue. If a 5. Execution of a “BRA #literal” instruction or a lower priority hard trap occurs while a higher priority “GOTO #literal” instruction, where literal trap is pending, acknowledged, or is being processed, is an unimplemented program memory address. a hard trap conflict will occur. 6. Executing instructions after modifying the PC to The device is automatically Reset in a hard trap conflict point to unimplemented program memory condition. The TRAPR status bit (RCON<15>) is set addresses. The PC may be modified by loading when the Reset occurs, so that the condition may be a value into the stack and executing a RETURN detected in software. instruction. Stack Error Trap: FIGURE 5-1: TRAP VECTORS This trap is initiated under the following conditions: Reset - GOTO Instruction 0x000000 1. The Stack Pointer is loaded with a value which Reset - GOTO Address 0x000002 is greater than the (user programmable) limit Reserved 0x000004 Oscillator Fail Trap Vector value written into the SPLIM register (stack Address Error Trap Vector overflow). g Stack Error Trap Vector 2. iTsh lee sSst athcakn P 0oxin0t8e0r 0is ( sloimapdleed s wtaicthk au nvdaelurfelo wwh).ich ecreasinPriority IVT MaRRRtheee Essseeerrrrrovvvreee Tdddr aVVVpeee cccVtttoooerrrctor D Interrupt 0 Vector 0x000014 Oscillator Fail Trap: Interrupt 1 Vector — This trap is initiated if the external oscillator fails and — — operation becomes reliant on an internal RC backup. Interrupt 52 Vector Interrupt 53 Vector 0x00007E Reserved 0x000080 Reserved 0x000082 Reserved 0x000084 Oscillator Fail Trap Vector Stack Error Trap Vector Address Error Trap Vector Math Error Trap Vector AIVT Reserved Vector Reserved Vector Reserved Vector Interrupt 0 Vector 0x000094 Interrupt 1 Vector — — — Interrupt 52 Vector Interrupt 53 Vector 0x0000FE DS70118J-page 40 © 2011 Microchip Technology Inc.

dsPIC30F2010 5.4 Interrupt Sequence 5.5 Alternate Vector Table All interrupt event flags are sampled in the beginning of In Program Memory, the Interrupt Vector Table (IVT) is each instruction cycle by the IFSx registers. A pending followed by the Alternate Interrupt Vector Table (AIVT), interrupt request (IRQ) is indicated by the flag bit being as shown in Figure5-1. Access to the Alternate Vector equal to a ‘1’ in an IFSx register. The IRQ will cause an Table is provided by the ALTIVT bit in the INTCON2 interrupt to occur if the corresponding bit in the interrupt register. If the ALTIVT bit is set, all interrupt and excep- enable (IECx) register is set. For the remainder of the tion processes will use the alternate vectors instead of instruction cycle, the priorities of all pending interrupt the default vectors. The alternate vectors are organized requests are evaluated. in the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing If there is a pending IRQ with a priority level greater a means to switch between an application and a sup- than the current processor priority level in the IPL bits, port environment, without requiring the interrupt vec- the processor will be interrupted. tors to be reprogrammed. This feature also enables The processor then stacks the current program counter switching between applications for evaluation of and the low byte of the processor STATUS register different software algorithms at run time. (SRL), as shown in Figure5-2. The low byte of the If the AIVT is not required, the program memory allo- status register contains the processor priority level at cated to the AIVT may be used for other purposes. the time, prior to the beginning of the interrupt cycle. AIVT is not a protected section and may be freely The processor then loads the priority level for this programmed by the user. interrupt into the STATUS register. This action will disable all lower priority interrupts until the completion 5.6 Fast Context Saving of the Interrupt Service Routine (ISR). A context saving option is available using shadow reg- FIGURE 5-2: INTERRUPT STACK isters. Shadow registers are provided for the DC, N, FRAME OV, Z and C bits in SR, and the registers W0 through W3. The shadows are only one level deep. The shadow 0x0000 15 0 registers are accessible using the PUSH.S and POP.S instructions only. s ards When the processor vectors to an interrupt, the ws PUSH.S instruction can be used to store the current oe s Tddr value of the aforementioned registers into their Growher A S R L IPPCL3< 1 P5:C0<>22:16> W15 (before CALL) rIfe sapne cIStivRe osfh aad ocewr traeing isptreiorsr.it y uses the PUSH.S and ck Hig <Free Word> W15 (after CALL) POP.S instructions for fast context saving, then a a St higher priority ISR should not include the same instruc- POP : [--W15] tions. Users must save the key registers in software PUSH : [W15++] during a lower priority interrupt, if the higher priority ISR uses fast context saving. Note1: The user can always lower the priority level by writing a new value into SR. The 5.7 External Interrupt Requests Interrupt Service Routine must clear the The interrupt controller supports five external interrupt interrupt flag bits in the IFSx register request signals, INT0-INT4. These inputs are edge before lowering the processor interrupt sensitive; they require a low-to-high or a high-to-low priority, in order to avoid recursive transition to generate an interrupt request. The interrupts. INTCON2 register has three bits, INT0EP-INT2EP, that 2: The IPL3 bit (CORCON<3>) is always select the polarity of the edge detection circuitry. clear when interrupts are being pro- cessed. It is set only during execution of 5.8 Wake-up from Sleep and Idle traps. The interrupt controller may be used to wake up the The RETFIE (Return from Interrupt) instruction will processor from either Sleep or Idle modes, if Sleep or unstack the program counter and status registers to Idle mode is active when the interrupt is generated. return the processor to its state prior to the interrupt If an enabled interrupt request of sufficient priority is sequence. received by the interrupt controller, then the standard interrupt request is presented to the processor. At the same time, the processor will wake-up from Sleep or Idle and begin execution of the Interrupt Service Routine needed to process the interrupt request. © 2011 Microchip Technology Inc. DS70118J-page 41

D TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP d S 701 NSaFmRe Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 1 P 8 J INTCON1 0080 NSTDIS — — — — OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 0000 0000 0000 -p I ag INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 0000 0000 0000 C e 42 IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000 3 IFS1 0086 — — — — — — — — INT2IF — — — — IC8IF IC7IF INT1IF 0000 0000 0000 0000 0 IFS2 0088 — — — — FLTAIF — — QEIIF PWMIF — — — — — — — 0000 0000 0000 0000 F IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000 2 IEC1 008E — — — — — — — — INT2IE — — — — IC8IE IC7IE INT1IE 0000 0000 0000 0000 0 IEC2 0090 — — — — FLTAIE — — QEIIE PWMIE — — — — — — — 0000 0000 0000 0000 1 IPC0 0094 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100 0 IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100 IPC2 0098 — ADIP<2:0> — U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100 IPC3 009A — CNIP<2:0> — MI2CIP<2:0> — SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100 IPC4 009C — — — — — IC8IP<2:0> — IC7IP<2:0> — INT1IP<2:0> 0100 0100 0100 0100 IPC5 009E — INT2IP<2:0> — — — — — — — — — — — — 0100 0000 0000 0000 IPC6 00A0 — — — — — — — — — — — — — — — — 0000 0000 0000 0000 IPC7 00A2 — — — — — — — — — — — — — — — — 0000 0000 0000 0000 IPC8 00A4 — — — — — — — — — — — — — — — — 0000 0000 0000 0000 IPC9 00A6 — PWMIP<2:0> — — — — — — — — — — — — 0000 0000 0000 0000 IPC10 00A8 — FLTAIP<2:0> — — — — — — — — — QEIIP<2:0> 0100 0000 0000 0100 IPC11 00AA — — — — — — — — — — — — — — — — 0000 0000 0000 0000 Legend: — = unimplemented bit, read as ‘0’ Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F2010 6.0 FLASH PROGRAM MEMORY Master Clear (MCLR). This allows customers to manu- facture boards with unprogrammed devices, and then Note: This data sheet summarizes features of program the digital signal controller just before shipping this group ofdsPIC30F devices and is not the product. This also allows the most recent firmware intended to be a complete reference or a custom firmware to be programmed. source. For more information on the CPU, peripherals, register descriptions and 6.2 Run-Time Self-Programming general device functionality, refer to the (RTSP) “dsPIC30F Family Reference Manual” (DS70046). For more information on the RTSP is accomplished using TBLRD (table read) and device instruction set and programming, TBLWT (table write) instructions. refer to the “16-bit MCU and DSC Pro- With RTSP, the user may erase program memory, 32 grammer’s Reference Manual” instructions (96 bytes) at a time and can write program (DS70157). memory data, 32 instructions (96 bytes) at a time. The dsPIC30F family of devices contains internal program Flash memory for executing user code. There 6.3 Table Instruction Operation Summary are two methods by which the user can program this The TBLRDL and the TBLWTL instructions are used to memory: read or write to bits<15:0> of program memory. 1. In-Circuit Serial Programming (ICSP™) TBLRDL and TBLWTL can access program memory in programming capability Word or Byte mode. 2. Run-Time Self-Programming (RTSP) The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH 6.1 In-Circuit Serial Programming and TBLWTH can access program memory in Word or (ICSP) Byte mode. A 24-bit program memory address is formed using dsPIC30F devices can be serially programmed while in bits<7:0> of the TBLPAG register and the EA from a W the end application circuit. This is simply done with two register specified in the table instruction, as shown in lines for Programming Clock and Programming Data Figure6-1. (which are named PGC and PGD respectively), and three other lines for Power (VDD), Ground (VSS) and FIGURE 6-1: ADDRESSING FOR TABLE AND NVM REGISTERS 24 bits Using Program 0 Program Counter 0 Counter NVMADR Reg EA Using NVMADR 1/0 NVMADRU Reg Addressing 8 bits 16 bits Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 bits 16 bits User/Configuration Byte Space Select Select 24-bit EA © 2011 Microchip Technology Inc. DS70118J-page 43

dsPIC30F2010 6.4 RTSP Operation 6.5 Control Registers The dsPIC30F Flash program memory is organized The four SFRs used to read and write the program into rows and panels. Each row consists of 32 instruc- Flash memory are: tions, or 96 bytes. Each panel consists of 128 rows, or • NVMCON 4K x 24 instructions. RTSP allows the user to erase one • NVMADR row (32 instructions) at a time and to program 32 instructions at one time. RTSP may be used to program • NVMADRU multiple program memory panels, but the table pointer • NVMKEY must be changed at each panel boundary. 6.5.1 NVMCON REGISTER Each panel of program memory contains write latches that hold 32 instructions of programming data. Prior to The NVMCON register controls which blocks are to be the actual programming operation, the write data must erased, which memory type is to be programmed, and be loaded into the panel write latches. The data to be the start of the programming cycle. programmed into the panel is loaded in sequential 6.5.2 NVMADR REGISTER order into the write latches; instruction 0, instruction 1, etc. The instruction words loaded must always be from The NVMADR register is used to hold the lower two a 32 address boundary. bytes of the effective address. The NVMADR register captures the EA<15:0> of the last table instruction that The basic sequence for RTSP programming is to set up has been executed and selects the row to write. a table pointer, then do a series of TBLWT instructions to load the write latches. Programming is performed by 6.5.3 NVMADRU REGISTER setting the special bits in the NVMCON register. 32 TBLWTL and four TBLWTH instructions are required to The NVMADRU register is used to hold the upper byte load the 32 instructions. If multiple panel programming of the effective address. The NVMADRU register cap- is required, the table pointer needs to be changed and tures the EA<23:16> of the last table instruction that the next set of multiple write latches written. has been executed. All of the table write operations are single word writes 6.5.4 NVMKEY REGISTER (2 instruction cycles), because only the table latches are written. A programming cycle is required for NVMKEY is a write-only register that is used for write programming each row. protection. To start a programming or an erase sequence, the user must consecutively write 0x55 and The Flash program memory is readable, writable and 0xAA to the NVMKEY register. Refer to Section6.6 erasable during normal operation over the entire VDD “Programming Operations” for further details. range. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. DS70118J-page 44 © 2011 Microchip Technology Inc.

dsPIC30F2010 6.6 Programming Operations 4. Write 32 instruction words of data from data RAM “image” into the program Flash write A complete programming sequence is necessary for latches. programming or erasing the internal Flash in RTSP 5. Program 32 instruction words into program mode. A programming operation is nominally 2 ms in Flash. duration and the processor stalls (waits) until the oper- a) Set up NVMCON register for multi-word, ation is finished. Setting the WR bit (NVMCON<15>) program Flash, program and set WREN bit. starts the operation, and the WR bit is automatically cleared when the operation is finished. b) Write 0x55 to NVMKEY. c) Write 0xAA to NVMKEY. 6.6.1 PROGRAMMING ALGORITHM FOR d) Set the WR bit. This will begin program PROGRAM FLASH cycle. The user can erase and program one row of program e) CPU will stall for duration of the program Flash memory at a time. The general process is: cycle. 1. Read one row of program Flash (32 instruction f) The WR bit is cleared by the hardware words) and store into data RAM as a data when program cycle ends. “image”. 6. Repeat steps 1 through 5 as needed to program 2. Update the data image with the desired new desired amount of program Flash memory. data. 6.6.2 ERASING A ROW OF PROGRAM 3. Erase program Flash row. MEMORY a) Set up NVMCON register for multi-word, program Flash, erase and set WREN bit. Example6-1 shows a code sequence that can be used to erase a row (32 instructions) of program memory. b) Write address of row to be erased into NVMADRU/NVMDR. c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. e) Set the WR bit. This will begin erase cycle. f) CPU will stall for the duration of the erase cycle. g) The WR bit is cleared when erase cycle ends. EXAMPLE 6-1: ERASING A ROW OF PROGRAM MEMORY ; Setup NVMCON for erase operation, multi word write ; program memory selected, and writes enabled MOV #0x4041,W0 ; MOV W0 NVMCON ; Init NVMCON SFR , ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR),W0 ; MOV W0 NVMADRU ; Initialize PM Page Boundary SFR , MOV #tbloffset(PROG_ADDR),W0 ; Initialize in-page EA[15:0] pointer MOV W0, NVMADR ; Initialize NVMADR SFR DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55,W0 MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted © 2011 Microchip Technology Inc. DS70118J-page 45

dsPIC30F2010 6.6.3 LOADING WRITE LATCHES Example6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000,W0 ; MOV W0 TBLPAG ; Initialize PM Page Boundary SFR , MOV #0x6000,W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0,W2 ; MOV #HIGH_BYTE_0,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , ; 1st_program_word MOV #LOW_WORD_1,W2 ; MOV #HIGH_BYTE_1,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , ; 2nd_program_word MOV #LOW_WORD_2,W2 ; MOV #HIGH_BYTE_2,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , • • • ; 31st_program_word MOV #LOW_WORD_31,W2 ; MOV #HIGH_BYTE_31,W3 ; TBLWTL W2 [W0] ; Write PM low word into program latch , TBLWTH W3 [W0++] ; Write PM high byte into program latch , Note: In Example6-2, the contents of the upper byte of W3 has no effect. 6.6.4 INITIATING THE PROGRAMMING SEQUENCE For protection, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs. EXAMPLE 6-3: INITIATING A PROGRAMMING SEQUENCE DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55,W0 MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted DS70118J-page 46 © 2011 Microchip Technology Inc.

© TABLE 6-1: NVM REGISTER MAP 2 01 File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All RESETS 1 M NVMCON 0760 WR WREN WRERR — — — — TWRI — PROGOP<6:0> 0000 0000 0000 0000 icro NVMADR 0762 NVMADR<15:0> uuuu uuuu uuuu uuuu ch NVMADRU 0764 — — — — — — — — NVMADR<23:16> 0000 0000 uuuu uuuu ip T NVMKEY 0766 — — — — — — — — KEY<7:0> 0000 0000 0000 0000 ec Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ h n Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. o lo g y In c . d s P I C 3 0 D S F 7 0 1 2 1 8 J 0 -p a 1 g e 4 0 7

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dsPIC30F2010 7.0 DATA EEPROM MEMORY A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- Note: This data sheet summarizes features of sible for waiting for the appropriate duration of time this group ofdsPIC30F devices and is not before initiating another data EEPROM write/erase intended to be a complete reference operation. Attempting to read the data EEPROM while source. For more information on the CPU, a programming or erase operation is in progress results peripherals, register descriptions and in unspecified data. general device functionality, refer to the Control bit WR initiates write operations, similar to pro- “dsPIC30F Family Reference Manual” gram Flash writes. This bit cannot be cleared, only set, (DS70046). For more information on the in software. This bit is cleared in hardware at the com- device instruction set and programming, pletion of the write operation. The inability to clear the refer to the “16-bit MCU and DSC Pro- WR bit in software prevents the accidental or grammer’s Reference Manual” premature termination of a write operation. (DS70157). The WREN bit, when set, will allow a write operation. The Data EEPROM Memory is readable and writable On power-up, the WREN bit is clear. The WRERR bit is during normal operation over the entire VDD range. The set when a write operation is interrupted by a MCLR data EEPROM memory is directly mapped in the Reset, or a WDT Time-out Reset, during normal oper- program memory address space. ation. In these situations, following Reset, the user can check the WRERR bit and rewrite the location. The The four SFRs used to read and write the program address register NVMADR remains unchanged. Flash memory are used to access data EEPROM memory as well. As described in Section6.0 “Flash Note: Interrupt flag bit NVMIF in the IFS0 regis- Program Memory”, these registers are: ter is set when write is complete. It must • NVMCON be cleared in software. • NVMADR 7.1 Reading the Data EEPROM • NVMADRU • NVMKEY A TBLRD instruction reads a word at the current pro- The EEPROM data memory allows read and write of gram word address. This example uses W0 as a single words and 16-word blocks. When interfacing to pointer to data EEPROM. The result is placed in data memory, NVMADR, in conjunction with the register W4, as shown in Example7-1. NVMADRU register, is used to address the EEPROM location being accessed. TBLRDL and TBLWTL EXAMPLE 7-1: DATA EEPROM READ instructions are used to read and write data EEPROM. MOV #LOW_ADDR_WORD,W0 ; Init Pointer The dsPIC30F devices have up to 1 Kbyte of data MOV #HIGH_ADDR_WORD,W1 EEPROM, with an address range from 0x7FFC00 to MOV W1 TBLPAG , 0x7FFFFE. TBLRDL [ W0 ], W4 ; read data EEPROM A word write operation should be preceded by an erase of the corresponding memory location(s). The write typically requires 2 ms to complete, but the write time will vary with voltage and temperature. © 2011 Microchip Technology Inc. DS70118J-page 49

dsPIC30F2010 7.2 Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the WR and WREN bits in NVMCON register. Setting the WR bit initiates the erase, as shown in Example7-2. EXAMPLE 7-2: DATA EEPROM BLOCK ERASE ; Select data EEPROM block, ERASE, WREN bits MOV #4045,W0 MOV W0 NVMCON ; Initialize NVMCON SFR , ; Start erase cycle by setting WR after writing key sequence DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55,W0 ; MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Initiate erase sequence NOP NOP ; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete 7.2.2 ERASING A WORD OF DATA EEPROM The NVMADRU and NVMADR registers must point to the block. Select erase a block of data Flash, and set the WR and WREN bits in NVMCON register. Setting the WR bit initiates the erase, as shown in Example7-3. EXAMPLE 7-3: DATA EEPROM WORD ERASE ; Select data EEPROM word, ERASE, WREN bits MOV #4044,W0 MOV W0 NVMCON , ; Start erase cycle by setting WR after writing key sequence DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55,W0 ; MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 ; MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Initiate erase sequence NOP NOP ; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete DS70118J-page 50 © 2011 Microchip Technology Inc.

dsPIC30F2010 7.3 Writing to the Data EEPROM The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to To write an EEPROM data location, the following NVMCON, then set WR bit) for each word. It is strongly sequence must be followed: recommended that interrupts be disabled during this 1. Erase data EEPROM word. codesegment. a) Select word, data EEPROM, erase and set Additionally, the WREN bit in NVMCON must be set to WREN bit in NVMCON register. enable writes. This mechanism prevents accidental b) Write address of word to be erased into writes to data EEPROM, due to unexpected code exe- NVMADRU/NVMADR. cution. The WREN bit should be kept clear at all times, c) Enable NVM interrupt (optional). except when updating the EEPROM. The WREN bit is not cleared byhardware. d) Write 0x55 to NVMKEY. e) Write 0xAA to NVMKEY. After a write sequence has been initiated, clearing the WREN bit will not affect the current write cycle. The WR f) Set the WR bit. This will begin erase cycle. bit will be inhibited from being set unless the WREN bit g) Either poll NVMIF bit or wait for NVMIF is set. The WREN bit must be set on a previous interrupt. instruction. Both WR and WREN cannot be set with the h) The WR bit is cleared when the erase cycle same instruction. ends. At the completion of the write cycle, the WR bit is 2. Write data word into data EEPROM write cleared in hardware and the Nonvolatile Memory Write latches. Complete Interrupt Flag bit (NVMIF) is set. The user 3. Program 1 data word into data EEPROM. may either enable this interrupt, or poll this bit. NVMIF a) Select word, data EEPROM, program and must be cleared by software. set WREN bit in NVMCON register. 7.3.1 WRITING A WORD OF DATA b) Enable NVM write done interrupt (optional). EEPROM c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. Once the user has erased the word to be programmed, then a table write instruction is used to write one write e) Set The WR bit. This will begin program latch, as shown in Example7-4. cycle. f) Either poll NVMIF bit or wait for NVM interrupt. g) The WR bit is cleared when the write cycle ends. EXAMPLE 7-4: DATA EEPROM WORD WRITE ; Point to data memory MOV #LOW_ADDR_WORD,W0 ; Init pointer MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #LOW(WORD),W2 ; Get data TBLWTL W2 [ W0] ; Write data , ; The NVMADR captures last table access address ; Select data EEPROM for 1 word op MOV #0x4004,W0 MOV W0 NVMCON , ; Operate key to allow write operation DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55,W0 MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Initiate program sequence NOP NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2011 Microchip Technology Inc. DS70118J-page 51

dsPIC30F2010 7.3.2 WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 ; Init pointer MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 ; Get 1st data TBLWTL W2 [ W0]++ ; write data , MOV #data2,W2 ; Get 2nd data TBLWTL W2 [ W0]++ ; write data , MOV #data3,W2 ; Get 3rd data TBLWTL W2 [ W0]++ ; write data , MOV #data4,W2 ; Get 4th data TBLWTL W2 [ W0]++ ; write data , MOV #data5,W2 ; Get 5th data TBLWTL W2 [ W0]++ ; write data , MOV #data6,W2 ; Get 6th data TBLWTL W2 [ W0]++ ; write data , MOV #data7,W2 ; Get 7th data TBLWTL W2 [ W0]++ ; write data , MOV #data8,W2 ; Get 8th data TBLWTL W2 [ W0]++ ; write data , MOV #data9,W2 ; Get 9th data TBLWTL W2 [ W0]++ ; write data , MOV #data10,W2 ; Get 10th data TBLWTL W2 [ W0]++ ; write data , MOV #data11,W2 ; Get 11th data TBLWTL W2 [ W0]++ ; write data , MOV #data12,W2 ; Get 12th data TBLWTL W2 [ W0]++ ; write data , MOV #data13,W2 ; Get 13th data TBLWTL W2 [ W0]++ ; write data , MOV #data14,W2 ; Get 14th data TBLWTL W2 [ W0]++ ; write data , MOV #data15,W2 ; Get 15th data TBLWTL W2 [ W0]++ ; write data , MOV #data16,W2 ; Get 16th data TBLWTL W2 [ W0]++ ; write data. The NVMADR captures last table access address. , MOV #0x400A,W0 ; Select data EEPROM for multi word op MOV W0 NVMCON ; Operate Key to allow program operation , DISI #5 ; Block all interrupts with priority <7 for next 5 instructions MOV #0x55,W0 MOV W0 NVMKEY ; Write the 0x55 key , MOV #0xAA,W1 MOV W1 NVMKEY ; Write the 0xAA key , BSET NVMCON,#WR ; Start write cycle NOP NOP 7.4 Write Verify 7.5 Protection Against Spurious Write Depending on the application, good programming There are conditions when the device may not want to practice may dictate that the value written to the mem- write to the data EEPROM memory. To protect against ory should be verified against the original value. This spurious EEPROM writes, various mechanisms have should be used in applications where excessive writes been built-in. On power-up, the WREN bit is cleared; can stress bits near the specification limit. also, the Power-up Timer prevents EEPROMwrite. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. DS70118J-page 52 © 2011 Microchip Technology Inc.

dsPIC30F2010 8.0 I/O PORTS or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Note: This data sheet summarizes features of Reset. Reads from the latch (LATx), read the latch. this group ofdsPIC30F devices and is not Writes to the latch, write the latch (LATx). Reads from intended to be a complete reference the port (PORTx), read the port pins, and writes to the source. For more information on the CPU, port pins, write the latch (LATx). peripherals, register descriptions and Any bit and its associated data and control registers general device functionality, refer to the that are not valid for a particular device will be disabled. “dsPIC30F Family Reference Manual” That means the corresponding LATx and TRISx (DS70046). registers and the port pin will read as zeros. All of the device pins (except VDD, VSS, MCLR and When a pin is shared with another peripheral or func- OSC1/CLKI) are shared between the peripherals and tion that is defined as an input only, it is nevertheless the parallel I/O ports. regarded as a dedicated port because there is no other competing source of outputs. An example is the All I/O input ports feature Schmitt Trigger inputs for INT4 pin. improved noise immunity. A parallel I/O (PIO) port that shares a pin with a periph- 8.1 Parallel I/O (PIO) Ports eral is, in general, subservient to the peripheral. The peripheral’s output buffer data and control signals are When a peripheral is enabled and the peripheral is provided to a pair of multiplexers. The multiplexers actively driving an associated pin, the use of the pin as select whether the peripheral or the associated port a general purpose output pin is disabled. The I/O pin has ownership of the output data and control signals of may be read, but the output driver for the parallel port the I/O pad cell. Figure8-1 shows how ports are shared bit will be disabled. If a peripheral is enabled, but the with other peripherals, and the associated I/O cell (pad) peripheral is not actively driving a pin, that pin may be to which they are connected. Table8-1 shows the driven by a port. formats of the registers for the shared ports, PORTB All port pins have three registers directly associated through PORTF. with the operation of the port pin. The data direction register (TRISx) determines whether the pin is an input FIGURE 8-1: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable Peripheral Output Enable I/O Cell Peripheral Output Data 1 Output Enable 0 PIO Module 1 Output Data Read TRIS 0 Data Bus D Q I/O Pad WR TRIS CK TRIS Latch D Q WR LAT + CK WR Port Data Latch Read LAT Input Data Read Port © 2011 Microchip Technology Inc. DS70118J-page 53

dsPIC30F2010 8.2 Configuring Analog Port Pins 8.3 Input Change Notification Module The use of the ADPCFG and TRIS registers control the The Input Change Notification module provides the operation of the A/D port pins. The port pins that are dsPIC30F devices the ability to generate interrupt desired as analog inputs must have their correspond- requests to the processor in response to a change-of- ing TRIS bit set (input). If the TRIS bit is cleared (out- state on selected input pins. This module is capable of put), the digital output level (VOH or VOL) will be detecting input change-of-states even in Sleep mode, converted. when the clocks are disabled. There are up to 22 exter- nal signals (CN0 through CN21) that may be selected When reading the PORT register, all pins configured as (enabled) for generating an interrupt request on a analog input channel will read as cleared (a low level). change-of-state. Pins configured as digital inputs will not convert an ana- log input. Analog levels on any pin that is defined as a digital input (including the ANx pins), may cause the input buffer to consume current that exceeds the device specifications. 8.2.1 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be a NOP. EXAMPLE 8-1: PORT WRITE/READ EXAMPLE MOV 0xFF00, W0 ; Configure PORTB<15:8> ; as inputs MOV W0, TRISBB ; and PORTB<7:0> as outputs NOP ; Delay 1 cycle btss PORTB, #13; Next Instruction DS70118J-page 54 © 2011 Microchip Technology Inc.

© TABLE 8-1: dsPIC30F2010 PORT REGISTER MAP 2 0 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 1 M TRISB 02C6 — — — — — — — — — — TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0000 0000 0011 1111 icro PORTB 02C8 — — — — — — — — — — RB5 RB4 RB3 RB2 RB1 RB0 0000 0000 0000 0000 c h LATB 02CA — — — — — — — — — — LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000 0000 0000 0000 ip T TRISC 02CC TRISC15 TRISC14 TRISC13 — — — — — — — — — — — — — 1110 0000 0000 0000 e c h PORTC 02CE RC15 RC14 RC13 — — — — — — — — — — — — — 0000 0000 0000 0000 n o lo LATC 02D0 LATC15 LATC14 LATC13 — — — — — — — — — — — — — 0000 0000 0000 0000 g y In TRISD 02D2 — — — — — — — — — — — — — — TRISD1 TRISD0 0000 0000 0000 0111 c. PORTD 02D4 — — — — — — — — — — — — — — RD1 RD0 0000 0000 0000 0000 LATD 02D6 — — — — — — — — — — — — — — LATD1 LATD0 0000 0000 0000 0000 TRISE 02D8 — — — — — — — TRISE8 — — TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 0000 0001 0011 1111 PORTE 02DA — — — — — — — RE8 — — RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000 LATE 02DC — — — — — — — LATE8 — — LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 0000 0000 0000 0000 TRISF 02DE — — — — — — — — — — — — TRISF3 TRISF2 — — 0000 0000 0000 1100 PORTF 02E0 — — — — — — — — — — — — RF3 RF2 — — 0000 0000 0000 0000 LATF 02E2 — — — — — — — — — — — — LATF3 LATF2 — — 0000 0000 0000 0000 Legend: — = unimplemented bit, read as ‘0’ Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-2: INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 15-0) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State CNEN1 00C0 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 0000 0000 0000 CNEN2 00C2 — — — — — — — — — — CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 0000 0000 0000 CNPU1 00C4 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000 d CNPU2 00C6 — — — — — — — — — — CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 0000 0000 0000 Legend: — = unimplemented bit, read as ‘0’ s Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. P I C 3 0 D S F 7 0 1 2 1 8 J 0 -p a 1 g e 5 0 5

dsPIC30F2010 NOTES: DS70118J-page 56 © 2011 Microchip Technology Inc.

dsPIC30F2010 9.0 TIMER1 MODULE These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure9-1 Note: This data sheet summarizes features of presents a block diagram of the 16-bit timer module. this group ofdsPIC30F devices and is not 16-bit Timer Mode: In the 16-bit Timer mode, the timer intended to be a complete reference increments on every instruction cycle up to a match source. For more information on the CPU, value, preloaded into the period register PR1, then peripherals, register descriptions and resets to ‘0’ and continues to count. general device functionality, refer to the When the CPU goes into the Idle mode, the timer will “dsPIC30F Family Reference Manual” stop incrementing unless the TSIDL (T1CON<13>) (DS70046). bit= 0. If TSIDL = 1, the timer module logic will resume This section describes the 16-bit general purpose the incrementing sequence upon termination of the Timer1 module and associated operational modes. CPU Idle mode. Figure9-1 depicts the simplified block diagram of the 16-bit Synchronous Counter Mode: In the 16-bit 16-bit Timer1 Module. Synchronous Counter mode, the timer increments on Note: Timer1 is a ‘Type A’ timer. Refer to the the rising edge of the applied external clock signal, specifications for the Type A timer in which is synchronized with the internal phase clocks. Section22.0 “Electrical Characteristics” The timer counts up to a match value preloaded in PR1, for details. then resets to ‘0’ and continues. When the CPU goes into the Idle mode, the timer will The following sections provide a detailed description of stop incrementing, unless the respective TSIDL bit = 0. the operational modes of the timers, including setup If TSIDL = 1, the timer module logic will resume the and control registers along with associated block incrementing sequence upon termination of the CPU diagrams. Idle mode. The Timer1 module is a 16-bit timer which can serve as 16-bit Asynchronous Counter Mode: In the 16-bit the time counter for the real-time clock, or operate as a Asynchronous Counter mode, the timer increments on free running interval timer/counter. The 16-bit timer has every rising edge of the applied external clock signal. the following modes: The timer counts up to a match value preloaded in PR1, • 16-bit Timer then resets to ‘0’ and continues. • 16-bit Synchronous Counter When the timer is configured for the Asynchronous • 16-bit Asynchronous Counter mode of operation and the CPU goes into the Idle Further, the following operational characteristics are mode, the timer will stop incrementing if TSIDL = 1. supported: • Timer gate operation • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit period register match or falling edge of external gate signal © 2011 Microchip Technology Inc. DS70118J-page 57

dsPIC30F2010 FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) PR1 Equal Comparator x 16 TSYNC 1 Sync TMR1 (3) Reset 0 0 T1IF Event Flag 1 Q D TGATE Q CK TGATE E T S A C G T T TCKPS<1:0> TON 2 SOSCO/ 1 X T1CK LPOSCEN Gate Prescaler Sync 0 1 1, 8, 64, 256 SOSCI TCY 0 0 9.1 Timer Gate Operation 9.3 Timer Operation During Sleep Mode The 16-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal TCY to During CPU Sleep mode, the timer will operate if: increment the respective timer when the gate input sig- • The timer module is enabled (TON = 1) and nal (T1CK pin) is asserted high. Control bit TGATE (T1CON<6>) must be set to enable this mode. The • The timer clock source is selected as external timer must be enabled (TON = 1) and the timer clock (TCS = 1) and source set to internal (TCS = 0). • The TSYNC bit (T1CON<2>) is asserted to a logic ‘0’, which defines the external clock source as When the CPU goes into the Idle mode, the timer will asynchronous stop incrementing, unless TSIDL = 0. If TSIDL = 1, the timer will resume the incrementing sequence upon When all three conditions are true, the timer will termination of the CPU Idle mode. continue to count up to the period register and be Reset to 0x0000. 9.2 Timer Prescaler When a match between the timer and the period regis- ter occurs, an interrupt can be generated, if the The input clock (FOSC/4 or external clock) to the 16-bit respective timer interrupt enable bit is asserted. Timer, has a prescale option of 1:1, 1:8, 1:64, and 1:256 selected by control bits TCKPS<1:0> (T1CON<5:4>). The prescaler counter is cleared when any of the following occurs: • A write to the TMR1 register • Clearing of the TON bit (T1CON<15>) • Device Reset such as POR and BOR However, if the timer is disabled (TON = 0), then the timer prescaler cannot be reset since the prescaler clock is halted. TMR1 is not cleared when T1CON is written. It is cleared by writing to the TMR1 register. DS70118J-page 58 © 2011 Microchip Technology Inc.

dsPIC30F2010 9.4 Timer Interrupt 9.5.1 RTC OSCILLATOR OPERATION The 16-bit timer has the ability to generate an interrupt When the TON = 1, TCS = 1 and TGATE = 0, the timer on period match. When the timer count matches the increments on the rising edge of the 32 kHz LP oscilla- period register, the T1IF bit is asserted and an interrupt tor output signal, up to the value specified in the period will be generated, if enabled. The T1IF bit must be register, and is then Reset to ‘0’. cleared in software. The timer interrupt flag T1IF is The TSYNC bit must be asserted to a logic ‘0’ located in the IFS0 control register in the Interrupt (Asynchronous mode) for correct operation. Controller. Enabling LPOSCEN (OSCCON<1>) will disable the When the Gated Time Accumulation mode is enabled, normal Timer and Counter modes, and enable a timer an interrupt will also be generated on the falling edge of carry-out wake-up event. the gate signal (at the end of the accumulation cycle). When the CPU enters Sleep mode, the RTC will con- Enabling an interrupt is accomplished via the respec- tinue to operate, provided the 32 kHz external crystal tive timer interrupt enable bit, T1IE. The timer interrupt oscillator is active and the control bits have not been enable bit is located in the IEC0 control register in the changed. The TSIDL bit should be cleared to ‘0’ in Interrupt Controller. order for RTC to continue operation in Idle mode. 9.5 Real-Time Clock 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective inter- Timer1, when operating in Real-Time Clock (RTC) rupt flag, T1IF, is asserted and an interrupt will be gen- mode, provides time-of-day and event time stamping erated, if enabled. The T1IF bit must be cleared in capabilities. Key operational features of the RTC are: software. The respective Timer interrupt flag, T1IF, is • Operation from 32 kHz LP oscillator located in the IFS0 status register in the Interrupt • 8-bit prescaler Controller. • Low power Enabling an interrupt is accomplished via the respec- • Real-Time Clock Interrupts tive timer interrupt enable bit, T1IE. The Timer interrupt • These Operating modes are determined by enable bit is located in the IEC0 control register in the setting the appropriate bit(s) in the T1CON Interrupt Controller. Control register FIGURE 9-2: RECOMMENDED COMPONENTS FOR TIMER1 LP OSCILLATOR RTC C1 SOSCI 32.768 kHz dsPIC30F2010 XTAL SOSCO C2 R C1 = C2 = 18 pF; R = 100K © 2011 Microchip Technology Inc. DS70118J-page 59

D TABLE 9-1: TIMER1 REGISTER MAP d S 70 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 1 18 TMR1 0100 Timer 1 Register uuuu uuuu uuuu uuuu P J -p PR1 0102 Period Register 1 1111 1111 1111 1111 I ag T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 0000 0000 0000 C e 60 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ 3 Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 0 F 2 0 1 0 © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F2010 10.0 TIMER2/3 MODULE For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word Note: This data sheet summarizes features of of the 32-bit timer. this group ofdsPIC30F devices and is not Note: For 32-bit timer operation, T3CON control intended to be a complete reference bits are ignored. Only T2CON control bits source. For more information on the CPU, are used for setup and control. Timer 2 peripherals, register descriptions and clock and gate inputs are utilized for the general device functionality, refer to the 32-bit timer module, but an interrupt is “dsPIC30F Family Reference Manual” generated with the Timer3 interrupt flag (DS70046). (T3IF), and the interrupt is enabled with This section describes the 32-bit general purpose the Timer3 interrupt enable bit (T3IE). Timer module (Timer2/3) and associated operational 16-bit Mode: In the 16-bit mode, Timer2 and Timer3 modes. Figure10-1 depicts the simplified block dia- can be configured as two independent 16-bit timers. gram of the 32-bit Timer2/3 module. Figure10-2 and Each timer can be set up in either 16-bit Timer mode or Figure10-3 show Timer2/3 configured as two 16-bit Synchronous Counter mode. See Section9.0 independent 16-bit timers; Timer2 and Timer3, “Timer1 Module” for details on these two operating respectively. modes. Note: Timer2 is a ‘Type B’ timer and Timer3 is a The only functional difference between Timer2 and ‘Type C’ timer. Please refer to the Timer3 is that Timer2 provides synchronization of the appropriate timer type in Section22.0 clock prescaler output. This is useful for high frequency “Electrical Characteristics” for details. external clock inputs. The Timer2/3 module is a 32-bit timer, which can be 32-bit Timer Mode: In the 32-bit Timer mode, the timer configured as two 16-bit timers, with selectable operat- increments on every instruction cycle up to a match ing modes. These timers are utilized by other value, preloaded into the combined 32-bit period regis- peripheral modules such as: ter PR3/PR2, then resets to ‘0’ and continues to count. • Input Capture For synchronous 32-bit reads of the Timer2/Timer3 • Output Compare/Simple PWM pair, reading the least significant word (TMR2 register) will cause the most significant word (msw) to be read The following sections provide a detailed description, and latched into a 16-bit holding register, termed including setup and control registers, along with asso- TMR3HLD. ciated block diagrams for the operational modes of the timers. For synchronous 32-bit writes, the holding register (TMR3HLD) must first be written to. When followed by The 32-bit timer has the following modes: a write to the TMR2 register, the contents of TMR3HLD • Two independent 16-bit timers (Timer2 and will be transferred and latched into the MSB of the Timer3) with all 16-bit operating modes (except 32-bit timer (TMR3). Asynchronous Counter mode) 32-bit Synchronous Counter Mode: In the 32-bit • Single 32-bit Timer operation Synchronous Counter mode, the timer increments on • Single 32-bit Synchronous Counter the rising edge of the applied external clock signal, Further, the following operational characteristics are which is synchronized with the internal phase clocks. supported: The timer counts up to a match value preloaded in the combined 32-bit period register PR3/PR2, then resets • ADC Event Trigger to ‘0’ and continues. • Timer Gate Operation When the timer is configured for the Synchronous • Selectable Prescaler Settings Counter mode of operation and the CPU goes into the • Timer Operation during Idle and Sleep modes Idle mode, the timer will stop incrementing, unless the • Interrupt on a 32-bit Period Register Match TSIDL (T2CON<13>) bit = ‘0’. If TSIDL = ‘1’, the timer module logic will resume the incrementing sequence These operating modes are determined by setting the upon termination of the CPU Idle mode. appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2011 Microchip Technology Inc. DS70118J-page 61

dsPIC30F2010 FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 16 Write TMR2 Read TMR2 16 Reset TMR3 TMR2 Sync MSB LSB ADC Event Trigger Comparator x 32 Equal PR3 PR2 0 T3IF Event Flag 1 Q D TGATE(T2CON<6>) Q CK TGATE (T2CON<6>) E T S A C G T T TCKPS<1:0> TON 2 T2CK 1 X Prescaler Gate Sync 0 1 1, 8, 64, 256 TCY 0 0 Note: Timer Configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70118J-page 62 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM (TYPE B TIMER) PR2 Equal Comparator x 16 TMR2 Sync Reset 0 T2IF Event Flag 1 Q D TGATE Q CK TGATE E T S A C G T T TCKPS<1:0> TON 2 T2CK 1 X Gate Prescaler Sync 0 1 1, 8, 64, 256 TCY 0 0 FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM (TYPE C TIMER) PR3 ADC Event Trigger Equal Comparator x 16 TMR3 Reset 0 T3IF Event Flag 1 Q D TGATE Q CK TGATE E T S A C G T T TCKPS<1:0> TON 2 Sync 1 X Prescaler See 0 1 1, 8, 64, 256 NOTE TCY 0 0 Note: The dsPIC30F2010 does not have an external pin input to TIMER3. The following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) © 2011 Microchip Technology Inc. DS70118J-page 63

dsPIC30F2010 10.1 Timer Gate Operation 10.4 Timer Operation During Sleep Mode The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal TCY to During CPU Sleep mode, the timer will not operate, increment the respective timer when the gate input sig- because the internal clocks are disabled. nal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in 10.5 Timer Interrupt this mode, Timer2 is the originating clock source. The TGATE setting is ignored for Timer3. The timer must be The 32-bit timer module can generate an interrupt on enabled (TON = 1) and the timer clock source set to period match, or on the falling edge of the external gate internal (TCS = 0). signal. When the 32-bit timer count matches the respective 32-bit period register, or the falling edge of The falling edge of the external signal terminates the the external “gate” signal is detected, the T3IF bit count operation, but does not reset the timer. The user (IFS0<7>) is asserted and an interrupt will be gener- must reset the timer in order to start counting from zero. ated if enabled. In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must 10.2 ADC Event Trigger be cleared in software. When a match occurs between the 32-bit timer (TMR3/ Enabling an interrupt is accomplished via the TMR2) and the 32-bit combined period register (PR3/ respective timer interrupt enable bit, T3IE (IEC0<7>). PR2), a special ADC trigger event signal is generated by Timer3. 10.3 Timer Prescaler The input clock (FOSC/4 or external clock) to the timer has a prescale option of 1:1, 1:8, 1:64, and 1:256 selected by control bits TCKPS<1:0> (T2CON<5:4> and T3CON<5:4>). For the 32-bit timer operation, the originating clock source is Timer2. The prescaler oper- ation for Timer3 is not applicable in this mode. The prescaler counter is cleared when any of the following occurs: • A write to the TMR2/TMR3 register • Clearing either of the TON (T2CON<15> or T3CON<15>) bits to ‘0’ • Device Reset such as POR and BOR However, if the timer is disabled (TON = 0), then the Timer 2 prescaler cannot be reset, since the prescaler clock is halted. TMR2/TMR3 is not cleared when T2CON/T3CON is written. DS70118J-page 64 © 2011 Microchip Technology Inc.

© TABLE 10-1: TIMER2/3 REGISTER MAP 2 0 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 1 M TMR2 0106 Timer2 Register uuuu uuuu uuuu uuuu ic TMR3HLD 0108 Timer3 Holding Register (For 32-bit timer operations only) uuuu uuuu uuuu uuuu ro ch TMR3 010A Timer3 Register uuuu uuuu uuuu uuuu ip T PR2 010C Period Register 2 1111 1111 1111 1111 e c PR3 010E Period Register 3 1111 1111 1111 1111 h no T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 0000 0000 0000 lo g T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000 0000 0000 0000 y In Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ c . Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. d s P I C 3 0 D S F 7 0 1 2 1 8 J 0 -p a 1 g e 6 0 5

dsPIC30F2010 NOTES: DS70118J-page 66 © 2011 Microchip Technology Inc.

dsPIC30F2010 11.0 INPUT CAPTURE MODULE The key operational features of the Input Capture module are: Note: This data sheet summarizes features of • Simple Capture Event mode this group ofdsPIC30F devices and is not • Timer2 and Timer3 mode selection intended to be a complete reference source. For more information on the CPU, • Interrupt on input capture event peripherals, register descriptions and These operating modes are determined by setting the general device functionality, refer to the appropriate bits in the ICxCON register (where “dsPIC30F Family Reference Manual” x=1,2,...,N). The dsPIC DSC devices contain up to (DS70046). eight capture channels, (i.e., the maximum value of Nis 8). This section describes the Input Capture module and associated operational modes. The features provided Note: The dsPIC30F2010 device has four by this module are useful in applications requiring Fre- capture inputs – IC1, IC2, IC7 and IC8. quency (Period) and Pulse measurement. Figure11-1 The naming of these four capture chan- depicts a block diagram of the Input Capture module. nels is intentional and preserves software Input capture is useful for such modes as: compatibility with other dsPIC DSC devices. • Frequency/Period/Pulse Measurements • Additional sources of External Interrupts FIGURE 11-1: INPUT CAPTURE MODE BLOCK DIAGRAM From General Purpose Timer Module T2_CNT T3_CNT 16 16 ICx ICTMR Pin 1 0 Prescaler Clock Edge FIFO 1, 4, 16 Synchronizer Detection R/W Logic Logic 3 ICM<2:0> ICxBUF Mode Select ICBNE, ICOV ICI<1:0> Interrupt ICxCON Logic Data Bus SSeett FFllaagg IICCxxIIFF Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2011 Microchip Technology Inc. DS70118J-page 67

dsPIC30F2010 11.1 Simple Capture Event Mode 11.1.3 TIMER2 AND TIMER3 SELECTION MODE The simple capture events in the dsPIC30F product family are: The input capture module consists of up to eight input capture channels. Each channel can select between • Capture every falling edge one of two timers for the time base, Timer2 or Timer3. • Capture every rising edge Selection of the timer resource is accomplished • Capture every 4th rising edge through SFR bit ICTMR (ICxCON<7>). Timer3 is the • Capture every 16th rising edge default timer resource available for the input capture • Capture every rising and falling edge module. These simple Input Capture modes are configured by 11.1.4 HALL SENSOR MODE setting the appropriate bits ICM<2:0> (ICxCON<2:0>). When the input capture module is set for capture on 11.1.1 CAPTURE PRESCALER every edge, rising and falling, ICM<2:0> = 001, the fol- There are four input capture prescaler settings, speci- lowing operations are performed by the input capture fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the logic: capture channel is turned off, the prescaler counter will • The input capture interrupt flag is set on every be cleared. In addition, any Reset will clear the edge, rising and falling. prescaler counter. • The interrupt on Capture mode setting bits, ICI<1:0>, is ignored, since every capture 11.1.2 CAPTURE BUFFER OPERATION generates an interrupt. Each capture channel has an associated FIFO buffer, • A capture overflow condition is not generated in which is four 16-bit words deep. There are two status this mode. flags, which provide status on the FIFO buffer: • ICBNE – Input Capture Buffer Not Empty • ICOV – Input Capture Overflow The ICBFNE will be set on the first input capture event and remain set until all capture events have been read from the FIFO. As each word is read from the FIFO, the remaining words are advanced by one position within the buffer. In the event that the FIFO is full with four capture events and a fifth capture event occurs prior to a read of the FIFO, an overflow condition will occur and the ICOV bit will be set to a logic ‘1’. The fifth capture event is lost and is not stored in the FIFO. No additional events will be captured until all four events have been read from the buffer. If a FIFO read is performed after the last read and no new capture event has been received, the read will yield indeterminate results. DS70118J-page 68 © 2011 Microchip Technology Inc.

dsPIC30F2010 11.2 Input Capture Operation During 11.2.2 INPUT CAPTURE IN CPU IDLE Sleep and Idle Modes MODE CPU Idle mode allows input capture module operation An input capture event will generate a device wake-up with full functionality. In the CPU Idle mode, the interrupt or interrupt, if enabled, if the device is in CPU Idle or mode selected by the ICI<1:0> bits are applicable, as Sleep mode. well as the 4:1 and 16:1 capture prescale settings, Independent of the timer being enabled, the input which are defined by control bits ICM<2:0>. This mode capture module will wake-up from the CPU Sleep or requires the selected timer to be enabled. Moreover, the Idle mode when a capture event occurs, if ICSIDL bit must be asserted to a logic ‘0’. ICM<2:0>=111 and the interrupt enable bit is If the input capture module is defined as asserted. The same wake-up can generate an inter- ICM<2:0>=111 in CPU Idle mode, the input capture rupt, if the conditions for processing the interrupt have pin will serve only as an external interrupt pin. been satisfied. The wake-up feature is useful as a method of adding extra external pin interrupts. 11.3 Input Capture Interrupts 11.2.1 INPUT CAPTURE IN CPU SLEEP The input capture channels have the ability to generate MODE an interrupt, based upon the selected number of cap- CPU Sleep mode allows input capture module opera- ture events. The selection number is set by control bits tion with reduced functionality. In the CPU Sleep ICI<1:0> (ICxCON<6:5>). mode, the ICI<1:0> bits are not applicable, and the Each channel provides an interrupt flag (ICxIF) bit. The input capture module can only function as an external respective capture channel interrupt flag is located in interrupt source. the corresponding IFSx status register. The capture module must be configured for interrupt Enabling an interrupt is accomplished via the respec- only on the rising edge (ICM<2:0> = 111), in order for tive capture channel interrupt enable (ICxIE) bit. The the input capture module to be used while the device capture interrupt enable bit is located in the is in Sleep mode. The prescale settings of 4:1 or 16:1 corresponding IEC Control register. are not applicable in this mode. © 2011 Microchip Technology Inc. DS70118J-page 69

D TABLE 11-1: INPUT CAPTURE REGISTER MAP d S 70 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 1 18 IC1BUF 0140 Input 1 Capture Register uuuu uuuu uuuu uuuu P J -p IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 I ag C e IC2BUF 0144 Input 2 Capture Register uuuu uuuu uuuu uuuu 70 IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 3 0 IC3BUF 0148 Input 3 Capture Register uuuu uuuu uuuu uuuu F IC3CON 014A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 2 IC4BUF 014C Input 4 Capture Register uuuu uuuu uuuu uuuu 0 IC4CON 014E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 1 IC5BUF 0150 Input 5 Capture Register uuuu uuuu uuuu uuuu 0 IC5CON 0152 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 IC6BUF 0154 Input 6 Capture Register uuuu uuuu uuuu uuuu IC6CON 0156 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 IC7BUF 0158 Input 7 Capture Register uuuu uuuu uuuu uuuu IC7CON 015A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 IC8BUF 015C Input 8 Capture Register uuuu uuuu uuuu uuuu IC8CON 015E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F2010 12.0 OUTPUT COMPARE MODULE The key operational features of the Output Compare module include: Note: This data sheet summarizes features of • Timer2 and Timer3 Selection mode this group ofdsPIC30F devices and is not • Simple Output Compare Match mode intended to be a complete reference source. For more information on the CPU, • Dual Output Compare Match mode peripherals, register descriptions and • Simple PWM mode general device functionality, refer to the • Output Compare during Sleep and Idle modes “dsPIC30F Family Reference Manual” • Interrupt on Output Compare/PWM Event (DS70046). These operating modes are determined by setting This section describes the Output Compare module theappropriate bits in the 16-bit OCxCON SFR (where and associated operational modes. The features pro- x = 1 and 2). vided by this module are useful in applications requiring OCxRS and OCxR in the figure represent the Dual operational modes such as: Compare registers. In the Dual Compare mode, the • Generation of Variable Width Output Pulses OCxR register is used for the first compare and OCxRS • Power Factor Correction is used for the second compare. Figure12-1 depicts a block diagram of the Output Compare module. FIGURE 12-1: OUTPUT COMPARE MODE BLOCK DIAGRAM Set Flag bit OCxIF OCxRS OCxR Output S Q OCx Logic R Output Enable 3 OCM<2:0> Comparator Mode Select OCFA (for x = 1 and 2) OCTSEL 0 1 0 1 From General Purpose Timer Module TMR2<15:0> TMR3<15:0> T2P2_MATCH T3P3_MATCH Note: Where ‘x’ is shown, reference is made to the registers associated with the respective Output Compare channels 1and 2. © 2011 Microchip Technology Inc. DS70118J-page 71

dsPIC30F2010 12.1 Timer2 and Timer3 Selection Mode 12.3.2 CONTINUOUS PULSE MODE Each output compare channel can select between one For the user to configure the module for the generation of two 16-bit timers: Timer2 or Timer3. of a continuous stream of output pulses, the following steps are required: The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource • Determine instruction cycle time TCY. for the Output Compare module. • Calculate desired pulse value based on TCY. • Calculate timer to start pulse width from timer start 12.2 Simple Output Compare Match value of 0x0000. Mode • Write pulse width start and stop times into OCxR and OCxRS (x denotes channel 1, 2) compare When control bits OCM<2:0> (OCxCON<2:0>) = 001, registers, respectively. 010 or 011, the selected output compare channel is • Set timer period register to value equal to, or configured for one of three simple Output Compare greater than, value in OCxRS compare register. Match modes: • Set OCM<2:0> = 101. • Compare forces I/O pin low • Enable timer, TON (TxCON<15>) = 1. • Compare forces I/O pin high • Compare toggles I/O pin 12.4 Simple PWM Mode The OCxR register is used in these modes. The OCxR When control bits OCM<2:0> (OCxCON<2:0>) = 110 register is loaded with a value and is compared to the or 111, the selected output compare channel is config- selected incrementing timer count. When a compare ured for the PWM mode of operation. When configured occurs, one of these Compare Match modes occurs. If for the PWM mode of operation, OCxR is the main latch the counter resets to zero before reaching the value in (read-only) and OCxRS is the secondary latch. This OCxR, the state of the OCx pin remains unchanged. enables glitchless PWM transitions. 12.3 Dual Output Compare Match Mode The user must perform the following steps in order to configure the output compare module for PWM When control bits OCM<2:0> (OCxCON<2:0>) = 100 operation: or 101, the selected output compare channel is config- 1. Set the PWM period by writing to the appropriate ured for one of two Dual Output Compare modes, period register. which are: 2. Set the PWM duty cycle by writing to the OCxRS • Single Output Pulse mode register. • Continuous Output Pulse mode 3. Configure the output compare module for PWM operation. 12.3.1 SINGLE PULSE MODE 4. Set the TMRx prescale value and enable the For the user to configure the module for the generation Timer, TON (TxCON<15>) = 1. of a single output pulse, the following steps are required (assuming timer is off): 12.4.1 INPUT PIN FAULT PROTECTION FOR PWM • Determine instruction cycle time TCY. • Calculate desired pulse width value based on TCY. When control bits OCM<2:0> (OCxCON<2:0>) = 111, • Calculate time to start pulse from timer start value the selected output compare channel is again config- of 0x0000. ured for the PWM mode of operation, with the additional feature of input fault protection. While in this • Write pulse width start and stop times into OCxR mode, if a logic ‘0’ is detected on the OCFA/B pin, the and OCxRS compare registers (x denotes respective PWM output pin is placed in the high-imped- channel 1, 2). ance input state. The OCFLT bit (OCxCON<4>) • Set timer period register to value equal to, or indicates whether a Fault condition has occurred. This greater than, value in OCxRS compare register. state will be maintained until both of the following • Set OCM<2:0> = 100. events have occurred: • Enable timer, TON (TxCON<15>) = 1. • The external Fault condition has been removed. To initiate another single pulse, issue another write to • The PWM mode has been re-enabled by writing set OCM<2:0> = 100. to the appropriate control bits. DS70118J-page 72 © 2011 Microchip Technology Inc.

dsPIC30F2010 12.4.2 PWM PERIOD 12.5 Output Compare Operation During CPU Sleep Mode The PWM period is specified by writing to the PRx reg- ister. The PWM period can be calculated using When the CPU enters the Sleep mode, all internal Equation12-1. clocks are stopped. Therefore, when the CPU enters the Sleep state, the output compare channel will drive EQUATION 12-1: PWM PERIOD the pin to the active state that was observed prior to entering the CPU Sleep state. PWM period = [(PRx) + 1] • 4 • TOSC • (TMRx prescale value) For example, if the pin was high when the CPU entered the Sleep state, the pin will remain high. Like- wise, if the pin was low when the CPU entered the PWM frequency is defined as 1/[PWM period]. Sleep state, the pin will remain low. In either case, the When the selected TMRx is equal to its respective output compare module will resume operation when period register, PRx, the following four events occur on the device wakes up. the next increment cycle: • TMRx is cleared. 12.6 Output Compare Operation During • The OCx pin is set. CPU Idle Mode - Exception 1: If PWM duty cycle is 0x0000, When the CPU enters the Idle mode, the output the OCx pin will remain low. compare module can operate with full functionality. - Exception 2: If duty cycle is greater than PRx, The output compare channel will operate during the the pin will remain high. CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at • The PWM duty cycle is latched from OCxRS into logic‘0’ and the selected time base (Timer2 or Timer3) OCxR. is enabled and the TSIDL bit of the selected timer is • The corresponding timer interrupt flag is set. set to logic ‘0’. See Figure12-1 for key PWM period comparisons. Timer3 is referred to in the figure for clarity. FIGURE 12-1: PWM OUTPUT TIMING Period Duty Cycle TMR3 = PR3 TMR3 = PR3 T3IF = 1 T3IF = 1 (Interrupt Flag) (Interrupt Flag) OCxR = OCxRS OCxR = OCxRS TMR3 = Duty Cycle (OCxR) TMR3 = Duty Cycle (OCxR) 12.7 Output Compare Interrupts For the PWM mode, when an event occurs, the respec- tive timer interrupt flag (T2IF or T3IF) is asserted and The output compare channels have the ability to gener- an interrupt will be generated, if enabled. The IF bit is ate an interrupt on a compare match, for whichever located in the IFS0 status register, and must be cleared Match mode has been selected. in software. The interrupt is enabled via the respective For all modes except the PWM mode, when a compare timer interrupt enable bit (T2IE or T3IE), located in the event occurs, the respective interrupt flag (OCxIF) is IEC0 Control register. The output compare interrupt asserted and an interrupt will be generated, if enabled. flag is never set during the PWM mode of operation. The OCxIF bit is located in the corresponding IFS status register, and must be cleared in software. The interrupt is enabled via the respective compare inter- rupt enable (OCxIE) bit, located in the corresponding IEC Control register. © 2011 Microchip Technology Inc. DS70118J-page 73

D TABLE 12-1: OUTPUT COMPARE REGISTER MAP d S 70 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 1 18 OC1RS 0180 Output Compare 1 Master Register 0000 0000 0000 0000 P J -p OC1R 0182 Output Compare 1 Slave Register 0000 0000 0000 0000 I age OC1CON 0184 — OCFRZ OCSIDL — — — — — — — — OCFLT1 OCTSEL1 OCM<2:0> 0000 0000 0000 0000 C 74 OC2RS 0186 Output Compare 2 Master Register 0000 0000 0000 0000 3 OC2R 0188 Output Compare 2 Slave Register 0000 0000 0000 0000 0 OC2CON 018A — OCFRZ OCSIDL — — — — — — — — OCFLT2 OCTSEL2 OCM<2:0> 0000 0000 0000 0000 F Legend: — = unimplemented bit, read as ‘0’ 2 Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 0 1 0 © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F2010 13.0 QUADRATURE ENCODER The Quadrature Encoder Interface (QEI) is a key fea- INTERFACE (QEI) MODULE ture requirement for several motor control applications, such as Switched Reluctance (SR) and AC Induction Note: This data sheet summarizes features of Motor (ACIM). The operational features of the QEI are, this group ofdsPIC30F devices and is not but not limited to: intended to be a complete reference • Three input channels for two phase signals and source. For more information on the CPU, index pulse peripherals, register descriptions and • 16-bit up/down position counter general device functionality, refer to the • Count direction status “dsPIC30F Family Reference Manual” • Position Measurement (x2 and x4) mode (DS70046). • Programmable digital noise filters on inputs This section describes the Quadrature Encoder Inter- • Alternate 16-bit Timer/Counter mode face (QEI) module and associated operational modes. • Quadrature Encoder Interface interrupts The QEI module provides the interface to incremental encoders for obtaining motor positioning data. Incre- These operating modes are determined by setting the mental encoders are very useful in motor control appropriate bits QEIM<2:0> (QEICON<10:8>). applications. Figure13-1 depicts the Quadrature Encoder Interface block diagram. FIGURE 13-1: QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM TQCKPS<1:0> Sleep Input TQCS 2 TCY 0 Synchronize Prescaler Det 1 1, 8, 64, 256 1 QEIM<2:0> 0 QEIIF D Q TQGATE Event CK Q Flag 16-bit Up/Down Counter Programmable 2 (POSCNT) QEA Digital Filter Quadrature Reset Encoder UPDN_SRC Interface Logic Comparator/ Zero Detect Equal 0 QEICON<11> 3 QEIM<2:0> 1 Mode Select Max Count Register (MAXCNT) Programmable QEB Digital Filter Programmable INDX Digital Filter 3 © 2011 Microchip Technology Inc. DS70118J-page 75

dsPIC30F2010 13.1 Quadrature Encoder Interface 13.2.2 POSITION COUNTER RESET Logic The Position Counter Reset Enable bit, POSRES (QEI<2>) controls whether the position counter is reset A typical incremental (a.k.a. optical) encoder has three when the index pulse is detected. This bit is only outputs: Phase A, Phase B, and an index pulse. These applicable when QEIM<2:0> = ‘100’ or ‘110’. signals are useful and often required in position and speed control of ACIM and SR motors. If the POSRES bit is set to ‘1’, then the position counter is reset when the index pulse is detected. If the The two channels, Phase A (QEA) and Phase B (QEB), POSRES bit is set to ‘0’, then the position counter is not have a unique relationship. If Phase A leads Phase B, reset when the index pulse is detected. The position then the direction (of the motor) is deemed positive or counter will continue counting up or down, and will be forward. If Phase A lags Phase B, then the direction (of reset on the rollover or underflow condition. the motor) is deemed negative or reverse. When selecting the INDX signal to reset the position A third channel, termed index pulse, occurs once per counter (POSCNT), the user has to specify the states revolution and is used as a reference to establish an on QEA and QEB input pins. These states have to be absolute position. The index pulse coincides with matched in order for a reset to occur. These states are Phase A and Phase B, both low. selected by the IMV<1:0> bit in the DFLTCON <10:9> register. 13.2 16-bit Up/Down Position Counter The IMV<1:0> (Index Match Value) bit allows the user Mode to specify the state of the QEA and QEB input pins The 16-bit Up/Down Counter counts up or down on during an index pulse when the POSCNT register is to every count pulse, which is generated by the difference be reset. of the Phase A and Phase B input signals. The counter In 4X Quadrature Count Mode: acts as an integrator, whose count value is proportional IMV1 =Required state of phase B input signal for to position. The direction of the count is determined by match on index pulse the UPDN signal, which is generated by the IMV0 =Required state of phase A input signal for Quadrature Encoder Interface Logic. match on index pulse In 2X Quadrature Count Mode: 13.2.1 POSITION COUNTER ERROR IMV1 =Selects phase input signal for index state CHECKING match (0 = Phase A, 1 = Phase B) Position count error checking in the QEI is provided for IMV0 =Required state of the selected phase input and indicated by the CNTERR bit (QEICON<15>). The signal for match on index pulse error checking only applies when the position counter The interrupt is still generated on the detection of the is configured for Reset on the Index Pulse modes index pulse and not on the position counter overflow/ (QEIM<2:0> = ‘110’ or ‘100’). In these modes, the underflow. contents of the POSCNT register is compared with the values (0xFFFF or MAXCNT + 1, depending on direc- 13.2.3 COUNT DIRECTION STATUS tion). If these values are detected, an error condition is As mentioned in the previous section, the QEI logic generated by setting the CNTERR bit and a QEI count generates an UPDN signal, based upon the relation- error interrupt is generated. The QEI count error ship between Phase A and Phase B. In addition to interrupt can be disabled by setting the CEID bit the output pin, the state of this internal UPDN signal (DFLTCON<8>). The position counter continues to is supplied to a SFR bit UPDN (QEICON<11>) as a count encoder edges after an error has been detected. read-only bit. The POSCNT register continues to count up/down until a natural rollover/underflow. No interrupt is generated for the natural rollover/underflow event. The CNTERR Note: QEI pins are multiplexed with analog bit is a read/write bit and reset in software by the user. inputs. User must insure that all QEI asso- ciated pins are set as digital inputs in the ADPCFG register. DS70118J-page 76 © 2011 Microchip Technology Inc.

dsPIC30F2010 13.3 Position Measurement Mode 13.5 Alternate 16-bit Timer/Counter There are two Measurement modes which are sup- When the QEI module is not configured for the QEI ported and are termed x2 and x4. These modes are mode QEIM<2:0> = 001, the module can be configured selected by the QEIM<2:0> mode select bits located in as a simple 16-bit timer/counter. The setup and control SFR QEICON<10:8>. of the auxiliary timer is accomplished through the QEI- CON SFR register. This timer functions identically to When control bits QEIM<2:0> = 100 or 101, the x2 Timer1. The QEA pin is used as the timer clock input. Measurement mode is selected and the QEI logic only looks at the Phase A input for the position counter When configured as a timer, the POSCNT register increment rate. Every rising and falling edge of the serves as the Timer Count Register and the MAXCNT Phase A signal causes the position counter to be incre- register serves as the Period Register. When a timer/ mented or decremented. The Phase B signal is still period register match occur, the QEI interrupt flag will utilized for the determination of the counter direction, be asserted. just as in the x4 mode. The only exception between the general purpose tim- Within the x2 Measurement mode, there are two ers and this timer is the added feature of external Up/ variations of how the position counter is reset: Down input select. When the UPDN pin is asserted high, the timer will increment up. When the UPDN pin 1. Position counter reset by detection of index is asserted low, the timer will be decremented. pulse, QEIM<2:0> = 100. 2. Position counter reset by match with MAXCNT, Note: Changing the Operational mode (i.e., from QEIM<2:0> = 101. QEI to Timer or vice versa), will not affect the Timer/Position Count Register When control bits QEIM<2:0> = 110 or 111, the x4 contents. Measurement mode is selected and the QEI logic looks at both edges of the Phase A and Phase B input sig- The UPDN control/status bit (QEICON<11>) can be nals. Every edge of both signals causes the position used to select the count direction state of the Timer reg- counter to increment or decrement. ister. When UPDN = 1, the timer will count up. When Within the x4 Measurement mode, there are two UPDN = 0, the timer will count down. variations of how the position counter is reset: In addition, control bit UPDN_SRC (QEICON<0>) 1. Position counter reset by detection of index determines whether the timer count direction state is pulse, QEIM<2:0> = 110. based on the logic state, written into the UPDN control/ status bit (QEICON<11>), or the QEB pin state. When 2. Position counter reset by match with MAXCNT, UPDN_SRC = 1, the timer count direction is controlled QEIM<2:0> = 111. from the QEB pin. Likewise, when UPDN_SRC = 0, the The x4 Measurement mode provides for finer resolu- timer count direction is controlled by the UPDN bit. tion data (more position counts) for determining motor position. Note: This Timer does not support the External Asynchronous Counter mode of operation. 13.4 Programmable Digital Noise If using an external clock source, the clock will automatically be synchronized to the Filters internal instruction cycle. The digital noise filter section is responsible for rejecting noise on the incoming quadrature signals. 13.6 QEI Module Operation During CPU Schmitt Trigger inputs and a three-clock cycle delay fil- Sleep Mode ter combine to reject low level noise and large, short duration noise spikes that typically occur in noise prone 13.6.1 QEI OPERATION DURING CPU applications, such as a motor system. SLEEP MODE The filter ensures that the filtered output signal is not The QEI module will be halted during the CPU Sleep permitted to change until a stable value has been mode. registered for three consecutive clock cycles. For the QEA, QEB and INDX pins, the clock divide fre- 13.6.2 TIMER OPERATION DURING CPU quency for the digital filter is programmed by bits SLEEP MODE QECK<2:0> (DFLTCON<6:4>) and are derived from During CPU Sleep mode, the timer will not operate, the base instruction cycle TCY. because the internal clocks are disabled. To enable the filter output for channels QEA, QEB and INDX, the QEOUT bit must be ‘1’. The filter network for all channels is disabled on POR and BOR. © 2011 Microchip Technology Inc. DS70118J-page 77

dsPIC30F2010 13.7 QEI Module Operation During CPU 13.8 Quadrature Encoder Interface Idle Mode Interrupts Since the QEI module can function as a quadrature The quadrature encoder interface has the ability to encoder interface, or as a 16-bit timer, the following generate an interrupt on occurrence of the following section describes operation of the module in both events: modes. • Interrupt on 16-bit up/down position counter rollover/underflow 13.7.1 QEI OPERATION DURING CPU IDLE • Detection of qualified index pulse, or if CNTERR MODE bit is set When the CPU is placed in the Idle mode, the QEI • Timer period match event (overflow/underflow) module will operate if the QEISIDL bit • Gate accumulation event (QEICON<13>)=0. This bit defaults to a logic ‘0’ upon executing POR and BOR. For halting the QEI The QEI interrupt flag bit, QEIIF, is asserted upon module during the CPU Idle mode, QEISIDL should be occurrence of any of the above events. The QEIIF bit set to ‘1’. must be cleared in software. QEIIF is located in the IFS2 status register. 13.7.2 TIMER OPERATION DURING CPU Enabling an interrupt is accomplished via the respec- IDLE MODE tive enable bit, QEIIE. The QEIIE bit is located in the When the CPU is placed in the Idle mode and the QEI IEC2 Control register. module is configured in the 16-bit Timer mode, the 16-bit timer will operate if the QEISIDL bit (QEI- CON<13>) = 0. This bit defaults to a logic ‘0’ upon executing POR and BOR. For halting the timer module during the CPU Idle mode, QEISIDL should be set to‘1’. If the QEISIDL bit is cleared, the timer will function normally, as if the CPU Idle mode had not been entered. DS70118J-page 78 © 2011 Microchip Technology Inc.

© TABLE 13-1: QEI REGISTER MAP 2 0 SFR 1 Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 Name M ic QEICON 0122 CNTERR — QEISIDL INDX UPDN QEIM2 QEIM1 QEIM0 SWPAB — TQGATE TQCKPS1 TQCKPS0 POSRES TQCS UPDN_SRC 0000 0000 0000 0000 roc DFLTCON 0124 — — — — — IMV1 IMV0 CEID QEOUT QECK2 QECK1 QECK0 — — — — 0000 0000 0000 0000 h ip POSCNT 0126 Position Counter<15:0> 0000 0000 0000 0000 T e MAXCNT 0128 Maximun Count<15:0> 1111 1111 1111 1111 c hn Legend: — = unimplemented bit, read as ‘0’ o lo Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. g y In c . d s P I C 3 0 D S F 7 0 1 2 1 8 J 0 -p a 1 g e 7 0 9

dsPIC30F2010 NOTES: DS70118J-page 80 © 2011 Microchip Technology Inc.

dsPIC30F2010 14.0 MOTOR CONTROL PWM MODULE Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). This module simplifies the task of generating multiple, synchronized Pulse Width Modulated (PWM) outputs. In particular, the following power and motion control applications are supported by the PWM module: • Three-Phase AC Induction Motor • Switched Reluctance (SR) Motor • Brushless DC (BLDC) Motor • Uninterruptible Power Supply (UPS) The PWM module has the following features: • Six PWM I/O pins with three duty cycle generators • Up to 16-bit resolution • ‘On-the-Fly’ PWM frequency changes • Edge and Center-Aligned Output modes • Single Pulse Generation mode • Interrupt support for asymmetrical updates in Center-Aligned mode • Output override control for Electrically Commutative Motor (ECM) operation • ‘Special Event’ comparator for scheduling other peripheral events • FLTA pin to optionally drive each of the PWM output pins to a defined state This module contains three duty cycle generators, numbered 1 through 3. The module has six PWM output pins, numbered PWM1H/PWM1L through PWM3H/PWM3L. The six I/O pins are grouped into high/low numbered pairs, denoted by the suffix H or L, respectively. For complementary loads, the low PWM pins are always the complement of the corresponding high I/O pin. A simplified block diagram of the Motor Control PWM modules is shown in Figure14-1. The PWM module allows several modes of operation which are beneficial for specific power control applications. © 2011 Microchip Technology Inc. DS70118J-page 81

dsPIC30F2010 FIGURE 14-1: PWM BLOCK DIAGRAM PWMCON1 PWM Enable and Mode SFRs PWMCON2 DTCON1 Dead-Time Control SFR FLTACON FLTA Pin Control SFR PWM Manual OVDCON Control SFR PWM Generator 3 PDC3 Buffer s u PDC3 B a at D bit Comparator ChaGnenneel r3a Dtoer aadn-dT ime PWM3H 6- Override Logic PWM3L 1 PTMR PWM Channel 2 Dead-Time Output PWM2H Generator 2 Generator and Driver Override Logic Block PWM2L Comparator PWM Channel 1 Dead-Time PWM1H Generator 1 Generator and PTPER Override Logic PWM1L FLTA PTPER Buffer PTCON Comparator Special Event Special Event Trigger Postscaler SEVTDIR SEVTCMP PTDIR PWM Time Base Note: Details of PWM Generator 1 and 2 not shown for clarity. DS70118J-page 82 © 2011 Microchip Technology Inc.

dsPIC30F2010 14.1 PWM Time Base 14.1.1 FREE RUNNING MODE The PWM time base is provided by a 15-bit timer with In the Free Running mode, the PWM time base counts a prescaler and postscaler. The time base is accessible upwards until the value in the Time Base Period regis- via the PTMR SFR. PTMR<15> is a read-only status ter (PTPER) is matched. The PTMR register is reset on bit, PTDIR, that indicates the present count direction of the following input clock edge and the time base will the PWM time base. If PTDIR is cleared, PTMR is continue to count upwards as long as the PTEN bit counting upwards. If PTDIR is set, PTMR is counting remains set. downwards. The PWM time base is configured via the When the PWM time base is in the Free Running mode PTCON SFR. The time base is enabled/disabled by (PTMOD<1:0> = 00), an interrupt event is generated setting/clearing the PTEN bit in the PTCON SFR. each time a match with the PTPER register occurs and PTMR is not cleared when the PTEN bit is cleared in the PTMR register is Reset to zero. The postscaler software. selection bits may be used in this mode of the timer to The PTPER SFR sets the counting period for PTMR. reduce the frequency of the interrupt events. The user must write a 15-bit value to PTPER<14:0>. 14.1.2 SINGLE-SHOT MODE When the value in PTMR<14:0> matches the value in PTPER<14:0>, the time base will either Reset to ‘0’, or In the Single-Shot Counting mode, the PWM time base reverse the count direction on the next occurring clock begins counting upwards when the PTEN bit is set. cycle. The action taken depends on the Operating When the value in the PTMR register matches the mode of the time base. PTPER register, the PTMR register will be reset on the following input clock edge and the PTEN bit will be Note: If the period register is set to 0x0000, the cleared by the hardware to halt the time base. timer will stop counting, and the interrupt and the special event trigger will not be When the PWM time base is in the Single-Shot mode generated, even if the special event value (PTMOD<1:0> = 01), an interrupt event is generated is also 0x0000. The module will not when a match with the PTPER register occurs, the update the period register if it is already at PTMR register is reset to zero on the following input 0x0000; therefore, the user must disable clock edge, and the PTEN bit is cleared. The postscaler the module in order to update the period selection bits have no effect in this mode of the timer. register. 14.1.3 CONTINUOUS UP/DOWN The PWM time base can be configured for four different COUNTING MODES modes of operation: In the Continuous Up/Down Counting modes, the PWM • Free Running mode time base counts upwards until the value in the PTPER • Single Shot mode register is matched. The timer will begin counting • Continuous Up/Down Count mode downwards on the following input clock edge. The PTDIR bit in the PTCON SFR is read-only and indi- • Continuous Up/Down Count mode with interrupts cates the counting direction The PTDIR bit is set when for double updates the timer counts downwards. These four modes are selected by the PTMOD<1:0> bits in the PTCON SFR. The Up/Down Counting modes In the Up/Down Counting mode (PTMOD<1:0> = 10), an interrupt event is generated each time the value of support center-aligned PWM generation. The Single the PTMR register becomes zero and the PWM time Shot mode allows the PWM module to support pulse base begins to count upwards. The postscaler selec- control of certain Electronically Commutative Motors tion bits may be used in this mode of the timer to reduce (ECMs). the frequency of the interrupt events. The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2011 Microchip Technology Inc. DS70118J-page 83

dsPIC30F2010 14.1.4 DOUBLE UPDATE MODE 14.2 PWM Period In the Double Update mode (PTMOD<1:0> = 11), an PTPER is a 15-bit register and is used to set the count- interrupt event is generated each time the PTMR regis- ing period for the PWM time base. PTPER is a double- ter is equal to zero, as well as each time a period match buffered register. The PTPER buffer contents are occurs. The postscaler selection bits have no effect in loaded into the PTPER register at the following this mode of the timer. instances: The Double Update mode provides two additional func- • Free Running and Single Shot modes: When the tions to the user. First, the control loop bandwidth is PTMR register is reset to zero after a match with doubled because the PWM duty cycles can be the PTPER register. updated, twice per period. Second, asymmetrical cen- • Up/Down Counting modes: When the PTMR ter-aligned PWM waveforms can be generated, which register is zero. are useful for minimizing output waveform distortion in certain motor control applications. The value held in the PTPER buffer is automatically loaded into the PTPER register when the PWM time Note: Programming a value of 0x0001 in the base is disabled (PTEN = 0). period register could generate a continu- The PWM period can be determined using ous interrupt pulse, and hence, must be Equation14-1: avoided. 14.1.5 PWM TIME BASE PRESCALER EQUATION 14-1: PWM PERIOD The input clock to PTMR (FOSC/4), has prescaler options of 1:1, 1:4, 1:16 or 1:64, selected by control bits TPWM =TCY • (PTPER + 1) (cid:129) PTMR Prescale Value PTCKPS<1:0> in the PTCON SFR. The prescaler counter is cleared when any of the following occurs: • a write to the PTMR register If the PWM time base is configured for one of the Up/ Down Count modes, the PWM period is found using • a write to the PTCON register Equation14-2. • any device Reset The PTMR register is not cleared when PTCON is EQUATION 14-2: PWM PERIOD (UP/DOWN written. COUNT MODE) 14.1.6 PWM TIME BASE POSTSCALER The match output of PTMR can optionally be post- TPWM =TCY (cid:129) 2 (cid:129) (PTPER + 1) (cid:129) PTMR Prescale Value scaled through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling). The maximum resolution (in bits) for a given device The postscaler counter is cleared when any of the oscillator and PWM frequency can be determined using following occurs: Equation14-3: • a write to the PTMR register • a write to the PTCON register EQUATION 14-3: PWM RESOLUTION • any device Reset log (2 (cid:129) TPWM/TCY) The PTMR register is not cleared when PTCON is Resolution = written. log (2) DS70118J-page 84 © 2011 Microchip Technology Inc.

dsPIC30F2010 14.3 Edge-Aligned PWM 14.4 Center-Aligned PWM Edge-aligned PWM signals are produced by the mod- Center-aligned PWM signals are produced by the ule when the PWM time base is in the Free Running or module when the PWM time base is configured in an Single Shot mode. For edge-aligned PWM outputs, the Up/Down Counting mode (see Figure14-3). output has a period specified by the value in PTPER The PWM compare output is driven to the active state and a duty cycle specified by the appropriate duty cycle when the value of the duty cycle register matches the register (see Figure14-2). The PWM output is driven value of PTMR and the PWM time base is counting active at the beginning of the period (PTMR = 0) and is downwards (PTDIR = 1). The PWM compare output is driven inactive when the value in the duty cycle register driven to the inactive state when the PWM time base is matches PTMR. counting upwards (PTDIR = 0) and the value in the If the value in a particular duty cycle register is zero, PTMR register matches the duty cycle value. then the output on the corresponding PWM pin will be If the value in a particular duty cycle register is zero, inactive for the entire PWM period. In addition, the out- then the output on the corresponding PWM pin will be put on the PWM pin will be active for the entire PWM inactive for the entire PWM period. In addition, the out- period if the value in the duty cycle register is greater put on the PWM pin will be active for the entire PWM than the value held in the PTPER register. period if the value in the duty cycle register is equal to the value held in the PTPER register. FIGURE 14-2: EDGE-ALIGNED PWM FIGURE 14-3: CENTER-ALIGNED PWM New Duty Cycle Latched Period/2 PTPER PTPER PTMR PTMR Value Duty Value Cycle 0 0 Duty Cycle Period Period 14.5 PWM Duty Cycle Comparison Units There are four 16-bit Special Function Registers (PDC1, PDC2, PDC3 and PDC4) used to specify duty cycle values for the PWM module. The value in each duty cycle register determines the amount of time that the PWM output is in the active state. The duty cycle registers are 16 bits wide. The LSb of a duty cycle register determines whether the PWM edge occurs in the beginning. Thus, the PWM resolution is effectively doubled. © 2011 Microchip Technology Inc. DS70118J-page 85

dsPIC30F2010 14.5.1 DUTY CYCLE REGISTER BUFFERS 14.7 Dead-Time Generators The four PWM duty cycle registers are double-buffered Dead-time generation may be provided when any of to allow glitchless updates of the PWM outputs. For the PWM I/O pin pairs are operating in the Comple- each duty cycle, there is a duty cycle register that is mentary Output mode. The PWM outputs use Push- accessible by the user and a second duty cycle register Pull drive circuits. Due to the inability of the power out- that holds the actual compare value used in the present put devices to switch instantaneously, some amount of PWM period. time must be provided between the turn off event of one For edge-aligned PWM output, a new duty cycle value PWM output in a complementary pair and the turn on will be updated whenever a match with the PTPER reg- event of the other transistor. ister occurs and PTMR is reset. The contents of the 14.7.1 DEAD-TIME GENERATORS duty cycle buffers are automatically loaded into the duty cycle registers when the PWM time base is dis- Each complementary output pair for the PWM module abled (PTEN = 0) and the UDIS bit is cleared in has a 6-bit down counter that is used to produce the PWMCON2. dead-time insertion. As shown in Figure14-4, the When the PWM time base is in the Up/Down Counting dead-time unit has a rising and falling edge detector mode, new duty cycle values are updated when the connected to the duty cycle comparison output. value of the PTMR register is zero and the PWM time 14.7.2 DEAD-TIME RANGES base begins to count upwards. The contents of the duty cycle buffers are automatically loaded into the duty The amount of dead time provided by the dead-time cycle registers when the PWM time base is disabled unit is selected by specifying the input clock prescaler (PTEN = 0). value and a 6-bit unsigned value. When the PWM time base is in the Up/Down Counting Four input clock prescaler selections have been pro- mode with double updates, new duty cycle values are vided to allow a suitable range of dead times, based on updated when the value of the PTMR register is zero, the device operating frequency. The dead-time clock and when the value of the PTMR register matches the prescaler value is selected using the DTAPS<1:0> and value in the PTPER register. The contents of the duty DTBPS<1:0> control bits in the DTCON1 SFR. One of cycle buffers are automatically loaded into the duty four clock prescaler options (TCY, 2TCY, 4TCY or 8TCY) cycle registers when the PWM time base is disabled is selected for the dead-time value. (PTEN = 0). After the prescaler value is selected, the dead time is adjusted by loading a 6-bit unsigned value into the 14.6 Complementary PWM Operation DTCON1 SFR. In the Complementary mode of operation, each pair of The dead-time unit prescaler is cleared on the following PWM outputs is obtained by a complementary PWM events: signal. A dead time may be optionally inserted during • On a load of the down timer due to a duty cycle device switching, when both outputs are inactive for a comparison edge event. short period (Refer to Section14.7 “Dead-Time • On a write to the DTCON1 register. Generators”). • On any device Reset. In Complementary mode, the duty cycle comparison units are assigned to the PWM outputs as follows: Note: The user should not modify the DTCON1 values while the PWM module is operat- • PDC1 register controls PWM1H/PWM1L outputs ing (PTEN = 1). Unexpected results may • PDC2 register controls PWM2H/PWM2L outputs occur. • PDC3 register controls PWM3H/PWM3L outputs The Complementary mode is selected for each PWM I/O pin pair by clearing the appropriate PMODx bit in the PWMCON1 SFR. The PWM I/O pins are set to Complementary mode by default upon a device Reset. DS70118J-page 86 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 14-4: DEAD-TIME TIMING DIAGRAM Duty Cycle Generator PWMxH PWMxL 14.8 Independent PWM Output 14.10 PWM Output Override An independent PWM Output mode is required for driv- The PWM output override bits allow the user to manu- ing certain types of loads. A particular PWM output pair ally drive the PWM I/O pins to specified logic states, is in the Independent Output mode when the corre- independent of the duty cycle comparison units. sponding PMOD bit in the PWMCON1 register is set. All control bits associated with the PWM output over- No dead-time control is implemented between adjacent ride function are contained in the OVDCON register. PWM I/O pins when the module is operating in the The upper half of the OVDCON register contains six Independent mode and both I/O pins are allowed to be bits, POVDxH<3:1> and POVDxL<3:1>, that determine active simultaneously. which PWM I/O pins will be overridden. The lower half In the Independent mode, each duty cycle generator is of the OVDCON register contains six bits, connected to both of the PWM I/O pins in an output POUTxH<3:1> and POUTxL<3:1>, that determine the pair. By using the associated duty cycle register and state of the PWM I/O pins when a particular output is the appropriate bits in the OVDCON register, the user overridden via the POVD bits. may select the following signal output options for each PWM I/O pin operating in the Independent mode: 14.10.1 COMPLEMENTARY OUTPUT MODE • I/O pin outputs PWM signal When a PWMxL pin is driven active via the OVDCON register, the output signal is forced to be the comple- • I/O pin inactive ment of the corresponding PWMxH pin in the pair. • I/O pin active Dead-time insertion is still performed when PWM channels are overridden manually. 14.9 Single Pulse PWM Operation 14.10.2 OVERRIDE SYNCHRONIZATION The PWM module produces single pulse outputs when the PTCON control bits PTMOD<1:0> = 10. Only edge- If the OSYNC bit in the PWMCON2 register is set, all aligned outputs may be produced in the Single Pulse output overrides performed via the OVDCON register mode. In Single Pulse mode, the PWM I/O pin(s) are are synchronized to the PWM time base. Synchronous driven to the active state when the PTEN bit is set. output overrides occur at the following times: When a match with a duty cycle register occurs, the • Edge-Aligned mode, when PTMR is zero. PWM I/O pin is driven to the inactive state. When a • Center-Aligned modes, when PTMR is zero and match with the PTPER register occurs, the PTMR reg- when the value of PTMR matches PTPER. ister is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared, and an interrupt is generated. © 2011 Microchip Technology Inc. DS70118J-page 87

dsPIC30F2010 14.11 PWM Output and Polarity Control 14.12.2 FAULT STATES There are three device Configuration bits associated The FLTACON special function register has eight bits with the PWM module that provide PWM output pin that determine the state of each PWM I/O pin when it is control: overridden by a FLTA input. When these bits are cleared, the PWM I/O pin is driven to the inactive state. • HPOL Configuration bit If the bit is set, the PWM I/O pin will be driven to the • LPOL Configuration bit active state. The active and inactive states are refer- • PWMPIN Configuration bit enced to the polarity defined for each PWM I/O pin (HPOL and LPOL polarity control bits). These three bits in the FBORPOR Configuration regis- ter (see Section19.6 “Device Configuration Regis- 14.12.3 FAULT INPUT MODES ters”) work in conjunction with the three PWM enable bits (PWMEN<3:1>) located in the PWMCON1 SFR. The FLTA input pin has two modes of operation: The Configuration bits and PWM enable bits ensure • Latched Mode: When the FLTA pin is driven low, that the PWM pins are in the correct states after a the PWM outputs will go to the states defined in device Reset occurs. The PWMPIN configuration fuse the FLTACON register. The PWM outputs will allows the PWM module outputs to be optionally remain in this state until the FLTA pin is driven enabled on a device Reset. If PWMPIN = 0, the PWM high and the corresponding interrupt flag has outputs will be driven to their inactive states at Reset. If been cleared in software. When both of these PWMPIN = 1 (default), the PWM outputs will be tri- actions have occurred, the PWM outputs will stated. The HPOL bit specifies the polarity for the return to normal operation at the beginning of the PWMxH outputs, whereas the LPOL bit specifies the next PWM cycle or half-cycle boundary. If the polarity for the PWMxL outputs. interrupt flag is cleared before the FLTA condition ends, the PWM module will wait until the FLTA pin 14.11.1 OUTPUT PIN CONTROL is no longer asserted to restore the outputs. The PENxH and PENxL control bits in the PWMCON1 • Cycle-by-Cycle Mode: When the FLTA input pin SFR enable each high PWM output pin and each low is driven low, the PWM outputs remain in the PWM output pin, respectively. If a particular PWM out- defined FLTA states for as long as the FLTA pin is put pin not enabled, it is treated as a general purpose held low. After the FLTA pin is driven high, the I/O pin. PWM outputs return to normal operation at the beginning of the following PWM cycle or 14.12 PWM FLTA Pin half-cycle boundary. There is one Fault input pin (FLTA) associated with the The Operating mode for the FLTA input pin is selected PWM module. When asserted, this pin can optionally using the FLTAM control bit in the FLTACON Special drive each of the PWM I/O pins to a defined state. Function Register. The FLTA pin can be controlled manually in software. 14.12.1 FAULT PIN ENABLE BITS The FLTACON SFR has 4 control bits that determine 14.13 PWM Update Lockout whether a particular pair of PWM I/O pins is to be con- For a complex PWM application, the user may need to trolled by the FLTA input pin. To enable a specific PWM write up to four duty cycle registers and the time base I/O pin pair for FLTA overrides, the corresponding bit period register, PTPER, at a given time. In some appli- should be set in the FLTACON register. cations, it is important that all buffer registers be written If all enable bits are cleared in the FLTACON register, before the new duty cycle and period values are loaded then the FLTA input pin has no effect on the PWM for use by the module. module and the pin may be used as a general purpose The PWM update lockout feature is enabled by setting interrupt or I/O pin. the UDIS control bit in the PWMCON2 SFR. The UDIS Note: The FLTA pin logic can operate indepen- bit affects all duty cycle buffer registers and the PWM dent of the PWM logic. If all the enable bits time base period buffer, PTPER. No duty cycle in the FLTACON register are cleared, then changes or period value changes will have effect while the FLTA pin could be used as a general UDIS = 1. purpose interrupt pin. The FLTA pin has an interrupt vector, interrupt flag bit and interrupt priority bits associated with it. DS70118J-page 88 © 2011 Microchip Technology Inc.

dsPIC30F2010 14.14 PWM Special Event Trigger 14.15 PWM Operation During CPU Sleep Mode The PWM module has a special event trigger that allows A/D conversions to be synchronized to the PWM The FLTA input pin has the ability to wake the CPU time base. The A/D sampling and conversion time may from Sleep mode. The PWM module generates an be programmed to occur at any point within the PWM interrupt if the FLTA pin is driven low while in Sleep. period. The special event trigger allows the user to min- imize the delay between the time when A/D conversion 14.16 PWM Operation During CPU Idle results are acquired, and the time when the duty cycle Mode value is updated. The PWM special event trigger has an SFR named The PTCON SFR contains a PTSIDL control bit. This SEVTCMP, and five control bits to control its operation. bit determines if the PWM module will continue to The PTMR value for which a special event trigger operate or stop when the device enters Idle mode. If should occur is loaded into the SEVTCMP register. PTSIDL = 0, the module will continue to operate. If When the PWM time base is in an Up/Down Counting PTSIDL = 1, the module will stop operation as long as mode, an additional control bit is required to specify the the CPU remains in Idle mode. counting phase for the special event trigger. The count phase is selected using the SEVTDIR control bit in the SEVTCMP SFR. If the SEVTDIR bit is cleared, the spe- cial event trigger will occur on the upward counting cycle of the PWM time base. If the SEVTDIR bit is set, the special event trigger will occur on the downward count cycle of the PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down Counting mode. 14.14.1 SPECIAL EVENT TRIGGER POSTSCALER The PWM special event trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler is configured by writing the SEVOPS<3:0> control bits in the PWMCON2 SFR. The special event output postscaler is cleared on the following events: • Any write to the SEVTCMP register • Any device Reset © 2011 Microchip Technology Inc. DS70118J-page 89

D TABLE 14-1: PWM REGISTER MAP d S 70 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 1 18 PTCON 01C0 PTEN — PTSIDL — — — — — PTOPS<3:0> PTCKPS<1:0> PTMOD<1:0> 0000 0000 0000 0000 P J -p PTMR 01C2 PTDIR PWM Timer Count Value 0000 0000 0000 0000 I age PTPER 01C4 — PWM Time Base Period Register 0011 1111 1111 1111 C 90 SEVTCMP 01C6 SEVTDIR PWM Special Event Compare Register 0000 0000 0000 0000 3 PWMCON1 01C8 — — — — — PTMOD3 PTMOD2 PTMOD1 — PEN3H PEN2H PEN1H — PEN3L PEN2L PEN1L 0000 0000 0111 0111 0 PWMCON2 01CA — — — — SEVOPS<3:0> — — — — — IUE OSYNC UDIS 0000 0000 0000 0000 F DTCON1 01CC DTBPS<1:0> DTB<5:0> DTAPS<1:0> Dead Time A Value 0000 0000 0000 0000 2 FLTACON 01D0 — — FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM — — — — FAEN3 FAEN2 FAEN1 0000 0000 0000 0000 0 OVDCON 01D4 — — POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L — — POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 0011 1111 0000 0000 1 PDC1 01D6 PWM Duty Cycle 1 Register 0000 0000 0000 0000 0 PDC2 01D8 PWM Duty Cycle 2 Register 0000 0000 0000 0000 PDC3 01DA PWM Duty Cycle 3 Register 0000 0000 0000 0000 Legend: — = unimplemented bit, read as ‘0’ Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F2010 15.0 SPI MODULE Transmit writes are also double-buffered. The user writes to SPIxBUF. When the master or slave transfer Note: This data sheet summarizes features of is completed, the contents of the shift register this group ofdsPIC30F devices and is not (SPIxSR) is moved to the receive buffer. If any trans- intended to be a complete reference mit data has been written to the buffer register, the source. For more information on the CPU, contents of the transmit buffer are moved to SPIxSR. peripherals, register descriptions and The received data is thus placed in SPIxBUF and the general device functionality, refer to the transmit data in SPIxSR is ready for the next transfer. “dsPIC30F Family Reference Manual” Note: Both the transmit buffer (SPIxTXB) and (DS70046). the receive buffer (SPIxRXB) are mapped The Serial Peripheral Interface (SPI) module is a syn- to the same register address, SPIxBUF. chronous serial interface. It is useful for communicating In Master mode, the clock is generated by prescaling with other peripheral devices such as EEPROMs, shift the system clock. Data is transmitted as soon as a registers, display drivers and A/D converters or other value is written to SPIxBUF. The interrupt is generated microcontrollers. It is compatible with Motorola's SPI at the middle of the transfer of the last bit. and SIOP interfaces. In Slave mode, data is transmitted and received as 15.1 Operating Function Description external clock pulses appear on SCK. Again, the inter- rupt is generated when the last bit is latched. If SSx Each SPI module consists of a 16-bit shift register, control is enabled, then transmission and reception SPIxSR (where x = 1 or 2), used for shifting data in are enabled only when SSx = low. The SDOx output and out, and a buffer register, SPIxBUF. A control reg- will be disabled in SSx mode with SSx high. ister, SPIxCON, configures the module. Additionally, a status register, SPIxSTAT, indicates various status The clock provided to the module is (FOSC/4). This clock is then prescaled by the primary (PPRE<1:0>) conditions. and the secondary (SPRE<2:0>) prescale factors. The The serial interface consists of 4 pins: SDIx (serial CKE bit determines whether transmit occurs on transi- data input), SDOx (serial data output), SCKx (shift tion from active clock state to Idle clock state, or vice clock input or output) and SSx (active-low slave versa. The CKP bit selects the Idle state (high or low) select). for the clock. In Master mode operation, SCK is a clock output, but 15.1.1 WORD AND BYTE in Slave mode, it is a clock input. COMMUNICATION A series of eight (8) or sixteen (16) clock pulses shifts out bits from the SPIxSR to SDOx pin and simultane- A control bit, MODE16 (SPIxCON<10>), allows the ously shifts in data from SDIx pin. An interrupt is gen- module to communicate in either 16-bit or 8-bit mode. erated when the transfer is complete and the 16-bit operation is identical to 8-bit operation, except corresponding interrupt flag bit (SPI1IF or SPI2IF) is that the number of bits transmitted is 16 instead of 8. set. This interrupt can be disabled through an interrupt The user software must disable the module prior to enable bit (SPI1IE or SPI2IE). changing the MODE16 bit. The SPI module is reset The receive operation is double-buffered. When a when the MODE16 bit is changed by the user. complete byte is received, it is transferred from A basic difference between 8-bit and 16-bit operation is SPIxSR to SPIxBUF. that the data is transmitted out of bit 7 of the SPIxSR for If the receive buffer is full when new data is being 8-bit operation, and data is transmitted out of bit 15 of transferred from SPIxSR to SPIxBUF, the module will the SPIxSR for 16-bit operation. In both modes, data is set the SPIROV bit, indicating an overflow condition. shifted into bit 0 of the SPIxSR. The transfer of the data from SPIxSR to SPIxBUF will 15.1.2 SDOx DISABLE not be completed and the new data will be lost. The module will not respond to SCL transitions while SPI- A control bit, DISSDO, is provided to the SPIxCON reg- ROV is ‘1’, effectively disabling the module until SPIx- ister to allow the SDOx output to be disabled. This will BUF is read by user software. allow the SPI module to be connected in an input only configuration. SDO can also be used for general purpose I/O. © 2011 Microchip Technology Inc. DS70118J-page 91

dsPIC30F2010 15.2 Framed SPI Support pin is an input or an output (i.e., whether the module receives or generates the frame synchronization The module supports a basic framed SPI protocol in pulse). The frame pulse is an active-high pulse for a Master or Slave mode. The control bit FRMEN enables single SPI clock cycle. When frame synchronization is framed SPI support and causes the SSx pin to perform enabled, the data transmission starts only on the the frame synchronization pulse (FSYNC) function. subsequent transmit edge of the SPI clock. The control bit SPIFSD determines whether the SSx FIGURE 15-1: SPI BLOCK DIAGRAM Internal Data Bus Read Write SPIxBUF SPIxBUF Receive Transmit SPIxSR SDIx bit 0 SDOx Shift clock SS and FSYNC Clock Edge Control Control Select SSx Primary Secondary Prescaler Prescaler FCY 1:1-1:8 1:1, 1:4, SCKx 1:16, 1:64 Enable Master Clock Note: x = 1 or 2. FIGURE 15-2: SPI MASTER/SLAVE CONNECTION SPI Master SPI Slave SDOx SDIy Serial Input Buffer Serial Input Buffer (SPIxBUF) (SPIyBUF) SDIx SDOy Shift Register Shift Register (SPIxSR) (SPIySR) MSb LSb MSb LSb Serial Clock SCKx SCKy PROCESSOR 1 PROCESSOR 2 Note: x = 1 or 2, y = 1 or 2. DS70118J-page 92 © 2011 Microchip Technology Inc.

dsPIC30F2010 15.3 Slave Select Synchronization 15.4 SPI Operation During CPU Sleep Mode The SSx pin allows a Synchronous Slave mode. The SPI must be configured in SPI Slave mode, with SSx During Sleep mode, the SPI module is shut down. If pin control enabled (SSEN = 1). When the SSx pin is the CPU enters Sleep mode while an SPI transaction low, transmission and reception are enabled, and the is in progress, then the transmission and reception is SDOx pin is driven. When SSx pin goes high, the SDOx aborted. pin is no longer driven. Also, the SPI module is re- The transmitter and receiver will stop in Sleep mode. synchronized, and all counters/control circuitry are However, register contents are not affected by reset. Therefore, when the SSx pin is asserted low entering or exiting Sleep mode. again, transmission/reception will begin at the MSb, even if SSx had been de-asserted in the middle of a 15.5 SPI Operation During CPU Idle transmit/receive. Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT<13>) selects if the SPI module will stop or continue on Idle. If SPISIDL = 0, the module will continue to operate when the CPU enters Idle mode. If SPISIDL = 1, the module will stop when the CPU enters Idle mode. © 2011 Microchip Technology Inc. DS70118J-page 93

D TABLE 15-1: SPI1 REGISTER MAP d S 701 NSaFmRe Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 1 P 8 J SPI1STAT 0220 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 0000 0000 0000 -p I ag SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 0000 0000 0000 C e 94 SLePgI1eBnUdF: 0—22 =4 unimplemented bit, read as ‘0’ Transmit and Receive Buffer 0000 0000 0000 0000 3 0 Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. F 2 0 1 0 © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F2010 16.0 I2C™ MODULE 16.1.1 VARIOUS I2C MODES The following types of I2C operation are supported: Note: This data sheet summarizes features of this group ofdsPIC30F devices and is not • I2C Slave operation with 7-bit addressing intended to be a complete reference • I2C Slave operation with 10-bit addressing source. For more information on the CPU, • I2C Master operation with 7-bit or 10-bit addressing peripherals, register descriptions and See the I2C programmer’s model in Figure16-1. general device functionality, refer to the “dsPIC30F Family Reference Manual” 16.1.2 PIN CONFIGURATION IN I2C MODE (DS70046). I2C has a 2-pin interface: pin SCL is clock and pin SDA The Inter-Integrated Circuit (I2C™) module provides is data. complete hardware support for both Slave and Multi- Master modes of the I2C serial communication 16.1.3 I2C REGISTERS standard, with a 16-bit interface. I2CCON and I2CSTAT are control and status registers, This module offers the following key features: respectively. The I2CCON register is readable and writ- • I2C interface supporting both Master and Slave able. The lower 6 bits of I2CSTAT are read-only. The remaining bits of the I2CSTAT are read/write. operation • I2C Slave mode supports 7-bit and 10-bit I2CRSR is the shift register used for shifting data, addressing whereas I2CRCV is the buffer register to which data • I2C Master mode supports 7-bit and 10-bit bytes are written, or from which data bytes are read. I2CRCV is the receive buffer, as shown in Figure16-1. addressing I2CTRN is the transmit register to which bytes are • I2C port allows bidirectional transfers between written during a transmit operation, as shown in master and slaves Figure16-2. • Serial clock synchronization for I2C port can be The I2CADD register holds the slave address. A status used as a handshake mechanism to suspend and bit, ADD10, indicates 10-bit Address mode. The resume serial transfer (SCLREL control) I2CBRG acts as the Baud Rate Generator (BRG) • I2C supports Multi-Master operation; detects bus reload value. collision and will arbitrate accordingly In receive operations, I2CRSR and I2CRCV together 16.1 Operating Function Description form a double-buffered receiver. When I2CRSR receives a complete byte, it is transferred to I2CRCV The hardware fully implements all the master and slave and an interrupt pulse is generated. During functions of the I2C Standard and Fast mode transmission, the I2CTRN is not double-buffered. specifications, as well as 7- and 10-bit addressing. Note: Following a Restart condition in 10-bit Thus, the I2C module can operate either as a slave or mode, the user only needs to match the a master on an I2C bus. first 7-bit address. FIGURE 16-1: PROGRAMMER’S MODEL I2CRCV (8 bits) bit 7 bit 0 I2CTRN (8 bits) bit 7 bit 0 I2CBRG (9 bits) bit 8 bit 0 I2CCON (16 bits) bit 15 bit 0 I2CSTAT (16 bits) bit 15 bit 0 I2CADD (10 bits) bit 9 bit 0 © 2011 Microchip Technology Inc. DS70118J-page 95

dsPIC30F2010 FIGURE 16-2: I2C™ BLOCK DIAGRAM Internal Data Bus I2CRCV Read Shift SCL Clock I2CRSR LSB SDA Addr_Match Match Detect Write I2CADD Read Start and Stop bit Detect Write T Start, Restart, A Stop bit Generate ST C I2 Read c gi o L Collision ol Detect ntr o Write C N O C C Acknowledge 2 I Read Generation Clock Stretching Write I2CTRN LSB Shift Read Clock Reload Control Write I2CBRG BRG Down Counter Read FCY DS70118J-page 96 © 2011 Microchip Technology Inc.

dsPIC30F2010 16.2 I2C Module Addresses 16.3.2 SLAVE RECEPTION The I2CADD register contains the Slave mode If the R_W bit received is a ‘0’ during an address addresses. The register is a 10-bit register. match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL. After 8 bits are If the A10M bit (I2CCON<10>) is ‘0’, the address is received, if I2CRCV is not full or I2COV is not set, interpreted by the module as a 7-bit address. When an I2CRSR is transferred to I2CRCV. ACK is sent on the address is received, it is compared to the 7 LSbs of the ninth clock. I2CADD register. If the RBF flag is set, indicating that I2CRCV is still If the A10M bit is ‘1’, the address is assumed to be a holding data from a previous operation (RBF = 1), then 10-bit address. When an address is received, it will be ACK is not sent; however, the interrupt pulse is gener- compared with the binary value ‘1 1 1 1 0 A9 A8’ ated. In the case of an overflow, the contents of the (where A9, A8 are two Most Significant bits of I2CRSR are not loaded into the I2CRCV. I2CADD). If that value matches, the next address will be compared with the Least Significant 8 bits of Note: The I2CRCV will be loaded if the I2COV I2CADD, as specified in the 10-bit addressing protocol. bit = 1 and the RBF flag = 0. In this case, a read of the I2CRCV was performed, but 2 the user did not clear the state of the TABLE 16-1: 7-BIT I C™ SLAVE I2COV bit before the next receive ADDRESSES SUPPORTED BY occurred. The acknowledgement is not dsPIC30F sent (ACK = 1) and the I2CRCV is Address updated. Description Address Range 0x00 General call address or Start byte 16.4 I2C 10-bit Slave Mode Operation 0x01-0x03 Reserved In 10-bit mode, the basic receive and transmit opera- 0x04-0x07 Hs mode master codes tions are the same as in the 7-bit mode. However, the criteria for address match is more complex. 0x08-0x77 Valid 7-bit addresses The I2C specification dictates that a slave must be 0x78-0x7B Valid 10-bit addresses (lower 7 bits) addressed for a write operation, with two address bytes 0x7C-0x7F Reserved following a Start bit. The A10M bit is a control bit that signifies that the 16.3 I2C 7-bit Slave Mode Operation address in I2CADD is a 10-bit address rather than a 7-bit address. The address detection protocol for the Once enabled (I2CEN = 1), the slave module will wait for a Start bit to occur (i.e., the I2C module is ‘Idle’). first byte of a message address is identical for 7-bit and 10-bit messages, but the bits being compared are Following the detection of a Start bit, 8 bits are shifted different. into I2CRSR and the address is compared against I2CADD. In 7-bit mode (A10M = 0), bits I2CADD<6:0> I2CADD holds the entire 10-bit address. Upon receiv- are compared against I2CRSR<7:1> and I2CRSR<0> ing an address following a Start bit, I2CRSR <7:3> is is the R_W bit. All incoming bits are sampled on the compared against a literal ‘11110’ (the default 10-bit rising edge of SCL. address) and I2CRSR<2:1> are compared against I2CADD<9:8>. If a match occurs and if R_W = 0, the If an address match occurs, an acknowledgement will interrupt pulse is sent. The ADD10 bit will be cleared to be sent, and the slave event interrupt flag (SI2CIF) is indicate a partial address match. If a match fails or set on the falling edge of the ninth (ACK) bit. The R_W = 1, the ADD10 bit is cleared and the module address match does not affect the contents of the returns to the Idle state. I2CRCV buffer or the RBF bit. The low byte of the address is then received and com- 16.3.1 SLAVE TRANSMISSION pared with I2CADD<7:0>. If an address match occurs, the interrupt pulse is generated and the ADD10 bit is If the R_W bit received is a ‘1’, then the serial port will set, indicating a complete 10-bit address match. If an go into Transmit mode. It will send ACK on the ninth bit address match did not occur, the ADD10 bit is cleared and then hold SCL to ‘0’ until the CPU responds by writ- and the module returns to the Idle state. ing to I2CTRN. SCL is released by setting the SCLREL bit, and 8 bits of data are shifted out. Data bits are 16.4.1 10-BIT MODE SLAVE shifted out on the falling edge of SCL, such that SDA is TRANSMISSION valid during SCL high (see timing diagram). The inter- rupt pulse is sent on the falling edge of the ninth clock Once a slave is addressed in this fashion, with the full 10- pulse, regardless of the status of the ACK received bit address (we will refer to this state as from the master. “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation. © 2011 Microchip Technology Inc. DS70118J-page 97

dsPIC30F2010 16.4.2 10-BIT MODE SLAVE RECEPTION holding the SCL line low, the user has time to service the ISR and read the contents of the I2CRCV before the Once addressed, the master can generate a Repeated master device can initiate another receive sequence. Start, reset the high byte of the address and set the This will prevent buffer overruns from occurring. R_W bit without generating a Stop bit, thus initiating a slave transmit operation. Note1: If the user reads the contents of the I2CRCV, clearing the RBF bit before the 16.5 Automatic Clock Stretch falling edge of the ninth clock, the SCLREL bit will not be cleared and clock In the Slave modes, the module can synchronize buffer stretching will not occur. reads and write to the master device by clock stretching. 2: The SCLREL bit can be set in software, regardless of the state of the RBF bit. The 16.5.1 TRANSMIT CLOCK STRETCHING user should be careful to clear the RBF Both 10-bit and 7-bit Transmit modes implement clock bit in the ISR before the next receive stretching by asserting the SCLREL bit after the falling sequence in order to prevent an overflow edge of the ninth clock if the TBF bit is cleared, indicat- condition. ing the buffer is empty. 16.5.4 CLOCK STRETCHING DURING In Slave Transmit modes, clock stretching is always 10-BIT ADDRESSING (STREN = 1) performed, irrespective of the STREN bit. Clock stretching takes place automatically during the Clock synchronization takes place following the ninth addressing sequence. Because this module has a clock of the transmit sequence. If the device samples register for the entire address, it is not necessary for an ACK on the falling edge of the ninth clock, and if the the protocol to wait for the address to be updated. TBF bit is still clear, then the SCLREL bit is automati- cally cleared. The SCLREL being cleared to ‘0’ will After the address phase is complete, clock stretching assert the SCL line low. The user’s ISR must set the will occur on each data receive or transmit sequence SCLREL bit before transmission is allowed to con- as was described earlier. tinue. By holding the SCL line low, the user has time to service the ISR and load the contents of the I2CTRN 16.6 Software Controlled Clock before the master device can initiate another transmit Stretching (STREN = 1) sequence. When the STREN bit is ‘1’, the SCLREL bit may be Note1: If the user loads the contents of I2CTRN, cleared by software to allow software to control the setting the TBF bit before the falling edge clock stretching. The logic will synchronize writes to of the ninth clock, the SCLREL bit will not the SCLREL bit with the SCL clock. Clearing the be cleared and clock stretching will not SCLREL bit will not assert the SCL output until the occur. module detects a falling edge on the SCL output and 2: The SCLREL bit can be set in software, SCL is sampled low. If the SCLREL bit is cleared by regardless of the state of the TBF bit. the user while the SCL line has been sampled low, the SCL output will be asserted (held low). The SCL out- 16.5.2 RECEIVE CLOCK STRETCHING put will remain low until the SCLREL bit is set, and all other devices on the I2C bus have de-asserted SCL. The STREN bit in the I2CCON register can be used to This ensures that a write to the SCLREL bit will not enable clock stretching in Slave Receive mode. When violate the minimum high time requirement for SCL. the STREN bit is set, the SCL pin will be held low at the end of each data receive sequence. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the 16.5.3 CLOCK STRETCHING DURING SCLREL bit. 7-BIT ADDRESSING (STREN = 1) 16.7 Interrupts When the STREN bit is set in Slave Receive mode, the SCL line is held low when the buffer register is full. The I2C module generates two interrupt flags, MI2CIF The method for stretching the SCL output is the same (I2C Master Interrupt Flag) and SI2CIF (I2C Slave Inter- for both 7 and 10-bit Addressing modes. rupt Flag). The MI2CIF interrupt flag is activated on Clock stretching takes place following the ninth clock of completion of a master message event. The SI2CIF the receive sequence. On the falling edge of the ninth interrupt flag is activated on detection of a message clock at the end of the ACK sequence, if the RBF bit is directed to the slave. set, the SCLREL bit is automatically cleared, forcing the SCL output to be held low. The user’s ISR must set the SCLREL bit before reception is allowed to continue. By DS70118J-page 98 © 2011 Microchip Technology Inc.

dsPIC30F2010 16.8 Slope Control In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The The I2C standard requires slope control on the SDA first byte transmitted contains the slave address of the and SCL signals for Fast Mode (400 kHz). The control receiving device (7 bits) and the data direction bit. In bit, DISSLW, enables the user to disable slew rate con- this case, the data direction bit (R_W) is logic ‘0’. Serial trol, if desired. It is necessary to disable the slew rate data is transmitted 8 bits at a time. After each byte is control for 1 MHz mode. transmitted, an ACK bit is received. Start and Stop con- ditions are output to indicate the beginning and the end 16.9 IPMI Support of a serial transfer. The control bit IPMIEN enables the module to support In Master Receive mode, the first byte transmitted con- Intelligent Peripheral Management Interface (IPMI). tains the slave address of the transmitting device (7 When this bit is set, the module accepts and acts upon bits) and the data direction bit. In this case, the data all addresses. direction bit (R_W) is logic ‘1’. Thus, the first byte trans- mitted is a 7-bit slave address, followed by a ‘1’ to indi- 16.10 General Call Address Support cate receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received 8 The general call address can address all devices. bits at a time. After each byte is received, an ACK bit is When this address is used, all devices should, in transmitted. Start and Stop conditions indicate the theory, respond with an acknowledgement. beginning and end of transmission. The general call address is one of eight addresses 16.12.1 I2C MASTER TRANSMISSION reserved for specific purposes by the I2C protocol. It consists of all 0s with R_W = 0. Transmission of a data byte, a 7-bit address or the sec- ond half of a 10-bit address is accomplished by simply The general call address is recognized when the Gen- writing a value to I2CTRN register. The user should eral Call Enable (GCEN) bit is set (I2CCON<15> = 1). only write to I2CTRN when the module is in a Wait Following a Start bit detection, 8 bits are shifted into state. This action will set the buffer full flag (TBF) and I2CRSR and the address is compared with I2CADD, allow the Baud Rate Generator to begin counting and and is also compared with the general call address start the next transmission. Each bit of address/data which is fixed in hardware. will be shifted out onto the SDA pin after the falling If a general call address match occurs, the I2CRSR is edge of SCL is asserted. The Transmit Status Flag, transferred to the I2CRCV after the eighth clock, the TRSTAT (I2CSTAT<14>), indicates that a master RBF flag is set, and on the falling edge of the ninth bit transmit is in progress. (ACK bit), the master event interrupt flag (MI2CIF) is set. 16.12.2 I2C MASTER RECEPTION When the interrupt is serviced, the source for the inter- Master mode reception is enabled by programming the rupt can be checked by reading the contents of the receive enable (RCEN) bit (I2CCON<11>). The I2C I2CRCV to determine if the address was device module must be Idle before the RCEN bit is set, other- specific, or a general call address. wise the RCEN bit will be disregarded. The Baud Rate Generator begins counting, and on each rollover, the 16.11 I2C Master Support state of the SCL pin toggles, and data is shifted in to the I2CRSR on the rising edge of each clock. As a Master device, six operations are supported. 16.12.3 BAUD RATE GENERATOR • Assert a Start condition on SDA and SCL. • Assert a Restart condition on SDA and SCL. In I2C Master mode, the reload value for the BRG is • Write to the I2CTRN register initiating located in the I2CBRG register. When the BRG is transmission of data/address. loaded with this value, the BRG counts down to ‘0’ and • Generate a Stop condition on SDA and SCL. stops until another reload has taken place. If clock • Configure the I2C port to receive data. arbitration is taking place, for instance, the BRG is • Generate an ACK condition at the end of a reloaded when the SCL pin is sampled high. received byte of data. As per the I2C standard, FSCK may be 100 kHz or 400kHz. However, the user can specify any baud rate 16.12 I2C Master Operation up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is EQUATION 16-1: I2CBRG VALUE ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also ⎛FCY FCY ⎞ the beginning of the next serial transfer, the I2C bus will I2CBRG = ⎝F-----S--C----L--–1---,-----1---1---1---,-----1---1---1--⎠ –1 not be released. © 2011 Microchip Technology Inc. DS70118J-page 99

dsPIC30F2010 16.12.4 CLOCK ARBITRATION 16.13 I2C Module Operation During CPU Sleep and Idle Modes Clock arbitration occurs when the master de-asserts the SCL pin (SCL allowed to float high) during any 16.13.1 I2C OPERATION DURING CPU receive, transmit or Restart/Stop condition. When the SCL pin is allowed to float high, the Baud Rate SLEEP MODE Generator is suspended from counting until the SCL When the device enters Sleep mode, all clock sources pin is actually sampled high. When the SCL pin is to the module are shutdown and stay at logic ‘0’. If sampled high, the Baud Rate Generator is reloaded Sleep occurs in the middle of a transmission, and the with the contents of I2CBRG and begins counting. This state machine is partially into a transmission as the ensures that the SCL high time will always be at least clocks stop, then the transmission is aborted. Similarly, one BRG rollover count in the event that the clock is if Sleep occurs in the middle of a reception, then the held low by an external device. reception is aborted. 16.12.5 MULTI-MASTER COMMUNICATION, 16.13.2 I2C OPERATION DURING CPU IDLE BUS COLLISION AND BUS MODE ARBITRATION For the I2C, the I2CSIDL bit selects if the module will Multi-Master operation support is achieved by bus stop on Idle or continue on Idle. If I2CSIDL = 0, the arbitration. When the master outputs address/data bits module will continue operation on assertion of the Idle onto the SDA pin, arbitration takes place when the mode. If I2CSIDL = 1, the module will stop on Idle. master outputs a ‘1’ on SDA, by letting SDA float high while another master asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin=0, then a bus collision has taken place. The master will set the MI2CIF pulse and reset the master portion of the I2C port to its Idle state. If a transmit was in progress when the bus collision occurred, the transmission is halted, the TBF flag is cleared, the SDA and SCL lines are de-asserted, and a value can now be written to I2CTRN. When the user services the I2C master event Interrupt Service Routine, if the I2C bus is free (i.e., the P bit is set) the user can resume communication by asserting a Start condition. If a Start, Restart, Stop or Acknowledge condition was in progress when the bus collision occurred, the condi- tion is aborted, the SDA and SCL lines are de-asserted, and the respective control bits in the I2CCON register are cleared to ‘0’. When the user services the bus col- lision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a Start condition. The Master will continue to monitor the SDA and SCL pins, and if a Stop condition occurs, the MI2CIF bit will be set. A write to the I2CTRN will start the transmission of data at the first data bit, regardless of where the transmitter left off when bus collision occurred. In a Multi-Master environment, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the I2CSTAT register, or the bus is Idle and the S and P bits are cleared. DS70118J-page 100 © 2011 Microchip Technology Inc.

© TABLE 16-2: I2C™ REGISTER MAP 2 0 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 1 M I2CRCV 0200 — — — — — — — — Receive Register 0000 0000 0000 0000 ic I2CTRN 0202 — — — — — — — — Transmit Register 0000 0000 1111 1111 ro ch I2CBRG 0204 — — — — — — — Baud Rate Generator 0000 0000 0000 0000 ip T I2CCON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0001 0000 0000 0000 ec I2CSTAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 0000 0000 0000 h no I2CADD 020A — — — — — — Address Register 0000 0000 0000 0000 log Legend: — = unimplemented bit, read as ‘0’ y In Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. c . d s P I C 3 D 0 S 7 F 0 1 1 2 8 J -p 0 a g 1 e 1 0 0 1

dsPIC30F2010 NOTES: DS70118J-page 102 © 2011 Microchip Technology Inc.

dsPIC30F2010 17.0 UNIVERSAL ASYNCHRONOUS 17.1 UART Module Overview RECEIVER TRANSMITTER The key features of the UART module are: (UART) MODULE • Full-duplex, 8- or 9-bit data communication Note: This data sheet summarizes features of • Even, Odd or No Parity options (for 8-bit data) this group ofdsPIC30F devices and is not • One or two Stop bits intended to be a complete reference • Fully integrated Baud Rate Generator with 16-bit source. For more information on the CPU, prescaler peripherals, register descriptions and • Baud rates range from 38 bps to 1.875 Mbps at a general device functionality, refer to the 30 MHz instruction rate “dsPIC30F Family Reference Manual” • 4-word deep transmit data buffer (DS70046). • 4-word deep receive data buffer This section describes the Universal Asynchronous • Parity, Framing and Buffer Overrun error detection Receiver/Transmitter Communications module. • Support for Interrupt only on Address Detect Note: Since dsPIC30F2010 devices have only (9th bit = 1) one UART, all references to Ux... imply • Separate Transmit and Receive Interrupts that x=1 only. • Loopback mode for diagnostic support FIGURE 17-1: UART TRANSMITTER BLOCK DIAGRAM Internal Data Bus Control and Status bits Write Write UTX8 UxTXREG Low Byte Transmit Control – Control TSR – Control Buffer – Generate Flags – Generate Interrupt Load TSR UxTXIF UTXBRK Data Transmit Shift Register (UxTSR) ‘0’ (Start) UxTX ‘1’ (Stop) Parity GePnaerritaytor 16 Divider 1fr6oXm B Baauudd C Rloactek Generator Control Signals Note: x = 1 only. © 2011 Microchip Technology Inc. DS70118J-page 103

dsPIC30F2010 FIGURE 17-2: UART RECEIVER BLOCK DIAGRAM Internal Data Bus 16 Read Write ReadRead Write UxMODE UxSTA URX8 UxRXREG Low Byte Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters LPBACK 8-9 From UxTX 1 Load RSR to Buffer Control R R UxRX 0 Receiv(eU SxRhiSft RR)egister Signals PER FER · Start bit Detect · Parity Check · Stop bit Detect 16 Divider · Shift Clock Generation · Wake Logic 16X Baud Clock from Baud Rate Generator UxRXIF Note: x = 1 only. DS70118J-page 104 © 2011 Microchip Technology Inc.

dsPIC30F2010 17.2 Enabling and Setting Up UART 17.3 Transmitting Data 17.2.1 ENABLING THE UART 17.3.1 TRANSMITTING IN 8-BIT DATA MODE The UART module is enabled by setting the UARTEN bit in the UxMODE register (where x = 1 only). Once The following steps must be performed in order to enabled, the UxTX and UxRX pins are configured as an transmit 8-bit data: output and an input respectively, overriding the TRIS 1. Set up the UART: and LATCH register bit settings for the corresponding First, the data length, parity and number of Stop I/O port pins. The UxTX pin is at logic ‘1’ when no bits must be selected. Then, the Transmit and transmission is taking place. Receive Interrupt enable and priority bits are setup in the UxMODE and UxSTA registers. 17.2.2 DISABLING THE UART Also, the appropriate baud rate value must be The UART module is disabled by clearing the written to the UxBRG register. UARTEN bit in the UxMODE register. This is the 2. Enable the UART by setting the UARTEN bit default state after any Reset. If the UART is disabled, (UxMODE<15>). all I/O pins operate as port pins under the control of 3. Set the UTXEN bit (UxSTA<10>), thereby the latch and TRIS bits of the corresponding port pins. enabling a transmission. Disabling the UART module resets the buffers to Note: The UTXEN bit must be set after the empty states. Any data characters in the buffers are UARTEN bit is set to enable UART lost, and the baud rate counter is reset. transmissions. All error and status flags associated with the UART 4. Write the byte to be transmitted to the lower byte module are reset when the module is disabled. The of UxTXREG. The value will be transferred to the URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and Transmit Shift register (UxTSR) immediately UTXBF bits are cleared, whereas RIDLE and TRMT and the serial bit stream will start shifting out are set. Other control bits, including ADDEN, during the next rising edge of the baud clock. URXISEL<1:0>, UTXISEL, as well as the UxMODE Alternatively, the data byte may be written while and UxBRG registers, are not affected. UTXEN = 0, following which the user may set Clearing the UARTEN bit while the UART is active will UTXEN. This will cause the serial bit stream to abort all pending transmissions and receptions and begin immediately because the baud clock will reset the module as defined above. Re-enabling the start from a cleared state. UART will restart the UART in the same configuration. 5. A Transmit interrupt will be generated depend- ing on the value of the interrupt control bit 17.2.3 ALTERNATE I/O UTXISEL (UxSTA<15>). The alternate I/O function is enabled by setting the ALTIO bit (UxMODE<10>). If ALTIO = 1, the UxATX 17.3.2 TRANSMITTING IN 9-BIT DATA and UxARX pins (alternate transmit and alternate MODE receive pins, respectively) are used by the UART mod- The sequence of steps involved in the transmission of ule instead of the UxTX and UxRX pins. If ALTIO = 0, 9-bit data is similar to 8-bit transmission, except that a the UxTX and UxRX pins are used by the UART 16-bit data word (of which the upper 7 bits are always module. clear) must be written to the UxTXREG register. 17.2.4 SETTING UP DATA, PARITY AND 17.3.3 TRANSMIT BUFFER (UXTXB) STOP BIT SELECTIONS The transmit buffer is 9 bits wide and four characters Control bits PDSEL<1:0> in the UxMODE register are deep. Including the Transmit Shift Register (UxTSR), used to select the data length and parity used in the the user effectively has a 5-deep FIFO (First In First transmission. The data length may either be 8 bits with Out) buffer. The UTXBF status bit (UxSTA<9>) even, odd, or no parity, or 9 bits with no parity. indicates whether the transmit buffer is full. The STSEL bit determines whether one or two Stop bits If a user attempts to write to a full buffer, the new data will be used during data transmission. will not be accepted into the FIFO, and no data shift The default (Power-on) setting of the UART is 8 bits, no will occur within the buffer. This enables recovery from parity, 1 Stop bit (typically represented as 8, N, 1). a buffer overrun condition. The FIFO is reset during any device Reset, but is not affected when the device enters or wakes up from a Power-Saving mode. © 2011 Microchip Technology Inc. DS70118J-page 105

dsPIC30F2010 17.3.4 TRANSMIT INTERRUPT 17.4.2 RECEIVE BUFFER (UXRXB) The transmit interrupt flag (U1TXIF or U2TXIF) is The receive buffer is 4 words deep. Including the located in the corresponding interrupt flag register. Receive Shift register (UxRSR), the user effectively has a 5-word deep FIFO buffer. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends URXDA (UxSTA<0>) = 1 indicates that the receive on UTXISEL control bit: buffer has data available. URXDA = 0 implies that the buffer is empty. If a user attempts to read an empty a) If UTXISEL = 0, an interrupt is generated when buffer, the old values in the buffer will be read and no a word is transferred from the Transmit buffer to data shift will occur within the FIFO. the Transmit Shift register (UxTSR). This means that the transmit buffer has at least one empty The FIFO is reset during any device Reset. It is not word. affected when the device enters or wakes up from a b) If UTXISEL = 1, an interrupt is generated when Power-Saving mode. a word is transferred from the Transmit buffer to 17.4.3 RECEIVE INTERRUPT the Transmit Shift register (UxTSR) and the Transmit buffer is empty. The receive interrupt flag (U1RXIF) can be read from the corresponding interrupt flag register. The interrupt Switching between the two interrupt modes during flag is set by an edge generated by the receiver. The operation is possible and sometimes offers more condition for setting the receive interrupt flag depends flexibility. on the settings specified by the URXISEL<1:0> 17.3.5 TRANSMIT BREAK (UxSTA<7:6>) control bits. Setting the UTXBRK bit (UxSTA<11>) will cause the a) If URXISEL<1:0> = 00 or 01, an interrupt is UxTX line to be driven to logic ‘0’. The UTXBRK bit generated every time a data word is transferred overrides all transmission activity. Therefore, the user from the Receive Shift Register (UxRSR) to the should generally wait for the transmitter to be Idle Receive Buffer. There may be one or more before setting UTXBRK. characters in the receive buffer. b) If URXISEL<1:0> = 10, an interrupt is generated To send a break character, the UTXBRK bit must be when a word is transferred from the Receive set by software and must remain set for a minimum of Shift Register (UxRSR) to the Receive Buffer, 13 baud clock cycles. The UTXBRK bit is then cleared which, as a result of the transfer, contains 3 by software to generate Stop bits. The user must wait characters. for a duration of at least one or two baud clock cycles in order to ensure a valid Stop bit(s) before reloading c) If URXISEL<1:0> = 11, an interrupt is set when the UxTXB or starting other transmitter activity. Trans- a word is transferred from the Receive Shift mission of a break character does not generate a Register (UxRSR) to the Receive Buffer, which, transmit interrupt. as a result of the transfer, contains 4 characters (i.e., becomes full). 17.4 Receiving Data Switching between the Interrupt modes during opera- tion is possible, though generally not advisable during 17.4.1 RECEIVING IN 8-BIT OR 9-BIT DATA normal operation. MODE 17.5 Reception Error Handling The following steps must be performed while receiving 8-bit or 9-bit data: 17.5.1 RECEIVE BUFFER OVERRUN 1. Set up the UART (see Section17.3.1 ERROR (OERR BIT) “Transmitting in 8-bit data mode”). The OERR bit (UxSTA<1>) is set if all of the following 2. Enable the UART (see Section17.3.1 conditions occur: “Transmitting in 8-bit data mode”). 3. A receive interrupt will be generated when one a) The receive buffer is full. or more data words have been received, b) The receive shift register is full, but unable to depending on the receive interrupt settings transfer the character to the receive buffer. specified by the URXISEL bits (UxSTA<7:6>). c) The Stop bit of the character in the UxRSR is 4. Read the OERR bit to determine if an overrun detected, indicating that the UxRSR needs to error has occurred. The OERR bit must be reset transfer the character to the buffer. in software. Once OERR is set, no further data is shifted in UxRSR 5. Read the received data from UxRXREG. The act (until the OERR bit is cleared in software or a Reset of reading UxRXREG will move the next word to occurs). The data held in UxRSR and UxRXREG the top of the receive FIFO, and the PERR and remains valid. FERR values will be updated. DS70118J-page 106 © 2011 Microchip Technology Inc.

dsPIC30F2010 17.5.2 FRAMING ERROR (FERR) 17.7 Loopback Mode The FERR bit (UxSTA<2>) is set if a ‘0’ is detected Setting the LPBACK bit enables this special mode in instead of a Stop bit. If two Stop bits are selected, both which the UxTX pin is internally connected to the UxRX Stop bits must be ‘1’, otherwise FERR will be set. The pin. When configured for the Loopback mode, the read-only FERR bit is buffered along with the received UxRX pin is disconnected from the internal UART data. It is cleared on any Reset. receive logic. However, the UxTX pin still functions as in a normal operation. 17.5.3 PARITY ERROR (PERR) To select this mode: The PERR bit (UxSTA<3>) is set if the parity of the received word is incorrect. This error bit is applicable a) Configure UART for desired mode of operation. only if a Parity mode (odd or even) is selected. The b) Set LPBACK = 1 to enable Loopback mode. read-only PERR bit is buffered along with the received c) Enable transmission as defined in Section17.3 data bytes. It is cleared on any Reset. “Transmitting Data”. 17.5.4 IDLE STATUS 17.8 Baud Rate Generator When the receiver is active (i.e., between the initial The UART has a 16-bit Baud Rate Generator to allow detection of the Start bit and the completion of the Stop maximum flexibility in baud rate generation. The Baud bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the Rate Generator register (UxBRG) is readable and completion of the Stop bit and detection of the next writable. The baud rate is computed as follows: Start bit, the RIDLE bit is ‘1’, indicating that the UART is Idle. BRG = 16-bit value held in UxBRG register (0 through 65535) 17.5.5 RECEIVE BREAK FCY = Instruction Clock Rate (1/TCY) The receiver will count and expect a certain number of The Baud Rate is given by Equation17-1. bit times based on the values programmed in the PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>) EQUATION 17-1: BAUD RATE bits. If the break is longer than 13 bit times, the reception is Baud Rate = FCY/(16 * (BRG + 1)) considered complete after the number of bit times specified by PDSEL and STSEL. The URXDA bit is Therefore, maximum baud rate possible is set, FERR is set, zeros are loaded into the receive FIFO, interrupts are generated, if appropriate, and the FCY/16 (if BRG = 0), RIDLE bit is set. and the minimum baud rate possible is When the module receives a long break signal and the FCY/(16 * 65536). receiver has detected the Start bit, the data bits and the invalid Stop bit (which sets the FERR), the receiver With a full 16-bit Baud Rate Generator, at 30 MIPs must wait for a valid Stop bit before looking for the next operation, the minimum baud rate achievable is Start bit. It cannot assume that the break condition on 28.5bps. the line is the next Start bit. 17.9 Auto Baud Support Break is regarded as a character containing all ‘0’s, with the FERR bit set. The break character is loaded To allow the system to determine baud rates of into the buffer. No further reception can occur until a received characters, the input can be optionally linked Stop bit is received. Note that RIDLE goes high when to a selected capture input. To enable this mode, the the Stop bit has not been received yet. user must program the input capture module to detect the falling and rising edges of the Start bit. 17.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this spe- cial mode, in which a 9th bit (URX8) value of ‘1’ identi- fies the received word as an address rather than data. This mode is only applicable for 9-bit data communica- tion. The URXISEL control bit does not have any impact on interrupt generation in this mode, since an interrupt (if enabled) will be generated every time the received word has the 9th bit set. © 2011 Microchip Technology Inc. DS70118J-page 107

dsPIC30F2010 17.10 UART Operation During CPU 17.10.2 UART OPERATION DURING CPU Sleep and Idle Modes IDLE MODE For the UART, the USIDL bit selects if the module will 17.10.1 UART OPERATION DURING CPU stop operation when the device enters Idle mode, or SLEEP MODE whether the module will continue on Idle. If USIDL=0, When the device enters Sleep mode, all clock sources the module will continue operation during Idle mode. If to the module are shutdown and stay at logic ‘0’. If USIDL = 1, the module will stop on Idle. entry into Sleep mode occurs while a transmission is in progress, then the transmission is aborted. The UxTX pin is driven to logic ‘1’. Similarly, if entry into Sleep mode occurs while a reception is in progress, then the reception is aborted. The UxSTA, UxMODE, transmit and receive registers and buffers, and the UxBRG register are not affected by Sleep mode. If the WAKE bit (UxMODE<7>) is set before the device enters Sleep mode, then a falling edge on the UxRX pin will generate a receive interrupt. The Receive Interrupt Select mode bit (URXISEL) has no effect for this function. If the receive interrupt is enabled, then this will wake-up the device from Sleep. The UARTEN bit must be set in order to generate a wake-up interrupt. DS70118J-page 108 © 2011 Microchip Technology Inc.

© TABLE 17-1: UART1 REGISTER MAP 2 0 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 1 M U1MODE 020C UARTEN — USIDL — — ALTIO — — WAKE LPBACK ABAUD — — PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000 ic U1STA 020E UTXISEL — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0000 0001 0001 0000 ro ch U1TXREG 0210 — — — — — — — UTX8 Transmit Register 0000 000u uuuu uuuu ip T U1RXREG 0212 — — — — — — — URX8 Receive Register 0000 0000 0000 0000 e c U1BRG 0214 Baud Rate Generator Prescaler 0000 0000 0000 0000 h no Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ lo Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. g y In c . d s P I C 3 D 0 S 7 F 0 1 1 2 8 J -p 0 a g 1 e 1 0 0 9

dsPIC30F2010 NOTES: DS70118J-page 110 © 2011 Microchip Technology Inc.

dsPIC30F2010 18.0 10-BIT HIGH-SPEED ANALOG- The ADC module has six 16-bit registers: TO-DIGITAL CONVERTER • A/D Control Register1 (ADCON1) (ADC) MODULE • A/D Control Register2 (ADCON2) • A/D Control Register3 (ADCON3) Note: This data sheet summarizes features of • A/D Input Select Register (ADCHS) this group ofdsPIC30F devices and is not • A/D Port Configuration Register (ADPCFG) intended to be a complete reference source. For more information on the CPU, • A/D Input Scan Selection Register (ADCSSL) peripherals, register descriptions and The ADCON1, ADCON2 and ADCON3 registers con- general device functionality, refer to the trol the operation of the ADC module. The ADCHS reg- “dsPIC30F Family Reference Manual” ister selects the input channels to be converted. The (DS70046). ADPCFG register configures the port pins as analog inputs or as digital I/O. The ADCSSL register selects The 10-bit high-speed Analog-to-Digital Converter inputs for scanning. (ADC) allows conversion of an analog input signal to a 10-bit digital number. This module is based on a Suc- Note: The SSRC<2:0>, ASAM, SIMSAM, cessive Approximation Register (SAR) architecture, SMPI<3:0>, BUFM and ALTS bits, as well and provides a maximum sampling rate of 500 ksps. as the ADCON3 and ADCSSL registers, The ADC module has up to 16 analog inputs which are must not be written to while ADON = 1. multiplexed into four sample and hold amplifiers. The This would lead to indeterminate results. output of the sample and hold is the input into the con- The block diagram of the ADC module is shown in verter, which generates the result. The analog refer- Figure18-1. ence voltages are software selectable to either the device supply voltage (AVDD/AVSS) or the voltage level on the (VREF+/VREF-) pin. The ADC has a unique fea- ture of being able to operate while the device is in Sleep mode. FIGURE 18-1: 10-BIT HIGH-SPEED ADC FUNCTIONAL BLOCK DIAGRAM AVDD VREF+ AVSS VREF- AN0 AN0 AN3 + S/H CH1 ADC - AN1 AN1 10-bit Result Conversion Logic AN4 + CH2 -S/H atamat 16-word, 10-bit Dor F Dual Port Buffer AN2 AN2 ce AN5 +S/H CH3 nterfa - CCHH13,,CCHH02, Sample/Sequence Bus I Sample Control AN0 AN1 Input AN2 Switches Input MUX AN3 AN3 Control AN4 AN4 AN5 AN5 + S/H CH0 AN1 - © 2011 Microchip Technology Inc. DS70118J-page 111

dsPIC30F2010 18.1 A/D Result Buffer The CHPS bits selects how many channels are sam- pled. This can vary from 1, 2 or 4 channels. If CHPS The module contains a 16-word dual port read-only buf- selects 1 channel, the CH0 channel will be sampled at fer, called ADCBUF0 through ADCBUFF, to buffer the the sample clock and converted. The result is stored in ADC results. The RAM is 10 bits wide, but is read into dif- the buffer. If CHPS selects 2 channels, the CH0 and ferent format 16-bit words. The contents of the sixteen CH1 channels will be sampled and converted. If CHPS ADC conversion result buffer registers, ADCBUF0 selects 4 channels, the CH0, CH1, CH2 and CH3 through ADCBUFF, cannot be written by user software. channels will be sampled and converted. The SMPI bits select the number of acquisition/conver- 18.2 Conversion Operation sion sequences that would be performed before an After the ADC module has been configured, the sample interrupt occurs. This can vary from 1 sample per acquisition is started by setting the SAMP bit. Various interrupt to 16 samples per interrupt. sources, such as a programmable bit, timer time-outs The user cannot program a combination of CHPS and and external events, will terminate acquisition and start SMPI bits that specifies more than 16 conversions per a conversion. When the A/D conversion is complete, interrupt, or 8 conversions per interrupt, depending on the result is loaded into ADCBUF0...ADCBUFF, and the BUFM bit. The BUFM bit, when set, will split the the A/D interrupt flag ADIF and the DONE bit are set 16-word results buffer (ADCBUF0...ADCBUFF) into after the number of samples specified by the SMPI bit. two 8-word groups. Writing to the 8-word buffers will be The following steps should be followed for doing an alternated on each interrupt event. Use of the BUFM bit A/D conversion: will depend on how much time is available for moving data out of the buffers after the interrupt, as determined 1. Configure the ADC module: by the application. - Configure analog pins, voltage reference If the processor can quickly unload a full buffer within and digital I/O the time it takes to acquire and convert one channel, - Select A/D input channels the BUFM bit can be ‘0’ and up to 16 conversions may - Select A/D conversion clock be done per interrupt. The processor will have one - Select A/D conversion trigger sample and conversion time to move the sixteen - Turn on A/D module conversions. 2. Configure A/D interrupt (if required): If the processor cannot unload the buffer within the - Clear ADIF bit acquisition and conversion time, the BUFM bit should - Select A/D interrupt priority be ‘1’. For example, if SMPI<3:0> (ADCON2<5:2>) = 0111, then eight conversions will be loaded into 1/2 3. Start sampling. of the buffer, following which an interrupt occurs. The 4. Wait the required acquisition time. next eight conversions will be loaded into the other 5. Trigger acquisition end, start conversion 1/2 of the buffer. The processor will have the entire 6. Wait for A/D conversion to complete, by either: time between interrupts to move the eight - Waiting for the A/D interrupt conversions. - Waiting for the DONE bit to get set The ALTS bit can be used to alternate the inputs 7. Read A/D result buffer, clear ADIF if required. selected during the sampling sequence. The input mul- tiplexer has two sets of sample inputs: MUX A and 18.3 Selecting the Conversion MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are selected for sampling. If the ALTS bit is ‘1’ and Sequence SMPI<3:0> = 0000, on the first sample/convert Several groups of control bits select the sequence in sequence, the MUX A inputs are selected, and on the which the A/D connects inputs to the sample/hold next acquire/convert sequence, the MUX B inputs are channels, converts channels, writes the buffer memory, selected. and generates interrupts. The sequence is controlled The CSCNA bit (ADCON2<10>) will allow the CH0 by the sampling clocks. channel inputs to be alternately scanned across a The SIMSAM bit controls the acquire/convert selected number of analog inputs for the MUX A group. sequence for multiple channels. If the SIMSAM bit is The inputs are selected by the ADCSSL register. If a ‘0’, the two or four selected channels are acquired and particular bit in the ADCSSL register is ‘1’, the corre- converted sequentially, with two or four sample clocks. sponding input is selected. The inputs are always If the SIMSAM bit is ‘1’, two or four selected channels scanned from lower to higher numbered inputs, starting are acquired simultaneously, with one sample clock. after each interrupt. If the number of inputs selected is The channels are then converted sequentially. Obvi- greater than the number of samples taken per interrupt, ously, if there is only one channel selected, the the higher numbered inputs are unused. SIMSAM bit is not applicable. DS70118J-page 112 © 2011 Microchip Technology Inc.

dsPIC30F2010 18.4 Programming the Start of 18.6 Selecting the A/D Conversion Conversion Trigger Clock The conversion trigger will terminate acquisition and The A/D conversion requires 12 TAD. The source of the start the requested conversions. A/D conversion clock is software selected using a 6-bit The SSRC<2:0> bits select the source of the counter. There are 64 possible options for TAD. conversion trigger. EQUATION 18-1: A/D CONVERSION CLOCK The SSRC bits provide for up to five alternate sources of conversion trigger. TAD = TCY * (0.5 * (ADCS<5:0> + 1)) When SSRC<2:0> = 000, the conversion trigger is TAD ADCS<5:0> = 2 – 1 under software control. Clearing the SAMP bit will TCY cause the conversion trigger. The internal RC oscillator is selected by setting the When SSRC<2:0> = 111 (Auto-Start mode), the con- ADRC bit. version trigger is under A/D clock control. The SAMC bits select the number of A/D clocks between the start For correct A/D conversions, the A/D conversion clock of acquisition and the start of conversion. This provides (TAD) must be selected to ensure a minimum TAD time the fastest conversion rates on multiple channels. of 83.33 ns (for VDD = 5V). Refer to Section22.0 SAMC must always be at least one clock cycle. “Electrical Characteristics” for minimum TAD under other operating conditions. Other trigger sources can come from timer modules, Motor Control PWM module or external interrupts. Example18-1 shows a sample calculation for the ADCS<5:0> bits, assuming a device operating speed Note: To operate the A/D at the maximum of 30 MIPS. specified conversion speed, the Auto Convert Trigger option should be selected EXAMPLE 18-1: A/D CONVERSION CLOCK (SSRC = 111) and the Auto Sample Time CALCULATION bits should be set to 1 TAD (SAMC = 00001). This configuration will give a total conversion period (sample + convert) of TAD = 84 ns 13 TAD. TCY = 33 ns (30 MIPS) The use of any other conversion trigger TAD will result in additional TAD cycles to ADCS<5:0> = 2 • T C Y – 1 synchronize the external event to the A/D. 84 ns = 2 • – 1 33 ns 18.5 Aborting a Conversion = 4.09 Clearing the ADON bit during a conversion will abort Therefore, the current conversion and stop the sampling sequenc- Set ADCS<5:0> = 5 ing. The ADCBUF will not be updated with the partially completed A/D conversion sample. That is, the TCY Actual TAD = • (ADCS<5:0> + 1) ADCBUF will continue to contain the value of the last 2 completed conversion (or the last value written to the 33 ns = • (5 + 1) ADCBUF register). 2 If the clearing of the ADON bit coincides with an auto = 99 ns start, the clearing has a higher priority. After the A/D conversion is aborted, a 2 TAD wait is required before the next sampling may be started by setting the SAMP bit. If sequential sampling is specified, the A/D will continue at the next sample pulse which corresponds with the next channel converted. If simultaneous sampling is specified, the A/D will continue with the next multichannel group conversion sequence. © 2011 Microchip Technology Inc. DS70118J-page 113

dsPIC30F2010 18.7 A/D Conversion Speeds The dsPIC30F 10-bit ADC specifications permit a max- imum 1 Msps sampling rate. Table18-1 summarizes the conversion speeds for the dsPIC30F 10-bit ADC and the required operating conditions. The configuration guidelines give the required setup values for the conversion speeds above 500 ksps, since they require external VREF pins usage and there are some differences in the configuration procedure. Configuration details that are not critical to the conversion speed have been omitted. Figure18-2 depicts the recommended circuit for the conversion rates above 500 ksps. FIGURE 18-2: ADC VOLTAGE REFERENCE SCHEMATIC VDD R2 10 C2 C1 VDD 0.1 μF 0.01 μF 10 R1 VVAA VDD RRVV EEDS C8 -F+FDS 1 μF d sPIC30F2010 VDD VDD VSS VSS VDD D D C5 V 1 μF VDD DS70118J-page 114 © 2011 Microchip Technology Inc.

dsPIC30F2010 TABLE 18-1: 10-BIT A/D CONVERSION RATE PARAMETERS dsPIC30F 10-bit A/D Converter Conversion Rates TAD Sampling A/D Speed RS Max VDD Temperature A/D Channels Configuration Minimum Time Min Up to 83.33 ns 12 TAD 500Ω 4.5V -40°C to +85°C 1 Msps(1) to VREF-VREF+ 5.5V CH1, CH2 or CH3 ANx S/H ADC CH0 S/H Up to 95.24 ns 2 TAD 500Ω 4.5V -40°C to +85°C 750 ksps(1) to VREF- VREF+ 5.5V ANx CHX S/H ADC Up to 138.89 ns 12 TAD 500Ω 3.0V -40°C to +125°C 600 ksps(1) to VREF- VREF+ 5.5V CH1, CH2 or CH3 ANx S/H ADC CH0 S/H Up to 153.85 ns 1 TAD 5.0 kΩ 4.5V -40°C to +125°C 500 ksps to VREF-VREF+ or or 5.5V AVSSAVDD ANx CHX S/H ADC ANx or VREF- Up to 256.41 ns 1 TAD 5.0 kΩ 3.0V -40°C to +125°C 300 ksps to VREF-VREF+ or or 5.5V AVSSAVDD ANx CHX S/H ADC ANx or VREF- Note1: External VREF- and VREF+ pins must be used for correct operation. See Figure18-2 for recommended circuit. © 2011 Microchip Technology Inc. DS70118J-page 115

dsPIC30F2010 18.7.1 1 Msps CONFIGURATION 18.7.2 750 ksps CONFIGURATION GUIDELINE GUIDELINE The configuration for 1 Msps operation is dependent on The following configuration items are required to whether a single input pin is to be sampled or whether achieve a 750 ksps conversion rate. This configuration multiple pins will be sampled. assumes that a single analog input is to be sampled. • Comply with conditions provided in Table18-2 18.7.1.1 Single Analog Input • Connect external VREF+ and VREF- pins following For conversions at 1 Msps for a single analog input, at the recommended circuit shown in Figure18-2 least two sample and hold channels must be enabled. • Set SSRC<2:0> = 111 in the ADCON1 register to The analog input multiplexer must be configured so enable the auto-convert option that the same input pin is connected to both sample • Enable automatic sampling by setting the ASAM and hold channels. The A/D converts the value held on control bit in the ADCON1 register one S/H channel, while the second S/H channel acquires a new input sample. • Enable one sample and hold channel by setting CHPS<1:0> = 00 in the ADCON2 register 18.7.1.2 Multiple Analog Inputs • Write the SMPI<3:0> control bits in the ADCON2 The A/D converter can also be used to sample multiple register for the desired number of conversions analog inputs using multiple sample and hold channels. between interrupts In this case, the total 1 Msps conversion rate is divided • Configure the A/D clock period to be: among the different input signals. For example, four 1 inputs can be sampled at a rate of 250 ksps for each = 95.24 ns (12 + 2) X 750,000 signal or two inputs could be sampled at a rate of 500ksps for each signal. Sequential sampling must be by writing to the ADCS<5:0> control bits in the used in this configuration to allow adequate sampling ADCON3 register time on each input. • Configure the sampling time to be 2 TAD by writing: SAMC<4:0> = 00010 18.7.1.3 1 Msps Configuration Items 18.7.3 600 ksps CONFIGURATION The following configuration items are required to GUIDELINE achieve a 1 Msps conversion rate. • Comply with conditions provided in Table19-2 The configuration for 600 ksps operation is dependent on whether a single input pin is to be sampled or • Connect external VREF+ and VREF- pins following whether multiple pins will be sampled. the recommended circuit shown in Figure18-2 • Set SSRC<2:0> = 111 in the ADCON1 register to 18.7.3.1 Single Analog Input enable the auto-convert option When performing conversions at 600 ksps for a single • Enable automatic sampling by setting the ASAM analog input, at least two sample and hold channels control bit in the ADCON1 register must be enabled. The analog input multiplexer must be • Enable sequential sampling by clearing the configured so that the same input pin is connected to SIMSAM bit in the ADCON1 register both sample and hold channels. The A/D converts the • Enable at least two sample and hold channels by value held on one S/H channel, while the second S/H writing the CHPS<1:0> control bits in the channel acquires a new input sample. ADCON2 register • Write the SMPI<3:0> control bits in the ADCON2 18.7.3.2 Multiple Analog Input register for the desired number of conversions The ADC can also be used to sample multiple analog between interrupts. At a minimum, set inputs using multiple sample and hold channels. In this SMPI<3:0> = 0001 since at least two sample and case, the total 600 ksps conversion rate is divided hold channels should be enabled among the different input signals. For example, four • Configure the A/D clock period to be: inputs can be sampled at a rate of 150 ksps for each 1 signal or two inputs can be sampled at a rate of 300 = 83.33 ns ksps for each signal. Sequential sampling must be 12 x 1,000,000 used in this configuration to allow adequate sampling by writing to the ADCS<5:0> control bits in the time on each input. ADCON3 register • Configure the sampling time to be 2 TAD by writing: SAMC<4:0> = 00010 • Select at least two channels per analog input pin by writing to the ADCHS register DS70118J-page 116 © 2011 Microchip Technology Inc.

dsPIC30F2010 18.7.3.3 600 ksps Configuration Items 18.8 A/D Acquisition Requirements The following configuration items are required to The analog input model of the 10-bit ADC is shown in achieve a 600 ksps conversion rate. Figure18-3. The total sampling time for the A/D is a • Comply with conditions provided in Table18-2 function of the internal amplifier settling time, device • Connect external VREF+ and VREF- pins following VDD and the holding capacitor charge time. the recommended circuit shown in Figure18-2 For the A/D converter to meet its specified accuracy, the • Set SSRC<2:0> = 111 in the ADCON1 register to charge holding capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin. enable the auto-convert option The source impedance (RS), the interconnect • Enable automatic sampling by setting the ASAM impedance (RIC), and the internal sampling switch control bit in the ADCON1 register (RSS) impedance combine to directly affect the time • Enable sequential sampling by clearing the required to charge the capacitor CHOLD. The combined SIMSAM bit in the ADCON1 register impedance of the analog sources must therefore be • Enable at least two sample and hold channels by small enough to fully charge the holding capacitor within writing the CHPS<1:0> control bits in the the chosen sample time. To minimize the effects of pin ADCON2 register leakage currents on the accuracy of the A/D converter, • Write the SMPI<3:0> control bits in the ADCON2 the maximum recommended source impedance, RS, is register for the desired number of conversions 5 kΩ. After the analog input channel is selected between interrupts. At a minimum, set (changed), this sampling function must be completed SMPI<3:0> = 0001 since at least two sample and prior to starting the conversion. The internal holding hold channels should be enabled capacitor will be in a discharged state prior to each sample operation. • Configure the A/D clock period to be: The user must allow at least 1 TAD period of sampling 1 = 138.89 ns time, TSAMP, between conversions to allow each sam- 12 x 600,000 ple to be acquired. This sample time may be controlled by writing to the ADCS<5:0> control bits in the manually in software by setting/clearing the SAMP bit, ADCON3 register or it may be automatically controlled by the A/D con- verter. In an automatic configuration, the user must • Configure the sampling time to be 2 TAD by allow enough time between conversion triggers so that writing: SAMC<4:0> = 00010 the minimum sample time can be satisfied. Refer to the Select at least two channels per analog input pin by Electrical Specifications for TAD and sample time writing to the ADCHS register. requirements. FIGURE 18-3: ADC ANALOG INPUT MODEL VDD RIC ≤ 250Ω Sampling RSS ≤ 3 kΩ Switch VT = 0.6V Rs ANx RSS CHOLD VA CPIN I leakage = DAC capacitance VT = 0.6V ± 500 nA = 4.4 pF VSS Legend: CPIN = input capacitance VT = threshold voltage I leakage = leakage current at the pin due to various junctions RIC = interconnect resistance RSS = sampling switch resistance CHOLD = sample/hold capacitance (from DAC) Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ. © 2011 Microchip Technology Inc. DS70118J-page 117

dsPIC30F2010 18.9 Module Power-Down Modes If the A/D interrupt is enabled, the device will wake-up from Sleep. If the A/D interrupt is not enabled, the A/D The module has three internal power modes. When the module will then be turned off, although the ADON bit ADON bit is ‘1’, the module is in Active mode; it is fully will remain set. powered and functional. When ADON is ‘0’, the module is in Off mode. The digital and analog portions of the 18.10.2 A/D OPERATION DURING CPU IDLE circuit are disabled for maximum current savings. In MODE order to return to the Active mode from Off mode, the The ADSIDL bit selects if the module will stop on Idle or user must wait for the ADC circuitry to stabilize. continue on Idle. If ADSIDL = 0, the module will con- tinue operation on assertion of Idle mode. If 18.10 A/D Operation During CPU Sleep ADSIDL=1, the module will stop on Idle. and Idle Modes 18.11 Effects of a Reset 18.10.1 A/D OPERATION DURING CPU SLEEP MODE A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off, and any When the device enters Sleep mode, all clock sources conversion and acquisition sequence is aborted. The to the module are shutdown and stay at logic ‘0’. values that are in the ADCBUF registers are not modi- If Sleep occurs in the middle of a conversion, the con- fied. The A/D result register will contain unknown data version is aborted. The converter will not continue with after a Power-on Reset. a partially completed conversion on exit from Sleep mode. 18.12 Output Formats Register contents are not affected by the device The A/D result is 10 bits wide. The data buffer RAM is entering or leaving Sleep mode. also 10 bits wide. The 10-bit data can be read in one of The A/D module can operate during Sleep mode if the four different formats. The FORM<1:0> bits select the A/D clock source is set to RC (ADRC = 1). When the format. Each of the output formats translates to a 16-bit RC clock source is selected, the A/D module waits one result on the data bus. instruction cycle before starting the conversion. This Write data will always be in right justified (integer) allows the SLEEP instruction to be executed, which format. eliminates all digital switching noise from the conver- sion. When the conversion is complete, the DONE bit will be set and the result loaded into the ADCBUF register. FIGURE 18-4: A/D OUTPUT DATA FORMATS RAM Contents: d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Read to Bus: Signed Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0 Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0 Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Integer 0 0 0 0 0 0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 DS70118J-page 118 © 2011 Microchip Technology Inc.

dsPIC30F2010 18.13 Configuring Analog Port Pins 18.14 Connection Considerations The use of the ADPCFG and TRIS registers control the The analog inputs have diodes to VDD and VSS as ESD operation of the A/D port pins. The port pins that are protection. This requires that the analog input be desired as analog inputs must have their correspond- between VDD and VSS. If the input voltage exceeds this ing TRIS bit set (input). If the TRIS bit is cleared (out- range by greater than 0.3V (either direction), one of the put), the digital output level (VOH or VOL) will be diodes becomes forward biased and it may damage the converted. device if the input current specification is exceeded. The A/D operation is independent of the state of the An external RC filter is sometimes added for anti- CH0SA<3:0>/CH0SB<3:0> bits and the TRIS bits. aliasing of the input signal. The R component should be selected to ensure that the sampling time requirements When reading the PORT register, all pins configured as are satisfied. Any external components connected (via analog input channels will read as cleared. high-impedance) to an analog input pin (capacitor, Pins configured as digital inputs will not convert an ana- zener diode, etc.) should have very little leakage log input. Analog levels on any pin that is defined as a current at the pin. digital input (including the ANx pins), may cause the input buffer to consume current that exceeds the device specifications. © 2011 Microchip Technology Inc. DS70118J-page 119

D TABLE 18-2: ADC REGISTER MAP d S 70 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State s 1 18 ADCBUF0 0280 — — — — — — ADC Data Buffer 0 0000 00uu uuuu uuuu P J -p ADCBUF1 0282 — — — — — — ADC Data Buffer 1 0000 00uu uuuu uuuu I age ADCBUF2 0284 — — — — — — ADC Data Buffer 2 0000 00uu uuuu uuuu C 12 ADCBUF3 0286 — — — — — — ADC Data Buffer 3 0000 00uu uuuu uuuu 3 0 ADCBUF4 0288 — — — — — — ADC Data Buffer 4 0000 00uu uuuu uuuu 0 ADCBUF5 028A — — — — — — ADC Data Buffer 5 0000 00uu uuuu uuuu F ADCBUF6 028C — — — — — — ADC Data Buffer 6 0000 00uu uuuu uuuu 2 ADCBUF7 028E — — — — — — ADC Data Buffer 7 0000 00uu uuuu uuuu 0 ADCBUF8 0290 — — — — — — ADC Data Buffer 8 0000 00uu uuuu uuuu 1 ADCBUF9 0292 — — — — — — ADC Data Buffer 9 0000 00uu uuuu uuuu 0 ADCBUFA 0294 — — — — — — ADC Data Buffer 10 0000 00uu uuuu uuuu ADCBUFB 0296 — — — — — — ADC Data Buffer 11 0000 00uu uuuu uuuu ADCBUFC 0298 — — — — — — ADC Data Buffer 12 0000 00uu uuuu uuuu ADCBUFD 029A — — — — — — ADC Data Buffer 13 0000 00uu uuuu uuuu ADCBUFE 029C — — — — — — ADC Data Buffer 14 0000 00uu uuuu uuuu ADCBUFF 029E — — — — — — ADC Data Buffer 15 0000 00uu uuuu uuuu ADCON1 02A0 ADON — ADSIDL — — — FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000 0000 0000 0000 ADCON2 02A2 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000 0000 0000 0000 ADCON3 02A4 — — — SAMC<4:0> ADRC — ADCS<5:0> 0000 0000 0000 0000 ADCHS 02A6 CH123NB<1:0> CH123SB CH0NB CH0SB<3:0> CH123NA<1:0> CH123SA CH0NA CH0SA<3:0> 0000 0000 0000 0000 ADPCFG 02A8 — — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000 ADCSSL 02AA — — — — — — — — — — CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 0000 0000 0000 Legend: u = uninitialized bit; — = unimplemented bit, read as ‘0’ Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. © 2 0 1 1 M ic ro c h ip T e c h n o lo g y In c .

dsPIC30F2010 19.0 SYSTEM INTEGRATION 19.1 Oscillator System Overview The dsPIC30F oscillator system has the following Note: This data sheet summarizes features of modules and features: this group ofdsPIC30F devices and is not intended to be a complete reference • Various external and internal oscillator options as source. For more information on the CPU, clock sources peripherals, register descriptions and • An on-chip PLL to boost internal operating general device functionality, refer to the frequency “dsPIC30F Family Reference Manual” • A clock switching mechanism between various (DS70046). For more information on the clock sources device instruction set and programming, • Programmable clock postscaler for system power refer to the “16-bit MCU and DSC Pro- savings grammer’s Reference Manual” (DS70157). • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and takes fail-safe measures There are several features intended to maximize sys- • Clock Control Register OSCCON tem reliability, minimize cost through elimination of • Configuration bits for main oscillator selection external components, provide Power-Saving Operating modes and offer code protection: Table19-1 provides a summary of the dsPIC30F Oscillator Operating modes. A simplified diagram of the • Oscillator Selection oscillator system is shown in Figure19-1. • Reset Configuration bits determine the clock source upon - Power-on Reset (POR) Power-on Reset (POR) and Brown-out Reset (BOR). - Power-up Timer (PWRT) Thereafter, the clock source can be changed between - Oscillator Start-up Timer (OST) permissible clock sources. The OSCCON register - Programmable Brown-out Reset (BOR) controls the clock switching and reflects system clock • Watchdog Timer (WDT) related status bits. • Power-Saving modes (Sleep and Idle) • Code Protection • Unit ID Locations • In-Circuit Serial Programming (ICSP) programming capability dsPIC30F devices have a Watchdog Timer, which is permanently enabled via the Configuration bits, or can be software controlled. It runs off its own RC oscillator for added reliability. There are two timers that offer nec- essary delays on power-up. One is the Oscillator Start- up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power- up Timer (PWRT), which provides a delay on power-up only, designed to keep the part in Reset while the power supply stabilizes. With these two timers on-chip, most applications need no external Reset circuitry. Sleep mode is designed to offer a very low current Power-down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer Wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit a wide variety of applications. In the Idle mode, the clock sources are still active, but the CPU is shut off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2011 Microchip Technology Inc. DS70118J-page 121

dsPIC30F2010 TABLE 19-1: OSCILLATOR OPERATING MODES Oscillator Mode Description XTL 200 kHz-4 MHz crystal on OSC1:OSC2. XT 4 MHz-10 MHz crystal on OSC1:OSC2. XT w/ PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2. 4x PLL enabled. XT w/ PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2. 8x PLL enabled. XT w/ PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2. 16x PLL enabled(1). LP 32 kHz crystal on SOSCO:SOSCI(2). HS 10 MHz-25 MHz crystal. EC External clock input (0-40 MHz). ECIO External clock input (0-40 MHz). OSC2 pin is I/O. EC w/ PLL 4x External clock input (0-40 MHz). OSC2 pin is I/O. 4x PLL enabled(1). EC w/ PLL 8x External clock input (0-40 MHz). OSC2 pin is I/O. 8x PLL enabled(1). EC w/ PLL 16x External clock input (0-40 MHz). OSC2 pin is I/O. 16x PLL enabled(1). ERC External RC oscillator. OSC2 pin is FOSC/4 output(3). ERCIO External RC oscillator. OSC2 pin is I/O(3). FRC 7.37 MHz internal RC Oscillator. LPRC 512 kHz internal RC Oscillator. Note1: dsPIC30F maximum operating frequency of 120 MHz must be met. 2: LP oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation up to 4 MHz. DS70118J-page 122 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 19-1: OSCILLATOR SYSTEM BLOCK DIAGRAM Oscillator Configuration bits PWRSAV Instruction Wake-up Request FPLL OSC1 Primary PLL Oscillator x4, x8, x16 PLL OSC2 Lock COSC<1:0> Primary Osc NOSC<1:0> Primary OSWEN Oscillator Stability Detector Oscillator POR Done Start-up Clock Timer Switching Programmable and Control Secondary Osc Clock Divider System Block Clock SOSCO Secondary 32 kHz LP 2 Oscillator Oscillator SOSCI Stability Detector POST<1:0> Internal Fast RC FRC Oscillator (FRC) Internal Low LPRC Power RC Oscillator (LPRC) CF Fail-Safe Clock FCKSM<1:0> Monitor (FSCM) 2 Oscillator Trap to Timer1 © 2011 Microchip Technology Inc. DS70118J-page 123

dsPIC30F2010 19.2 Oscillator Configurations 19.2.2 OSCILLATOR START-UP TIMER (OST) 19.2.1 INITIAL CLOCK SOURCE In order to ensure that a crystal oscillator (or ceramic SELECTION resonator) has started and stabilized, an oscillator While coming out of Power-on Reset or Brown-out start-up timer is included. It is a simple 10-bit counter Reset, the device selects its clock source based on: that counts 1024 TOSC cycles before releasing the oscillator clock to the rest of the system. The time-out a) FOS<1:0> Configuration bits that select one of four oscillator groups. period is designated as TOST. The TOST time is involved every time the oscillator has to restart (i.e., on POR, b) AND FPR<3:0> Configuration bits that select one BOR and wake-up from Sleep). The oscillator start-up of 13 oscillator choices within the primary group. timer is applied to the LP Oscillator, XT, XTL, and HS The selection is as shown in Table19-2. modes (upon wake-up from Sleep, POR, and BOR) for the primary oscillator. TABLE 19-2: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Oscillator Mode FOS1 FOS0 FPR3 FPR2 FPR1 FPR0 OSC2 Function Source EC Primary 1 1 1 0 1 1 CLKO ECIO Primary 1 1 1 1 0 0 I/O EC w/ PLL 4x Primary 1 1 1 1 0 1 I/O EC w/ PLL 8x Primary 1 1 1 1 1 0 I/O EC w/ PLL 16x Primary 1 1 1 1 1 1 I/O ERC Primary 1 1 1 0 0 1 CLKO ERCIO Primary 1 1 1 0 0 0 I/O XT Primary 1 1 0 1 0 0 OSC2 XT w/ PLL 4x Primary 1 1 0 1 0 1 OSC2 XT w/ PLL 8x Primary 1 1 0 1 1 0 OSC2 XT w/ PLL 16x Primary 1 1 0 1 1 1 OSC2 XTL Primary 1 1 0 0 0 x OSC2 HS Primary 1 1 0 0 1 x OSC2 LP Secondary 0 0 — — — — See Note 1 and 2 FRC Internal FRC 0 1 — — — — See Note 1 and 2 LPRC Internal LPRC 1 0 — — — — See Note 1 and 2 Note 1: The OSC2 pin is either usable as a general-purpose I/O pin or is completely unusable, depending on the Primary Oscillator mode selection (FPR<3:0>). 2: Note that the OSC1 pin cannot be used as an I/O pin, even if the Secondary Oscillator or an internal clock source is selected at all times. DS70118J-page 124 © 2011 Microchip Technology Inc.

dsPIC30F2010 19.2.3 LP OSCILLATOR CONTROL TABLE 19-4: FRC TUNING Enabling the LP oscillator is controlled with two TUN<3:0> FRC Frequency elements: Bits • The current oscillator group bits COSC<1:0> 0111 + 10.5% • The LPOSCEN bit (OSCCON register) 0110 + 9.0% The LP oscillator is ON (even during Sleep mode) if 0101 + 7.5% LPOSCEN = 1. The LP oscillator is the device clock if: 0100 + 6.0% • COSC<1:0> = 00 (LP selected as main osc.) and 0011 + 4.5% • LPOSCEN = 1 0010 + 3.0% Keeping the LP oscillator ON at all times allows for a 0001 + 1.5% fast switch to the 32 kHz system clock for lower power 0000 Center Frequency (oscillator is operation. Returning to the faster main oscillator will running at calibrated frequency) still require a start-up time 1111 - 1.5% 19.2.4 PHASE-LOCKED LOOP (PLL) 1110 - 3.0% 1101 - 4.5% The PLL multiplies the clock that is generated by the 1100 - 6.0% primary oscillator. The PLL is selectable to have either gains of x4, x8, and x16. Input and output frequency 1011 - 7.5% ranges are summarized in Table19-3. 1010 - 9.0% 1001 - 10.5% TABLE 19-3: PLL FREQUENCY RANGE 1000 - 12.0% PLL FIN FOUT 19.2.6 LOW-POWER RC OSCILLATOR Multiplier (LPRC) 4 MHz-10 MHz x4 16 MHz-40 MHz 4 MHz-10 MHz x8 32 MHz-80 MHz The LPRC oscillator is a component of the Watchdog Timer (WDT) and oscillates at a nominal frequency of 4 MHz-7.5 MHz x16 64 MHz-120 MHz 512 kHz. The LPRC oscillator is the clock source for The PLL features a lock output which is asserted when the Power-up Timer (PWRT) circuit, WDT, and clock the PLL enters a phase locked state. Should the loop monitor circuits. It may also be used to provide a low fall out of lock (e.g., due to noise), the lock signal will be frequency clock source option for applications where rescinded. The state of this signal is reflected in the power consumption is critical and timing accuracy is read-only LOCK bit in the OSCCON register. not required The LPRC oscillator is always enabled at a Power-on 19.2.5 FAST RC OSCILLATOR (FRC) Reset because it is the clock source for the PWRT. The FRC oscillator is a fast (7.37 MHz ±2% nominal) After the PWRT expires, the LPRC oscillator will remain internal RC oscillator. This oscillator is intended to on if one of the following is true: provide reasonable device operating speeds without • The Fail-Safe Clock Monitor is enabled the use of an external crystal, ceramic resonator or RC network. • The WDT is enabled • The LPRC oscillator is selected as the system The dsPIC30F operates from the FRC oscillator when clock via the COSC<1:0> control bits in the the current oscillator selection control bits in the OSCCON register OSCCON register (OSCCON<13:12>) are set to ‘01’. If one of the above conditions is not true, the LPRC will The four bit field specified by TUN<3:0> (OSCCON shut-off after the PWRT expires. <15:14> and OSCCON<11:10>) allows the user to tune the internal fast RC oscillator (nominal 7.37MHz). The Note1: OSC2 pin function is determined by the user can tune the FRC oscillator within a range of -12% Primary Oscillator mode selection (or -960 kHz) to +10.5% (or +840 kHz) in steps of (FPR<3:0>). 1.50% around the factory calibrated setting, see 2: OSC1 pin cannot be used as an I/O pin Table19-4. even if the secondary oscillator or an Note: OSCTUN functionality has been provided internal clock source is selected at all to help customers compensate for times. temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. © 2011 Microchip Technology Inc. DS70118J-page 125

dsPIC30F2010 19.2.7 FAIL-SAFE CLOCK MONITOR The OSCCON register holds the control and Status bits related to clock switching. The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator • COSC<1:0>: Read-only status bits always reflect failure. The FSCM function is enabled by appropriately the current oscillator group in effect. programming the FCKSM Configuration bits (Clock • NOSC<1:0>: Control bits which are written to Switch and Monitor Selection bits) in the FOSC device indicate the new oscillator group of choice. Configuration register. If the FSCM function is - On POR and BOR, COSC<1:0> and enabled, the LPRC Internal oscillator will run at all NOSC<1:0> are both loaded with the times (except during Sleep mode) and will not be Configuration bit values FOS<1:0>. subject to control by the SWDTEN bit. • LOCK: The LOCK status bit indicates a PLL lock. In the event of an oscillator failure, the FSCM will gen- • CF: Read-only status bit indicating if a clock fail erate a clock failure trap event and will switch the sys- detect has occurred. tem clock over to the FRC oscillator. The user will then • OSWEN: Control bit changes from a ‘0’ to a ‘1’ have the option to either attempt to restart the oscillator when a clock transition sequence is initiated. or execute a controlled shutdown. The user may decide Clearing the OSWEN control bit will abort a clock to treat the trap as a warm Reset by simply loading the transition in progress (used for hang-up Reset address into the oscillator fail trap vector. In this situations). event, the CF (Clock Fail) status bit (OSCCON<3>) is also set whenever a clock failure is recognized. If Configuration bits FCKSM<1:0> = 1x, then the clock switching and fail-safe clock monitor functions are In the event of a clock failure, the WDT is unaffected disabled. This is the default Configuration bit setting. and continues to run on the LPRC clock. If clock switching is disabled, then the FOS<1:0> and If the oscillator has a very slow start-up time coming FPR<3:0> bits directly control the oscillator selection out of POR, BOR or Sleep, it is possible that the and the COSC<1:0> bits do not control the clock PWRT timer will expire before the oscillator has selection. However, these bits will reflect the clock started. In such cases, the FSCM will be activated and source selection. the FSCM will initiate a clock failure trap, and the COSC<1:0> bits are loaded with FRC oscillator selec- Note: The application should not attempt to tion. This will effectively shut-off the original oscillator switch to a clock of frequency lower than that was trying to start. 100 kHz when the fail-safe clock monitor is enabled. If such clock switching is The user may detect this situation and restart the performed, the device may generate an oscillator in the clock fail trap ISR. oscillator fail trap and switch to the Fast Upon a clock failure detection, the FSCM module will RC oscillator. initiate a clock switch to the FRC Oscillator as follows: 1. The COSC bits (OSCCON<13:12>) are loaded 19.2.8 PROTECTION AGAINST with the FRC Oscillator selection value. ACCIDENTAL WRITES TO OSCCON 2. CF bit is set (OSCCON<3>). A write to the OSCCON register is intentionally made 3. OSWEN control bit (OSCCON<0>) is cleared. difficult because it controls clock switching and clock scaling. For the purpose of clock switching, the clock sources are sectioned into four groups: To write to the OSCCON low byte, the following code sequence must be executed without any other • Primary instructions in between: • Secondary • Internal FRC Byte Write 0x46 to OSCCON low Byte Write 0x57 to OSCCON low • Internal LPRC Byte Write is allowed for one instruction cycle. Write the The user can switch between these functional groups, desired value or use bit manipulation instruction. but cannot switch between options within a group. If the primary group is selected, then the choice within the To write to the OSCCON high byte, the following group is always determined by the FPR<3:0> instructions must be executed without any other Configuration bits. instructions in between: Byte Write 0x78 to OSCCON high Byte Write 0x9A to OSCCON high Byte Write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. DS70118J-page 126 © 2011 Microchip Technology Inc.

dsPIC30F2010 19.3 Reset 19.3.1 POR: POWER-ON RESET The dsPIC30F2010 differentiates between various A power-on event will generate an internal POR pulse kinds of Reset: when a VDD rise is detected. The Reset pulse will occur at the POR circuit threshold voltage (VPOR), which is a) Power-on Reset (POR) nominally 1.85V. The device supply voltage character- b) MCLR Reset during normal operation istics must meet specified starting voltage and rise rate c) MCLR Reset during Sleep requirements. The POR pulse will Reset a POR timer d) Watchdog Timer (WDT) Reset (during normal and place the device in the Reset state. The POR also operation) selects the device clock source identified by the oscillator configuration fuses. e) Programmable Brown-out Reset (BOR) f) RESET Instruction The POR circuit inserts a small delay, TPOR, which is nominally 10 μs and ensures that the device bias cir- g) Reset cause by trap lockup (TRAPR) cuits are stable. Furthermore, a user selected power- h) Reset caused by illegal opcode, or by using an up time-out (TPWRT) is applied. The TPWRT parameter uninitialized W register as an Address Pointer is based on device Configuration bits and can be 0 ms (IOPUWR) (no delay), 4 ms, 16 ms, or 64 ms. The total delay is at Different registers are affected in different ways by var- device power-up TPOR + TPWRT. When these delays ious Reset conditions. Most registers are not affected have expired, SYSRST will be negated on the next by a WDT wake-up, since this is viewed as the resump- leading edge of the Q1 clock, and the PC will jump to tion of normal operation. Status bits from the RCON the Reset vector. register are set or cleared differently in different Reset The timing for the SYSRST signal is shown in situations, as indicated in Table19-5. These bits are Figure19-3 through Figure19-5. used in software to determine the nature of the Reset. A block diagram of the on-chip Reset circuit is shown in Figure19-2. A MCLR noise filter is provided in the MCLR Reset path. The filter detects and ignores small pulses. Internally generated Resets do not drive MCLR pin low. FIGURE 19-2: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Digital Glitch Filter MCLR Sleep or Idle WDT Module VDD Rise POR S Detect VDD Brown-out BOR Reset BOREN R Q SYSRST Trap Conflict Illegal Opcode/ Uninitialized W Register © 2011 Microchip Technology Inc. DS70118J-page 127

dsPIC30F2010 FIGURE 19-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset FIGURE 19-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset FIGURE 19-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TOST OST TIME-OUT TPWRT PWRT TIME-OUT INTERNAL Reset DS70118J-page 128 © 2011 Microchip Technology Inc.

dsPIC30F2010 19.3.1.1 POR with Long Crystal Start-up Time A BOR will generate a Reset pulse which will reset the (with FSCM Enabled) device. The BOR will select the clock source, based on the device Configuration bit values (FOS<1:0> and The oscillator start-up circuitry is not linked to the POR FPR<3:0>). Furthermore, if an Oscillator mode is circuitry. Some crystal circuits (especially low fre- selected, the BOR will activate the Oscillator Start-up quency crystals) will have a relatively long start-up Timer (OST). The system clock is held until OST time. Therefore, one or more of the following conditions expires. If the PLL is used, then the clock will be held is possible after the POR timer and the PWRT have until the LOCK bit (OSCCON<5>) is ‘1’. expired: Concurrently, the POR time-out (TPOR) and the PWRT • The oscillator circuit has not begun to oscillate. time-out (TPWRT) will be applied before the internal • The oscillator start-up timer has NOT expired (if a Reset is released. If TPWRT = 0 and a crystal oscillator crystal oscillator is used). is being used, then a nominal delay of TFSCM = 100 μs • The PLL has not achieved a LOCK (if PLL is is applied. The total delay in this case is (TPOR + used). TFSCM). If the FSCM is enabled and one of the above conditions The BOR status bit (RCON<1>) will be set to indicate is true, then a clock failure trap will occur. The device that a BOR has occurred. The BOR circuit, if enabled, will automatically switch to the FRC oscillator and the will continue to operate while in Sleep or Idle modes user can switch to the desired crystal oscillator in the and will reset the device should VDD fall below the BOR trap ISR. threshold voltage. 19.3.1.2 Operating without FSCM and PWRT FIGURE 19-6: EXTERNAL POWER-ON If the FSCM is disabled and the Power-up Timer RESET CIRCUIT (FOR (PWRT) is also disabled, then the device will exit rap- SLOW VDD POWER-UP) idly from Reset on power-up. If the clock source is VDD FRC, LPRC, EXTRC, or EC, it will be active immediately. D R If the FSCM is disabled and the system clock has not R1 MCLR started, the device will be in a frozen state at the Reset vector until the system clock starts. From the user’s C dsPIC30F perspective, the device will appear to be in Reset until a system clock is available. Note1: External Power-on Reset circuit is 19.3.2 BOR: PROGRAMMABLE required only if the VDD power-up slope BROWN-OUT RESET is too slow. The diode D helps discharge The BOR module is based on an internal voltage refer- the capacitor quickly when VDD powers ence circuit. The main purpose of the BOR module is to down. generate a device Reset when a brown-out condition 2: R should be suitably chosen so as to occurs. Brown-out conditions are generally caused by make sure that the voltage drop across glitches on the AC mains (i.e., missing portions of the R does not violate the device’s electrical AC cycle waveform due to bad power transmission specification. lines or voltage sags due to excessive current draw 3: R1 should be suitably chosen so as to when a large inductive load is turned on). limit any current flowing into MCLR from The BOR module allows selection of one of the external capacitor C, in the event of following voltage trip points: MCLR/VPP pin breakdown due to Elec- • 2.6V-2.71V trostatic Discharge (ESD) or Electrical Overstress (EOS). • 4.1V-4.4V • 4.58V-4.73V Note: Dedicated supervisory devices, such as Note: The BOR voltage trip points indicated here the MCP1XX and MCP8XX, may also be are nominal values provided for design used as an external Power-on Reset guidance only. circuit. © 2011 Microchip Technology Inc. DS70118J-page 129

dsPIC30F2010 Table19-5 shows the Reset conditions for the RCON Register. Since the control bits within the RCON regis- ter are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. TABLE 19-5: INITIALIZATION CONDITION FOR RCON REGISTER CASE 1 Program Condition TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR Counter Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1 Brown-out Reset 0x000000 0 0 0 0 0 0 0 0 1 MCLR Reset during normal 0x000000 0 0 1 0 0 0 0 0 0 operation Software Reset during 0x000000 0 0 0 1 0 0 0 0 0 normal operation MCLR Reset during Sleep 0x000000 0 0 1 0 0 0 1 0 0 MCLR Reset during Idle 0x000000 0 0 1 0 0 1 0 0 0 WDT Time-out Reset 0x000000 0 0 0 0 1 0 0 0 0 WDT Wake-up PC + 2 0 0 0 0 1 0 1 0 0 Interrupt Wake-up from PC + 2(1) 0 0 0 0 0 0 1 0 0 Sleep Clock Failure Trap 0x000004 0 0 0 0 0 0 0 0 0 Trap Reset 0x000000 1 0 0 0 0 0 0 0 0 Illegal Operation Trap 0x000000 0 1 0 0 0 0 0 0 0 Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. Table19-6 shows a second example of the bit conditions for the RCON Register. In this case, it is not assumed the user has set/cleared specific bits prior to action specified in the condition column. TABLE 19-6: INITIALIZATION CONDITION FOR RCON REGISTER CASE 2 Program Condition TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR Counter Power-on Reset 0x000000 0 0 0 0 0 0 0 1 1 Brown-out Reset 0x000000 u u u u u u u 0 1 MCLR Reset during normal 0x000000 u u 1 0 0 0 0 u u operation Software Reset during 0x000000 u u 0 1 0 0 0 u u normal operation MCLR Reset during Sleep 0x000000 u u 1 u 0 0 1 u u MCLR Reset during Idle 0x000000 u u 1 u 0 1 0 u u WDT Time-out Reset 0x000000 u u 0 0 1 0 0 u u WDT Wake-up PC + 2 u u u u 1 u 1 u u Interrupt Wake-up from PC + 2(1) u u u u u u 1 u u Sleep Clock Failure Trap 0x000004 u u u u u u u u u Trap Reset 0x000000 1 u u u u u u u u Illegal Operation Reset 0x000000 u 1 u u u u u u u Legend: u = unchanged Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70118J-page 130 © 2011 Microchip Technology Inc.

dsPIC30F2010 19.4 Watchdog Timer (WDT) The processor wakes up from Sleep if at least one of the following conditions has occurred: 19.4.1 WATCHDOG TIMER OPERATION • any interrupt that is individually enabled and The primary function of the Watchdog Timer (WDT) is meets the required priority level to reset the processor in the event of a software • any Reset (POR, BOR and MCLR) malfunction. The WDT is a free running timer, which • WDT time-out runs off an on-chip RC oscillator, requiring no external On waking up from Sleep mode, the processor will component. Therefore, the WDT timer will continue to restart the same clock that was active prior to entry operate even if the main processor clock (e.g., the into Sleep mode. When clock switching is enabled, crystal oscillator) fails. bits COSC<1:0> will determine the oscillator source 19.4.2 ENABLING AND DISABLING THE that will be used on wake-up. If clock switch is WDT disabled, then there is only one system clock. The Watchdog Timer can be “Enabled” or “Disabled” Note: If a POR or BOR occurred, the selection of only through a Configuration bit (FWDTEN) in the the oscillator is based on the FOS<1:0> Configuration register FWDT. and FPR<3:0> Configuration bits. Setting FWDTEN = 1 enables the Watchdog Timer. If the clock source is an oscillator, the clock to the The enabling is done when programming the device. device will be held off until OST times out (indicating a By default, after chip-erase, FWDTEN bit = 1. Any stable oscillator). If PLL is used, the system clock is device programmer capable of programming held off until LOCK = 1 (indicating that the PLL is dsPIC30F devices allows programming of this and stable). In either case, TPOR, TLOCK and TPWRT delays other Configuration bits. are applied. If enabled, the WDT will increment until it overflows or If EC, FRC, LPRC or ERC oscillators are used, then a “times out”. A WDT time-out will force a device Reset delay of TPOR (~ 10 μs) is applied. This is the smallest (except during Sleep). To prevent a WDT time-out, the delay possible on wake-up from Sleep. user must clear the Watchdog Timer using a CLRWDT Moreover, if LP oscillator was active during Sleep, and instruction. LP is the oscillator used on wake-up, then the start-up If a WDT times out during Sleep, the device will wake- delay will be equal to TPOR. PWRT delay and OST up. The WDTO bit in the RCON register will be cleared timer delay are not applied. In order to have the small- to indicate a wake-up resulting from a WDT time-out. est possible start-up delay when waking up from Sleep, one of these faster wake-up options should be selected Setting FWDTEN = 0 allows user software to enable/ before entering Sleep. disable the Watchdog Timer via the SWDTEN (RCON<5>) control bit. Any interrupt that is individually enabled (using the cor- responding IE bit) and meets the prevailing priority 19.5 Power-Saving Modes level will be able to wake-up the processor. The proces- sor will process the interrupt and branch to the ISR. There are two power-saving states that can be entered The Sleep status bit in RCON register is set upon through the execution of a special instruction, PWRSAV. wake-up. These are: Sleep and Idle. Note: In spite of various delays applied (TPOR, The format of the PWRSAV instruction is as follows: TLOCK and TPWRT), the crystal oscillator PWRSAV <parameter>, where ‘parameter’ defines (and PLL) may not be active at the end of Idle or Sleep mode. the time-out (e.g., for low-frequency crys- tals. In such cases), if FSCM is enabled, 19.5.1 SLEEP MODE then the device will detect this as a clock failure and process the clock failure trap, In Sleep mode, the clock to the CPU and peripherals is the FRC oscillator will be enabled, and the shutdown. If an on-chip oscillator is being used, it is user will have to re-enable the crystal shutdown. oscillator. If FSCM is not enabled, then the The fail-safe clock monitor is not functional during device will simply suspend execution of Sleep, since there is no clock to monitor. However, code until the clock is stable, and will LPRC clock remains active if WDT is operational during remain in Sleep until the oscillator clock Sleep. has started. The Brown-out protection circuit and the Low Voltage Detect circuit, if enabled, will remain functional during Sleep. © 2011 Microchip Technology Inc. DS70118J-page 131

dsPIC30F2010 All Resets will wake-up the processor from Sleep 3. FBORPOR (0xF80004): BOR and POR mode. Any Reset, other than POR, will set the Sleep Configuration Register status bit. In a POR, the Sleep bit is cleared. 4. FGS (0xF8000A): General Code Segment If Watchdog Timer is enabled, then the processor will Configuration Register wake-up from Sleep mode upon WDT time-out. The 5. FICD (0xF8000C): Debug Configuration Sleep and WDTO status bits are both set. Register The placement of the Configuration bits is 19.5.2 IDLE MODE automatically handled when you select the device in In Idle mode, the clock to the CPU is shutdown while your device programmer. The desired state of the peripherals keep running. Unlike Sleep mode, the clock Configuration bits may be specified in the source code source remains active. (dependent on the language tool used), or through the Several peripherals have a control bit in each module, programming interface. After the device has been that allows them to operate during Idle. programmed, the application software may read the Configuration bit values through the table read LPRC fail-safe clock remains active if clock failure instructions. For additional information, please refer to detect is enabled. the programming specifications of the device. The processor wakes up from Idle if at least one of the Note: If the code protection configuration fuse following conditions is true: bits (FGS<GCP> and FGS<GWRP>) • on any interrupt that is individually enabled (IE bit have been programmed, an erase of the is ‘1’) and meets the required priority level entire code-protected device is only • on any Reset (POR, BOR, MCLR) possible at voltages VDD ≥ 4.5V. • on WDT time-out 19.7 In-Circuit Debugger Upon wake-up from Idle mode, the clock is reapplied to the CPU and instruction execution begins immediately, When MPLAB® ICD 2 is selected as a Debugger, the starting with the instruction following the PWRSAV In-Circuit Debugging functionality is enabled. This instruction. function allows simple debugging functions when used Any interrupt that is individually enabled (using IE bit) with MPLAB IDE. When the device has this feature and meets the prevailing priority level will be able to enabled, some of the resources are not available for wake-up the processor. The processor will process the general use. These resources include the first 80 bytes interrupt and branch to the ISR. The Idle status bit in of data RAM and two I/O pins. RCON register is set upon wake-up. One of four pairs of debug I/O pins may be selected by Any Reset, other than POR, will set the Idle status bit. the user using configuration options in MPLAB IDE. On a POR, the Idle bit is cleared. These pin pairs are named EMUD/EMUC, EMUD1/ EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3. If Watchdog Timer is enabled, then the processor will wake-up from Idle mode upon WDT time-out. The Idle In each case, the selected EMUD pin is the Emulation/ and WDTO status bits are both set. Debug Data line, and the EMUC pin is the Emulation/ Debug Clock line. These pins will interface to the Unlike wake-up from Sleep, there are no time delays MPLAB ICD 2 module available from Microchip. The involved in wake-up from Idle. selected pair of Debug I/O pins is used by MPLAB ICD2 to send commands and receive responses, as 19.6 Device Configuration Registers well as to send and receive data. To use the In-Circuit The Configuration bits in each device Configuration Debugger function of the device, the design must register specify some of the device modes and are pro- implement ICSP connections to MCLR, VDD, VSS, grammed by a device programmer, or by using the In- PGC, PGD and the selected EMUDx/EMUCx pin pair. Circuit Serial Programming (ICSP) programming capa- This gives rise to two possibilities: bility feature of the device. Each device Configuration 1. If EMUD/EMUC is selected as the Debug I/O pin register is a 24-bit register, but only the lower 16 bits of pair, then only a 5-pin interface is required, as each register are used to hold configuration data. the EMUD and EMUC pin functions are multi- There are five device Configuration registers available plexed with the PGD and PGC pin functions in to the user: all dsPIC30F devices. 1. FOSC (0xF80000): Oscillator Configuration 2. If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/ Register EMUC3 is selected as the Debug I/O pin pair, 2. FWDT (0xF80002): Watchdog Timer then a 7-pin interface is required, as the Configuration Register EMUDx/EMUCx pin functions (x = 1, 2 or 3) are not multiplexed with the PGD and PGC pin functions. DS70118J-page 132 © 2011 Microchip Technology Inc.

© TABLE 19-7: SYSTEM INTEGRATION REGISTER MAP(1) 2 01 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State 1 M RCON 0740 TRAPR IOPUWR BGST — — — — — EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Depends on type of Reset ic ro OSCCON 0742 TUN3 TUN2 COSC<1:0> TUN1 TUN0 NOSC<1:0> POST<1:0> LOCK — CF — LPOSCEN OSWEN Depends on Configuration bits c h Legend: — = unimplemented bit ip T Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. e c hn TABLE 19-8: DEVICE CONFIGURATION REGISTER MAP(1) o lo g Name Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 y Inc FOSC F80000 FCKSM<1:0> — — — — FOS<1:0> — — — — FPR<3:0> . FWDT F80002 FWDTEN — — — — — — — — — FWPSA<1:0> FWPSB<3:0> FBORPOR F80004 MCLREN — — — — PWMPIN HPOL LPOL BOREN — BORV<1:0> — — FPWRT<1:0> FBS F80006 — — Reserved(2) — — — Reserved(2) — — — — Reserved(2) FSS F80008 — — Reserved(2) — — Reserved(2) — — — — Reserved(2) FGS F8000A — — — — — — — — — — — — — Reserved(2) GCP GWRP FICD F8000C BKBUG COE — — — — — — — — — — — — ICS<1:0> Legend: — = unimplemented bit Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 2: Reserved bits read as ‘1’ and must be programmed as ‘1’. d s P I C 3 D 0 S 7 F 0 1 1 2 8 J -p 0 a g 1 e 1 0 3 3

dsPIC30F2010 NOTES: DS70118J-page 134 © 2011 Microchip Technology Inc.

dsPIC30F2010 20.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: Note: This data sheet summarizes features of • The W register (with or without an address modi- this group ofdsPIC30F devices and is not fier) or file register (specified by the value of ‘Ws’ intended to be a complete reference or ‘f’) source. For more information on the CPU, • The bit in the W register or file register peripherals, register descriptions and (specified by a literal value, or indirectly by the general device functionality, refer to the contents of register ‘Wb’) “dsPIC30F Family Reference Manual” (DS70046). For more information on the The literal instructions that involve data movement may device instruction set and programming, use some of the following operands: refer to the “16-bit MCU and DSC Pro- • A literal value to be loaded into a W register or file grammer’s Reference Manual” register (specified by the value of ‘k’) (DS70157). • The W register or file register where the literal The dsPIC30F instruction set adds many value is to be loaded (specified by ‘Wb’ or ‘f’) enhancements to the previous PIC® MCU instruction However, literal instructions that involve arithmetic or sets, while maintaining an easy migration from PIC logical operations use some of the following operands: MCU instruction sets. • The first source operand, which is a register ‘Wb’ Most instructions are a single program memory word without any address modifier (24 bits). Only three instructions require two program • The second source operand, which is a literal memory locations. value Each single-word instruction is a 24-bit word divided • The destination of the result (only if not the same into an 8-bit opcode which specifies the instruction as the first source operand), which is typically a type, and one or more operands which further specify register ‘Wd’ with or without an address modifier the operation of the instruction. The MAC class of DSP instructions may use some of the The instruction set is highly orthogonal and is grouped following operands: into five basic categories: • The accumulator (A or B) to be used (required • Word or byte-oriented operations operand) • Bit-oriented operations • The W registers to be used as the two operands • Literal operations • The X and Y address space prefetch operations • DSP operations • The X and Y address space prefetch destinations • Control operations • The accumulator write-back destination Table20-1 shows the general symbols used in The other DSP instructions do not involve any describing the instructions. multiplication, and may include: The dsPIC30F instruction set summary in Table20-2 • The accumulator to be used (required) lists all the instructions along with the status flags • The source or destination operand (designated as affected by each instruction. Wso or Wdo, respectively) with or without an Most word or byte-oriented W register instructions address modifier (including barrel shift instructions) have three • The amount of shift, specified by a W register ‘Wn’ operands: or a literal value • The first source operand, which is typically a The control instructions may use some of the following register ‘Wb’ without any address modifier operands: • The second source operand, which is typically a • A program memory address register ‘Ws’ with or without an address modifier • The mode of the table read and table write • The destination of the result, which is typically a instructions register ‘Wd’ with or without an address modifier All instructions are a single word, except for certain However, word or byte-oriented file register instructions double word instructions, which were made double have two operands: word instructions so that all the required information is • The file register specified by the value ‘f’ available in these 48 bits. In the second word, the • The destination, which could either be the file 8MSbs are ‘0’s. If this second word is executed as an register ‘f’ or the W0 register, which is denoted as instruction (by itself), it will execute as a NOP. ‘WREG’ © 2011 Microchip Technology Inc. DS70118J-page 135

dsPIC30F2010 Most single-word instructions are executed in a single three cycles if the skip is performed, depending on instruction cycle, unless a conditional test is true or the whether the instruction being skipped is a single-word program counter is changed as a result of the instruc- or two-word instruction. Moreover, double word moves tion. In these cases, the execution takes two instruction require two cycles. The double word instructions cycles with the additional instruction cycle(s) executed execute in two instruction cycles. as a NOP. Notable exceptions are the BRA (uncondi- Note: For more details on the instruction set, tional/computed branch), indirect CALL/GOTO, all table refer to the “16-bit MCU and DSC Pro- reads and writes and RETURN/RETFIE instructions, grammer’s Reference Manual” which are single-word instructions, but take two or (DS70157). three cycles. Certain instructions that involve skipping over the subsequent instruction, require either two or TABLE 20-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator write-back destination address register ∈ {W13, [W13] + = 2} bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...15} C, DC, N, OV, Z MCU status bits: Carry, Digit Carry, Negative, Overflow, Zero Expr Absolute address, label or expression (resolved by the linker) f File register address ∈ {0x0000...0x1FFF} lit1 1-bit unsigned literal ∈ {0,1} lit4 4-bit unsigned literal ∈ {0...15} lit5 5-bit unsigned literal ∈ {0...31} lit8 8-bit unsigned literal ∈ {0...255} lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal ∈ {0...16384} lit16 16-bit unsigned literal ∈ {0...65535} lit23 23-bit unsigned literal ∈ {0...8388608}; LSB must be 0 None Field does not require an entry, may be blank OA, OB, SA, SB DSP status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate PC Program Counter Slit10 10-bit signed literal ∈ {-512...511} Slit16 16-bit signed literal ∈ {-32768...32767} Slit6 6-bit signed literal ∈ {-16...16} DS70118J-page 136 © 2011 Microchip Technology Inc.

dsPIC30F2010 TABLE 20-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wb Base W register ∈ {W0..W15} Wd Destination W register ∈ {Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd]} Wdo Destination W register ∈ {Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb]} Wm,Wn Dividend, Divisor working register pair (direct addressing) Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈ {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈ {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 working registers ∈ {W0..W15} Wnd One of 16 destination working registers ∈ {W0..W15} Wns One of 16 source working registers ∈ {W0..W15} WREG W0 (working register used in file register instructions) Ws Source W register ∈ {Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws]} Wso Source W register ∈ {Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb]} Wx X data space prefetch address register for DSP instructions ∈ {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12],none} Wxd X data space prefetch destination register for DSP instructions ∈ {W4..W7} Wy Y data space prefetch address register for DSP instructions ∈ {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Wyd Y data space prefetch destination register for DSP instructions ∈ {W4..W7} © 2011 Microchip Technology Inc. DS70118J-page 137

dsPIC30F2010 TABLE 20-2: INSTRUCTION SET OVERVIEW Base # of Assembly # of Status Flags Instr Assembly Syntax Description word Mnemonic cycles Affected # s 1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB 2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z 3 AND AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z 4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z 5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None 6 BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if greater than or equal 1 1 (2) None BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None BRA GT,Expr Branch if greater than 1 1 (2) None BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None BRA LE,Expr Branch if less than or equal 1 1 (2) None BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None BRA LT,Expr Branch if less than 1 1 (2) None BRA LTU,Expr Branch if unsigned less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OA,Expr Branch if accumulator A overflow 1 1 (2) None BRA OB,Expr Branch if accumulator B overflow 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA SA,Expr Branch if accumulator A saturated 1 1 (2) None BRA SB,Expr Branch if accumulator B saturated 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None 7 BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None 8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None 9 BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None 10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3) DS70118J-page 138 © 2011 Microchip Technology Inc.

dsPIC30F2010 TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base # of Assembly # of Status Flags Instr Assembly Syntax Description word Mnemonic cycles Affected # s 11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) 12 BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z 13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z 14 CALL CALL lit23 Call subroutine 2 2 None CALL Wn Call indirect subroutine 1 2 None 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB 16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep 17 COM COM f f = f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z 18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb - Ws) 1 1 C,DC,N,OV,Z 19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z 20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z (Wb - Ws - C) 21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1 None (2 or 3) 22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1 None (2 or 3) 23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1 None (2 or 3) ≠ 24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if 1 1 None (2 or 3) 25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C 26 DEC DEC f f = f - 1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f -1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws - 1 1 1 C,DC,N,OV,Z 27 DEC2 DEC2 f f = f - 2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f -2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws - 2 1 1 C,DC,N,OV,Z 28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None 29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C, OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C, OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C, OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C, OV 30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C, OV 31 DO DO #lit14,Expr Do code to PC+Expr, lit14 + 1 times 2 2 None DO Wn,Expr Do code to PC+Expr, (Wn) + 1 times 2 2 None 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB © 2011 Microchip Technology Inc. DS70118J-page 139

dsPIC30F2010 TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base # of Assembly # of Status Flags Instr Assembly Syntax Description word Mnemonic cycles Affected # s 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indirect 1 2 None 39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z 41 IOR IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 43 LNK LNK #lit14 Link frame pointer 1 1 None 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z 45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd, Multiply and Accumulate 1 1 OA,OB,OAB, AWB SA,SB,SAB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB 46 MOV MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 N,Z MOV f,WREG Move f to WREG 1 1 N,Z MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N,Z MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None 47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store accumulator 1 1 None 48 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd, Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, AWB SA,SB,SAB 51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * 1 1 None unsigned(Ws) MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None signed(Ws) MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(Ws) MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * 1 1 None unsigned(lit5) MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(lit5) MUL f W3:W2 = f * WREG 1 1 None DS70118J-page 140 © 2011 Microchip Technology Inc.

dsPIC30F2010 TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base # of Assembly # of Status Flags Instr Assembly Syntax Description word Mnemonic cycles Affected # s 52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f = f + 1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 53 NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None 54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd 1 2 None + 1) POP.S Pop Shadow Registers 1 1 All 55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None 56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep 57 RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None 58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None 59 RESET RESET Software device Reset 1 1 None 60 RETFIE RETFIE Return from interrupt 1 3 (2) None 61 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None 62 RETURN RETURN Return from Subroutine 1 3 (2) None 63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z 64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z 65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z 66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None 68 SE SE Ws,Wnd Wnd = sign extended Ws 1 1 C,N,Z 69 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None 70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB 71 SL SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z © 2011 Microchip Technology Inc. DS70118J-page 141

dsPIC30F2010 TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base # of Assembly # of Status Flags Instr Assembly Syntax Description word Mnemonic cycles Affected # s 72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f - WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f - WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn - lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb - Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb - lit5 1 1 C,DC,N,OV,Z 73 SUBB SUBB f f = f - WREG - (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f - WREG - (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn - lit10 - (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb - Ws - (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb - lit5 - (C) 1 1 C,DC,N,OV,Z 74 SUBR SUBR f f = WREG - f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG - f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws - Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 - Wb 1 1 C,DC,N,OV,Z 75 SUBBR SUBBR f f = WREG - f - (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG - f - (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws - Wb - (C) 1 1 C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 - Wb - (C) 1 1 C,DC,N,OV,Z 76 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None SWAP Wn Wn = byte swap Wn 1 1 None 77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None 78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None 79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 81 ULNK ULNK Unlink frame pointer 1 1 None 82 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z 83 ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C,Z,N DS70118J-page 142 © 2011 Microchip Technology Inc.

dsPIC30F2010 21.0 DEVELOPMENT SUPPORT 21.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® • Integrated Development Environment operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2011 Microchip Technology Inc. DS70118J-page 143

dsPIC30F2010 21.2 MPLAB C Compilers for Various 21.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 21.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 21.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 21.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS70118J-page 144 © 2011 Microchip Technology Inc.

dsPIC30F2010 21.7 MPLAB SIM Software Simulator 21.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip's most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is con- The MPLAB SIM Software Simulator fully supports nected to the design engineer's PC using a high-speed symbolic debugging using the MPLAB CCompilers, USB 2.0 interface and is connected to the target with a and the MPASM and MPLAB Assemblers. The soft- connector compatible with the MPLAB ICD 2 or MPLAB ware simulator offers the flexibility to develop and REAL ICE systems (RJ-11). MPLAB ICD 3 supports all debug code outside of the hardware laboratory envi- MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 21.10 PICkit 3 In-Circuit Debugger/ Programmer and 21.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and program- MPLAB REAL ICE In-Circuit Emulator System is ming of PIC® and dsPIC® Flash microcontrollers at a Microchip’s next generation high-speed emulator for most affordable price point using the powerful graphical Microchip Flash DSC and MCU devices. It debugs and user interface of the MPLAB Integrated Development programs PIC® Flash MCUs and dsPIC® Flash DSCs Environment (IDE). The MPLAB PICkit 3 is connected with the easy-to-use, powerful graphical user interface of to the design engineer's PC using a full speed USB the MPLAB Integrated Development Environment (IDE), interface and can be connected to the target via an included with each kit. Microchip debug (RJ-11) connector (compatible with The emulator is connected to the design engineer’s PC MPLAB ICD 3 and MPLAB REAL ICE). The connector using a high-speed USB 2.0 interface and is connected uses two device I/O pins and the reset line to imple- to the target with either a connector compatible with in- ment in-circuit debugging and In-Circuit Serial Pro- circuit debugger systems (RJ11) or with the new high- gramming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2011 Microchip Technology Inc. DS70118J-page 145

dsPIC30F2010 21.11 PICkit 2 Development 21.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 21.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS70118J-page 146 © 2011 Microchip Technology Inc.

dsPIC30F2010 22.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. For detailed information about the dsPIC30F architecture and core, refer to “dsPIC30F Family Reference Manual” (DS70046). Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR)...................................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V Voltage on MCLR with respect to VSS (Note 1).........................................................................................0V to +13.25V Total power dissipation (Note 2)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports..................................................................................................................200 mA Note1: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. 2: Maximum allowable current is a function of device maximum power dissipation. See Table22-4. †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2011 Microchip Technology Inc. DS70118J-page 147

dsPIC30F2010 22.1 DC Characteristics TABLE 22-1: OPERATING MIPS VS. VOLTAGE Max MIPS VDD Range Temp Range dsPIC30F2010-30I dsPIC30F2010-20E 4.5-5.5V -40°C to 85°C 30 — 4.5-5.5V -40°C to 125°C — 20 3.0-3.6V -40°C to 85°C 20 — 3.0-3.6V -40°C to 125°C — 15 2.5-3.0V -40°C to 85°C 10 — TABLE 22-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit dsPIC30F2010-30I Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C dsPIC30F2010-20E Operating Junction Temperature Range TJ -40 — +150 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal chip power dissipation: PINT = VDD× ⎝⎛IDD–∑IOH⎠⎞ PD PINT + PI/O W I/O Pin power dissipation: PI/O= ∑({VDD–VOH}× IOH)+∑(VOL× IOL) θ Maximum Allowed Power Dissipation PDMAX (TJ - TA)/ JA W TABLE 22-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes θ Package Thermal Resistance, 28-pin SOIC (SO) JA 48.3 — °C/W 1 θ Package Thermal Resistance, 28-pin QFN JA 33.7 — °C/W 1 θ Package Thermal Resistance, 28-pin SPDIP (SP) JA 42 — °C/W 1 θ Note 1: Junction to ambient thermal resistance, Theta-ja ( JA) numbers are achieved by package simulations. DS70118J-page 148 © 2011 Microchip Technology Inc.

dsPIC30F2010 T ABLE 22-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Operating Voltage(2) DC10 VDD Supply Voltage 2.5 — 5.5 V Industrial temperature DC11 VDD Supply Voltage 3.0 — 5.5 V Extended temperature DC12 VDR RAM Data Retention Voltage(3) 1.75 — — V — DC16 VPOR VDD Start Voltage — — VSS V — to ensure internal Power-on Reset signal DC17 SVDD VDD Rise Rate 0.05 — — V/ms 0-5V in 0.1 sec to ensure internal 0-3V in 60 ms Power-on Reset signal Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which VDD can be lowered without losing RAM data. © 2011 Microchip Technology Inc. DS70118J-page 149

dsPIC30F2010 T ABLE 22-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Parameter Typical Max Units Conditions No. Operating Current (IDD)(1) DC31a 1.6 3 mA 25°C DC31b 1.6 3 mA 85°C 3.3V DC31c 1.6 3 mA 125°C 0.128 MIPS DC31e 3.9 7 mA 25°C LPRC (512 kHz) DC31f 3.5 7 mA 85°C 5V DC31g 3.4 7 mA 125°C DC30a 3 5 mA 25°C DC30b 3 5 mA 85°C 3.3V DC30c 3 5 mA 125°C (1.8 MIPS) DC30e 6 9 mA 25°C FRC (7.37 MHz) DC30f 6 9 mA 85°C 5V DC30g 6 9 mA 125°C DC23a 9 14 mA 25°C DC23b 10 15 mA 85°C 3.3V DC23c 10 15 mA 125°C 4 MIPS EC mode, 4X PLL DC23e 16 24 mA 25°C DC23f 16 24 mA 85°C 5V DC23g 16 24 mA 125°C DC24a 21 32 mA 25°C DC24b 21 32 mA 85°C 3.3V DC24c 21 32 mA 125°C 10 MIPS EC mode, 4X PLL DC24e 35 53 mA 25°C DC24f 36 53 mA 85°C 5V DC24g 36 53 mA 125°C DC27a 39 59 mA 25°C 3.3V DC27b 39 59 mA 85°C DC27d 66 99 mA 25°C 20 MIPS EC mode, 8X PLL DC27e 66 99 mA 85°C 5V DC27f 66 99 mA 125°C DC29a 95 150 mA 25°C 5V 30 MIPS EC mode, 16X PLL DC29b 94 150 mA 85°C Note 1: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating. DS70118J-page 150 © 2011 Microchip Technology Inc.

dsPIC30F2010 TABLE 22-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Parameter Typical Max Units Conditions No. Operating Current (IDD)(1) DC51a 1.5 3.0 mA 25°C DC51b 1.5 3.0 mA 85°C 3.3V DC51c 1.5 3.0 mA 125°C 0.128 MIPS DC51e 4.1 7 mA 25°C LPRC (512 kHz) DC51f 3.6 7 mA 85°C 5V DC51g 3.5 7 mA 125°C DC50a 3 5 mA 25°C DC50b 3 5 mA 85°C 3.3V DC50c 3 5 mA 125°C (1.8 MIPS) DC50e 7 9 mA 25°C FRC (7.37MHz) DC50f 6 9 mA 85°C 5V DC50g 6 9 mA 125°C DC43a 5 9 mA 25°C DC43b 6 9 mA 85°C 3.3V DC43c 6 9 mA 125°C 4 MIPS EC mode, 4X PLL DC43e 10 15 mA 25°C DC43f 10 15 mA 85°C 5V DC43g 10 15 mA 125°C DC44a 11 18 mA 25°C DC44b 12 18 mA 85°C 3.3V DC44c 12 18 mA 125°C 10 MIPS EC mode, 4X PLL DC44e 20 30 mA 25°C DC44f 20 30 mA 85°C 5V DC44g 20 30 mA 125°C DC47a 20 30 mA 25°C 3.3V DC47b 21 30 mA 85°C DC47d 35 45 mA 25°C 20 MIPS EC mode, 8X PLL DC47e 35 45 mA 85°C 5V DC47f 35 45 mA 125°C DC49a 49 65 mA 25°C 5V 30 MIPS EC mode, 16X PLL DC49b 50 65 mA 85°C Note 1: Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base IIDLE current is measured with core off, clock on and all modules turned off. © 2011 Microchip Technology Inc. DS70118J-page 151

dsPIC30F2010 T ABLE 22-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Parameter Typical Max Units Conditions No. Power Down Current (IPD)(1) DC60a 0.05 — μA 25°C DC60b 3 25 μA 85°C 3.3V DC60c 20 50 μA 125°C Base Power Down Current(2) DC60e 0.1 — μA 25°C DC60f 6 35 μA 85°C 5V DC60g 40 200 μA 125°C DC61a 30 45 μA 25°C DC61b 34 51 μA 85°C 3.3V DC61c 46 69 μA 125°C Watchdog Timer Current: ΔIWDT(2) DC61e 35 53 μA 25°C DC61f 39 59 μA 85°C 5V DC61g 40 60 μA 125°C DC62a 4 10 μA 25°C DC62b 5 10 μA 85°C 3.3V DC62c 4 10 μA 125°C Timer 1 w/32 kHz Crystal: ΔITI32(2) DC62e 4 15 μA 25°C DC62f 6 15 μA 85°C 5V DC62g 5 15 μA 125°C DC63a 4 6 μA 25°C DC63b 4 6 μA 85°C 3.3V DC63c 5 7.5 μA 125°C BOR On: ΔIBOR(2) DC63e 10 15 μA 25°C DC63f 9 15 μA 85°C 5V DC63g 10 15 μA 125°C Note 1: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. LVD, BOR, WDT, etc. are all switched off. 2: The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. DS70118J-page 152 © 2011 Microchip Technology Inc.

dsPIC30F2010 TABLE 22-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VIL Input Low Voltage(2) DI10 I/O pins: with Schmitt Trigger buffer VSS — 0.2VDD V DI15 MCLR VSS — 0.2VDD V DI16 OSC1 (in XT, HS and LP modes) VSS — 0.2VDD V DI17 OSC1 (in RC mode)(3) VSS — 0.3VDD V DI18 SDA, SCL VSS — 0.3VDD V SMBus disabled DI19 SDA, SCL VSS — 0.8 V SMBus enabled VIH Input High Voltage(2) DI20 I/O pins: with Schmitt Trigger buffer 0.8VDD — VDD V DI25 MCLR 0.8VDD — VDD V DI26 OSC1 (in XT, HS and LP modes) 0.7VDD — VDD V DI27 OSC1 (in RC mode)(3) 0.9VDD — VDD V DI28 SDA, SCL 0.7VDD — VDD V SMBus disabled DI29 SDA, SCL 2.1 — VDD V SMBus enabled ICNPU CNXX Pull-up Current(2) DI30 50 250 400 μA VDD = 5V, VPIN = VSS IIL Input Leakage Current(2,4,5) DI50 I/O ports — 0.01 ±1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance DI51 Analog input pins — 0.50 ±1.3 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance DI55 MCLR — 0.05 ±5 μA VSS ≤ VPIN ≤ VDD DI56 OSC1 — 0.05 ±7 μA VSS ≤ VPIN ≤ VDD, XT, HS and LP Osc mode Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that the dsPIC30F device be driven with an external clock while in RC mode. 4: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2011 Microchip Technology Inc. DS70118J-page 153

dsPIC30F2010 TABLE 22-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VOL Output Low Voltage(2) DO10 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 5V — — 0.15 V IOL = 2.0 mA, VDD = 3V DO16 OSC2/CLKO — — 0.6 V IOL = 1.6 mA, VDD = 5V (RC or EC Osc mode) — — 0.72 V IOL = 2.0 mA, VDD = 3V VOH Output High Voltage(2) DO20 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 5V VDD - 0.2 — — V IOH = -2.0 mA, VDD = 3V DO26 OSC2/CLKO VDD – 0.7 — — V IOH = -1.3 mA, VDD = 5V (RC or EC Osc mode) VDD - 0.1 — — V IOH = -2.0 mA, VDD = 3V Capacitive Loading Specs on Output Pins(2) DO50 COSC2 OSC2/SOSC2 pin — — 15 pF In XTL, XT, HS and LP modes when external clock is used to drive OSC1. DO56 CIO All I/O pins and OSC2 — — 50 pF RC or EC Osc mode DO58 CB SCL, SDA — — 400 pF In I2C™ mode Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. FIGURE 22-1: BROWN-OUT RESET CHARACTERISTICS VDD (Device not in Brown-out Reset) BO15 BO10 (Device in Brown-out Reset) Reset (due to BOR) Power Up Time-out DS70118J-page 154 © 2011 Microchip Technology Inc.

dsPIC30F2010 TABLE 22-10: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. BO10 VBOR BOR Voltage(2) on BORV = 11(3) — — — V Not in operating VDD transition high to range low BORV = 10 2.6 — 2.71 V — BORV = 01 4.1 — 4.4 V — BORV = 00 4.58 — 4.73 V — BO15 VBHYS — 5 — mV — Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: 11 values not in usable operating range. TABLE 22-11: DC CHARACTERISTICS: PROGRAM AND EEPROM Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Data EEPROM Memory(2) D120 ED Byte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time 0.8 2 2.6 ms RTSP D123 TRETD Characteristic Retention 40 100 — Year Provided no other specifications are violated D124 IDEW IDD During Programming — 10 30 mA Row Erase Program Flash Memory(2) D130 EP Cell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VEB VDD for Bulk Erase 4.5 — 5.5 V D133 VPEW VDD for Erase/Write 3.0 — 5.5 V D134 TPEW Erase/Write Cycle Time 0.8 2 2.6 ms RTSP D135 TRETD Characteristic Retention 40 100 — Year Provided no other specifications are violated D137 IPEW IDD During Programming — 10 30 mA Row Erase D138 IEB IDD During Programming — 10 30 mA Bulk Erase Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2011 Microchip Technology Inc. DS70118J-page 155

dsPIC30F2010 22.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 22-12: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Operating voltage VDD range as described in Table22-1. FIGURE 22-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSC2 Load Condition 2 - for OSC2 VDD/2 RL Pin CL VSS CL Pin RL = 464Ω CL = 50 pF for all pins except OSC2 VSS 5 pF for OSC2 output FIGURE 22-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS40 OS41 DS70118J-page 156 © 2011 Microchip Technology Inc.

dsPIC30F2010 TABLE 22-13: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS10 FOSC External CLKI Frequency(2) DC — 40 MHz EC (External clocks allowed only 4 — 10 MHz EC with 4x PLL in EC mode) 4 — 10 MHz EC with 8x PLL 4 — 7.5 MHz EC with 16x PLL Oscillator Frequency(2) DC — 4 MHz RC 0.4 — 4 MHz XTL 4 — 10 MHz XT 4 — 10 MHz XT with 4x PLL 4 — 10 MHz XT with 8x PLL 4 — 7.5 MHz XT with 16x PLL 10 — 25 MHz HS 31 — 33 kHz LP — 7.37 — MHz FRC internal — 512 — kHz LPRC internal OS20 TOSC TOSC = 1/FOSC — — — — See parameter OS10 for FOSC value OS25 TCY Instruction Cycle Time(2,3) 33 — DC ns See Table22-16 OS30 TosL, External Clock(2) in (OSC1) .45 x TOSC — — ns EC TosH High or Low Time OS31 TosR, External Clock(2) in (OSC1) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(2,4) — 6 10 ns — OS41 TckF CLKO Fall Time(2,4) — 6 10 ns — Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “Max” cycle time limit is “DC” (no clock) for all devices. 4: Measurements are taken in EC or ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). © 2011 Microchip Technology Inc. DS70118J-page 157

dsPIC30F2010 TABLE 22-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5V) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. OS50 FPLLI PLL Input Frequency Range(2) 4 — 10 MHz EC with 4x PLL 4 — 10 MHz EC with 8x PLL 4 — 7.5(3) MHz EC with 16x PLL 4 — 10 MHz XT with 4x PLL 4 — 10 MHz XT with 8x PLL 4 — 7.5(3) MHz XT with 16x PLL OS51 FSYS On-Chip PLL Output(2) 16 — 120 MHz EC, XT modes with PLL OS52 TLOC PLL Start-up Time (Lock Time) — 20 50 μs — Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Limited by device operating frequency range. TABLE 22-15: PLL JITTER Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Characteristic Min Typ(1) Max Units Conditions No. OS61 x4 PLL — 0.251 0.413 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V — 0.251 0.413 % -40°C ≤ TA ≤ +125°C VDD = 3.0 to 3.6V — 0.256 0.47 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V — 0.256 0.47 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V x8 PLL — 0.355 0.584 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V — 0.355 0.584 % -40°C ≤ TA ≤ +125°C VDD = 3.0 to 3.6V — 0.362 0.664 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V — 0.362 0.664 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V x16 PLL — 0.67 0.92 % -40°C ≤ TA ≤ +85°C VDD = 3.0 to 3.6V — 0.632 0.956 % -40°C ≤ TA ≤ +85°C VDD = 4.5 to 5.5V — 0.632 0.956 % -40°C ≤ TA ≤ +125°C VDD = 4.5 to 5.5V Note 1: These parameters are characterized but not tested in manufacturing. DS70118J-page 158 © 2011 Microchip Technology Inc.

dsPIC30F2010 TABLE 22-16: INTERNAL CLOCK TIMING EXAMPLES Clock Oscillator (MFHOzS)C(1 ) TCY (μsec)(2) wM/oIP Ps(L3L) wM PIPLsL( 3x)4 wM PIPLsL( 3x)8 w MPILPLs (x31)6 Mode 0.200 20.0 0.05 — — — 4 1.0 1.0 4.0 8.0 16.0 EC 10 0.4 2.5 10.0 20.0 — 25 0.16 6.25 — — — 4 1.0 1.0 4.0 8.0 16.0 XT 10 0.4 2.5 10.0 20.0 — Note 1: Assumption: Oscillator Postscaler is divided by 1. 2: Instruction Execution Cycle Time: TCY = 1/MIPs. 3: Instruction Execution Frequency: MIPs = (FOSC * PLLx)/4 (since there are 4 Q clocks per instruction cycle). TABLE 22-17: AC CHARACTERISTICS: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. OS63 Internal FRC Accuracy @ FRC Freq. = 7.37 MHz(1) FRC — — ±2.00 % -40°C ≤ TA ≤ +85°C VDD = 3.0-5.5V — — ±5.00 % -40°C ≤ TA ≤ +125°C VDD = 3.0-5.5V Note 1: Frequency calibrated at 7.372 MHz ±2%, 25°C and 5V. TUN <3:0> bits can be used to compensate for temperature drift. TABLE 22-18: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. OS65A -50 — +50 % VDD = 5.0V, ±10% OS65B LPRC @ Freq. = 512 kHz(1) -60 — +60 % VDD = 3.3V, ±10% OS65C -70 — +70 % VDD = 2.5V Note 1: Change of LPRC frequency as VDD changes. © 2011 Microchip Technology Inc. DS70118J-page 159

dsPIC30F2010 FIGURE 22-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure22-2 for load conditions. TABLE 22-19: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1,2,3) Min Typ(4) Max Units Conditions No. DO31 TIOR Port output rise time — 7 20 ns — DO32 TIOF Port output fall time — 7 20 ns — DI35 TINP INTx pin high or low time (output) 20 — — ns — DI40 TRBP CNx high or low time (input) 2 TCY — — — — Note 1: These parameters are asynchronous events not related to any internal clock edges 2: Measurements are taken in RC mode and EC mode where CLKO output is 4 x TOSC. 3: These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. DS70118J-page 160 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 22-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD SY12 MCLR Internal SY10 POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Note: Refer to Figure22-2 for load conditions. Delay TABLE 22-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SY10 TmcL MCLR Pulse Width (low) 2 — — μs -40°C to +85°C SY11 TPWRT Power-up Timer Period 2 4 6 ms -40°C to +85°C, VDD = 5V 8 16 24 User programmable 32 64 96 SY12 TPOR Power-on Reset Delay 3 10 30 μs -40°C to +85°C SY13 TIOZ I/O high-impedance from MCLR — 0.8 1.0 μs — Low or Watchdog Timer Reset SY20 TWDT1 Watchdog Timer Time-out Period 0.6 2.0 3.4 ms VDD = 2.5V TWDT2 (No Prescaler) 0.8 2.0 3.2 ms VDD = 3.3V, ±10% TWDT3 1.0 2.0 3.0 ms VDD = 5V, ±10% SY25 TBOR Brown-out Reset Pulse Width(3) 100 — — μs VDD ≤ VBOR (D034) SY30 TOST Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 900 μs -40°C to +85°C Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure22-1 and Table22-10 for BOR. © 2011 Microchip Technology Inc. DS70118J-page 161

dsPIC30F2010 FIGURE 22-6: BAND GAP START-UP TIME CHARACTERISTICS VBGAP 0V Enable Band Gap (see Note) Band Gap SY40 Stable Note: Band Gap is enabled when FBORPOR<7> is set. TABLE 22-21: BAND GAP START-UP TIME REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SY40 TBGAP Band Gap Start-up Time — 40 65 µs Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. RCON<13>Status bit Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. DS70118J-page 162 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 22-7: TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRX Note: “x” refers to Timer Type A or Timer Type B. Refer to Figure22-2 for load conditions. TABLE 22-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TA10 TTXH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TA15 Synchronous, 10 — — ns with prescaler Asynchronous 10 — — ns TA11 TTXL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TA15 Synchronous, 10 — — ns with prescaler Asynchronous 10 — — ns TA15 TTXP TxCK Input Period Synchronous, TCY + 10 — — ns — no prescaler Synchronous, Greater of: — — — N = prescale with prescaler 20 ns or value (TCY + 40)/N (1, 8, 64, 256) Asynchronous 20 — — ns — OS60 Ft1 SOSC1/T1CK oscillator input DC — 50 kHz — frequency range (oscillator enabled by setting bit TCS (T1CON, bit 1)) TA20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — — Edge to Timer Increment © 2011 Microchip Technology Inc. DS70118J-page 163

dsPIC30F2010 TABLE 22-23: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TB10 TtxH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TB15 Synchronous, 10 — — ns with prescaler TB11 TtxL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TB15 Synchronous, 10 — — ns with prescaler TB15 TtxP TxCK Input Period Synchronous, TCY + 10 — — ns N = prescale no prescaler value Synchronous, Greater of: (1, 8, 64, 256) with prescaler 20 ns or (TCY + 40)/N TB20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — — Edge to Timer Increment TABLE 22-24: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet parameter TC15 TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet parameter TC15 TC15 TtxP TxCK Input Period Synchronous, TCY + 10 — — ns N = prescale no prescaler value Synchronous, Greater of: (1, 8, 64, 256) with prescaler 20 ns or (TCY + 40)/N TC20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — — Edge to Timer Increment DS70118J-page 164 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 22-8: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEB TQ10 TQ11 TQ15 TQ20 POSCNT TABLE 22-25: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. TQ10 TtQH TQCK High Time Synchronous, TCY + 20 — — ns Must also meet with prescaler parameter TQ15 TQ11 TtQL TQCK Low Time Synchronous, TCY + 20 — — ns Must also meet with prescaler parameter TQ15 TQ15 TtQP TQCP Input Period Synchronous, 2 * TCY + 40 — — ns — with prescaler TQ20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY ns — Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing. © 2011 Microchip Technology Inc. DS70118J-page 165

dsPIC30F2010 FIGURE 22-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICX IC10 IC11 IC15 Note: Refer to Figure22-2 for load conditions. TABLE 22-26: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Max Units Conditions No. IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns — With Prescaler 10 — ns IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns — With Prescaler 10 — ns IC15 TccP ICx Input Period (2 TCY + 40)/N — ns N = prescale value (1, 4, 16) Note 1: These parameters are characterized but not tested in manufacturing. FIGURE 22-10: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure22-2 for load conditions. TABLE 22-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. OC10 TccF OCx Output Fall Time — — — ns See parameter DO32 OC11 TccR OCx Output Rise Time — — — ns See parameter DO31 Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70118J-page 166 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 22-11: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 22-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. OC15 TFD Fault Input to PWM I/O — — 50 ns — — Change OC20 TFLT Fault Input Pulse Width 50 — — ns — — Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2011 Microchip Technology Inc. DS70118J-page 167

dsPIC30F2010 FIGURE 22-12: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTA/B MP20 PWMx FIGURE 22-13: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure22-2 for load conditions. TABLE 22-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. MP10 TFPWM PWM Output Fall Time — — — ns See parameter DO32 MP11 TRPWM PWM Output Rise Time — — — ns See parameter DO31 TFD Fault Input ↓ to PWM — — 50 ns — MP20 I/O Change MP30 TFH Minimum Pulse Width 50 — — ns — Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70118J-page 168 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 22-14: QEA/QEB INPUT CHARACTERISTICS TQ36 QEA (input) TQ31 TQ30 TQ35 QEB (input) TQ41 TQ40 TQ31 TQ30 TQ35 QEB Internal TABLE 22-30: QUADRATURE DECODER TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Typ(2) Max Units Conditions No. TQ30 TQUL Quadrature Input Low Time 6 TCY — ns — TQ31 TQUH Quadrature Input High Time 6 TCY — ns — TQ35 TQUIN Quadrature Input Period 12 TCY — ns — TQ36 TQUP Quadrature Phase Period 3 TCY — ns — TQ40 TQUFL Filter Time to Recognize Low, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) TQ41 TQUFH Filter Time to Recognize High, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) Note 1: These parameters are characterized but not tested in manufacturing. 2: N = Index Channel Digital Filter Clock Divide Select Bits. Refer to Section 16. “Quadrature Encoder Interface (QEI)” (DS70063) in the “dsPIC30F Family Reference Manual” (DS70046). © 2011 Microchip Technology Inc. DS70118J-page 169

dsPIC30F2010 FIGURE 22-15: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ50 TQ51 Index Internal TQ55 Position Counter Reset TABLE 22-31: QEI INDEX PULSE TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Max Units Conditions No. TQ50 TqIL Filter Time to Recognize Low, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) TQ51 TqiH Filter Time to Recognize High, 3 * N * TCY — ns N = 1, 2, 4, 16, 32, 64, with Digital Filter 128 and 256 (Note 2) TQ55 Tqidxr Index Pulse Recognized to Position 3 TCY — ns — Counter Reset (Ungated Index) Note 1: These parameters are characterized but not tested in manufacturing. 2: Alignment of Index Pulses to QEA and QEB is shown for Position Counter reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but Index Pulse recognition occurs on falling edge. DS70118J-page 170 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 22-16: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb BIT14 - - - - - -1 LSb SP31 SP30 SDIx MSb IN BIT14 - - - -1 LSb IN SP40 SP41 Note: Refer to Figure22-2 for load conditions. TABLE 22-32: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscL SCKX Output Low Time(3) TCY/2 — — ns See Note 3 SP11 TscH SCKX Output High Time(3) TCY/2 — — ns See Note 3 SP20 TscF SCKX Output Fall Time(4 — — — ns See parameter DO32 SP21 TscR SCKX Output Rise Time(4) — — — ns See parameter DO31 SP30 TdoF SDOX Data Output Fall Time(4) — — — ns See parameter DO32 SP31 TdoR SDOX Data Output Rise Time(4) — — — ns See parameter DO31 SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns — TscL2doV SCKX Edge SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns — TdiV2scL to SCKX Edge SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns — TscL2diL to SCKX Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2011 Microchip Technology Inc. DS70118J-page 171

dsPIC30F2010 FIGURE 22-17: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SCKX (CKP = 1) SP35 SP20 SP21 SDOX MSb BIT14 - - - - - -1 LSb SP40 SP30,SP31 SDIX MSb IN BIT14 - - - -1 LSb IN SP41 Note: Refer to Figure22-2 for load conditions. TABLE 22-33: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscL SCKX output low time(3) TCY/2 — — ns See Note 3 SP11 TscH SCKX output high time(3) TCY/2 — — ns See Note 3 SP20 TscF SCKX output fall time(4) — — — ns See parameter DO32 SP21 TscR SCKX output rise time(4) — — — ns See parameter DO31 SP30 TdoF SDOX data output fall time(4) — — — ns See parameter DO32 SP31 TdoR SDOX data output rise time(4) — — — ns See parameter DO31 SP35 TscH2doV, SDOX data output valid after — — 30 ns — TscL2doV SCKX edge SP36 TdoV2sc, SDOX data output setup to 30 — — ns — TdoV2scL first SCKX edge SP40 TdiV2scH, Setup time of SDIX data input 20 — — ns — TdiV2scL to SCKX edge SP41 TscH2diL, Hold time of SDIX data input 20 — — ns — TscL2diL to SCKX edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. DS70118J-page 172 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 22-18: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOX MSb BIT14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIX MSb IN BIT14 - - - -1 LSb IN SP41 SP40 Note: Refer to Figure22-2 for load conditions. TABLE 22-34: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscL SCKX Input Low Time 30 — — ns See Note 3 SP71 TscH SCKX Input High Time 30 — — ns See Note 3 SP72 TscF SCKX Input Fall Time(3) — 10 25 ns — SP73 TscR SCKX Input Rise Time(3) — 10 25 ns — SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parameter DO32 SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parameter DO31 SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns — TscL2doV SCKX Edge SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns — TdiV2scL to SCKX Edge SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns — TscL2diL to SCKX Edge SP50 TssL2scH, SSX↓ to SCKX↑ or SCKX↓ Input 120 — — ns — TssL2scL SP51 TssH2doZ SSX↑ to SDOX Output 10 — 50 ns — High-Impedance(3) SP52 TscH2ssH SSX after SCK Edge 1.5 TCY +40 — — ns — TscL2ssH Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. © 2011 Microchip Technology Inc. DS70118J-page 173

dsPIC30F2010 FIGURE 22-19: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SCKX (CKP = 1) SP35 SP72 SP73 SP52 SDOX MSb BIT14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIX MSb IN BIT14 - - - -1 LSb IN SP41 SP40 Note: Refer to Figure22-2 for load conditions. DS70118J-page 174 © 2011 Microchip Technology Inc.

dsPIC30F2010 TABLE 22-35: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscL SCKX Input Low Time 30 — — ns See Note 3 SP71 TscH SCKX Input High Time 30 — — ns See Note 3 SP72 TscF SCKX Input Fall Time(3) — 10 25 ns — SP73 TscR SCKX Input Rise Time(3) — 10 25 ns — SP30 TdoF SDOX Data Output Fall Time(3) — — — ns See parameter DO32 SP31 TdoR SDOX Data Output Rise Time(3) — — — ns See parameter DO31 SP35 TscH2doV, SDOX Data Output Valid after — — 30 ns — TscL2doV SCKX Edge SP40 TdiV2scH, Setup Time of SDIX Data Input 20 — — ns — TdiV2scL to SCKX Edge SP41 TscH2diL, Hold Time of SDIX Data Input 20 — — ns — TscL2diL to SCKX Edge SP50 TssL2scH, SSX↓ to SCKX↓ or SCKX↑ input 120 — — ns — TssL2scL SP51 TssH2doZ SS↑ to SDOX Output 10 — 50 ns — High-Impedance(4) SP52 TscH2ssH SSX↑ after SCKX Edge 1.5 TCY + 40 — — ns — TscL2ssH SP60 TssL2doV SDOX Data Output Valid after — — 50 ns — SSX Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2011 Microchip Technology Inc. DS70118J-page 175

dsPIC30F2010 FIGURE 22-20: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM34 IM30 IM33 SDA Start Stop Condition Condition Note: Refer to Figure22-2 for load conditions. FIGURE 22-21: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM21 IM10 SCL IM11 IM26 IM10 IM25 IM33 SDA In IM40 IM40 IM45 SDA Out Note: Refer to Figure22-2 for load conditions. DS70118J-page 176 © 2011 Microchip Technology Inc.

dsPIC30F2010 TABLE 22-36: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min(1) Max Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — µs — 400 kHz mode TCY/2 (BRG + 1) — µs — 1 MHz mode(2) TCY/2 (BRG + 1) — µs — IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — µs — 400 kHz mode TCY/2 (BRG + 1) — µs — 1 MHz mode(2) TCY/2 (BRG + 1) — µs — IM20 TF:SCL SDA and SCL 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 100 ns IM21 TR:SCL SDA and SCL 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns — 1 MHz mode(2) — — ns IM26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 µs — 1 MHz mode(2) — — ns IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — µs Only relevant for Setup Time 400 kHz mode TCY/2 (BRG + 1) — µs repeated Start condition 1 MHz mode(2) TCY/2 (BRG + 1) — µs IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — µs After this period the Hold Time 400 kHz mode TCY/2 (BRG + 1) — µs first clock pulse is generated 1 MHz mode(2) TCY/2 (BRG + 1) — µs IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — µs Setup Time 400 kHz mode TCY/2 (BRG + 1) — µs — 1 MHz mode(2) TCY/2 (BRG + 1) — µs IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns — 1 MHz mode(2) TCY/2 (BRG + 1) — ns IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns — From Clock 400 kHz mode — 1000 ns — 1 MHz mode(2) — — ns — IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — µs Time the bus must be 400 kHz mode 1.3 — µs free before a new transmission can start 1 MHz mode(2) — — µs IM50 CB Bus Capacitive Loading — 400 pF — Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit™ (I2C)” (DS70068) in the “dsPIC30F Family Reference Manual” (DS70046). 2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only). © 2011 Microchip Technology Inc. DS70118J-page 177

dsPIC30F2010 FIGURE 22-22: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS31 IS34 IS30 IS33 SDA Start Stop Condition Condition FIGURE 22-23: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS10 SCL IS30 IS26 IS31 IS25 IS33 SDA In IS40 IS40 IS45 SDA Out DS70118J-page 178 © 2011 Microchip Technology Inc.

dsPIC30F2010 TABLE 22-37: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min Max Units Conditions No. IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs Device must operate at a minimum of 10 MHz. 1 MHz mode(1) 0.5 — μs — IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — μs — IS20 TF:SCL SDA and SCL 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns — 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 μs — 1 MHz mode(1) 0 0.3 μs IS30 TSU:STA Start Condition 100 kHz mode 4.7 — μs Only relevant for repeated Setup Time 400 kHz mode 0.6 — μs Start condition 1 MHz mode(1) 0.25 — μs IS31 THD:STA Start Condition 100 kHz mode 4.0 — μs After this period the first Hold Time 400 kHz mode 0.6 — μs clock pulse is generated 1 MHz mode(1) 0.25 — μs IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — μs Setup Time 400 kHz mode 0.6 — μs — 1 MHz mode(1) 0.6 — μs IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — ns — 1 MHz mode(1) 250 ns IS40 TAA:SCL Output Valid From 100 kHz mode 0 3500 ns Clock 400 kHz mode 0 1000 ns — 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode 1.3 — μs before a new transmission 1 MHz mode(1) 0.5 — μs can start IS50 CB Bus Capacitive — 400 pF — Loading Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only). © 2011 Microchip Technology Inc. DS70118J-page 179

dsPIC30F2010 TABLE 22-38: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of — Lesser of V — VDD - 0.3 VDD + 0.3 or 2.7 or 5.5 AD02 AVSS Module VSS Supply Vss - 0.3 — VSS + 0.3 V — Reference Inputs AD05 VREFH Reference Voltage High AVss+2.7 — AVDD V — AD06 VREFL Reference Voltage Low AVss — AVDD - 2.7 V — AD07 VREF Absolute Reference Voltage AVss - 0.3 — AVDD + 0.3 V — AD08 IREF Current Drain — 200 300 μA A/D operating .001 3 μA A/D off Analog Input AD10 VINH-VINL Full-Scale Input Span VREFL — VREFH V — AD11 VIN Absolute Input Voltage AVSS - 0.3 — AVDD + 0.3 V — AD12 — Leakage Current — ±0.001 ±0.244 μA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V Source Impedance = 5kΩ AD13 — Leakage Current — ±0.001 ±0.244 μA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Source Impedance = 5kΩ AD17 RIN Recommended Impedance — — 5k Ω — Of Analog Voltage Source DC Accuracy AD20 Nr Resolution 10 data bits bits — AD21 INL Integral Nonlinearity(3) — ±1 ±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD21A INL Integral Nonlinearity(3) — ±1 ±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD22 DNL Differential Nonlinearity(3) — ±1 ±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD22A DNL Differential Nonlinearity(3) — ±1 ±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD23 GERR Gain Error(3) +1 ±5 ±6 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD23A GERR Gain Error(3) +1 ±5 ±6 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 2: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. 3: Measurements were taken with external VREF+ and VREF- used as the ADC voltage references. DS70118J-page 180 © 2011 Microchip Technology Inc.

dsPIC30F2010 TABLE 22-38: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. AD24 EOFF Offset Error ±1 ±2 ±3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V AD24A EOFF Offset Error ±1 ±2 ±3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD25 — Monotonicity(2) — — — — Guaranteed Dynamic Performance AD30 THD Total Harmonic Distortion — -64 -67 dB — AD31 SINAD Signal to Noise and — 57 58 dB — Distortion AD32 SFDR Spurious Free Dynamic — 67 71 dB — Range AD33 FNYQ Input Signal Bandwidth — — 500 kHz — AD34 ENOB Effective Number of Bits 9.29 9.41 — bits — Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 2: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. 3: Measurements were taken with external VREF+ and VREF- used as the ADC voltage references. © 2011 Microchip Technology Inc. DS70118J-page 181

dsPIC30F2010 FIGURE 22-24: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) AD50 ADCLK Instruction ExecutionSET SAMP CLEAR SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 TSAMP AD55 AD55 DONE ADIF ADRES(0) ADRES(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 17. “10-bit A/D Converter” (DS70064) of the ”dsPIC30F Family Reference Manual” (DS70 3 – Software clears ADCON. SAMP to start conversion. 4 – Sampling ends, conversion sequence starts. 5 – Convert bit 9. 6 – Convert bit 8. 7 – Convert bit 0. 8 – One TAD for end of conversion. DS70118J-page 182 © 2011 Microchip Technology Inc.

dsPIC30F2010 FIGURE 22-25: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS (CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001) AD50 ADCLK Instruction Execution SET ADON SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc TSAMP TSAMP AD55 AD55 TCONV DONE ADIF ADRES(0) ADRES(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 – Software sets ADCON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. TSAMP is described 6 – One TAD for end of conversion. in Section 17. “10-bit A/D Converter” (DS70064) of the ”dsPIC30F Family Reference Manual” (DS70046). 7 – Begin conversion of next channel 3 – Convert bit 9. 8 – Sample for time specified by SAMC. TSAMP is described in Section 17. “10-bit A/D Converter” 4 – Convert bit 8. (DS70064) of the ”dsPIC30F Family Reference Manual” (DS70046). © 2011 Microchip Technology Inc. DS70118J-page 183

dsPIC30F2010 TABLE 22-39: 10-BIT HIGH-SPEED A/D CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Clock Parameters AD50 TAD A/D Clock Period 84 — — ns See Table18-1(1) AD51 tRC A/D Internal RC Oscillator Period 700 900 1100 ns — Conversion Rate AD55 tCONV Conversion Time — 12 TAD — — — AD56 FCNV Throughput Rate — 1.0 — Msps See Table18-1(1) AD57 TSAMP Sample Time 1 TAD — — — See Table18-1(1) Timing Parameters AD60 tPCS Conversion Start from Sample — 1.0 TAD — ns — Trigger AD61 tPSS Sample Start from Setting 0.5 TAD — 1.5 TAD ns — Sample (SAMP) Bit AD62 tCSS Conversion Completion to — 0.5 TAD — ns — Sample Start (ASAM = 1) AD63 tDPU(2) Time to Stabilize Analog Stage — — 20 μs — from A/D Off to A/D On Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 2: tDPU is the time required for the ADC module to stabilize when it is turned on (ADCON1<ADON> = 1). During this time the ADC result is indeterminate. DS70118J-page 184 © 2011 Microchip Technology Inc.

dsPIC30F2010 23.0 PACKAGING INFORMATION 23.1 Package Marking Information 28-Lead QFN-S Example XXXXXXXX dsPIC30F2010 XXXXXXXX -30I/MM e3 YYWWNNN 060700U 28-Lead SPDIP (Skinny DIP) Example XXXXXXXXXXXXXXXXX dsPIC30F2010-30I/SP XXXXXXXXXXXXXXXXX 0648017 e3 YYWWNNN 28-Lead SOIC (7.5 mm) Example XXXXXXXXXXXXXXXXXXXX dsPIC30F2010-30I/SO XXXXXXXXXXXXXXXXXXXX 0648017 e3 XXXXXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011 Microchip Technology Inc. DS70118J-page 185

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!(cid:11)(cid:26)(cid:26)(cid:27)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13)’(cid:14)$(cid:22)(cid:21)(cid:14)(cid:19)(cid:25)$(cid:22)(cid:21)&(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:10)!(cid:21)(cid:10)(cid:22) (cid:13) (cid:14)(cid:22)(cid:25)(cid:26)(cid:27)(cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11))(cid:19)(cid:25)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:15)(cid:16)(cid:5)/ DS70118J-page 186 © 2011 Microchip Technology Inc.

dsPIC30F2010 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:8)(cid:9)(cid:18)(cid:11)(cid:7)(cid:13)(cid:19)(cid:9)(cid:20)(cid:21)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:22)(cid:7)(cid:23)(cid:6)(cid:9)(cid:24)(cid:25)(cid:25)(cid:26)(cid:9)(cid:27)(cid:9)(cid:28)(cid:29)(cid:28)(cid:29)(cid:30)(cid:31) (cid:9)!!(cid:9)"(cid:21)(cid:8)#(cid:9)$(cid:16)(cid:18)(cid:20)(cid:4)%& ’(cid:14)(cid:13)((cid:9)(cid:30)(cid:31))(cid:30)(cid:9)!!(cid:9)*(cid:21)+(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)+(cid:23)(cid:13)( (cid:20)(cid:21)(cid:13)(cid:6), 2(cid:22)(cid:21)(cid:14)%(cid:23)(cid:13)(cid:14)&(cid:22) %(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:25)%(cid:14)(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:21)(cid:11))(cid:19)(cid:25)(cid:12) ’(cid:14)(cid:10)(cid:26)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)$(cid:19)(cid:20)(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:23)%%(cid:10)133)))(cid:29)&(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)&3(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) © 2011 Microchip Technology Inc. DS70118J-page 187

dsPIC30F2010 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)%(cid:22)(cid:14)++#(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)-(cid:17)(cid:7)(cid:11)(cid:9).+(cid:4)(cid:5)(cid:14)+(cid:6)(cid:9)(cid:24)%(cid:10)(cid:26)(cid:9)(cid:27)(cid:9)/(cid:30)(cid:30)(cid:9)!(cid:14)(cid:11)(cid:9)"(cid:21)(cid:8)#(cid:9)$%(cid:10)-.(cid:10)& (cid:20)(cid:21)(cid:13)(cid:6), 2(cid:22)(cid:21)(cid:14)%(cid:23)(cid:13)(cid:14)&(cid:22) %(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:25)%(cid:14)(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:21)(cid:11))(cid:19)(cid:25)(cid:12) ’(cid:14)(cid:10)(cid:26)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)$(cid:19)(cid:20)(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:23)%%(cid:10)133)))(cid:29)&(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)&3(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 4(cid:25)(cid:19)% (cid:28)60;,(cid:3) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:14)5(cid:19)&(cid:19)% (cid:18)(cid:28)6 67(cid:18) (cid:18)(cid:7)8 6!&((cid:13)(cid:21)(cid:14)(cid:22)$(cid:14)(cid:30)(cid:19)(cid:25) 6 (cid:16)9 (cid:30)(cid:19)%(cid:20)(cid:23) (cid:13) (cid:29)(cid:15)(cid:4)(cid:4)(cid:14)/(cid:3)0 (cid:24)(cid:22)(cid:10)(cid:14)%(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)%(cid:19)(cid:25)(cid:12)(cid:14)(cid:30)(cid:26)(cid:11)(cid:25)(cid:13) (cid:7) > > (cid:29)(cid:16)(cid:4)(cid:4) (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:7)(cid:16) (cid:29)(cid:15)(cid:16)(cid:4) (cid:29)(cid:15)+. (cid:29)(cid:15).(cid:4) /(cid:11) (cid:13)(cid:14)%(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)%(cid:19)(cid:25)(cid:12)(cid:14)(cid:30)(cid:26)(cid:11)(cid:25)(cid:13) (cid:7)(cid:15) (cid:29)(cid:4)(cid:15). > > (cid:3)(cid:23)(cid:22)!(cid:26)"(cid:13)(cid:21)(cid:14)%(cid:22)(cid:14)(cid:3)(cid:23)(cid:22)!(cid:26)"(cid:13)(cid:21)(cid:14)<(cid:19)"%(cid:23) , (cid:29)(cid:16)(cid:6)(cid:4) (cid:29)+(cid:15)(cid:4) (cid:29)++. (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)<(cid:19)"%(cid:23) ,(cid:15) (cid:29)(cid:16)(cid:5)(cid:4) (cid:29)(cid:16)9. (cid:29)(cid:16)(cid:6). 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)5(cid:13)(cid:25)(cid:12)%(cid:23) (cid:2) (cid:15)(cid:29)+(cid:5). (cid:15)(cid:29)+:. (cid:15)(cid:29)(cid:5)(cid:4)(cid:4) (cid:24)(cid:19)(cid:10)(cid:14)%(cid:22)(cid:14)(cid:3)(cid:13)(cid:11)%(cid:19)(cid:25)(cid:12)(cid:14)(cid:30)(cid:26)(cid:11)(cid:25)(cid:13) 5 (cid:29)(cid:15)(cid:15)(cid:4) (cid:29)(cid:15)+(cid:4) (cid:29)(cid:15).(cid:4) 5(cid:13)(cid:11)"(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:20) (cid:29)(cid:4)(cid:4)9 (cid:29)(cid:4)(cid:15)(cid:4) (cid:29)(cid:4)(cid:15). 4(cid:10)(cid:10)(cid:13)(cid:21)(cid:14)5(cid:13)(cid:11)"(cid:14)<(cid:19)"%(cid:23) ((cid:15) (cid:29)(cid:4)(cid:5)(cid:4) (cid:29)(cid:4).(cid:4) (cid:29)(cid:4)(cid:17)(cid:4) 5(cid:22))(cid:13)(cid:21)(cid:14)5(cid:13)(cid:11)"(cid:14)<(cid:19)"%(cid:23) ( (cid:29)(cid:4)(cid:15)(cid:5) (cid:29)(cid:4)(cid:15)9 (cid:29)(cid:4)(cid:16)(cid:16) 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14)(cid:8)(cid:22))(cid:14)(cid:3)(cid:10)(cid:11)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:14)? (cid:13)/ > > (cid:29)(cid:5)+(cid:4) (cid:20)(cid:21)(cid:13)(cid:6)(cid:12), (cid:15)(cid:29) (cid:30)(cid:19)(cid:25)(cid:14)(cid:15)(cid:14)(cid:31)(cid:19) !(cid:11)(cid:26)(cid:14)(cid:19)(cid:25)"(cid:13)#(cid:14)$(cid:13)(cid:11)%!(cid:21)(cid:13)(cid:14)&(cid:11)(cid:27)(cid:14)(cid:31)(cid:11)(cid:21)(cid:27)’(cid:14)(!%(cid:14)&! %(cid:14)((cid:13)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14))(cid:19)%(cid:23)(cid:19)(cid:25)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:23)(cid:11)%(cid:20)(cid:23)(cid:13)"(cid:14)(cid:11)(cid:21)(cid:13)(cid:11)(cid:29) (cid:16)(cid:29) ?(cid:14)(cid:3)(cid:19)(cid:12)(cid:25)(cid:19)$(cid:19)(cid:20)(cid:11)(cid:25)%(cid:14)0(cid:23)(cid:11)(cid:21)(cid:11)(cid:20)%(cid:13)(cid:21)(cid:19) %(cid:19)(cid:20)(cid:29) +(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25) (cid:14)(cid:2)(cid:14)(cid:11)(cid:25)"(cid:14),(cid:15)(cid:14)"(cid:22)(cid:14)(cid:25)(cid:22)%(cid:14)(cid:19)(cid:25)(cid:20)(cid:26)!"(cid:13)(cid:14)&(cid:22)(cid:26)"(cid:14)$(cid:26)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)%(cid:21)! (cid:19)(cid:22)(cid:25) (cid:29)(cid:14)(cid:18)(cid:22)(cid:26)"(cid:14)$(cid:26)(cid:11) (cid:23)(cid:14)(cid:22)(cid:21)(cid:14)(cid:10)(cid:21)(cid:22)%(cid:21)! (cid:19)(cid:22)(cid:25) (cid:14) (cid:23)(cid:11)(cid:26)(cid:26)(cid:14)(cid:25)(cid:22)%(cid:14)(cid:13)#(cid:20)(cid:13)(cid:13)"(cid:14)(cid:29)(cid:4)(cid:15)(cid:4)@(cid:14)(cid:10)(cid:13)(cid:21)(cid:14) (cid:19)"(cid:13)(cid:29) (cid:5)(cid:29) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:19)(cid:25)(cid:12)(cid:14)(cid:11)(cid:25)"(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:19)(cid:25)(cid:12)(cid:14)(cid:10)(cid:13)(cid:21)(cid:14)(cid:7)(cid:3)(cid:18),(cid:14)-(cid:15)(cid:5)(cid:29).(cid:18)(cid:29) /(cid:3)01 /(cid:11) (cid:19)(cid:20)(cid:14)(cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:29)(cid:14)(cid:24)(cid:23)(cid:13)(cid:22)(cid:21)(cid:13)%(cid:19)(cid:20)(cid:11)(cid:26)(cid:26)(cid:27)(cid:14)(cid:13)#(cid:11)(cid:20)%(cid:14)(cid:31)(cid:11)(cid:26)!(cid:13)(cid:14) (cid:23)(cid:22))(cid:25)(cid:14))(cid:19)%(cid:23)(cid:22)!%(cid:14)%(cid:22)(cid:26)(cid:13)(cid:21)(cid:11)(cid:25)(cid:20)(cid:13) (cid:29) (cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:24)(cid:13)(cid:20)(cid:23)(cid:25)(cid:22)(cid:26)(cid:22)(cid:12)(cid:27)(cid:2)(cid:21)(cid:11))(cid:19)(cid:25)(cid:12)0(cid:4)(cid:5)(cid:9)(cid:4)(cid:17)(cid:4)/ DS70118J-page 188 © 2011 Microchip Technology Inc.

dsPIC30F2010 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)%!(cid:7)(cid:11)(cid:11)(cid:9)0(cid:17)(cid:13)(cid:11)(cid:14)+(cid:6)(cid:9)(cid:24)%0(cid:26)(cid:9)(cid:27)(cid:9)1(cid:14)(cid:8)(cid:6)(cid:19)(cid:9)2(cid:31)3(cid:30)(cid:9)!!(cid:9)"(cid:21)(cid:8)#(cid:9)$%0.*& (cid:20)(cid:21)(cid:13)(cid:6), 2(cid:22)(cid:21)(cid:14)%(cid:23)(cid:13)(cid:14)&(cid:22) %(cid:14)(cid:20)!(cid:21)(cid:21)(cid:13)(cid:25)%(cid:14)(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)"(cid:21)(cid:11))(cid:19)(cid:25)(cid:12) ’(cid:14)(cid:10)(cid:26)(cid:13)(cid:11) (cid:13)(cid:14) (cid:13)(cid:13)(cid:14)%(cid:23)(cid:13)(cid:14)(cid:18)(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12)(cid:14)(cid:3)(cid:10)(cid:13)(cid:20)(cid:19)$(cid:19)(cid:20)(cid:11)%(cid:19)(cid:22)(cid:25)(cid:14)(cid:26)(cid:22)(cid:20)(cid:11)%(cid:13)"(cid:14)(cid:11)%(cid:14) (cid:23)%%(cid:10)133)))(cid:29)&(cid:19)(cid:20)(cid:21)(cid:22)(cid:20)(cid:23)(cid:19)(cid:10)(cid:29)(cid:20)(cid:22)&3(cid:10)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:19)(cid:25)(cid:12) D N E E1 NOTE1 1 2 3 e b h α h φ c A A2 L A1 L1 β 4(cid:25)(cid:19)% (cid:18)(cid:28)55(cid:28)(cid:18),(cid:24),(cid:8)(cid:3) (cid:2)(cid:19)&(cid:13)(cid:25) (cid:19)(cid:22)(cid:25)(cid:14)5(cid:19)&(cid:19)% (cid:18)(cid:28)6 67(cid:18) (cid:18)(cid:7)8 6!&((cid:13)(cid:21)(cid:14)(cid:22)$(cid:14)(cid:30)(cid:19)(cid:25) 6 (cid:16)9 (cid:30)(cid:19)%(cid:20)(cid:23) (cid:13) (cid:15)(cid:29)(cid:16)(cid:17)(cid:14)/(cid:3)0 7(cid:31)(cid:13)(cid:21)(cid:11)(cid:26)(cid:26)(cid:14);(cid:13)(cid:19)(cid:12)(cid:23)% (cid:7) > > (cid:16)(cid:29):. (cid:18)(cid:22)(cid:26)"(cid:13)"(cid:14)(cid:30)(cid:11)(cid:20)*(cid:11)(cid:12)(cid:13)(cid:14)(cid:24)(cid:23)(cid:19)(cid:20)*(cid:25)(cid:13) (cid:7)(cid:16) (cid:16)(cid:29)(cid:4). > > (cid:3)%(cid:11)(cid:25)"(cid:22)$$(cid:14)(cid:14)? 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DS70118J-page 189

dsPIC30F2010 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70118J-page 190 © 2011 Microchip Technology Inc.

dsPIC30F2010 APPENDIX A: REVISION HISTORY Revision H (March 2008) This revision reflects these updates: Revision F (May 2006) • Changed the location of the input reference in the Previous versions of this data sheet contained 10-bit High-Speed ADC Functional Block Diagram Advance or Preliminary Information. They were (see Figure18-1) distributed with incomplete characterization data. • Removed incorrect reference to LVDIN function This revision reflects these updates: on Port B (see Figure1-1), previously shown on pin 4 of SDIP and SOIC packages and pin 1 of • Supported I2C Slave addresses QFN package (see Pin Diagrams) (see Table16-1) • Removed erroneous reference to use of the Fast • 10-bit A/D High-speed Conversion timing RC Oscillator with the PLL (see Section19.2.4 requirements (see Section18.0 “10-bit High- “Phase-Locked Loop (PLL)”) Speed Analog-to-Digital Converter (ADC) • Added FUSE Configuration Register (FICD) Module” details (see Section19.6 “Device Configuration • Operating Current (IDD) specifications Registers” and Table19-8) (see Table22-5) • Electrical Specifications: • Idle Current (IIDLE) specifications - Resolved TBD values for parameters DO10, (see Table22-6) DO16, DO20, and DO26 (see Table22-9) • Power-down Current (IPD) specifications (see Table22-7) - 10-bit High-Speed ADC tPDU timing parame- ter (time to stabilize) has been updated from • I/O pin Input specifications 20 µs typical to 20 µs maximum (see (see Table22-8) Table22-39) • BOR voltage limits - Parameter OS65 (Internal RC Accuracy) has (see Table22-10) been expanded (see Table22-18) to reflect • PLL Clock Timing specifications multiple Min and Max values for different tem- (see Table22-14) peratures • PLL Jitter specifications - Parameter D134 (Erase/Write Cycle Time) (see Table22-15) has been updated to include Min and Max • Internal RC Accuracy specifications values and the Typ value has been removed (see Table22-17) (see Table22-11) • Watchdog Timer time-out limits - Parameter DC12 (RAM Data Retention Volt- (see Table22-20) age) has been updated to include a Min value • Additional minor corrections throughout (see Table22-4) document. - Removed parameters OS62 (Internal FRC Jitter) and OS64 (Internal FRC Drift) and Revision G (December 2006) Note 2 from AC Characteristics (see Table22-17) This revision includes updates to the packaging - Parameter OS63 (Internal FRC Accuracy) diagrams. has been expanded to reflect multiple Min and Max values for different temperatures (see Table22-17) - Updated Min and Max values and Conditions for parameter SY11 and updated Min, Typ, and Max values and Conditions for parameter SY20 (see Table22-20) • Additional minor corrections throughout the document © 2011 Microchip Technology Inc. DS70118J-page 191

dsPIC30F2010 Revision J (February 2011) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in TableA-1. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Added Note 1 to all QFN pin diagrams (see “Pin Diagrams”). Digital Signal Controller” Section1.0 “Device Overview” Updated the Pinout I/O Descriptions for AVDD and AVSS (see Table1-1). Section14.0 “Motor Control Added the IUE bit (PWMCON2<2>) to the PWM Register Map (see Table14-1). PWM Module” Updated the PWM Period equations (see Equation14-1 and Equation14-2). Section19.0 “System Added a shaded note on OSCTUN functionality in Section19.2.5 “Fast RC Integration” Oscillator (FRC)”. Section22.0 “Electrical Updated the maximum value for parameter DC60g in the Power-Down Current Characteristics” (Ipd) specifications (see Table22-7). Updated the maximum value for parameter DI19 and the minimum value for parameter DI29 in the I/O Pin Input Specifications (see Table22-8). Removed parameter D136 and updated the minimum, typical, maximum, and conditions for parameters D122 and D134 in the Program and EEPROM specifications (see Table22-11). Section23.0 “Packaging All package drawings have been updated. Information” “Product Identification System” Added the “MM” package definition. DS70118J-page 192 © 2011 Microchip Technology Inc.

dsPIC30F2010 INDEX Block Diagrams 10-bit High Speed ADC Functional...........................111 Numerics 16-bit Timer1 Module..................................................58 DSP Engine................................................................15 10-bit High Speed A/D dsPIC30F2010..............................................................8 A/D Acquisition Requirements..................................117 External Power-on Reset Circuit..............................129 Aborting a Conversion..............................................113 I2C..............................................................................96 ADCHS.....................................................................111 Input Capture Mode....................................................67 ADCON1...................................................................111 Oscillator System......................................................123 ADCON2...................................................................111 Output Compare Mode...............................................71 ADCON3...................................................................111 Quadrature Encoder Interface....................................75 ADCSSL....................................................................111 Reset System...........................................................127 ADPCFG...................................................................111 Shared Port Structure.................................................53 Configuring Analog Port Pins....................................119 SPI..............................................................................92 Connection Considerations.......................................119 SPI Master/Slave Connection.....................................92 Conversion Operation...............................................112 UART Receiver.........................................................104 Effects of a Reset......................................................118 UART Transmitter.....................................................103 Operation During CPU Idle Mode.............................118 BOR Characteristics.........................................................155 Operation During CPU Sleep Mode..........................118 BOR. See Brown-out Reset Output Formats.........................................................118 Brown-out Reset Power-Down Modes..................................................118 Characteristics..........................................................154 Programming the Start of Conversion Trigger..........113 Timing Requirements...............................................161 Register Map.............................................................120 Brown-out Reset (BOR)....................................................121 Result Buffer.............................................................112 Sampling Requirements............................................117 C Selecting the Conversion Sequence.........................112 C Compilers 10-bit High Speed Analog-to-Digital Converter. See A/D MPLAB C18..............................................................144 16-bit Up/Down Position Counter Mode..............................76 Center-Aligned PWM..........................................................85 Count Direction Status................................................76 CLKO and I/O Timing Error Checking............................................................76 Characteristics..........................................................160 A Requirements...........................................................160 Code Examples A/D....................................................................................111 Data EEPROM Block Erase.......................................50 1 Msps Configuration Guideline................................116 Data EEPROM Block Write........................................52 600 ksps Configuration Guideline.............................116 Data EEPROM Read..................................................49 750 ksps Configuration Guideline.............................116 Data EEPROM Word Erase.......................................50 Conversion Rate Parameters....................................115 Data EEPROM Word Write........................................51 Conversion Speeds...................................................114 Erasing a Row of Program Memory...........................45 Selecting the Conversion Clock................................113 Initiating a Programming Sequence...........................46 Voltage Reference Schematic..................................114 Loading Write Latches................................................46 AC Characteristics............................................................156 Code Protection................................................................121 Load Conditions........................................................156 Complementary PWM Operation........................................86 AC Temperature and Voltage Specifications....................156 Configuring Analog Port Pins..............................................54 Address Generator Units....................................................31 Control Registers................................................................44 Alternate 16-bit Timer/Counter............................................77 NVMADR....................................................................44 Alternate Vector Table........................................................41 NVMADRU.................................................................44 Assembler NVMCON....................................................................44 MPASM Assembler...................................................144 NVMKEY....................................................................44 Automatic Clock Stretch......................................................98 Core Architecture During 10-bit Addressing (STREN = 1).......................98 Overview.....................................................................11 During 7-bit Addressing (STREN = 1).........................98 Core Register Map..............................................................28 Receive Mode.............................................................98 Customer Change Notification Service.............................199 Transmit Mode............................................................98 Customer Notification Service..........................................199 B Customer Support.............................................................199 Band Gap Start-up Time D Requirements............................................................162 Data Access from Program Memory Timing Characteristics..............................................162 Using Program Space Visibility..................................22 Barrel Shifter.......................................................................18 Data Accumulators and Adder................................16, 17, 18 Bit-Reversed Addressing....................................................35 Data Address Space...........................................................23 Example......................................................................35 Access RAM...............................................................27 Implementation...........................................................35 Alignment....................................................................26 Modifier Values (Table)...............................................36 Alignment (Figure)......................................................26 Sequence Table (16-Entry).........................................36 MCU and DSP (MAC Class) Instructions...................25 Block Diagram Memory Map.........................................................23, 24 PWM...........................................................................82 Spaces........................................................................26 © 2011 Microchip Technology Inc. DS70118J-page 193

dsPIC30F2010 Width...........................................................................26 In-Circuit Serial Programming (ICSP).........................43 Data EEPROM Memory......................................................49 Run-Time Self-Programming (RTSP).........................43 Erasing........................................................................50 Table Instruction Operation Summary........................43 Erasing, Block.............................................................50 I Erasing, Word.............................................................50 Protection Against Spurious Write..............................52 I/O Pin Specifications Reading.......................................................................49 Input..........................................................................153 Write Verify.................................................................52 Output.......................................................................154 Writing.........................................................................51 I/O Ports..............................................................................53 Writing, Block..............................................................52 Parallel I/O (PIO)........................................................53 Writing, Word..............................................................51 I2C.......................................................................................95 DC Characteristics............................................................148 I2C 10-bit Slave Mode Operation........................................97 BOR..........................................................................155 Reception...................................................................98 Brown-out Reset.......................................................154 Transmission..............................................................97 I/O Pin Input Specifications.......................................153 I2C 7-bit Slave Mode Operation..........................................97 I/O Pin Output Specifications....................................154 Reception...................................................................97 Idle Current (IIDLE)....................................................151 Transmission..............................................................97 Operating Current (IDD).............................................150 I2C Master Mode Power-Down Current (IPD)........................................152 Baud Rate Generator.................................................99 Program and EEPROM.............................................155 Clock Arbitration.......................................................100 Temperature and Voltage Specifications..................148 Multi-Master Communication, Bus Collision Dead-Time Generators.......................................................86 and Bus Arbitration...........................................100 Ranges........................................................................86 Reception...................................................................99 Development Support.......................................................143 Transmission..............................................................99 Device Configuration I2C Module Register Map.............................................................133 Addresses...................................................................97 Device Configuration Registers.........................................132 Bus Data Timing Characteristics FBORPOR................................................................132 Master Mode.....................................................176 FGS...........................................................................132 Slave Mode.......................................................178 FOSC........................................................................132 Bus Data Timing Requirements FWDT........................................................................132 Master Mode.....................................................177 Device Overview...................................................................7 Slave Mode.......................................................179 Divide Support.....................................................................14 Bus Start/Stop Bits Timing Characteristics DSP Engine.........................................................................14 Master Mode.....................................................176 Multiplier......................................................................16 Slave Mode.......................................................178 Dual Output Compare Match Mode....................................72 General Call Address Support....................................99 Continuous Pulse Mode..............................................72 Interrupts....................................................................98 Single Pulse Mode......................................................72 IPMI Support...............................................................99 Master Operation........................................................99 E Master Support...........................................................99 Edge-Aligned PWM.............................................................85 Operating Function Description..................................95 Electrical Characteristics...................................................147 Operation During CPU Sleep and Idle Modes..........100 AC.............................................................................156 Pin Configuration........................................................95 DC.............................................................................148 Programmer’s Model..................................................95 Equations Register Map............................................................101 A/D Conversion Clock...............................................113 Registers....................................................................95 Baud Rate.................................................................107 Slope Control..............................................................99 PWM Period................................................................84 Software Controlled Clock Stretching (STREN = 1)...98 PWM Period (Up/Down Count Mode).........................84 Various Modes............................................................95 PWM Resolution.........................................................84 Idle Current (IIDLE)............................................................151 Serial Clock Rate........................................................99 In-Circuit Serial Programming (ICSP)...............................121 Errata....................................................................................6 Independent PWM Output..................................................87 Exception Sequence Initialization Condition for RCON Register Case 1...........130 Trap Sources..............................................................39 Initialization Condition for RCON Register Case 2...........130 External Clock Timing Characteristics Initialization Condition for RCON Register, Case 1..........130 Type A and B Timer..................................................163 Input Capture (CAPx) Timing Characteristics...................166 External Clock Timing Requirements................................157 Input Capture Interrupts......................................................69 Type A Timer............................................................163 Register Map..............................................................70 Type B Timer............................................................164 Input Capture Module.........................................................67 Type C Timer............................................................164 In CPU Sleep Mode....................................................69 External Interrupt Requests................................................41 Simple Capture Event Mode.......................................68 Input Capture Timing Requirements.................................166 F Input Change Notification Module.......................................54 Fast Context Saving............................................................41 Register Map (bits 15-0).............................................55 Firmware Instructions........................................................135 Input Characteristics Flash Program Memory.......................................................43 QEA/QEB.................................................................169 DS70118J-page 194 © 2011 Microchip Technology Inc.

dsPIC30F2010 Instruction Addressing Modes.............................................31 Output Compare Operation During CPU Idle Mode...........73 File Register Instructions............................................31 Output Compare Sleep Mode Operation............................73 Fundamental Modes Supported..................................31 P MAC Instructions.........................................................32 MCU Instructions........................................................32 Packaging Information......................................................185 Move and Accumulator Instructions............................32 Marking.....................................................................185 Other Instructions........................................................32 Pinout Descriptions...............................................................9 Instruction Set...................................................................135 PLL Clock Timing Specifications......................................158 Inter-Integrated Circuit. See I2C POR. See Power-on Reset Internal Clock Timing Examples.......................................159 Port Register Map...............................................................55 Internet Address................................................................199 Port Write/Read Example...................................................54 Interrupt Controller PORTB Register Map...............................................................42 Register Map..............................................................55 Interrupt Priority..................................................................38 PORTC Traps...........................................................................39 Register Map..............................................................55 Interrupt Sequence.............................................................41 PORTD Interrupt Stack Frame.................................................41 Register Map..............................................................55 Interrupts.............................................................................37 PORTE Register Map..............................................................55 L PORTF Load Conditions................................................................156 Register Map..............................................................55 Position Measurement Mode..............................................77 M Power-Down Current (IPD)................................................152 Memory Organization..........................................................19 Power-on Reset (POR).....................................................121 Microchip Internet Web Site..............................................199 Oscillator Start-up Timer (OST)................................121 Modulo Addressing.............................................................33 Power-up Timer (PWRT)..........................................121 Applicability.................................................................35 Power-Saving Modes........................................................131 Operation Example.....................................................34 Idle............................................................................132 Start and End Address................................................33 Sleep........................................................................131 W Address Register Selection....................................33 Power-Saving Modes (Sleep and Idle).............................121 Motor Control PWM Module................................................81 Power-up Timer Fault Timing Characteristics.....................................168 Timing Characteristics..............................................161 Timing Characteristics..............................................168 Timing Requirements...............................................161 Timing Requirements................................................168 Product Identification System...........................................201 MPLAB ASM30 Assembler, Linker, Librarian...................144 Program Address Space.....................................................19 MPLAB Integrated Development Environment Software..143 Construction...............................................................20 MPLAB PM3 Device Programmer....................................146 Data Access from Program Memory Using MPLAB REAL ICE In-Circuit Emulator System.................145 Table Instructions...............................................21 MPLINK Object Linker/MPLIB Object Librarian................144 Data Access From, Address Generation....................20 Memory Map...............................................................19 O Table Instructions OC/PWM Module Timing Characteristics..........................167 TBLRDH.............................................................21 Operating Current (IDD).....................................................150 TBLRDL..............................................................21 Operating MIPS vs Voltage TBLWTH.............................................................21 dsPIC30F2010..........................................................148 TBLWTL.............................................................21 Oscillator Program and EEPROM Characteristics............................155 Configurations Program Counter................................................................12 Fast RC (FRC)..................................................125 Program Data Table Access...............................................22 Low Power RC (LPRC).....................................125 Program Space Visibility Phase Locked Loop (PLL)................................125 Window into Program Space Operation.....................23 Oscillator Configurations...................................................124 Programmable..................................................................121 Fail-Safe Clock Monitor.............................................126 Programmable Digital Noise Filters....................................77 Initial Clock Source Selection...................................124 Programmer’s Model..........................................................12 LP Oscillator Control.................................................125 Diagram......................................................................13 Start-up Timer (OST)................................................124 Programming Operations....................................................45 Oscillator Operating Modes Table....................................122 Algorithm for Program Flash.......................................45 Oscillator Selection...........................................................121 Erasing a Row of Program Memory...........................45 Oscillator Start-up Timer Initiating the Programming Sequence........................46 Timing Characteristics..............................................161 Loading Write Latches................................................46 Timing Requirements................................................161 Programming, Device Instructions....................................135 Output Compare Interrupts.................................................73 Protection Against Accidental Writes to OSCCON...........126 Output Compare Mode PWM Register Map...............................................................74 Register Map..............................................................90 Output Compare Module.....................................................71 PWM Duty Cycle Comparison Units...................................85 Timing Characteristics..............................................166 Duty Cycle Register Buffers.......................................86 Timing Requirements................................................166 PWM FLTA Pins.................................................................88 © 2011 Microchip Technology Inc. DS70118J-page 195

dsPIC30F2010 Enable Bits..................................................................88 Simple PWM Mode.............................................................72 Fault States.................................................................88 Input Pin Fault Protection...........................................72 Modes.........................................................................88 Period.........................................................................73 Cycle-by-Cycle....................................................88 Single Pulse PWM Operation.............................................87 Latched...............................................................88 Software Simulator (MPLAB SIM)....................................145 PWM Operation During CPU Idle Mode..............................89 Software Stack Pointer, Frame Pointer..............................12 PWM Operation During CPU Sleep Mode..........................89 CALL Stack Frame.....................................................27 PWM Output and Polarity Control.......................................88 SPI......................................................................................91 Output Pin Control......................................................88 SPI Mode PWM Output Override.........................................................87 Slave Select Synchronization.....................................93 Complementary Output Mode.....................................87 SPI1 Register Map......................................................94 Synchronization..........................................................87 SPI Module.........................................................................91 PWM Period........................................................................84 Framed SPI Support...................................................92 PWM Special Event Trigger................................................89 Operating Function Description..................................91 Postscaler...................................................................89 SDOx Disable.............................................................91 PWM Time Base.................................................................83 Timing Characteristics Continuous Up/Down Counting Modes.......................83 Master Mode (CKE = 0)....................................171 Double Update Mode..................................................84 Master Mode (CKE = 1)....................................172 Free Running Mode....................................................83 Slave Mode (CKE = 1)..............................173, 174 Postscaler...................................................................84 Timing Requirements Prescaler.....................................................................84 Master Mode (CKE = 0)....................................171 Single-Shot Mode.......................................................83 Master Mode (CKE = 1)....................................172 PWM Update Lockout.........................................................88 Slave Mode (CKE = 0)......................................173 Slave Mode (CKE = 1)......................................175 Q Word and Byte Communication..................................91 QEA/QEB Input Characteristics........................................169 SPI Operation During CPU Idle Mode................................93 QEI Module SPI Operation During CPU Sleep Mode.............................93 External Clock Timing Requirements........................165 STATUS Register...............................................................12 Index Pulse Timing Characteristics...........................170 Subtracter...........................................................................16 Index Pulse Timing Requirements............................170 Data Space Write Saturation......................................18 Operation During CPU Idle Mode...............................78 Overflow and Saturation.............................................16 Operation During CPU Sleep Mode............................77 Round Logic...............................................................17 Register Map...............................................................79 Write Back..................................................................17 Timer Operation During CPU Idle Mode.....................78 Symbols used in Opcode Descriptions.............................136 Timer Operation During CPU Sleep Mode..................77 System Integration............................................................121 Quadrature Decoder Timing Requirements......................169 Overview...................................................................121 Quadrature Encoder Interface (QEI) Module......................75 Register Map............................................................133 Quadrature Encoder Interface Interrupts............................78 T Quadrature Encoder Interface Logic...................................76 Temperature and Voltage Specifications R AC.............................................................................156 Reader Response.............................................................200 DC............................................................................148 Reset.........................................................................121, 127 Timer1 Module....................................................................57 Reset Sequence..................................................................39 16-bit Asynchronous Counter Mode...........................57 Reset Sources............................................................39 16-bit Synchronous Counter Mode.............................57 Reset Timing Characteristics............................................161 16-bit Timer Mode.......................................................57 Reset Timing Requirements..............................................161 Gate Operation...........................................................58 Resets Interrupt......................................................................59 BOR, Programmable.................................................129 Operation During Sleep Mode....................................58 POR..........................................................................127 Prescaler....................................................................58 Operating without FSCM and PWRT................129 Real-Time Clock.........................................................59 POR with Long Crystal Start-up Time.......................129 RTC Interrupts....................................................59 RTSP Operation..................................................................44 RTC Oscillator Operation...................................59 Register Map..............................................................60 S Timer2 and Timer3 Selection Mode....................................72 Serial Peripheral Interface. See SPI Timer2/3 Module.................................................................61 Simple Capture Event Mode 32-bit Synchronous Counter Mode.............................61 Capture Buffer Operation............................................68 32-bit Timer Mode.......................................................61 Capture Prescaler.......................................................68 ADC Event Trigger......................................................64 Hall Sensor Mode.......................................................68 Gate Operation...........................................................64 Input Capture in CPU Idle Mode.................................69 Interrupt......................................................................64 Timer2 and Timer3 Selection Mode............................68 Operation During Sleep Mode....................................64 Simple OC/PWM Mode Timing Requirements..................167 Register Map..............................................................65 Simple Output Compare Match Mode.................................72 Timer Prescaler..........................................................64 DS70118J-page 196 © 2011 Microchip Technology Inc.

dsPIC30F2010 TimerQ (QEI Module) External Clock Quadrature Decoder.................................................169 Timing Characteristics..............................................165 Reset........................................................................161 Timing Characteristics Simple OC/PWM Mode............................................167 A/D Conversion SPI Module 10-Bit High-speed (CHPS = 01, SIMSAM = 0, Master Mode (CKE = 0)....................................171 ASAM = 0, SSRC = 000)..........................182 Master Mode (CKE = 1)....................................172 10-bit High-speed (CHPS = 01, SIMSAM = 0, Slave Mode (CKE = 0)......................................173 ASAM = 1, SSRC = 111, SAMC = 00001)183 Slave Mode (CKE = 1)......................................175 Band Gap Start-up Time...........................................162 Type A Timer External Clock....................................163 CLKO and I/O...........................................................160 Type B Timer External Clock....................................164 External Clock...........................................................156 Type C Timer External Clock....................................164 I2C Bus Data Watchdog Timer.......................................................161 Master Mode.....................................................176 Timing Specifications Slave Mode.......................................................178 PLL Clock.................................................................158 I2C Bus Start/Stop Bits U Master Mode.....................................................176 Slave Mode.......................................................178 UART Input Capture (CAPx)................................................166 Address Detect Mode...............................................107 Motor Control PWM Module......................................168 Auto Baud Support...................................................107 Motor Control PWM Module Fault.............................168 Baud Rate Generator...............................................107 OC/PWM Module......................................................167 Enabling and Setting Up UART................................105 Oscillator Start-up Timer...........................................161 Alternate I/O.....................................................105 Output Compare Module...........................................166 Disabling...........................................................105 Power-up Timer........................................................161 Enabling...........................................................105 QEI Module Index Pulse...........................................170 Setting Up Data, Parity and Reset.........................................................................161 Stop Bit Selections...................................105 SPI Module Loopback Mode........................................................107 Master Mode (CKE = 0)....................................171 Module Overview......................................................103 Master Mode (CKE = 1)....................................172 Operation During CPU Sleep and Idle Modes..........108 Slave Mode (CKE = 0)......................................173 Receiving Data.........................................................106 Slave Mode (CKE = 1)......................................174 In 8-bit or 9-bit Data Mode................................106 TimerQ (QEI Module) External Clock.......................165 Interrupt............................................................106 Type A and B Timer External Clock..........................163 Receive Buffer (UxRXB)...................................106 Watchdog Timer........................................................161 Reception Error Handling.........................................106 Timing Diagrams Framing Error (FERR)......................................107 Center-Aligned PWM..................................................85 Idle Status........................................................107 Dead-Time..................................................................87 Parity Error (PERR)..........................................107 Edge-Aligned PWM.....................................................85 Receive Break..................................................107 PWM Output...............................................................73 Receive Buffer Overrun Error (OERR Bit)........106 Time-out Sequence on Power-up Transmitting Data.....................................................105 (MCLR Not Tied to VDD), Case 1......................128 In 8-bit Data Mode............................................105 Time-out Sequence on Power-up In 9-bit Data Mode............................................105 (MCLR Not Tied to VDD), Case 2......................128 Interrupt............................................................106 Time-out Sequence on Power-up Transmit Buffer (UxTXB)..................................105 (MCLR Tied to VDD)..........................................128 UART1 Register Map...............................................109 Timing Diagrams and Specifications Unit ID Locations..............................................................121 DC Characteristics - Internal RC Accuracy...............159 Universal Asynchronous Receiver Transmitter. See UART. Timing Diagrams.See Timing Characteristics W Timing Requirements A/D Conversion Wake-up from Sleep.........................................................121 High-speed.......................................................184 Wake-up from Sleep and Idle.............................................41 Band Gap Start-up Time...........................................162 Watchdog Timer Brown-out Reset.......................................................161 Timing Characteristics..............................................161 CLKO and I/O...........................................................160 Timing Requirements...............................................161 External Clock...........................................................157 Watchdog Timer (WDT)............................................121, 131 I2C Bus Data (Master Mode).....................................177 Enabling and Disabling.............................................131 I2C Bus Data (Slave Mode).......................................179 Operation..................................................................131 Input Capture............................................................166 WWW Address.................................................................199 Motor Control PWM Module......................................168 WWW, On-Line Support.......................................................6 Oscillator Start-up Timer...........................................161 Output Compare Module...........................................166 Power-up Timer........................................................161 QEI Module External Clock...................................................165 Index Pulse.......................................................170 © 2011 Microchip Technology Inc. DS70118J-page 197

dsPIC30F2010 NOTES: DS70118J-page 198 © 2011 Microchip Technology Inc.

dsPIC30F2010 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design • Development Systems Information Line resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQs), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. © 2011 Microchip Technology Inc. DS70118J-page 199

dsPIC30F2010 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: dsPIC30F2010 Literature Number: DS70118J Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70118J-page 200 © 2011 Microchip Technology Inc.

dsPIC30F2010 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC30F2010AT-20E/SO-ES Custom ID (3 digits) or Trademark Engineering Sample (ES) Architecture Package MM = QFN-S Flash SP = SPDIP SO = SOIC S = Die (Waffle Pack) Memory Size in Bytes W = Die (Wafers) 0 = ROMless 1 = 1K to 6K 2 = 7K to 12K 3 = 13K to 24K 4 = 25K to 48K Temperature 5 = 49K to 96K I = Industrial -40°C to +85°C 6 = 97K to 192K E = Extended High Temp -40°C to +125°C 7 = 193K to 384K 8 = 385K to 768K Speed 9 = 769K and Up 20 = 20 MIPS 30 = 30 MIPS Device ID T = Tape and Reel A,B,C… = Revision Level Example: dsPIC30F2010AT-20E/SO = 20 MIPS, Extended temp., SOIC package, Rev. A © 2011 Microchip Technology Inc. DS70118J-page 201

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