Product Sample & Technical Tools & Support & Folder Buy Documents Software Community DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 DS92LV241x 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer 1 Features 3 Description • 24-BitData,3–BitControl,5to50MHzClock The DS92LV2411 (Serializer) and DS92LV2412 1 (Deserializer) chipset translates a parallel 24–bit • ApplicationPayloadsupto1.2Gbps LVCMOSdatainterfaceintoasinglehigh-speedCML • ACCoupledInterconnects:STPupto10mor serial interface with embedded clock information. This Coax20+m single serial stream eliminates skew issues between • 1.8Vor3.3VCompatibleLVCMOSI/OInterface clock and data, reduces connector size and interconnect cost for transferring a 24-bit, or less, bus • IntegratedTerminationsonSerandDes over FR-4 printed circuit board backplanes, • AT-SPEEDBISTModeandReportingPin differentialorcoaxcables. • ConfigurablebyPinsorI2CCompatibleSerial In addition to the 24-bit data bus interface, the ControlBus DS92LV2411/12 also features a 3-bit control bus for • PowerDownModeMinimizesPowerDissipation slow speed signals. This allows implementing video • >8kVHBMESDRating and display applications with up to 24–bits per pixel (RGB888). • SERIALIZER —DS92LV2411 Programmable transmit de-emphasis, receive – SupportsSpreadSpectrumClocking(SSC)on equalization, on-chip scrambling and DC balancing Inputs enables long distance transmission over lossy cables – DataScramblerforReducedEMI and backplanes. The DS92LV2412 automatically – DC-BalanceEncoderforACCoupling locks to incoming data without an external reference clock or special sync patterns, providing easy “plug- – SelectableOutputV andAdjustableDe- OD and-go” or “hot plug” operation. EMI is minimized by emphasis the use of low voltage differential signaling, receiver • DESERIALIZER —DS92LV2412 drive strength control, and spread spectrum clocking – RandomDataLock;noReferenceClock capability. Required TheDS92LV2411/12chipsetisprogrammablethough – AdjustableInputReceiverEqualization an I2C interface as well as through Pins. A built-in – LOCK(RealTimeLinkStatus)ReportingPin AT-SPEED BIST feature validates link integrity and maybeusedforsystemdiagnostics. – SelectableSpreadSpectrumClockGeneration (SSCG)andOutputSlewRateControl(OS)to The DS92LV2411 is offered in a 48-Pin WQFN and ReduceEMI the DS92LV2412 is offered in a 60-Pin WQFN package. Both devices operate over the full industrial 2 Applications temperaturerangeof-40°Cto+85°C. • EmbeddedVideoandDisplay DeviceInformation • MedicalImaging PARTNUMBER PACKAGE BODYSIZE(NOM) • FactoryAutomation DS92LV2411 WQFN(48) 7.00mm×7.00mm • OfficeAutomation —Printer,Scanner DS92LV2412 WQFN(60) 9.00mm×9.00mm • SecurityandVideoSurveillance 4 Typical Application Schematic • GeneralPurposeDataCommunication VDDIO VDDn VDDn VDDIO (1.8V or 3.3V)1.8V 1.8V (1.8V or 3.3V) PGrorVOcaiepdRshesoicor DDDIIICC[[[217II1235:0::18]6]] DOUT+ 0.1 PF 1 PCahiar n/ AnCel CLoinukp IlIe d0.1 PF RIN+ DDDOOCOCO[O[[2171235:0::18]6]] 24D-ObisiRtp RlaGyB Imager CI3 CO3 ASIC/FPGA ASICO/RFPGA CLPKDIBN DSSe9r2iLaDlVizO2e4Ur1T1- 100 ohm STP CableCMF RDDINSe9-s2eLriVa2li4ze1r2 CLPLKOAOSCUSKT PDB BISTEN RFB BISTEN STRAP pins Optional SSDCAL DVOeEDmSpEhL Optional SSDCAL not shown ID[x] ID[x] DAP DAP 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8.1 Overview.................................................................22 2 Applications........................................................... 1 8.2 FunctionalBlockDiagrams.....................................22 3 Description............................................................. 1 8.3 FeatureDescription.................................................23 8.4 DeviceFunctionalModes........................................34 4 TypicalApplicationSchematic............................. 1 8.5 Programming...........................................................34 5 RevisionHistory..................................................... 2 8.6 RegisterMaps.........................................................37 6 PinConfigurationandFunctions......................... 3 9 ApplicationsandImplementation...................... 40 7 Specifications....................................................... 10 9.1 ApplicationInformation............................................40 7.1 AbsoluteMaximumRatings....................................10 9.2 TypicalApplications................................................40 7.2 ESDRatings............................................................10 10 PowerSupplyRecommendations..................... 44 7.3 RecommendedOperatingConditions.....................10 11 Layout................................................................... 44 7.4 ThermalInformation................................................11 11.1 LayoutGuidelines.................................................44 7.5 SerializerDCElectricalCharacteristics..................11 11.2 LayoutExample....................................................44 7.6 DeserializerDCElectricalCharacteristics..............12 12 DeviceandDocumentationSupport................. 47 7.7 DCandACSerialControlBusCharacteristics.......13 7.8 RecommendedTimingForTheSerialControlBus 14 12.1 RelatedLinks........................................................47 7.9 RecommendedSerializerTimingForCLKIN..........18 12.2 Trademarks...........................................................47 7.10 SerializerSwitchingCharacteristics......................19 12.3 ElectrostaticDischargeCaution............................47 7.11 DeserializerSwitchingCharacteristics..................20 12.4 Glossary................................................................47 7.12 TypicalCharacteristics..........................................21 13 Mechanical,Packaging,andOrderable Information........................................................... 47 8 DetailedDescription............................................ 22 5 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionD(April2014)toRevisionE Page • Changed"Terminal"terminologybackto"Pin" ..................................................................................................................... 1 • AddedstatementaboutcheckerboardpatternfromdeserializerdataoutputwheninBISTmode ..................................... 32 • AddednotethatBISTENpinmustbehighandREG=0touseBISTmode. .................................................................... 32 • ChangeddeserializerReg0x02[6]definitiontomatchcorrectOSS_SELbehavior............................................................ 38 ChangesfromRevisionC(April2013)toRevisionD Page • AddedHandlingRatingsandThermalCharacteristicsandupdateddatasheettonewlayout. ............................................ 1 • ChangedSerializerSupplycurrentpowerdowntestconditionfromV from13.6Vto3.6V .......................................... 12 DDIO • AddedDCto"DeserializerElectricalCharacteristics".......................................................................................................... 12 • Changedtypicalvalueto36mAinsteadof37mA ............................................................................................................... 12 • ChangedTestconditionofV fordeterminingI ........................................................................................................... 12 OUT OZ • AddedmaxvalueforV whenusing1.8VI/OLVCMOS .................................................................................................... 12 IL • ChangedIOLfrom3mAto1.25mA ..................................................................................................................................... 13 • ChangedparentheseslocationofUIequationforclarification ............................................................................................ 20 • AddedcharacteristicgraphicsforserializerCMLdriveroutputanddeserializerLVCMOSclockoutput ............................ 21 • Addedapplicationsgraphicsoftheserializeroutputwithandwithoutde-emphasis .......................................................... 43 • Addedlayoutexampleandstencildiagramgraphics........................................................................................................... 44 ChangesfromRevisionB(April2013)toRevisionC Page • ChangedlayoutofNationalDataSheettoTIformat........................................................................................................... 43 2 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 6 Pin Configuration and Functions 48-PinWQFN PackageRHS TopView TEN DIO DI9 DI8 DI7 DI6 DI5 BIS VD DI4 DI3 DI2 DI1 DI0 6 5 4 3 2 1 0 9 8 7 6 5 3 3 3 3 3 3 3 2 2 2 2 2 DI10 37 24 VODSEL DI11 38 23 De-Emph DI12 39 22 VDDTX DI13 40 21 PDB DI14 41 20 DOUT+ DS92LV2411 DI15 42 TOP VIEW 19 DOUT- DI16 43 18 RES2 DAP = GND DI17 44 17 VDDHS DI18 45 16 RES1 DI19 46 15 RES0 DI20 47 14 VDDP DI21 48 13 CONFIG[1] 1 2 3 4 5 6 7 8 9 10 11 12 DI22 DI23 CI2 CI3 CI1 ID[x] VDDL SCL SDA CLKIN RFB NFIG[0] O C PinFunctions,DS92LV2411Serializer(1) PIN TYPE DESCRIPTION NAME NO. LVCMOSPARALLELINTERFACE CI1 5 I,LVCMOS ControlSignalInput w/pull-down ForDisplay/VideoApplication: CI1=DataEnableInput Controlsignalpulsewidthmustbe3clocksorlongertobetransmittedwhentheControl SignalFilterisenabled(CONFIG[1:0]=01).Thereisnorestrictionontheminimumtransition pulsewhentheControlSignalFilterisdisabled(CONFIG[1:0]=00). Thesignalislimitedto2transitionsper130clocksregardlessoftheControlSignalFilter setting. CI2 3 I,LVCMOS ControlSignalInput w/pull-down ForDisplay/VideoApplication: CI2=HorizontalSyncInput Controlsignalpulsewidthmustbe3clocksorlongertobetransmittedwhentheControl SignalFilterisenabled(CONFIG[1:0]=01).Thereisnorestrictionontheminimumtransition pulsewhentheControlSignalFilterisdisabled(CONFIG[1:0]=00). Thesignalislimitedto2transitionsper130clocksregardlessoftheControlSignalFilter setting. CI3 4 I,LVCMOS ControlSignalInput w/pull-down ForDisplay/VideoApplication: CI3=VerticalSyncInput CI3islimitedto1transitionper130clockcycles.Thus,theminimumpulsewidthallowedis 130clockcyclewide. (1) NOTE:1=HIGH,0=LOW TheVDD(V andV )supplyrampshouldbefasterthan1.5mswithamonotonicrise.Ifslowerthen1.5msthenacapacitoron DDn DDIO thePDBPinisneededtoensurePDBarrivesafteralltheVDDhavesettledtotherecommendedoperatingvoltage. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com PinFunctions,DS92LV2411Serializer(1)(continued) PIN TYPE DESCRIPTION NAME NO. CLKIN 10 I,LVCMOS ClockInput w/pull-down Latch/datastrobeedgesetbyRFBPin. DI[7:0] 34,33,32,29, I,LVCMOS ParallelInterfaceDataInputPins 28,27,26,25 w/pull-down For8–bitREDDisplay:DI7=R7–MSB,DI0=R0–LSB. DI[15:8] 42,41,40,39, I,LVCMOS ParallelInterfaceDataInputPins 38,37,36,35 w/pull-down For8–bitGREENDisplay:DI15=G7–MSB,DI8=G0–LSB. DI[23:16] 2,1,48,47, I,LVCMOS ParallelInterfaceDataInputPins 46,45,44,43 w/pull-down For8–bitBLUEDisplay:DI23=B7–MSB,DI16=B0–LSB. CONTROLANDCONFIGURATION BISTEN 31 I,LVCMOS BISTMode—Optional w/pull-down BISTEN=0,BISTisdisabled(normaloperation) BISTEN=1,BISTisenabled CONFIG[1: 13,12 I,LVCMOS 00:ControlSignalFilterDISABLED.InterfaceswithDS92LV2412orDS92LV0412 0] w/pull-down 01:ControlSignalFilterENABLED.InterfaceswithDS92LV2412orDS92LV0412 10:ReversecompatibilitymodetointerfacewiththeDS90UR124orDS99R124Q 11:ReversecompatibilitymodetointerfacewiththeDS90C124 De-Emph 23 I,Analog De-EmphasisControl w/pull-up De-Emph=open(float)-disabled ToenableDe-emphasis,tiearesistorfromthisPintoGNDorcontrolviaregister. SeeTable2. ThiscanalsobecontrolledbyI2Cregisteraccess. ID[x] 6 I,Analog I2CSerialControlBusDeviceIDAddressSelect—Optional ResistortoGroundand10kΩpull-upto1.8Vrail.SeeTable11. PDB 21 I,LVCMOS Power-downModeInput w/pull-down PDB=1,Serisenabled(normaloperation). Referto”PowerUpRequirementsandPDBPin”intheApplicationsInformationSection. PDB=0,Serispowereddown WhentheSerisinthepower-downstate,thedriveroutputs(DOUT+/-)arebothlogichigh, thePLLisshutdown,IDDisminimized.ControlRegistersareRESET. RES[2:0] 18,16,15 I,LVCMOS Reserved-tieLOW w/pull-down RFB 11 I,LVCMOS ClockInputLatch/DataStrobeEdgeSelect w/pull-down RFB=1,parallelinterfacedataandcontrolsignalsarelatchedontherisingclockedge. RFB=0,parallelinterfacedataandcontrolsignalsarelatchedonthefallingclockedge. ThiscanalsobecontrolledbyI2Cregisteraccess. SCL 8 I,LVCMOS I2CSerialControlBusClockInput-Optional OpenDrain SCLrequiresanexternalpull-upresistorto3.3V. SDA 9 I/O,LVCMOS I2CSerialControlBusDataInput/Output-Optional OpenDrain SDArequiresanexternalpull-upresistor3.3V. VODSEL 24 I,LVCMOS DifferentialDriverOutputVoltageSelect w/pull-down VODSEL=1,CMLVODis±420mV,840mVp-p(typ)—longcable/De-Emphapplications VODSEL=0,CMLVODis±280mV,560mVp-p(typ)—shortcable(noDe-emph),low powermode. ThisiscanalsobecontrolbyI2Cregister. 4 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 PinFunctions,DS92LV2411Serializer(1)(continued) PIN TYPE DESCRIPTION NAME NO. CHANNEL-LINKII—CMLSERIALINTERFACE DOUT- 19 O,CML InvertingOutput. TheoutputmustbeACCoupledwitha0.1µFcapacitor. DOUT+ 20 O,CML Non–InvertingOutput. TheoutputmustbeACCoupledwitha0.1µFcapacitor. POWERANDGROUND GND DAP Ground DAPisthelargemetalcontactatthebottomside,locatedatthecenteroftheWQFN package.Connecttothegroundplane(GND)withatleast9vias. VDDHS 17 Power TXHighSpeedLogicPower,1.8V±5% VDDIO 30 Power LVCMOSI/OPower,1.8V±5%OR3.3V±10% VDDL 7 Power LogicPower,1.8V±5% VDDP 14 Power PLLPower,1.8V±5% VDDTX 22 Power OutputDriverPower,1.8V±5% Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com 60-PinWQFN PackageNKB TopView 0] 1] W L[ L[ O E E NC BISTEN VDDR PASS/OP_L DO0/MAP_S DO1/MAP_S DO2 VDDIO DO3/SSC0 DO4/SSC1 DO5/SSC2 DO6/SSC3 DO7 LOCK NC 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 NC 46 30 NC RES 47 29 VDDL VDDIR 48 28 DO8/OSC_SEL0 RIN+ 49 27 DO9/OSC_SEL1 RIN- 50 26 DO10/OSC_SEL2 CMF 51 25 DO11 ROUT+ 52 DS92LV2412 24 VDDIO TOP VIEW ROUT- 53 23 DO12/EQ0 VDDCMLO 54 DAP = GND 22 DO13/EQ1 VDDR 55 21 DO14/EQ2 ID[x] 56 20 DO15/EQ3 BOLD PIN NAME ± indicates I/O strap VDDPR 57 19 DO16 pin associated with output pin VDDSC 58 18 DO17/RFB PDB 59 17 DO18/OSS_SEL NC 60 16 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NC SDA SCL VDDSC CLKOUT CO1 CO3 CO2 DO23/CONFIG[0] DO22/CONFIG[1] O21/OS_CLKOUT DO20/LF_MODE VDDIO DO19/OS_DATA NC D PinFunctions,DS92LV2412Deserializer (1) PIN TYPE DESCRIPTION NAME NO. LVCMOSPARALLELINTERFACE CLKOUT 5 O,LVCMOS PixelClockOutput Inpower-down(PDB=0),outputiscontrolledbytheOSS_SELPin(SeeTable6).Data strobeedgesetbyRFB. CO1 6 O,LVCMOS ControlSignalOutput ForDisplay/VideoApplication: CO1=DataEnableOutput Controlsignalpulsewidthmustbe3clocksorlongertobetransmittedwhentheControl SignalFilterisenabled(CONFIG[1:0]=01).Thereisnorestrictionontheminimumtransition pulsewhentheControlSignalFilterisdisabled(CONFIG[1:0]=00). Thesignalislimitedto2transitionsper130clocksregardlessoftheControlSignalFilter setting. Inpower-down(PDB=0),outputiscontrolledbytheOSS_SELPin(SeeTable6). (1) NOTE:1=HIGH,0=LOW TheVDD(V andV )supplyrampshouldbefasterthan1.5mswithamonotonicrise.Ifslowerthen1.5msthenacapacitoron DDn DDIO thePDBPinisneededtoensurePDBarrivesafteralltheVDDhavesettledtotherecommendedoperatingvoltage. 6 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 PinFunctions,DS92LV2412Deserializer (1)(continued) PIN TYPE DESCRIPTION NAME NO. CO2 8 O,LVCMOS ControlSignalOutput ForDisplay/VideoApplication: CO2=HorizontalSyncOutput Controlsignalpulsewidthmustbe3clocksorlongertobetransmittedwhentheControl SignalFilterisenabled(CONFIG[1:0]=01).Thereisnorestrictionontheminimumtransition pulsewhentheControlSignalFilterisdisabled(CONFIG[1:0]=00). Thesignalislimitedto2transitionsper130clocksregardlessoftheControlSignalFilter setting. Inpower-down(PDB=0),outputiscontrolledbytheOSS_SELPin(SeeTable6). CO3 7 O,LVCMOS ControlSignalOutput ForDisplay/VideoApplication: CO3=VerticalSyncOutput CO3isdifferentthanCO1andCO2becauseitislimitedto1transitionper130clockcycles. Thus,theminimumpulsewidthallowedis130clockcyclewide. TheCONFIG[1:0]PinshavenoaffectonCO3signal Inpower-down(PDB=0),outputiscontrolledbytheOSS_SELPin(SeeTable6). DO[7:0] 33,34,35, I,STRAP, ParallelInterfaceDataOutputPins 36,37,39, O,LVCMOS For8–bitREDDisplay:DO7=R7–MSB,DO0=R0–LSB. 40,41 Inpower-down(PDB=0),outputsarecontrolledbytheOSS_SEL(SeeTable6).These Pinsareinputsduringpower-up(SeeSTRAPInputs). DO[15:8] 20,21,22, I,STRAP, ParallelInterfaceDataOutputPins 23,25,26, O,LVCMOS For8–bitGREENDisplay:DO15=G7–MSB,DO8=G0–LSB. 27,28 Inpower-down(PDB=0),outputsarecontrolledbytheOSS_SEL(SeeTable6).These Pinsareinputsduringpower-up(SeeSTRAPInputs). DO[23:16] 9,10,11, I,STRAP, ParallelInterfaceDataInputPins 12,14,17, O,LVCMOS For8–bitBLUEDisplay:DO23=B7–MSB,DO16=B0–LSB. 18,19 Inpower-down(PDB=0),outputsarecontrolledbytheOSS_SEL(SeeTable6).These Pinsareinputsduringpower-up(SeeSTRAPInputs). LOCK 32 O,LVCMOS LOCKStatusOutput LOCK=1,PLLisLocked,outputsareactiveLOCK=0,PLLisunlocked,DO[23:0],CO1, CO2,CO3andCLKOUToutputstatesarecontrolledbyOSS_SEL(SeeTable6).Maybe usedasLinkStatusortoflagwhenVideoDataisactive(ON/OFF). PASS 42 O,LVCMOS PASSOutput(BISTMode) PASS=1,errorfreetransmission PASS=0,oneormoreerrorsweredetectedinthereceivedpayload Routetotestpointformonitoring,orleaveopenifunused. CONTROLANDCONFIGURATION—STRAPPINS (2) CONFIG[1:0] 10[DO22], STRAP 00:ControlSignalFilterDISABLED.InterfaceswithDS92LV2411orDS92LV0411 9[DO23] I,LVCMOS 01:ControlSignalFilterENABLED.InterfaceswithDS92LV2411orDS92LV0411 w/pull-down 10:ReversecompatibilitymodetointerfacewiththeDS90UR241orDS99R241 11:ReversecompatibilitymodetointerfacewiththeDS90C241 EQ[3:0] 20[DO15], STRAP ReceiverInputEqualization 21[DO14], I,LVCMOS (SeeTable3). 22[DO13], w/pull-down ThiscanalsobecontrolledbyI2Cregisteraccess. 23[DO12] LF_MODE 12[DO20] STRAP SSCGLowFrequencyMode I,LVCMOS OnlyrequiredwhenSSCGisenabled,otherwiseLF_MODEconditionisaDON’TCARE(X). w/pull-down LF_MODE=1,SSCGinlowfrequencymode(CLK=5-20MHz) LF_MODE=0,SSCGinhighfrequencymode(CLK=20-50MHz) ThiscanalsobecontrolledbyI2Cregisteraccess. MAP_SEL[1:0] 40[D], STRAP Bitmappingreversecompatibility/DS90UR241Options 41[D] I,LVCMOS PinorRegisterControl w/pull-down Defaultsettingisb'00. (2) ForaHighState,usea10kΩpulluptoV ;foraLowState,theIOincludesaninternalpulldown.TheSTRAPPinsarereadupon DDIO power-upandsetdeviceconfiguration.PinNumberlistedalongwithshareddataoutputnameinsquarebrackets. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com PinFunctions,DS92LV2412Deserializer (1)(continued) PIN TYPE DESCRIPTION NAME NO. OP_LOW 42[PASS] STRAP OutputsheldLOWwhenLOCK=1 I,LVCMOS NOTE:Donotuseanyotherstrapoptionswiththisstrapfunctionenabled w/pull-down OP_LOW=1:alloutputsareheldLOWduringpowerupuntilreleasedbyprogramming OP_LOWrelease/setregisterHIGH. NOTE:Beforethedeviceispoweredup,theoutputsareinTRI-STATE SeeFigure26andFigure27 OP_LOW=0:alloutputstogglenormallyassoonasLOCKgoesHIGH(default) ThiscanalsobecontrolledbyI2Cregisteraccess. OS_CLKOUT 11[DO21] STRAP OutputCLKOUTSlewSelect I,LVCMOS OS_CLKOUT=1,IncreasedCLKOUTslewrate w/pull-down OS_CLKOUT=0,NormalCLKOUTslewrate(default) ThiscanalsobecontrolledbyI2Cregisteraccess. OS_DATA 14[DO19] STRAP OutputDO[23:0],CO1,CO2,CO3SlewSelect I,LVCMOS OS_DATA=1,IncreasedDOslewrate w/pull-down OS_DATA=0,NormalDOslewrate(default) ThiscanalsobecontrolledbyI2Cregisteraccess. OSS_SEL 17[DO18] STRAP OutputSleepStateSelect I,LVCMOS OSS_SELisusedinconjunctionwithPDBtodeterminethestateoftheoutputsinPower w/pull-down Down(Sleep).(SeeTable6). NOTE:OSS_SELSTRAPCANNOTBEUSEDIFOP_LOW=1 ThiscanalsobecontrolledbyI2Cregisteraccess. RFB 18[DO17] STRAP ClockOutputStrobeEdgeSelect I,LVCMOS RFB=1,parallelinterfacedataandcontrolsignalsarestrobedontherisingclockedge. w/pull-down RFB=0,parallelinterfacedataandcontrolsignalsarestrobedonthefallingclockedge. ThiscanalsobecontrolledbyI2Cregisteraccess. OSC_SEL[2:0] 26[DO10], STRAP OscillatorSelectl 27[DO9], I,LVCMOS (SeeTable7andTable8). 28[DO8] w/pull-down ThiscanalsobecontrolledbyI2Cregisteraccess. SSC[3:0] 34[DO6], STRAP SpreadSpectrumClockGeneration(SSCG)RangeSelect 35[DO5], I,LVCMOS (SeeTable4andTable5). 36[DO4], w/pull-down ThiscanalsobecontrolledbyI2Cregisteraccess. 37[DO3] CONTROLANDCONFIGURATION BISTEN 44 I,LVCMOS BISTEnableInput—Optional w/pull-down BISTEN=0,BISTisdisabled(normaloperation) BISTEN=1,BISTisenabled ID[x] 56 I,Analog I2CSerialControlBusDeviceIDAddressSelect—Optional ResistortoGroundand10kΩpull-upto1.8Vrail.(SeeTable11). NC 1,15,16, NotConnected 30,31,45, LeavePinopen(float) 46,60 PDB 59 I,LVCMOS PowerDownModeInput w/pull-down PDB=1,Desisenabled(normaloperation). Referto“PowerUpRequirementsandPDBPin”intheApplicationsInformationSection. PDB=0,Desisinpower-down. WhentheDesisinthepower-downstate,theLVCMOSoutputstateisdeterminedby Table6.ControlRegistersareRESET. RES 47 I,LVCMOS Reserved-tieLOW w/pull-down SCL 3 I,LVCMOS I2CSerialControlBusClockInput-Optional OpenDrain SCLrequiresanexternalpull-upresistorto3.3V. SDA 2 I/O,LVCMOS I2CSerialControlBusDataInput/Output-Optional OpenDrain SDArequiresanexternalpull-upresistorto3.3V. 8 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 PinFunctions,DS92LV2412Deserializer (1)(continued) PIN TYPE DESCRIPTION NAME NO. CHANNEL-LINKII—CMLSERIALINTERFACE CMF 51 I,Analog Common-ModeFilter VCMcenter-tapisavirtualgroundwhichmaybeACcoupledtogroundtoincreasereceiver commonmodenoiseimmunity.Recommendedvalueis4.7μForhigher. RIN+ 49 I,CML TrueInput.TheinputmustbeACCoupledwitha0.1μFcapacitor. RIN- 50 I,CML InvertingInput.TheinputmustbeACCoupledwitha0.1μFcapacitor. ROUT+ 52 O,CML TrueOutput—ReceiveSignalaftertheEqualizer NCifnotusedorconnecttotestpointformonitor.RequiresI2Ccontroltoenable. ROUT- 53 O,CML InvertingOutput—ReceiveSignalaftertheEqualizer NCifnotusedorconnecttotestpointformonitor.RequiresI2Ccontroltoenable. POWERANDGROUND(3) GND DAP Ground DAPisthelargemetalcontactatthebottomside,locatedatthecenteroftheWQFN package.Connectedtothegroundplane(GND)withatleast9vias. VDDCMLO 54 Power RXHighSpeedLogicPower,1.8V±5% VDDIO 13,24,38 Power LVCMOSI/OPower,1.8V±5%OR3.3V±10%(V ) DDIO VDDIR 48 Power InputPower,1.8V±5% VDDL 29 Power LogicPower,1.8V±5% VDDPR 57 Power PLLPower,1.8V±5% VDDR 43,55 Power RXHighSpeedLogicPower,1.8V±5% VDDSC 4,58 Power SSCGPower,1.8V±5% (3) PowermustbesuppliedtoallpowerPinsfornormaloperation Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings(1)(2)(3) MIN MAX UNIT SupplyVoltage–V (1.8V) −0.3 2.5 V DDn SupplyVoltage–V −0.3 4.0 V DDIO LVCMOSI/OVoltage −0.3 (VDDIO+0.3) V ReceiverInputVoltage −0.3 (VDD+0.3) V DriverOutputVoltage −0.3 (VDD+0.3) V JunctionTemperature +150 °C StorageTemperatureRange(T ) −65 +150 °C stg (1) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications. (2) “AbsoluteMaximumRatings”indicatelimitsbeyondwhichdamagetothedevicemayoccur,includinginoperabilityanddegradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximumRatingsor otherconditionsbeyondthoseindicatedintheRecommendedOperatingConditionsisnotimplied.TheRecommendedOperating Conditionsindicateconditionsatwhichthedeviceisfunctionalandthedeviceshouldnotbeoperatedbeyondsuchconditions. (3) Forsolderingspecifications,seeproductfolderatwww.ti.comandhttp://www.ti.com/lit/SNOA549 7.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±8000 Charged-devicemodel(CDM),perJEDECspecificationJESD22- V(ESD) Electrostaticdischarge C101(2) ±1000 V MachineModel(MM) ±250 IEC61000–4–2),R =330Ω,C =150pF D S AirDischarge(D ,D ) ±2500 OUT+ OUT- ContactDischarge(D ,D ) ±800 OUT+ OUT- V Electrostaticdischarge V (ESD) AirDischarge(R ,D ) ±2500 IN+ IN- ContactDischarge(R ,R ) ±800 IN+ IN- (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.Manufacturingwith lessthan500-VHBMispossibleifnecessaryprecautionsaretaken.PinslistedasD ,D orR ,D mayactuallyhavehigher OUT+ OUT- IN+ IN- performance. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.Manufacturingwith lessthan250-VCDMispossibleifnecessaryprecautionsaretaken.PinslistedasD ,D orR ,D mayactuallyhavehigher OUT+ OUT- IN+ IN- performance. 7.3 Recommended Operating Conditions MIN TYP MAX UNIT SupplyVoltage(V ) 1.71 1.8 1.89 V DDn LVCMOSSupplyVoltage(V ) 1.71 1.8 1.89 V DDIO OR LVCMOSSupplyVoltage(V ) 3.0 3.3 3.6 V DDIO OperatingFreeAirTemperature(T ) −40 +25 +85 °C A ClockFrequency 5 50 MHz SupplyNoise(1) 50 mV P-P (1) SupplynoisetestingwasdonewithminimumcapacitorsonthePCB.AsinusoidalsignalisACcoupledtotheV (1.8V)supplywith DDn amplitude=100mVp-pmeasuredatthedeviceV Pins.BiterrorratetestingofinputtotheSerandoutputoftheDeswith10meter DDn cableshowsnoerrorwhenthenoisefrequencyontheSerislessthan750kHz.TheDesontheotherhandshowsnoerrorwhenthe noisefrequencyislessthan400kHz. 10 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 7.4 Thermal Information RHS(2) NKB(3) THERMALMETRIC(1) UNIT 48PINS 60PINS R Junction-to-ambientthermalresistance 27.1 24.6 θJA °C/W R Junction-to-case(top)thermalresistance 4.5 2.8 θJC(top) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. (2) Ratingsformaximumdissipationcapacity(215mW). (3) Ratingsformaximumdissipationcapacity(478mW). 7.5 Serializer DC Electrical Characteristics Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.(1)(2)(3) PARAMETER TESTCONDITIONS PIN/FREQ. MIN TYP MAX UNIT LVCMOSINPUTDCSPECIFICATIONS V =3.0to3.6V 2.2 V DDIO DDIO HighLevelInput VIH Voltage V =1.71to1.89V 0.65* V V DDIO V DDIO DDIO V =3.0to3.6V DI[23:0], GND 0.8 DDIO LowLevelInput CI1,CI2,CI3,CLKIN, VIL Voltage V =1.71to1.89V PDB,VODSEL, GND 0.35* V DDIO RFB,BISTEN, VDDIO V =3.0to CONFIG[1:0] DDIO –15 ±1 +15 3.6V I InputCurrent V =0VorV μA IN IN DDIO V =1.71to DDIO –15 ±1 +15 1.89V CMLDRIVERDCSPECIFICATIONS DifferentialOutput VODSEL=0 ±205 ±280 ±355 V mV OD Voltage RL=100Ω,De- VODSEL=1 ±320 ±420 ±520 emph=disabled, DifferentialOutput VODSEL=0 560 mVp-p Figure2 V Voltage(DOUT+)– ODp-p (DOUT-) VODSEL=1 840 mVp-p R =100Ω,De- L ΔV emph=disabled, 1 50 mV OD VODSEL=L OffsetVoltage– R =100Ω,De- VODSEL=0 0.65 V L VOS Single-endedAtTPA emph=disabled DOUT+,DOUT- andB,Figure1 VODSEL=1 1.575 V OffsetVoltage R =100Ω,De-emph=disabled L UnbalanceSingle- ΔV 1 mV OS endedAtTPAandB, Figure1 DOUT+/-=0V, OutputShortCircuit I De-emph= VODSEL=0 –36 mA OS Current disabled InternalOutput R 80 100 120 Ω TO TerminationResistor (1) TheElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommendedOperatingConditionsexceptas otherwisemodifiedorspecifiedbytheElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) TypicalvaluesrepresentmostlikelyparametricnormsatV =3.3V,Ta=+25degC,andattheRecommendedOperationConditionsat DD thetimeofproductcharacterizationandarenotensured. (3) CurrentintodevicePinsisdefinedaspositive.CurrentoutofadevicePinisdefinedasnegative.Voltagesarereferencedtoground exceptVOD,ΔVOD,VTHandVTLwhicharedifferentialvoltages. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com Serializer DC Electrical Characteristics (continued) Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.(1)(2)(3) PARAMETER TESTCONDITIONS PIN/FREQ. MIN TYP MAX UNIT SUPPLYCURRENT SerializerSupply CheckerBoard V =1.89V AllV Pins 75 85 mA DD DD IDDT1 Current(includesload Pattern,De-emph V =1.89V 3 5 mA current)RL=100Ω, =3kΩ,VODSEL DDIO VDDIO IDDIOT1 CLKIN=50MHz =H,Figure9 VDDIO=3.6V 11 15 mA CheckerBoard V =1.89V AllV Pins 65 75 mA DD33 DD IDDT2 Pattern,De-emph V =1.89V 3 5 mA =6kΩ,VODSEL DDIO V DDIO IDDIOT2 =L,Figure9 VDDIO=3.6V 11 15 mA SerializerSupply PDB=0V,(All V =1.89V AllV Pins 40 1000 µA DD33 DD IDDZ CurrentPower-down otherLVCMOS V =1.89V 5 10 µA Inputs=0V) DDIO V DDIO I V =3.6V 10 20 µA DDIOZ DDIO 7.6 Deserializer DC Electrical Characteristics Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.(1) (2) (3) PARAMETER TESTCONDITIONS PIN/FREQ. MIN TYP MAX UNIT 3.3VI/OLVCMOSDCSPECIFICATIONS–VDDIO=3.0to3.6V HighLevelInput V 2.2 V V IH Voltage DDIO LowLevelInput PDB,BISTEN V GND 0.8 V IL Voltage I InputCurrent V =0VorV –15 ±1 +15 μA IN IN DDIO V HighLevelOutput IOH=−0.5mA,RDS=L DO[23:0],CO1, 2.4 V V OH Voltage CO2,CO3, DDIO V CLKOUT,LOCK, LowLevelOutput I =+0.5mA,RDS=L VOL Voltage OL PASS GND 0.4 V V =3.3V,V =0V, DDIO OUT CLKOUT OutputShortCircuit OS_PCLK/DATA=L/H I 36 mA OS Current V =3.3V,V =0V, DDIO OUT Outputs OS_PCLK/DATA=L/H TRI-STATEOutput I PDB=0V,OSS_SEL=0V,V =H Outputs –15 +15 μA OZ Current OUT 1.8VI/OLVCMOSDCSPECIFICATIONS–VDDIO=1.71to1.89V HighLevelInput V 1.235 V V IH Voltage DDIO LowLevelInput PDB,BISTEN V GND 0.595 V IL Voltage I InputCurrent V =0VorV –15 ±1 +15 µA IN IN DDIO V HighLevelOutput IOH=−0.5mA,RDS=L DO[23:0],CO1, VDDIO– V V OH Voltage CO2,CO3, 0.45 DDIO LowLevelOutput I =+0.5mA,RDS=L CLKOUT,LOCK, VOL Voltage OL PASS GND 0.45 V V =1.8V,V =0V, DDIO OUT CLKOUT 18 mA OutputShortCircuit OS_PCLK/DATA=L/H I OS Current V =1.8V,V =0V, DDIO OUT Outputs 18 mA OS_PCLK/DATA=L/H (1) TheElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommendedOperatingConditionsexceptas otherwisemodifiedorspecifiedbytheElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) TypicalvaluesrepresentmostlikelyparametricnormsatV =3.3V,Ta=+25degC,andattheRecommendedOperationConditionsat DD thetimeofproductcharacterizationandarenotensured. (3) CurrentintodevicePinsisdefinedaspositive.CurrentoutofadevicePinisdefinedasnegative.Voltagesarereferencedtoground exceptVOD,ΔVOD,VTHandVTLwhicharedifferentialvoltages. 12 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 Deserializer DC Electrical Characteristics (continued) Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.(1)(2)(3) PARAMETER TESTCONDITIONS PIN/FREQ. MIN TYP MAX UNIT TRI-STATEOutput I PDB=0V,OSS_SEL=0V,V =H Outputs –15 +15 µA OZ Current OUT CMLRECEIVERDCSPECIFICATIONS DifferentialInput V =+1.2V(InternalVBIAS) V CM +50 mV TH ThresholdHighVoltage DifferentialInput V –50 mV TL ThresholdLowVoltage RIN+,RIN- CommonMode V 12 V CM Voltage,InternalV BIAS I InputCurrent V =0VorV –15 +15 µA IN IN DDIO InternalInput R RIN+,RIN- 80 100 120 Ω TI TerminationResistor LOOPTHROUGHCMLDRIVEROUTPUTDCSPECIFICATIONS–EQTESTPORT DifferentialOutput R =100Ω V L 542 mV OD Voltage ROUT+/- OffsetVoltageSingle- R =100Ω V L 1.4 V OS ended InternalTermination R ROUT+/- 80 100 120 Ω T Resistor SUPPLYCURRENT Deserializer CheckerBoard V =1.89V AllV Pins 93 110 mA DD DD IDD1 SupplyCurrent Pattern,RDS= V =1.89V 33 45 mA (includesloadcurrent) H,CL=4pF, DDIO V DDIO IDDIO1 CLKOUT=50MHz Figure9 VDDIO=3.6V 62 75 mA DeserializerSupply PDB=0V,All V =1.89V AllV Pins 40 3000 µA DD DD IDDZ CurrentPowerDown otherLVCMOS V =1.89V 5 50 µA Inputs=0V DDIO V DDIO I V =3.6V 10 100 µA DDIOZ DDIO 7.7 DC and AC Serial Control Bus Characteristics Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V InputHighLevel SDAandSCL 2.2 V V IH DD3.3V V InputLowLevelVoltage SDAandSCL GND 0.8 V IL V InputHysteresis >50 mV HY V OutputLowVoltage(1) SDA,IOL=1.25mA,V =3.3V 0 0.4 V OL DDIO I SDAorSCL,Vin=V orGND -15 +15 µA in DDIO t SDARiseTime–READ SDA,RPU=X,Cb≤400pF 40 ns R t SDAFallTime–READ 25 ns F t SetUpTime—READ 520 ns SU;DAT t HoldUpTime—READ 55 ns HD;DAT t InputFilter 50 ns SP C InputCapacitance SDAorSCL <5 pF in (1) Specificationisensuredbycharacterizationandisnottestedinproduction. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com 7.8 Recommended Timing For The Serial Control Bus Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT f SCLClockFrequency StandardMode 100 kHz SCL FastMode 400 kHz t SCLLowPeriod StandardMode 4.7 µs LOW FastMode 1.3 µs t SCLHighPeriod StandardMode 4.0 µs HIGH FastMode 0.6 µs t Holdtimeforastartora StandardMode 4.0 µs HD;STA repeatedstartcondition, Figure18 FastMode 0.6 µs t SetUptimeforastartora StandardMode 4.7 µs SU:STA repeatedstartcondition, Figure18 FastMode 0.6 µs t DataHoldTime, StandardMode 0 3.45 µs HD;DAT Figure18 FastMode 0 0.9 µs t DataSetUpTime, StandardMode 250 ns SU;DAT Figure18 FastMode 100 ns t SetUpTimeforSTOP StandardMode 4.0 µs SU;STO Condition,Figure18 FastMode 0.6 µs t BusFreeTime StandardMode 4.7 µs BUF BetweenSTOPandSTART, Figure18 FastMode 1.3 µs t SCLandSDARiseTime, StandardMode 1000 ns r Figure18 FastMode 300 ns t SCLandSDAFallTime, StandardMode 300 ns f Figure18 Fastmode 300 ns A CA A' Scope 50:(cid:3) 50:(cid:3) B CB B' 50:(cid:3) 50:(cid:3) Figure1. SerializerTestCircuit d DOUT+ de VOD+ VOD- e-En DOUT- VOS Singl GND (DOUT+) - (DOUT+) VOD+ VODp-p VOD- 0V Differential Figure2. SerializerOutputWaveforms 14 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 +VOD 80% (DOUT+) - (DOUT-) 0V 20% -VOD tLLHT tLHLT Figure3. SerializerOutputTransitionTimes tTCP tTCIH tTCIL CLKIN 80% VDDIO w/ RFB = L 1/2 VDDIO 20% GND tCLKT tCLKT DI[23:0], VIHmin VDDIO CI1,CI2,CI3 VILmax GND tDIS tDIH Figure4. SerializerInputCLKINWaveformAndSetAndHoldTimes PDB 1/2 VDDIO CLKIN "X" active tPLD DOUT (Diff.) Driver OFF, VOD= 0V Driver On Figure5. SerializerLockTime PDB 1/2 VDDIO CLKIN active "X" tXZD DOUT active (Diff.) Driver OFF, VOD = 0V Figure6. SerializerDisableTime Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com DIN[23:0], SYMBOL N SYMBOL N+1 CI1,CI2,CI3 tSD CLKIN (RFB = L) START STOP START STOP BIT BIT BIT BIT DOUT (Diff.) SYMBOL N-1 SYMBOL N Figure7. SerializerLatencyDelay tDJIT tDJIT VOD (+) DOUT TxOUT_E_O 0V (Diff.) VOD (-) tBIT (1 UI) Figure8. SerializerOutputJitter CLKIN/ VDDIO CLKOUT w/ RFB = L GND DI/DO (odd), VDDIO CI2/CO2, CI3/CO3 GND VDDIO DI/DO (even), CI1/CO1 GND Figure9. CheckerboardDataPattern VDDIO 80% 20% GND tCLH tCHL Figure10. DeserializerLVCMOSTransitionTimes START STOP START STOP BIT BIT BIT BIT RIN (Diff.) SYMBOL N SYMBOL N+1 tDD CLKOUT (RFB = L) DO[23:0], SYMBOL N-2 SYMBOL N-1 SYMBOL N CO1,CO2,CO3 Figure11. DeserializerDelay –Latency 16 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 PDB 1/2 VDDIO RIN active "X" (Diff.) tXZR CLKOUT, DO[23:0], active Z (TRI-STATE) CO1,CO2,CO3 PASS, LOCK Figure12. DeserializerDisableTime(OSS_SEL=0) PDB 2.0V 0.8V RIN 'RQ¶W(cid:3)&DUH (Diff.) tDDLT LOCK TRI-STATE Z or L or LOW tRxZ DO[23:0], CO1,CO2,CO3 TRI-STATE or LOW or Pulled Up Z or L or PU CLKOUT TRI-STATE or LOW Z or L (RFB = L) OFF IN LOCK TIME ACTIVE OFF Figure13. DeserializerPLLLockTimesAndPDBTri-StateDelay VDDIO CLKOUT w/RFB = H 1/2 VDDIO GND VDDIO CO1,CDOO2[2,C3:O03], 1/2 VDDIO 1/2 VDDIO GND tROS tROH Figure14. DeserializerOutputDataValid(SetupAndHold)TimesWithSSCG=Off VDDIO CLKOUT w/RFB = H 1/2 VDDIO GND CO1,CDOO2[2,C3:O03], 1/2 VDDIO 1/2 VDDIO VDDIO GND tROS tROH Figure15. DeserializerOutputDataValid(SetupAndHold)TimesWithSSCG=On Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com Ideal Data Bit Sampling Ideal Data Beginning Window Bit End VTH 0V RxIN_TOL RxIN_TOL Left Right VTL Ideal Center Position (tBIT/2) tBIT (1 UI) tRJIT = RxIN_TOL (Left + Right) Sampling Window = 1 UI - tRJIT Figure16. ReceiverInputJitterTolerance BISTEN 1/2 VDDIO t PASS PASS (w/ errors) 1/2 VDDIO Prior BIST Result Current BIST Test - Toggle on Error Result Held Figure17. BISTPassWaveform SDA tf tLOW tHD;STA tr tBUF tr tf tSP SCL tHD;STA tSU;STA tSU;STO tHIGH tHD;DAT tSU;DAT START REPEATED STOP START START Figure18. SerialControlBusTimingDiagram 7.9 Recommended Serializer Timing For CLKIN Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t TransmitInputCLKINPeriod 5MHzto50MHz,Figure4 20 T 200 ns TCP t TransmitInputCLKINHighTime 0.4T 0.5T 0.6T ns TCIH t TransmitInputCLKINLowTime 0.4T 0.5T 0.6T ns TCIL t CLKINInputTransitionTime 0.5 2.4 ns CLKT SSC CLKINInput–SpreadSpectrum fmod 35 kHz IN at50MHz fdev ±0.02 kHz f MOD 18 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 7.10 Serializer Switching Characteristics Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t SerOutputLow-to-High R =100Ω,De-emphasis=disabled, LHT L 200 ps TransitionTime,Figure3 VODSEL=0 R =100Ω,De-emphasis=disabled, L 200 ps VODSEL=1 t SerOutputHigh-to-Low R =100Ω,De-emphasis=disabled, HLT L 200 ps TransitionTime,Figure3 VODSEL=0 R =100Ω,De-emphasis=disabled, L 200 ps VODSEL=1 t InputData-SetupTime, DI[23:0],CI1,CI2,CI3toCLKIN DIS 2 ns Figure4 t InputData-HoldTime, CLKINtoDI[23:0],CI1,CI2,CI3 DIH 2 ns Figure4 t SerOutputActivetoOFF XZD 8 15 ns Delay,Figure6 t SerializerPLLLockTime(1), R =100Ω PLD L 1.4 10 ms Figure5 t SerializerDelay-Latency, R =100Ω SD L 144*T 145*T ns Figure7 t SerOutputTotalJitter, R =100Ω,De-Emph=disabled, DJIT L 0.28 UI Figure8 RANDOMpattern,CLKIN=50MHz R =100Ω,De-Emph=disabled, L 0.27 UI RANDOMpattern,CLKIN=43MHz R =100Ω,De-Emph=disabled, L 0.35 UI RANDOMpattern,CLKIN=5MHz λ SerializerJitterTransfer CLKIN=50MHz 3 MHz STXBW Function-3dBBandwidth CLKIN=43MHz 2.3 MHz CLKIN=20MHz 1.3 MHz CLKIN=5MHz 650 kHz δ SerializerJitterTransfer CLKIN=50MHz 0.84 dB STX FunctionPeaking CLKIN=43MHz 0.83 dB CLKIN=20MHz 0.83 dB CLKIN=5MHz 0.28 dB (1) WhentheSerializeroutputisatTRI-STATEtheDeserializerwilllosePLLlock.Resynchronization/Relockmustoccurbeforedata transferrequiret PLD Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com 7.11 Deserializer Switching Characteristics Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified. PARAMETER TESTCONDITIONS PIN/FREQ. MIN TYP MAX UNIT t CLKOutputPeriod t =t CLKOUT 20 T 200 ns RCP RCP TCP t CLKOutputDutyCycle SSCG=OFF,5–50MHz 0.43T 0.50T 0.57T ns RDC SSCG=ON,5–20MHz 0.35T 0.59T 0.65T ns SSCG=ON,20–50MHz 0.40T 0.53T 0.60T ns t LVCMOS V =1.8V, CLKOUT/DO[23:0], CLH DDIO Low-to-High C =4pF, CO1,CO2,CO3 2.1 ns L TransitionTime, OS_CLKOUT/DATA=L Figure10 V =3.3V DDIO C =4pF, 2.0 ns L OS_CLKOUT/DATA=H t LVCMOS V =1.8V CLKOUT/DO[23:0], CHL DDIO High-to-Low C =4pF, CO1,CO2,CO3 1.6 ns L TransitionTime, OS_CLKOUT/DATA=L Figure10 V =3.3V DDIO C =8pF, 1.5 ns L OS_CLKOUT/DATA=H t DataValidbefore V =1.71to1.89Vor DO[23:0],CO1,CO2, ROS DDIO CLKOUT–SetUpTime, V =3.0to3.6V CO3 0.27 0.45 T DDIO Figure14 C =4pF(lumpedload) L t DataValidafter V =1.71to1.89Vor DO[23:0],CO1,CO2, ROH DDIO CLKOUT–HoldTime, V =3.0to3.6V CO3 0.4 0.55 T DDIO Figure14 C =4pF(lumpedload) L t DeserializerLockTime, SSC[3:0]=OFF, CLKOUT=5MHz DDLT Figure13 See(1) 3 ms SSC[3:0]=OFF, CLKOUT=50MHz See(1) 4 ms SSC[3:0]=ON, CLKOUT=5MHz See(1) 30 ms SSC[3:0]=ON, CLKOUT=50MHz See(1) 6 ms t DesDelay-Latency, SSC[3:0]=ON, CLKOUT=5to50MHz DD Figure11 See(2) 139*T 140*T ns t DesPeriodJitter SSC[3:0]=OFF, CLKOUT=5MHz 975 1700 ps DPJ See(3) CLKOUT=10MHz 500 1000 ps CLKOUT=50MHz 550 1250 ps t DesCycle-to-CycleJitter SSC[3:0]=OFF, CLKOUT=5MHz 675 1150 ps DCCJ See(2) CLKOUT=10MHz 375 900 ps CLKOUT=50MHz 500 1150 ps t DesInputJitter EQ=OFF, jitterfreq<2MHz 0.9 UI(4) IIT Tolerance,Figure16 SSCG=OFF, CLKOUT=50MHz jitterfreq>6MHz 0.5 UI(4) BISTMODE t BISTPASSValidTime, PASS 1 10 µs BISTEN=1,Figure17 SSCGMODE f SpreadSpectrum Undertypicalconditions CLKOUT=5to50MHz, DEV ±0.005 ±0.02 ClockingDeviation SSC[3:0]=ON KHz f f Frequency MOD MOD f SpreadSpectrum Undertypicalconditions CLKOUT=5to50MHz, MOD ClockingModulation SSC[3:0]=ON 8 100 kHz Frequency (1) t andt isthetimerequiredbytheserializeranddeserializertoobtainlockwhenexitingpower-downstatewithanactiveclock. PLD DDLT (2) t isthemaximumamountofjitterbetweenadjacentclockcycles. DCCJ (3) t isthemaximumamounttheperiodisallowedtodeviateovermanysamples. DPJ (4) UI–UnitIntervalisequivalenttooneserializeddatabitwidth(1UI=1/(28*CLK)).TheUIscaleswithclockfrequency. 20 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 7.12 Typical Characteristics 50 MHz TX Pixel Clock Input (2 V/DIV) CML Serializer Data Throughput (100 mV/DIV) 50 MHz RX Pixel Clock Input (2 V/DIV) Time (1 ns/DIV) Time (20 ns/DIV) Note:Ontherisingedgeofeachclockperiod,theCMLdriveroutputs Note:Whenbothdevicesarelockedandthescopeistriggeredfrom alowStopbit,highStartbit,and28DC-scrambleddatabits. theTXpixelclock,theRXclockisgenlockedtotheTXpixelclock Figure19.SerializerCMLDriverOutputwith50MHzTX anddoesnotdrift. PixelClock. Figure20.ComparisonofDeserializerLVCMOSRXClock Outputlockedtoa50MHzTXPixelClock. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com 8 Detailed Description 8.1 Overview The DS92LV2411 / DS92LV2412 chipset transmits and receives 24-bits of data and 3 control signals over a single serial CML pair operating at 140 Mbps to 1.4 Gbps. The serial stream also contains an embedded clock, videocontrolsignalsandtheDC-balanceinformationwhichenhancessignalqualityandsupportsACcoupling. The Des can attain lock to a data stream without the use of a separate reference clock source, which greatly simplifies system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data pattern, delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without the need of special training patterns or sync characters. The Des recovers the clock and data by extracting the embedded clock information, validating and then deserializing the incoming data stream providing a parallel LVCMOSvideobustothedisplayorASIC/FPGA. The DS92LV2411 / DS92LV2412 chipset can operate in 24-bit color depth (with DE, HS, VS encoded within the serial data stream). In 18–bit color applications, the three video control signals maybe sent encoded within the serialbitstream(restrictionsapply)alongwithsixadditionalgeneralpurposesignals. 8.2 Functional Block Diagrams VODSEL De-Emph re DI[23:0] do la CCCIII123///DHVESS hctaL tupn cnE ecnala ireS ot lella DDOOUUTT+- RFB I B C raP D Pattern CLKIN PLL Generator CONFIG[1:0] PDB Timing and SCL Control SCA ID[x] BISTEN DS92LV2411 ± SERIALIZER 22 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 Functional Block Diagrams (continued) STRAP INPUT SSCG LF_MODE OS_CLKOUT ROUT+ OS_DATA RORCUIMNTF+- EQ lellaraP ot laireS redoceD ecnalaB C hctaL tuptuO DCCCOOOO[1232///3DHV:SES0] OREOSCMQSFOSSABCS CNP[3 ___F[:3SSSI0G:EEE]0 L]LL[1 [[:210::]00]] RIN- D STRAP INPUT Error PASS BISTEN Detector OP_LOW PDB SCL Timing and Clock and CLKOUT Data SCA Control LOCK Recovery ID[x] DS92LV2412 ± DESERIALIZER 8.3 Feature Description 8.3.1 SerializerFunctionalDescription The Ser converts a wide parallel input bus to a single serial output data stream, and also acts as a signal generator for the chipset Built In Self Test (BIST) mode. The device can be configured via external Pins or through the optional serial control bus. The Ser features enhance signal quality on the link by supporting: a selectable VOD level, a selectable de-emphasis signal conditioning and also the Channel Link II data coding that provides randomization, scrambling, and DC Balancing of the data. The Ser includes multiple features to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the data and also the system spread spectrum clock support. The Ser features power saving features with a sleep mode, auto stopclockfeature,andoptionalLVCMOS(1.8V)parallelbuscompatibility. 8.3.1.1 EMIReductionFeatures 8.3.1.1.1 DataRandomizationandScrambling Channel Link II Ser / Des feature a 3 step encoding process which enables the use of AC coupled interconnects and also helps to manage EMI. The serializer first passes the parallel data through a scrambler which randomizes the data. The randomized data is then DC balanced. The DC balanced and randomized data then goes through a bit shuffling circuit and is transmitted out on the serial line. This encoding process helps to prevent static data patterns on the serial stream. The resulting frequency content of the serial stream ranges from the parallel clock frequency to the nyquist rate. For example, if the Ser / Des chip set is operating at a parallel clock frequency of 50 MHz, the resulting frequency content of serial stream ranges from 50 MHz to 700 MHz(50MHz*28bits=1.4Gbps/2=700MHz). 8.3.1.1.2 Ser—SpreadSpectrumCompatibility The Ser CLKIN is capable of tracking spread spectrum clocking (SSC) from a host source. The CLKIN will accept spread spectrum tracking up to 35 kHz modulation and ±0.5, ±1 or ±2% deviations (center spread). The maximum conditions for the CLKIN input are: a modulation frequency of 35 kHz and amplitude deviations of ±2% (4%total). Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com Feature Description (continued) 8.3.1.2 IntegratedSignalConditioningFeatures —Ser 8.3.1.2.1 Ser—VODSelect(VODSEL) The Ser differential output voltage may be increased by setting the VODSEL Pin High. When VODSEL is Low, the VOD is at the standard (default) level. When VODSEL is High, the VOD is increased in level. The increased VOD is useful in extremely high noise environments and also on extra long cable length applications. When using de-emphasis it is recommended to set VODSEL = H to avoid excessive signal attenuation especially with thelargerde-emphasissettings.ThisfeaturemaybecontrolledbytheexternalPinorbyregister. Table1.DifferentialOutputVoltage INPUT EFFECT VOD VOD VODSEL mV mVp-p H ±420 840 L ±280 560 8.3.1.2.2 Ser—De-Emphasis(De-Emph) The De-Emph Pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the Ser drives. This is useful to counteract loading effects of long or lossy cables. This Pin should be left open for standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by connecting a resistor on this Pin to ground, with R value between 0.5 kΩ to 1 MΩ, or by register setting. When using De- EmphasisitisrecommendedtosetVODSEL=H. Table2. De-EmphasisResistorValue RESISTORVALUE(kΩ) DE-EMPHASISSETTING Open Disabled 0.6 -12dB 1.0 -9dB 2.0 -6dB 5.0 -3dB 0.00 VDD = 1.8V, -2.00 TA = 25oC -4.00 )B d ( H -6.00 P M E -8.00 -E D -10.00 -12.00 -14.00 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 R VALUE - LOG SCALE (:) Figure21. De-Emphvs.RValue 24 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 8.3.1.3 PowerSavingFeatures 8.3.1.3.1 Ser—PowerDownFeature(PDB) The Ser has a PDB input Pin to ENABLE or POWER DOWN the device. This Pin is controlled by the host and is used to save power, disabling the link when the it is not needed. In the POWER DOWN mode, the high-speed driveroutputsarebothpulledtoVDDandpresenta0VVODstate.Note –inPOWERDOWN,theoptionalSerial BusControlRegistersareRESET. 8.3.1.3.2 Ser—StopClockFeature The Ser will enter a low power SLEEP state when the CLKIN is stopped. A STOP condition is detected when the input clock frequency is less than 3 MHz. The clock should be held at a static Low or high state. When the CLKIN starts again, the Ser will then lock to the valid input clock and then transmits the serial data to the Des. Note–inSTOPCLOCKSLEEP,theoptionalSerialBusControlRegistersvaluesare RETAINED. 8.3.1.3.3 1.8Vor3.3VVDDIOOperation TheSerparallelbusandSerialBusInterfacecanoperatewith1.8Vor3.3Vlevels(V )forhostcompatibility. DDIO The1.8Vlevelswillofferlowernoise(EMI)andalsoasystempowersavings. 8.3.1.4 Ser—PixelClockEdgeSelect(RFB) The RFB Pin determines the edge that the data is latched on. If RFB is High, input data is latched on the Rising edge of the CLKIN. If RFB is Low, input data is latched on the Falling edge of the CLKIN. Ser and Des maybe setdifferently.ThisfeaturemaybecontrolledbytheexternalPinorbyregister. 8.3.1.5 OptionalSerialBusControl PleaseseethefollowingsectionontheoptionalSerialBusControlInterface. 8.3.1.6 OptionalBISTMode PleaseseethefollowingsectiononthechipsetBISTmodefordetails. 8.3.2 DeserializerFunctionalDescription The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal check for the chipset Built In Self Test (BIST) mode. The device can be configured via external Pins and strap Pins or through the optional serial control bus. The Des features enhance signal quality on the link with an integrated equalizer on the serial input and Channel Link II data encoding which provides randomization, scrambling, and DC balancing of the data. The Des includes multiple features to reduce EMI associated with data transmission. This includes the randomization and scrambling of the data, the output spread spectrum clock generation (SSCG) support and output clock and data slew rate select. The Des features power saving features withapowerdownmode,andoptionalLVCMOS(1.8V)interfacecompatibility. 8.3.2.1 IntegratedSignalConditioningFeatures —Des 8.3.2.1.1 Des—InputEqualizerGain(Eq) The Des can enable receiver input equalization of the serial stream to increase the eye opening to the Des input. Note this function cannot be seen at the RxIN+/- input but can be observed at the serial test port (ROUT+/-) enabled via the Serial Bus control registers. The equalization feature may be controlled by the external Pin or by register. Table3. ReceiverEqualizationConfiguration INPUTS EFFECT EQ3 EQ2 EQ1 EQ0 L L L H ~1.5dB L L H H ~3dB L H L H ~4.5dB L H H H ~6dB Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com Table3. ReceiverEqualizationConfiguration (continued) INPUTS EFFECT EQ3 EQ2 EQ1 EQ0 H L L H ~7.5dB H L H H ~9dB H H L H ~10.5dB H H H H ~12dB X X X L OFF* *DefaultSettingisEQ=Off 8.3.2.2 EMIReductionFeatures 8.3.2.2.1 Des—OutputSlewRateSelect(OS_CLKOUT/OS_DATA) The parallel data outputs and clock outputs of the deserializer feature selectable output slew rates. The slew rate of the CLKOUT Pin is controlled by the strap Pin or register OS_CLKOUT, while the data outputs (DO[23:0] and CO[3:1]) are controlled by the strap Pin or register OS_DATA. When OS_CLKOUT/DATA = HIGH, the maximum slew rate is selected. When the OS_CLKOUT/DATA = LOW, the minimum slew rate is selected. Use the higher slewratewhendrivinglongertracesoraheaviercapacitiveload. 8.3.2.2.2 Des—CommonModeFilterPin(CMF)—Optional The Des provides access to the center tap of the internal termination. A capacitor may be placed on this Pin for additional common-mode filtering of the differential pair. This can be useful in high noise environments for additionalnoiserejectioncapability.A4.7 µFcapacitormaybeconnectedtothisPintoGround. 8.3.2.2.3 Des—SSCGGeneration—Optional The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2% (4% total) at up to 100 kHz modulations is available. See Table 4. This feature may be controlled by external STRAP Pins or by register. Table4. SSCGConfiguration(LF_MODE=L) —DesOutput SSC[3:0]INPUTS RESULT LF_MODE=L(20-50MHz) SSC3 SSC2 SSC1 SSC0 fdev(%) fmod(kHz) L L L L NA Disable L L L H ±0.5 L L H L ±1.0 CLK/2168 L L H H ±1.5 L H L L ±2.0 L H L H ±0.5 CLK/1300 L H H L ±1.0 L H H H ±1.5 H L L L ±2.0 H L L H ±0.5 CLK/868 H L H L ±1.0 H L H H ±1.5 H H L L ±2.0 H H L H ±0.5 CLK/650 H H H L ±1.0 H H H H ±1.5 26 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 Table5. SSCGConfiguration(Lf_mode=H) —DesOutput SSC[3:0]INPUTS RESULT LH_MODE=H(5-20MHz) SSC3 SSC2 SSC1 SSC0 fdev(%) fmod(kHz) L L L L NA Disable L L L H ±0.5 L L H L ±1.0 CLK/620 L L H H ±1.5 L H L L ±2.0 L H L H ±0.5 CLK/370 L H H L ±1.0 L H H H ±1.5 H L L L ±2.0 H L L H ±0.5 CLK/258 H L H L ±1.0 H L H H ±1.5 H H L L ±2.0 H H L H ±0.5 CLK/192 H H H L ±1.0 H H H H ±1.5 Frequency FCLKOUT+ fdev(max) FCLKOUT FCLKOUT- fdev(min) Time 1/fmod Figure22. SSCGWaveform 8.3.2.2.4 1.8Vor3.3VVDDIOOperation The Des parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (V ) for target host DDIO compatibility.The1.8Vlevelswillofferalowernoise(EMI)andalsoasystempowersavings. 8.3.2.3 PowerSavingFeatures 8.3.2.3.1 Des—PowerdownFeature(PDB) The Des has a PDB input Pin to ENABLE or POWER DOWN the device. This Pin can be controlled by the system to save power, disabling the Des when the display is not needed. An auto detect mode is also available. In this mode, the PDB Pin is tied High and the Des will enter POWER DOWN when the serial stream stops. Whentheserialstreamstartsupagain,theDeswilllocktotheinputstreamandasserttheLOCKPinandoutput valid data. In POWER DOWN mode, the Data and CLKOUT output states are determined by the OSS_SEL status.Note– inPOWERDOWN,theoptionalSerialBusControlRegistersare RESET. 8.3.2.3.2 Des—StopStreamSleepFeature The Des will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition is detected when the embedded clock bits are not present. When the serial stream starts again, the Des will then lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the optional Serial Bus ControlRegistersvaluesare RETAINED. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com 8.3.2.4 Des—Clock-DataRecoveryStatusFlag(Lock)AndOutputStateSelect(OSS_SEL) When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to LOW (depending on the value of the OSS_SEL setting). After the DS92LV2412 completes its lock sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available on the parallel bus and clock outputs. The CLKOUT output is held at its current state at the changefromOSC_CLK(ifthisisenabledviaOSC_SEL)totherecoveredclock(orviceversa). If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the outputs are based ontheOSS_SELsetting(STRAPPinconfigurationorregister). 8.3.2.5 Des—OscillatorOutput —Optional The Des provides an optional clock output when the input clock (serial stream) has been lost. This is based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by the externalPinorbyregister.SeeTable7andTable8. Table6. OSS_SELAndPDBConfiguration —DesOutputs INPUTS OUTPUTS SERIAL PDB OSS_SEL CLKOUT DO[23:0],CO1, LOCK PASS INPUT CO2,CO3 X L L Z Z Z Z X L H Z Z Z Z Static H L L L L L Static H H Z Z* L L Active H X Active Active H H *NOTE—IfPinisstrappedHIGHtheoutputwillbepulledup Table7. OSC(Oscillator)Mode —DesOutput INPUTS OUTPUTS EMBEDDEDCLK CLKOUT DO[23:0]/CO1/CO2/CO3 LOCK PASS NOTE* OSC L L H Output Present Toggling Active H H *NOTE—AbsentandOSC_SEL≠000 28 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 PDB (DES) RIN (Diff.) active serial stream X LOCK Z H H Z L L DO[23:0], CO1,CO2,CO3 Z Z L L CLKOUT* (DES) Z Z L L OFF Locking Active C0 or C1 Error Active OFF In Bit Stream (Loss of LOCK) CONDITIONS: * RFB = L, and OSS_SEL Strap = L Figure23. DesOutputsWithOutputStateSelectLow(OSS_SEL=L) PDB (DES) RIN active serial stream X (Diff.) Z H H Z LOCK L L DO[23:0], Z Z Z CO1,CO2,CO3 CLKOUT* Z Z Z (DES) OFF Locking Active C0 or C1 Error Active OFF In Bit Stream (Loss of LOCK) CONDITIONS: * RFB = L, and OSS_SEL Strap = H Figure24. DesOutputsWithOutputStateSelectHigh(OSS_SEL=H) Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com Table8. OSC_SEL(Oscillator)Configuration OSC_SEL[2:0]INPUTS CLKOUTOSCILLATORFREQUENCY OSC_SEL2 OSC_SEL1 OSC_SEL0 L L L Off–FeatureDisabled–Default L L H 50MHz±40% L H L 25MHz±40% L H H 16.7MHz±40% H L L 12.5MHz±40% H L H 10MHz±40% H H L 8.3MHz±40% H H H 6.3MHz±40% PDB (DES) RIN active serial stream X (Diff.) Z H H LOCK L L Z DO[23:0], Z Z CO1,CO2,CO3 L L CLKOUT* Z Z (DES) L f f H H Z PASS Z L L OFF Locking Active C0 or C1 Error Active OFF In Bit Stream (Loss of LOCK) CONDITIONS: * RFB = L, OSS_SEL = H , and OSC_SEL not equal to 000. Figure25. DesOutputsWithOutputStateHighAndClkOutputOscillatorOptionEnabled 8.3.2.6 Des—OP_LOW —Optional The OP_LOW feature is used to hold the LVCMOS outputs, except for the LOCK output, at a LOW state. When the OP_LOW feature is enabled, the LVCMOS outputs will be held at logic LOW while LOCK = LOW. The user must toggle the OP_LOW Set/Reset register bit to release the outputs to the normal toggling state. Note that the release of the outputs can only occur when LOCK is HIGH. The OP_LOW strap option is assigned to the PASS Pin,atPinlocation42. Restrictionsonotherstraps: 1. OtherstrapoptionsshouldnotbeusedinordertokeepthedataandclockoutputsatatruelogicLOWstate. OtherfeaturesshouldbeselectedthroughtheI2Cregisterinterface. 2. TheOSS_SELfeatureisnotavailablewhenOP_LOWisenabled. Outputs DO[23:0], CO[3:1] and CLKOUT are in TRI-STATE before PDB toggles HIGH because the OP-LOW strap value has not been recognized until the DS92LV2412 powers up. Figure 26 shows the user controlled release of the OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 27 shows the user controlled release of OP_LOW and manual reset of OP_LOW set. Note manual reset of OP_LOW can only occurwhenLOCKisHIGH. 30 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 2.0V PDB LOCK OP_ LOW SET (Strap pin) User User controlled controlled OP_ LOW RELEASE/SET (Register) DO[23:0], TRI- ACTIVE ACTIVE CO3, CO2, CO1 STATE TRI- CLKOUT STATE ACTIVE ACTIVE Figure26. OP_LOWAutoSet 2.0V PDB LOCK OP_LOW SET (Strap pin) User User controlled controlled OP_ LOW RELEASE/SET (Register) DO[23:0], TRI- ACTIVE CO3, CO2, CO1 STATE TRI- CLKOUT STATE ACTIVE Figure27. OP_LOWManualSet/Reset 8.3.2.7 Des—ClockEdgeSelect(RFB) The RFB Pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the Rising edge of the CLKOUT. If RFB is Low, data is strobed on the Falling edge of the CLKOUT. This allows for inter-operability with downstream devices. The Des output does not need to use the same edge as the Ser input. ThisfeaturemaybecontrolledbytheexternalPinorbyregister. 8.3.2.8 Des—ControlSignalFilter —Optional The deserializer provides an optional Control Signal (C3, C2, C1) filter that monitors the three control signals and eliminates any pulses or glitches that are 1 or 2 parallel clock periods wide. Control signals must be 3 parallel clockperiodswide(initsHIGHorLOWstate,regardlessofwhichstateisactive).ThisissetbytheCONFIG[1:0] strapoptionorbyI2Cregistercontrol. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com 8.3.2.9 Des—SSCGLowFrequencyOptimization(Lf_mode) Texttocome.ThisfeaturemaybecontrolledbytheexternalPinorbyRegister. 8.3.2.10 Des—StrapInputPins Configuration of the device maybe done via configuration input Pins and the STRAP input Pins, or via the Serial Control Bus. The STRAP input Pins share select parallel bus output Pins. They are used to load in configuration values during the initial power up sequence of the device. Only a pull-up on the Pin is required when a HIGH is desired. By default the pad has an internal pull down, and will bias Low by itself. The recommended value of the pull up is 10 kΩ to V ; open (NC) for Low, no pull-down is required (internal pull-down). If using the Serial DDIO ControlBus,nopullupsarerequired. 8.3.3 BuiltInSelfTest(BIST) An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST mode only a input clock is required along with control to the Ser and Des BISTEN input Pins. The Ser outputs a test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors. A PASS output Pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the test,theresultofthetestisheldonthePASSoutputuntilreset(newBISTtestorPowerDown).AhighonPASS indicatesNOERRORSweredetected.ALowonPASSindicatesoneormoreerrorsweredetected.Theduration of the test is controlled by the pulse width applied to the Des BISTEN Pin. During the BIST duration, the deserializerdataoutputstogglewithacheckerboardpattern. Inter-operabilityissupportedbetweenthisChannelLinkIIdeviceandallChannelLinkIIgenerations(Gen1/2/3). Note: In order to use BIST mode, the BISTEN Pin must be pulled high and REG = 0. The serializer cannot be placedinBISTmodeifREG=1,asthiswillcausetheDS92LV2411toignorethepininputvoltage. 8.3.3.1 SampleBISTSequence SeeFigure28fortheBISTmodeflowdiagram. Step 1: Place the DS92LV2411 Ser in BIST Mode by setting Ser BISTEN = H. For the DS92LV2411 Ser or DS99R421 Channel Link II Ser BIST Mode is enabled via the BISTEN Pin. A CLKIN is required for BIST. When the Des detects the BIST mode pattern and command (DCA and DCB code) the data and control signal outputs areshutoff. Step2:PlacetheDS92LV2412DesinBISTmodebysettingtheBISTEN=H.TheDesisnowintheBISTmode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS Pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and countedtodeterminethepayloaderrorrate. Step 3: To Stop the BIST mode, the Des BISTEN Pin is set Low. The Des stops checking the data and the final test result is held on the PASS Pin. If the test ran error free, the PASS output will be High. If there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the deviceisRESET,orPoweredDown.TheBISTdurationisusercontrolledbythedurationoftheBISTENsignal. Step 4: To return the link to normal operation, the Ser BISTEN input is set Low. The Link returns to normal operation. Figure 29 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting theinterconnect,reducingsignalconditionenhancements(De-Emphasis,VODSEL,orRxEqualization). 32 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 Normal Step 1: SER in BIST BIST Wait Step 2: Wait, DES in BIST BIST start Step 3: DES in Normal Mode - check PASS BIST stop Step 4: SER in Normal Figure28. BISTModeFlowDiagram 8.3.3.2 BERCalculations ItispossibletocalculatetheapproximateBitErrorRate(BER).Thefollowingisrequired: • ClockFrequency(MHz) • BISTDuration(seconds) • BISTtestResult(PASS) The BER is less than or equal to one over the product of 24 times the CLK rate times the test duration. If we assumea50MHzclock,a10minute(600second)test,andaPASS,theBERTis ≤ 1.39X10E-12 The BIST mode runs a check on the data payload bits. The LOCK Pin also provides a link status. It the recovery of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK Pin will switch Low. The combination of the LOCK and At-Speed BIST PASS Pin provides a powerful tool for system evaluation and performancemonitoring. BISTEN S (SER) E R BISTEN (DES) D E S O CLKOUT u (RFB = L) tpu DO[23:0] ts CO1,CO2,CO3 C a s DATA e (internal) 1 - P PASS Prior Result PASS as s X = bit error(s) C DATA X X X as (internal) e 2 PASS Prior Result FAIL - F a il BIST Normal PRBS BIST Test Result Normal BIST Duration Held Figure29. BISTWaveforms Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com 8.4 Device Functional Modes 8.4.1 DataTransfer The DS92LV2411 / DS92LV2412 chipset will transmit and receive a pixel of data in the following format: C1 and C0 represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. The remaining26bitspacescontainthescrambled,encodedandDC-Balancedserialdata. 8.4.2 SerializerandDeserializerOperatingModesandReverseCompatibility(Config[1:0]) TheDS92LV2411/DS92LV2412chipsetiscompatiblewithothersingleseriallaneChannelLinkIIorFPD-LinkII devices. Configuration modes are provided for reverse compatibility with the DS90C241 / DS90C124 and also the DS90UR241 / DS90UR124 by setting the respective mode with the CONFIG[1:0] Pins on the Ser or Des as shown in Table and Table. This selection also determines whether the Control Signal Filter feature is enabled or disabledintheNormalmode.TheseconfigurationmodesareselectablethecontrolPinsonly. Table9. DS92LV2411SerializerModes CONFIG1 CONFIG0 MODE DESDEVICE NormalMode,ControlSignalFilterdisabled DS92LV2412,DS92LV2412,DS92LV0422, L L DS92LV0412 NormalMode,ControlSignalFilterenabled DS92LV2412,DS92LV2412,DS92LV0422, L H DS92LV0412 H L ReverseCompatibilityMode DS90UR124,DS99R124 H H ReverseCompatibilityMode DS90C124 Table10.DS92LV2412SerializerModes CONFIG1 CONFIG0 MODE SERDEVICE NormalMode,ControlSignalFilterdisabled DS92LV2411,DS92LV2411,DS92LV0421, L L DS92LV0411 NormalMode,ControlSignalFilterenabled DS92LV2411,DS92LV2411,DS92LV0421, L H DS92LV0411 H L ReverseCompatibilityMode DS90UR241 H H ReverseCompatibilityMode DS90C241 8.4.3 VideoControlSignalFilter —SerializerandDeserializer WhenoperatingthedevicesinNormalMode,theControlSignalshavethefollowingrestrictions: • Normal Mode with Control Signal Filter Enabled: Control Signal 1 and Control Signal 2 — Only 2 transitions per130clockcyclesaretransmitted,thetransitionpulsemustbe3parallelclocksorlonger. • Normal Mode with Control Signal Filter Disabled: Control Signal 1 and Control Signal 2 — Only 2 transitions per130clockcyclesaretransmitted,norestrictiononminimumtransitionpulse. • Control Signal 3 — Only 1 transition per 130 clock cycles is transmitted , minimum pulse width is 130 clock cycles. ControlSignalsaredefinedaslowfrequencysignalswithlimitedtransition.Glitchesofacontrolsignalcancause a visual error in display applications. This feature allows for the chipset to validate and filter out any high frequencynoiseonthecontrolsignals.SeeFigure. 8.5 Programming 8.5.1 OptionalSerialBusControl The Ser and Des may also be configured by the use of a serial control bus that is I2C protocol compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap Pins. A write of 01'h to reg_0x00'h will enable/allow configuration by registers; this will override the control/strap Pins. Multiple devices maysharetheserialcontrolbussincemultipleaddressesaresupported.SeeFigure30. 34 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 Programming (continued) The serial bus is comprised of three Pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pull up resistor to V . For most DDIO applications a 4.7 k pull up resistor to V may be used. The resistor value may be adjusted for capacitive DDIO loadinganddataraterequirements.ThesignalsareeitherpulledHigh,ordrivenLow. 1.8V VDDIO 10 k ID[X] 4.7k 4.7k SER RID HOST or SCL SCL DES SDA SDA To other Devices Figure30. SerialControlBusConnection The third Pin is the ID[X] Pin. This Pin sets one of four possible device addresses. As shown in Figure 30 , Table11andTable12differentResistorvaluescouldbeusedtosetdifferentSMBUSaddresses. The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SDA transitions Low while SCL is High. A STOP occurs when SDA transition High while SCL is also HIGH. See Figure31 SDA SCL S P STARTcondition, or STOPcondition STARTrepeat condition Figure31. StartandStopConditions To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus beginswitheitheraStartconditionoraRepeatedStartcondition.AllcommunicationonthebusendswithaStop condition.AREADisshowninFigure32andaWRITEisshowninFigure33. IftheSerialBusisnotrequired,thethreePinsmaybeleftopen(NC). Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com Programming (continued) Table11. Id[X]ResistorValue –DS92LV2411Serializer RESISTOR ADDRESS ADDRESS RIDkΩ 7'b 8'b 0APPENDED (WRITE) 0.47 7b'1101001(h'69) 8b'11010010(h'D2) 2.7 7b'1101010(h'6A) 8b'11010100(h'D4) 8.2 7b'1101011(h'6B) 8b'11010110(h'D6) Open 7b'1101110(h'6E) 8b'11011100(h'DC) Table12. Id[X]ResistorValue –DS92LV2412Deserializer RESISTOR ADDRESS ADDRESS RIDkΩ 7'b 8'b 0APPENDED (WRITE) 0.47 7b'1110001(h'71) 8b'11100010(h'E2) 2.7 7b'1110010(h'72) 8b'11100100(h'E4) 8.2 7b'1110011(h'73) 8b'11100110(h'E6) Open 7b'1110110(h'76) 8b'11101100(h'EC) Slave Address Register Address Slave Address Data S A2 A1 A0 0 ack ack S A2 A1 A0 1 ack ack P Figure32. SerialControlBus—Read Slave Address Register Address Data S A2 A1 A0 0 ack ack ack P Figure33. SerialControlBus—Write 36 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 8.6 Register Maps Table13.Serializer—SerialBusControlRegisters ADD ADD REGISTER Bit(s) R/W DEFAULT FUNCTION DESCRIPTION (dec) (hex) NAME (bin) 0 0 SerConfig1 7 R/W 0 Reserved Reserved 6 R/W 0 Reserved Reserved 5 R/W 0 VODSEL 0:Low 1:High 4 R/W 0 RFB 0:DatalatchedonFallingedgeofCLKIN 1:DatalatchedonRisingedgeofCLKIN 3:2 R/W 00 CONFIG 00:ControlSignalFilterDisabled 01:ControlSignalFilterEnabled 10:Reserved 11:Reserved 1 R/W 0 SLEEP Note–notthesamefunctionasPowerDown (PDB) 0:normalmode 1:SleepMode–Registersettingsretained. 0 R/W 0 REG 0:ConfigurationssetfromcontrolPins 1:Configurationsetfromregisters(exceptI2C_ID) 1 1 DeviceID 7 R/W 0 REGID 0:AddressfromID[X]Pin 1:AddressfromRegister 6:0 R/W 1101000 ID[X] SerialBusDeviceID,FourIDsare: 7b'1101001(h'69) 7b'1101010(h'6A) 7b'1101011(h'6B) 7b'1101110(h'6E) AllotheraddressesareReserved. 2 2 De-Emphasis 7:5 R/W 000 De-ESetting 000:setbyexternalResistor Control 001:-1dB 010:-2dB 011:-3.3dB 100:-5dB 101:-6.7dB 110:-9dB 111:-12dB 4 R/W 0 De-EEN 0:De-EmphasisEnabled 1:De-EmphasisDisabled 3:0 R/W 000 Reserved Reserved Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com Table14.Deserializer —SerialBusControlRegisters ADD ADD REGISTER Bit(s) R/W DEFAULT FUNCTION DESCRIPTION (dec) (hex) NAME (bin) 0 0 DesConfig1 7 R/W 0 LF_MODE 0:20to50MHzSSCGOperation 1:5to20MHzSSCGOperation 6 R/W 0 OS_CLKOUT 0:NormalCLKOUTSlewRate 1:IncreasedCLKOUTSlewRate 5 R/W 0 OS_DATA 0:NormalDATASlewRate 1:IncreasedDATASlewRate 4 R/W 0 RFB 0:DatastrobedonFallingedgeofCLKOUT 1:DatastrobedonRisingedgeofCLKOUT 3:2 R/W 00 CONFIG 00:NormalMode,ControlSignalFilterDisabled 01:NormalMode,ControlSignalFilterEnabled 10:Reserved 11:Reserved 1 R/W 0 SLEEP Note–notthesamefunctionasPowerDown(PDB) 0:NormalMode 1:SleepMode–Registersettingsretained. 0 R/W 0 REGControl 0:ConfigurationssetfromcontrolPins/STRAP Pins 1:Configurationssetfromregisters(exceptI2C_ID) 1 1 SlaveID 7 R/W 0 0:AddressfromID[X]Pin 1:AddressfromRegister 6:0 R/W 1110000 ID[X] SerialBusDeviceID,FourIDsare: 7b'1110001(h'71) 7b'1110010(h'72) 7b'1110011(h'73) 7b'1110110(h'76) AllotheraddressesareReserved. 2 2 DesFeatures1 7 R/W 0 OP_LOW 0:SetoutputsstateLOW(exceptLOCK) 1:ReleaseoutputLOWstate,outputstoggling normally Note:ThisregisteronlyworksduringLOCK=1 6 R/W 0 OSS_SEL OutputSleepStateSelect 0:CLKOUT,DO[23:0],CO1,CO2,CO3=L,LOCK =Normal,PASS=H 1:CLKOUT,DO[23:0],CO1,CO2,CO3=Tri-State, LOCK=Normal,PASS=H 5:4 R/W 00 Reserved Reserved 3 R/W 0 OP_LOWStrap 0:StrapwilldeterminewhetherOP_LOWfeatureis Bypass ONorOFF 1:TurnsOFFOP_LOWfeature 2:0 R/W 00 OSC_SEL 000:disable 001:50MHz±40% 010:25MHz±40% 011:16.7MHz±40% 100:12.5MHz±40% 101:10MHz±40% 110:8.3MHz±40% 111:6.3MHz±40% 38 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 Table14.Deserializer —SerialBusControlRegisters(continued) ADD ADD REGISTER Bit(s) R/W DEFAULT FUNCTION DESCRIPTION (dec) (hex) NAME (bin) 3 3 DesFeatures2 7:5 R/W 000 EQGain 000:~1.625dB 001:~3.25dB 010:~4.87dB 011:~6.5dB 100:~8.125dB 101:~9.75dB 110:~11.375dB 111:~13dB 4 R/W 0 EQEnable 0:EQ=disable 1:EQ=enable 3:0 R/W 0000 SSC IFLF_MODE=0,then: 000:SSCGdisable 0001:fdev=±0.5%,fmod=CLK/2168 0010:fdev=±1.0%,fmod=CLK/2168 0011:fdev=±1.5%,fmod=CLK/2168 0100:fdev=±2.0%,fmod=CLK/2168 0101:fdev=±0.5%,fmod=CLK/1300 0110:fdev=±1.0%,fmod=CLK/1300 0111:fdev=±1.5%,fmod=CLK/1300 1000:fdev=±2.0%,fmod=CLK/1300 1001:fdev=±0.5%,fmod=CLK/868 1010:fdev=±1.0%,fmod=CLK/868 1011:fdev=±1.5%,fmod=CLK/868 1100:fdev=±2.0%,fmod=CLK/868 1101:fdev=±0.5%,fmod=CLK/650 1110:fdev=±1.0%,fmod=CLK/650 1111:fdev=±1.5%,fmod=CLK/650 IFLF_MODE=1,then: 000:SSCGdisable 0001:fdev=±0.5%,fmod=CLK/620 0010:fdev=±1.0%,fmod=CLK/620 0011:fdev=±1.5%,fmod=CLK/620 0100:fdev=±2.0%,fmod=CLK/620 0101:fdev=±0.5%,fmod=CLK/370 0110:fdev=±1.0%,fmod=CLK/370 0111:fdev=±1.5%,fmod=CLK/370 1000:fdev=±2.0%,fmod=CLK/370 1001:fdev=±0.5%,fmod=CLK/258 1010:fdev=±1.0%,fmod=CLK/258 1011:fdev=±1.5%,fmod=CLK/258 1100:fdev=±2.0%,fmod=CLK/258 1101:fdev=±0.5%,fmod=CLK/192 1110:fdev=±1.0%,fmod=CLK/192 1111:fdev=±1.5%,fmod=CLK/192 4 4 ROUTConfig 7 R/W 0 RepeaterEnable 0:OutputROUT+/-=disable 1:OutputROUT+/-=enable 6:0 R/W 0000000 Reserved Reserved Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com 9 Applications and Implementation 9.1 Application Information The DS92LV2411/DS92LV2412 chipset is intended for interface between a host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888). In a RGB888 application, 24 color bits (D[23:0), Pixel Clock (CLKIN)andthreecontrolbits(C1,C2,C3)aresupportedacrosstheseriallinkwithCLKratesfrom5to50MHz. The chipset may also be used in 18-bit color applications. In this application three to six general purpose signals mayalsobesentfromhosttodisplay. The Des is expected to be located close to its target device. The interconnect between the Des and the target device is typically in the 1 to 3 inch separation range. The input capacitance of the target device is expected to be in the 5 to 10 pF range. Care should be taken on the CLK output trace as this signal is edge sensitive and strobes the data. It is also assumed that the fanout of the Des is one. If additional loads need to be driven, a logicbufferormuxdeviceisrecommended. 9.2 Typical Applications VDDIO VDDn VDDn VDDIO (1.8V or 3.3V) 1.8V 1.8V (1.8V or 3.3V) DI[7:0] Channel Link II DO[7:0] Graphic DI[15:8] 1 Pair / AC Coupled DO[15:8] Processor DI[23:16] 0.1 PF 0.1 PF DO[23:16] 24-bit RGB OR CI1 CO1 Display Video CI2 DOUT+ RIN+ CO2 OR Imager CI3 CO3 ASIC/FPGA OR CLKIN DOUT- RIN- CLKOUT ASIC/FPGA 100 ohm STP Cable DS92LV2411 DS92LV2412 LOCK PDB Serializer CMF Deserializer PASS PDB BISTEN RFB BISTEN STRAP pins VODSEL not shown SCL DeEmph SCL Optional SDA Optional SDA ID[x] ID[x] DAP DAP Figure34. TypicalApplicationSchematicforDS92LV2411,DS92LV2412Ser/DesPair 9.2.1 DesignRequirements Forthistypicaldesignapplication,usethefollowingasinputparameters. Table15.DesignParameters DESIGNPARAMETER EXAMPLEVALUE VDDIO 1.8Vor3.3V VDDn 1.8V ACCouplingCapacitorforDOUT±andRIN± 0.1µF CLKFrequency 50MHz 9.2.2 DetailedDesignProcedure 9.2.2.1 TypicalApplicationConnection Figure 35 shows a typical connection diagram of the DS92LV2411 Ser in Pin control mode for a 24-bit application. The CML outputs require 0.1 µF AC coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors are placed near the power supply Pins. At a minimum, four 0.1 µF capacitors and a 4.7 µF capacitor should be used for local device bypassing. System GPO (General Purpose Output) signals control the PDB and BISTEN Pins. In this application the RFB Pin is tied Low to latch data on the falling edge of 40 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 the CLKIN. In this example the cable is long, therefore the VODSEL Pin is tied High and a De-Emphasis value is selected by the resistor R1. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO Pin is connected also to the 1.8V rail. The optional Serial Bus control is not used in this example, thus the SCL, SDA and ID[x] Pins are left open. A delay cap is placed on the PDB signal to delay the enabling of the device until powerisstable. DS92LV2411 (SER) VDDIO 1.8V VDDIO VDDTX C9 C7 FB1 C3 VDDHS C4 FB2 C8 C10 DI0 VDDP DI1 DI2 C11 C5 FB3 DI3 DI4 VDDL DI5 C6 FB4 DI6 DI7 DI8 DI9 DI10 C1 Serial DI11 DOUT+ Channel Link II LVCMOS DDII1123 DOUT- Interface Parallel DI14 C2 Video DI15 Interface DI16 DI17 DI18 DI19 DI20 DI21 DI22 DI23 VDDIO CLKIN VODSEL CI1 De-Emph 1.8V CI2 R1 CI3 LVCMOS Control BISTEN 10k Interface PDB ID[X] C12 SCL RID SDA NOTE: C1-C2 = 0.1 PF CONFIG1 C3-C8 = 0.1 PF CONFIG0 RES2 C9-11 = 4.7 PF RFB RES1 RES0 C12 = >10 PF R1 (cable specific) DAP (GND) RID (see ID[x] Resistor Value Table 12) FB1-FB4: Impedance = 1 k:, low DC resistance (<1:) Figure35. DS92LV2411TypicalConnectionDiagram —PinControl Figure 36 shows a typical connection diagram of the DS92LV2412 Des in Pin/strap control mode for a 24-bit application. The CML inputs utilize 0.1 µF coupling capacitors to the line and the receiver provides internal termination. Bypass capacitors are placed near the power supply Pins. At a minimum, seven 0.1 µF capacitors and two 4.7 µF capacitors should be used for local device bypassing. System GPO (General Purpose Output) signals control the PDB and the BISTEN Pins. In this application the RFB Pin is tied Low to strobe the data on thefallingedgeoftheCLKOUT. Since the device in the Pin/STRAP mode, four 10 kΩ pull up resistors are used on the parallel output bus to select the desired device features. CFEN is set to 1 for Normal Mode with Control Signal Filter enabled, this is accomplished with the STRAP pull-up on DO23. The receiver input equalizer is also enabled and set to provide 7.5 dB of gain, this is accomplished with EQ[3:0] set to 1001'b with STRAP pull ups on DO12 and DO15. To reduceparallelbusEMI,theSSCGfeatureisenabledandsettofmod=CLK/2168and ±1%withSSC[3:0]setto 0010'bandaSTRAPpull-uponDO4.Thedesiredfeaturesaresetwiththeuseofthefourpullupresistors. The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO Pin is connected to the 3.3 V rail. The optional Serial Bus Control is not used in this example, thus the SCL, SDA and ID[x] Pins are left open. AdelaycapisplacedonthePDBsignaltodelaytheenablingofthedeviceuntilpowerisstable. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com DS92LV2412 (DES) 1.8V VDDIO VDDL VDDIO C13 C11 C3 C8 C12 C14 VDDSC VDDIO C4 C9 VDDPR VDDIO C5 C10 VDDR C15 C6 VDDIR VDDIO VDDCMLO EXAMPLE: STRAP C16 C7 Input Pull-Ups (10k) DO0 C1 DO1 Serial DO2 Channel Link II RIN+ DO3 Interface RIN- DO4 C2 CMF DO5 DO6 C17 DO7 DO8 DO9 TP_A ROUT+ DO10 TP_B ROUT- DO11 DO12 LVCMOS Host BISTEN DO13 Parallel Control PDB DO14 Video C18 DO15 Interface DO16 1.8V DO17 DO18 DO19 10k DO20 DO21 ID[X] DO22 RID SCL DO23 SDA CO1 C1 - C2 = 0.1 PF CO2 C3 - C12 = 0.1 PF CO3 NC C13, C16 = 4.7 PF 8 CLKOUT C17 = 4.7 PF C18 = >10 PF RES LOCK RID (see ID[x] Resistor Value Table 13) DAP (GND) PASS FB1-FB4: Impedance = 1 k:, low DC resistance (<1:) Figure36. DS92LV2412TypicalConnectionDiagram —PinControl 9.2.2.2 PowerUpRequirementsandPDBPin TheVDD(V andV )supplyrampshouldbefasterthan1.5mswithamonotonicrise.Ifslowerthen1.5ms DDn DDIO then a capacitor on the PDB Pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. When PDB Pin is pulled to V , it is recommended to use a 10 kΩ pull-up DDIO anda22uFcaptoGNDtodelaythePDBinputsignal. 42 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 9.2.2.3 TransmissionMedia The Ser/Des chip set is intended to be used in a point-to-point configuration, through a PCB trace, through twisted pair cable or through 50Ω coaxial cables. The Ser and Des provide internal terminations providing a clean signaling environment. The interconnect for the differential serial interface should present a differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Shielded or un-shielded cables may be used depending upon the noise environment andapplicationrequirements. For 50Ω coaxial cable serial interfaces, any unused input or output Pin must be terminated with an 0.1 µF AC coupling capacitor and a 50Ω resistor to ground. The PCB traces and serial interconnect should have a single endedimpedanceof50Ω. 9.2.2.4 LiveLinkInsertion The Ser and Des devices support live pluggable applications. The automatic receiver lock to random data “plug and go” hot insertion capability allows the DS92LV2412 to attain lock to the active data stream during a live insertionevent. 9.2.2.5 SerialInterconnectGuidelines SeeAN-1108(SNLA008)andAN-905(SNLA035)forfulldetails. • Use100Ω coupleddifferentialpairs • UsetheS/2S/3Sruleinspacings – S=spacebetweenthepair – 2S=spacebetweenpairs – 3S=spacetoLVCMOSsignal • MinimizethenumberofVias • Usedifferentialconnectorswhenoperatingabove500Mbpslinespeed • Maintainbalanceofthetraces • Minimizeskewwithinthepair • TerminateasclosetotheTXoutputsandRXinputsaspossible Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas Instrumentswebsiteat:http://www.ti.com/ww/en/analog/interface/lvds.shtml 9.2.3 ApplicationCurves CML CML Serializer Data Serializer Data Throughput Throughput (100 mV/DIV) (100 mV/DIV) 50 MHz TX 50 MHz TX Pixel Clock Pixel Clock Input Input (2 V/DIV) (2 V/DIV) Time (4 ns/DIV) Time (4 ns/DIV) Figure37.SerializerOutputwith50MHzTXPixelClock, Figure38.SerializerOutputwith50MHzTXPixelClock, De-emphasisDisabled De-emphasisEnabled Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com 10 Power Supply Recommendations Thedevicesaredesignedtooperatefromaninputvoltagesupplyof1.8V.Somedevicesprovideseparatepower and ground Pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power Pin pairs. In some cases, an externalfiltermaybeusedtoprovidecleanpowertosensitivecircuitssuchasPLLs. 11 Layout 11.1 Layout Guidelines Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwantedstraynoisepickup,feedbackandinterference.Powersystemperformancemaybegreatlyimprovedby using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the tantalumcapacitorsshouldbeatleast5Xthepowersupplyvoltagebeingused. Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply Pin, locate the smaller value closer to the Pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is recommendedtoconnectpowerandgroundPinsdirectlytothepowerandgroundplaneswithbypasscapacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground Pins to an external bypasscapacitorwillincreasetheinductanceofthepath. A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground Pins to the planes, reducing theimpedanceathighfrequency. Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML linestopreventcouplingfromtheLVCMOSlinestotheCMLlines.Closely-coupleddifferentiallinesof100Ohms are typically recommended for differential interconnect. The closely coupled lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiateless. InformationontheWQFNstylepackageisprovidedinTIApplicationNote:AN-1187(SNOA401). 11.2 Layout Example Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of the LLP package is highly recommended to improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow unevenlythroughtheDAP.Stencilparametersforapertureopeningandvialocationsareshownbelow: 44 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 Layout Example (continued) Figure39. NoPullbackLLP,SingleRowReferenceDiagram Table16.NoPullbackLLPStencilApertureSummaryforDS92LV2411andDS92LV2412 Device Pin MKTDwg PCBI/O PCB PCBDAP StencilI/O StencilDAP Numberof GapBetweenDAP Count PadSize Pitch size(mm) Aperture Aperture DAP Aperture(DimA (mm) (mm) (mm) (mm) Aperture mm) Openings 0.25x DS92LV2411 48 SQA48A 0.5 5.1x5.1 0.25x0.7 1.1x1.1 16 0.2 0.6 0.25x DS92LV2412 60 SQA60B 0.5 7.2x7.2 0.25x0.9 1.16x1.16 25 0.3 0.8 Figure40. 48-PinWQFNStencilExampleofViaandOpeningPlacement The following PCB layout examples are derived from the layout design of the DS9LV2411 and DS92LV2412 in the LV24EVK01 Evaluation Module User's Guide (SNLU006). These graphics and additional layout description areusedtodemonstratebothproperroutingandpropersoldertechniqueswhendesigningintheSer/Despair. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 SNLS302E–MAY2010–REVISEDFEBRUARY2015 www.ti.com Figure41. DS92LV2411SerializerExampleLayout Figure42. DS92LV2412DeserializerExampleLayout 46 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:DS92LV2411 DS92LV2412

DS92LV2411,DS92LV2412 www.ti.com SNLS302E–MAY2010–REVISEDFEBRUARY2015 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table17.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY DS92LV2411 Clickhere Clickhere Clickhere Clickhere Clickhere DS92LV2412 Clickhere Clickhere Clickhere Clickhere Clickhere 12.2 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 12.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLinks:DS92LV2411 DS92LV2412

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) DS92LV2411SQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS SN Level-3-260C-168 HR -40 to 85 LV2411SQ & no Sb/Br) DS92LV2411SQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS SN Level-3-260C-168 HR -40 to 85 LV2411SQ & no Sb/Br) DS92LV2411SQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS SN Level-3-260C-168 HR -40 to 85 LV2411SQ & no Sb/Br) DS92LV2412SQ/NOPB ACTIVE WQFN NKB 60 1000 Green (RoHS SN Level-3-260C-168 HR -40 to 85 LV2412SQ & no Sb/Br) DS92LV2412SQE/NOPB ACTIVE WQFN NKB 60 250 Green (RoHS SN Level-3-260C-168 HR -40 to 85 LV2412SQ & no Sb/Br) DS92LV2412SQX/NOPB ACTIVE WQFN NKB 60 2000 Green (RoHS SN Level-3-260C-168 HR -40 to 85 LV2412SQ & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) DS92LV2411SQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 DS92LV2411SQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 DS92LV2411SQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 DS92LV2412SQ/NOPB WQFN NKB 60 1000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 DS92LV2412SQE/NOPB WQFN NKB 60 250 178.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 DS92LV2412SQX/NOPB WQFN NKB 60 2000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) DS92LV2411SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS92LV2411SQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0 DS92LV2411SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 DS92LV2412SQ/NOPB WQFN NKB 60 1000 367.0 367.0 38.0 DS92LV2412SQE/NOPB WQFN NKB 60 250 210.0 185.0 35.0 DS92LV2412SQX/NOPB WQFN NKB 60 2000 367.0 367.0 38.0 PackMaterials-Page2

PACKAGE OUTLINE RHS0048A WQFN - 0.8 mm max height SCALE 1.800 PLASTIC QUAD FLATPACK - NO LEAD A 7.15 B 6.85 PIN 1 INDEX AREA 0.5 0.3 7.15 6.85 0.30 0.18 DETAIL OPTIONAL TERMINAL TYPICAL 0.8 0.7 C DIM A SEATING PLANE OPT 1 OPT 2 0.05 0.08 C (0.1) (0.2) 0.00 2X 5.5 (0.2) 5.1 0.1 (A) TYP 44X 0.5 13 24 12 25 EXPOSED THERMAL PAD 2X 49 SYMM 5.5 SEE TERMINAL DETAIL 1 36 0.30 48X 48 37 0.18 PIN 1 ID SYMM 0.5 0.1 C A B (OPTIONAL) 48X 0.3 0.05 4214990/B 04/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RHS0048A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 5.1) SYMM 48 37 48X (0.6) 1 36 48X (0.25) (1.05) TYP 44X (0.5) (1.25) TYP 49 SYMM (6.8) (R0.05) TYP ( 0.2) TYP VIA 12 25 13 24 (1.25) (1.05) TYP TYP (6.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL EDGE OPENING EXPOSED METAL SOLDER MASK EXPOSED METAL UNDER OPENING METAL SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214990/B 04/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RHS0048A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD (0.625) TYP (1.25) TYP 48 37 48X (0.6) 1 49 36 48X (0.25) 44X (0.5) (1.25) TYP (0.625) TYP SYMM (6.8) (R0.05) TYP METAL TYP 12 25 13 24 16X SYMM ( 1.05) (6.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:15X 4214990/B 04/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

PACKAGE OUTLINE NKB0060B VQFN - 0.8 mm max height SCALE 1.500 PLASTIC QUAD FLATPACK - NO LEAD 9.1 B A 8.9 PIN 1 INDEX AREA 9.1 8.9 0.8 0.7 C SEATING PLANE 0.05 0.08 C 0.00 2X 7 6.3 0.1 EXPOSED THERMAL PAD SYMM (0.1) TYP 16 30 15 31 SYMM 61 2X 7 1 45 0.3 60X 56X 0.5 0.2 60 46 0.1 C A B PIN 1 ID 60X 0.7 0.05 0.5 4214995/A 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT NKB0060B VQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 6.3) SYMM SEE SOLDER MASK 60X (0.8) 60 46 DETAIL 60X (0.25) 1 45 56X (0.5) (1.1) TYP (1.2) TYP (R0.05) TYP ( 0.2) TYP 61 SYMM VIA (0.6) TYP (8.6) 15 31 16 30 (0.6) TYP (1.2) TYP (1.1) TYP (8.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 8X 0.07 MIN 0.07 MAX ALL AROUND ALL AROUND METAL UNDER METAL EDGE SOLDER MASK EXPOSED METAL SOLDER MASK EXPOSED SOLDER MASK OPENING METAL OPENING NON SOLDER MASK DEFINED SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS 4214995/A 03/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN NKB0060B VQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD 25X ( 1) (1.2) TYP 60X (0.8) 60 46 60X (0.25) 1 45 56X (0.5) (R0.05) TYP (1.2) TYP 61 SYMM (8.6) 15 31 16 30 SYMM (8.6) SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 8X EXPOSED PAD 61 63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE 4214995/A 03/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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