Product Sample & Technical Tools & Support & Folder Buy Documents Software Community DS90LV048A SNLS045C–JULY1999–REVISEDJULY2016 DS90LV048A 3-V LVDS Quad CMOS Differential Line Receiver 1 Features 3 Description • >400-Mbps(200-MHz)SwitchingRates The DS90LV048A device is a quad CMOS flow- 1 through differential line receiver designed for • Flow-ThroughPinoutSimplifiesPCBLayout applications requiring ultra-low power dissipation and • 150-psChannel-to-ChannelSkew(Typical) high data rates. The device is designed to support • 100-psDifferentialSkew(Typical) data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) • 2.7-nsMaximumPropagationDelay technology. • 3.3-VPowerSupplyDesign The DS90LV048A accepts low voltage (350 mV • HighImpedanceLVDSInputsonPowerDown typical) differential input signals and translates them • LowPowerDesign(40mWat3.3-VStatic) to 3-V CMOS output levels. The receiver supports a • InteroperableWithExisting5-VLVDSDrivers TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, • AcceptsSmallSwing(350mVTypical)Differential and terminated (100-Ω) input fail-safe. The receiver SignalLevels output is HIGH for all fail-safe conditions. The • SupportsInputFailsafe DS90LV048A has a flow-through pinout for easy PCB – Open,Short,andTerminated layout. • 0Vto−100mVThresholdRegion The EN and EN* inputs are ANDed together and • ConformstoANSI/TIA/EIA-644Standard control the TRI-STATE outputs. The enables are common to all four receivers. The DS90LV048A and • OperatingTemperatureRange:–40°Cto+85°C companion LVDS line driver (for example, • AvailableinSOICandTSSOPPackage DS90LV047A) provide a new alternative to high- power PECL/ECL devices for high-speed point-to- 2 Applications pointinterfaceapplications. • MultifunctionPrinters DeviceInformation(1) • LVDS-LVCMOSTranslation PARTNUMBER PACKAGE BODYSIZE(NOM) SOIC(16) 9.90mm×3.91mm DS90LV048A TSSOP(16) 5.00mm×4.40mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. FunctionalDiagram 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

DS90LV048A SNLS045C–JULY1999–REVISEDJULY2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8.3 FeatureDescription.................................................11 2 Applications........................................................... 1 8.4 DeviceFunctionalModes........................................11 3 Description............................................................. 1 9 ApplicationandImplementation........................ 12 4 RevisionHistory..................................................... 2 9.1 ApplicationInformation............................................12 9.2 TypicalApplication .................................................12 5 PinConfigurationandFunctions......................... 3 10 PowerSupplyRecommendations..................... 13 6 Specifications......................................................... 3 11 Layout................................................................... 13 6.1 AbsoluteMaximumRatings......................................3 6.2 ESDRatings..............................................................4 11.1 LayoutGuidelines.................................................13 6.3 RecommendedOperatingConditions.......................4 11.2 LayoutExample....................................................14 6.4 ThermalInformation..................................................4 12 DeviceandDocumentationSupport................. 15 6.5 ElectricalCharacteristics...........................................4 12.1 DocumentationSupport........................................15 6.6 SwitchingCharacteristics..........................................5 12.2 ReceivingNotificationofDocumentationUpdates15 6.7 TypicalCharacteristics..............................................6 12.3 CommunityResources..........................................15 7 ParameterMeasurementInformation..................9 12.4 Trademarks...........................................................15 12.5 ElectrostaticDischargeCaution............................15 8 DetailedDescription............................................ 10 12.6 Glossary................................................................15 8.1 Overview.................................................................10 13 Mechanical,Packaging,andOrderable 8.2 FunctionalBlockDiagram.......................................10 Information........................................................... 15 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(April2013)toRevisionC Page • AddedESDRatingstable,ThermalInformationtable,FeatureDescriptionsection,DeviceFunctionalModes, ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Deviceand DocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection....................................... 1 ChangesfromRevisionA(April2013)toRevisionB Page • ChangedlayoutofNationalSemiconductorDataSheettoTIformat.................................................................................... 8 2 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV048A

DS90LV048A www.ti.com SNLS045C–JULY1999–REVISEDJULY2016 5 Pin Configuration and Functions DorPWPackage 16-PinSOICorTSSOP TopView PinFunctions PIN I/O DESCRIPTION NAME NO. Receiverenablepin:WhenENislow,thereceiverisdisabled.WhenENishighandEN*islow EN 16 I oropen,thereceiverisenabled.IfbothENandEN*areopencircuit,thenthereceiveris disabled. Receiverenablepin:WhenEN*ishigh,thereceiverisdisabled.WhenEN*isloworopenand EN* 9 I ENishigh,thereceiverisenabled.IfbothENandEN*areopencircuit,thenthereceiveris disabled. GND 12 — Groundpin R 2,3,6,7 I Noninvertingreceiverinputpin IN+ R 1,4,5,8 I Invertingreceiverinputpin IN− 10,11,14, Receiveroutputpin R O OUT 15 V 13 — Powersupplypin,+3.3V±0.3V CC 6 Specifications 6.1 Absolute Maximum Ratings See (1)(2) MIN MAX UNIT Supplyvoltage(V ) –0.3 4 V CC Inputvoltage(R ,R ) –0.3 3.6 V IN+ IN− Enableinputvoltage(EN,EN*) –0.3 V +0.3 V CC Outputvoltage(R ) –0.3 V +0.3 V OUT CC D0016Apackage 1025 mW PW0016Apackage 866 Maximumpackagepowerdissipation DerateD0016A at+25°C package above+25°C 8.2 mW/°C DeratePW0016A above+25°C 6.9 package Leadtemperaturesoldering (4s) 260 °C Maximumjunctiontemperature 150 °C Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS90LV048A

DS90LV048A SNLS045C–JULY1999–REVISEDJULY2016 www.ti.com 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM) ±10000 V Electrostaticdischarge(1) V (ESD) Machinemodel ±1200 (1) ESDRating: HBM(1.5kΩ,100pF) EIAJ(0Ω,200pF) 6.3 Recommended Operating Conditions MIN NOM MAX UNIT Supplyvoltage,V 3 3.3 3.6 V CC Receiverinputvoltage GND 3 V Operatingfreeairtemperature,T −40 25 85 °C A 6.4 Thermal Information DS90LV048A THERMALMETRIC(1) PW(TSSOP) UNIT 16PINS R Junction-to-ambientthermalresistance 110.2 °C/W θJA R Junction-to-case(top)thermalresistance 47 °C/W θJC(top) R Junction-to-boardthermalresistance 54.7 °C/W θJB ψ Junction-to-topcharacterizationparameter 6.1 °C/W JT ψ Junction-to-boardcharacterizationparameter 54.2 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6.5 Electrical Characteristics OverSupplyVoltageandOperatingTemperatureranges,unlessotherwisespecified.(1)(2) PARAMETER TESTCONDITIONS PIN MIN TYP MAX UNIT V Differentialinputhighthreshold −35 0 mV TH V =+1.2V,0.05V,2.95V(3) CM V Differentialinputlowthreshold −100 −35 mV TL VCMR Common-modevoltagerange VID=200mVpeaktopeak?(4) R , 0.1 2.3 V IN+ VIN=+2.8V RIN− −10 ±5 10 V =3.6Vor0V CC I Inputcurrent V =0V −10 ±1 10 μA IN IN V =+3.6V V =0V –20 ±1 20 IN CC I =−0.4mA,V =+200mV 2.7 3.3 OH ID V Outputhighvoltage I =−0.4mA,inputterminated 2.7 3.3 V OH OH I =−0.4mA,inputshorted 2.7 3.3 OH R OUT V Outputlowvoltage I =2mA,V =−200mV 0.05 0.25 V OL OL ID I Outputshort-circuitcurrent Enabled,V =0V(5) −15 −47 −100 mA OS OUT I OutputTRI-STATEcurrent Disabled,V =0VorV −10 ±1 10 μA OZ OUT CC (1) Currentintodevicepinsisdefinedaspositive.Currentoutofdevicepinsisdefinedasnegative.Allvoltagesarereferencedtoground unlessotherwisespecified. (2) Alltypicalsaregivenfor:V =3.3V,T =25°C. CC A (3) V isalwayshigherthanR andR voltage.R andR areallowedtohaveavoltagerange−0.2VtoV −VID/2.However,to CC IN+ IN− IN− IN+ CC becompliantwithACspecifications,thecommonvoltagerangeis0.1Vto2.3V. (4) TheVCMRrangeisreducedforlargerVID.Example:ifVID=400mV,theVCMRis0.2Vto2.2V.Thefail-safeconditionwithinputs shortedisnotsupportedoverthecommon-moderangeof0Vto2.4V,butissupportedonlywithinputsshortedandnoexternal common-modevoltageapplied.AVIDuptoV –0VmaybeappliedtotheR /R inputswiththeCommon-Modevoltagesetto CC IN+ IN− V /2.PropagationdelayandDifferentialPulseskewdecreasewhenVIDisincreasedfrom200mVto400mV.Skewspecifications CC applyfor200mV≤VID≤800mVoverthecommon-moderange. (5) Outputshort-circuitcurrent(I )isspecifiedasmagnitudeonly;minussignindicatesdirectiononly.Onlyoneoutputshouldbeshorted OS atatime;donotexceedmaximumjunctiontemperaturespecification. 4 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV048A

DS90LV048A www.ti.com SNLS045C–JULY1999–REVISEDJULY2016 Electrical Characteristics (continued) OverSupplyVoltageandOperatingTemperatureranges,unlessotherwisespecified.(1)(2) PARAMETER TESTCONDITIONS PIN MIN TYP MAX UNIT V Inputhighvoltage 2 V V IH CC VIL Inputlowvoltage EN, GND 0.8 V I Inputcurrent V =0VorV ,otherInput=V orGND EN* −10 ±5 10 μA I IN CC CC V Inputclampvoltage I =−18mA −1.5 −0.8 V CL CL Noloadsupplycurrent I EN=V ,inputsopen 9 15 mA CC receiversenabled CC V CC Noloadsupplycurrent I EN=GND,inputsopen 1 5 mA CCZ receiversdisabled 6.6 Switching Characteristics OverSupplyVoltageandOperatingTemperatureranges,unlessotherwisespecified.(1)(2)(3)(4) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t Differentialpropagationdelayhightolow 1.2 2 2.7 ns PHLD t Differentialpropagationdelaylowtohigh 1.2 1.9 2.7 ns PLHD t Differentialpulseskew|t −t |(5) 0 0.1 0.4 ns SKD1 PHLD PLHD Differentialchannel-to-channelskew;same C =15pF tSKD2 device(3) VL =200mV 0 0.15 0.5 ns ID t Differentialpart-to-partskew(4) (Figure15andFigure16) 1 ns SKD3 t Differentialpart-to-partskew(6) 1.5 ns SKD4 t Risetime 0.5 1 ns TLH t Falltime 0.35 1 ns THL t DisabletimehightoZ 8 14 ns PHZ R =2kΩ t DisabletimelowtoZ L 8 14 ns PLZ C =15pF L t EnabletimeZtohigh 9 14 ns PZH (Figure17andFigure18) t EnabletimeZtolow 9 14 ns PZL f Maximumoperatingfrequency(7) Allchannelsswitching 200 250 MHz MAX (1) Alltypicalsaregivenfor:V =3.3V,T =25°C. CC A (2) Generatorwaveformforalltestsunlessotherwisespecified:f=1MHz,Z =50Ω,t andt (0%to100%)≤3nsforR . O r f IN (3) t ,channel-to-channelskewisdefinedasthedifferencebetweenthepropagationdelayofonechannelandthatoftheothersonthe SKD2 samechipwithanyeventontheinputs. (4) t ,part-to-partskew,isthedifferentialchannel-to-channelskewofanyeventbetweendevices.Thisspecificationappliestodevices SKD3 atthesameV ,andwithin5°Cofeachotherwithintheoperatingtemperaturerange. CC (5) t isthemagnitudedifferenceindifferentialpropagationdelaytimebetweenthepositivegoingedgeandthenegativegoingedgeof SKD1 thesamechannel (6) t ,part-to-partskew,isthedifferentialchannel-to-channelskewofanyeventbetweendevices.Thisspecificationappliestodevices SKD4 overrecommendedoperatingtemperatureandvoltageranges,andacrossprocessdistribution.t isdefinedas|Max−Min|differential SKD4 propagationdelay. (7) f generatorinputconditions:t =t <1ns(0%to100%),50%dutycycle,differential(1.05-Vto1.35-Vpeaktopeak).Outputcriteria: MAX r f 60/40%dutycycle,V (maximum0.4V),V (minimum2.7V),Load=15pF(strayplusprobes). OL OH Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS90LV048A

DS90LV048A SNLS045C–JULY1999–REVISEDJULY2016 www.ti.com 6.7 Typical Characteristics Figure1.OutputHighVoltagevsPowerSupplyVoltage Figure2.OutputLowVoltagevsPowerSupplyVoltage Figure3.OutputShort-CircuitCurrentvsPowerSupply Figure4.OutputTRI-STATECurrentvsPowerSupply Voltage Voltage Figure5.DifferentialTransitionVoltagevsPowerSupply Figure6.PowerSupplyCurrentvsAmbientTemperature Voltage 6 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV048A

DS90LV048A www.ti.com SNLS045C–JULY1999–REVISEDJULY2016 Typical Characteristics (continued) Figure7.DifferentialPropagationDelayvsPowerSupply Figure8.DifferentialPropagationDelayvsAmbient Voltage Temperature Figure9.DifferentialPropagationDelayvsDifferentialInput Figure10.DifferentialPropagationDelayvsCommon-Mode Voltage Voltage Figure11.DifferentialSkewvsPowerSupplyVoltage Figure12.DifferentialSkewvsAmbientTemperature Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS90LV048A

DS90LV048A SNLS045C–JULY1999–REVISEDJULY2016 www.ti.com Typical Characteristics (continued) Figure13.TransitionTimevsPowerSupplyVoltage Figure14.TransitionTimevsAmbientTemperature 8 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV048A

DS90LV048A www.ti.com SNLS045C–JULY1999–REVISEDJULY2016 7 Parameter Measurement Information Figure15. ReceiverPropagationDelayandTransitionTimeTestCircuit Figure16. ReceiverPropagationDelayandTransitionTimeWaveforms C includesloadandtestjigcapacitance. L S =V fort andt measurements. 1 CC PZL PLZ S =GNDfort andt measurements. 1 PZH PHZ Figure17. ReceiverTRI-STATEDelayTestCircuit Figure18. ReceiverTRI-STATEDelayWaveforms Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS90LV048A

DS90LV048A SNLS045C–JULY1999–REVISEDJULY2016 www.ti.com 8 Detailed Description 8.1 Overview LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as shown in Figure 19. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the range of 100 Ω. A termination resistor of 100 Ω (selected to match the media) is located as close to the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects ofamid-streamconnector(s),cablestub(s),andotherimpedancediscontinuitiesaswellasgroundshifting,noise marginlimits,andtotalterminationloadingmustbeconsidered. The DS90LV048A differential line receiver is capable of detecting signals as low as 100 mV, over a ±1-V common-moderangecenteredaround+1.2V.Thisisrelatedtothedriveroffsetvoltagewhichistypically+1.2V. The driven signal is centered around this voltage and may shift ±1 V around this center point. The ±1-V shifting may be the result of a ground potential difference between the ground reference of the driver and the ground reference of the receiver, the common-mode effects of coupled noise, or a combination of the two. The AC parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0 V to +2.4 V (measured from each pin to ground). The device operates for receiver input voltages up to V , but CC exceedingV turnsontheESDprotectioncircuitry,whichclampsthebusvoltages. CC The DS90LV048A has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise isolationisachievedwiththeLVDSsignalsononesideofthedeviceandtheTTLsignalsontheotherside. 8.2 Functional Block Diagram 10 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV048A

DS90LV048A www.ti.com SNLS045C–JULY1999–REVISEDJULY2016 8.3 Feature Description 8.3.1 Fail-SafeFeature The LVDS receiver is a high-gain, high-speed device that amplifies a small differential signal (20 mV) to CMOS logiclevels.Duetothehighgainandtightthresholdofthereceiver,takecaretopreventnoisefromappearingas avalidsignal. The internal fail-safe circuitry of the receiver is designed to source or sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins. The DS90LV048A is a quad receiver device, and if an application requires only 1, 2, or 3 receivers, the unused channel(s) inputs must be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pullup and pulldown resistors to set the output toaHIGHstate.ThisinternalcircuitryensuresaHIGH,stableoutputstateforopeninputs. 2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or power-off condition, the receiver output is again in a HIGH state, even with the end of cable 100-Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10 mV of differential noise, the receiver may see the noise as a valid signal and switch. To ensure that any noise is seen as common-mode and not differential, a balanced interconnectshouldbeused.Twistedpaircableoffersbetterbalancethanflatribboncable. 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0-V differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported acrossthecommon-moderangeofthedevice(GNDto2.4V).Itisonlysupportedwithinputsshortedandno externalcommon-modevoltageapplied. External lower value pullup and pulldown resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pullup and pulldown resistors must be in the 5-kΩ to 15-kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point must be set to approximately1.2V(lessthan1.75V)tobecompatiblewiththeinternalcircuitry. Additional information on fail-safe biasing of LVDS devices may be found in AN-1194 Failsafe Biasing of LVDS Interfaces (SNLA051). 8.4 Device Functional Modes Table1liststhefunctionalmodesoftheDS90LV048A. Table1.TruthTable ENABLES INPUT OUTPUT EN EN* R −R R IN+ IN− OUT V ≥0V H ID V ≤−0.1V L ID H LorOpen FullFail-safe OPEN/SHORTor H Terminated AllothercombinationsofENABLEinputs X Z Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS90LV048A

DS90LV048A SNLS045C–JULY1999–REVISEDJULY2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The DS90LV048A has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise isolationisachievedwiththeLVDSsignalsononesideofthedeviceandtheTTLsignalsontheotherside. 9.2 Typical Application Figure19. BalancedSystemPoint-to-PointApplication 9.2.1 DesignRequirements When using LVDS devices, it is important to remember to specify controlled impedance PCB traces, cable assemblies, and connectors. All components of the transmission media must have a matched differential impedanceofabout100Ω.Theymustnotintroducemajorimpedancediscontinuities. Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the LVDSreceiver. For cable distances < 0.5 M, most cables can be made to work effectively. For distances 0.5 M ≤ d ≤ 10 M, CAT5(Category5)twistedpaircableworkswell,isreadilyavailable,andrelativelyinexpensive. 9.2.2 DetailedDesignProcedure 9.2.2.1 ProbingLVDSTransmissionLines Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz) scope.Improperprobinggivesdeceivingresults. 9.2.2.2 Threshold The LVDS Standard (ANSI/TIA/EIA-644) specifies a maximum threshold of ±100 mV for the LVDS receiver. The DS90LV048A supports an enhanced threshold region of −100 mV to 0 V. This is useful for fail-safe biasing. The threshold region is shown in the Voltage Transfer Curve (VTC) in Figure 20. The typical DS90LV048A LVDS receiverswitchesatabout−35mV. NOTE With V = 0 V, the output is in a HIGH state. With an external fail-safe bias of +25 mV ID applied, the typical differential noise margin is now the difference from the switch point to thebiaspoint. In the following example, this would be 60 mV of Differential Noise Margin (+25 mV − (−35 mV)). With the enhancedthresholdregionof−100mVto0V,thissmallexternalfail-safebiasingof+25mV(withrespectto 12 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV048A

DS90LV048A www.ti.com SNLS045C–JULY1999–REVISEDJULY2016 Typical Application (continued) 0 V) gives a DNM of a comfortable 60 mV. With the standard threshold region of ±100 mV, the external fail-safe biasing would need to be +25 mV with respect to +100 mV or +125 mV, giving a DNM of 160 mV which is stronger fail-safe biasing than is necessary for the DS90LV048A. If more DNM is required, then a stronger fail- safebiaspointcanbesetbychangingresistorvalues. Figure20. VTCoftheDS90LV048ALVDSReceiver 9.2.3 ApplicationCurve Figure21. PowerSupplyCurrentvsFrequency 10 Power Supply Recommendations AlthoughtheDS90LV047Adrawsverylittlepowerwhileatrest,itsoverallpowerconsumptionincreasesduetoa dynamic current component. The DS90LV048A power supply connection must take this additional current consumptionintoconsiderationformaximumpowerrequirements. 11 Layout 11.1 Layout Guidelines • Useatleast4PCBlayers(toptobottom):LVDSsignals,ground,power,andTTLsignals. • IsolateTTLsignalsfromLVDSsignals,otherwisetheTTLmaycoupleontotheLVDSlines.Bestpracticeisto putTTLandLVDSsignalsondifferentlayerswhichareisolatedbyapower/groundplane(s). • Keepdriversandreceiversasclosetothe(LVDSportside)connectorsaspossible. 11.1.1 PowerDecouplingRecommendations Bypass capacitors must be used on power pins. Use high-frequency ceramic (surface mount is recommended) 0.1-μFand0.001-μFcapacitorsinparallelatthepowersupplypinwiththesmallestvaluecapacitorclosesttothe device supply pin. Additional scattered capacitors over the printed-circuit board improves decoupling. Multiple vias must be used to connect the decoupling capacitors to the power planes. A 10-μF (35-V) or greater solid tantalum capacitor must be connected at the power entry point on the printed-circuit board between the supply andground. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS90LV048A

DS90LV048A SNLS045C–JULY1999–REVISEDJULY2016 www.ti.com Layout Guidelines (continued) 11.1.2 DifferentialTraces Use controlled impedance traces that match the differential impedance of your transmission medium (that is, cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs must be < 10 mm long). This helps eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1 mm apart radiate far less noise than traces 3 mm apart because magnetic field cancellation is much better with the closer traces. In addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals, which destroys the magnetic field cancellation benefits of differential signals and EMI, results. Remember the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997 mm/ps or 0.0118in/ps. Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number or vias and other discontinuitiesontheline. Avoid90° turns(thesecauseimpedancediscontinuities).Usearcsor45° bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed-circuit board, this distance must remain constant to avoid discontinuities indifferentialimpedance.Minorviolationsatconnectionpointsareallowable. 11.1.3 Termination Use a termination resistor that best matches the differential impedance or your transmission line. The resistor must be between 90 Ω and 130 Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS does not work without resistor termination. Typically, connecting a single resistoracrossthepairatthereceiverendwillsuffice. Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination tothereceiverinputsmustbeminimized.Thedistancebetweentheterminationresistorandthereceivermustbe <10mm(12mmmaximum). 11.2 Layout Example DS90LV047A DS90LV048A 1 EN DOUT1- 16 1 RIN1- EN 16 Series Termination (optional) 2 DIN1 DOUT1+ 15 2 RIN1+ ROUT1 15 LVCMOS LVCMOS Inputs 3 DIN2 DOUT2+ 14 3 RIN2+ ROUT2 14 Outputs 4 VCC DOUT2- 13 4 RIN2- VCC 13 Decoupling Cap 5 GND DOUT3- 12 5 RIN3- GND 12 Decoupling Cap 6 DIN3 DOUT3+ 11 6 RIN3+ ROUT3 11 7 DIN4 DOUT4+ 10 7 RIN4+ ROUT4 10 8 EN* DOUT4- 9 8 RIN4- EN* 9 Series Termination (optional) Input Termination (Required) Figure22. LayoutRecommendation 14 SubmitDocumentationFeedback Copyright©1999–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV048A

DS90LV048A www.ti.com SNLS045C–JULY1999–REVISEDJULY2016 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: • LVDSOwner'sManual(SNLA187) • AN-808LongTransmissionLinesandDataSignalQuality (SNLA028) • AN-977LVDSSignalQuality:JitterMeasurementsUsingEyePatternsTestReport#1SNLA166) • AN-971AnOverviewofLVDSTechnology (SNLA165) • AN-916APracticalGuidetoCableSelection(SNLA219) • AN-805CalculatingPowerDissipationforDifferentialLineDrivers (SNOA233) • AN-903AComparisonofDifferentialTerminationTechniques (SNLA034) • AN-1194FailsafeBiasingofLVDSInterfaces (SNLA051) 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.4 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©1999–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS90LV048A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) DS90LV048ATM NRND SOIC D 16 48 TBD Call TI Call TI -40 to 85 DS90LV048A TM DS90LV048ATM/NOPB ACTIVE SOIC D 16 48 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 DS90LV048A & no Sb/Br) TM DS90LV048ATMTC NRND TSSOP PW 16 92 TBD Call TI Call TI -40 to 85 DS90LV 048AT DS90LV048ATMTC/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 DS90LV & no Sb/Br) 048AT DS90LV048ATMTCX NRND TSSOP PW 16 2500 TBD Call TI Call TI -40 to 85 DS90LV 048AT DS90LV048ATMTCX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 DS90LV & no Sb/Br) 048AT DS90LV048ATMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 DS90LV048A & no Sb/Br) TM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) DS90LV048ATMTCX TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 DS90LV048ATMTCX/NO TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 PB DS90LV048ATMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) DS90LV048ATMTCX TSSOP PW 16 2500 367.0 367.0 35.0 DS90LV048ATMTCX/NOP TSSOP PW 16 2500 367.0 367.0 35.0 B DS90LV048ATMX/NOPB SOIC D 16 2500 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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