DS34C87T www.ti.com SNLS376B–MAY1998–REVISEDAPRIL2013 DS34C87T CMOS Quad TRI-STATE Differential Line Driver CheckforSamples:DS34C87T FEATURES DESCRIPTION 1 • TTLInputCompatible The DS34C87T is a quad differential line driver 2 designed for digital data transmission over balanced • TypicalPropagationDelays:6ns lines. The DS34C87T meets all the requirements of • TypicalOutputSkew:0.5ns EIA standard RS-422 while retaining the low power • OutputsWon'tLoadLineWhenV =0V characteristics of CMOS. This enables the CC construction of serial and terminal interfaces while • MeetstheRequirementsofEIAStandardRS- maintainingminimalpowerconsumption. 422 The DS34C87T accepts TTL or CMOS input levels • OperationfromSingle5VSupply and translates these to RS-422 output levels. This • TRI-STATEOutputsforConnectiontoSystem part uses special output circuitry that enables the Buses individualdriverstopowerdownwithoutloadingdown • LowQuiescentCurrent the bus. This device has separate enable circuitry for each pair of the four drivers. The DS34C87T is pin • AvailableinSurfaceMount compatibletotheDS3487T. All inputs are protected against damage due to electrostaticdischargebydiodestoV andground. CC Connection and Logic Diagrams TopView Figure2. LogicDiagram SeePINDESCRIPTIONSfordetails. Figure1. PDIPPackage SeePackageNumbersD0016AorNFG0016E 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1998–2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

DS34C87T SNLS376B–MAY1998–REVISEDAPRIL2013 www.ti.com Truth Table(1) Input Control Non-Inverting Inverting Input Output Output H H H L L H L H X L Z Z (1) L=Lowlogicstate H=Highlogicstate X=Irrelevant Z=TRI-STATE(highperformance) Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. Absolute Maximum Ratings(1)(2)(3)(4) SupplyVoltage(V ) −0.5to7.0V CC DCVoltage(V ) −1.5toV +1.5V IN CC DCOutputVoltage(V ) −0.5to7V OUT ClampDiodeCurrent(I ,I ) ±20mA IK OK DCOutputCurrent,perpin(I ) ±150mA OUT DCV orGNDCurrent(I ) ±150mA CC CC StorageTemperatureRange(T ) −65°Cto+150°C STG MaximumPowerDissipation(P )@25°C(5) D PDIPPackage 1736mW SOICPackage 1226mW LeadTemperature(T ) L (Soldering4sec) 260°C Thisdevicedoesnotmeet2000VESDrating.(6) (1) Unlessotherwisespecified,allvoltagesarereferencedtoground.Allcurrentsintodevicepinsarepositive;allcurrentsoutofdevice pinsarenegative. (2) AbsoluteMaximumRatingsarethosevaluesbeyondwhichthesafetyofthedevicecannotbespecified.Theyarenotmeanttoimply thatthedeviceshouldbeoperatedattheselimits.Thetableof“ElectricalCharacteristics”provideconditionsforactualdeviceoperation. (3) ESDRating:HBM(1.5kΩ,100pF) Inputs≥1500V Outputs≥1000V EIAJ(0Ω,200pF) AllPins≥350V (4) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications. (5) Ratingsapplytoambienttemperatureat25°C.AbovethistemperaturederateNFG0016EPackage13.89mW/°C,andD0016APackage 9.80mW/°C. (6) ESDRating:HBM(1.5kΩ,100pF) Inputs≥1500V Outputs≥1000V EIAJ(0Ω,200pF) AllPins≥350V Operating Conditions Min Max Units SupplyVoltage(V ) 4.50 5.50 V CC DCInputorOutputVoltage(V ,V ) 0 V V IN OUT CC OperatingTemperatureRange(T )DS34C87T −40 +85 °C A InputRiseorFallTimes(t,t) 500 ns r f 2 SubmitDocumentationFeedback Copyright©1998–2013,TexasInstrumentsIncorporated ProductFolderLinks:DS34C87T

DS34C87T www.ti.com SNLS376B–MAY1998–REVISEDAPRIL2013 DC Electrical Characteristics(1) V =5V±10%(unlessotherwisespecified) CC Parameter TestConditions Min Typ Max Units V HighLevelInput 2.0 V IH Voltage V LowLevelInput 0.8 V IL Voltage V HighLevelOutput V =V orV , 2.5 3.4 V OH IN IH IL Voltage I =−20mA OUT V LowLevelOutput V =V orV , 0.3 0.5 V OL IN IH IL Voltage I =48mA OUT V DifferentialOutput R =100Ω 2.0 3.1 V T L Voltage See(2) |V |–|V | DifferenceIn R =100Ω 0.4 V T T L DifferentialOutput See(2) V CommonMode R =100Ω 2.0 3.0 V OS L OutputVoltage See(2) |V –V | DifferenceIn R =100Ω 0.4 V OS OS L CommonModeOutput See(2) I InputCurrent V =V ,GND,V ,orV ±1.0 μA IN IN CC IH IL I QuiescentSupply I =0μA, CC OUT Current V =V orGND 200 500 μA IN CC V =2.4Vor0.5V(3) 0.8 2.0 mA IN I TRI-STATEOutput V =V orGND ±0.5 ±5.0 μA OZ OUT CC LeakageCurrent Control=V IL I OutputShort V =V orGND −30 −150 mA SC IN CC CircuitCurrent See(2)and (4) I PowerOffOutput V =0V V =6V 100 μA OFF CC OUT LeakageCurrent See(2) V =−0.25V −100 μA OUT (1) Unlessotherwisespecified,min/maxlimitsapplyacrossthe−40°Cto85°Ctemperaturerange.AlltypicalsaregivenforV =5Vand CC T =25°C. A (2) SeeEIASpecificationRS-422forexacttestconditions. (3) Measuredperinput.AllotherinputsatV orGND. CC (4) Thisisthecurrentsourcedwhenahighoutputisshortedtoground.Onlyoneoutputatatimeshouldbeshorted. Copyright©1998–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS34C87T

DS34C87T SNLS376B–MAY1998–REVISEDAPRIL2013 www.ti.com Switching Characteristics(1) V =5V±10%,t ,t ≤6ns(Figure3,Figure4,Figure5,Figure6) CC r f Parameter TestConditions Min Typ Max Units t ,t PropagationDelayInputtoOutput S1Open 6 11 ns PLH PHL Skew See(2) S1Open 0.5 3 ns t ,t DifferentialOutputRiseAndFallTimes S1Open 6 10 ns TLH THL t OutputEnableTime S1Closed 12 25 ns PZH t OutputEnableTime S1Closed 13 26 ns PZL t OutputDisableTime(3) S1Closed 4 8 ns PHZ t OutputDisableTime(3) S1Closed 6 12 ns PLZ C PowerDissipationCapacitance(4) 100 pF PD C InputCapacitance 6 pF IN (1) Unlessotherwisespecified,min/maxlimitsapplyacrossthe−40°Cto85°Ctemperaturerange.AlltypicalsaregivenforV =5Vand CC T =25°C. A (2) Skewisdefinedasthedifferenceinpropagationdelaysbetweencomplementaryoutputsatthe50%point. (3) Outputdisabletimeisthedelayfromthecontrolinputbeingswitchedtotheoutputtransistorsturningoff.Theactualdisabletimesare lessthanindicatedduetothedelayaddedbytheRCtimeconstantoftheload. (4) C determinesthenoloaddynamicpowerconsumption,P =C V2CCf+I V ,andthenoloaddynamiccurrentconsumption,I PD D PD CC CC S =C V f+I . PD CC CC Comparison Table of Switching Characteristics into “LS-Type” Load(1) V =5V,T =+25°C,t ≤6ns,t ≤6ns(Figure6,Figure7,Figure8,Figure9,Figure10,Figure11) CC A r f DS34C87 DS3487 Parameter TestConditions Units Typ Max Typ Max t ,t PropagationDelay 6 10 10 15 ns PLH PHL InputtoOutput Skew See(2) 1.5 2.0 ns t ,t DifferentialOutputRise 4 7 10 15 ns THL TLH andFallTimes t OutputDisableTime C =50pF,R =200Ω, 8 11 17 25 ns PHZ L L See(3) S1Closed,S2Closed t OutputDisableTime C =50pF,R =200Ω, 7 10 15 25 ns PLZ L L See(3) S1Closed,S2Closed t OutputEnableTime C =50pF,R =∞, 11 19 11 25 ns PZH L L S1Open,S2Closed t OutputEnableTime C =50pF,R =200Ω, 14 21 15 25 ns PZL L L S1Closed,S2Open (1) Thistableisprovidedforcomparisonpurposesonly.ThevaluesinthistablefortheDS34C87reflecttheperformanceofthedevicebut arenottestedorensured. (2) Skewisdefinedasthedifferenceinpropagationdelaysbetweencomplementaryoutputsatthe50%point. (3) Outputdisabletimeisthedelayfromthecontrolinputbeingswitchedtotheoutputtransistorsturningoff.Theactualdisabletimesare lessthanindicatedduetothedelayaddedbytheRCtimeconstantoftheload. 4 SubmitDocumentationFeedback Copyright©1998–2013,TexasInstrumentsIncorporated ProductFolderLinks:DS34C87T

DS34C87T www.ti.com SNLS376B–MAY1998–REVISEDAPRIL2013 AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS Note:C1=C2=C3=40pF(includingProbeandJigCapacitance),R1=R2=50Ω,R3=500Ω Figure3. ACTestCircuit Inputpulse;f=1MHz,50%,t ≤6ns,t ≤ Figure4. PropagationDelays r f 6ns Figure6. DifferentialRiseandFallTimes Figure7. PropagationDelaysTestCircuit for“LS-Type”Load Figure5. EnableandDisableTimes Copyright©1998–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS34C87T

DS34C87T SNLS376B–MAY1998–REVISEDAPRIL2013 www.ti.com Figure8. DifferentialRiseandFallTimes TestCircuitfor“LS-Type”Load Figure9. LoadEnableandDisableTimes TestCircuitfor“LS-Type”Load Figure10. LoadPropagationDelaysfor“LS-Type”Load Figure11. LoadEnableandDisableTimesfor“LS-Type”Load TYPICAL APPLICATIONS *R isoptionalalthoughhighlyrecommendedtoreducereflection. T 6 SubmitDocumentationFeedback Copyright©1998–2013,TexasInstrumentsIncorporated ProductFolderLinks:DS34C87T

DS34C87T www.ti.com SNLS376B–MAY1998–REVISEDAPRIL2013 PINDESCRIPTIONS PinNumber (PDIPorSOIC PinName Function package) 1 INPUTA ChannelA-TTL/CMOSinput 2 OUTPUTA-True TrueOutputforChannelA, RS422Levels 3 OUTPUTA-Inverting InvertingOutputforChannelA, RS422Levels 4 A/BCONTROL EnablePinforChannelsAandB, ActiveHigh,TTL/CMOSLevels 5 OUTPUTB-Inverting InvertingOutputforChannelB, RS422Levels 6 OUTPUTB-True TrueOutputforChannelB, RS422Levels 7 INPUTB ChannelB-TTL/CMOSinput 8 GND GroundPin(0V) 9 INPUTC ChannelC-TTL/CMOSinput 10 OUTPUTC-True TrueOutputforChannelC, RS422Levels 11 OUTPUTC-Inverting InvertingOutputforChannelC, RS422Levels 12 C/DCONTROL EnablePinforChannelsCandD, ActiveHigh,TTL/CMOSLevels 13 OUTPUTD-Inverting InvertingOutputforChannelD, RS422Levels 14 OUTPUTD-True TrueOutputforChannelD, RS422Levels 15 INPUTD ChannelD-TTL/CMOSinput 16 V PowerSupplyPin,5.0Vtypical CC Copyright©1998–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS34C87T

DS34C87T SNLS376B–MAY1998–REVISEDAPRIL2013 www.ti.com REVISION HISTORY ChangesfromRevisionA(April2013)toRevisionB Page • ChangedlayoutofNationalDataSheettoTIformat............................................................................................................ 7 8 SubmitDocumentationFeedback Copyright©1998–2013,TexasInstrumentsIncorporated ProductFolderLinks:DS34C87T

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) DS34C87TM/NOPB ACTIVE SOIC D 16 48 Green (RoHS Call TI | SN Level-1-260C-UNLIM -40 to 85 DS34C87TM & no Sb/Br) DS34C87TMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 DS34C87TM & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 8-Mar-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) DS34C87TMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 8-Mar-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) DS34C87TMX/NOPB SOIC D 16 2500 367.0 367.0 35.0 PackMaterials-Page2

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