Product Order Technical Tools & Support & Folder Now Documents Software Community DLP4500 DLPS151–JANUARY2019 DLP4500 .45 WXGA DMD 1 Features – InlineSurfaceInspection • 0.45-InchDiagonalMicromirrorArray – PickandPlace 1 – 912 ×1140ResolutionArray(>1Million – 3-DCapture Micromirrors) – DefectRejection – DiamondArrayOrientationSupportsSide • MedicalInstruments IlluminationforSimplified,EfficientOptics – 3-DDentalScanners Designs – VascularImaging – CapableofWXGAResolutionDisplay • 3-DBiometrics – 7.6-µmMicromirrorPitch – FingerprintIdentification – ±12° TiltAngle – FacialRecognition – 5-µsMicromirrorCrossoverTime • VirtualGauges • HighlyEfficientSteeringof VisibleLight • AugmentedReality – WindowTransmissionEfficiency96%Nominal • InteractiveDisplay (420to700 nm,SinglePassThroughTwo • Microscopes WindowSurfaces) – Polarization-IndependentAluminum 3 Description Micromirrors The DLP4500 digital micromirror device (DMD) acts – ArrayFillFactor92%(Nominal) as a spatial light modulator (SLM) to steer visible light • DedicatedDLPC350ControllerforReliable and create patterns with speed, precision, and Operation efficiency. Featuring high resolution and high brightness in a compact form factor, the DLP4500 – BinaryPatternRatesUpto4kHz DMD is well-suited for very accurate, portable 3D – PatternSequenceModeforControlOverEach machine vision and display solutions used in MicromirrorinArray industrial,medical,andsecurityapplications. • IntegratedMicromirrorDriverCircuitry DeviceInformation (1) • 9.1-mm× 20.7-mmforPortableInstruments THERMAL – FQEPackageWithSimpleConnector PARTNUMBER PACKAGE INTERFACEAREA Interface LCCC(80)(2) None – FQDPackageWithEnhancedThermal DLP4500 LCCC(98)(3) 7mmx7mm Interface (1) For all available packages, see the orderable addendum at theendofthedatasheet. 2 Applications (2) FQE package (Series-241) drawing. See DLP® Series-241 • MachineVision DMDandSystemMountingConceptsformoreinformation. (3) FQD package (Series-310) drawing. See DLP® Series-310 – 3-DDepthMeasurement DMDandSystemMountingConceptsformoreinformation. – RoboticGuidance SimplifiedApplication DC Power RGB Interface LED Drivers LEDs LVDS Interface USB Interface Light Sensor I2C Interface DLPC350 JTAG GPIO Interface Oscillator DDR Interface DLP4500 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

DLP4500 DLPS151–JANUARY2019 www.ti.com Table of Contents 1 Features.................................................................. 1 8.4 DeviceFunctionalModes........................................27 2 Applications........................................................... 1 8.5 MicromirrorArrayTemperatureCalculation............27 3 Description............................................................. 1 8.6 MicromirrorLanded-on/Landed-OffDutyCycle......30 4 RevisionHistory..................................................... 2 9 ApplicationsandImplementation...................... 33 9.1 ApplicationInformation............................................33 5 ChipsetComponentUsageSpecification...........3 9.2 TypicalApplication..................................................33 6 PinConfigurationandFunctions......................... 4 10 PowerSupplyRecommendations..................... 38 7 Specifications....................................................... 12 10.1 PowerSupplySequencingRequirements............38 7.1 AbsoluteMaximumRatings ...................................12 10.2 DMDPowerSupplyPower-UpProcedure............38 7.2 StorageConditions..................................................12 10.3 DMDPowerSupplyPower-DownProcedure.......38 7.3 ESDRatings ..........................................................12 11 Layout................................................................... 40 7.4 RecommendedOperatingConditions.....................13 11.1 LayoutGuidelines.................................................40 7.5 ThermalInformation................................................15 11.2 LayoutExample....................................................45 7.6 ElectricalCharacteristics.........................................16 12 DeviceandDocumentationSupport................. 50 7.7 TimingRequirements..............................................17 7.8 SystemMountingInterfaceLoads..........................19 12.1 DeviceSupport......................................................50 7.9 MicromirrorArrayPhysicalCharacteristics.............21 12.2 DocumentationSupport........................................51 7.10 MicromirrorArrayOpticalCharacteristics.............22 12.3 CommunityResources..........................................51 7.11 TypicalCharacteristics..........................................23 12.4 Trademarks...........................................................51 12.5 ElectrostaticDischargeCaution............................51 8 DetailedDescription............................................ 24 12.6 Glossary................................................................52 8.1 Overview.................................................................24 13 Mechanical,Packaging,andOrderable 8.2 FunctionalBlockDiagram.......................................24 Information........................................................... 52 8.3 FeatureDescription.................................................25 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. DATE REVISION NOTES January2019 * Initialrelease. 2 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 5 Chipset Component Usage Specification NOTE TI assumes no responsibility for image quality artifacts or DMD failures caused by optical systemoperatingconditionsexceedinglimitsdescribedpreviously. The DLP4500 is a component of one or more DLP® chipsets. Reliable function and operation of the DLP4500 requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI technologyanddevicesforoperatingorcontrollingaDLPDMD. Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com 6 Pin Configuration and Functions FQEPackage LCCC(80) BottomView 4 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 ConnectorPinsforFQE PIN TYPE SIGNAL DATARATE (1) INTERNAL DESCRIPTION TRACE(mm) (2) NAME NO. TERMINATION DATAINPUTS DATA(0) C12 Input LVCMOS DDR none Inputdatabus,bit0,LSB 8.11 DATA(1) C10 Input LVCMOS DDR none Inputdatabus,bit1 7.82 DATA(2) C9 Input LVCMOS DDR none Inputdatabus,bit2 7.88 DATA(3) C7 Input LVCMOS DDR none Inputdatabus,bit3 7.84 DATA(4) C4 Input LVCMOS DDR none Inputdatabus,bit4 8.10 DATA(5) C6 Input LVCMOS DDR none Inputdatabus,bit5 7.89 DATA(6) C3 Input LVCMOS DDR none Inputdatabus,bit6 7.87 DATA(7) C13 Input LVCMOS DDR none Inputdatabus,bit7 7.84 DATA(8) C15 Input LVCMOS DDR none Inputdatabus,bit8 8.13 DATA(9) C16 Input LVCMOS DDR none Inputdatabus,bit9 8.00 DATA(10) C18 Input LVCMOS DDR none Inputdatabus,bit10 8.12 DATA(11) C19 Input LVCMOS DDR none Inputdatabus,bit11 8.08 DATA(12) C21 Input LVCMOS DDR none Inputdatabus,bit12 9.27 DATA(13) C22 Input LVCMOS DDR none Inputdatabus,bit13 9.47 DATA(14) D22 Input LVCMOS DDR none Inputdatabus,bit14 9.46 DATA(15) D21 Input LVCMOS DDR none Inputdatabus,bit15 8.73 DATA(16) D19 Input LVCMOS DDR none Inputdatabus,bit16 8.10 DATA(17) D4 Input LVCMOS DDR none Inputdatabus,bit17 8.02 DATA(18) D9 Input LVCMOS DDR none Inputdatabus,bit18 8.07 DATA(19) D10 Input LVCMOS DDR none Inputdatabus,bit19 7.91 DATA(20) D6 Input LVCMOS DDR none Inputdatabus,bit20 8.52 DATA(21) D16 Input LVCMOS DDR none Inputdatabus,bit21 9.10 DATA(22) D7 Input LVCMOS DDR none Inputdatabus,bit22 8.00 DATA(23) D15 Input LVCMOS DDR none Inputdatabus,bit23,MSB 8.61 DCLK D13 Input LVCMOS DDR none Inputdatabusclock 8.63 DATACONTROLINPUTS LOADB D12 Input LVCMOS DDR none Parallel-dataloadenable 8.65 TRC D3 Input LVCMOS DDR none Input-datatoggle-ratecontrol 4.67 SCTRL D18 Input LVCMOS DDR none Serialcontrolbus 9.40 Steppedaddress-controlserial- 6.56 SAC_BUS D33 Input LVCMOS — none busdata Steppedaddress-controlserial 8.07 SAC_CLK D29 Input LVCMOS — none busclock MIRRORRESETCONTROLINPUTS DRC_BUS C29 Input LVCMOS — none DMDreset-controlserialbus 8.24 Active-lowoutputenablesignal 4.43 DRC_OE C33 Input LVCMOS — none forinternalDMDresetdriver circuitry StrobesignalforDMDreset 9.20 DRC_STROBE C36 Input LVCMOS — none controlinputs (1) (a)DDR=Doubledatarate (b)SDR=Singledatarate (c)RefertoTimingRequirementsforspecificationsandrelationships. (2) Nettracelengthsinsidethepackage: (a)RelativedielectricconstantfortheFQEpackageis9.8. (b)Propagationspeed=11.8/√(9.8)=3.769inches/ns. (c)Propagationdelay=0.265ns/inch=265ps/inch=10.43ps/mm. Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com ConnectorPinsforFQE(continued) PIN TYPE SIGNAL DATARATE (1) INTERNAL DESCRIPTION TRACE(mm) (2) NAME NO. TERMINATION POWERINPUTS (3) VBIAS C31 Power none Mirror-resetbiasvoltage VBIAS C32 Power VOFFSET D25 Power none Mirror-resetoffsetvoltage VOFFSET D26 Power VRESET D31 Power none Mirror-resetvoltage VRESET D32 Power VREF C25 Power Powersupplyforlow-voltage none CMOSdouble-data-rate(DDR) VREF C26 Power interface VCC C1 Power VCC C2 Power VCC C34 Power VCC C35 Power VCC C37 Power VCC C38 Power VCC C39 Power VCC C40 Power none PowersupplyforLVCMOSlogic VCC D1 Power VCC D2 Power VCC D34 Power VCC D35 Power VCC D37 Power VCC D38 Power VCC D39 Power VCC D40 Power (3) ThefollowingpowersuppliesareallrequiredtooperatetheDMD:VSS,VCC,VOFFSET,VBIAS,VRESET. 6 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 ConnectorPinsforFQE(continued) PIN TYPE SIGNAL DATARATE (1) INTERNAL DESCRIPTION TRACE(mm) (2) NAME NO. TERMINATION VSS C5 Power VSS C8 Power VSS C11 Power VSS C14 Power VSS C17 Power VSS C20 Power VSS C23 Power VSS C24 Power VSS C27 Power VSS C28 Power VSS C30 Power Ground–Commonreturnforall none VSS D5 Power powerinputs VSS D8 Power VSS D11 Power VSS D14 Power VSS D17 Power VSS D20 Power VSS D23 Power VSS D24 Power VSS D27 Power VSS D28 Power VSS D30 Power PinConfigurationandFunctions – TestPadsforFQEPackage NAME PIN SIGNAL DESCRIPTION A1thruA25 B1thruB25 UNUSED D36 Testpads Donotconnect E1thruE25 F1thruF25 Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com FQDPackage LCCC(98) BottomView 8 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 ConnectorPinsforFQD PIN PACKAGENET TYPE SIGNAL DATARATE (1) INTERNAL DESCRIPTION LENGTH(mm) NAME NO. TERMINATION (2) DATAINPUTS DATA(0) A1 Input LVCMOS DDR none Inputdatabus,bit0,LSB 3.77 DATA(1) A2 Input LVCMOS DDR none Inputdatabus,bit1 3.77 DATA(2) A3 Input LVCMOS DDR none Inputdatabus,bit2 3.73 DATA(3) A4 Input LVCMOS DDR none Inputdatabus,bit3 3.74 DATA(4) B1 Input LVCMOS DDR none Inputdatabus,bit4 3.79 DATA(5) B3 Input LVCMOS DDR none Inputdatabus,bit5 3.75 DATA(6) C1 Input LVCMOS DDR none Inputdatabus,bit6 3.72 DATA(7) C3 Input LVCMOS DDR none Inputdatabus,bit7 3.75 DATA(8) C4 Input LVCMOS DDR none Inputdatabus,bit8 3.78 DATA(9) D1 Input LVCMOS DDR none Inputdatabus,bit9 3.75 DATA(10) D4 Input LVCMOS DDR none Inputdatabus,bit10 3.77 DATA(11) E1 Input LVCMOS DDR none Inputdatabus,bit11 3.75 DATA(12) E4 Input LVCMOS DDR none Inputdatabus,bit12 3.71 DATA(13) F1 Input LVCMOS DDR none Inputdatabus,bit13 3.76 DATA(14) F3 Input LVCMOS DDR none Inputdatabus,bit14 3.73 DATA(15) G1 Input LVCMOS DDR none Inputdatabus,bit15 3.72 DATA(16) G2 Input LVCMOS DDR none Inputdatabus,bit16 3.77 DATA(17) G4 Input LVCMOS DDR none Inputdatabus,bit17 3.73 DATA(18) H1 Input LVCMOS DDR none Inputdatabus,bit18 3.74 DATA(19) H2 Input LVCMOS DDR none Inputdatabus,bit19 3.76 DATA(20) H4 Input LVCMOS DDR none Inputdatabus,bit20 3.70 DATA(21) J1 Input LVCMOS DDR none Inputdatabus,bit21 3.77 DATA(22) J3 Input LVCMOS DDR none Inputdatabus,bit22 3.76 DATA(23) J4 Input LVCMOS DDR none Inputdatabus,bit23,MSB 3.77 DCLK K1 Input LVCMOS DDR none Inputdatabusclock 3.74 DATACONTROLINPUTS LOADB K2 Input LVCMOS DDR none Parallel-dataloadenable 3.74 TRC K4 Input LVCMOS DDR none Input-datatoggleratecontrol 4.70 SCTRL K3 Input LVCMOS DDR none Serial-controlbus 3.75 Steppedaddress-controlserial- 3.77 SAC_BUS C20 Input LVCMOS — none busdata Steppedaddress-controlserial- 1.49 SAC_CLK C22 Input LVCMOS — none busclock MIRRORRESETCONTROLINPUTS DRC_BUS B21 Input LVCMOS — none DMDreset-controlserialbus 3.73 Active-lowoutputenablesignal 3.74 DRC_OE A20 Input LVCMOS — none forinternalDMDresetdriver circuitry StrobesignalforDMDreset- 3.73 DRC_STROBE A22 Input LVCMOS — none controlinputs (1) (a)DDR=Doubledatarate (b)SDR=Singledatarate (c)RefertoTimingRequirementsforspecificationsandrelationships. (2) Nettracelengthsinsidethepackage: (a)RelativedielectricconstantfortheFQDceramicpackageis9.8. (b)Propagationspeed=11.8/sqrt(9.8)=3.769inches/ns. (c)Propagationdelay=0.265ns/inch=265ps/inch=10.43ps/mm. Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com ConnectorPinsforFQD(continued) PIN PACKAGENET TYPE SIGNAL DATARATE (1) INTERNAL DESCRIPTION LENGTH(mm) NAME NO. TERMINATION (2) POWERINPUTS (3) VBIAS C19 Power Mirror-resetbiasvoltage VBIAS D19 Power VOFFSET A19 Power Mirror-resetoffsetvoltage VOFFSET K19 Power VRESET E19 Power Mirror-resetvoltage VRESET F19 Power VREF B19 Power PowersupplyforLVCMOS double-data-rate(DDR) VREF J19 Power interface VCC B22 Power VCC C2 Power VCC D21 Power VCC E2 Power VCC E20 Power VCC E22 Power VCC F21 Power VCC G3 Power PowersupplyforLVCMOSlogic VCC G19 Power VCC G20 Power VCC G22 Power VCC H19 Power VCC H21 Power VCC J20 Power VCC J22 Power VCC K21 Power (3) ThefollowingpowersuppliesareallrequiredtooperatetheDMD:VSS,VCC,VOFFSET,VBIAS,VRESET. 10 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 ConnectorPinsforFQD(continued) PIN PACKAGENET TYPE SIGNAL DATARATE (1) INTERNAL DESCRIPTION LENGTH(mm) NAME NO. TERMINATION (2) VSS A21 Power VSS B2 Power VSS B4 Power VSS B20 Power VSS C21 Power VSS D2 Power VSS D3 Power VSS D20 Power VSS D22 Power VSS E3 Power VSS E21 Power Ground–Commonreturnforall VSS F2 Power powerinputs VSS F4 Power VSS F20 Power VSS F22 Power VSS G21 Power VSS H3 Power VSS H20 Power VSS H22 Power VSS J2 Power VSS J21 Power VSS K20 Power PinConfigurationandFunctions – TestPadsforFQDPackage NAME PIN SIGNAL DESCRIPTION A5,A18,B5,B18,C5,C18,D5,D18,E5, UNUSED E18,F5,F18,G5,G18,H5,H18,J5,J18, Testpads Donotconnect K22 Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1) MIN MAX UNIT SUPPLYVOLTAGES (2) VCC SupplyvoltageforLVCMOScorelogic –0.5 4 V VREF SupplyvoltageforLVCMOSDDRinterface –0.5 4 V VOFFSET SupplyvoltageforhighvoltageCMOSandmicromirrorelectrode –0.5 8.75 V VBIAS (3) Supplyvoltageformicromirrorelectrode –0.5 17 V VRESET Supplyvoltageformicromirrorelectrode –11 0.5 V |VBIAS-VOFFSET| (3) Supplyvoltagedelta(absolutevalue) 8.75 V INPUTVOLTAGES (2) Inputvoltagetoallotherinputpins –0.5 VREF+0.5 V INPUTCURRENTS Currentrequiredfromahigh-leveloutput V =1.4V –9 mA OH Currentrequiredfromalow-leveloutput V =0.4V 18 mA OL CLOCKS f DCLKclockfrequency 80 120 MHz CLK ENVIRONMENTAL Casetemperature-operational (4) –20 90 °C T CASE Casetemperature-non-operational (4) –40 90 °C T DewPoint(operationandnon-operational) 81 °C DP OperatingRelativeHumidity(non-condensing) 0 95 %RH (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceisnotimpliedattheseoranyconditionsbeyondthoseindicatedunder.Exposureabove RecommendedOperatingConditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagevaluesarereferencedtocommongroundVSS.SupplyvoltagesVCC,VREF,VOFFSET,VBIAS,andVRESETareall requiredforproperDMDoperation.VSSmustalsobeconnected. (3) Topreventexcesscurrent,thesupplyvoltagedelta|VBIAS–VOFFSET|mustbelessthanthespecifiedlimit. (4) DMDTemperatureistheworst-caseofanytestpointshowninFigure9orFigure10,ortheactivearrayascalculatedbythe MicromirrorArrayTemperatureCalculation,oranypointalongtheWindowEdgeasdefinedinFigure9orFigure10.Thelocationsof thermaltestpointTP2isintendedtomeasurethehighestwindowedgetemperature.Ifaparticularapplicationcausesanotherpointon thewindowedgetobeatahighertemperature,atestpointshouldbeaddedtothatlocation. 7.2 Storage Conditions applicablebeforetheDMDisinstalledinthefinalproduct MIN MAX UNIT Storagetemperature (1) –40 85 °C Storagehumidity,non-condensing (1) 0 95% RH T stg Long-termstoragedewpoint (1) (2) 24 °C Short-termstoragedewpoint (1) (3) 28 °C (1) Asabestpractice,TIrecommendsstoringtheDMDinatemperatureandhumiditycontrolledenvironment. (2) Long-termisdefinedastheaverageovertheusablelife. (3) Short-termisdefinedas<60cumulativedaysovertheusablelifeofthedevice. 7.3 ESD Ratings VALUE UNIT V Electrostatic Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) (2) (3) ±2000 V (ESD) discharge (1) ESDRatingsareapplicablebeforetheDMDisinstalledinfinalproduct. (2) AllCMOSdevicesrequireproperElectrostaticDischarge(ESD)handlingprocedures. (3) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. 12 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 7.4 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT SUPPLYVOLTAGES (1) VCC SupplyvoltageforLVCMOScorelogic 2.375 2.5 2.625 V VREF SupplyvoltageforLVCMOSDDRinterface 1.6 1.9 2 V VOFFSET SupplyvoltageforHVCMOSandmicromirrorelectrode (2) (3) 8.25 8.5 8.75 V VBIAS Supplyvoltageformicromirrorelectrode (2) 15.5 16 16.5 V VRESET Supplyvoltageformicromirrorelectrode –9.5 –10 –10.5 V |VBIAS– Supplyvoltagedelta(absolutevalue) (2) 8.75 V VOFFSET| VOLTAGERANGE V Positive-goingthresholdvoltage 0.4×VREF 0.7×VREF V T+ V Negative-goingthresholdvoltage 0.3×VREF 0.6×VREF V T– V Hysteresisvoltage(V –V ) 0.1×VREF 0.4×VREF V hys T+ T– CLOCKFREQUENCY ƒ DCLKclockfrequency 80 120 MHz (CLK) ENVIRONMENTAL (4) DMDtemperature-operational,long-term (5) (6) 10 40to70 (7) °C T DMD DMDtemperature-operational,short-term –20 70 °C T DMDwindowtemperature-operational 0 90 °C Window T DMD|ceramicTP1-window|temperaturedelta-operational CERAMIC- (8) (9) 0 30 °C WINDOW-DELTA DMDlong-termdewpoint(operational,non-operational) 24 °C DMDshort-termdewpoint(operational,non-operational) (10) 28 °C ILLUMINATION ILL Illuminationpower-spectralregion<420nm 0.68 mW/cm2 UV-VIS Ipllaucmkiangaetionpower-spectralregion420to700nm,FQE LiTmhietermda(1ll1y) mW/cm2 ILL VIS Ipllaucmkiangaetionpower-spectralregion420to700nm,FQD LiTmhietermda(1ll1y) mW/cm2 ILL Illuminationpower-spectralregion>700nm 10 mW/cm2 IR (1) SupplyvoltagesVCC,VREF,VOFFSET,VBIAS,andVRESETareallrequiredforproperDMDoperation.Allvoltagevaluesare referencedtocommongroundVSS. (2) Topreventexcesscurrent,thesupplyvoltagedelta|VBIAS–VOFFSET|mustbelessthanspecifiedlimit. (3) VOFFSETsupplytransientsmustfallwithinspecifiedmaxvoltages. (4) Optimallong-termperformanceandopticalefficiencyofthedigitalmicromirrordevice(DMD)canbeaffectedbyvariousapplication parameters,includingilluminationspectrum,illuminationpowerdensity,micromirrorlandeddutycycle,ambienttemperature(storage andoperating),DMDtemperature,ambienthumidy(storageandoperating),andpoweronoroffdutycycle. (5) DMDtemperatureistheworst-caseofanytestpointshowninFigure9orFigure10,ortheactivearrayascalculatedbytheMicromirror ArrayTemperatureCalculation,oranypointalongthewindowedgeasdefinedinFigure9orFigure10.Thelocationsofthermaltest pointTP2inFigure9orFigure10isintendedtomeasurethehighestwindowedgetemperature.Ifaparticularapplicationcauses anotherpointonthewindowedgetobeatahighertemperature,atestpointshouldbeaddedtothatlocation. (6) Long-termisdefinedastheaverageovertheusablelife. (7) PerFigure1,themaximumoperationalcasetemperatureattestpointsTP1andTP2asshowninFigure9orFigure10shouldbe deratedbasedonthemicromirrorlandeddutycyclethattheDMDexperiencesintheendapplication.RefertoMicromirrorLanded- on/Landed-OffDutyCycleforadefinitionoflandeddutycycle. (8) Betweenanytwopointsonorwithinthepackageincludingthemirrorarray. (9) CeramicpackageandwindowtemperatureasmeasuredattestpointsTP1andTP2inFigure9orFigure10. (10) Dewpointsbeyondthespecifiedlong-termdewpoint(operating,non-operating,orstorage)areforshort-termconditionsonly,where short-termisdefinedas<60cumulativedaysovertheusefullifeofthedevice. (11) RefertoMicromirrorArrayTemperatureCalculationandTemperatureCalculationforinformationrelatedtocalculatingthemicromirror arraytemperature. Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com 80 – e ur erat 70 p m TeC) MDal (° 60 Dn nded eratio 50 ep mO m o ec 40 R x a M 30 0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50 100/0 95/5 90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45 Micromirror Landed Duty Cycle D001 Figure1. MaximumRecommendedDMDTemperature – DeratingCurve 14 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 7.5 Thermal Information overoperatingfree-airtemperaturerange(unlessotherwisenoted) DLP4500 THERMALMETRIC FQE(LCCC) FQD(LCCC) UNIT 80PINS 98PINS Thermalresistance-Activeareatocaseceramic 2 2 °C/W Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com 7.6 Electrical Characteristics overtherangeofrecommendedsupplyvoltageandrecommendedcaseoperatingtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN NOM MAX UNIT I Low-levelinputcurrent (1) VREF=2.00V,V =0V –50 nA IL I I High-levelinputcurrent (1) VREF=2.00V,V =VREF 50 nA IH I CURRENT I CurrentintoVREFpin VREF=2.00V,f =120MHz 2.15 2.75 mA REF DCLK I CurrentintoVCCpin VCC=2.75V,f =120MHz 125 160 mA CC DCLK I CurrentintoVOFFSETpin (2) VOFFSET=8.75V,Threeglobalresets 3 3.3 mA OFFSET withintimeperiod=200μs I CurrentintoVBIASpin (2) (3) VBIAS=16.5V,Threeglobalresets 2.55 6.5 mA BIAS withintimeperiod=200μs I CurrentintoVRESETpin VRESET=–10.5V 2.45 3.1 mA RESET I 135.15 175.65 mA TOTAL POWER P PowerintoVREFpin (4) VREF=2.00V,f =120MHz 4.15 5.5 mW REF DCLK P PowerintoVCCpin (4) VCC=2.75V,f =120MHz 343.75 440 mW CC DCLK POFFSET PowerintoVOFFSETpin (4) VOFFSET=8.75V,Threeglobalresets 26.25 28.9 mW withintimeperiod=200μs PBIAS PowerintoVBIASpin (4) VBIAS=16.5V,Threeglobalresets 42.1 58.6 mW withintimeperiod=200μs P PowerintoVRESETpin (4) VRESET=–10.5V 25.71 32.6 mW RESET P 442 566 mW TOTAL CAPACITANCE C Inputcapacitance ƒ=1MHz 10 pF I C Outputcapacitance ƒ=1MHz 10 pF O (1) AppliestoLVCMOSpinsonly.LVCMOSpinsdonothavepulluporpulldownconfigurations. (2) ExceedingthemaximumallowableabsolutevoltagedifferencebetweenVBIASandVOFFSETmayresultinexcesscurrentdraw.See theAbsoluteMaximumRatingsforfurtherdetails. (3) WhenDRC_OE=HIGH,theinternalresetdriversaretri-statedandI standbycurrentis6.5mA. BIAS (4) Insomeapplications,thetotalDMDheatloadcanbedominatedbytheamountofincidentlightenergyabsorbed.SeetheMicromirror ArrayTemperatureCalculationforfurtherdetails. 16 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 7.7 Timing Requirements Overoperatingfree-airtemperaturerange(unlessotherwisenoted).Thisdatasheetprovidestimingatthedevicepin. MIN NOM MAX UNIT Setuptime:DATAbeforerisingorfallingedgeofDCLK (1) 0.7 t Setuptime:TRCbeforerisingorfallingedgeofDCLK (1) 0.7 ns su(1) Setuptime:SCTRLbeforerisingorfallingedgeofDCLK (1) 0.7 t Setuptime:LOADBlowbeforerisingedgeofDCLK (1) 0.7 ns su(2) t Setuptime:SAC_BUSlowbeforerisingedgeofSAC_CLK (1) 1 ns su(3) t Setuptime:DRC_BUShighbeforerisingedgeofSAC_CLK (1) 1 ns su(4) t Setuptime:DRC_STROBEhighbeforerisingedgeofSAC_CLK (1) 2 ns su(5) Holdtime:DATAafterrisingorfallingedgeofDCLK (1) 0.7 t Holdtime:TRCafterrisingorfallingedgeofDCLK (1) 0.7 ns h(1) Holdtime:SCTRLafterrisingorfallingedgeofDCLK (1) 0.7 t Holdtime:LOADBlowafterfallingedgeofDCLK (1) 0.7 ns h(2) t Holdtime:SAC_BUSlowafterrisingedgeofSAC_CLK (1) 1 ns h(3) t Holdtime:DRC_BUSafterrisingedgeofSAC_CLK (1) 1 ns h(4) t Holdtime:DRC_STROBEafterrisingedgeofSAC_CLK (1) 2 ns h(5) Risetime(20%to80%):DCLK/SAC_CLK,VREF=1.8V 1.08 t ns r Risetime(20%to80%):DATA/TRC/SCTRL/LOADB,VREF=1.8V 1.08 Falltime(20%to80%):DCLK/SAC_CLK,VREF=1.8V 1.08 t ns f Falltime(20%to80%):DATA/TRC/SCTRL/LOADB 1.08 t Clockcycle:DCLK 8.33 10 12.5 ns c1 t Clockcycle:SAC_CLK 12.5 13.33 14.3 ns c3 t Pulsewidthhighorlow:DCLK 3.33 ns w1 t Pulsewidthlow:LOADB 4.73 ns w2 t Pulsewidthhighorlow:SAC_CLK 5 ns w3 t Pulsewidthhigh:DRC_STROBE 7 ns w5 (1) Setupandholdtimesshownareforfastinputslewrates>1V/ns.Forslowslewrates>0.5V/nsand<1V/ns,thesetupandholdtimes arelonger.Forevery0.1V/nsdecreaseinslewratefrom1V/ns,add150psonsetupandhold. Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com Figure2. TimingDiagram 18 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 7.8 System Mounting Interface Loads MIN NOM MAX UNIT Uniformlydistributedacrossthe Staticloadappliedtothepackageelectrical connectorarea (1) FQE threedatum-Aareasandthe 110 N package( datum-Earea. 2) StaticloadappliedtotheDMDmountingarea (1) 110 N Loadappliedtothethermalinterfacearea (3) FQD UThneifromrmallyIndteisrtfraibcueteadreoaver 62 N package( Loadappliedtotheelectricalinterfaceareas 4) Uniformlydistributedovereachof (3) thetwoareas 55 N (1) SeeandMechanical,Packaging,andOrderableInformationfordiagrams. (2) SeeMountingConceptsDLP4500FQE. (3) SeeandFigure4fordiagrams. (4) SeeMountingConceptsDLP4500FQD. Datum'A'area(3places) Datum'E'(1place) ConnectorArea DMDMountingAreas (3placesoppositeDatum'A' 1placeoppositeDatum'E') Figure3. SystemInterfaceLoadsforFQE Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com Datum'A'area(3places) Datum'E'area(1place) ThermalInterfaceArea ElectricalInterface ElectricalInterface AreaNumber1 Area Number 2 Figure4. SystemInterfaceLoadsforFQD 20 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 7.9 Micromirror Array Physical Characteristics VALUE UNIT Numberofactivemicromirrorrows (1) 1140 micromirrors Numberofactivemicromirrorcolumns (1) 912 micromirrors Micromirrorpitch,diagonal (1) 7.6 µm Micromirrorpitch,verticalandhorizontal (1) 10.8 µm 1140 micromirrors Micromirroractivearrayheight (2) 6161.4 µm 912 micromirrors Micromirroractivearraywidth (2) 9855 µm Micromirrorarrayborder (3) 10 mirrors/side (1) SeeMicromirrorArray,Pitch,andHinge-AxisOrientation. (2) SeeMicromirrorActiveAreainFigure5. (3) Themirrorsthatformthearrayborderarehard-wiredtotiltinthe–12°(“Off”)directiononcepowerisappliedtotheDMD(see MicromirrorArray,Pitch,andHinge-AxisOrientationandMicromirrorLandedPositionsandLightPaths). Figure5. DLP4500MicromirrorActiveArea Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com 7.10 Micromirror Array Optical Characteristics TIassumesnoresponsibilityforend-equipmentopticalperformance.Achievingthedesiredend-equipmentoptical performanceinvolvesmakingtrade-offsbetweennumerouscomponentandsystemdesignparameters.Seetherelated applicationreportsinRelatedDocumentationforspecificguidelines. PARAMETER TESTCONDITIONS MIN NOM MAX UNIT DMDparkedstate (1)(2) (3),see (4) 0 α Micromirrortiltangle degrees DMDlandedstate (1) (5) (6),see (4) 11 12 13 β M(8)ic(r9o)mirrortiltanglevariation (1) (5) (7) See (4) –1 1 degrees Micromirrorcrossovertime (10) (11) 5 μs Micromirrorswitchingtime (11) 16 μs Non-operatingmicromirrors (12) Non-adjacentmicromirrors 10 micromirro Adjacentmicromirrors 0 rs Orientationofthemicromirroraxis-of- rotation (13) 89 90 91 degrees Micromirrorarrayfillfactor (14) (15) (16) f/3illuminationat24degreeangle, 92% mirrorstiltedtowardillumination Mirrormetalspecularreflectivity (14) (15) 420nmto700nm 89% Windowmaterial CorningEagleXG Windowaperture See (17) (1) Measuredrelativetotheplaneformedbytheoverallmicromirrorarray. (2) Parkingthemicromirrorarrayreturnsallofthemicromirrorstoarelativelyflat(0˚)state(asmeasuredrelativetotheplaneformedbythe overallmicromirrorarray). (3) Whenthemicromirrorarrayisparked,thetiltangleofeachindividualmicromirrorisuncontrolled. (4) SeeFigure8. (5) Additionalvariationexistsbetweenthemicromirrorarrayandthepackagedatums. (6) Whenthemicromirrorarrayislanded,thetiltangleofeachindividualmicromirrorisdictatedbythebinarycontentsoftheCMOS memorycellassociatedwitheachindividualmicromirror.Abinaryvalueof1resultsinamicromirrorlandinginannominalangular positionof+12°.Abinaryvalueof0resultsinamicromirrorlandinginannominalangularpositionof–12°. (7) Representsthelandedtiltanglevariationrelativetothenominallandedtiltangle (8) Representsthevariationthatcanoccurbetweenanytwoindividualmicromirrors,locatedonthesamedeviceorlocatedondifferent devices. (9) Forsomeapplications,itiscriticaltoaccountforthemicromirrortiltanglevariationintheoverallsystemopticaldesign.Withsome systemopticaldesigns,themicromirrortiltanglevariationwithinadevicemayresultinperceivablenon-uniformitiesinthelightfield reflectedfromthemicromirrorarray.Withsomesystemopticaldesigns,themicromirrortiltanglevariationbetweendevicesmayresultin colorimetryvariationsorsystemcontrastvariations. (10) Micromirrorcrossovertimeisprimarilyafunctionofthenaturalresponsetimeofthemicromirrors. (11) Performanceasmeasuredatthestartoflife. (12) Non-operatingmicromirrorisdefinedasamicromirrorthatisunabletotransitionnominallyfromthe–12°positionto+12°orviceversa. (13) MeasuredrelativetothepackagedatumsBandC,showninthePackageMechanicalDatasectioninMechanical,Packaging,and OrderableInformation. (14) ThenominalDMDtotalopticalefficiencyresultsfromthefollowingfourcomponents: (a)Micromirrorarrayfillfactor (b)Micromirrorarraydiffractionefficiency (c)Micromirrorsurfacereflectivity(verysimilartothereflectivityofbulkAluminum) (d)WindowTransmission(singlepassthroughtwosurfacesforincominglight,andsinglepassthroughtwosurfacesforreflectedlight) (15) TheDMDdiffractionefficiencyandtotalopticalefficiencyobservedinaspecificapplicationdependsonnumerousapplication-specific designvariables,suchas: (a)Illuminationwavelength,bandwidthorline-width,degreeofcoherence (b)Illuminationangle,plusangletolerence (c)Illuminationandprojectionaperturesize,andlocationinthesystemopticalpath (d)IlluminationoverfilloftheDMDmicromirrorarray (e)Aberrationspresentintheilluminationsourceorpath,orboth (f)Aberrationspresentintheprojectionpath Doesnotaccountfortheeffectofmicromirrorswitchingdutycycle,whichisapplicationdependent.Micromirrorswitchingdutycycle representsthepercentageoftimethatthemicromirrorisactuallyreflectinglightfromtheopticalilluminationpathtotheopticalprojection path.Thisdutycycledependsontheilluminationaperturesize,theprojectionaperturesize,andthemicromirrorarrayupdaterate. (16) TheMicromirrorarrayfillfactordependsonnumerousapplication-specificdesignvariables,suchas: (a)Illuminationangle,plusangletolerance (b)Illuminationandprojectionaperturesize,andlocationinthesystemopticalpath (17) SeethePackageMechanicalCharacteristicsinMechanical,Packaging,andOrderableInformationfordetailsregardingthesizeand locationofthewindowaperture. 22 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 Micromirror Array Optical Characteristics (continued) TIassumesnoresponsibilityforend-equipmentopticalperformance.Achievingthedesiredend-equipmentoptical performanceinvolvesmakingtrade-offsbetweennumerouscomponentandsystemdesignparameters.Seetherelated applicationreportsinRelatedDocumentationforspecificguidelines. PARAMETER TESTCONDITIONS MIN NOM MAX UNIT Illuminationoverfill (18) See (18) Windowtransmittance(singlepass 96% throughtwowindowsurfaces) (14) (15) 420nmto700nm,SeeFigure6 (18) TheactiveareaoftheDLP4500deviceissurroundedbyanapertureontheinsideoftheDMDwindowsurfacethatmasksstructuresof theDMDdeviceassemblyfromnormalview.Theapertureissizedtoanticipateseveralopticalconditions.Overfilllightilluminatingthe areaoutsidetheactivearraycanscatterandcreateadverseeffectstotheperformanceofanendapplicationusingtheDMD. Design theilluminationopticalsystemastolimitlightfluxincidentoutsidetheactivearraytolessthan10%ofthelightfluxlevelintheactive area.Dependingontheparticularsystem'sopticalarchitectureandassemblytolerances,theamountofoverfilllightontheoutsideofthe activearraymaycausesystemperformancedegradation. 7.11 Typical Characteristics Singlepassthroughtwowindowsurfaces. 110 100 90 80 %) e ( 70 nc 60 a mitt 50 s an 40 Tr 30 20 0 Degrees AOI 10 30 Degrees AOI 0 200 250 300 350 400 450 500 550 600 650 700 750 800 Wavelength (nm) D001 Figure6.DLP4500DMDWindowTransmittance Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com 8 Detailed Description 8.1 Overview Electrically, the DLP4500 device consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of 912 memory cell columns by 1140 memory cell rows. The CMOS memory array is addressed on a column-by-column basis, over a 24-bit DDR bus. Addressing is handled through a serial control bus. The specific CMOSmemoryaccessprotocolishandledbytheDLPC350digitalcontroller. Optically, the DLP4500 device consists of 1039680 highly reflective, digitally switchable, micrometer-sized mirrors (micromirrors) organized in a two-dimensional array. The micromirror array consists of 912 micromirror columns by 1140 micromirror rows in diamond pixel configuration (Figure 7). Due to the diamond pixel configuration,thecolumnsofeachoddrowareoffsetbyhalfapixelfromthecolumnsoftheevenrow. 8.2 Functional Block Diagram VCC VSS Data (23:0) SCTRL SAC_BUS SAC_CLK DCLK TRC LOADBZ High Speed Interface Misc Column Write Control Bit Lines (0,0) Voltage Voltages Word Lines Micromirror Array Row Generators (911,1139) Control Column Read Control Low Speed Interface VCC VSS VRESET OFFSET VBIAS VRef RC_BUS RC_OEZ STROBE V D D _ C R D 24 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 8.3 Feature Description Each aluminum micromirror is approximately 7.6 microns in size and arranged in row and columns as shown in Figure 7. Due to the diamond pixel array of the DMD, the pixel data does not appear on the DMD exactly as it would in an orthogonal pixel arrangement. Pixel arrangement and numbering for the DLP4500 is shown in Figure7. Each micromirror is switchable between two discrete angular positions: –12° and 12°. The angular positions α and β are measured relative to a 0° flat reference when the mirrors are parked in their inactive state, parallel to the array plane (see Figure 8). The parked position is not a latched position. Individual micromirror angular positions are relatively flat, but do vary. The tilt direction is perpendicular to the hinge-axis. The on-state landed positionisdirectedtowardtheleftsideofthepackage(seeFigure8). Figure7. MicromirrorArray,Pitch,andHinge-AxisOrientation Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com Feature Description (continued) Figure8. MicromirrorLandedPositionsandLightPaths 26 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 Feature Description (continued) Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell contents, after the mirror clocking pulse is applied. The angular position (–12° or 12°) of the individual micromirrors changes synchronously with a micromirror clocking pulse, rather than being coincident with the CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror switching to a 12° position. Writing a logic 0 into a memory cell followedbyamirrorclockingpulseresultsinthecorrespondingmicromirrorswitchingtoa–12° position. Updatingtheangularpositionofthemicromirrorarrayconsistsoftwosteps. 1. UpdatethecontentsoftheCMOSmemory. 2. Applyingamirrorclockingpulsetotheentiremicromirrorarray. Mirror reset pulses are generated internally by the DLP4500 DMD, with initiation of the pulses being coordinated bytheDLPC350controller.Fortimingspecifications,seeTimingRequirements. Around the perimeter of the 912 × 1140 array of micromirrors is a uniform band of border micromirrors. The border micromirrors are not user-addressable. The border micromirrors land in the –12° position after power has beenappliedtothedevice.Thereare10bordermicromirrorsoneachsideofthe912× 1140activearray. 8.4 Device Functional Modes DLP4500 is part of the chipset comprising of the DLP4500 DMD and DLPC350 display controller. To ensure reliable operation, the DLP4500 DMD must always be used with the DLPC350 display controller. DMD functional modes are controlled by the DLPC350 digital display controller. See the DLPC350 data sheet listed in Related Documentation. 8.4.1 OperatingModes The DLPC350 is capable of sending patterns to the DLP4500 DMD in two different streaming modes. The first mode is continuous streaming mode, where the DLPC350 uses the parallel RGB interface to stream the 24-bit patterns to the DMD. The second mode is burst mode, where the DLPC350 loads up to 48 binary patterns from flash storage into internal memory, and then streams those patterns to the DMD. Table 1 shows the maximum patternanddataratesforbothmodesofoperation. Table1.PatternandDataRates OPERATINGMODE PATTERNRATE(Hz) DATARATE(Gbps) MAXIMUMBINARYPATTERNS ContinuousStreaming(1) 2880 2.99 Unlimited Burst(2) 4220 4.39 48 (1) ContinuousstreamingmodeusespatternsfromRGBinterface. (2) Burstmodeusespatternsfrominternalmemory. 8.5 Micromirror Array Temperature Calculation Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the maximum temperature of any individual micromirror in the active array, the maximum temperature of the window aperture,andthetemperaturegradientbetweenanytwopointsonorwithinthepackage. SeetheAbsoluteMaximumRatingsandRecommendedOperatingConditionsforapplicabletemperaturelimits. 8.5.1 PackageThermalResistance The DMD is designed to conduct the absorbed and dissipated heat back to the package where it can be removed by an appropriate thermal management system. The thermal management system must be capable of maintaining the package within the specified operational temperatures at the Thermal test point location, see Figure 9. The total heat load on the DMD is typically driven by the incident light absorbed by the active area; although other contributions can include light energy absorbed by the window aperture, electrical power dissipationofthearray,and/orparasiticheating. Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com Micromirror Array Temperature Calculation (continued) 8.5.2 CaseTemperature The temperature of the DMD case can be measured directly. For consistency, a thermal test point location TP1 representingthecasetemperatureisdefinedasshowninFigure9andFigure10. Figure9. ThermalTestPointLocation-FQEPackage 28 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 Micromirror Array Temperature Calculation (continued) Figure10. ThermalTestPointLocation-FQDPackage 8.5.2.1 TemperatureCalculation Micromirror array temperature cannot be measured directly, therefore it must be computed analytically using one ormoreoftheseconditions: • Thermaltestpointlocation(seeFigure9orFigure10) • Packagethermalresistance • Electricalpowerdissipation • Illuminationheatload Therelationshipbetweenthemicromirrorarrayandthecasetemperatureisprovidedbythefollowingequations: T =T +(Q ×R ) (1) Array Ceramic Array Array-To-Ceramic Q =Q +Q (2) Array Elec Illum Q =C ×SL Illum L2W where • T =Computedmicromirrorarraytemperature(°C) Array • T =Ceramiccasetemperature(°C),locatedatTP1 Ceramic • Q =Total(electrical+absorbed)DMDarraypower(W) Array • R =ThermalresistanceofDMDpackagefromarraytoTP1(°C/W) Array-to-Ceramic • Q =Nominalelectricalpower(W) Elec • Q =Absorbedilluminationheat(W) Illum • C =Lumens-to-wattsconstant,estimatedat0.00293W/lm,basedonarraycharacteristics.Itassumesa L2W spectralefficiencyof300lm/Wfortheprojectedlight,illuminationdistributionof83.7%ontheactivearray,and 16.3%onthearrayborderandwindowaperture • SL=Screenlumens (3) Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com Micromirror Array Temperature Calculation (continued) An example calculation is provided in Equation 4 and Equation 5. DMD electrical power dissipation varies and depends on the voltage, data rates, and operating frequencies. The nominal electrical power dissipation is used in this calculation with nominal screen lumens of 200 lm and a ceramic case temperature at TP1 of 55°C. Using thesevaluesinthepreviousequations,thefollowingvaluesarecomputed: Q =Q +C ×SL=0.442W+(0.00293W/lm×200lm)=1.028W (4) Array Elec L2W T =T +(Q ×R )=55°C+(1.028W×2°C/W)=57.1°C (5) Array Ceramic Array Array-To-Ceramic 8.6 Micromirror Landed-on/Landed-Off Duty Cycle 8.6.1 DefinitionofMicromirrorLanded-On/Landed-OffDutyCycle The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a percentage) that an individual micromirror is landed in the On–state versus the amount of time the same micromirrorislandedintheOff–state. As an example, a landed duty cycle of 75/25 indicates that the referenced micromirror is in the On–state 75% of the time (and in the Off–state 25% of the time); whereas 25/75 would indicate that the micromirror is in the On–state 25% of the time. Likewise, 50/50 indicates that the micromirror is On 50% of the time and Off 50% of thetime. Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other state(OFForON)isconsiderednegligibleandisthusignored. Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages) alwaysaddto100. 8.6.2 LandedDutyCycleandUsefulLifeoftheDMD Knowing the long-term average landed duty cycle (of the end product or application) is important because subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed dutycycleforaprolongedperiodoftimecanreducetheDMD’susablelife. ThesymmetryofthelandeddutycycleisdeterminedbyhowclosetheOn-stateandOff-statepercentagesareto being equal. For example, a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0or0/100isperfectlyasymmetrical. For extended useful lifetime of the DMD, it is strongly recommended not to put any individual pixel in a 100/0 or 0/100 duty cycle for prolonged periods of time. It’s recommended as much as possible to put the DMD in a 50/50 duty cycle across the entire DMD mirror array, where all the mirrors are continuously flipped between the on and off states. A few examples when the DMD could be in a 50/50 duty cycle mode include: when the system is idle, the illumination is disabled, between sequential pattern exposures, or when the exposure pattern sequence is stoppedforanyreason. 8.6.3 LandedDutyCycleandOperationalDMDTemperature Operational DMD temperature and landed duty cycle interact to affect the DMD’s usable life, and this interaction can be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD’s usable life. This isquantifiedinthede-ratingcurveshowninFigure1.Theimportanceofthiscurveisthat: • Allpointsalongthiscurverepresentthesameusablelife. • All points above this curve represent lower usable life (and the further away from the curve, the lower the usablelife). • All points below this curve represent higher usable life (and the further away from the curve, the higher the usablelife). In practice, this curve specifies the maximum operating DMD temperature for a given long-term average landed dutycycle. 8.6.4 EstimatingtheLong-TermAverageLandedDutyCycleofaProductorApplication During a given period of time, the landed duty cycle of a given micromirror follows from the image content being displayedbythatmicromirror. 30 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 Micromirror Landed-on/Landed-Off Duty Cycle (continued) For example, in the simplest case, when displaying pure-white on a given micromirror for a given time period, that micromirror experiences a 100/0 landed duty cycle during that time period. Likewise, when displaying pure- black,themicromirrorexperiencesa0/100landeddutycycle. Between the two extremes (ignoring for the moment color and any image processing that may be applied to an incomingimage),thelandeddutycycletracksone-to-onewiththelineargrayscalevalue,asshowninTable2. Table2.GrayscaleValueandLandedDutyCycle NOMINALLANDEDDUTY GRAYSCALEVALUE CYCLE 0% 0/100 10% 10/90 20% 20/80 30% 30/70 40% 40/60 50% 50/50 60% 60/40 70% 70/30 80% 80/20 90% 90/10 100% 100/0 Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from 0% to 100%) for each constituent primary color (red, green, and/or blue) for the given micromirror as well as the color cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a givenprimarymustbedisplayedinordertoachievethedesiredwhitepoint. Duringagivenperiodoftime,thelandeddutycycleofagivenmicromirrorcanbecalculatedasfollows: LandedDutyCycle=(Red_Cycle_%×Red_Scale_Value)+(Green_Cycle_%×Green_Scale_Value)+(Blue_Cycle_% ×Blue_Scale_Value) where • Red_Cycle_%,Green_Cycle_%,andBlue_Cycle_%,representthepercentageoftheframetimethatRed, Green,andBluearedisplayed(respectively)toachievethedesiredwhitepoint. (6) For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in order to achieve the desired white point), then the landed duty cycle for various combinations of red, green, blue colorintensitieswouldbeasshowninTable3. Table3.ExampleLandedDutyCycleforFull-Color REDCYCLEPERCENTAGE GREENCYCLEPERCENTAGE BLUECYCLEPERCENTAGE 50% 20% 30% NOMINALLANDEDDUTY CYCLE REDSCALEVALUE GREENSCALEVALUE BLUESCALEVALUE 0% 0% 0% 0/100 100% 0% 0% 50/50 0% 100% 0% 20/80 0% 0% 100% 30/70 12% 0% 0% 6/94 0% 35% 0% 7/93 0% 0% 60% 18/82 100% 100% 0% 70/30 0% 100% 100% 50/50 100% 0% 100% 80/20 12% 35% 0% 13/87 Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com Table3.ExampleLandedDutyCycleforFull-Color (continued) REDCYCLEPERCENTAGE GREENCYCLEPERCENTAGE BLUECYCLEPERCENTAGE 50% 20% 30% NOMINALLANDEDDUTY CYCLE REDSCALEVALUE GREENSCALEVALUE BLUESCALEVALUE 0% 35% 60% 25/75 12% 0% 60% 24/76 100% 100% 100% 100/0 32 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 9 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information For reliable operation, the DLP4500 DMD must be coupled with the DLPC350 controller. The DMD is a spatial light modulator which reflects incoming light from an illumination source to one of two directions, with the primary direction being into a projection or collection optic. Each application is derived primarily from the optical architecture of the system and the format of the data coming into the DLPC350. Applications of interest include 3Dmeasurementsystems,spectrometers,medicalsystems,andcompressivesensing. 9.2 Typical Application Figure 11 shows a typical embedded system application using the DLPC350 controller and DLP4500 DMD. In thisconfiguration,theDLPC350controllersupportsa24-bitparallelRGBinput,typicalofLCDinterfaces,froman external source or processor. This system supports both still and motion video sources. However, the controller only supports sources with periodic synchronization pulses. This is ideal for motion video sources, but can also be used for still images by maintaining periodic syncs and only sending a new frame of data when needed. The still image must be fully contained within a single video frame and meet the frame timing constraints. The DLPC350 controller refreshes the displayed image at the source frame rate and repeats the last active frame for intervalsinwhichnonewframehasbeenreceived. DC Power RGB Interface LED Enables LVDS Interface Lamp LEDs Driver USB Interface Control Processor I2C Digital Pattern Light Illumination Creation Hardware Triggers Sensor Optics DLPC350 System Control GPIO Interface DMD Control DMD Data DLP4500 OSC Camera FAN CTL VRST VBIAS VOFF FLASH JTAG DMD Voltage Supplies Figure11. TypicalApplicationSchematic Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com Typical Application (continued) 9.2.1 DesignRequirements All applications using the DLP4500 chipset require both the controller and DMD components for operation. The system also requires an external parallel flash memory device loaded with the DLPC350 configuration and support firmware. The chipset has several system interfaces and requires some support circuitry. The following interfacesandsupportcircuitryarerequired: • DLPC350systeminterfaces: – Controlinterface – Triggerinterface – Inputdatainterface – Illuminationinterface • DLPC350supportcircuitryandinterfaces: – Referenceclock – PLL – Programmemoryflashinterface • DMDinterfaces: – DLPC350toDMDdigitaldata – DLPC350toDMDcontrolinterface – DLPC350toDMDmicromirrorresetcontrolinterface 9.2.2 DetailedDesignProcedure 9.2.2.1 DLPC350SystemInterfaces The DLP4500 chipset supports a 30-bit parallel RGB interface for image data transfers from another device and a 30-bit interface for video data transfers. The system input requires proper generation of the PWRGOOD and POSENSE inputs to ensure reliable operation. The two primary output interfaces are the illumination driver controlinterfaceandsyncoutputs. 9.2.2.1.1 ControlInterface The DLP4500 chipset accepts control interface commands via the I2C or USB input buses. The control interface allows another master processor to send commands to the DLP4500 chipset to query system status or perform realtimeoperationssuchasprogrammingLEDdrivercurrentsettings. The DLPC350 controller offers two different sets of slave addresses. The I2C_ADDR_SEL pin provides the ability to select an alternate set of 7-bit I2C slave addresses only during power-up. If the I2C_ADDR_SEL pin is set low (logic '0'), then the DLPC350 slave addresses are 0x34 and 0x35. If the I2C-ADDR_SEL pin is set high (logic '1'), then the DLPC350 slave address is 0x3A and 0x3B. The I2C_ADDR_SEL pin also changes the serial number for the USB device so that two DLPC350s can be connected to one computer through USB. Once the systeminitializationiscomplete,thispinisavailableasaGPIO.SeetheDLPC350Programmer'sGuide(listedin RelatedDocumentation)fordetailedinformationabouttheseoperations. Table4listsadescriptionforactivesignalsusedbytheDLPC350tosupporttheI2Cinterface. Table4.ActiveSignals – I2CInterface SignalName Description I2Cclock.Bidirectionalopen-drainsignal.I2Cslaveclockinputfromtheexternal I2C1_SCL processor. I2Cdata.Bidirectionalopen-drainsignal.I2Cslavetoacceptcommandortransferdata I2C1_SDA toandfromtheexternalprocessor. I2C0_SCL I2Cbus0,clock;I2Cmasterforon-boardperipherals I2C0_SDA I2Cbus0,data;I2Cmasterforon-boardperipherals 34 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 9.2.2.1.2 InputDataInterface The data interface has two input data ports: a parallel RGB-input port and an FPD-Link LVDS input port. Both input ports can support up to 30 bits and have a nominal I/O voltage of 3.3 V. See the DLPC350 controller data sheet(listedinRelatedDocumentation)fordetailsrelatingtomaximumandminimuminputtimingspecifications. The parallel RGB port can support up to 30 bits in video mode. In pattern mode, only the upper 8 bits of each colorarerecognized,therebycreatinga24bitbusfromthe30bitinputbus. The FPD-Link input port can be configured to connect to a video decoder device or an external processor througha24-,27-,or30-bitinterface. Table5providesadescriptionofthesignalsassociatedwiththedatainterface. Table5.ActiveSignals – DataInterface SIGNALNAME DESCRIPTION RGBParallelInterface P1_(A,B,C)_[0:9] 30-bitdatainputs10bitsforeachofthered,green,andbluechannels).If interfacingtoasystemwithlessthan10-bitspercolor,connectthebusofthe red,green,andbluechannelstotheupperbitsoftheDLPC35010-bitbus. P1A_CLK Pixelclock;allinputsignalsondatainterfacearesynchronizedwiththisclock. P1_VSYNC Verticalsync P1_HSYNC Horizontalsync P1_DATAEN Inputdatavalid FPD-LinkLVDSInput RCK Differentialinputsignalforclock RA_IN DifferentialinputsignalfordatachannelA RB_IN DifferentialinputsignalfordatachannelB RC_IN DifferentialinputsignalfordatachannelC RD_IN DifferentialinputsignalfordatachannelD RE_IN DifferentialinputsignalfordatachannelE TheA,B,andCinputdatachannelsofPort1canbeinternallyswappedforoptimumboardlayout. 9.2.2.2 DLPC350SystemOutputInterfaces 9.2.2.2.1 IlluminationInterface AnilluminationinterfaceisprovidedthatsupportsanLEDdriverwithupto3individualchannels. Table6describestheactivesignalsfortheilluminationinterface. Table6.ActiveSignals – IlluminationInterface SIGNALNAME DESCRIPTION HEARTBEAT LEDblinkscontinuouslytoindicatesystemisrunningfine FAULT_STATUS LEDoffindicatessystemfault LEDR_EN RedLEDenable LEDG_EN GreenLEDenable LEDB_EN BlueLEDenable LEDR_PWM RedLEDPWMsignalusedtocontroltheLEDcurrent LEDG_PWM GreenLEDPWMsignalusedtocontroltheLEDcurrent LEDB_PWM BlueLEDPWMsignalusedtocontroltheLEDcurrent 9.2.2.2.2 TriggerInterface(SyncOutputs) The DLPC350 controller outputs a set of trigger signals for synchronizing displayed patterns with a camera, sensor, or other peripherals. The DLPC350 also has input triggers, where an external processor controls when thepatternsaredisplayed. Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com Table7.ActiveSignals – TriggerandSyncInterface SIGNALNAME DESCRIPTION P1_HSYNC Horizontalsync P1_VSYNC Verticalsync Advancesthepatterndisplayordisplaystwoalternatingpatterns,dependingonthe TRIG_IN_1 mode TRIG_IN_2 Pausesthepatterndisplayoradvancesthepatternbytwo,dependingonthemode TRIG_OUT_1 Activehighduringpatternexposure TRIG_OUT_2 Activehightoindicatefirstpatterndisplay 9.2.2.3 DLPC350SystemSupportInterfaces 9.2.2.3.1 ReferenceClock The DLPC350 controller requires a 32-MHz 3.3-V external input from an oscillator. This signal serves as the DLP4500 chipset reference clock from which the majority of the interfaces derive their timing. This includes DMD interfacesandserialinterfaces. 9.2.2.3.2 PLL The DLPC350 controller contains two PLLs (PLLM and PLLD), each of which have dedicated 1.2-V digital and 1.8-V analog supplies. These 1.2-V PLL pins must be individually isolated from the main 1.2-V system supply via a ferrite bead. The impedance of the ferrite bead must be much greater than the capacitor at frequencies where noise is expected. The impedance of the ferrite bead must also be less than 0.5 Ω in the frequency range of 100 to300kHzandgreaterthan10Ω atfrequenciesgreaterthan100MHz. Isolate the 1.8-V analog PLL power and ground pins as a minimum, using an LC filter with a ferrite bead serving as the inductor and a 0.1-µF capacitor on the DLPC350 side of the ferrite bead. TI recommends that this 1.8-V PLL power be supplied from a dedicated linear regulator and each PLL should be individually isolated from the regulator.Thesameferriterecommendationsdescribedforthe1.8-VanalogPLLsupplyapplytothe1.2-Vdigital PLLsupply. When designing the overall supply filter network, care must be taken to ensure that no resonances occur. Take specialcarewhenusingthe1-to2-MHzbandbecausethiscoincideswiththePLLnaturalloopfrequency. 9.2.2.3.3 ProgramMemoryFlashInterface TheDLPC350controllerprovidestwoexternalprogrammemorychipselects: • PM_CS_1mustbeusedasthechipselectforthebootflashdevice.(Standard NORFlash≤ 128Mb). • PM_CS_2isavailableforanoptionalflashdevice(≤128Mb). Theflashaccesstimingisfixedat100.5nsforreadtiming,and154.1nsforwritetiming.Instandbymode,these valueschangeto803.5nsforreadtimingand1232.1nsforwritetiming. Thesetimingvaluesassumeamaximumsingledirectiontracelengthof75mm.Whenanadditionalflashisused in conjunction with the boot flash, stub lengths must be kept short and located as close as possible to the flash endoftheroute. The DLPC350 controller provides enough program memory address pins to support a flash device up to 128 Mb. PM_ADDR_22 and PM_ADDR_21 are tri-stated GPIO pins during reset, so they require board-level pulldown resistorstopreventtheflashaddressbitsfromfloatingduringinitialbootload. 9.2.2.4 DMDInterfaces 9.2.2.4.1 DLPC350toDMDDigitalData The DLPC350 controller provides the pattern data to the DMD over a double data rate (DDR) interface. Data is clockedonbothrisingandfallingedgesoftheDCLK. Table8describesthesignalsusedforthisinterface. 36 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 Table8.ActiveSignals – DLPC350toDMDDigitalDataInterface DLPC350SIGNALNAME DMDSIGNALNAME DMD_D(23:0) DATA(23:0) DMD_DCLK DCLK 9.2.2.4.2 DLPC350toDMDControlInterface TheDLPC350controllerprovidesthecontroldatatotheDMDoveraserialbus. Table9describesthesignalsusedforthisinterface. Table9.ActiveSignals – DLPC350toDMDControlInterface DLPC350 DMD DESCRIPTION SIGNALNAME SIGNALNAME DMD_SAC_BUS SAC_BUS DMDstepped-addresscontrol(SAC)busdata DMD_SAC_CLK SAC_CLK DMDstepped-addresscontrol(SAC)busclock DMD_LOADB LOADB DMDdataloadsignal DMD_SCTRL SCTRL DMDdataserialcontrolsignal DMD_TRC TRC DMDdatatoggleratecontrol 9.2.2.4.3 DLPC350toDMDMicromirrorResetControlInterface The DLPC350 controls the micromirror clock pulses in a manner to ensure proper and reliable operation of the DMD. Table10describesthesignalsusedforthisinterface. Table10.ActiveSignals –DLPC350toDMDMicromirrorResetControlInterface DLPC350 DMD DESCRIPTION SIGNALNAME SIGNALNAME DMD_DRC_BUS DRC_BUS DMDresetcontrolserialbus DMD_DRC_OE DRC_OE DMDresetcontroloutputenable DMD_DRC_STRB DRC_STRB DMDresetcontrolstrobe Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com 10 Power Supply Recommendations 10.1 Power Supply Sequencing Requirements The DLP4500 DMD includes five voltage-level supplies (V , V , V , V , and V ), all referenced to CC REF OFFSET BIAS RESET VSS ground. For reliable operation of the DLP4500 DMD, the following power supply sequencing requirements mustbefollowed. CAUTION ReliableperformanceoftheDMDrequiresthatthefollowingconditionsbemet: 1. The V , V , V , V , and V power supply inputs must all be present CC REF OFFSET BIAS RESET duringoperation.AllvoltagesmustbereferencedtoDMDground(VSS). 2. The V , V , V , V , and V power supplies must be sequenced on CC REF OFFSET BIAS RESET andoffinthemannerprescribed. Repeated failure to adhere to the prescribed power-up and power-down procedures mayaffectdevicereliability 10.2 DMD Power Supply Power-Up Procedure 1. PowerupV andV inanyorder. CC REF 2. WaitforV andV toeachreachastablelevelwithintheirrespectiverecommendedoperatingranges. CC REF 3. Power up V , V , and V in any order, provided that the maximum delta-voltage between V BIAS OFFSET RESET BIAS andV isnotexceeded(seeAbsoluteMaximumRatingsfordetails). OFFSET NOTE During the power-up procedure, the DMD LVCMOS inputs should not be driven high untilafterstep2 iscomplete. NOTE Power supply slew rates during power up are unrestricted, provided that all other conditionsaremet. 10.3 DMD Power Supply Power-Down Procedure 1. Command the chipset controller to execute a mirror-parking sequence. See the controller data sheet (listed inRelatedDocumentation)fordetails. 2. Power down V , V , and V in any order, provided that the maximum delta voltage between BIAS OFFSET RESET V andV isnotexceeded(seeAbsoluteMaximumRatingsfordetails). BIAS OFFSET 3. WaitforV ,V ,andV toeachdischargetoastablelevelwithin4Vofthereferenceground. BIAS OFFSET RESET 4. PowerdownV andV inanyorder. CC REF NOTE During the power-down procedure, the DMD LVCMOS inputs should be held at a levellessthanV +0.3V. REF NOTE Power-supplyslewratesduringpowerdownareunrestricted,providedthatallother conditions aremet. 38 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 DMD Power Supply Power-Down Procedure (continued) Figure12. Power-UpandPower-DownTiming Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com 11 Layout 11.1 Layout Guidelines 11.1.1 DMDInterfaceDesignConsiderations The DMD interface is modeled after the low-power DDR-memory (LPDDR) interface. To minimize power dissipation, the LPDDR interface is defined to be unterminated. As a result, PCB signal-integrity management is imperative. Impedance control and crosstalk mitigation is critical to robust operation. LPDDR board design recommendations include trace spacing that is three times the trace width, impedance control within 10%, and signalroutingdirectlyoveraneighboringreferenceplane(groundor1.9-Vplane). DMD interface performance is also a function of trace length; therefore the length of the trace limits performance. The DLPC350 controller only works over a narrow range of DMD signal routing lengths at 120 MHz. Ensuring positivetimingmarginsrequiresattentiontomanyfactors. Asanexample,theDMDinterfacesystemtimingmargincanbecalculatedasfollows. SetupMargin=(DLPC350OutputSetup)–(DMDInputSetup)–(PCBRoutingMismatch)–(PCBSIDegradation) (7) Hold-TimeMargin=(DLPC350OutputHold)–(DMDInputHold)–(PCBRoutingMismatch)–(PCBSIDegradation)(8) PCB signal integrity degradation can be minimized by reducing the affects of simultaneously switching output (SSO) noise, crosstalk, and inter-symbol interface (ISI). Additionally, PCB routing mismatch can be budgeted via controlledPCBrouting. In an attempt to minimize the need for signal integrity analysis that would otherwise be required, the following PCB design guidelines are provided. They describe an interconnect system that satisfies both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab measurements. 11.1.2 DMDTerminationRequirements Table 11 lists the termination requirements for the DMD interface. These series resistors should be placed as closetotheDLPC350pinsaspossiblewhilefollowingallPCBguidelines. Table11.TerminationRequirementsforDMDInterface SIGNALS SYSTEMTERMINATION DMD_D(23:0),DMD_TRC,DMD_SCTRL, DMD_LOADB,DMD_DRC_STRB, External5-Ωseriesterminationatthetransmitter DMD_DRC_BUS,DMD_SAC_CLK,and DMD_SAC_BUS DMD_DCLK External5-Ωseriesterminationatthetransmitter External0-Ωseriestermination.Thissignalmustbe DMD_DRC_OE externallypulled-uptoVDD_DMDviaa30-kΩto 51-kΩresistor 40 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 DMD_CLKandDMD_SAC_CLKclocksshouldbeequallengths,asshowninFigure13. Figure13. Series-TerminatedClocks 11.1.3 DecouplingCapacitors The decoupling capacitors should be given placement priority. The supply voltage pin of the capacitor should be located close to the DLPC350 supply voltage pin or pins. Decoupling capacitors should have two vias connecting the capacitor to ground and two vias connecting the capacitor to the power plane, but if the trace length is less than 0.05 inches, the device can be connected directly to the decoupling capacitor. The vias should be located on opposite sides of the long side of the capacitor, and those connections should be less than 0.05 inches as well. 11.1.4 PowerPlaneRecommendations Forbestperformance,TIrecommendsthefollowing: • Twopowerplanes – Onesolidplaneforground(GND) – Onesplitplaneforothervoltageswithnosignalroutingonthepowerplanes • Powerandgroundpinsshouldbeconnectedtotheseplanesthroughaviaforeachpin. • Alldevicepinandviaconnectionstotheseplanesshoulduseathermalreliefwithaminimumoffourspokes. • Tracelengthsforthecomponentpowerandgroundpinsshouldbeminimizedto0.03inchesorless. • Viasshouldbespacedouttoavoidformingslotsonthepowerplanes. • Highspeedsignalsshouldnotcrossoveraslotintheadjacentpowerplanes. • Vias connecting all the digital layers should be placed around the edge of the rigid PCB regions 0.03 inches fromtheboardedgeswith0.1inchspacingpriortorouting. • Placing extra vias is not required if there are sufficient ground vias due to normal ground connections of devices. • Allsignalroutingandsignalviasshouldbeinsidetheperimeterringofgroundvias. 11.1.5 SignalLayerRecommendations ThePCBsignallayersshouldfollowtypicalgoodpracticeguidelinesincluding: • Layerchangesshouldbeminimizedforsingle-endedsignals. • Individual differential pairs can be routed on different layers, but the signals of a given pair should not changelayers. • Stubsshouldbeavoided. • Only voltage or low-frequency signals should be routed on the outer layers, except as noted previously in thisdocument. • Doubledataratesignalsshouldberoutedfirstforbestimpedanceandtracelengthmatching. ThePCBshouldhaveasoldermaskonthetopandbottomlayers.Themaskshouldnotcoverthevias. Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com • Except for fine pitch devices (pitch ≤ 0.032 inches), the copper pads and the solder mask cutout should beofthesamesize. • Soldermaskbetweenpadsoffinepitchdevicesshouldberemoved. • IntheBGApackage,thecopperpadsandthesoldermaskcutoutshouldbeofthesamesize. 11.1.6 GeneralHandlingGuidelinesforCMOS-TypePins To avoid potentially damaging current caused by floating CMOS input-only pins, TI recommends that unused input pins be tied through a pullup resistor to its associated power supply, or a pulldown to ground. For inputs with internal pullup or pulldown resistors, adding an external pullup or pulldown resistor is unnecessary unless specified in the Pin Configuration and Functions section. Note that internal pullup and pulldown resistors are weakandshouldnotbeexpectedtodriveanexternalline. After power-up or device reset, bidirectional pins are configured as inputs as a reset default until directed otherwise. Unusedoutput-onlypinscanbeleftopen. 11.1.7 PCBManufacturing The DLPC350 Controller and DMD are a high-performance (high-frequency and high-bandwidth) set of components.ThissectionprovidesPCBguidelinestohelpensureproperoperationofthesecomponents. The DLPC350 controller board will be a multi-layer PCB with surface mount components on both sides. The majority of large surface mount components are placed on the top side of the PCB. Circuitry is high speed digital logic.Thehighspeedinterfacesinclude: • 120-MHzDDRinterfacefromDLPC350toDMD • 150-MHzLVTTLinterfacefromavideodecodertotheDLPC350 • 150-MHzpixelclocksupporting30-bitparallelRGBinterface • LVTTLparallelmemoryinterfacebetweentheDLPC350controllerandflashwith70-nsaccesstime • LVDSflatpaneldisplayporttoDLPC350 The PCB should be designed to IPC2221 and IPC2222, Class 2, Type Z, at level B producibility and built to IPC6011andIPC6012,Class2. 11.1.7.1 GeneralGuidelines Table12.PCBGeneralRecommendations DESCRIPTION RECOMMENDATION Configuration Asymmetricdualstripline Etchthickness(T) 1.0-oz.(1.2-milthick)copper Single-endedsignalimpedance 50Ω(±10%) Differentialsignalimpedance 100Ωdifferential(±10%) 11.1.7.2 TraceWidthsandMinimumSpacings Forbestperformance,TIrecommendsthetracewidthsandminimumspacingsshowninTable13. Table13.TraceWidthsandMinimumSpacings MINIMUMTRACESPACING SIGNALNAME TRACEWIDTH(inches) (inches) P1P2,P1P2V_PLLM,P1P2V_PLLD, P2P5V,P3P3V,P1P9V,A1P8V, 0.02 0.010 A1P8V_PLLD,A1P8V_PLLM VRST,VBIAS,VOFFSET 0.02 0.010 VSS(GND) 0.02 0.005 FANx_OUT 0.02 0.020 DMD_DCLK 0.030 P1A_CLK,P1B_CLK,P1C_CLK 0.030 42 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 Table13.TraceWidthsandMinimumSpacings(continued) MINIMUMTRACESPACING SIGNALNAME TRACEWIDTH(inches) (inches) MOSC,MOSCN 0.030 11.1.7.3 RoutingConstraints In order to meet the specifications listed in the following tables, typically the PCB designer must route these signals manually (not using automated PCB routing software). In case of length matching requirements, routing traces in a serpentine fashion may be required. Keep the number of turns to a minimum and the turn angles no sharper than 45°. Traces must be 0.1 inches from board edges when possible; otherwise they must be 0.05 inches minimum from the board edges. Avoid routing long traces all around the PCB. PCB layout assumes adjacent trace spacing is twice the trace width. However, three times the trace width will reduce crosstalk and significantlyhelpperformance. Themaximumandminimumsignalroutingtracelengthsincludeescaperouting. Table14.SignalLengthRoutingConstraintsforDMDInterface MINIMUMSIGNAL MAXIMUMSIGNAL SIGNALS ROUTINGLENGTH(1) ROUTINGLENGTH(2) DMD_D(23:0),DMD_DCLK,DMD_TRC, 2480mil 2953mil DMD_SCTRL,DMD_LOADB, (63mm) (75mm) DMD_OE,DMD_DRC_STRB,DMD_DRC_BUS, 512mil 5906mil DMD_SAC_CLK,andDMD_SAC_BUS (13mm) (150mm) (1) Signallengthsbelowthestatedminimumwilllikelyresultinovershootorundershoot. (2) DMD-DDRmaximumsignallengthisafunctionoftheDMD_DCLKrate. Each high-speed, single-ended signal should be routed in relation to its reference signal, such that a constant impedance is maintained throughout the routed trace. Avoid sharp turns and layer switching while keeping total trace lengths to a minimum. The following signals should follow the signal matching requirements described in Table15. Table15.High-SpeedSignalMatchingRequirementsforDMDInterface SIGNALS REFERENCESIGNAL MAXMISMATCH UNIT DMD_D(23:0),DMD_TRC,DMD_SCTRL, ±200 mil DMD_DCLK DMD_LOADB (±5.08) (mm) DMD_DRC_STRB,DMD_DRC_BUS, ±200 mil DMD_SAC_CLK DMD_SAC_BUS,DMD_OE (±5.08) (mm) The values in Table 15 apply to the PCB routing only. They do not include any internal package routing mismatch associated with the DLPC350 or DMD. Additional margin can be attained if internal DLPC350 package skew is taken into account. Additionally, to minimize EMI radiation, serpentine routes added to facilitate trace lengthmatchingshouldonlybeimplementedonsignallayersbetweenreferenceplanes. Both the DLPC350 output timing parameters and the DMD input timing parameters include a timing budget to account for their respective internal package routing skew. Thus, additional system margin can be attained by comprehending the package variations and compensating for them in the PCB layout. To increase the system timing margin, TI recommends that the DLPC350 package variation be compensated for (by signal group), but it may not be desirable to compensate for DMD package skew. This is due to the fact that each DMD has a different skew profile, making the PCB layout DMD specific. To use a common PCB design for different DMDs, TIrecommendsthateithertheDMDpackageskewvariationnotbecompensatedforonthePCB,orthepackage lengths for all applicable DMDs being considered. Table 16 provides the DLPC350 package output delay at the packageballforeachDMDinterfacesignal. The total length of all the traces in Table 16 should be matched to the DMD_DCLK trace length. Total trace lengthincludespackageskews,PCBlength,andDMDflexcablelength. Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com Table16.DLPC350PackageSkewandRoutingTraceLengthfortheDMD Interface TOTALDELAY(PackageSkews) SIGNAL PACKAGEPIN (ps) (mil) DMD_D0 25.9 152.35 A8 DMD_D1 19.6 115.29 B8 DMD_D2 13.4 78.82 C8 DMD_D3 7.4 43.53 D8 DMD_D4 18.1 106.47 B11 DMD_D5 11.1 65.29 C11 DMD_D6 4.4 25.88 D11 DMD_D7 0.0 0.00 E11 DMD_D8 14.8 87.06 C7 DMD_D9 18.4 108.24 B10 DMD_D10 6.4 37.65 E7 DMD_D11 4.8 28.24 D10 DMD_D12 29.8 175.29 A6 DMD_D13 25.7 151.18 A12 DMD_D14 19.0 111.76 B12 DMD_D15 11.7 68.82 C12 DMD_D16 4.7 27.65 D12 DMD_D17 21.5 126.47 B7 DMD_D18 24.8 145.88 A10 DMD_D19 8.3 48.82 D7 DMD_D20 23.9 140.59 B6 DMD_D21 1.6 9.41 E9 DMD_D22 10.7 62.94 C10 DMD_D23 16.7 98.24 C6 DMD_DCLK 24.8 145.88 A9 DMD_LOADB 18.0 105.88 B9 DMD_SCTRL 11.4 67.06 C9 DMD_TRC 4.6 27.06 D9 Table17.RoutingPriority ROUTING ROUTING MATCHING SIGNAL TOLERANCE PRIORITY LAYER REFERENCESIGNAL DMD_DCLK(1) (2) (3) 1 3 – – DMD_D[23:0],DMD_SCTRL,DMD_TRC, DMD_LOADB(1) (2) (3) (4) 1 3,4 DMD_DCLK ±150mils P1_A[9:0],P1_B[9:0],P1_C[9:0], P1_HSYNC,P1_VSYNC,P1_DATAEN, 1 3,4 P1X_CLK ±0.1inches P1X_CLK ±150mils R[A-E]_IN_P,R[A-E]_IN_N,RCK_IN_P, 2 3,4 RCK Differentialsignalsneedtobe RCK_IN_N matchedwithin±12mils (1) TotalsignallengthfromtheDLPC350andtheDMD,includingflexcabletracesandPCBsignaltracelengthsmustbeheldtothe lengthsspecifiedinTable14. (2) Switchingroutinglayersisnotpermittedexceptatthebeginningandendofatrace. (3) MinimizeviasonDMDtraces. (4) MatchingincludesPCBtracelengthplustheDLPC350packagelengthplustheDMDflexcablelength. 44 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 11.1.7.4 Fiducials Fiducialsforautomaticcomponentinsertionshouldbe0.05inchdiametercopperwitha0.1-inchcutout(antipad). FiducialsforopticalautoinsertionareplacedonthreecornersofbothsidesofthePCB. 11.1.7.5 FlexConsiderations Table 18 shows the general DMD flex design recommendations. Table 19 lists the minimum flex design requirements. Table18.FlexGeneralRecommendations DESCRIPTION RECOMMENDATION Configuration Two-layermicrostrip Referenceplane1 Groundplanforproperreturn Vias Maximumtwopersignal Singletracewidth 4-milminimum Etchthickness(T) 0.5-oz.(0.6milthick)copper Single-endedsignalimpedance 50Ω(±10%) Table19.MinimumFlexDesignRequirements PARAMETER APPLICATION SINGLE-ENDEDSIGNALS UNIT 4 mil Escaperoutinginballfield (0.1) (mm) Linewidth(W)(1) PCBetchdataandcontrol 5 mil (0.13) (mm) 7 mil PCBetchclocks (0.18) (mm) 4 mil Escaperoutinginballfield (0.1) (mm) Minimumlinespacingto PCBetchdataandcontrol 2xthelinewidth(2) mil othersignals(S) (mm) mil PCBetchclocks 3xthelinewidth (mm) (1) Linewidthisexpectedtobeadjustedtoachieveimpedancerequirements. (2) Threetimesthelinespacingisrecommendedforallsignalstohelpachievethedesiredsignal integrity. 11.1.7.6 DLPC350ThermalConsiderations The underlying thermal limitation for the DLPC350 controller is that the maximum operating junction temperature (T ) must not be exceeded (see Recommended Operating Conditions in Specifications). This temperature is J dependent on operating ambient temperature, airflow, PCB design (including the component layout density and the amount of copper used), power dissipation of the DLPC350 controller, and power dissipation of surrounding components. The DLPC350 package is designed to extract heat through the power and ground planes of the PCB,thuscoppercontentandairflowoverthePCBareimportantfactors. 11.2 Layout Example 11.2.1 PrintedCircuitBoardLayerStackupGeometry The DLPC350 PCB is targeted at six layers with layer stack up shown in Figure 14. The PCB layer stack may vary depending on system design. However, careful attention is required to meet design considerations. Layers one and six should consist of the components layers. Low-speed routing and power splits are allowed on these layers. Layer two should consist of a solid ground plane. Layer five should be a split voltage plane. Layers three and four should be used as the primary routing layers. Routing on external layers should be less than 0.25 inchesforpriorityoneandtwosignals.RefertoTable17forsignalprioritygroups. Board material should be FR-370HR or similar. PCB should be designed for lead-free assembly with the stackup geometryshowninFigure14. Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com Layout Example (continued) Figure14. LayerStackup Table20.PCBLayerStackupGeometry PARAMETER DESCRIPTION RECOMMENDATION Referenceplane1 Groundplaneforproperreturn Referenceplane2 1.9-VDMDI/Opowerplaneorground Er DielectricFR4 4.3at1GHz(nominal) H1 Signaltracedistancetoreferenceplane1 5mil(0.127mm) H2 Signaltracedistancetoreferenceplane2 30.4mil 11.2.2 RecommendedDLPC350MOSCCrystalOscillatorConfiguration The DLPC350 controller requires an external reference clock to feed its internal PLL. This reference may be suppliedviaacrystaloroscillator.TheDLPC350controlleracceptsareferenceclockof32MHzwithamaximum frequency variation of 100 ppm (including aging, temperature, and trim component variation). When a crystal is used,severaldiscretecomponentsarealsorequired,asshowninFigure15. 46 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 Figure15. RecommendedCrystalOscillatorConfiguration Table21.CrystalPortElectricalCharacteristics PARAMETER NOM UNIT MOSCtoGNDcapacitance 3.9 pF MOSCNtoGNDcapacitance 3.8 pF Table22.RecommendedCrystalConfiguration PARAMETER RECOMMENDED UNIT Crystalcircuitconfiguration Parallelresonant Crystaltype Fundamental(firstharmonic) Crystalnominalfrequency 32 MHz Crystalfrequencytolerance(includingaccuracy, ±100 PPM temperature,agingandtrimsensitivity) Crystalequivalentseriesresistance(ESR) 50max Ω Crystalload 10 pF Crystalshuntload 7max pF Crystalfrequencytemperaturestability ±30 PPM R driveresistor(nominal) 100 Ω S R feedbackresistor(nominal) 1 MΩ FB TypicaldrivelevelwithTCX9C3207001crystal C externalcrystalloadcapacitor(MOSC) pF L1 (ESRmax=30Ω)=160µW.SeeFigure15 Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com Table22.RecommendedCrystalConfiguration(continued) PARAMETER RECOMMENDED UNIT TypicaldrivelevelwithTCX9C3207001crystal C externalcrystalloadcapacitor(MOSCN) pF L2 (ESRmax=30Ω)=160µW.SeeFigure15 PCBlayout Agroundisolationringaroundthecrystal If an external oscillator is used, then the oscillator output must drive the MOSC pin on the DLPC350 controller, and the MOSCN pin should be left unconnected. Note that the DLPC350 controller can only accept a triangular waveform. Similartothecrystaloption,theoscillatorinputfrequencyislimitedto32MHz. Itisassumedthattheexternalcrystaloroscillatorstabilizeswithin50msafterstablepowerisapplied. 11.2.3 RecommendedDLPC350PLLLayoutConfiguration High-frequency decoupling is required for both 1.2-V and 1.8-V PLL supplies and should be provided as close as possible to each of the PLL supply package pins as shown in the example layout in Figure 16. TI recommends that decoupling capacitors be placed under the package on the opposite side of the board. High quality, low- ESR, monolithic, surface mount capacitors should be used. Typically 0.1 µF for each PLL supply should be sufficient. The length of a connecting trace increases the parasitic inductance of the mounting and thus, where possible, there should be no trace, allowing the via to butt up against the land itself. Additionally, the connecting trace should be made as wide as possible. Further improvement can be made by placing vias to the side of the capacitorlandsordoublingthenumberofvias. The location of bulk decoupling depends on the system design. Typically, a good ceramic capacitor in the 10-µF rangeisadequate. 48 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 Figure16. PLLFilterLayout Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 49 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 DeviceNomenclature Figure17providesalegendforreadingthecompletedevicenameforanyDLPdevice. Table23.Package-SpecificInformation PACKAGETYPE PACKAGEDRAWING BODYSIZE CONNECTOR LCCC FQE 9.1mmx20.7mm PanasonicAXT580124 LCCC FQD 9.1mmx20.7mm NeoconixFBX0040CMFF6AU00 DLP4500A FQD Package Type Device Descriptor Figure17. DeviceNomenclature 12.1.2 DeviceMarkings ThedevicemarkingconsistsofthefieldsshowninFigure18Figure19. GHJJJJK DLP4500AFQE Lot Trace Code on top of DMD Device Name embedded connector Figure18. DeviceMarkingforFQE 50 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

DLP4500 www.ti.com DLPS151–JANUARY2019 Two Dimensional Matrix Code (DMD part number and lot trace code) D L P G 4 H 5 0 J 0 J J A J F K Q D DMD Device Name Lot Trace Code Figure19. DeviceMarkingsforFQD 12.2 Documentation Support 12.2.1 RelatedDocumentation ThefollowingdocumentscontainadditionalinformationrelatedtotheuseoftheDLP4500device: • DLPC350DigitalControllerDataSheet,DLPS029DLPS029 • DLPC350SoftwareProgrammer'sGuide,DLPU010 • DLP® LightCrafter™4500EvaluationModuleUser'sGuide,DLPU011 • GeometricOpticsApplicationNote,DLPA044 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.4 Trademarks E2EisatrademarkofTexasInstruments. DLPisaregisteredtrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. Copyright©2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 51 ProductFolderLinks:DLP4500

DLP4500 DLPS151–JANUARY2019 www.ti.com 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 52 SubmitDocumentationFeedback Copyright©2019,TexasInstrumentsIncorporated ProductFolderLinks:DLP4500

PACKAGE OPTION ADDENDUM www.ti.com 29-Jan-2019 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) DLP4500AFQD ACTIVE CLGA FQD 98 80 RoHS (In Call TI Level-1-NC-NC Work) & Green (In Work) DLP4500AFQE ACTIVE CLGA FQE 80 80 RoHS & Green Call TI Level-1-NC-NC DLP4500FQD ACTIVE CLGA FQD 98 5 RoHS & Green Call TI Level-1-NC-NC DLP4500FQE NRND CLGA FQE 80 80 RoHS & Call TI Level-1-NC-NC non-Green (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 29-Jan-2019 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

8 7 6 5 4 3 DWG NO. 2510852 SH 1 1 NOTES UNLESS OTHERWISE SPECIFIED: C COPYRIGHT 2010 TEXAS INSTRUMENTS REVISIONS UN-PUBLISHED, ALL RIGHTS RESERVED. REV DESCRIPTION DATE BY 1 DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY. A ECO 2104138 INITIAL RELEASE 01/20/2010 J. HOLM 2 ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION B ECO 2121955 CORRECT APERTURE X DIMENSIONS VIEW D 1/23/2012 BMH C ECO 2144971 ADD (FQD PACKAGE) TO TITLE 9/11/2014 MAA TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES. 3 BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY. 4 DMD MARKING TO APPEAR ON SYMBOLIZATION PAD. D 5 NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC, D AS SHOWN IN SECTION A-A. 6 ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEWS C AND D (SHEET 2). 7 WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1, WHEN MOUNTING IN SYSTEM. 5 2X 0.8000.100 5 4X R0.2000.050 5 C (ILLUMINATION R0.6000.100 C DIRECTION) 5 2X R0.4000.100 5 90°1.0° 3.0000.075 5 A +0.200 9.100+0.300 4.550-0.100 -0.100 A 2X 3.050+0.200 5 -0.100 5 +0.200 5 1.000-0.100 18.7000.100 (1.000) +0.300 20.700 5 -0.100 B (1.600) B (3.000) 0.400 MIN TYP. 0.9520.079 D 0.6500.050 WINDOW WINDOW APERTURE 2X ENCAPSULANT 6 3 SURFACES INDICATED A (1.732) 0 MIN TYP. IN VIEW B (SHEET 2) 1 0.038A 0.020D SECTION A-A 5 NOTCH OFFSETS 0.7800.063 1.6000.100 ACTIVE ARRAY 0.050 E E (SHEET 3) (SHEET 3) A DIMENSIONUSN LAERSES I NO TMHILELRIMWEISTEE RSSPECIFIED DJR. AHWONLM 12/1D1A/T2E009 INSTTREUXMAESNTS A T O L AENRGALNECSE S:1 EJN. GHINOEELRM 12/11/2009TITLE ICD, MECHDaAllasN TeIxaCsAL, DMD, 2 PLACE DECIMALS 0.25 QPA./ CKEONRAD 1/20/2010 .45 WXGA-800 DDR SERIES 310 1 PLACE DECIMALS 0.50 CM DIMENSIONAL LIMITS APPLY BEFORE PROCESSES F. ARMSTRONG1/20/2010 (FQD PACKAGE) INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME TPHRIORJDE ACNTGIOLNE NONE 0314DA YR1E4M.5OMV-E1 9A9L4L BURRS AND SHARP EDGES J. HALL 1/20/2010 SDIZE DWG NO 2510852 RCEV NEXT ASSY USED ON PARENTHETICAL INFORMATION FOR REFERENCE ONLY APPROVED APPLICATION SCALE 15:1 SHEET 1 OF 3 INV11-2006a 8 7 6 5 4 3 2 1

8 7 6 5 4 3 DWG NO. 2510852 SH 2 1 2X 0.812 2X 18.700 4X (1.000) D D A3 A2 4X 2.250 1.500 C 1.500 B 4X (2.300) 6 C 6 0.812 18.700 C 7 E1 VIEW B DATUMS A, B, C, AND E SCALE 15 : 1 A1 (FROM SHEET 1) B 1.500 6 9.400 1.500 4.700 C B 6 B VIEW C ENCAPSULANT MAXIMUM X/Y DIMENSIONS SCALE 15 : 1 (FROM SHEET 1) 2X 0 MIN 6 A A VIEW D ENCAPSULANT MAXIMUM HEIGHT SCALE 15 : 1 TEXAS DJR. AHWONLM 12D/A1T1E/2009SDIZE DWG NO 2510852 RCEV INSTRUMENTS Dallas Texas SCALE SHEET 2 OF 3 INV11-2006a 8 7 6 5 4 3 2 1

8 7 6 5 4 3 DWG NO. 2510852 SH 3 1 5.3130.075 (9.855) 4X (0.108) 3 ACTIVE ARRAY 1.2400.050 (0.188) 0.2600.089 D D 2 3.0810.075 (8.640) (6.1614) (6.681) 6.4210.089 WINDOW ACTIVE ARRAY APERTURE 1.500 1.500 F 7.4000.050 B C C C 0.3760.089 10.074±0.089 (10.450) C APERTURE C 80X LGA PADS L L 0.6000.060 X 0.6000.060 2.1510.050 11.8500.050 6.660.25 70.25 0.200ABC (18X TEST PADS)  0.100A (14.001) WINDOW K VIEW D J WINDOW AND ACTIVE ARRAY C APERTURE DIMENSIONS TO CENTER (FROM SHEET 1) 3.50.25 H LINE OF ZIGZAG PATTERN G B CL F 1.500 9 x 0.742 = 6.678 B 70.25 E (0.150) TYP. (42°) TYP. 1.500 D 10X 3.339 C B B A (42°) TYP. (0.068) TYP. 22 21 20 19 (18) (5) 4 3 2 1 BACK INDEX MARK (0.742) (0.742) C L 2.371 3 x 0.742 = 2.226 SYMBOLIZATION PAD 4 DETAIL F APERTURE SHORT EDGES 15.727 3 x 0.742 = 2.226 SCALE 50 : 1 A A VIEW E-E BACK SIDE METALLIZATION (FROM SHEET 1) TEXAS DJR. AHWONLM 12D/A1T1E/2009SDIZE DWG NO 2510852 RCEV INSTRUMENTS Dallas Texas SCALE SHEET 3 OF 3 INV11-2006a 8 7 6 5 4 3 2 1

8 7 6 5 4 3 DWG NO. 2511423 SH 1 1 NOTES UNLESS OTHERWISE SPECIFIED: C COPYRIGHT 2010 TEXAS INSTRUMENTS REVISIONS UN-PUBLISHED, ALL RIGHTS RESERVED. REV DESCRIPTION DATE BY 1 DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY. A ECO #2109845 - INITIAL RELEASE 8/16/2010 JLH 2 ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION B ECO #2121955 - CORRECT APERTURE X DIM'S IN VIEW D 1/23/2012 BMH C ECO #2144972 - ADD (FQE PACKAGE) TO TITLE BLOCK 9/11/2014 MAA TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES. 3 BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY. 4 DMD MARKING TO APPEAR IN CONNECTOR RECESS. D 5 NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC, D AS SHOWN IN SECTION A-A. 6 ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEWS C AND D (SHEET 2). NO ENCAPSULANT IS ALLOWED ON TOP OF THE WINDOW. 7 WHILE ONLY THE THREE DATUM A TARGET AREAS A1, A2, AND A3 ARE USED FOR MEASUREMENT, ALL 4 CORNERS SHOULD BE CONTACTED, INCLUDING E1, WHEN MOUNTING IN SYSTEM. 8 ENCAPSULANT NOT TO EXCEED THE HEIGHT OF THE WINDOW. 5 2X 0.8000.100 5 4X R0.2000.050 5 C (ILLUMINATION R0.6000.100 C DIRECTION) 5 2X R0.4000.100 5 90°1.0° 3.0000.075 5 A +0.200 9.100+0.300 4.550-0.100 -0.100 A 2X 3.050+0.200 5 -0.100 5 +0.200 5 1.000-0.100 18.7000.100 (1.000) +0.300 20.700 5 -0.100 B (1.600) (3.000) 0.9530.079 D 0.6500.050 WINDOW WINDOW APERTURE 2X ENCAPSULANT 6 B 0.400 MIN TYP. A 3 SURFACES INDICATED 7 (1.733) IN VIEW B (SHEET 2) 0.038A 0 MIN TYP. 1 0.020D SECTION A-A 0.7800.063 1.6000.100 5 ACTIVE ARRAY NOTCH OFFSETS 0.050 (0.880) E E (SHEET 3) (SHEET 3) (PANASONIC AXT680124DD1, 80-CONTACT 0.4 mm PITCH BOARD-TO-BOARD CONNECTOR HEADER) MATES WITH PANASONIC AXT580124DD1 OR EQUIVALENT A CONNECTOR SOCKET DIMENSIONUSN LAERSES I NO TMHILELRIMWEISTEE RSSPECIFIED DJR. AHWONLM 7/14D/A2T0E10 INSTTREUXMAESNTS A T O L AENRGALNECSE S:1 EJN. GHINOEELRM 7/14/2010 TITLE ICD, MECHDaAllasN TeIxaCsAL, DMD, 2 PLACE DECIMALS 0.25 QA/CE .45 WXGA-800 DDR SERIES 241 1 PLACE DECIMALS 0.50 CM DIMENSIONAL LIMITS APPLY BEFORE PROCESSES (FQE PACKAGE) INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME TPHRIORJDE ACNTGIOLNE NONE 0314DA YR1E4M.5OMV-E1 9A9L4L BURRS AND SHARP EDGES SDIZE DWG NO 2511423 RCEV NEXT ASSY USED ON PARENTHETICAL INFORMATION FOR REFERENCE ONLY APPROVED APPLICATION SCALE 15:1 SHEET 1 OF 3 INV11-2006a 8 7 6 5 4 3 2 1

8 7 6 5 4 3 DWG NO. 2511423 SH 2 1 2X 0.812 2X 18.700 4X (1.000) D D A3 A2 4X 2.250 1.500 C 1.500 B 4X (2.300) 6 C 6 0.812 18.700 C 7 E1 VIEW B DATUMS A, B, C, AND E SCALE 15 : 1 A1 (FROM SHEET 1) B 1.500 6 9.400 1.500 4.700 C B 6 B VIEW C ENCAPSULANT MAXIMUM X/Y DIMENSIONS SCALE 15 : 1 2X 0 MIN (FROM SHEET 1) 8 A A VIEW D ENCAPSULANT MAXIMUM HEIGHT SCALE 15 : 1 TEXAS DJR. AHWONLM 7/D1A4T/E2010 SDIZE DWG NO 2511423 RCEV INSTRUMENTS Dallas Texas SCALE SHEET 2 OF 3 INV11-2006a 8 7 6 5 4 3 2 1

8 7 6 5 4 3 DWG NO. 2511423 SH 3 1 5.3130.075 (9.855) 4X (0.108) 3 ACTIVE ARRAY 1.2400.050 (0.188) 0.2600.089 D D 2 3.0810.075 (8.640) (6.1614) (6.681) 6.4210.089 WINDOW ACTIVE ARRAY APERTURE 1.500 1.500 F 7.4000.050 B C C C 0.3760.089 10.074±0.089 (10.450) APERTURE 100X TEST PADS CL CL 98X 0.5500.100 X 0.5500.100 00..210000AABC 2.1510.050 11.8500.050 4 (14.001) 24 X 0.75 = 18.000 2X 0.5500.100 WINDOW (0.750) VIEW D F WINDOW AND ACTIVE ARRAY 0.750 APERTURE DIMENSIONS TO CENTER E (FROM SHEET 1) LINE OF ZIGZAG PATTERN 1.500 C C B L 2X 3.075 B D (0.150) TYP. (42°) TYP. 2X 0.930 1.500 C 2X (1.860) 40 35 30 25 20 15 10 5 1 (42°) TYP. 0.4ABC B B A (0.068) TYP. 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C L 1.262 (17.800) DETAIL F APERTURE SHORT EDGES 0.4ABC SCALE 50 : 1 A A VIEW E-E TEST PADS AND CONNECTOR (FROM SHEET 1) TEXAS DJR. AHWONLM 7/D1A4T/E2010 SDIZE DWG NO 2511423 RCEV INSTRUMENTS Dallas Texas SCALE SHEET 3 OF 3 INV11-2006a 8 7 6 5 4 3 2 1

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